OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [tags/] [arelease/] [dbe/] [new_rf_stage.BDE] - Blame information for rev 51

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Line No. Rev Author Line
1 2 mcupro 
SCHM0103
2 
 
3 
HEADER
4 
{
5 
 FREEID 7830
6 
 VARIABLES
7 
 {
8 
  #BLOCKTABLE_FILE="#table.bde"
9 
  #BLOCKTABLE_INCLUDED="1"
10 
  #LANGUAGE="VERILOG"
11 
  #MODULE="rf_stage8"
12 
  AUTHOR="liwei"
13 
  COMPANY="PKU"
14 
  CREATIONDATE="2007-8-4"
15 
  TITLE="No Title"
16 
 }
17 
 SYMBOL "#default" "rd_sel" "rd_sel"
18 
 {
19 
  HEADER
20 
  {
21 
   VARIABLES
22 
   {
23 
    #DESCRIPTION=""
24 
    #LANGUAGE="VERILOG"
25 
    #MODIFIED="1186227267"
26 
   }
27 
  }
28 
  PAGE ""
29 
  {
30 
   PAGEHEADER
31 
   {
32 
    RECT (0,0,340,160)
33 
    FREEID 11
34 
   }
35 
 
36 
   BODY
37 
   {
38 
    RECT  1, -1, 0
39 
    {
40 
     VARIABLES
41 
     {
42 
      #OUTLINE_FILLING="1"
43 
     }
44 
     AREA (20,0,320,160)
45 
    }
46 
    TEXT  3, 0, 0
47 
    {
48 
     TEXT "$#NAME"
49 
     RECT (25,30,115,54)
50 
     ALIGN 4
51 
     MARGINS (1,1)
52 
     PARENT 2
53 
    }
54 
    TEXT  5, 0, 0
55 
    {
56 
     TEXT "$#NAME"
57 
     RECT (214,30,315,54)
58 
     ALIGN 6
59 
     MARGINS (1,1)
60 
     PARENT 4
61 
    }
62 
    TEXT  7, 0, 0
63 
    {
64 
     TEXT "$#NAME"
65 
     RECT (25,70,126,94)
66 
     ALIGN 4
67 
     MARGINS (1,1)
68 
     PARENT 6
69 
    }
70 
    TEXT  9, 0, 0
71 
    {
72 
     TEXT "$#NAME"
73 
     RECT (25,110,126,134)
74 
     ALIGN 4
75 
     MARGINS (1,1)
76 
     PARENT 8
77 
    }
78 
    PIN  2, 0, 0
79 
    {
80 
     COORD (0,40)
81 
     VARIABLES
82 
     {
83 
      #DIRECTION="IN"
84 
      #DOWNTO="1"
85 
      #LENGTH="20"
86 
      #MDA_RECORD_TOKEN="OTHER"
87 
      #NAME="ctl(1:0)"
88 
      #NUMBER="0"
89 
      #VERILOG_TYPE="wire"
90 
     }
91 
     LINE  2, 0, 0
92 
     {
93 
      POINTS ( (0,0), (20,0) )
94 
     }
95 
    }
96 
    PIN  4, 0, 0
97 
    {
98 
     COORD (340,40)
99 
     VARIABLES
100 
     {
101 
      #DIRECTION="OUT"
102 
      #DOWNTO="1"
103 
      #LENGTH="20"
104 
      #MDA_RECORD_TOKEN="OTHER"
105 
      #NAME="rd_o(4:0)"
106 
      #NUMBER="0"
107 
      #VERILOG_TYPE="reg"
108 
     }
109 
     LINE  2, 0, 0
110 
     {
111 
      POINTS ( (-20,0), (0,0) )
112 
     }
113 
    }
114 
    PIN  6, 0, 0
115 
    {
116 
     COORD (0,80)
117 
     VARIABLES
118 
     {
119 
      #DIRECTION="IN"
120 
      #DOWNTO="1"
121 
      #LENGTH="20"
122 
      #MDA_RECORD_TOKEN="OTHER"
123 
      #NAME="rd_i(4:0)"
124 
      #NUMBER="0"
125 
      #VERILOG_TYPE="wire"
126 
     }
127 
     LINE  2, 0, 0
128 
     {
129 
      POINTS ( (0,0), (20,0) )
130 
     }
131 
    }
132 
    PIN  8, 0, 0
133 
    {
134 
     COORD (0,120)
135 
     VARIABLES
136 
     {
137 
      #DIRECTION="IN"
138 
      #DOWNTO="1"
139 
      #LENGTH="20"
140 
      #MDA_RECORD_TOKEN="OTHER"
141 
      #NAME="rt_i(4:0)"
142 
      #NUMBER="0"
143 
      #VERILOG_TYPE="wire"
144 
     }
145 
     LINE  2, 0, 0
146 
     {
147 
      POINTS ( (0,0), (20,0) )
148 
     }
149 
    }
150 
   }
151 
  }
152 
 }
153 
 SYMBOL "#default" "ext" "ext"
154 
 {
155 
  HEADER
156 
  {
157 
   VARIABLES
158 
   {
159 
    #DESCRIPTION=""
160 
    #LANGUAGE="VERILOG"
161 
    #MODIFIED="1186227213"
162 
   }
163 
  }
164 
  PAGE ""
165 
  {
166 
   PAGEHEADER
167 
   {
168 
    RECT (0,0,340,120)
169 
    FREEID 9
170 
   }
171 
 
172 
   BODY
173 
   {
174 
    RECT  1, -1, 0
175 
    {
176 
     VARIABLES
177 
     {
178 
      #OUTLINE_FILLING="1"
179 
     }
180 
     AREA (20,0,320,120)
181 
    }
182 
    TEXT  3, 0, 0
183 
    {
184 
     TEXT "$#NAME"
185 
     RECT (25,30,115,54)
186 
     ALIGN 4
187 
     MARGINS (1,1)
188 
     PARENT 2
189 
    }
190 
    TEXT  5, 0, 0
191 
    {
192 
     TEXT "$#NAME"
193 
     RECT (214,30,315,54)
194 
     ALIGN 6
195 
     MARGINS (1,1)
196 
     PARENT 4
197 
    }
198 
    TEXT  7, 0, 0
199 
    {
200 
     TEXT "$#NAME"
201 
     RECT (25,70,148,94)
202 
     ALIGN 4
203 
     MARGINS (1,1)
204 
     PARENT 6
205 
    }
206 
    PIN  2, 0, 0
207 
    {
208 
     COORD (0,40)
209 
     VARIABLES
210 
     {
211 
      #DIRECTION="IN"
212 
      #DOWNTO="1"
213 
      #LENGTH="20"
214 
      #MDA_RECORD_TOKEN="OTHER"
215 
      #NAME="ctl(2:0)"
216 
      #NUMBER="0"
217 
      #VERILOG_TYPE="wire"
218 
     }
219 
     LINE  2, 0, 0
220 
     {
221 
      POINTS ( (0,0), (20,0) )
222 
     }
223 
    }
224 
    PIN  4, 0, 0
225 
    {
226 
     COORD (340,40)
227 
     VARIABLES
228 
     {
229 
      #DIRECTION="OUT"
230 
      #DOWNTO="1"
231 
      #LENGTH="20"
232 
      #MDA_RECORD_TOKEN="OTHER"
233 
      #NAME="res(31:0)"
234 
      #NUMBER="0"
235 
      #VERILOG_TYPE="reg"
236 
     }
237 
     LINE  2, 0, 0
238 
     {
239 
      POINTS ( (-20,0), (0,0) )
240 
     }
241 
    }
242 
    PIN  6, 0, 0
243 
    {
244 
     COORD (0,80)
245 
     VARIABLES
246 
     {
247 
      #DIRECTION="IN"
248 
      #DOWNTO="1"
249 
      #LENGTH="20"
250 
      #MDA_RECORD_TOKEN="OTHER"
251 
      #NAME="ins_i(31:0)"
252 
      #NUMBER="0"
253 
      #VERILOG_TYPE="wire"
254 
     }
255 
     LINE  2, 0, 0
256 
     {
257 
      POINTS ( (0,0), (20,0) )
258 
     }
259 
    }
260 
   }
261 
  }
262 
 }
263 
 SYMBOL "#default" "jack" "jack"
264 
 {
265 
  HEADER
266 
  {
267 
   VARIABLES
268 
   {
269 
    #DESCRIPTION=""
270 
    #LANGUAGE="VERILOG"
271 
    #MODIFIED="1186228529"
272 
   }
273 
  }
274 
  PAGE ""
275 
  {
276 
   PAGEHEADER
277 
   {
278 
    RECT (0,0,340,160)
279 
    FREEID 11
280 
   }
281 
 
282 
   BODY
283 
   {
284 
    RECT  1, -1, 0
285 
    {
286 
     VARIABLES
287 
     {
288 
      #OUTLINE_FILLING="1"
289 
     }
290 
     AREA (20,0,320,160)
291 
    }
292 
    TEXT  3, 0, 0
293 
    {
294 
     TEXT "$#NAME"
295 
     RECT (25,30,148,54)
296 
     ALIGN 4
297 
     MARGINS (1,1)
298 
     PARENT 2
299 
    }
300 
    TEXT  5, 0, 0
301 
    {
302 
     TEXT "$#NAME"
303 
     RECT (214,30,315,54)
304 
     ALIGN 6
305 
     MARGINS (1,1)
306 
     PARENT 4
307 
    }
308 
    TEXT  7, 0, 0
309 
    {
310 
     TEXT "$#NAME"
311 
     RECT (214,110,315,134)
312 
     ALIGN 6
313 
     MARGINS (1,1)
314 
     PARENT 6
315 
    }
316 
    TEXT  9, 0, 0
317 
    {
318 
     TEXT "$#NAME"
319 
     RECT (214,70,315,94)
320 
     ALIGN 6
321 
     MARGINS (1,1)
322 
     PARENT 8
323 
    }
324 
    PIN  2, 0, 0
325 
    {
326 
     COORD (0,40)
327 
     VARIABLES
328 
     {
329 
      #DIRECTION="IN"
330 
      #DOWNTO="1"
331 
      #LENGTH="20"
332 
      #MDA_RECORD_TOKEN="OTHER"
333 
      #NAME="ins_i(31:0)"
334 
      #NUMBER="0"
335 
      #VERILOG_TYPE="wire"
336 
     }
337 
     LINE  2, 0, 0
338 
     {
339 
      POINTS ( (0,0), (20,0) )
340 
     }
341 
    }
342 
    PIN  4, 0, 0
343 
    {
344 
     COORD (340,40)
345 
     VARIABLES
346 
     {
347 
      #DIRECTION="OUT"
348 
      #DOWNTO="1"
349 
      #LENGTH="20"
350 
      #MDA_RECORD_TOKEN="OTHER"
351 
      #NAME="rd_o(4:0)"
352 
      #NUMBER="0"
353 
      #VERILOG_TYPE="wire"
354 
     }
355 
     LINE  2, 0, 0
356 
     {
357 
      POINTS ( (-20,0), (0,0) )
358 
     }
359 
    }
360 
    PIN  6, 0, 0
361 
    {
362 
     COORD (340,120)
363 
     VARIABLES
364 
     {
365 
      #DIRECTION="OUT"
366 
      #DOWNTO="1"
367 
      #LENGTH="20"
368 
      #MDA_RECORD_TOKEN="OTHER"
369 
      #NAME="rs_o(4:0)"
370 
      #NUMBER="0"
371 
      #SIDE="right"
372 
      #VERILOG_TYPE="wire"
373 
     }
374 
     LINE  2, 0, 0
375 
     {
376 
      POINTS ( (-20,0), (0,0) )
377 
     }
378 
    }
379 
    PIN  8, 0, 0
380 
    {
381 
     COORD (340,80)
382 
     VARIABLES
383 
     {
384 
      #DIRECTION="OUT"
385 
      #DOWNTO="1"
386 
      #LENGTH="20"
387 
      #MDA_RECORD_TOKEN="OTHER"
388 
      #NAME="rt_o(4:0)"
389 
      #NUMBER="0"
390 
      #SIDE="right"
391 
      #VERILOG_TYPE="wire"
392 
     }
393 
     LINE  2, 0, 0
394 
     {
395 
      POINTS ( (-20,0), (0,0) )
396 
     }
397 
    }
398 
   }
399 
  }
400 
 }
401 
 SYMBOL "#default" "r32_reg_clr_cls" "r32_reg_clr_cls"
402 
 {
403 
  HEADER
404 
  {
405 
   VARIABLES
406 
   {
407 
    #DESCRIPTION=""
408 
    #LANGUAGE="VERILOG"
409 
    #MODIFIED="1194388783"
410 
   }
411 
  }
412 
  PAGE ""
413 
  {
414 
   PAGEHEADER
415 
   {
416 
    RECT (0,0,200,200)
417 
    FREEID 12
418 
   }
419 
 
420 
   BODY
421 
   {
422 
    RECT  1, -1, 0
423 
    {
424 
     VARIABLES
425 
     {
426 
      #OUTLINE_FILLING="1"
427 
     }
428 
     AREA (20,0,180,200)
429 
    }
430 
    TEXT  3, 0, 0
431 
    {
432 
     TEXT "$#NAME"
433 
     RECT (25,30,60,54)
434 
     ALIGN 4
435 
     MARGINS (1,1)
436 
     PARENT 2
437 
    }
438 
    TEXT  5, 0, 0
439 
    {
440 
     TEXT "$#NAME"
441 
     RECT (52,30,175,54)
442 
     ALIGN 6
443 
     MARGINS (1,1)
444 
     PARENT 4
445 
    }
446 
    TEXT  7, 0, 0
447 
    {
448 
     TEXT "$#NAME"
449 
     RECT (25,70,60,94)
450 
     ALIGN 4
451 
     MARGINS (1,1)
452 
     PARENT 6
453 
    }
454 
    TEXT  9, 0, 0
455 
    {
456 
     TEXT "$#NAME"
457 
     RECT (25,110,60,134)
458 
     ALIGN 4
459 
     MARGINS (1,1)
460 
     PARENT 8
461 
    }
462 
    TEXT  11, 0, 0
463 
    {
464 
     TEXT "$#NAME"
465 
     RECT (25,150,148,174)
466 
     ALIGN 4
467 
     MARGINS (1,1)
468 
     PARENT 10
469 
    }
470 
    PIN  2, 0, 0
471 
    {
472 
     COORD (0,40)
473 
     VARIABLES
474 
     {
475 
      #DIRECTION="IN"
476 
      #LENGTH="20"
477 
      #MDA_RECORD_TOKEN="OTHER"
478 
      #NAME="clk"
479 
      #NUMBER="0"
480 
      #VERILOG_TYPE="wire"
481 
     }
482 
     LINE  2, 0, 0
483 
     {
484 
      POINTS ( (0,0), (20,0) )
485 
     }
486 
    }
487 
    PIN  4, 0, 0
488 
    {
489 
     COORD (200,40)
490 
     VARIABLES
491 
     {
492 
      #DIRECTION="OUT"
493 
      #DOWNTO="1"
494 
      #LENGTH="20"
495 
      #MDA_RECORD_TOKEN="OTHER"
496 
      #NAME="r32_o(31:0)"
497 
      #NUMBER="0"
498 
      #VERILOG_TYPE="reg"
499 
     }
500 
     LINE  2, 0, 0
501 
     {
502 
      POINTS ( (-20,0), (0,0) )
503 
     }
504 
    }
505 
    PIN  6, 0, 0
506 
    {
507 
     COORD (0,80)
508 
     VARIABLES
509 
     {
510 
      #DIRECTION="IN"
511 
      #LENGTH="20"
512 
      #MDA_RECORD_TOKEN="OTHER"
513 
      #NAME="clr"
514 
      #NUMBER="0"
515 
      #VERILOG_TYPE="wire"
516 
     }
517 
     LINE  2, 0, 0
518 
     {
519 
      POINTS ( (0,0), (20,0) )
520 
     }
521 
    }
522 
    PIN  8, 0, 0
523 
    {
524 
     COORD (0,120)
525 
     VARIABLES
526 
     {
527 
      #DIRECTION="IN"
528 
      #LENGTH="20"
529 
      #MDA_RECORD_TOKEN="OTHER"
530 
      #NAME="cls"
531 
      #NUMBER="0"
532 
      #VERILOG_TYPE="wire"
533 
     }
534 
     LINE  2, 0, 0
535 
     {
536 
      POINTS ( (0,0), (20,0) )
537 
     }
538 
    }
539 
    PIN  10, 0, 0
540 
    {
541 
     COORD (0,160)
542 
     VARIABLES
543 
     {
544 
      #DIRECTION="IN"
545 
      #DOWNTO="1"
546 
      #LENGTH="20"
547 
      #MDA_RECORD_TOKEN="OTHER"
548 
      #NAME="r32_i(31:0)"
549 
      #NUMBER="0"
550 
      #VERILOG_TYPE="wire"
551 
     }
552 
     LINE  2, 0, 0
553 
     {
554 
      POINTS ( (0,0), (20,0) )
555 
     }
556 
    }
557 
   }
558 
  }
559 
 }
560 
 SYMBOL "#default" "fwd_mux" "fwd_mux"
561 
 {
562 
  HEADER
563 
  {
564 
   VARIABLES
565 
   {
566 
    #DESCRIPTION=""
567 
    #LANGUAGE="VERILOG"
568 
    #MODIFIED="1218368893"
569 
   }
570 
  }
571 
  PAGE ""
572 
  {
573 
   PAGEHEADER
574 
   {
575 
    RECT (0,0,240,200)
576 
    FREEID 12
577 
   }
578 
 
579 
   BODY
580 
   {
581 
    RECT  1, -1, 0
582 
    {
583 
     VARIABLES
584 
     {
585 
      #OUTLINE_FILLING="1"
586 
     }
587 
     AREA (20,0,220,200)
588 
    }
589 
    TEXT  3, 0, 0
590 
    {
591 
     TEXT "$#NAME"
592 
     RECT (25,30,126,54)
593 
     ALIGN 4
594 
     MARGINS (1,1)
595 
     PARENT 2
596 
    }
597 
    TEXT  5, 0, 0
598 
    {
599 
     TEXT "$#NAME"
600 
     RECT (103,30,215,54)
601 
     ALIGN 6
602 
     MARGINS (1,1)
603 
     PARENT 4
604 
    }
605 
    TEXT  7, 0, 0
606 
    {
607 
     TEXT "$#NAME"
608 
     RECT (25,70,159,94)
609 
     ALIGN 4
610 
     MARGINS (1,1)
611 
     PARENT 6
612 
    }
613 
    TEXT  9, 0, 0
614 
    {
615 
     TEXT "$#NAME"
616 
     RECT (25,110,148,134)
617 
     ALIGN 4
618 
     MARGINS (1,1)
619 
     PARENT 8
620 
    }
621 
    TEXT  11, 0, 0
622 
    {
623 
     TEXT "$#NAME"
624 
     RECT (25,150,170,174)
625 
     ALIGN 4
626 
     MARGINS (1,1)
627 
     PARENT 10
628 
    }
629 
    PIN  2, 0, 0
630 
    {
631 
     COORD (0,40)
632 
     VARIABLES
633 
     {
634 
      #DIRECTION="IN"
635 
      #DOWNTO="1"
636 
      #LENGTH="20"
637 
      #MDA_RECORD_TOKEN="OTHER"
638 
      #NAME="din(31:0)"
639 
      #NUMBER="0"
640 
      #VERILOG_TYPE="wire"
641 
     }
642 
     LINE  2, 0, 0
643 
     {
644 
      POINTS ( (0,0), (20,0) )
645 
     }
646 
    }
647 
    PIN  4, 0, 0
648 
    {
649 
     COORD (240,40)
650 
     VARIABLES
651 
     {
652 
      #DIRECTION="OUT"
653 
      #DOWNTO="1"
654 
      #LENGTH="20"
655 
      #MDA_RECORD_TOKEN="OTHER"
656 
      #NAME="dout(31:0)"
657 
      #NUMBER="0"
658 
      #VERILOG_TYPE="reg"
659 
     }
660 
     LINE  2, 0, 0
661 
     {
662 
      POINTS ( (-20,0), (0,0) )
663 
     }
664 
    }
665 
    PIN  6, 0, 0
666 
    {
667 
     COORD (0,80)
668 
     VARIABLES
669 
     {
670 
      #DIRECTION="IN"
671 
      #DOWNTO="1"
672 
      #LENGTH="20"
673 
      #MDA_RECORD_TOKEN="OTHER"
674 
      #NAME="fw_alu(31:0)"
675 
      #NUMBER="0"
676 
      #VERILOG_TYPE="wire"
677 
     }
678 
     LINE  2, 0, 0
679 
     {
680 
      POINTS ( (0,0), (20,0) )
681 
     }
682 
    }
683 
    PIN  8, 0, 0
684 
    {
685 
     COORD (0,120)
686 
     VARIABLES
687 
     {
688 
      #DIRECTION="IN"
689 
      #DOWNTO="1"
690 
      #LENGTH="20"
691 
      #MDA_RECORD_TOKEN="OTHER"
692 
      #NAME="fw_ctl(2:0)"
693 
      #NUMBER="0"
694 
      #VERILOG_TYPE="wire"
695 
     }
696 
     LINE  2, 0, 0
697 
     {
698 
      POINTS ( (0,0), (20,0) )
699 
     }
700 
    }
701 
    PIN  10, 0, 0
702 
    {
703 
     COORD (0,160)
704 
     VARIABLES
705 
     {
706 
      #DIRECTION="IN"
707 
      #DOWNTO="1"
708 
      #LENGTH="20"
709 
      #MDA_RECORD_TOKEN="OTHER"
710 
      #NAME="fw_dmem(31:0)"
711 
      #NUMBER="0"
712 
      #VERILOG_TYPE="wire"
713 
     }
714 
     LINE  2, 0, 0
715 
     {
716 
      POINTS ( (0,0), (20,0) )
717 
     }
718 
    }
719 
   }
720 
  }
721 
 }
722 
 SYMBOL "#default" "compare" "compare"
723 
 {
724 
  HEADER
725 
  {
726 
   VARIABLES
727 
   {
728 
    #DESCRIPTION=""
729 
    #LANGUAGE="VERILOG"
730 
    #MODIFIED="1218368824"
731 
   }
732 
  }
733 
  PAGE ""
734 
  {
735 
   PAGEHEADER
736 
   {
737 
    RECT (0,0,160,160)
738 
    FREEID 10
739 
   }
740 
 
741 
   BODY
742 
   {
743 
    RECT  1, -1, 0
744 
    {
745 
     VARIABLES
746 
     {
747 
      #OUTLINE_FILLING="1"
748 
     }
749 
     AREA (20,0,140,160)
750 
    }
751 
    TEXT  3, 0, 0
752 
    {
753 
     TEXT "$#NAME"
754 
     RECT (25,30,115,54)
755 
     ALIGN 4
756 
     MARGINS (1,1)
757 
     PARENT 2
758 
    }
759 
    TEXT  5, 0, 0
760 
    {
761 
     TEXT "$#NAME"
762 
     RECT (100,30,135,54)
763 
     ALIGN 6
764 
     MARGINS (1,1)
765 
     PARENT 4
766 
    }
767 
    TEXT  7, 0, 0
768 
    {
769 
     TEXT "$#NAME"
770 
     RECT (25,70,104,94)
771 
     ALIGN 4
772 
     MARGINS (1,1)
773 
     PARENT 6
774 
    }
775 
    TEXT  9, 0, 0
776 
    {
777 
     TEXT "$#NAME"
778 
     RECT (25,110,104,134)
779 
     ALIGN 4
780 
     MARGINS (1,1)
781 
     PARENT 8
782 
    }
783 
    PIN  2, 0, 0
784 
    {
785 
     COORD (0,40)
786 
     VARIABLES
787 
     {
788 
      #DIRECTION="IN"
789 
      #DOWNTO="1"
790 
      #LENGTH="20"
791 
      #MDA_RECORD_TOKEN="OTHER"
792 
      #NAME="ctl(2:0)"
793 
      #NUMBER="0"
794 
      #VERILOG_TYPE="wire"
795 
     }
796 
     LINE  2, 0, 0
797 
     {
798 
      POINTS ( (0,0), (20,0) )
799 
     }
800 
    }
801 
    PIN  4, 0, 0
802 
    {
803 
     COORD (160,40)
804 
     VARIABLES
805 
     {
806 
      #DIRECTION="OUT"
807 
      #LENGTH="20"
808 
      #MDA_RECORD_TOKEN="OTHER"
809 
      #NAME="res"
810 
      #NUMBER="0"
811 
      #VERILOG_TYPE="reg"
812 
     }
813 
     LINE  2, 0, 0
814 
     {
815 
      POINTS ( (-20,0), (0,0) )
816 
     }
817 
    }
818 
    PIN  6, 0, 0
819 
    {
820 
     COORD (0,80)
821 
     VARIABLES
822 
     {
823 
      #DIRECTION="IN"
824 
      #DOWNTO="1"
825 
      #LENGTH="20"
826 
      #MDA_RECORD_TOKEN="OTHER"
827 
      #NAME="s(31:0)"
828 
      #NUMBER="0"
829 
      #VERILOG_TYPE="wire"
830 
     }
831 
     LINE  2, 0, 0
832 
     {
833 
      POINTS ( (0,0), (20,0) )
834 
     }
835 
    }
836 
    PIN  8, 0, 0
837 
    {
838 
     COORD (0,120)
839 
     VARIABLES
840 
     {
841 
      #DIRECTION="IN"
842 
      #DOWNTO="1"
843 
      #LENGTH="20"
844 
      #MDA_RECORD_TOKEN="OTHER"
845 
      #NAME="t(31:0)"
846 
      #NUMBER="0"
847 
      #VERILOG_TYPE="wire"
848 
     }
849 
     LINE  2, 0, 0
850 
     {
851 
      POINTS ( (0,0), (20,0) )
852 
     }
853 
    }
854 
   }
855 
  }
856 
 }
857 
 SYMBOL "#default" "reg_array2" "reg_array2"
858 
 {
859 
  HEADER
860 
  {
861 
   VARIABLES
862 
   {
863 
    #DESCRIPTION=""
864 
    #LANGUAGE="VERILOG"
865 
    #MODIFIED="1218399944"
866 
   }
867 
  }
868 
  PAGE ""
869 
  {
870 
   PAGEHEADER
871 
   {
872 
    RECT (0,0,240,320)
873 
    FREEID 20
874 
   }
875 
 
876 
   BODY
877 
   {
878 
    RECT  1, -1, 0
879 
    {
880 
     VARIABLES
881 
     {
882 
      #OUTLINE_FILLING="1"
883 
     }
884 
     AREA (20,0,220,320)
885 
    }
886 
    TEXT  3, 0, 0
887 
    {
888 
     TEXT "$#NAME"
889 
     RECT (25,30,82,54)
890 
     ALIGN 4
891 
     MARGINS (1,1)
892 
     PARENT 2
893 
    }
894 
    TEXT  5, 0, 0
895 
    {
896 
     TEXT "$#NAME"
897 
     RECT (125,30,215,54)
898 
     ALIGN 6
899 
     MARGINS (1,1)
900 
     PARENT 4
901 
    }
902 
    TEXT  7, 0, 0
903 
    {
904 
     TEXT "$#NAME"
905 
     RECT (25,70,137,94)
906 
     ALIGN 4
907 
     MARGINS (1,1)
908 
     PARENT 6
909 
    }
910 
    TEXT  9, 0, 0
911 
    {
912 
     TEXT "$#NAME"
913 
     RECT (125,70,215,94)
914 
     ALIGN 6
915 
     MARGINS (1,1)
916 
     PARENT 8
917 
    }
918 
    TEXT  11, 0, 0
919 
    {
920 
     TEXT "$#NAME"
921 
     RECT (25,110,137,134)
922 
     ALIGN 4
923 
     MARGINS (1,1)
924 
     PARENT 10
925 
    }
926 
    TEXT  13, 0, 0
927 
    {
928 
     TEXT "$#NAME"
929 
     RECT (25,150,203,174)
930 
     ALIGN 4
931 
     MARGINS (1,1)
932 
     PARENT 12
933 
    }
934 
    TEXT  15, 0, 0
935 
    {
936 
     TEXT "$#NAME"
937 
     RECT (25,190,203,214)
938 
     ALIGN 4
939 
     MARGINS (1,1)
940 
     PARENT 14
941 
    }
942 
    TEXT  17, 0, 0
943 
    {
944 
     TEXT "$#NAME"
945 
     RECT (25,230,181,254)
946 
     ALIGN 4
947 
     MARGINS (1,1)
948 
     PARENT 16
949 
    }
950 
    TEXT  19, 0, 0
951 
    {
952 
     TEXT "$#NAME"
953 
     RECT (25,270,71,294)
954 
     ALIGN 4
955 
     MARGINS (1,1)
956 
     PARENT 18
957 
    }
958 
    PIN  2, 0, 0
959 
    {
960 
     COORD (0,40)
961 
     VARIABLES
962 
     {
963 
      #DIRECTION="IN"
964 
      #LENGTH="20"
965 
      #MDA_RECORD_TOKEN="OTHER"
966 
      #NAME="clock"
967 
      #NUMBER="0"
968 
      #VERILOG_TYPE="wire"
969 
     }
970 
     LINE  2, 0, 0
971 
     {
972 
      POINTS ( (0,0), (20,0) )
973 
     }
974 
    }
975 
    PIN  4, 0, 0
976 
    {
977 
     COORD (240,40)
978 
     VARIABLES
979 
     {
980 
      #DIRECTION="OUT"
981 
      #DOWNTO="1"
982 
      #LENGTH="20"
983 
      #MDA_RECORD_TOKEN="OTHER"
984 
      #NAME="qa(31:0)"
985 
      #NUMBER="0"
986 
      #VERILOG_TYPE="wire"
987 
     }
988 
     LINE  2, 0, 0
989 
     {
990 
      POINTS ( (-20,0), (0,0) )
991 
     }
992 
    }
993 
    PIN  6, 0, 0
994 
    {
995 
     COORD (0,80)
996 
     VARIABLES
997 
     {
998 
      #DIRECTION="IN"
999 
      #DOWNTO="1"
1000 
      #LENGTH="20"
1001 
      #MDA_RECORD_TOKEN="OTHER"
1002 
      #NAME="data(31:0)"
1003 
      #NUMBER="0"
1004 
      #VERILOG_TYPE="wire"
1005 
     }
1006 
     LINE  2, 0, 0
1007 
     {
1008 
      POINTS ( (0,0), (20,0) )
1009 
     }
1010 
    }
1011 
    PIN  8, 0, 0
1012 
    {
1013 
     COORD (240,80)
1014 
     VARIABLES
1015 
     {
1016 
      #DIRECTION="OUT"
1017 
      #DOWNTO="1"
1018 
      #LENGTH="20"
1019 
      #MDA_RECORD_TOKEN="OTHER"
1020 
      #NAME="qb(31:0)"
1021 
      #NUMBER="0"
1022 
      #VERILOG_TYPE="wire"
1023 
     }
1024 
     LINE  2, 0, 0
1025 
     {
1026 
      POINTS ( (-20,0), (0,0) )
1027 
     }
1028 
    }
1029 
    PIN  10, 0, 0
1030 
    {
1031 
     COORD (0,120)
1032 
     VARIABLES
1033 
     {
1034 
      #DIRECTION="IN"
1035 
      #LENGTH="20"
1036 
      #MDA_RECORD_TOKEN="OTHER"
1037 
      #NAME="rd_clk_cls"
1038 
      #NUMBER="0"
1039 
      #VERILOG_TYPE="wire"
1040 
     }
1041 
     LINE  2, 0, 0
1042 
     {
1043 
      POINTS ( (0,0), (20,0) )
1044 
     }
1045 
    }
1046 
    PIN  12, 0, 0
1047 
    {
1048 
     COORD (0,160)
1049 
     VARIABLES
1050 
     {
1051 
      #DIRECTION="IN"
1052 
      #DOWNTO="1"
1053 
      #LENGTH="20"
1054 
      #MDA_RECORD_TOKEN="OTHER"
1055 
      #NAME="rdaddress_a(4:0)"
1056 
      #NUMBER="0"
1057 
      #VERILOG_TYPE="wire"
1058 
     }
1059 
     LINE  2, 0, 0
1060 
     {
1061 
      POINTS ( (0,0), (20,0) )
1062 
     }
1063 
    }
1064 
    PIN  14, 0, 0
1065 
    {
1066 
     COORD (0,200)
1067 
     VARIABLES
1068 
     {
1069 
      #DIRECTION="IN"
1070 
      #DOWNTO="1"
1071 
      #LENGTH="20"
1072 
      #MDA_RECORD_TOKEN="OTHER"
1073 
      #NAME="rdaddress_b(4:0)"
1074 
      #NUMBER="0"
1075 
      #VERILOG_TYPE="wire"
1076 
     }
1077 
     LINE  2, 0, 0
1078 
     {
1079 
      POINTS ( (0,0), (20,0) )
1080 
     }
1081 
    }
1082 
    PIN  16, 0, 0
1083 
    {
1084 
     COORD (0,240)
1085 
     VARIABLES
1086 
     {
1087 
      #DIRECTION="IN"
1088 
      #DOWNTO="1"
1089 
      #LENGTH="20"
1090 
      #MDA_RECORD_TOKEN="OTHER"
1091 
      #NAME="wraddress(4:0)"
1092 
      #NUMBER="0"
1093 
      #VERILOG_TYPE="wire"
1094 
     }
1095 
     LINE  2, 0, 0
1096 
     {
1097 
      POINTS ( (0,0), (20,0) )
1098 
     }
1099 
    }
1100 
    PIN  18, 0, 0
1101 
    {
1102 
     COORD (0,280)
1103 
     VARIABLES
1104 
     {
1105 
      #DIRECTION="IN"
1106 
      #LENGTH="20"
1107 
      #MDA_RECORD_TOKEN="OTHER"
1108 
      #NAME="wren"
1109 
      #NUMBER="0"
1110 
      #VERILOG_TYPE="wire"
1111 
     }
1112 
     LINE  2, 0, 0
1113 
     {
1114 
      POINTS ( (0,0), (20,0) )
1115 
     }
1116 
    }
1117 
   }
1118 
  }
1119 
 }
1120 
 SYMBOL "#default" "pc_gen2" "pc_gen2"
1121 
 {
1122 
  HEADER
1123 
  {
1124 
   VARIABLES
1125 
   {
1126 
    #DESCRIPTION=""
1127 
    #LANGUAGE="VERILOG"
1128 
    #MODIFIED="1218999367"
1129 
   }
1130 
  }
1131 
  PAGE ""
1132 
  {
1133 
   PAGEHEADER
1134 
   {
1135 
    RECT (-60,0,240,360)
1136 
    FREEID 21
1137 
   }
1138 
 
1139 
   BODY
1140 
   {
1141 
    RECT  1, -1, 0
1142 
    {
1143 
     VARIABLES
1144 
     {
1145 
      #OUTLINE_FILLING="1"
1146 
     }
1147 
     AREA (-40,0,220,360)
1148 
    }
1149 
    TEXT  3, 0, 0
1150 
    {
1151 
     TEXT "$#NAME"
1152 
     RECT (-35,30,22,54)
1153 
     ALIGN 4
1154 
     MARGINS (1,1)
1155 
     PARENT 2
1156 
    }
1157 
    TEXT  5, 0, 0
1158 
    {
1159 
     TEXT "$#NAME"
1160 
     RECT (70,30,215,54)
1161 
     ALIGN 6
1162 
     MARGINS (1,1)
1163 
     PARENT 4
1164 
    }
1165 
    TEXT  7, 0, 0
1166 
    {
1167 
     TEXT "$#NAME"
1168 
     RECT (-35,70,55,94)
1169 
     ALIGN 4
1170 
     MARGINS (1,1)
1171 
     PARENT 6
1172 
    }
1173 
    TEXT  9, 0, 0
1174 
    {
1175 
     TEXT "$#NAME"
1176 
     RECT (-35,110,66,134)
1177 
     ALIGN 4
1178 
     MARGINS (1,1)
1179 
     PARENT 8
1180 
    }
1181 
    TEXT  11, 0, 0
1182 
    {
1183 
     TEXT "$#NAME"
1184 
     RECT (-35,150,66,174)
1185 
     ALIGN 4
1186 
     MARGINS (1,1)
1187 
     PARENT 10
1188 
    }
1189 
    TEXT  13, 0, 0
1190 
    {
1191 
     TEXT "$#NAME"
1192 
     RECT (-35,190,55,214)
1193 
     ALIGN 4
1194 
     MARGINS (1,1)
1195 
     PARENT 12
1196 
    }
1197 
    TEXT  15, 0, 0
1198 
    {
1199 
     TEXT "$#NAME"
1200 
     RECT (-35,230,121,254)
1201 
     ALIGN 4
1202 
     MARGINS (1,1)
1203 
     PARENT 14
1204 
    }
1205 
    TEXT  17, 0, 0
1206 
    {
1207 
     TEXT "$#NAME"
1208 
     RECT (-35,270,44,294)
1209 
     ALIGN 4
1210 
     MARGINS (1,1)
1211 
     PARENT 16
1212 
    }
1213 
    TEXT  19, 0, 0
1214 
    {
1215 
     TEXT "$#NAME"
1216 
     RECT (-35,310,99,334)
1217 
     ALIGN 4
1218 
     MARGINS (1,1)
1219 
     PARENT 18
1220 
    }
1221 
    PIN  2, 0, 0
1222 
    {
1223 
     COORD (-60,40)
1224 
     VARIABLES
1225 
     {
1226 
      #DIRECTION="IN"
1227 
      #LENGTH="20"
1228 
      #MDA_RECORD_TOKEN="OTHER"
1229 
      #NAME="check"
1230 
      #NUMBER="0"
1231 
      #VERILOG_TYPE="wire"
1232 
     }
1233 
     LINE  2, 0, 0
1234 
     {
1235 
      POINTS ( (0,0), (20,0) )
1236 
     }
1237 
    }
1238 
    PIN  4, 0, 0
1239 
    {
1240 
     COORD (240,40)
1241 
     VARIABLES
1242 
     {
1243 
      #DIRECTION="OUT"
1244 
      #DOWNTO="1"
1245 
      #LENGTH="20"
1246 
      #MDA_RECORD_TOKEN="OTHER"
1247 
      #NAME="pc_next(31:0)"
1248 
      #NUMBER="0"
1249 
      #VERILOG_TYPE="reg"
1250 
     }
1251 
     LINE  2, 0, 0
1252 
     {
1253 
      POINTS ( (-20,0), (0,0) )
1254 
     }
1255 
    }
1256 
    PIN  6, 0, 0
1257 
    {
1258 
     COORD (-60,80)
1259 
     VARIABLES
1260 
     {
1261 
      #DIRECTION="IN"
1262 
      #DOWNTO="1"
1263 
      #LENGTH="20"
1264 
      #MDA_RECORD_TOKEN="OTHER"
1265 
      #NAME="ctl(2:0)"
1266 
      #NUMBER="0"
1267 
      #VERILOG_TYPE="wire"
1268 
     }
1269 
     LINE  2, 0, 0
1270 
     {
1271 
      POINTS ( (0,0), (20,0) )
1272 
     }
1273 
    }
1274 
    PIN  8, 0, 0
1275 
    {
1276 
     COORD (-60,120)
1277 
     VARIABLES
1278 
     {
1279 
      #DIRECTION="IN"
1280 
      #DOWNTO="1"
1281 
      #LENGTH="20"
1282 
      #MDA_RECORD_TOKEN="OTHER"
1283 
      #NAME="imm(31:0)"
1284 
      #NUMBER="0"
1285 
      #VERILOG_TYPE="wire"
1286 
     }
1287 
     LINE  2, 0, 0
1288 
     {
1289 
      POINTS ( (0,0), (20,0) )
1290 
     }
1291 
    }
1292 
    PIN  10, 0, 0
1293 
    {
1294 
     COORD (-60,160)
1295 
     VARIABLES
1296 
     {
1297 
      #DIRECTION="IN"
1298 
      #DOWNTO="1"
1299 
      #LENGTH="20"
1300 
      #MDA_RECORD_TOKEN="OTHER"
1301 
      #NAME="irq(31:0)"
1302 
      #NUMBER="0"
1303 
      #VERILOG_TYPE="wire"
1304 
     }
1305 
     LINE  2, 0, 0
1306 
     {
1307 
      POINTS ( (0,0), (20,0) )
1308 
     }
1309 
    }
1310 
    PIN  12, 0, 0
1311 
    {
1312 
     COORD (-60,200)
1313 
     VARIABLES
1314 
     {
1315 
      #DIRECTION="IN"
1316 
      #DOWNTO="1"
1317 
      #LENGTH="20"
1318 
      #MDA_RECORD_TOKEN="OTHER"
1319 
      #NAME="pc(31:0)"
1320 
      #NUMBER="0"
1321 
      #VERILOG_TYPE="wire"
1322 
     }
1323 
     LINE  2, 0, 0
1324 
     {
1325 
      POINTS ( (0,0), (20,0) )
1326 
     }
1327 
    }
1328 
    PIN  14, 0, 0
1329 
    {
1330 
     COORD (-60,240)
1331 
     VARIABLES
1332 
     {
1333 
      #DIRECTION="IN"
1334 
      #DOWNTO="1"
1335 
      #LENGTH="20"
1336 
      #MDA_RECORD_TOKEN="OTHER"
1337 
      #NAME="pc_prectl(3:0)"
1338 
      #NUMBER="0"
1339 
      #VERILOG_TYPE="wire"
1340 
     }
1341 
     LINE  2, 0, 0
1342 
     {
1343 
      POINTS ( (0,0), (20,0) )
1344 
     }
1345 
    }
1346 
    PIN  16, 0, 0
1347 
    {
1348 
     COORD (-60,280)
1349 
     VARIABLES
1350 
     {
1351 
      #DIRECTION="IN"
1352 
      #DOWNTO="1"
1353 
      #LENGTH="20"
1354 
      #MDA_RECORD_TOKEN="OTHER"
1355 
      #NAME="s(31:0)"
1356 
      #NUMBER="0"
1357 
      #VERILOG_TYPE="wire"
1358 
     }
1359 
     LINE  2, 0, 0
1360 
     {
1361 
      POINTS ( (0,0), (20,0) )
1362 
     }
1363 
    }
1364 
    PIN  18, 0, 0
1365 
    {
1366 
     COORD (-60,320)
1367 
     VARIABLES
1368 
     {
1369 
      #DIRECTION="IN"
1370 
      #DOWNTO="1"
1371 
      #LENGTH="20"
1372 
      #MDA_RECORD_TOKEN="OTHER"
1373 
      #NAME="zz_spc(31:0)"
1374 
      #NUMBER="0"
1375 
      #VERILOG_TYPE="wire"
1376 
     }
1377 
     LINE  2, 0, 0
1378 
     {
1379 
      POINTS ( (0,0), (20,0) )
1380 
     }
1381 
    }
1382 
   }
1383 
  }
1384 
 }
1385 
 SYMBOL "#default" "ctl_FSM8" "ctl_FSM8"
1386 
 {
1387 
  HEADER
1388 
  {
1389 
   VARIABLES
1390 
   {
1391 
    #DESCRIPTION=""
1392 
    #GENERIC0="ID_CUR:integer:=1"
1393 
    #GENERIC1="ID_LD:integer:=5"
1394 
    #GENERIC10="ZERO:integer:=0"
1395 
    #GENERIC2="ID_MUL:integer:=2"
1396 
    #GENERIC3="ID_NOI:integer:=6"
1397 
    #GENERIC4="ID_RET:integer:=4"
1398 
    #GENERIC5="ONE:integer:=1"
1399 
    #GENERIC6="PC_IGN:integer:=1"
1400 
    #GENERIC7="PC_IRQ:integer:=4"
1401 
    #GENERIC8="PC_KEP:integer:=2"
1402 
    #GENERIC9="PC_RST:integer:=8"
1403 
    #LANGUAGE="VERILOG"
1404 
    #MODIFIED="1219253769"
1405 
   }
1406 
  }
1407 
  PAGE ""
1408 
  {
1409 
   PAGEHEADER
1410 
   {
1411 
    RECT (0,0,280,360)
1412 
    FREEID 26
1413 
   }
1414 
 
1415 
   BODY
1416 
   {
1417 
    RECT  1, -1, 0
1418 
    {
1419 
     VARIABLES
1420 
     {
1421 
      #OUTLINE_FILLING="1"
1422 
     }
1423 
     AREA (20,0,260,360)
1424 
    }
1425 
    TEXT  3, 0, 0
1426 
    {
1427 
     TEXT "$#NAME"
1428 
     RECT (25,30,60,54)
1429 
     ALIGN 4
1430 
     MARGINS (1,1)
1431 
     PARENT 2
1432 
    }
1433 
    TEXT  5, 0, 0
1434 
    {
1435 
     TEXT "$#NAME"
1436 
     RECT (209,30,255,54)
1437 
     ALIGN 6
1438 
     MARGINS (1,1)
1439 
     PARENT 4
1440 
    }
1441 
    TEXT  7, 0, 0
1442 
    {
1443 
     TEXT "$#NAME"
1444 
     RECT (25,70,148,94)
1445 
     ALIGN 4
1446 
     MARGINS (1,1)
1447 
     PARENT 6
1448 
    }
1449 
    TEXT  9, 0, 0
1450 
    {
1451 
     TEXT "$#NAME"
1452 
     RECT (110,70,255,94)
1453 
     ALIGN 6
1454 
     MARGINS (1,1)
1455 
     PARENT 8
1456 
    }
1457 
    TEXT  11, 0, 0
1458 
    {
1459 
     TEXT "$#NAME"
1460 
     RECT (25,110,60,134)
1461 
     ALIGN 4
1462 
     MARGINS (1,1)
1463 
     PARENT 10
1464 
    }
1465 
    TEXT  13, 0, 0
1466 
    {
1467 
     TEXT "$#NAME"
1468 
     RECT (110,110,255,134)
1469 
     ALIGN 6
1470 
     MARGINS (1,1)
1471 
     PARENT 12
1472 
    }
1473 
    TEXT  15, 0, 0
1474 
    {
1475 
     TEXT "$#NAME"
1476 
     RECT (25,150,60,174)
1477 
     ALIGN 4
1478 
     MARGINS (1,1)
1479 
     PARENT 14
1480 
    }
1481 
    TEXT  17, 0, 0
1482 
    {
1483 
     TEXT "$#NAME"
1484 
     RECT (110,150,255,174)
1485 
     ALIGN 6
1486 
     MARGINS (1,1)
1487 
     PARENT 16
1488 
    }
1489 
    TEXT  19, 0, 0
1490 
    {
1491 
     TEXT "$#NAME"
1492 
     RECT (110,190,255,214)
1493 
     ALIGN 6
1494 
     MARGINS (1,1)
1495 
     PARENT 18
1496 
    }
1497 
    TEXT  21, 0, 0
1498 
    {
1499 
     TEXT "$#NAME"
1500 
     RECT (99,230,255,254)
1501 
     ALIGN 6
1502 
     MARGINS (1,1)
1503 
     PARENT 20
1504 
    }
1505 
    TEXT  23, 0, 0
1506 
    {
1507 
     TEXT "$#NAME"
1508 
     RECT (88,270,255,294)
1509 
     ALIGN 6
1510 
     MARGINS (1,1)
1511 
     PARENT 22
1512 
    }
1513 
    TEXT  25, 0, 0
1514 
    {
1515 
     TEXT "$#NAME"
1516 
     RECT (154,310,255,334)
1517 
     ALIGN 6
1518 
     MARGINS (1,1)
1519 
     PARENT 24
1520 
    }
1521 
    PIN  2, 0, 0
1522 
    {
1523 
     COORD (0,40)
1524 
     VARIABLES
1525 
     {
1526 
      #DIRECTION="IN"
1527 
      #LENGTH="20"
1528 
      #MDA_RECORD_TOKEN="OTHER"
1529 
      #NAME="clk"
1530 
      #NUMBER="0"
1531 
      #VERILOG_TYPE="wire"
1532 
     }
1533 
     LINE  2, 0, 0
1534 
     {
1535 
      POINTS ( (0,0), (20,0) )
1536 
     }
1537 
    }
1538 
    PIN  4, 0, 0
1539 
    {
1540 
     COORD (280,40)
1541 
     VARIABLES
1542 
     {
1543 
      #DIRECTION="OUT"
1544 
      #LENGTH="20"
1545 
      #MDA_RECORD_TOKEN="OTHER"
1546 
      #NAME="iack"
1547 
      #NUMBER="0"
1548 
      #VERILOG_TYPE="reg"
1549 
     }
1550 
     LINE  2, 0, 0
1551 
     {
1552 
      POINTS ( (-20,0), (0,0) )
1553 
     }
1554 
    }
1555 
    PIN  6, 0, 0
1556 
    {
1557 
     COORD (0,80)
1558 
     VARIABLES
1559 
     {
1560 
      #DIRECTION="IN"
1561 
      #DOWNTO="1"
1562 
      #LENGTH="20"
1563 
      #MDA_RECORD_TOKEN="OTHER"
1564 
      #NAME="id_cmd(2:0)"
1565 
      #NUMBER="0"
1566 
      #VERILOG_TYPE="wire"
1567 
     }
1568 
     LINE  2, 0, 0
1569 
     {
1570 
      POINTS ( (0,0), (20,0) )
1571 
     }
1572 
    }
1573 
    PIN  8, 0, 0
1574 
    {
1575 
     COORD (280,80)
1576 
     VARIABLES
1577 
     {
1578 
      #DIRECTION="OUT"
1579 
      #LENGTH="20"
1580 
      #MDA_RECORD_TOKEN="OTHER"
1581 
      #NAME="id2ra_ctl_clr"
1582 
      #NUMBER="0"
1583 
      #VERILOG_TYPE="reg"
1584 
     }
1585 
     LINE  2, 0, 0
1586 
     {
1587 
      POINTS ( (-20,0), (0,0) )
1588 
     }
1589 
    }
1590 
    PIN  10, 0, 0
1591 
    {
1592 
     COORD (0,120)
1593 
     VARIABLES
1594 
     {
1595 
      #DIRECTION="IN"
1596 
      #LENGTH="20"
1597 
      #MDA_RECORD_TOKEN="OTHER"
1598 
      #NAME="irq"
1599 
      #NUMBER="0"
1600 
      #VERILOG_TYPE="wire"
1601 
     }
1602 
     LINE  2, 0, 0
1603 
     {
1604 
      POINTS ( (0,0), (20,0) )
1605 
     }
1606 
    }
1607 
    PIN  12, 0, 0
1608 
    {
1609 
     COORD (280,120)
1610 
     VARIABLES
1611 
     {
1612 
      #DIRECTION="OUT"
1613 
      #LENGTH="20"
1614 
      #MDA_RECORD_TOKEN="OTHER"
1615 
      #NAME="id2ra_ctl_cls"
1616 
      #NUMBER="0"
1617 
      #VERILOG_TYPE="reg"
1618 
     }
1619 
     LINE  2, 0, 0
1620 
     {
1621 
      POINTS ( (-20,0), (0,0) )
1622 
     }
1623 
    }
1624 
    PIN  14, 0, 0
1625 
    {
1626 
     COORD (0,160)
1627 
     VARIABLES
1628 
     {
1629 
      #DIRECTION="IN"
1630 
      #LENGTH="20"
1631 
      #MDA_RECORD_TOKEN="OTHER"
1632 
      #NAME="rst"
1633 
      #NUMBER="0"
1634 
      #VERILOG_TYPE="wire"
1635 
     }
1636 
     LINE  2, 0, 0
1637 
     {
1638 
      POINTS ( (0,0), (20,0) )
1639 
     }
1640 
    }
1641 
    PIN  16, 0, 0
1642 
    {
1643 
     COORD (280,160)
1644 
     VARIABLES
1645 
     {
1646 
      #DIRECTION="OUT"
1647 
      #LENGTH="20"
1648 
      #MDA_RECORD_TOKEN="OTHER"
1649 
      #NAME="id2ra_ins_clr"
1650 
      #NUMBER="0"
1651 
      #VERILOG_TYPE="reg"
1652 
     }
1653 
     LINE  2, 0, 0
1654 
     {
1655 
      POINTS ( (-20,0), (0,0) )
1656 
     }
1657 
    }
1658 
    PIN  18, 0, 0
1659 
    {
1660 
     COORD (280,200)
1661 
     VARIABLES
1662 
     {
1663 
      #DIRECTION="OUT"
1664 
      #LENGTH="20"
1665 
      #MDA_RECORD_TOKEN="OTHER"
1666 
      #NAME="id2ra_ins_cls"
1667 
      #NUMBER="0"
1668 
      #VERILOG_TYPE="reg"
1669 
     }
1670 
     LINE  2, 0, 0
1671 
     {
1672 
      POINTS ( (-20,0), (0,0) )
1673 
     }
1674 
    }
1675 
    PIN  20, 0, 0
1676 
    {
1677 
     COORD (280,240)
1678 
     VARIABLES
1679 
     {
1680 
      #DIRECTION="OUT"
1681 
      #DOWNTO="1"
1682 
      #LENGTH="20"
1683 
      #MDA_RECORD_TOKEN="OTHER"
1684 
      #NAME="pc_prectl(3:0)"
1685 
      #NUMBER="0"
1686 
      #VERILOG_TYPE="reg"
1687 
     }
1688 
     LINE  2, 0, 0
1689 
     {
1690 
      POINTS ( (-20,0), (0,0) )
1691 
     }
1692 
    }
1693 
    PIN  22, 0, 0
1694 
    {
1695 
     COORD (280,280)
1696 
     VARIABLES
1697 
     {
1698 
      #DIRECTION="OUT"
1699 
      #LENGTH="20"
1700 
      #MDA_RECORD_TOKEN="OTHER"
1701 
      #NAME="ra2exec_ctl_clr"
1702 
      #NUMBER="0"
1703 
      #VERILOG_TYPE="reg"
1704 
     }
1705 
     LINE  2, 0, 0
1706 
     {
1707 
      POINTS ( (-20,0), (0,0) )
1708 
     }
1709 
    }
1710 
    PIN  24, 0, 0
1711 
    {
1712 
     COORD (280,320)
1713 
     VARIABLES
1714 
     {
1715 
      #DIRECTION="OUT"
1716 
      #LENGTH="20"
1717 
      #MDA_RECORD_TOKEN="OTHER"
1718 
      #NAME="zz_is_nop"
1719 
      #NUMBER="0"
1720 
      #VERILOG_TYPE="reg"
1721 
     }
1722 
     LINE  2, 0, 0
1723 
     {
1724 
      POINTS ( (-20,0), (0,0) )
1725 
     }
1726 
    }
1727 
   }
1728 
  }
1729 
 }
1730 
 SYMBOL "#default" "cal_cpi" "cal_cpi"
1731 
 {
1732 
  HEADER
1733 
  {
1734 
   VARIABLES
1735 
   {
1736 
    #DESCRIPTION=""
1737 
    #LANGUAGE="VERILOG"
1738 
    #MODIFIED="1219253792"
1739 
   }
1740 
  }
1741 
  PAGE ""
1742 
  {
1743 
   PAGEHEADER
1744 
   {
1745 
    RECT (0,0,260,160)
1746 
    FREEID 12
1747 
   }
1748 
 
1749 
   BODY
1750 
   {
1751 
    RECT  1, -1, 0
1752 
    {
1753 
     VARIABLES
1754 
     {
1755 
      #OUTLINE_FILLING="1"
1756 
     }
1757 
     AREA (20,0,240,160)
1758 
    }
1759 
    TEXT  3, 0, 0
1760 
    {
1761 
     TEXT "$#NAME"
1762 
     RECT (25,30,60,54)
1763 
     ALIGN 4
1764 
     MARGINS (1,1)
1765 
     PARENT 2
1766 
    }
1767 
    TEXT  5, 0, 0
1768 
    {
1769 
     TEXT "$#NAME"
1770 
     RECT (90,30,235,54)
1771 
     ALIGN 6
1772 
     MARGINS (1,1)
1773 
     PARENT 4
1774 
    }
1775 
    TEXT  7, 0, 0
1776 
    {
1777 
     TEXT "$#NAME"
1778 
     RECT (25,70,93,94)
1779 
     ALIGN 4
1780 
     MARGINS (1,1)
1781 
     PARENT 6
1782 
    }
1783 
    TEXT  9, 0, 0
1784 
    {
1785 
     TEXT "$#NAME"
1786 
     RECT (90,70,235,94)
1787 
     ALIGN 6
1788 
     MARGINS (1,1)
1789 
     PARENT 8
1790 
    }
1791 
    TEXT  11, 0, 0
1792 
    {
1793 
     TEXT "$#NAME"
1794 
     RECT (25,110,60,134)
1795 
     ALIGN 4
1796 
     MARGINS (1,1)
1797 
     PARENT 10
1798 
    }
1799 
    PIN  2, 0, 0
1800 
    {
1801 
     COORD (0,40)
1802 
     VARIABLES
1803 
     {
1804 
      #DIRECTION="IN"
1805 
      #LENGTH="20"
1806 
      #MDA_RECORD_TOKEN="OTHER"
1807 
      #NAME="clk"
1808 
      #NUMBER="0"
1809 
      #VERILOG_TYPE="wire"
1810 
     }
1811 
     LINE  2, 0, 0
1812 
     {
1813 
      POINTS ( (0,0), (20,0) )
1814 
     }
1815 
    }
1816 
    PIN  4, 0, 0
1817 
    {
1818 
     COORD (260,40)
1819 
     VARIABLES
1820 
     {
1821 
      #DIRECTION="OUT"
1822 
      #DOWNTO="1"
1823 
      #LENGTH="20"
1824 
      #MDA_RECORD_TOKEN="OTHER"
1825 
      #NAME="clk_no(100:0)"
1826 
      #NUMBER="0"
1827 
      #VERILOG_TYPE="reg"
1828 
     }
1829 
     LINE  2, 0, 0
1830 
     {
1831 
      POINTS ( (-20,0), (0,0) )
1832 
     }
1833 
    }
1834 
    PIN  6, 0, 0
1835 
    {
1836 
     COORD (0,80)
1837 
     VARIABLES
1838 
     {
1839 
      #DIRECTION="IN"
1840 
      #LENGTH="20"
1841 
      #MDA_RECORD_TOKEN="OTHER"
1842 
      #NAME="is_nop"
1843 
      #NUMBER="0"
1844 
      #VERILOG_TYPE="wire"
1845 
     }
1846 
     LINE  2, 0, 0
1847 
     {
1848 
      POINTS ( (0,0), (20,0) )
1849 
     }
1850 
    }
1851 
    PIN  8, 0, 0
1852 
    {
1853 
     COORD (260,80)
1854 
     VARIABLES
1855 
     {
1856 
      #DIRECTION="OUT"
1857 
      #DOWNTO="1"
1858 
      #LENGTH="20"
1859 
      #MDA_RECORD_TOKEN="OTHER"
1860 
      #NAME="ins_no(100:0)"
1861 
      #NUMBER="0"
1862 
      #VERILOG_TYPE="reg"
1863 
     }
1864 
     LINE  2, 0, 0
1865 
     {
1866 
      POINTS ( (-20,0), (0,0) )
1867 
     }
1868 
    }
1869 
    PIN  10, 0, 0
1870 
    {
1871 
     COORD (0,120)
1872 
     VARIABLES
1873 
     {
1874 
      #DIRECTION="IN"
1875 
      #LENGTH="20"
1876 
      #MDA_RECORD_TOKEN="OTHER"
1877 
      #NAME="rst"
1878 
      #NUMBER="0"
1879 
      #VERILOG_TYPE="wire"
1880 
     }
1881 
     LINE  2, 0, 0
1882 
     {
1883 
      POINTS ( (0,0), (20,0) )
1884 
     }
1885 
    }
1886 
   }
1887 
  }
1888 
 }
1889 
}
1890 
 
1891 
PAGE ""
1892 
{
1893 
 PAGEHEADER
1894 
 {
1895 
  PAGESIZE (2338,1653)
1896 
  MARGINS (200,200,200,200)
1897 
  RECT (0,0,100,200)
1898 
 }
1899 
 
1900 
 BODY
1901 
 {
1902 
  INSTANCE  47, 0, 0
1903 
  {
1904 
   VARIABLES
1905 
   {
1906 
    #COMPONENT="rd_sel"
1907 
    #LIBRARY="#default"
1908 
    #REFERENCE="rd_sel"
1909 
    #SYMBOL="rd_sel"
1910 
   }
1911 
   COORD (820,320)
1912 
   VERTEXES ( (2,7022), (6,7024), (8,7029), (4,7048) )
1913 
  }
1914 
  TEXT  48, 0, 0
1915 
  {
1916 
   TEXT "$#REFERENCE"
1917 
   RECT (820,284,924,319)
1918 
   ALIGN 8
1919 
   MARGINS (1,1)
1920 
   PARENT 47
1921 
  }
1922 
  TEXT  52, 0, 0
1923 
  {
1924 
   TEXT "$#COMPONENT"
1925 
   RECT (980,420,1084,455)
1926 
   MARGINS (1,1)
1927 
   PARENT 47
1928 
  }
1929 
  INSTANCE  56, 0, 0
1930 
  {
1931 
   VARIABLES
1932 
   {
1933 
    #COMPONENT="ext"
1934 
    #LIBRARY="#default"
1935 
    #REFERENCE="i_ext"
1936 
    #SYMBOL="ext"
1937 
   }
1938 
   COORD (760,140)
1939 
   VERTEXES ( (2,6998), (6,6997), (4,7020) )
1940 
  }
1941 
  TEXT  57, 0, 0
1942 
  {
1943 
   TEXT "$#REFERENCE"
1944 
   RECT (760,104,847,139)
1945 
   ALIGN 8
1946 
   MARGINS (1,1)
1947 
   PARENT 56
1948 
  }
1949 
  TEXT  61, 0, 0
1950 
  {
1951 
   TEXT "$#COMPONENT"
1952 
   RECT (760,260,813,295)
1953 
   MARGINS (1,1)
1954 
   PARENT 56
1955 
  }
1956 
  INSTANCE  217, 0, 0
1957 
  {
1958 
   VARIABLES
1959 
   {
1960 
    #COMPONENT="Output"
1961 
    #LIBRARY="#terminals"
1962 
    #REFERENCE="id2ra_ctl_cls_o"
1963 
    #SYMBOL="Output"
1964 
   }
1965 
   COORD (2000,260)
1966 
   VERTEXES ( (2,7040) )
1967 
  }
1968 
  TEXT  218, 0, 0
1969 
  {
1970 
   TEXT "$#REFERENCE"
1971 
   RECT (2052,243,2309,278)
1972 
   ALIGN 4
1973 
   MARGINS (1,1)
1974 
   PARENT 217
1975 
  }
1976 
  INSTANCE  232, 0, 0
1977 
  {
1978 
   VARIABLES
1979 
   {
1980 
    #COMPONENT="jack"
1981 
    #LIBRARY="#default"
1982 
    #REFERENCE="jack2"
1983 
    #SYMBOL="jack"
1984 
   }
1985 
   COORD (480,1280)
1986 
   VERTEXES ( (2,7007), (8,7094), (6,7088) )
1987 
  }
1988 
  TEXT  233, 0, 0
1989 
  {
1990 
   TEXT "$#REFERENCE"
1991 
   RECT (500,1245,587,1280)
1992 
   ALIGN 8
1993 
   MARGINS (1,1)
1994 
   PARENT 232
1995 
  }
1996 
  TEXT  237, 0, 0
1997 
  {
1998 
   TEXT "$#COMPONENT"
1999 
   RECT (480,1440,550,1475)
2000 
   MARGINS (1,1)
2001 
   PARENT 232
2002 
  }
2003 
  INSTANCE  304, 0, 0
2004 
  {
2005 
   VARIABLES
2006 
   {
2007 
    #COMPONENT="BusInput"
2008 
    #LIBRARY="#terminals"
2009 
    #REFERENCE="ins_i(31:0)"
2010 
    #SYMBOL="BusInput"
2011 
    #VERILOG_TYPE="wire"
2012 
   }
2013 
   COORD (320,760)
2014 
   VERTEXES ( (2,7008) )
2015 
  }
2016 
  TEXT  305, 0, 0
2017 
  {
2018 
   TEXT "$#REFERENCE"
2019 
   RECT (80,743,269,778)
2020 
   ALIGN 6
2021 
   MARGINS (1,1)
2022 
   PARENT 304
2023 
  }
2024 
  NET BUS  347, 0, 0
2025 
  NET BUS  355, 0, 0
2026 
  INSTANCE  357, 0, 0
2027 
  {
2028 
   VARIABLES
2029 
   {
2030 
    #COMPONENT="BusOutput"
2031 
    #LIBRARY="#terminals"
2032 
    #REFERENCE="rd_index_o(4:0)"
2033 
    #SYMBOL="BusOutput"
2034 
   }
2035 
   COORD (1320,360)
2036 
   VERTEXES ( (2,7049) )
2037 
  }
2038 
  TEXT  358, 0, 0
2039 
  {
2040 
   TEXT "$#REFERENCE"
2041 
   RECT (1372,343,1629,378)
2042 
   ALIGN 4
2043 
   MARGINS (1,1)
2044 
   PARENT 357
2045 
  }
2046 
  INSTANCE  372, 0, 0
2047 
  {
2048 
   VARIABLES
2049 
   {
2050 
    #COMPONENT="BusInput"
2051 
    #LIBRARY="#terminals"
2052 
    #REFERENCE="pc_gen_ctl(2:0)"
2053 
    #SYMBOL="BusInput"
2054 
    #VERILOG_TYPE="wire"
2055 
   }
2056 
   COORD (320,100)
2057 
   VERTEXES ( (2,7520) )
2058 
  }
2059 
  TEXT  373, 0, 0
2060 
  {
2061 
   TEXT "$#REFERENCE"
2062 
   RECT (12,83,269,118)
2063 
   ALIGN 6
2064 
   MARGINS (1,1)
2065 
   PARENT 372
2066 
  }
2067 
  NET BUS  384, 0, 0
2068 
  INSTANCE  402, 0, 0
2069 
  {
2070 
   VARIABLES
2071 
   {
2072 
    #COMPONENT="BusInput"
2073 
    #LIBRARY="#terminals"
2074 
    #REFERENCE="cmp_ctl_i(2:0)"
2075 
    #SYMBOL="BusInput"
2076 
    #VERILOG_TYPE="wire"
2077 
   }
2078 
   COORD (320,880)
2079 
   VERTEXES ( (2,7702) )
2080 
  }
2081 
  TEXT  403, 0, 0
2082 
  {
2083 
   TEXT "$#REFERENCE"
2084 
   RECT (29,863,269,898)
2085 
   ALIGN 6
2086 
   MARGINS (1,1)
2087 
   PARENT 402
2088 
  }
2089 
  INSTANCE  535, 0, 0
2090 
  {
2091 
   VARIABLES
2092 
   {
2093 
    #COMPONENT="BusOutput"
2094 
    #LIBRARY="#terminals"
2095 
    #REFERENCE="rs_n_o(4:0)"
2096 
    #SYMBOL="BusOutput"
2097 
    #VERILOG_TYPE="wire"
2098 
   }
2099 
   COORD (880,540)
2100 
   VERTEXES ( (2,7026) )
2101 
  }
2102 
  TEXT  536, 0, 0
2103 
  {
2104 
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2105 
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   TEXT "$#REFERENCE"
2734 
   RECT (1880,1423,2052,1458)
2735 
   ALIGN 4
2736 
   MARGINS (1,1)
2737 
   PARENT 6134
2738 
  }
2739 
  NET BUS  6228, 0, 0
2740 
  NET BUS  6238, 0, 0
2741 
  INSTANCE  6445, 0, 0
2742 
  {
2743 
   VARIABLES
2744 
   {
2745 
    #COMPONENT="reg_array2"
2746 
    #LIBRARY="#default"
2747 
    #REFERENCE="reg_bank"
2748 
    #SYMBOL="reg_array2"
2749 
   }
2750 
   COORD (500,900)
2751 
   VERTEXES ( (2,7096), (6,7079), (10,7087), (12,7089), (14,7095), (16,7092), (18,7090), (4,7077), (8,7081) )
2752 
  }
2753 
  TEXT  6446, 0, 0
2754 
  {
2755 
   TEXT "$#REFERENCE"
2756 
   RECT (500,864,638,899)
2757 
   ALIGN 8
2758 
   MARGINS (1,1)
2759 
   PARENT 6445
2760 
  }
2761 
  TEXT  6450, 0, 0
2762 
  {
2763 
   TEXT "$#COMPONENT"
2764 
   RECT (500,1220,672,1255)
2765 
   MARGINS (1,1)
2766 
   PARENT 6445
2767 
  }
2768 
  NET WIRE  6609, 0, 0
2769 
  NET WIRE  6658, 0, 0
2770 
  VTX  6996, 0, 0
2771 
  {
2772 
   COORD (340,420)
2773 
  }
2774 
  VTX  6997, 0, 0
2775 
  {
2776 
   COORD (760,220)
2777 
  }
2778 
  VTX  6998, 0, 0
2779 
  {
2780 
   COORD (760,180)
2781 
  }
2782 
  VTX  6999, 0, 0
2783 
  {
2784 
   COORD (320,180)
2785 
  }
2786 
  VTX  7000, 0, 0
2787 
  {
2788 
   COORD (360,420)
2789 
  }
2790 
  VTX  7001, 0, 0
2791 
  {
2792 
   COORD (680,640)
2793 
  }
2794 
  VTX  7002, 0, 0
2795 
  {
2796 
   COORD (320,940)
2797 
  }
2798 
  VTX  7003, 0, 0
2799 
  {
2800 
   COORD (320,640)
2801 
  }
2802 
  VTX  7004, 0, 0
2803 
  {
2804 
   COORD (480,640)
2805 
  }
2806 
  VTX  7005, 0, 0
2807 
  {
2808 
   COORD (400,760)
2809 
  }
2810 
  VTX  7006, 0, 0
2811 
  {
2812 
   COORD (480,760)
2813 
  }
2814 
  VTX  7007, 0, 0
2815 
  {
2816 
   COORD (480,1320)
2817 
  }
2818 
  VTX  7008, 0, 0
2819 
  {
2820 
   COORD (320,760)
2821 
  }
2822 
  VTX  7017, 0, 0
2823 
  {
2824 
   COORD (1200,180)
2825 
  }
2826 
  VTX  7019, 0, 0
2827 
  {
2828 
   COORD (1320,140)
2829 
  }
2830 
  VTX  7020, 0, 0
2831 
  {
2832 
   COORD (1100,180)
2833 
  }
2834 
  VTX  7021, 0, 0
2835 
  {
2836 
   COORD (320,360)
2837 
  }
2838 
  VTX  7022, 0, 0
2839 
  {
2840 
   COORD (820,360)
2841 
  }
2842 
  VTX  7023, 0, 0
2843 
  {
2844 
   COORD (700,420)
2845 
  }
2846 
  VTX  7024, 0, 0
2847 
  {
2848 
   COORD (820,400)
2849 
  }
2850 
  VTX  7025, 0, 0
2851 
  {
2852 
   COORD (700,500)
2853 
  }
2854 
  VTX  7026, 0, 0
2855 
  {
2856 
   COORD (880,540)
2857 
  }
2858 
  VTX  7027, 0, 0
2859 
  {
2860 
   COORD (880,500)
2861 
  }
2862 
  VTX  7028, 0, 0
2863 
  {
2864 
   COORD (800,460)
2865 
  }
2866 
  VTX  7029, 0, 0
2867 
  {
2868 
   COORD (820,440)
2869 
  }
2870 
  VTX  7030, 0, 0
2871 
  {
2872 
   COORD (700,460)
2873 
  }
2874 
  VTX  7031, 0, 0
2875 
  {
2876 
   COORD (1680,180)
2877 
  }
2878 
  VTX  7032, 0, 0
2879 
  {
2880 
   COORD (2000,180)
2881 
  }
2882 
  VTX  7033, 0, 0
2883 
  {
2884 
   COORD (1960,180)
2885 
  }
2886 
  VTX  7034, 0, 0
2887 
  {
2888 
   COORD (1600,220)
2889 
  }
2890 
  VTX  7035, 0, 0
2891 
  {
2892 
   COORD (1680,220)
2893 
  }
2894 
  VTX  7036, 0, 0
2895 
  {
2896 
   COORD (2000,220)
2897 
  }
2898 
  VTX  7037, 0, 0
2899 
  {
2900 
   COORD (1960,220)
2901 
  }
2902 
  VTX  7038, 0, 0
2903 
  {
2904 
   COORD (1600,260)
2905 
  }
2906 
  VTX  7039, 0, 0
2907 
  {
2908 
   COORD (1680,260)
2909 
  }
2910 
  VTX  7040, 0, 0
2911 
  {
2912 
   COORD (2000,260)
2913 
  }
2914 
  VTX  7041, 0, 0
2915 
  {
2916 
   COORD (1960,260)
2917 
  }
2918 
  VTX  7042, 0, 0
2919 
  {
2920 
   COORD (1600,300)
2921 
  }
2922 
  VTX  7043, 0, 0
2923 
  {
2924 
   COORD (1680,300)
2925 
  }
2926 
  VTX  7046, 0, 0
2927 
  {
2928 
   COORD (2000,420)
2929 
  }
2930 
  VTX  7047, 0, 0
2931 
  {
2932 
   COORD (1960,420)
2933 
  }
2934 
  VTX  7048, 0, 0
2935 
  {
2936 
   COORD (1160,360)
2937 
  }
2938 
  VTX  7049, 0, 0
2939 
  {
2940 
   COORD (1320,360)
2941 
  }
2942 
  VTX  7050, 0, 0
2943 
  {
2944 
   COORD (1520,1160)
2945 
  }
2946 
  VTX  7051, 0, 0
2947 
  {
2948 
   COORD (1480,1160)
2949 
  }
2950 
  VTX  7052, 0, 0
2951 
  {
2952 
   COORD (1240,1240)
2953 
  }
2954 
  VTX  7053, 0, 0
2955 
  {
2956 
   COORD (1160,1240)
2957 
  }
2958 
  VTX  7054, 0, 0
2959 
  {
2960 
   COORD (1240,1200)
2961 
  }
2962 
  VTX  7055, 0, 0
2963 
  {
2964 
   COORD (1200,1200)
2965 
  }
2966 
  VTX  7056, 0, 0
2967 
  {
2968 
   COORD (1160,1200)
2969 
  }
2970 
  VTX  7057, 0, 0
2971 
  {
2972 
   COORD (1240,1280)
2973 
  }
2974 
  VTX  7058, 0, 0
2975 
  {
2976 
   COORD (1180,1280)
2977 
  }
2978 
  VTX  7059, 0, 0
2979 
  {
2980 
   COORD (1160,1280)
2981 
  }
2982 
  VTX  7064, 0, 0
2983 
  {
2984 
   COORD (1520,1440)
2985 
  }
2986 
  VTX  7065, 0, 0
2987 
  {
2988 
   COORD (1480,1440)
2989 
  }
2990 
  VTX  7066, 0, 0
2991 
  {
2992 
   COORD (1240,1480)
2993 
  }
2994 
  VTX  7067, 0, 0
2995 
  {
2996 
   COORD (1160,1520)
2997 
  }
2998 
  VTX  7068, 0, 0
2999 
  {
3000 
   COORD (1240,1520)
3001 
  }
3002 
  VTX  7069, 0, 0
3003 
  {
3004 
   COORD (1240,1560)
3005 
  }
3006 
  VTX  7072, 0, 0
3007 
  {
3008 
   COORD (1540,1160)
3009 
  }
3010 
  VTX  7073, 0, 0
3011 
  {
3012 
   COORD (1820,1160)
3013 
  }
3014 
  VTX  7075, 0, 0
3015 
  {
3016 
   COORD (1820,1440)
3017 
  }
3018 
  VTX  7076, 0, 0
3019 
  {
3020 
   COORD (1240,1160)
3021 
  }
3022 
  VTX  7077, 0, 0
3023 
  {
3024 
   COORD (740,940)
3025 
  }
3026 
  VTX  7078, 0, 0
3027 
  {
3028 
   COORD (320,1000)
3029 
  }
3030 
  VTX  7079, 0, 0
3031 
  {
3032 
   COORD (500,980)
3033 
  }
3034 
  VTX  7080, 0, 0
3035 
  {
3036 
   COORD (1240,1440)
3037 
  }
3038 
  VTX  7081, 0, 0
3039 
  {
3040 
   COORD (740,980)
3041 
  }
3042 
  VTX  7082, 0, 0
3043 
  {
3044 
   COORD (480,680)
3045 
  }
3046 
  VTX  7083, 0, 0
3047 
  {
3048 
   COORD (1960,300)
3049 
  }
3050 
  VTX  7084, 0, 0
3051 
  {
3052 
   COORD (1960,340)
3053 
  }
3054 
  VTX  7085, 0, 0
3055 
  {
3056 
   COORD (440,860)
3057 
  }
3058 
  VTX  7086, 0, 0
3059 
  {
3060 
   COORD (480,720)
3061 
  }
3062 
  VTX  7087, 0, 0
3063 
  {
3064 
   COORD (500,1020)
3065 
  }
3066 
  VTX  7088, 0, 0
3067 
  {
3068 
   COORD (820,1400)
3069 
  }
3070 
  VTX  7089, 0, 0
3071 
  {
3072 
   COORD (500,1060)
3073 
  }
3074 
  VTX  7090, 0, 0
3075 
  {
3076 
   COORD (500,1180)
3077 
  }
3078 
  VTX  7091, 0, 0
3079 
  {
3080 
   COORD (320,1180)
3081 
  }
3082 
  VTX  7092, 0, 0
3083 
  {
3084 
   COORD (500,1140)
3085 
  }
3086 
  VTX  7093, 0, 0
3087 
  {
3088 
   COORD (320,1140)
3089 
  }
3090 
  VTX  7094, 0, 0
3091 
  {
3092 
   COORD (820,1360)
3093 
  }
3094 
  VTX  7095, 0, 0
3095 
  {
3096 
   COORD (500,1100)
3097 
  }
3098 
  VTX  7096, 0, 0
3099 
  {
3100 
   COORD (500,940)
3101 
  }
3102 
  VTX  7097, 0, 0
3103 
  {
3104 
   COORD (340,220)
3105 
  }
3106 
  BUS  7098, 0, 0
3107 
  {
3108 
   NET 2085
3109 
   VTX 6996, 7097
3110 
  }
3111 
  BUS  7099, 0, 0
3112 
  {
3113 
   NET 2085
3114 
   VTX 7097, 6997
3115 
  }
3116 
  BUS  7100, 0, 0
3117 
  {
3118 
   NET 662
3119 
   VTX 6998, 6999
3120 
  }
3121 
  BUS  7101, 0, 0
3122 
  {
3123 
   NET 2085
3124 
   VTX 6996, 7000
3125 
  }
3126 
  VTX  7102, 0, 0
3127 
  {
3128 
   COORD (340,560)
3129 
  }
3130 
  BUS  7103, 0, 0
3131 
  {
3132 
   NET 2085
3133 
   VTX 6996, 7102
3134 
  }
3135 
  VTX  7104, 0, 0
3136 
  {
3137 
   COORD (720,560)
3138 
  }
3139 
  BUS  7105, 0, 0
3140 
  {
3141 
   NET 2085
3142 
   VTX 7102, 7104
3143 
  }
3144 
  VTX  7106, 0, 0
3145 
  {
3146 
   COORD (720,640)
3147 
  }
3148 
  BUS  7107, 0, 0
3149 
  {
3150 
   NET 2085
3151 
   VTX 7104, 7106
3152 
  }
3153 
  BUS  7108, 0, 0
3154 
  {
3155 
   NET 2085
3156 
   VTX 7106, 7001
3157 
  }
3158 
  WIRE  7109, 0, 0
3159 
  {
3160 
   NET 7754
3161 
   VTX 7002, 7003
3162 
  }
3163 
  WIRE  7110, 0, 0
3164 
  {
3165 
   NET 7754
3166 
   VTX 7004, 7003
3167 
  }
3168 
  BUS  7111, 0, 0
3169 
  {
3170 
   NET 2030
3171 
   VTX 7005, 7006
3172 
  }
3173 
  VTX  7112, 0, 0
3174 
  {
3175 
   COORD (400,1320)
3176 
  }
3177 
  BUS  7113, 0, 0
3178 
  {
3179 
   NET 2030
3180 
   VTX 7005, 7112
3181 
  }
3182 
  BUS  7114, 0, 0
3183 
  {
3184 
   NET 2030
3185 
   VTX 7112, 7007
3186 
  }
3187 
  BUS  7115, 0, 0
3188 
  {
3189 
   NET 2030
3190 
   VTX 7008, 7005
3191 
  }
3192 
  VTX  7131, 0, 0
3193 
  {
3194 
   COORD (1200,140)
3195 
  }
3196 
  BUS  7132, 0, 0
3197 
  {
3198 
   NET 347
3199 
   VTX 7019, 7131
3200 
  }
3201 
  BUS  7133, 0, 0
3202 
  {
3203 
   NET 347
3204 
   VTX 7131, 7017
3205 
  }
3206 
  BUS  7134, 0, 0
3207 
  {
3208 
   NET 347
3209 
   VTX 7020, 7017
3210 
  }
3211 
  BUS  7135, 0, 0
3212 
  {
3213 
   NET 658
3214 
   VTX 7021, 7022
3215 
  }
3216 
  VTX  7136, 0, 0
3217 
  {
3218 
   COORD (760,420)
3219 
  }
3220 
  BUS  7137, 0, 0
3221 
  {
3222 
   NET 5421
3223 
   VTX 7023, 7136
3224 
  }
3225 
  VTX  7138, 0, 0
3226 
  {
3227 
   COORD (760,400)
3228 
  }
3229 
  BUS  7139, 0, 0
3230 
  {
3231 
   NET 5421
3232 
   VTX 7136, 7138
3233 
  }
3234 
  BUS  7140, 0, 0
3235 
  {
3236 
   NET 5421
3237 
   VTX 7138, 7024
3238 
  }
3239 
  VTX  7141, 0, 0
3240 
  {
3241 
   COORD (740,500)
3242 
  }
3243 
  BUS  7142, 0, 0
3244 
  {
3245 
   NET 5354
3246 
   VTX 7025, 7141
3247 
  }
3248 
  VTX  7143, 0, 0
3249 
  {
3250 
   COORD (740,540)
3251 
  }
3252 
  BUS  7144, 0, 0
3253 
  {
3254 
   NET 5354
3255 
   VTX 7141, 7143
3256 
  }
3257 
  BUS  7145, 0, 0
3258 
  {
3259 
   NET 5354
3260 
   VTX 7143, 7026
3261 
  }
3262 
  VTX  7146, 0, 0
3263 
  {
3264 
   COORD (800,500)
3265 
  }
3266 
  BUS  7147, 0, 0
3267 
  {
3268 
   NET 5429
3269 
   VTX 7027, 7146
3270 
  }
3271 
  BUS  7148, 0, 0
3272 
  {
3273 
   NET 5429
3274 
   VTX 7146, 7028
3275 
  }
3276 
  VTX  7149, 0, 0
3277 
  {
3278 
   COORD (800,440)
3279 
  }
3280 
  BUS  7150, 0, 0
3281 
  {
3282 
   NET 5429
3283 
   VTX 7029, 7149
3284 
  }
3285 
  BUS  7151, 0, 0
3286 
  {
3287 
   NET 5429
3288 
   VTX 7149, 7028
3289 
  }
3290 
  BUS  7152, 0, 0
3291 
  {
3292 
   NET 5429
3293 
   VTX 7030, 7028
3294 
  }
3295 
  VTX  7153, 0, 0
3296 
  {
3297 
   COORD (320,580)
3298 
  }
3299 
  WIRE  7154, 0, 0
3300 
  {
3301 
   NET 7754
3302 
   VTX 7003, 7153
3303 
  }
3304 
  VTX  7155, 0, 0
3305 
  {
3306 
   COORD (1240,580)
3307 
  }
3308 
  WIRE  7156, 0, 0
3309 
  {
3310 
   NET 7754
3311 
   VTX 7153, 7155
3312 
  }
3313 
  VTX  7157, 0, 0
3314 
  {
3315 
   COORD (1240,180)
3316 
  }
3317 
  WIRE  7158, 0, 0
3318 
  {
3319 
   NET 7754
3320 
   VTX 7155, 7157
3321 
  }
3322 
  WIRE  7160, 0, 0
3323 
  {
3324 
   NET 2652
3325 
   VTX 7032, 7033
3326 
  }
3327 
  BUS  7161, 0, 0
3328 
  {
3329 
   NET 1324
3330 
   VTX 7034, 7035
3331 
  }
3332 
  WIRE  7162, 0, 0
3333 
  {
3334 
   NET 2648
3335 
   VTX 7036, 7037
3336 
  }
3337 
  WIRE  7163, 0, 0
3338 
  {
3339 
   NET 1316
3340 
   VTX 7038, 7039
3341 
  }
3342 
  WIRE  7164, 0, 0
3343 
  {
3344 
   NET 2636
3345 
   VTX 7040, 7041
3346 
  }
3347 
  WIRE  7175, 0, 0
3348 
  {
3349 
   NET 2700
3350 
   VTX 7046, 7047
3351 
  }
3352 
  BUS  7176, 0, 0
3353 
  {
3354 
   NET 355
3355 
   VTX 7048, 7049
3356 
  }
3357 
  BUS  7177, 0, 0
3358 
  {
3359 
   NET 6238
3360 
   VTX 7050, 7051
3361 
  }
3362 
  BUS  7178, 0, 0
3363 
  {
3364 
   NET 5995
3365 
   VTX 7052, 7053
3366 
  }
3367 
  BUS  7179, 0, 0
3368 
  {
3369 
   NET 6096
3370 
   VTX 7054, 7055
3371 
  }
3372 
  BUS  7180, 0, 0
3373 
  {
3374 
   NET 6096
3375 
   VTX 7055, 7056
3376 
  }
3377 
  BUS  7181, 0, 0
3378 
  {
3379 
   NET 6093
3380 
   VTX 7057, 7058
3381 
  }
3382 
  BUS  7182, 0, 0
3383 
  {
3384 
   NET 6093
3385 
   VTX 7058, 7059
3386 
  }
3387 
  BUS  7194, 0, 0
3388 
  {
3389 
   NET 5974
3390 
   VTX 7064, 7065
3391 
  }
3392 
  VTX  7195, 0, 0
3393 
  {
3394 
   COORD (1200,1480)
3395 
  }
3396 
  BUS  7196, 0, 0
3397 
  {
3398 
   NET 6096
3399 
   VTX 7055, 7195
3400 
  }
3401 
  BUS  7197, 0, 0
3402 
  {
3403 
   NET 6096
3404 
   VTX 7195, 7066
3405 
  }
3406 
  BUS  7198, 0, 0
3407 
  {
3408 
   NET 6002
3409 
   VTX 7067, 7068
3410 
  }
3411 
  VTX  7199, 0, 0
3412 
  {
3413 
   COORD (1180,1560)
3414 
  }
3415 
  BUS  7200, 0, 0
3416 
  {
3417 
   NET 6093
3418 
   VTX 7058, 7199
3419 
  }
3420 
  BUS  7201, 0, 0
3421 
  {
3422 
   NET 6093
3423 
   VTX 7199, 7069
3424 
  }
3425 
  BUS  7211, 0, 0
3426 
  {
3427 
   NET 6238
3428 
   VTX 7072, 7073
3429 
  }
3430 
  BUS  7219, 0, 0
3431 
  {
3432 
   NET 6238
3433 
   VTX 7072, 7050
3434 
  }
3435 
  BUS  7220, 0, 0
3436 
  {
3437 
   NET 5974
3438 
   VTX 7064, 7075
3439 
  }
3440 
  VTX  7221, 0, 0
3441 
  {
3442 
   COORD (1200,1160)
3443 
  }
3444 
  BUS  7222, 0, 0
3445 
  {
3446 
   NET 6061
3447 
   VTX 7076, 7221
3448 
  }
3449 
  VTX  7223, 0, 0
3450 
  {
3451 
   COORD (1200,960)
3452 
  }
3453 
  BUS  7224, 0, 0
3454 
  {
3455 
   NET 6061
3456 
   VTX 7221, 7223
3457 
  }
3458 
  VTX  7225, 0, 0
3459 
  {
3460 
   COORD (760,960)
3461 
  }
3462 
  BUS  7226, 0, 0
3463 
  {
3464 
   NET 6061
3465 
   VTX 7223, 7225
3466 
  }
3467 
  VTX  7227, 0, 0
3468 
  {
3469 
   COORD (760,940)
3470 
  }
3471 
  BUS  7228, 0, 0
3472 
  {
3473 
   NET 6061
3474 
   VTX 7225, 7227
3475 
  }
3476 
  BUS  7229, 0, 0
3477 
  {
3478 
   NET 6061
3479 
   VTX 7227, 7077
3480 
  }
3481 
  VTX  7230, 0, 0
3482 
  {
3483 
   COORD (480,1000)
3484 
  }
3485 
  BUS  7231, 0, 0
3486 
  {
3487 
   NET 715
3488 
   VTX 7078, 7230
3489 
  }
3490 
  VTX  7232, 0, 0
3491 
  {
3492 
   COORD (480,980)
3493 
  }
3494 
  BUS  7233, 0, 0
3495 
  {
3496 
   NET 715
3497 
   VTX 7230, 7232
3498 
  }
3499 
  BUS  7234, 0, 0
3500 
  {
3501 
   NET 715
3502 
   VTX 7232, 7079
3503 
  }
3504 
  VTX  7235, 0, 0
3505 
  {
3506 
   COORD (1100,1440)
3507 
  }
3508 
  BUS  7236, 0, 0
3509 
  {
3510 
   NET 6095
3511 
   VTX 7080, 7235
3512 
  }
3513 
  VTX  7237, 0, 0
3514 
  {
3515 
   COORD (1100,1000)
3516 
  }
3517 
  BUS  7238, 0, 0
3518 
  {
3519 
   NET 6095
3520 
   VTX 7235, 7237
3521 
  }
3522 
  VTX  7239, 0, 0
3523 
  {
3524 
   COORD (760,1000)
3525 
  }
3526 
  BUS  7240, 0, 0
3527 
  {
3528 
   NET 6095
3529 
   VTX 7237, 7239
3530 
  }
3531 
  VTX  7241, 0, 0
3532 
  {
3533 
   COORD (760,980)
3534 
  }
3535 
  BUS  7242, 0, 0
3536 
  {
3537 
   NET 6095
3538 
   VTX 7239, 7241
3539 
  }
3540 
  BUS  7243, 0, 0
3541 
  {
3542 
   NET 6095
3543 
   VTX 7241, 7081
3544 
  }
3545 
  VTX  7244, 0, 0
3546 
  {
3547 
   COORD (460,680)
3548 
  }
3549 
  WIRE  7245, 0, 0
3550 
  {
3551 
   NET 6609
3552 
   VTX 7082, 7244
3553 
  }
3554 
  VTX  7246, 0, 0
3555 
  {
3556 
   COORD (460,820)
3557 
  }
3558 
  WIRE  7247, 0, 0
3559 
  {
3560 
   NET 6609
3561 
   VTX 7244, 7246
3562 
  }
3563 
  VTX  7248, 0, 0
3564 
  {
3565 
   COORD (1220,820)
3566 
  }
3567 
  WIRE  7249, 0, 0
3568 
  {
3569 
   NET 6609
3570 
   VTX 7246, 7248
3571 
  }
3572 
  VTX  7250, 0, 0
3573 
  {
3574 
   COORD (1220,800)
3575 
  }
3576 
  WIRE  7251, 0, 0
3577 
  {
3578 
   NET 6609
3579 
   VTX 7248, 7250
3580 
  }
3581 
  VTX  7252, 0, 0
3582 
  {
3583 
   COORD (2060,800)
3584 
  }
3585 
  WIRE  7253, 0, 0
3586 
  {
3587 
   NET 6609
3588 
   VTX 7250, 7252
3589 
  }
3590 
  VTX  7254, 0, 0
3591 
  {
3592 
   COORD (2060,300)
3593 
  }
3594 
  WIRE  7255, 0, 0
3595 
  {
3596 
   NET 6609
3597 
   VTX 7252, 7254
3598 
  }
3599 
  WIRE  7256, 0, 0
3600 
  {
3601 
   NET 6609
3602 
   VTX 7254, 7083
3603 
  }
3604 
  VTX  7257, 0, 0
3605 
  {
3606 
   COORD (2080,340)
3607 
  }
3608 
  WIRE  7258, 0, 0
3609 
  {
3610 
   NET 6658
3611 
   VTX 7084, 7257
3612 
  }
3613 
  VTX  7259, 0, 0
3614 
  {
3615 
   COORD (2080,860)
3616 
  }
3617 
  WIRE  7260, 0, 0
3618 
  {
3619 
   NET 6658
3620 
   VTX 7257, 7259
3621 
  }
3622 
  WIRE  7261, 0, 0
3623 
  {
3624 
   NET 6658
3625 
   VTX 7085, 7259
3626 
  }
3627 
  VTX  7262, 0, 0
3628 
  {
3629 
   COORD (440,720)
3630 
  }
3631 
  WIRE  7263, 0, 0
3632 
  {
3633 
   NET 6658
3634 
   VTX 7086, 7262
3635 
  }
3636 
  WIRE  7264, 0, 0
3637 
  {
3638 
   NET 6658
3639 
   VTX 7262, 7085
3640 
  }
3641 
  VTX  7265, 0, 0
3642 
  {
3643 
   COORD (440,1020)
3644 
  }
3645 
  WIRE  7266, 0, 0
3646 
  {
3647 
   NET 6658
3648 
   VTX 7085, 7265
3649 
  }
3650 
  WIRE  7267, 0, 0
3651 
  {
3652 
   NET 6658
3653 
   VTX 7265, 7087
3654 
  }
3655 
  VTX  7268, 0, 0
3656 
  {
3657 
   COORD (840,1400)
3658 
  }
3659 
  BUS  7269, 0, 0
3660 
  {
3661 
   NET 3237
3662 
   VTX 7088, 7268
3663 
  }
3664 
  VTX  7270, 0, 0
3665 
  {
3666 
   COORD (840,1460)
3667 
  }
3668 
  BUS  7271, 0, 0
3669 
  {
3670 
   NET 3237
3671 
   VTX 7268, 7270
3672 
  }
3673 
  VTX  7272, 0, 0
3674 
  {
3675 
   COORD (460,1460)
3676 
  }
3677 
  BUS  7273, 0, 0
3678 
  {
3679 
   NET 3237
3680 
   VTX 7270, 7272
3681 
  }
3682 
  VTX  7274, 0, 0
3683 
  {
3684 
   COORD (460,1060)
3685 
  }
3686 
  BUS  7275, 0, 0
3687 
  {
3688 
   NET 3237
3689 
   VTX 7272, 7274
3690 
  }
3691 
  BUS  7276, 0, 0
3692 
  {
3693 
   NET 3237
3694 
   VTX 7274, 7089
3695 
  }
3696 
  WIRE  7277, 0, 0
3697 
  {
3698 
   NET 739
3699 
   VTX 7090, 7091
3700 
  }
3701 
  BUS  7278, 0, 0
3702 
  {
3703 
   NET 781
3704 
   VTX 7092, 7093
3705 
  }
3706 
  VTX  7279, 0, 0
3707 
  {
3708 
   COORD (860,1360)
3709 
  }
3710 
  BUS  7280, 0, 0
3711 
  {
3712 
   NET 3236
3713 
   VTX 7094, 7279
3714 
  }
3715 
  VTX  7281, 0, 0
3716 
  {
3717 
   COORD (860,1260)
3718 
  }
3719 
  BUS  7282, 0, 0
3720 
  {
3721 
   NET 3236
3722 
   VTX 7279, 7281
3723 
  }
3724 
  VTX  7283, 0, 0
3725 
  {
3726 
   COORD (440,1260)
3727 
  }
3728 
  BUS  7284, 0, 0
3729 
  {
3730 
   NET 3236
3731 
   VTX 7281, 7283
3732 
  }
3733 
  VTX  7285, 0, 0
3734 
  {
3735 
   COORD (440,1100)
3736 
  }
3737 
  BUS  7286, 0, 0
3738 
  {
3739 
   NET 3236
3740 
   VTX 7283, 7285
3741 
  }
3742 
  BUS  7287, 0, 0
3743 
  {
3744 
   NET 3236
3745 
   VTX 7285, 7095
3746 
  }
3747 
  WIRE  7288, 0, 0
3748 
  {
3749 
   NET 7754
3750 
   VTX 7002, 7096
3751 
  }
3752 
  INSTANCE  7394, 0, 0
3753 
  {
3754 
   VARIABLES
3755 
   {
3756 
    #COMPONENT="pc_gen2"
3757 
    #LIBRARY="#default"
3758 
    #REFERENCE="U1"
3759 
    #SYMBOL="pc_gen2"
3760 
   }
3761 
   COORD (1360,440)
3762 
   VERTEXES ( (4,7457), (6,7521), (8,7519), (10,7518), (12,7516), (14,7514), (16,7512), (18,7578), (2,7704) )
3763 
  }
3764 
  TEXT  7395, 0, 0
3765 
  {
3766 
   TEXT "$#REFERENCE"
3767 
   RECT (1300,404,1336,439)
3768 
   ALIGN 8
3769 
   MARGINS (1,1)
3770 
   PARENT 7394
3771 
  }
3772 
  TEXT  7399, 0, 0
3773 
  {
3774 
   TEXT "$#COMPONENT"
3775 
   RECT (1300,800,1421,835)
3776 
   MARGINS (1,1)
3777 
   PARENT 7394
3778 
  }
3779 
  VTX  7456, 0, 0
3780 
  {
3781 
   COORD (1700,640)
3782 
  }
3783 
  VTX  7457, 0, 0
3784 
  {
3785 
   COORD (1600,480)
3786 
  }
3787 
  VTX  7477, 0, 0
3788 
  {
3789 
   COORD (1660,640)
3790 
  }
3791 
  BUS  7478, 0, 0
3792 
  {
3793 
   NET 894
3794 
   VTX 7456, 7477
3795 
  }
3796 
  VTX  7479, 0, 0
3797 
  {
3798 
   COORD (1660,480)
3799 
  }
3800 
  BUS  7480, 0, 0
3801 
  {
3802 
   NET 894
3803 
   VTX 7477, 7479
3804 
  }
3805 
  BUS  7481, 0, 0
3806 
  {
3807 
   NET 894
3808 
   VTX 7479, 7457
3809 
  }
3810 
  VTX  7512, 0, 0
3811 
  {
3812 
   COORD (1300,720)
3813 
  }
3814 
  VTX  7513, 0, 0
3815 
  {
3816 
   COORD (1960,380)
3817 
  }
3818 
  VTX  7514, 0, 0
3819 
  {
3820 
   COORD (1300,680)
3821 
  }
3822 
  VTX  7515, 0, 0
3823 
  {
3824 
   COORD (1180,640)
3825 
  }
3826 
  VTX  7516, 0, 0
3827 
  {
3828 
   COORD (1300,640)
3829 
  }
3830 
  VTX  7517, 0, 0
3831 
  {
3832 
   COORD (1180,600)
3833 
  }
3834 
  VTX  7518, 0, 0
3835 
  {
3836 
   COORD (1300,600)
3837 
  }
3838 
  VTX  7519, 0, 0
3839 
  {
3840 
   COORD (1300,560)
3841 
  }
3842 
  VTX  7520, 0, 0
3843 
  {
3844 
   COORD (320,100)
3845 
  }
3846 
  VTX  7521, 0, 0
3847 
  {
3848 
   COORD (1300,520)
3849 
  }
3850 
  VTX  7524, 0, 0
3851 
  {
3852 
   COORD (1540,960)
3853 
  }
3854 
  BUS  7525, 0, 0
3855 
  {
3856 
   NET 6238
3857 
   VTX 7072, 7524
3858 
  }
3859 
  VTX  7526, 0, 0
3860 
  {
3861 
   COORD (1240,960)
3862 
  }
3863 
  BUS  7527, 0, 0
3864 
  {
3865 
   NET 6238
3866 
   VTX 7524, 7526
3867 
  }
3868 
  VTX  7528, 0, 0
3869 
  {
3870 
   COORD (1240,720)
3871 
  }
3872 
  BUS  7529, 0, 0
3873 
  {
3874 
   NET 6238
3875 
   VTX 7526, 7528
3876 
  }
3877 
  BUS  7530, 0, 0
3878 
  {
3879 
   NET 6238
3880 
   VTX 7528, 7512
3881 
  }
3882 
  VTX  7531, 0, 0
3883 
  {
3884 
   COORD (1980,380)
3885 
  }
3886 
  BUS  7532, 0, 0
3887 
  {
3888 
   NET 1013
3889 
   VTX 7513, 7531
3890 
  }
3891 
  VTX  7533, 0, 0
3892 
  {
3893 
   COORD (1980,500)
3894 
  }
3895 
  BUS  7534, 0, 0
3896 
  {
3897 
   NET 1013
3898 
   VTX 7531, 7533
3899 
  }
3900 
  VTX  7535, 0, 0
3901 
  {
3902 
   COORD (1640,500)
3903 
  }
3904 
  BUS  7536, 0, 0
3905 
  {
3906 
   NET 1013
3907 
   VTX 7533, 7535
3908 
  }
3909 
  VTX  7537, 0, 0
3910 
  {
3911 
   COORD (1640,420)
3912 
  }
3913 
  BUS  7538, 0, 0
3914 
  {
3915 
   NET 1013
3916 
   VTX 7535, 7537
3917 
  }
3918 
  VTX  7539, 0, 0
3919 
  {
3920 
   COORD (1290,420)
3921 
  }
3922 
  BUS  7540, 0, 0
3923 
  {
3924 
   NET 1013
3925 
   VTX 7537, 7539
3926 
  }
3927 
  VTX  7541, 0, 0
3928 
  {
3929 
   COORD (1290,680)
3930 
  }
3931 
  BUS  7542, 0, 0
3932 
  {
3933 
   NET 1013
3934 
   VTX 7539, 7541
3935 
  }
3936 
  BUS  7543, 0, 0
3937 
  {
3938 
   NET 1013
3939 
   VTX 7541, 7514
3940 
  }
3941 
  BUS  7544, 0, 0
3942 
  {
3943 
   NET 1454
3944 
   VTX 7515, 7516
3945 
  }
3946 
  BUS  7545, 0, 0
3947 
  {
3948 
   NET 1450
3949 
   VTX 7517, 7518
3950 
  }
3951 
  VTX  7546, 0, 0
3952 
  {
3953 
   COORD (1200,560)
3954 
  }
3955 
  BUS  7547, 0, 0
3956 
  {
3957 
   NET 347
3958 
   VTX 7017, 7546
3959 
  }
3960 
  BUS  7548, 0, 0
3961 
  {
3962 
   NET 347
3963 
   VTX 7546, 7519
3964 
  }
3965 
  VTX  7549, 0, 0
3966 
  {
3967 
   COORD (1280,100)
3968 
  }
3969 
  BUS  7550, 0, 0
3970 
  {
3971 
   NET 384
3972 
   VTX 7520, 7549
3973 
  }
3974 
  VTX  7551, 0, 0
3975 
  {
3976 
   COORD (1280,520)
3977 
  }
3978 
  BUS  7552, 0, 0
3979 
  {
3980 
   NET 384
3981 
   VTX 7549, 7551
3982 
  }
3983 
  BUS  7553, 0, 0
3984 
  {
3985 
   NET 384
3986 
   VTX 7551, 7521
3987 
  }
3988 
  NET BUS  7565, 0, 0
3989 
  INSTANCE  7573, 0, 0
3990 
  {
3991 
   VARIABLES
3992 
   {
3993 
    #COMPONENT="BusInput"
3994 
    #LIBRARY="#terminals"
3995 
    #REFERENCE="zz_spc_i(31:0)"
3996 
    #SYMBOL="BusInput"
3997 
   }
3998 
   COORD (1700,740)
3999 
   ORIENTATION 2
4000 
   VERTEXES ( (2,7579) )
4001 
  }
4002 
  TEXT  7574, 0, 0
4003 
  {
4004 
   TEXT "$#REFERENCE"
4005 
   RECT (1751,723,1991,758)
4006 
   ALIGN 4
4007 
   MARGINS (1,1)
4008 
   PARENT 7573
4009 
   ORIENTATION 2
4010 
  }
4011 
  VTX  7578, 0, 0
4012 
  {
4013 
   COORD (1300,760)
4014 
  }
4015 
  VTX  7579, 0, 0
4016 
  {
4017 
   COORD (1700,740)
4018 
  }
4019 
  VTX  7580, 0, 0
4020 
  {
4021 
   COORD (1280,760)
4022 
  }
4023 
  BUS  7581, 0, 0
4024 
  {
4025 
   NET 7565
4026 
   VTX 7578, 7580
4027 
  }
4028 
  VTX  7582, 0, 0
4029 
  {
4030 
   COORD (1280,840)
4031 
  }
4032 
  BUS  7583, 0, 0
4033 
  {
4034 
   NET 7565
4035 
   VTX 7580, 7582
4036 
  }
4037 
  VTX  7584, 0, 0
4038 
  {
4039 
   COORD (1680,840)
4040 
  }
4041 
  BUS  7585, 0, 0
4042 
  {
4043 
   NET 7565
4044 
   VTX 7582, 7584
4045 
  }
4046 
  VTX  7586, 0, 0
4047 
  {
4048 
   COORD (1680,740)
4049 
  }
4050 
  BUS  7587, 0, 0
4051 
  {
4052 
   NET 7565
4053 
   VTX 7584, 7586
4054 
  }
4055 
  BUS  7588, 0, 0
4056 
  {
4057 
   NET 7565
4058 
   VTX 7586, 7579
4059 
  }
4060 
  INSTANCE  7645, 0, 0
4061 
  {
4062 
   VARIABLES
4063 
   {
4064 
    #COMPONENT="ctl_FSM8"
4065 
    #LIBRARY="#default"
4066 
    #REFERENCE="RF_STAGE"
4067 
    #SYMBOL="ctl_FSM8"
4068 
   }
4069 
   COORD (1680,140)
4070 
   VERTEXES ( (2,7031), (4,7033), (6,7035), (8,7037), (10,7039), (12,7041), (14,7043), (16,7083), (18,7084), (20,7513), (22,7047), (24,7773) )
4071 
  }
4072 
  TEXT  7646, 0, 0
4073 
  {
4074 
   TEXT "$#REFERENCE"
4075 
   RECT (1680,104,1818,139)
4076 
   ALIGN 8
4077 
   MARGINS (1,1)
4078 
   PARENT 7645
4079 
  }
4080 
  TEXT  7650, 0, 0
4081 
  {
4082 
   TEXT "$#COMPONENT"
4083 
   RECT (1680,500,1818,535)
4084 
   MARGINS (1,1)
4085 
   PARENT 7645
4086 
  }
4087 
  INSTANCE  7655, 0, 0
4088 
  {
4089 
   VARIABLES
4090 
   {
4091 
    #COMPONENT="cal_cpi"
4092 
    #LIBRARY="#default"
4093 
    #REFERENCE="CAL_CPI"
4094 
    #SYMBOL="cal_cpi"
4095 
   }
4096 
   COORD (1860,900)
4097 
   VERTEXES ( (2,7738), (10,7756), (6,7772), (4,7784), (8,7788) )
4098 
  }
4099 
  TEXT  7656, 0, 0
4100 
  {
4101 
   TEXT "$#REFERENCE"
4102 
   RECT (1860,864,1981,899)
4103 
   ALIGN 8
4104 
   MARGINS (1,1)
4105 
   PARENT 7655
4106 
  }
4107 
  TEXT  7660, 0, 0
4108 
  {
4109 
   TEXT "$#COMPONENT"
4110 
   RECT (1860,1060,1981,1095)
4111 
   MARGINS (1,1)
4112 
   PARENT 7655
4113 
  }
4114 
  VTX  7702, 0, 0
4115 
  {
4116 
   COORD (320,880)
4117 
  }
4118 
  VTX  7703, 0, 0
4119 
  {
4120 
   COORD (1600,1240)
4121 
  }
4122 
  VTX  7704, 0, 0
4123 
  {
4124 
   COORD (1300,480)
4125 
  }
4126 
  VTX  7705, 0, 0
4127 
  {
4128 
   COORD (1760,1240)
4129 
  }
4130 
  VTX  7706, 0, 0
4131 
  {
4132 
   COORD (1600,1280)
4133 
  }
4134 
  VTX  7707, 0, 0
4135 
  {
4136 
   COORD (1600,1320)
4137 
  }
4138 
  VTX  7708, 0, 0
4139 
  {
4140 
   COORD (1580,880)
4141 
  }
4142 
  BUS  7709, 0, 0
4143 
  {
4144 
   NET 6228
4145 
   VTX 7702, 7708
4146 
  }
4147 
  VTX  7710, 0, 0
4148 
  {
4149 
   COORD (1580,1240)
4150 
  }
4151 
  BUS  7711, 0, 0
4152 
  {
4153 
   NET 6228
4154 
   VTX 7708, 7710
4155 
  }
4156 
  BUS  7712, 0, 0
4157 
  {
4158 
   NET 6228
4159 
   VTX 7710, 7703
4160 
  }
4161 
  VTX  7713, 0, 0
4162 
  {
4163 
   COORD (1260,480)
4164 
  }
4165 
  WIRE  7714, 0, 0
4166 
  {
4167 
   NET 904
4168 
   VTX 7704, 7713
4169 
  }
4170 
  VTX  7715, 0, 0
4171 
  {
4172 
   COORD (1260,820)
4173 
  }
4174 
  WIRE  7716, 0, 0
4175 
  {
4176 
   NET 904
4177 
   VTX 7713, 7715
4178 
  }
4179 
  VTX  7717, 0, 0
4180 
  {
4181 
   COORD (1780,820)
4182 
  }
4183 
  WIRE  7718, 0, 0
4184 
  {
4185 
   NET 904
4186 
   VTX 7715, 7717
4187 
  }
4188 
  VTX  7719, 0, 0
4189 
  {
4190 
   COORD (1780,1240)
4191 
  }
4192 
  WIRE  7720, 0, 0
4193 
  {
4194 
   NET 904
4195 
   VTX 7717, 7719
4196 
  }
4197 
  WIRE  7721, 0, 0
4198 
  {
4199 
   NET 904
4200 
   VTX 7719, 7705
4201 
  }
4202 
  VTX  7722, 0, 0
4203 
  {
4204 
   COORD (1520,1280)
4205 
  }
4206 
  BUS  7723, 0, 0
4207 
  {
4208 
   NET 6238
4209 
   VTX 7050, 7722
4210 
  }
4211 
  BUS  7724, 0, 0
4212 
  {
4213 
   NET 6238
4214 
   VTX 7722, 7706
4215 
  }
4216 
  VTX  7725, 0, 0
4217 
  {
4218 
   COORD (1520,1340)
4219 
  }
4220 
  BUS  7726, 0, 0
4221 
  {
4222 
   NET 5974
4223 
   VTX 7064, 7725
4224 
  }
4225 
  VTX  7727, 0, 0
4226 
  {
4227 
   COORD (1580,1340)
4228 
  }
4229 
  BUS  7728, 0, 0
4230 
  {
4231 
   NET 5974
4232 
   VTX 7725, 7727
4233 
  }
4234 
  VTX  7729, 0, 0
4235 
  {
4236 
   COORD (1580,1320)
4237 
  }
4238 
  BUS  7730, 0, 0
4239 
  {
4240 
   NET 5974
4241 
   VTX 7727, 7729
4242 
  }
4243 
  BUS  7731, 0, 0
4244 
  {
4245 
   NET 5974
4246 
   VTX 7729, 7707
4247 
  }
4248 
  VTX  7738, 0, 0
4249 
  {
4250 
   COORD (1860,940)
4251 
  }
4252 
  VTX  7739, 0, 0
4253 
  {
4254 
   COORD (1360,180)
4255 
  }
4256 
  WIRE  7740, 0, 0
4257 
  {
4258 
   NET 7754
4259 
   VTX 7157, 7739
4260 
  }
4261 
  WIRE  7741, 0, 0
4262 
  {
4263 
   NET 7754
4264 
   VTX 7739, 7031
4265 
  }
4266 
  VTX  7743, 0, 0
4267 
  {
4268 
   COORD (1800,940)
4269 
  }
4270 
  WIRE  7744, 0, 0
4271 
  {
4272 
   NET 7754
4273 
   VTX 7738, 7743
4274 
  }
4275 
  VTX  7745, 0, 0
4276 
  {
4277 
   COORD (1800,660)
4278 
  }
4279 
  WIRE  7746, 0, 0
4280 
  {
4281 
   NET 7754
4282 
   VTX 7743, 7745
4283 
  }
4284 
  VTX  7747, 0, 0
4285 
  {
4286 
   COORD (1620,660)
4287 
  }
4288 
  WIRE  7748, 0, 0
4289 
  {
4290 
   NET 7754
4291 
   VTX 7745, 7747
4292 
  }
4293 
  VTX  7749, 0, 0
4294 
  {
4295 
   COORD (1620,320)
4296 
  }
4297 
  WIRE  7750, 0, 0
4298 
  {
4299 
   NET 7754
4300 
   VTX 7747, 7749
4301 
  }
4302 
  VTX  7751, 0, 0
4303 
  {
4304 
   COORD (1360,320)
4305 
  }
4306 
  WIRE  7752, 0, 0
4307 
  {
4308 
   NET 7754
4309 
   VTX 7749, 7751
4310 
  }
4311 
  WIRE  7753, 0, 0
4312 
  {
4313 
   NET 7754
4314 
   VTX 7751, 7739
4315 
  }
4316 
  NET WIRE  7754, 0, 0
4317 
  VTX  7755, 0, 0
4318 
  {
4319 
   COORD (1660,300)
4320 
  }
4321 
  VTX  7756, 0, 0
4322 
  {
4323 
   COORD (1860,1020)
4324 
  }
4325 
  WIRE  7757, 0, 0
4326 
  {
4327 
   NET 7771
4328 
   VTX 7042, 7755
4329 
  }
4330 
  WIRE  7758, 0, 0
4331 
  {
4332 
   NET 7771
4333 
   VTX 7755, 7043
4334 
  }
4335 
  VTX  7760, 0, 0
4336 
  {
4337 
   COORD (1660,120)
4338 
  }
4339 
  WIRE  7761, 0, 0
4340 
  {
4341 
   NET 7771
4342 
   VTX 7755, 7760
4343 
  }
4344 
  VTX  7762, 0, 0
4345 
  {
4346 
   COORD (2100,120)
4347 
  }
4348 
  WIRE  7763, 0, 0
4349 
  {
4350 
   NET 7771
4351 
   VTX 7760, 7762
4352 
  }
4353 
  VTX  7764, 0, 0
4354 
  {
4355 
   COORD (2100,880)
4356 
  }
4357 
  WIRE  7765, 0, 0
4358 
  {
4359 
   NET 7771
4360 
   VTX 7762, 7764
4361 
  }
4362 
  VTX  7766, 0, 0
4363 
  {
4364 
   COORD (1850,880)
4365 
  }
4366 
  WIRE  7767, 0, 0
4367 
  {
4368 
   NET 7771
4369 
   VTX 7764, 7766
4370 
  }
4371 
  VTX  7768, 0, 0
4372 
  {
4373 
   COORD (1850,1020)
4374 
  }
4375 
  WIRE  7769, 0, 0
4376 
  {
4377 
   NET 7771
4378 
   VTX 7766, 7768
4379 
  }
4380 
  WIRE  7770, 0, 0
4381 
  {
4382 
   NET 7771
4383 
   VTX 7768, 7756
4384 
  }
4385 
  NET WIRE  7771, 0, 0
4386 
  VTX  7772, 0, 0
4387 
  {
4388 
   COORD (1860,980)
4389 
  }
4390 
  VTX  7773, 0, 0
4391 
  {
4392 
   COORD (1960,460)
4393 
  }
4394 
  NET WIRE  7774, 0, 0
4395 
  VTX  7775, 0, 0
4396 
  {
4397 
   COORD (1840,980)
4398 
  }
4399 
  WIRE  7776, 0, 0
4400 
  {
4401 
   NET 7774
4402 
   VTX 7772, 7775
4403 
  }
4404 
  VTX  7777, 0, 0
4405 
  {
4406 
   COORD (1840,520)
4407 
  }
4408 
  WIRE  7778, 0, 0
4409 
  {
4410 
   NET 7774
4411 
   VTX 7775, 7777
4412 
  }
4413 
  VTX  7779, 0, 0
4414 
  {
4415 
   COORD (2000,520)
4416 
  }
4417 
  WIRE  7780, 0, 0
4418 
  {
4419 
   NET 7774
4420 
   VTX 7777, 7779
4421 
  }
4422 
  VTX  7781, 0, 0
4423 
  {
4424 
   COORD (2000,460)
4425 
  }
4426 
  WIRE  7782, 0, 0
4427 
  {
4428 
   NET 7774
4429 
   VTX 7779, 7781
4430 
  }
4431 
  WIRE  7783, 0, 0
4432 
  {
4433 
   NET 7774
4434 
   VTX 7781, 7773
4435 
  }
4436 
  VTX  7784, 0, 0
4437 
  {
4438 
   COORD (2120,940)
4439 
  }
4440 
  VTX  7785, 0, 0
4441 
  {
4442 
   COORD (2200,940)
4443 
  }
4444 
  BUS  7787, 0, 0
4445 
  {
4446 
   NET 7797
4447 
   VTX 7784, 7785
4448 
   VARIABLES
4449 
   {
4450 
    #NAMED="1"
4451 
   }
4452 
  }
4453 
  VTX  7788, 0, 0
4454 
  {
4455 
   COORD (2120,980)
4456 
  }
4457 
  VTX  7789, 0, 0
4458 
  {
4459 
   COORD (2200,980)
4460 
  }
4461 
  BUS  7791, 0, 0
4462 
  {
4463 
   NET 7792
4464 
   VTX 7788, 7789
4465 
   VARIABLES
4466 
   {
4467 
    #NAMED="1"
4468 
   }
4469 
  }
4470 
  NET BUS  7792, 0, 0
4471 
  {
4472 
   VARIABLES
4473 
   {
4474 
    #MDA_RECORD_TOKEN="OTHER"
4475 
    #NAME="INS_NO"
4476 
    #VERILOG_TYPE="wire"
4477 
   }
4478 
  }
4479 
  TEXT  7793, 0, 0
4480 
  {
4481 
   TEXT "$#NAME"
4482 
   RECT (2117,950,2203,979)
4483 
   ALIGN 9
4484 
   MARGINS (1,1)
4485 
   PARENT 7791
4486 
  }
4487 
  NET BUS  7797, 0, 0
4488 
  {
4489 
   VARIABLES
4490 
   {
4491 
    #MDA_RECORD_TOKEN="OTHER"
4492 
    #NAME="CLK_NO"
4493 
    #VERILOG_TYPE="wire"
4494 
   }
4495 
  }
4496 
  TEXT  7798, 0, 0
4497 
  {
4498 
   TEXT "$#NAME"
4499 
   RECT (2117,910,2203,939)
4500 
   ALIGN 9
4501 
   MARGINS (1,1)
4502 
   PARENT 7787
4503 
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4504 
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4505 
 
4506 
}
4507 
 
4508 
PAGE ""
4509 
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4510 
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4511 
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4512 
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4513 
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4521 
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4522 
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4523 
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4530 
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   TEXT "Created:"
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   RECT (1278,1339,1395,1392)
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4541 
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   RECT (1448,1333,2118,1393)
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4551 
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4552 
   PAGEALIGN 10
4553 
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   RECT (1279,1397,1350,1450)
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4562 
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   TEXT "$TITLE"
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4600 
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4601 
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4602 
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4603 
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4604 
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4751 
 
4752 
}
4753 
 

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