OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [tags/] [arelease/] [dbe/] [pipelinedregs.BDE] - Blame information for rev 53

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Line No. Rev Author Line
1 2 mcupro 
SCHM0103
2 
 
3 
HEADER
4 
{
5 
 FREEID 7902
6 
 VARIABLES
7 
 {
8 
  #BLOCKTABLE_FILE="#table.bde"
9 
  #BLOCKTABLE_INCLUDED="1"
10 
  #LANGUAGE="VERILOG"
11 
  #MODULE="pipelinedregs"
12 
  AUTHOR="liwei",BOTH
13 
  COMPANY="PKU",BOTH
14 
  CREATIONDATE="2007-11-6",BOTH
15 
  TITLE="regqueue",BOTH
16 
 }
17 
 SYMBOL "#default" "wb_we_reg_clr_cls" "wb_we_reg_clr_cls"
18 
 {
19 
  HEADER
20 
  {
21 
   VARIABLES
22 
   {
23 
    #DESCRIPTION=""
24 
    #LANGUAGE="VERILOG"
25 
    #MODIFIED="1194389182"
26 
   }
27 
  }
28 
  PAGE ""
29 
  {
30 
   PAGEHEADER
31 
   {
32 
    RECT (0,0,220,200)
33 
    FREEID 12
34 
   }
35 
 
36 
   BODY
37 
   {
38 
    RECT  1, -1, 0
39 
    {
40 
     VARIABLES
41 
     {
42 
      #OUTLINE_FILLING="1"
43 
     }
44 
     AREA (20,0,200,200)
45 
    }
46 
    TEXT  3, 0, 0
47 
    {
48 
     TEXT "$#NAME"
49 
     RECT (25,30,60,54)
50 
     ALIGN 4
51 
     MARGINS (1,1)
52 
     PARENT 2
53 
    }
54 
    TEXT  5, 0, 0
55 
    {
56 
     TEXT "$#NAME"
57 
     RECT (61,30,195,54)
58 
     ALIGN 6
59 
     MARGINS (1,1)
60 
     PARENT 4
61 
    }
62 
    TEXT  7, 0, 0
63 
    {
64 
     TEXT "$#NAME"
65 
     RECT (25,70,60,94)
66 
     ALIGN 4
67 
     MARGINS (1,1)
68 
     PARENT 6
69 
    }
70 
    TEXT  9, 0, 0
71 
    {
72 
     TEXT "$#NAME"
73 
     RECT (25,110,60,134)
74 
     ALIGN 4
75 
     MARGINS (1,1)
76 
     PARENT 8
77 
    }
78 
    TEXT  11, 0, 0
79 
    {
80 
     TEXT "$#NAME"
81 
     RECT (25,150,159,174)
82 
     ALIGN 4
83 
     MARGINS (1,1)
84 
     PARENT 10
85 
    }
86 
    PIN  2, 0, 0
87 
    {
88 
     COORD (0,40)
89 
     VARIABLES
90 
     {
91 
      #DIRECTION="IN"
92 
      #LENGTH="20"
93 
      #MDA_RECORD_TOKEN="OTHER"
94 
      #NAME="clk"
95 
      #NUMBER="0"
96 
      #VERILOG_TYPE="wire"
97 
     }
98 
     LINE  2, 0, 0
99 
     {
100 
      POINTS ( (0,0), (20,0) )
101 
     }
102 
    }
103 
    PIN  4, 0, 0
104 
    {
105 
     COORD (220,40)
106 
     VARIABLES
107 
     {
108 
      #DIRECTION="OUT"
109 
      #DOWNTO="1"
110 
      #LENGTH="20"
111 
      #MDA_RECORD_TOKEN="OTHER"
112 
      #NAME="wb_we_o(0:0)"
113 
      #NUMBER="0"
114 
      #VERILOG_TYPE="reg"
115 
     }
116 
     LINE  2, 0, 0
117 
     {
118 
      POINTS ( (-20,0), (0,0) )
119 
     }
120 
    }
121 
    PIN  6, 0, 0
122 
    {
123 
     COORD (0,80)
124 
     VARIABLES
125 
     {
126 
      #DIRECTION="IN"
127 
      #LENGTH="20"
128 
      #MDA_RECORD_TOKEN="OTHER"
129 
      #NAME="clr"
130 
      #NUMBER="0"
131 
      #VERILOG_TYPE="wire"
132 
     }
133 
     LINE  2, 0, 0
134 
     {
135 
      POINTS ( (0,0), (20,0) )
136 
     }
137 
    }
138 
    PIN  8, 0, 0
139 
    {
140 
     COORD (0,120)
141 
     VARIABLES
142 
     {
143 
      #DIRECTION="IN"
144 
      #LENGTH="20"
145 
      #MDA_RECORD_TOKEN="OTHER"
146 
      #NAME="cls"
147 
      #NUMBER="0"
148 
      #VERILOG_TYPE="wire"
149 
     }
150 
     LINE  2, 0, 0
151 
     {
152 
      POINTS ( (0,0), (20,0) )
153 
     }
154 
    }
155 
    PIN  10, 0, 0
156 
    {
157 
     COORD (0,160)
158 
     VARIABLES
159 
     {
160 
      #DIRECTION="IN"
161 
      #DOWNTO="1"
162 
      #LENGTH="20"
163 
      #MDA_RECORD_TOKEN="OTHER"
164 
      #NAME="wb_we_i(0:0)"
165 
      #NUMBER="0"
166 
      #VERILOG_TYPE="wire"
167 
     }
168 
     LINE  2, 0, 0
169 
     {
170 
      POINTS ( (0,0), (20,0) )
171 
     }
172 
    }
173 
   }
174 
  }
175 
 }
176 
 SYMBOL "#default" "wb_mux_ctl_reg_clr_cls" "wb_mux_ctl_reg_clr_cls"
177 
 {
178 
  HEADER
179 
  {
180 
   VARIABLES
181 
   {
182 
    #DESCRIPTION=""
183 
    #LANGUAGE="VERILOG"
184 
    #MODIFIED="1194389195"
185 
   }
186 
  }
187 
  PAGE ""
188 
  {
189 
   PAGEHEADER
190 
   {
191 
    RECT (0,0,260,200)
192 
    FREEID 12
193 
   }
194 
 
195 
   BODY
196 
   {
197 
    RECT  1, -1, 0
198 
    {
199 
     VARIABLES
200 
     {
201 
      #OUTLINE_FILLING="1"
202 
     }
203 
     AREA (20,0,240,200)
204 
    }
205 
    TEXT  3, 0, 0
206 
    {
207 
     TEXT "$#NAME"
208 
     RECT (25,30,60,54)
209 
     ALIGN 4
210 
     MARGINS (1,1)
211 
     PARENT 2
212 
    }
213 
    TEXT  5, 0, 0
214 
    {
215 
     TEXT "$#NAME"
216 
     RECT (46,30,235,54)
217 
     ALIGN 6
218 
     MARGINS (1,1)
219 
     PARENT 4
220 
    }
221 
    TEXT  7, 0, 0
222 
    {
223 
     TEXT "$#NAME"
224 
     RECT (25,70,60,94)
225 
     ALIGN 4
226 
     MARGINS (1,1)
227 
     PARENT 6
228 
    }
229 
    TEXT  9, 0, 0
230 
    {
231 
     TEXT "$#NAME"
232 
     RECT (25,110,60,134)
233 
     ALIGN 4
234 
     MARGINS (1,1)
235 
     PARENT 8
236 
    }
237 
    TEXT  11, 0, 0
238 
    {
239 
     TEXT "$#NAME"
240 
     RECT (25,150,214,174)
241 
     ALIGN 4
242 
     MARGINS (1,1)
243 
     PARENT 10
244 
    }
245 
    PIN  2, 0, 0
246 
    {
247 
     COORD (0,40)
248 
     VARIABLES
249 
     {
250 
      #DIRECTION="IN"
251 
      #LENGTH="20"
252 
      #MDA_RECORD_TOKEN="OTHER"
253 
      #NAME="clk"
254 
      #NUMBER="0"
255 
      #VERILOG_TYPE="wire"
256 
     }
257 
     LINE  2, 0, 0
258 
     {
259 
      POINTS ( (0,0), (20,0) )
260 
     }
261 
    }
262 
    PIN  4, 0, 0
263 
    {
264 
     COORD (260,40)
265 
     VARIABLES
266 
     {
267 
      #DIRECTION="OUT"
268 
      #DOWNTO="1"
269 
      #LENGTH="20"
270 
      #MDA_RECORD_TOKEN="OTHER"
271 
      #NAME="wb_mux_ctl_o(0:0)"
272 
      #NUMBER="0"
273 
      #VERILOG_TYPE="reg"
274 
     }
275 
     LINE  2, 0, 0
276 
     {
277 
      POINTS ( (-20,0), (0,0) )
278 
     }
279 
    }
280 
    PIN  6, 0, 0
281 
    {
282 
     COORD (0,80)
283 
     VARIABLES
284 
     {
285 
      #DIRECTION="IN"
286 
      #LENGTH="20"
287 
      #MDA_RECORD_TOKEN="OTHER"
288 
      #NAME="clr"
289 
      #NUMBER="0"
290 
      #VERILOG_TYPE="wire"
291 
     }
292 
     LINE  2, 0, 0
293 
     {
294 
      POINTS ( (0,0), (20,0) )
295 
     }
296 
    }
297 
    PIN  8, 0, 0
298 
    {
299 
     COORD (0,120)
300 
     VARIABLES
301 
     {
302 
      #DIRECTION="IN"
303 
      #LENGTH="20"
304 
      #MDA_RECORD_TOKEN="OTHER"
305 
      #NAME="cls"
306 
      #NUMBER="0"
307 
      #VERILOG_TYPE="wire"
308 
     }
309 
     LINE  2, 0, 0
310 
     {
311 
      POINTS ( (0,0), (20,0) )
312 
     }
313 
    }
314 
    PIN  10, 0, 0
315 
    {
316 
     COORD (0,160)
317 
     VARIABLES
318 
     {
319 
      #DIRECTION="IN"
320 
      #DOWNTO="1"
321 
      #LENGTH="20"
322 
      #MDA_RECORD_TOKEN="OTHER"
323 
      #NAME="wb_mux_ctl_i(0:0)"
324 
      #NUMBER="0"
325 
      #VERILOG_TYPE="wire"
326 
     }
327 
     LINE  2, 0, 0
328 
     {
329 
      POINTS ( (0,0), (20,0) )
330 
     }
331 
    }
332 
   }
333 
  }
334 
 }
335 
 SYMBOL "#default" "dmem_ctl_reg_clr_cls" "dmem_ctl_reg_clr_cls"
336 
 {
337 
  HEADER
338 
  {
339 
   VARIABLES
340 
   {
341 
    #DESCRIPTION=""
342 
    #LANGUAGE="VERILOG"
343 
    #MODIFIED="1194389139"
344 
   }
345 
  }
346 
  PAGE ""
347 
  {
348 
   PAGEHEADER
349 
   {
350 
    RECT (0,0,240,200)
351 
    FREEID 12
352 
   }
353 
 
354 
   BODY
355 
   {
356 
    RECT  1, -1, 0
357 
    {
358 
     VARIABLES
359 
     {
360 
      #OUTLINE_FILLING="1"
361 
     }
362 
     AREA (20,0,220,200)
363 
    }
364 
    TEXT  3, 0, 0
365 
    {
366 
     TEXT "$#NAME"
367 
     RECT (25,30,60,54)
368 
     ALIGN 4
369 
     MARGINS (1,1)
370 
     PARENT 2
371 
    }
372 
    TEXT  5, 0, 0
373 
    {
374 
     TEXT "$#NAME"
375 
     RECT (48,30,215,54)
376 
     ALIGN 6
377 
     MARGINS (1,1)
378 
     PARENT 4
379 
    }
380 
    TEXT  7, 0, 0
381 
    {
382 
     TEXT "$#NAME"
383 
     RECT (25,70,60,94)
384 
     ALIGN 4
385 
     MARGINS (1,1)
386 
     PARENT 6
387 
    }
388 
    TEXT  9, 0, 0
389 
    {
390 
     TEXT "$#NAME"
391 
     RECT (25,110,60,134)
392 
     ALIGN 4
393 
     MARGINS (1,1)
394 
     PARENT 8
395 
    }
396 
    TEXT  11, 0, 0
397 
    {
398 
     TEXT "$#NAME"
399 
     RECT (25,150,192,174)
400 
     ALIGN 4
401 
     MARGINS (1,1)
402 
     PARENT 10
403 
    }
404 
    PIN  2, 0, 0
405 
    {
406 
     COORD (0,40)
407 
     VARIABLES
408 
     {
409 
      #DIRECTION="IN"
410 
      #LENGTH="20"
411 
      #MDA_RECORD_TOKEN="OTHER"
412 
      #NAME="clk"
413 
      #NUMBER="0"
414 
      #VERILOG_TYPE="wire"
415 
     }
416 
     LINE  2, 0, 0
417 
     {
418 
      POINTS ( (0,0), (20,0) )
419 
     }
420 
    }
421 
    PIN  4, 0, 0
422 
    {
423 
     COORD (240,40)
424 
     VARIABLES
425 
     {
426 
      #DIRECTION="OUT"
427 
      #DOWNTO="1"
428 
      #LENGTH="20"
429 
      #MDA_RECORD_TOKEN="OTHER"
430 
      #NAME="dmem_ctl_o(3:0)"
431 
      #NUMBER="0"
432 
      #VERILOG_TYPE="reg"
433 
     }
434 
     LINE  2, 0, 0
435 
     {
436 
      POINTS ( (-20,0), (0,0) )
437 
     }
438 
    }
439 
    PIN  6, 0, 0
440 
    {
441 
     COORD (0,80)
442 
     VARIABLES
443 
     {
444 
      #DIRECTION="IN"
445 
      #LENGTH="20"
446 
      #MDA_RECORD_TOKEN="OTHER"
447 
      #NAME="clr"
448 
      #NUMBER="0"
449 
      #VERILOG_TYPE="wire"
450 
     }
451 
     LINE  2, 0, 0
452 
     {
453 
      POINTS ( (0,0), (20,0) )
454 
     }
455 
    }
456 
    PIN  8, 0, 0
457 
    {
458 
     COORD (0,120)
459 
     VARIABLES
460 
     {
461 
      #DIRECTION="IN"
462 
      #LENGTH="20"
463 
      #MDA_RECORD_TOKEN="OTHER"
464 
      #NAME="cls"
465 
      #NUMBER="0"
466 
      #VERILOG_TYPE="wire"
467 
     }
468 
     LINE  2, 0, 0
469 
     {
470 
      POINTS ( (0,0), (20,0) )
471 
     }
472 
    }
473 
    PIN  10, 0, 0
474 
    {
475 
     COORD (0,160)
476 
     VARIABLES
477 
     {
478 
      #DIRECTION="IN"
479 
      #DOWNTO="1"
480 
      #LENGTH="20"
481 
      #MDA_RECORD_TOKEN="OTHER"
482 
      #NAME="dmem_ctl_i(3:0)"
483 
      #NUMBER="0"
484 
      #VERILOG_TYPE="wire"
485 
     }
486 
     LINE  2, 0, 0
487 
     {
488 
      POINTS ( (0,0), (20,0) )
489 
     }
490 
    }
491 
   }
492 
  }
493 
 }
494 
 SYMBOL "#default" "alu_func_reg_clr_cls" "alu_func_reg_clr_cls"
495 
 {
496 
  HEADER
497 
  {
498 
   VARIABLES
499 
   {
500 
    #DESCRIPTION=""
501 
    #LANGUAGE="VERILOG"
502 
    #MODIFIED="1194389395"
503 
   }
504 
  }
505 
  PAGE ""
506 
  {
507 
   PAGEHEADER
508 
   {
509 
    RECT (0,0,340,200)
510 
    FREEID 12
511 
   }
512 
 
513 
   BODY
514 
   {
515 
    RECT  1, -1, 0
516 
    {
517 
     VARIABLES
518 
     {
519 
      #OUTLINE_FILLING="1"
520 
     }
521 
     AREA (20,0,320,200)
522 
    }
523 
    TEXT  3, 0, 0
524 
    {
525 
     TEXT "$#NAME"
526 
     RECT (25,30,192,54)
527 
     ALIGN 4
528 
     MARGINS (1,1)
529 
     PARENT 2
530 
    }
531 
    TEXT  5, 0, 0
532 
    {
533 
     TEXT "$#NAME"
534 
     RECT (148,30,315,54)
535 
     ALIGN 6
536 
     MARGINS (1,1)
537 
     PARENT 4
538 
    }
539 
    TEXT  7, 0, 0
540 
    {
541 
     TEXT "$#NAME"
542 
     RECT (25,70,60,94)
543 
     ALIGN 4
544 
     MARGINS (1,1)
545 
     PARENT 6
546 
    }
547 
    TEXT  9, 0, 0
548 
    {
549 
     TEXT "$#NAME"
550 
     RECT (25,110,60,134)
551 
     ALIGN 4
552 
     MARGINS (1,1)
553 
     PARENT 8
554 
    }
555 
    TEXT  11, 0, 0
556 
    {
557 
     TEXT "$#NAME"
558 
     RECT (25,150,60,174)
559 
     ALIGN 4
560 
     MARGINS (1,1)
561 
     PARENT 10
562 
    }
563 
    PIN  2, 0, 0
564 
    {
565 
     COORD (0,40)
566 
     VARIABLES
567 
     {
568 
      #DIRECTION="IN"
569 
      #DOWNTO="1"
570 
      #LENGTH="20"
571 
      #MDA_RECORD_TOKEN="OTHER"
572 
      #NAME="alu_func_i(4:0)"
573 
      #NUMBER="0"
574 
      #VERILOG_TYPE="wire"
575 
     }
576 
     LINE  2, 0, 0
577 
     {
578 
      POINTS ( (0,0), (20,0) )
579 
     }
580 
    }
581 
    PIN  4, 0, 0
582 
    {
583 
     COORD (340,40)
584 
     VARIABLES
585 
     {
586 
      #DIRECTION="OUT"
587 
      #DOWNTO="1"
588 
      #LENGTH="20"
589 
      #MDA_RECORD_TOKEN="OTHER"
590 
      #NAME="alu_func_o(4:0)"
591 
      #NUMBER="0"
592 
      #VERILOG_TYPE="reg"
593 
     }
594 
     LINE  2, 0, 0
595 
     {
596 
      POINTS ( (-20,0), (0,0) )
597 
     }
598 
    }
599 
    PIN  6, 0, 0
600 
    {
601 
     COORD (0,80)
602 
     VARIABLES
603 
     {
604 
      #DIRECTION="IN"
605 
      #LENGTH="20"
606 
      #MDA_RECORD_TOKEN="OTHER"
607 
      #NAME="clk"
608 
      #NUMBER="0"
609 
      #VERILOG_TYPE="wire"
610 
     }
611 
     LINE  2, 0, 0
612 
     {
613 
      POINTS ( (0,0), (20,0) )
614 
     }
615 
    }
616 
    PIN  8, 0, 0
617 
    {
618 
     COORD (0,120)
619 
     VARIABLES
620 
     {
621 
      #DIRECTION="IN"
622 
      #LENGTH="20"
623 
      #MDA_RECORD_TOKEN="OTHER"
624 
      #NAME="clr"
625 
      #NUMBER="0"
626 
      #VERILOG_TYPE="wire"
627 
     }
628 
     LINE  2, 0, 0
629 
     {
630 
      POINTS ( (0,0), (20,0) )
631 
     }
632 
    }
633 
    PIN  10, 0, 0
634 
    {
635 
     COORD (0,160)
636 
     VARIABLES
637 
     {
638 
      #DIRECTION="IN"
639 
      #LENGTH="20"
640 
      #MDA_RECORD_TOKEN="OTHER"
641 
      #NAME="cls"
642 
      #NUMBER="0"
643 
      #VERILOG_TYPE="wire"
644 
     }
645 
     LINE  2, 0, 0
646 
     {
647 
      POINTS ( (0,0), (20,0) )
648 
     }
649 
    }
650 
   }
651 
  }
652 
 }
653 
 SYMBOL "#default" "muxb_ctl_reg_clr_cls" "muxb_ctl_reg_clr_cls"
654 
 {
655 
  HEADER
656 
  {
657 
   VARIABLES
658 
   {
659 
    #DESCRIPTION=""
660 
    #LANGUAGE="VERILOG"
661 
    #MODIFIED="1194389423"
662 
   }
663 
  }
664 
  PAGE ""
665 
  {
666 
   PAGEHEADER
667 
   {
668 
    RECT (0,0,240,200)
669 
    FREEID 12
670 
   }
671 
 
672 
   BODY
673 
   {
674 
    RECT  1, -1, 0
675 
    {
676 
     VARIABLES
677 
     {
678 
      #OUTLINE_FILLING="1"
679 
     }
680 
     AREA (20,0,220,200)
681 
    }
682 
    TEXT  3, 0, 0
683 
    {
684 
     TEXT "$#NAME"
685 
     RECT (25,30,60,54)
686 
     ALIGN 4
687 
     MARGINS (1,1)
688 
     PARENT 2
689 
    }
690 
    TEXT  5, 0, 0
691 
    {
692 
     TEXT "$#NAME"
693 
     RECT (48,30,215,54)
694 
     ALIGN 6
695 
     MARGINS (1,1)
696 
     PARENT 4
697 
    }
698 
    TEXT  7, 0, 0
699 
    {
700 
     TEXT "$#NAME"
701 
     RECT (25,70,60,94)
702 
     ALIGN 4
703 
     MARGINS (1,1)
704 
     PARENT 6
705 
    }
706 
    TEXT  9, 0, 0
707 
    {
708 
     TEXT "$#NAME"
709 
     RECT (25,110,60,134)
710 
     ALIGN 4
711 
     MARGINS (1,1)
712 
     PARENT 8
713 
    }
714 
    TEXT  11, 0, 0
715 
    {
716 
     TEXT "$#NAME"
717 
     RECT (25,150,192,174)
718 
     ALIGN 4
719 
     MARGINS (1,1)
720 
     PARENT 10
721 
    }
722 
    PIN  2, 0, 0
723 
    {
724 
     COORD (0,40)
725 
     VARIABLES
726 
     {
727 
      #DIRECTION="IN"
728 
      #LENGTH="20"
729 
      #MDA_RECORD_TOKEN="OTHER"
730 
      #NAME="clk"
731 
      #NUMBER="0"
732 
      #VERILOG_TYPE="wire"
733 
     }
734 
     LINE  2, 0, 0
735 
     {
736 
      POINTS ( (0,0), (20,0) )
737 
     }
738 
    }
739 
    PIN  4, 0, 0
740 
    {
741 
     COORD (240,40)
742 
     VARIABLES
743 
     {
744 
      #DIRECTION="OUT"
745 
      #DOWNTO="1"
746 
      #LENGTH="20"
747 
      #MDA_RECORD_TOKEN="OTHER"
748 
      #NAME="muxb_ctl_o(1:0)"
749 
      #NUMBER="0"
750 
      #VERILOG_TYPE="reg"
751 
     }
752 
     LINE  2, 0, 0
753 
     {
754 
      POINTS ( (-20,0), (0,0) )
755 
     }
756 
    }
757 
    PIN  6, 0, 0
758 
    {
759 
     COORD (0,80)
760 
     VARIABLES
761 
     {
762 
      #DIRECTION="IN"
763 
      #LENGTH="20"
764 
      #MDA_RECORD_TOKEN="OTHER"
765 
      #NAME="clr"
766 
      #NUMBER="0"
767 
      #VERILOG_TYPE="wire"
768 
     }
769 
     LINE  2, 0, 0
770 
     {
771 
      POINTS ( (0,0), (20,0) )
772 
     }
773 
    }
774 
    PIN  8, 0, 0
775 
    {
776 
     COORD (0,120)
777 
     VARIABLES
778 
     {
779 
      #DIRECTION="IN"
780 
      #LENGTH="20"
781 
      #MDA_RECORD_TOKEN="OTHER"
782 
      #NAME="cls"
783 
      #NUMBER="0"
784 
      #VERILOG_TYPE="wire"
785 
     }
786 
     LINE  2, 0, 0
787 
     {
788 
      POINTS ( (0,0), (20,0) )
789 
     }
790 
    }
791 
    PIN  10, 0, 0
792 
    {
793 
     COORD (0,160)
794 
     VARIABLES
795 
     {
796 
      #DIRECTION="IN"
797 
      #DOWNTO="1"
798 
      #LENGTH="20"
799 
      #MDA_RECORD_TOKEN="OTHER"
800 
      #NAME="muxb_ctl_i(1:0)"
801 
      #NUMBER="0"
802 
      #VERILOG_TYPE="wire"
803 
     }
804 
     LINE  2, 0, 0
805 
     {
806 
      POINTS ( (0,0), (20,0) )
807 
     }
808 
    }
809 
   }
810 
  }
811 
 }
812 
 SYMBOL "#default" "muxa_ctl_reg_clr_cls" "muxa_ctl_reg_clr_cls"
813 
 {
814 
  HEADER
815 
  {
816 
   VARIABLES
817 
   {
818 
    #DESCRIPTION=""
819 
    #LANGUAGE="VERILOG"
820 
    #MODIFIED="1194389441"
821 
   }
822 
  }
823 
  PAGE ""
824 
  {
825 
   PAGEHEADER
826 
   {
827 
    RECT (0,0,240,200)
828 
    FREEID 12
829 
   }
830 
 
831 
   BODY
832 
   {
833 
    RECT  1, -1, 0
834 
    {
835 
     VARIABLES
836 
     {
837 
      #OUTLINE_FILLING="1"
838 
     }
839 
     AREA (20,0,220,200)
840 
    }
841 
    TEXT  3, 0, 0
842 
    {
843 
     TEXT "$#NAME"
844 
     RECT (25,30,60,54)
845 
     ALIGN 4
846 
     MARGINS (1,1)
847 
     PARENT 2
848 
    }
849 
    TEXT  5, 0, 0
850 
    {
851 
     TEXT "$#NAME"
852 
     RECT (48,30,215,54)
853 
     ALIGN 6
854 
     MARGINS (1,1)
855 
     PARENT 4
856 
    }
857 
    TEXT  7, 0, 0
858 
    {
859 
     TEXT "$#NAME"
860 
     RECT (25,70,60,94)
861 
     ALIGN 4
862 
     MARGINS (1,1)
863 
     PARENT 6
864 
    }
865 
    TEXT  9, 0, 0
866 
    {
867 
     TEXT "$#NAME"
868 
     RECT (25,110,60,134)
869 
     ALIGN 4
870 
     MARGINS (1,1)
871 
     PARENT 8
872 
    }
873 
    TEXT  11, 0, 0
874 
    {
875 
     TEXT "$#NAME"
876 
     RECT (25,150,192,174)
877 
     ALIGN 4
878 
     MARGINS (1,1)
879 
     PARENT 10
880 
    }
881 
    PIN  2, 0, 0
882 
    {
883 
     COORD (0,40)
884 
     VARIABLES
885 
     {
886 
      #DIRECTION="IN"
887 
      #LENGTH="20"
888 
      #MDA_RECORD_TOKEN="OTHER"
889 
      #NAME="clk"
890 
      #NUMBER="0"
891 
      #VERILOG_TYPE="wire"
892 
     }
893 
     LINE  2, 0, 0
894 
     {
895 
      POINTS ( (0,0), (20,0) )
896 
     }
897 
    }
898 
    PIN  4, 0, 0
899 
    {
900 
     COORD (240,40)
901 
     VARIABLES
902 
     {
903 
      #DIRECTION="OUT"
904 
      #DOWNTO="1"
905 
      #LENGTH="20"
906 
      #MDA_RECORD_TOKEN="OTHER"
907 
      #NAME="muxa_ctl_o(1:0)"
908 
      #NUMBER="0"
909 
      #VERILOG_TYPE="reg"
910 
     }
911 
     LINE  2, 0, 0
912 
     {
913 
      POINTS ( (-20,0), (0,0) )
914 
     }
915 
    }
916 
    PIN  6, 0, 0
917 
    {
918 
     COORD (0,80)
919 
     VARIABLES
920 
     {
921 
      #DIRECTION="IN"
922 
      #LENGTH="20"
923 
      #MDA_RECORD_TOKEN="OTHER"
924 
      #NAME="clr"
925 
      #NUMBER="0"
926 
      #VERILOG_TYPE="wire"
927 
     }
928 
     LINE  2, 0, 0
929 
     {
930 
      POINTS ( (0,0), (20,0) )
931 
     }
932 
    }
933 
    PIN  8, 0, 0
934 
    {
935 
     COORD (0,120)
936 
     VARIABLES
937 
     {
938 
      #DIRECTION="IN"
939 
      #LENGTH="20"
940 
      #MDA_RECORD_TOKEN="OTHER"
941 
      #NAME="cls"
942 
      #NUMBER="0"
943 
      #VERILOG_TYPE="wire"
944 
     }
945 
     LINE  2, 0, 0
946 
     {
947 
      POINTS ( (0,0), (20,0) )
948 
     }
949 
    }
950 
    PIN  10, 0, 0
951 
    {
952 
     COORD (0,160)
953 
     VARIABLES
954 
     {
955 
      #DIRECTION="IN"
956 
      #DOWNTO="1"
957 
      #LENGTH="20"
958 
      #MDA_RECORD_TOKEN="OTHER"
959 
      #NAME="muxa_ctl_i(1:0)"
960 
      #NUMBER="0"
961 
      #VERILOG_TYPE="wire"
962 
     }
963 
     LINE  2, 0, 0
964 
     {
965 
      POINTS ( (0,0), (20,0) )
966 
     }
967 
    }
968 
   }
969 
  }
970 
 }
971 
 SYMBOL "#default" "alu_we_reg_clr_cls" "alu_we_reg_clr_cls"
972 
 {
973 
  HEADER
974 
  {
975 
   VARIABLES
976 
   {
977 
    #DESCRIPTION=""
978 
    #LANGUAGE="VERILOG"
979 
    #MODIFIED="1194389464"
980 
   }
981 
  }
982 
  PAGE ""
983 
  {
984 
   PAGEHEADER
985 
   {
986 
    RECT (0,0,320,200)
987 
    FREEID 12
988 
   }
989 
 
990 
   BODY
991 
   {
992 
    RECT  1, -1, 0
993 
    {
994 
     VARIABLES
995 
     {
996 
      #OUTLINE_FILLING="1"
997 
     }
998 
     AREA (20,0,300,200)
999 
    }
1000 
    TEXT  3, 0, 0
1001 
    {
1002 
     TEXT "$#NAME"
1003 
     RECT (25,30,170,54)
1004 
     ALIGN 4
1005 
     MARGINS (1,1)
1006 
     PARENT 2
1007 
    }
1008 
    TEXT  5, 0, 0
1009 
    {
1010 
     TEXT "$#NAME"
1011 
     RECT (150,30,295,54)
1012 
     ALIGN 6
1013 
     MARGINS (1,1)
1014 
     PARENT 4
1015 
    }
1016 
    TEXT  7, 0, 0
1017 
    {
1018 
     TEXT "$#NAME"
1019 
     RECT (25,70,60,94)
1020 
     ALIGN 4
1021 
     MARGINS (1,1)
1022 
     PARENT 6
1023 
    }
1024 
    TEXT  9, 0, 0
1025 
    {
1026 
     TEXT "$#NAME"
1027 
     RECT (25,110,60,134)
1028 
     ALIGN 4
1029 
     MARGINS (1,1)
1030 
     PARENT 8
1031 
    }
1032 
    TEXT  11, 0, 0
1033 
    {
1034 
     TEXT "$#NAME"
1035 
     RECT (25,150,60,174)
1036 
     ALIGN 4
1037 
     MARGINS (1,1)
1038 
     PARENT 10
1039 
    }
1040 
    PIN  2, 0, 0
1041 
    {
1042 
     COORD (0,40)
1043 
     VARIABLES
1044 
     {
1045 
      #DIRECTION="IN"
1046 
      #DOWNTO="1"
1047 
      #LENGTH="20"
1048 
      #MDA_RECORD_TOKEN="OTHER"
1049 
      #NAME="alu_we_i(0:0)"
1050 
      #NUMBER="0"
1051 
      #VERILOG_TYPE="wire"
1052 
     }
1053 
     LINE  2, 0, 0
1054 
     {
1055 
      POINTS ( (0,0), (20,0) )
1056 
     }
1057 
    }
1058 
    PIN  4, 0, 0
1059 
    {
1060 
     COORD (320,40)
1061 
     VARIABLES
1062 
     {
1063 
      #DIRECTION="OUT"
1064 
      #DOWNTO="1"
1065 
      #LENGTH="20"
1066 
      #MDA_RECORD_TOKEN="OTHER"
1067 
      #NAME="alu_we_o(0:0)"
1068 
      #NUMBER="0"
1069 
      #VERILOG_TYPE="reg"
1070 
     }
1071 
     LINE  2, 0, 0
1072 
     {
1073 
      POINTS ( (-20,0), (0,0) )
1074 
     }
1075 
    }
1076 
    PIN  6, 0, 0
1077 
    {
1078 
     COORD (0,80)
1079 
     VARIABLES
1080 
     {
1081 
      #DIRECTION="IN"
1082 
      #LENGTH="20"
1083 
      #MDA_RECORD_TOKEN="OTHER"
1084 
      #NAME="clk"
1085 
      #NUMBER="0"
1086 
      #VERILOG_TYPE="wire"
1087 
     }
1088 
     LINE  2, 0, 0
1089 
     {
1090 
      POINTS ( (0,0), (20,0) )
1091 
     }
1092 
    }
1093 
    PIN  8, 0, 0
1094 
    {
1095 
     COORD (0,120)
1096 
     VARIABLES
1097 
     {
1098 
      #DIRECTION="IN"
1099 
      #LENGTH="20"
1100 
      #MDA_RECORD_TOKEN="OTHER"
1101 
      #NAME="clr"
1102 
      #NUMBER="0"
1103 
      #VERILOG_TYPE="wire"
1104 
     }
1105 
     LINE  2, 0, 0
1106 
     {
1107 
      POINTS ( (0,0), (20,0) )
1108 
     }
1109 
    }
1110 
    PIN  10, 0, 0
1111 
    {
1112 
     COORD (0,160)
1113 
     VARIABLES
1114 
     {
1115 
      #DIRECTION="IN"
1116 
      #LENGTH="20"
1117 
      #MDA_RECORD_TOKEN="OTHER"
1118 
      #NAME="cls"
1119 
      #NUMBER="0"
1120 
      #VERILOG_TYPE="wire"
1121 
     }
1122 
     LINE  2, 0, 0
1123 
     {
1124 
      POINTS ( (0,0), (20,0) )
1125 
     }
1126 
    }
1127 
   }
1128 
  }
1129 
 }
1130 
 SYMBOL "#default" "ext_ctl_reg_clr_cls" "ext_ctl_reg_clr_cls"
1131 
 {
1132 
  HEADER
1133 
  {
1134 
   VARIABLES
1135 
   {
1136 
    #DESCRIPTION=""
1137 
    #LANGUAGE="VERILOG"
1138 
    #MODIFIED="1194389480"
1139 
   }
1140 
  }
1141 
  PAGE ""
1142 
  {
1143 
   PAGEHEADER
1144 
   {
1145 
    RECT (0,0,220,200)
1146 
    FREEID 12
1147 
   }
1148 
 
1149 
   BODY
1150 
   {
1151 
    RECT  1, -1, 0
1152 
    {
1153 
     VARIABLES
1154 
     {
1155 
      #OUTLINE_FILLING="1"
1156 
     }
1157 
     AREA (20,0,200,200)
1158 
    }
1159 
    TEXT  3, 0, 0
1160 
    {
1161 
     TEXT "$#NAME"
1162 
     RECT (25,30,60,54)
1163 
     ALIGN 4
1164 
     MARGINS (1,1)
1165 
     PARENT 2
1166 
    }
1167 
    TEXT  5, 0, 0
1168 
    {
1169 
     TEXT "$#NAME"
1170 
     RECT (39,30,195,54)
1171 
     ALIGN 6
1172 
     MARGINS (1,1)
1173 
     PARENT 4
1174 
    }
1175 
    TEXT  7, 0, 0
1176 
    {
1177 
     TEXT "$#NAME"
1178 
     RECT (25,70,60,94)
1179 
     ALIGN 4
1180 
     MARGINS (1,1)
1181 
     PARENT 6
1182 
    }
1183 
    TEXT  9, 0, 0
1184 
    {
1185 
     TEXT "$#NAME"
1186 
     RECT (25,110,60,134)
1187 
     ALIGN 4
1188 
     MARGINS (1,1)
1189 
     PARENT 8
1190 
    }
1191 
    TEXT  11, 0, 0
1192 
    {
1193 
     TEXT "$#NAME"
1194 
     RECT (25,150,181,174)
1195 
     ALIGN 4
1196 
     MARGINS (1,1)
1197 
     PARENT 10
1198 
    }
1199 
    PIN  2, 0, 0
1200 
    {
1201 
     COORD (0,40)
1202 
     VARIABLES
1203 
     {
1204 
      #DIRECTION="IN"
1205 
      #LENGTH="20"
1206 
      #MDA_RECORD_TOKEN="OTHER"
1207 
      #NAME="clk"
1208 
      #NUMBER="0"
1209 
      #VERILOG_TYPE="wire"
1210 
     }
1211 
     LINE  2, 0, 0
1212 
     {
1213 
      POINTS ( (0,0), (20,0) )
1214 
     }
1215 
    }
1216 
    PIN  4, 0, 0
1217 
    {
1218 
     COORD (220,40)
1219 
     VARIABLES
1220 
     {
1221 
      #DIRECTION="OUT"
1222 
      #DOWNTO="1"
1223 
      #LENGTH="20"
1224 
      #MDA_RECORD_TOKEN="OTHER"
1225 
      #NAME="ext_ctl_o(2:0)"
1226 
      #NUMBER="0"
1227 
      #VERILOG_TYPE="reg"
1228 
     }
1229 
     LINE  2, 0, 0
1230 
     {
1231 
      POINTS ( (-20,0), (0,0) )
1232 
     }
1233 
    }
1234 
    PIN  6, 0, 0
1235 
    {
1236 
     COORD (0,80)
1237 
     VARIABLES
1238 
     {
1239 
      #DIRECTION="IN"
1240 
      #LENGTH="20"
1241 
      #MDA_RECORD_TOKEN="OTHER"
1242 
      #NAME="clr"
1243 
      #NUMBER="0"
1244 
      #VERILOG_TYPE="wire"
1245 
     }
1246 
     LINE  2, 0, 0
1247 
     {
1248 
      POINTS ( (0,0), (20,0) )
1249 
     }
1250 
    }
1251 
    PIN  8, 0, 0
1252 
    {
1253 
     COORD (0,120)
1254 
     VARIABLES
1255 
     {
1256 
      #DIRECTION="IN"
1257 
      #LENGTH="20"
1258 
      #MDA_RECORD_TOKEN="OTHER"
1259 
      #NAME="cls"
1260 
      #NUMBER="0"
1261 
      #VERILOG_TYPE="wire"
1262 
     }
1263 
     LINE  2, 0, 0
1264 
     {
1265 
      POINTS ( (0,0), (20,0) )
1266 
     }
1267 
    }
1268 
    PIN  10, 0, 0
1269 
    {
1270 
     COORD (0,160)
1271 
     VARIABLES
1272 
     {
1273 
      #DIRECTION="IN"
1274 
      #DOWNTO="1"
1275 
      #LENGTH="20"
1276 
      #MDA_RECORD_TOKEN="OTHER"
1277 
      #NAME="ext_ctl_i(2:0)"
1278 
      #NUMBER="0"
1279 
      #VERILOG_TYPE="wire"
1280 
     }
1281 
     LINE  2, 0, 0
1282 
     {
1283 
      POINTS ( (0,0), (20,0) )
1284 
     }
1285 
    }
1286 
   }
1287 
  }
1288 
 }
1289 
 SYMBOL "#default" "cmp_ctl_reg_clr_cls" "cmp_ctl_reg_clr_cls"
1290 
 {
1291 
  HEADER
1292 
  {
1293 
   VARIABLES
1294 
   {
1295 
    #DESCRIPTION=""
1296 
    #LANGUAGE="VERILOG"
1297 
    #MODIFIED="1194389491"
1298 
   }
1299 
  }
1300 
  PAGE ""
1301 
  {
1302 
   PAGEHEADER
1303 
   {
1304 
    RECT (0,0,220,200)
1305 
    FREEID 12
1306 
   }
1307 
 
1308 
   BODY
1309 
   {
1310 
    RECT  1, -1, 0
1311 
    {
1312 
     VARIABLES
1313 
     {
1314 
      #OUTLINE_FILLING="1"
1315 
     }
1316 
     AREA (20,0,200,200)
1317 
    }
1318 
    TEXT  3, 0, 0
1319 
    {
1320 
     TEXT "$#NAME"
1321 
     RECT (25,30,60,54)
1322 
     ALIGN 4
1323 
     MARGINS (1,1)
1324 
     PARENT 2
1325 
    }
1326 
    TEXT  5, 0, 0
1327 
    {
1328 
     TEXT "$#NAME"
1329 
     RECT (39,30,195,54)
1330 
     ALIGN 6
1331 
     MARGINS (1,1)
1332 
     PARENT 4
1333 
    }
1334 
    TEXT  7, 0, 0
1335 
    {
1336 
     TEXT "$#NAME"
1337 
     RECT (25,70,60,94)
1338 
     ALIGN 4
1339 
     MARGINS (1,1)
1340 
     PARENT 6
1341 
    }
1342 
    TEXT  9, 0, 0
1343 
    {
1344 
     TEXT "$#NAME"
1345 
     RECT (25,110,60,134)
1346 
     ALIGN 4
1347 
     MARGINS (1,1)
1348 
     PARENT 8
1349 
    }
1350 
    TEXT  11, 0, 0
1351 
    {
1352 
     TEXT "$#NAME"
1353 
     RECT (25,150,181,174)
1354 
     ALIGN 4
1355 
     MARGINS (1,1)
1356 
     PARENT 10
1357 
    }
1358 
    PIN  2, 0, 0
1359 
    {
1360 
     COORD (0,40)
1361 
     VARIABLES
1362 
     {
1363 
      #DIRECTION="IN"
1364 
      #LENGTH="20"
1365 
      #MDA_RECORD_TOKEN="OTHER"
1366 
      #NAME="clk"
1367 
      #NUMBER="0"
1368 
      #VERILOG_TYPE="wire"
1369 
     }
1370 
     LINE  2, 0, 0
1371 
     {
1372 
      POINTS ( (0,0), (20,0) )
1373 
     }
1374 
    }
1375 
    PIN  4, 0, 0
1376 
    {
1377 
     COORD (220,40)
1378 
     VARIABLES
1379 
     {
1380 
      #DIRECTION="OUT"
1381 
      #DOWNTO="1"
1382 
      #LENGTH="20"
1383 
      #MDA_RECORD_TOKEN="OTHER"
1384 
      #NAME="cmp_ctl_o(2:0)"
1385 
      #NUMBER="0"
1386 
      #VERILOG_TYPE="reg"
1387 
     }
1388 
     LINE  2, 0, 0
1389 
     {
1390 
      POINTS ( (-20,0), (0,0) )
1391 
     }
1392 
    }
1393 
    PIN  6, 0, 0
1394 
    {
1395 
     COORD (0,80)
1396 
     VARIABLES
1397 
     {
1398 
      #DIRECTION="IN"
1399 
      #LENGTH="20"
1400 
      #MDA_RECORD_TOKEN="OTHER"
1401 
      #NAME="clr"
1402 
      #NUMBER="0"
1403 
      #VERILOG_TYPE="wire"
1404 
     }
1405 
     LINE  2, 0, 0
1406 
     {
1407 
      POINTS ( (0,0), (20,0) )
1408 
     }
1409 
    }
1410 
    PIN  8, 0, 0
1411 
    {
1412 
     COORD (0,120)
1413 
     VARIABLES
1414 
     {
1415 
      #DIRECTION="IN"
1416 
      #LENGTH="20"
1417 
      #MDA_RECORD_TOKEN="OTHER"
1418 
      #NAME="cls"
1419 
      #NUMBER="0"
1420 
      #VERILOG_TYPE="wire"
1421 
     }
1422 
     LINE  2, 0, 0
1423 
     {
1424 
      POINTS ( (0,0), (20,0) )
1425 
     }
1426 
    }
1427 
    PIN  10, 0, 0
1428 
    {
1429 
     COORD (0,160)
1430 
     VARIABLES
1431 
     {
1432 
      #DIRECTION="IN"
1433 
      #DOWNTO="1"
1434 
      #LENGTH="20"
1435 
      #MDA_RECORD_TOKEN="OTHER"
1436 
      #NAME="cmp_ctl_i(2:0)"
1437 
      #NUMBER="0"
1438 
      #VERILOG_TYPE="wire"
1439 
     }
1440 
     LINE  2, 0, 0
1441 
     {
1442 
      POINTS ( (0,0), (20,0) )
1443 
     }
1444 
    }
1445 
   }
1446 
  }
1447 
 }
1448 
 SYMBOL "#default" "rd_sel_reg_clr_cls" "rd_sel_reg_clr_cls"
1449 
 {
1450 
  HEADER
1451 
  {
1452 
   VARIABLES
1453 
   {
1454 
    #DESCRIPTION=""
1455 
    #LANGUAGE="VERILOG"
1456 
    #MODIFIED="1194389536"
1457 
   }
1458 
  }
1459 
  PAGE ""
1460 
  {
1461 
   PAGEHEADER
1462 
   {
1463 
    RECT (0,0,220,200)
1464 
    FREEID 12
1465 
   }
1466 
 
1467 
   BODY
1468 
   {
1469 
    RECT  1, -1, 0
1470 
    {
1471 
     VARIABLES
1472 
     {
1473 
      #OUTLINE_FILLING="1"
1474 
     }
1475 
     AREA (20,0,200,200)
1476 
    }
1477 
    TEXT  3, 0, 0
1478 
    {
1479 
     TEXT "$#NAME"
1480 
     RECT (25,30,60,54)
1481 
     ALIGN 4
1482 
     MARGINS (1,1)
1483 
     PARENT 2
1484 
    }
1485 
    TEXT  5, 0, 0
1486 
    {
1487 
     TEXT "$#NAME"
1488 
     RECT (50,30,195,54)
1489 
     ALIGN 6
1490 
     MARGINS (1,1)
1491 
     PARENT 4
1492 
    }
1493 
    TEXT  7, 0, 0
1494 
    {
1495 
     TEXT "$#NAME"
1496 
     RECT (25,70,60,94)
1497 
     ALIGN 4
1498 
     MARGINS (1,1)
1499 
     PARENT 6
1500 
    }
1501 
    TEXT  9, 0, 0
1502 
    {
1503 
     TEXT "$#NAME"
1504 
     RECT (25,110,60,134)
1505 
     ALIGN 4
1506 
     MARGINS (1,1)
1507 
     PARENT 8
1508 
    }
1509 
    TEXT  11, 0, 0
1510 
    {
1511 
     TEXT "$#NAME"
1512 
     RECT (25,150,170,174)
1513 
     ALIGN 4
1514 
     MARGINS (1,1)
1515 
     PARENT 10
1516 
    }
1517 
    PIN  2, 0, 0
1518 
    {
1519 
     COORD (0,40)
1520 
     VARIABLES
1521 
     {
1522 
      #DIRECTION="IN"
1523 
      #LENGTH="20"
1524 
      #MDA_RECORD_TOKEN="OTHER"
1525 
      #NAME="clk"
1526 
      #NUMBER="0"
1527 
      #VERILOG_TYPE="wire"
1528 
     }
1529 
     LINE  2, 0, 0
1530 
     {
1531 
      POINTS ( (0,0), (20,0) )
1532 
     }
1533 
    }
1534 
    PIN  4, 0, 0
1535 
    {
1536 
     COORD (220,40)
1537 
     VARIABLES
1538 
     {
1539 
      #DIRECTION="OUT"
1540 
      #DOWNTO="1"
1541 
      #LENGTH="20"
1542 
      #MDA_RECORD_TOKEN="OTHER"
1543 
      #NAME="rd_sel_o(1:0)"
1544 
      #NUMBER="0"
1545 
      #VERILOG_TYPE="reg"
1546 
     }
1547 
     LINE  2, 0, 0
1548 
     {
1549 
      POINTS ( (-20,0), (0,0) )
1550 
     }
1551 
    }
1552 
    PIN  6, 0, 0
1553 
    {
1554 
     COORD (0,80)
1555 
     VARIABLES
1556 
     {
1557 
      #DIRECTION="IN"
1558 
      #LENGTH="20"
1559 
      #MDA_RECORD_TOKEN="OTHER"
1560 
      #NAME="clr"
1561 
      #NUMBER="0"
1562 
      #VERILOG_TYPE="wire"
1563 
     }
1564 
     LINE  2, 0, 0
1565 
     {
1566 
      POINTS ( (0,0), (20,0) )
1567 
     }
1568 
    }
1569 
    PIN  8, 0, 0
1570 
    {
1571 
     COORD (0,120)
1572 
     VARIABLES
1573 
     {
1574 
      #DIRECTION="IN"
1575 
      #LENGTH="20"
1576 
      #MDA_RECORD_TOKEN="OTHER"
1577 
      #NAME="cls"
1578 
      #NUMBER="0"
1579 
      #VERILOG_TYPE="wire"
1580 
     }
1581 
     LINE  2, 0, 0
1582 
     {
1583 
      POINTS ( (0,0), (20,0) )
1584 
     }
1585 
    }
1586 
    PIN  10, 0, 0
1587 
    {
1588 
     COORD (0,160)
1589 
     VARIABLES
1590 
     {
1591 
      #DIRECTION="IN"
1592 
      #DOWNTO="1"
1593 
      #LENGTH="20"
1594 
      #MDA_RECORD_TOKEN="OTHER"
1595 
      #NAME="rd_sel_i(1:0)"
1596 
      #NUMBER="0"
1597 
      #VERILOG_TYPE="wire"
1598 
     }
1599 
     LINE  2, 0, 0
1600 
     {
1601 
      POINTS ( (0,0), (20,0) )
1602 
     }
1603 
    }
1604 
   }
1605 
  }
1606 
 }
1607 
 SYMBOL "#default" "pc_gen_ctl_reg_clr_cls" "pc_gen_ctl_reg_clr_cls"
1608 
 {
1609 
  HEADER
1610 
  {
1611 
   VARIABLES
1612 
   {
1613 
    #DESCRIPTION=""
1614 
    #LANGUAGE="VERILOG"
1615 
    #MODIFIED="1194389553"
1616 
   }
1617 
  }
1618 
  PAGE ""
1619 
  {
1620 
   PAGEHEADER
1621 
   {
1622 
    RECT (0,0,260,200)
1623 
    FREEID 12
1624 
   }
1625 
 
1626 
   BODY
1627 
   {
1628 
    RECT  1, -1, 0
1629 
    {
1630 
     VARIABLES
1631 
     {
1632 
      #OUTLINE_FILLING="1"
1633 
     }
1634 
     AREA (20,0,240,200)
1635 
    }
1636 
    TEXT  3, 0, 0
1637 
    {
1638 
     TEXT "$#NAME"
1639 
     RECT (25,30,60,54)
1640 
     ALIGN 4
1641 
     MARGINS (1,1)
1642 
     PARENT 2
1643 
    }
1644 
    TEXT  5, 0, 0
1645 
    {
1646 
     TEXT "$#NAME"
1647 
     RECT (46,30,235,54)
1648 
     ALIGN 6
1649 
     MARGINS (1,1)
1650 
     PARENT 4
1651 
    }
1652 
    TEXT  7, 0, 0
1653 
    {
1654 
     TEXT "$#NAME"
1655 
     RECT (25,70,60,94)
1656 
     ALIGN 4
1657 
     MARGINS (1,1)
1658 
     PARENT 6
1659 
    }
1660 
    TEXT  9, 0, 0
1661 
    {
1662 
     TEXT "$#NAME"
1663 
     RECT (25,110,60,134)
1664 
     ALIGN 4
1665 
     MARGINS (1,1)
1666 
     PARENT 8
1667 
    }
1668 
    TEXT  11, 0, 0
1669 
    {
1670 
     TEXT "$#NAME"
1671 
     RECT (25,150,214,174)
1672 
     ALIGN 4
1673 
     MARGINS (1,1)
1674 
     PARENT 10
1675 
    }
1676 
    PIN  2, 0, 0
1677 
    {
1678 
     COORD (0,40)
1679 
     VARIABLES
1680 
     {
1681 
      #DIRECTION="IN"
1682 
      #LENGTH="20"
1683 
      #MDA_RECORD_TOKEN="OTHER"
1684 
      #NAME="clk"
1685 
      #NUMBER="0"
1686 
      #VERILOG_TYPE="wire"
1687 
     }
1688 
     LINE  2, 0, 0
1689 
     {
1690 
      POINTS ( (0,0), (20,0) )
1691 
     }
1692 
    }
1693 
    PIN  4, 0, 0
1694 
    {
1695 
     COORD (260,40)
1696 
     VARIABLES
1697 
     {
1698 
      #DIRECTION="OUT"
1699 
      #DOWNTO="1"
1700 
      #LENGTH="20"
1701 
      #MDA_RECORD_TOKEN="OTHER"
1702 
      #NAME="pc_gen_ctl_o(2:0)"
1703 
      #NUMBER="0"
1704 
      #VERILOG_TYPE="reg"
1705 
     }
1706 
     LINE  2, 0, 0
1707 
     {
1708 
      POINTS ( (-20,0), (0,0) )
1709 
     }
1710 
    }
1711 
    PIN  6, 0, 0
1712 
    {
1713 
     COORD (0,80)
1714 
     VARIABLES
1715 
     {
1716 
      #DIRECTION="IN"
1717 
      #LENGTH="20"
1718 
      #MDA_RECORD_TOKEN="OTHER"
1719 
      #NAME="clr"
1720 
      #NUMBER="0"
1721 
      #VERILOG_TYPE="wire"
1722 
     }
1723 
     LINE  2, 0, 0
1724 
     {
1725 
      POINTS ( (0,0), (20,0) )
1726 
     }
1727 
    }
1728 
    PIN  8, 0, 0
1729 
    {
1730 
     COORD (0,120)
1731 
     VARIABLES
1732 
     {
1733 
      #DIRECTION="IN"
1734 
      #LENGTH="20"
1735 
      #MDA_RECORD_TOKEN="OTHER"
1736 
      #NAME="cls"
1737 
      #NUMBER="0"
1738 
      #VERILOG_TYPE="wire"
1739 
     }
1740 
     LINE  2, 0, 0
1741 
     {
1742 
      POINTS ( (0,0), (20,0) )
1743 
     }
1744 
    }
1745 
    PIN  10, 0, 0
1746 
    {
1747 
     COORD (0,160)
1748 
     VARIABLES
1749 
     {
1750 
      #DIRECTION="IN"
1751 
      #DOWNTO="1"
1752 
      #LENGTH="20"
1753 
      #MDA_RECORD_TOKEN="OTHER"
1754 
      #NAME="pc_gen_ctl_i(2:0)"
1755 
      #NUMBER="0"
1756 
      #VERILOG_TYPE="wire"
1757 
     }
1758 
     LINE  2, 0, 0
1759 
     {
1760 
      POINTS ( (0,0), (20,0) )
1761 
     }
1762 
    }
1763 
   }
1764 
  }
1765 
 }
1766 
 SYMBOL "#default" "alu_we_reg_clr" "alu_we_reg_clr"
1767 
 {
1768 
  HEADER
1769 
  {
1770 
   VARIABLES
1771 
   {
1772 
    #DESCRIPTION=""
1773 
    #LANGUAGE="VERILOG"
1774 
    #MODIFIED="1194390513"
1775 
   }
1776 
  }
1777 
  PAGE ""
1778 
  {
1779 
   PAGEHEADER
1780 
   {
1781 
    RECT (0,0,320,160)
1782 
    FREEID 10
1783 
   }
1784 
 
1785 
   BODY
1786 
   {
1787 
    RECT  1, -1, 0
1788 
    {
1789 
     VARIABLES
1790 
     {
1791 
      #OUTLINE_FILLING="1"
1792 
     }
1793 
     AREA (20,0,300,160)
1794 
    }
1795 
    TEXT  3, 0, 0
1796 
    {
1797 
     TEXT "$#NAME"
1798 
     RECT (25,30,170,54)
1799 
     ALIGN 4
1800 
     MARGINS (1,1)
1801 
     PARENT 2
1802 
    }
1803 
    TEXT  5, 0, 0
1804 
    {
1805 
     TEXT "$#NAME"
1806 
     RECT (150,30,295,54)
1807 
     ALIGN 6
1808 
     MARGINS (1,1)
1809 
     PARENT 4
1810 
    }
1811 
    TEXT  7, 0, 0
1812 
    {
1813 
     TEXT "$#NAME"
1814 
     RECT (25,70,60,94)
1815 
     ALIGN 4
1816 
     MARGINS (1,1)
1817 
     PARENT 6
1818 
    }
1819 
    TEXT  9, 0, 0
1820 
    {
1821 
     TEXT "$#NAME"
1822 
     RECT (25,110,60,134)
1823 
     ALIGN 4
1824 
     MARGINS (1,1)
1825 
     PARENT 8
1826 
    }
1827 
    PIN  2, 0, 0
1828 
    {
1829 
     COORD (0,40)
1830 
     VARIABLES
1831 
     {
1832 
      #DIRECTION="IN"
1833 
      #DOWNTO="1"
1834 
      #LENGTH="20"
1835 
      #MDA_RECORD_TOKEN="OTHER"
1836 
      #NAME="alu_we_i(0:0)"
1837 
      #NUMBER="0"
1838 
      #VERILOG_TYPE="wire"
1839 
     }
1840 
     LINE  2, 0, 0
1841 
     {
1842 
      POINTS ( (0,0), (20,0) )
1843 
     }
1844 
    }
1845 
    PIN  4, 0, 0
1846 
    {
1847 
     COORD (320,40)
1848 
     VARIABLES
1849 
     {
1850 
      #DIRECTION="OUT"
1851 
      #DOWNTO="1"
1852 
      #LENGTH="20"
1853 
      #MDA_RECORD_TOKEN="OTHER"
1854 
      #NAME="alu_we_o(0:0)"
1855 
      #NUMBER="0"
1856 
      #VERILOG_TYPE="reg"
1857 
     }
1858 
     LINE  2, 0, 0
1859 
     {
1860 
      POINTS ( (-20,0), (0,0) )
1861 
     }
1862 
    }
1863 
    PIN  6, 0, 0
1864 
    {
1865 
     COORD (0,80)
1866 
     VARIABLES
1867 
     {
1868 
      #DIRECTION="IN"
1869 
      #LENGTH="20"
1870 
      #MDA_RECORD_TOKEN="OTHER"
1871 
      #NAME="clk"
1872 
      #NUMBER="0"
1873 
      #VERILOG_TYPE="wire"
1874 
     }
1875 
     LINE  2, 0, 0
1876 
     {
1877 
      POINTS ( (0,0), (20,0) )
1878 
     }
1879 
    }
1880 
    PIN  8, 0, 0
1881 
    {
1882 
     COORD (0,120)
1883 
     VARIABLES
1884 
     {
1885 
      #DIRECTION="IN"
1886 
      #LENGTH="20"
1887 
      #MDA_RECORD_TOKEN="OTHER"
1888 
      #NAME="clr"
1889 
      #NUMBER="0"
1890 
      #VERILOG_TYPE="wire"
1891 
     }
1892 
     LINE  2, 0, 0
1893 
     {
1894 
      POINTS ( (0,0), (20,0) )
1895 
     }
1896 
    }
1897 
   }
1898 
  }
1899 
 }
1900 
 SYMBOL "#default" "alu_func_reg_clr" "alu_func_reg_clr"
1901 
 {
1902 
  HEADER
1903 
  {
1904 
   VARIABLES
1905 
   {
1906 
    #DESCRIPTION=""
1907 
    #LANGUAGE="VERILOG"
1908 
    #MODIFIED="1194390608"
1909 
   }
1910 
  }
1911 
  PAGE ""
1912 
  {
1913 
   PAGEHEADER
1914 
   {
1915 
    RECT (0,0,340,160)
1916 
    FREEID 10
1917 
   }
1918 
 
1919 
   BODY
1920 
   {
1921 
    RECT  1, -1, 0
1922 
    {
1923 
     VARIABLES
1924 
     {
1925 
      #OUTLINE_FILLING="1"
1926 
     }
1927 
     AREA (20,0,320,160)
1928 
    }
1929 
    TEXT  3, 0, 0
1930 
    {
1931 
     TEXT "$#NAME"
1932 
     RECT (25,30,192,54)
1933 
     ALIGN 4
1934 
     MARGINS (1,1)
1935 
     PARENT 2
1936 
    }
1937 
    TEXT  5, 0, 0
1938 
    {
1939 
     TEXT "$#NAME"
1940 
     RECT (148,30,315,54)
1941 
     ALIGN 6
1942 
     MARGINS (1,1)
1943 
     PARENT 4
1944 
    }
1945 
    TEXT  7, 0, 0
1946 
    {
1947 
     TEXT "$#NAME"
1948 
     RECT (25,70,60,94)
1949 
     ALIGN 4
1950 
     MARGINS (1,1)
1951 
     PARENT 6
1952 
    }
1953 
    TEXT  9, 0, 0
1954 
    {
1955 
     TEXT "$#NAME"
1956 
     RECT (25,110,60,134)
1957 
     ALIGN 4
1958 
     MARGINS (1,1)
1959 
     PARENT 8
1960 
    }
1961 
    PIN  2, 0, 0
1962 
    {
1963 
     COORD (0,40)
1964 
     VARIABLES
1965 
     {
1966 
      #DIRECTION="IN"
1967 
      #DOWNTO="1"
1968 
      #LENGTH="20"
1969 
      #MDA_RECORD_TOKEN="OTHER"
1970 
      #NAME="alu_func_i(4:0)"
1971 
      #NUMBER="0"
1972 
      #VERILOG_TYPE="wire"
1973 
     }
1974 
     LINE  2, 0, 0
1975 
     {
1976 
      POINTS ( (0,0), (20,0) )
1977 
     }
1978 
    }
1979 
    PIN  4, 0, 0
1980 
    {
1981 
     COORD (340,40)
1982 
     VARIABLES
1983 
     {
1984 
      #DIRECTION="OUT"
1985 
      #DOWNTO="1"
1986 
      #LENGTH="20"
1987 
      #MDA_RECORD_TOKEN="OTHER"
1988 
      #NAME="alu_func_o(4:0)"
1989 
      #NUMBER="0"
1990 
      #VERILOG_TYPE="reg"
1991 
     }
1992 
     LINE  2, 0, 0
1993 
     {
1994 
      POINTS ( (-20,0), (0,0) )
1995 
     }
1996 
    }
1997 
    PIN  6, 0, 0
1998 
    {
1999 
     COORD (0,80)
2000 
     VARIABLES
2001 
     {
2002 
      #DIRECTION="IN"
2003 
      #LENGTH="20"
2004 
      #MDA_RECORD_TOKEN="OTHER"
2005 
      #NAME="clk"
2006 
      #NUMBER="0"
2007 
      #VERILOG_TYPE="wire"
2008 
     }
2009 
     LINE  2, 0, 0
2010 
     {
2011 
      POINTS ( (0,0), (20,0) )
2012 
     }
2013 
    }
2014 
    PIN  8, 0, 0
2015 
    {
2016 
     COORD (0,120)
2017 
     VARIABLES
2018 
     {
2019 
      #DIRECTION="IN"
2020 
      #LENGTH="20"
2021 
      #MDA_RECORD_TOKEN="OTHER"
2022 
      #NAME="clr"
2023 
      #NUMBER="0"
2024 
      #VERILOG_TYPE="wire"
2025 
     }
2026 
     LINE  2, 0, 0
2027 
     {
2028 
      POINTS ( (0,0), (20,0) )
2029 
     }
2030 
    }
2031 
   }
2032 
  }
2033 
 }
2034 
 SYMBOL "#default" "wb_mux_ctl_reg_clr" "wb_mux_ctl_reg_clr"
2035 
 {
2036 
  HEADER
2037 
  {
2038 
   VARIABLES
2039 
   {
2040 
    #DESCRIPTION=""
2041 
    #LANGUAGE="VERILOG"
2042 
    #MODIFIED="1194390665"
2043 
   }
2044 
  }
2045 
  PAGE ""
2046 
  {
2047 
   PAGEHEADER
2048 
   {
2049 
    RECT (0,0,260,160)
2050 
    FREEID 10
2051 
   }
2052 
 
2053 
   BODY
2054 
   {
2055 
    RECT  1, -1, 0
2056 
    {
2057 
     VARIABLES
2058 
     {
2059 
      #OUTLINE_FILLING="1"
2060 
     }
2061 
     AREA (20,0,240,160)
2062 
    }
2063 
    TEXT  3, 0, 0
2064 
    {
2065 
     TEXT "$#NAME"
2066 
     RECT (25,30,60,54)
2067 
     ALIGN 4
2068 
     MARGINS (1,1)
2069 
     PARENT 2
2070 
    }
2071 
    TEXT  5, 0, 0
2072 
    {
2073 
     TEXT "$#NAME"
2074 
     RECT (46,30,235,54)
2075 
     ALIGN 6
2076 
     MARGINS (1,1)
2077 
     PARENT 4
2078 
    }
2079 
    TEXT  7, 0, 0
2080 
    {
2081 
     TEXT "$#NAME"
2082 
     RECT (25,70,60,94)
2083 
     ALIGN 4
2084 
     MARGINS (1,1)
2085 
     PARENT 6
2086 
    }
2087 
    TEXT  9, 0, 0
2088 
    {
2089 
     TEXT "$#NAME"
2090 
     RECT (25,110,214,134)
2091 
     ALIGN 4
2092 
     MARGINS (1,1)
2093 
     PARENT 8
2094 
    }
2095 
    PIN  2, 0, 0
2096 
    {
2097 
     COORD (0,40)
2098 
     VARIABLES
2099 
     {
2100 
      #DIRECTION="IN"
2101 
      #LENGTH="20"
2102 
      #MDA_RECORD_TOKEN="OTHER"
2103 
      #NAME="clk"
2104 
      #NUMBER="0"
2105 
      #VERILOG_TYPE="wire"
2106 
     }
2107 
     LINE  2, 0, 0
2108 
     {
2109 
      POINTS ( (0,0), (20,0) )
2110 
     }
2111 
    }
2112 
    PIN  4, 0, 0
2113 
    {
2114 
     COORD (260,40)
2115 
     VARIABLES
2116 
     {
2117 
      #DIRECTION="OUT"
2118 
      #DOWNTO="1"
2119 
      #LENGTH="20"
2120 
      #MDA_RECORD_TOKEN="OTHER"
2121 
      #NAME="wb_mux_ctl_o(0:0)"
2122 
      #NUMBER="0"
2123 
      #VERILOG_TYPE="reg"
2124 
     }
2125 
     LINE  2, 0, 0
2126 
     {
2127 
      POINTS ( (-20,0), (0,0) )
2128 
     }
2129 
    }
2130 
    PIN  6, 0, 0
2131 
    {
2132 
     COORD (0,80)
2133 
     VARIABLES
2134 
     {
2135 
      #DIRECTION="IN"
2136 
      #LENGTH="20"
2137 
      #MDA_RECORD_TOKEN="OTHER"
2138 
      #NAME="clr"
2139 
      #NUMBER="0"
2140 
      #VERILOG_TYPE="wire"
2141 
     }
2142 
     LINE  2, 0, 0
2143 
     {
2144 
      POINTS ( (0,0), (20,0) )
2145 
     }
2146 
    }
2147 
    PIN  8, 0, 0
2148 
    {
2149 
     COORD (0,120)
2150 
     VARIABLES
2151 
     {
2152 
      #DIRECTION="IN"
2153 
      #DOWNTO="1"
2154 
      #LENGTH="20"
2155 
      #MDA_RECORD_TOKEN="OTHER"
2156 
      #NAME="wb_mux_ctl_i(0:0)"
2157 
      #NUMBER="0"
2158 
      #VERILOG_TYPE="wire"
2159 
     }
2160 
     LINE  2, 0, 0
2161 
     {
2162 
      POINTS ( (0,0), (20,0) )
2163 
     }
2164 
    }
2165 
   }
2166 
  }
2167 
 }
2168 
 SYMBOL "#default" "dmem_ctl_reg" "dmem_ctl_reg"
2169 
 {
2170 
  HEADER
2171 
  {
2172 
   VARIABLES
2173 
   {
2174 
    #DESCRIPTION=""
2175 
    #LANGUAGE="VERILOG"
2176 
    #MODIFIED="1194390823"
2177 
   }
2178 
  }
2179 
  PAGE ""
2180 
  {
2181 
   PAGEHEADER
2182 
   {
2183 
    RECT (0,0,240,120)
2184 
    FREEID 8
2185 
   }
2186 
 
2187 
   BODY
2188 
   {
2189 
    RECT  1, -1, 0
2190 
    {
2191 
     VARIABLES
2192 
     {
2193 
      #OUTLINE_FILLING="1"
2194 
     }
2195 
     AREA (20,0,220,120)
2196 
    }
2197 
    TEXT  3, 0, 0
2198 
    {
2199 
     TEXT "$#NAME"
2200 
     RECT (25,30,60,54)
2201 
     ALIGN 4
2202 
     MARGINS (1,1)
2203 
     PARENT 2
2204 
    }
2205 
    TEXT  5, 0, 0
2206 
    {
2207 
     TEXT "$#NAME"
2208 
     RECT (48,30,215,54)
2209 
     ALIGN 6
2210 
     MARGINS (1,1)
2211 
     PARENT 4
2212 
    }
2213 
    TEXT  7, 0, 0
2214 
    {
2215 
     TEXT "$#NAME"
2216 
     RECT (25,70,192,94)
2217 
     ALIGN 4
2218 
     MARGINS (1,1)
2219 
     PARENT 6
2220 
    }
2221 
    PIN  2, 0, 0
2222 
    {
2223 
     COORD (0,40)
2224 
     VARIABLES
2225 
     {
2226 
      #DIRECTION="IN"
2227 
      #LENGTH="20"
2228 
      #MDA_RECORD_TOKEN="OTHER"
2229 
      #NAME="clk"
2230 
      #NUMBER="0"
2231 
      #VERILOG_TYPE="wire"
2232 
     }
2233 
     LINE  2, 0, 0
2234 
     {
2235 
      POINTS ( (0,0), (20,0) )
2236 
     }
2237 
    }
2238 
    PIN  4, 0, 0
2239 
    {
2240 
     COORD (240,40)
2241 
     VARIABLES
2242 
     {
2243 
      #DIRECTION="OUT"
2244 
      #DOWNTO="1"
2245 
      #LENGTH="20"
2246 
      #MDA_RECORD_TOKEN="OTHER"
2247 
      #NAME="dmem_ctl_o(3:0)"
2248 
      #NUMBER="0"
2249 
      #VERILOG_TYPE="reg"
2250 
     }
2251 
     LINE  2, 0, 0
2252 
     {
2253 
      POINTS ( (-20,0), (0,0) )
2254 
     }
2255 
    }
2256 
    PIN  6, 0, 0
2257 
    {
2258 
     COORD (0,80)
2259 
     VARIABLES
2260 
     {
2261 
      #DIRECTION="IN"
2262 
      #DOWNTO="1"
2263 
      #LENGTH="20"
2264 
      #MDA_RECORD_TOKEN="OTHER"
2265 
      #NAME="dmem_ctl_i(3:0)"
2266 
      #NUMBER="0"
2267 
      #VERILOG_TYPE="wire"
2268 
     }
2269 
     LINE  2, 0, 0
2270 
     {
2271 
      POINTS ( (0,0), (20,0) )
2272 
     }
2273 
    }
2274 
   }
2275 
  }
2276 
 }
2277 
 SYMBOL "#default" "dmem_ctl_reg_clr" "dmem_ctl_reg_clr"
2278 
 {
2279 
  HEADER
2280 
  {
2281 
   VARIABLES
2282 
   {
2283 
    #DESCRIPTION=""
2284 
    #LANGUAGE="VERILOG"
2285 
    #MODIFIED="1194390978"
2286 
   }
2287 
  }
2288 
  PAGE ""
2289 
  {
2290 
   PAGEHEADER
2291 
   {
2292 
    RECT (0,0,240,160)
2293 
    FREEID 10
2294 
   }
2295 
 
2296 
   BODY
2297 
   {
2298 
    RECT  1, -1, 0
2299 
    {
2300 
     VARIABLES
2301 
     {
2302 
      #OUTLINE_FILLING="1"
2303 
     }
2304 
     AREA (20,0,220,160)
2305 
    }
2306 
    TEXT  3, 0, 0
2307 
    {
2308 
     TEXT "$#NAME"
2309 
     RECT (25,30,60,54)
2310 
     ALIGN 4
2311 
     MARGINS (1,1)
2312 
     PARENT 2
2313 
    }
2314 
    TEXT  5, 0, 0
2315 
    {
2316 
     TEXT "$#NAME"
2317 
     RECT (48,30,215,54)
2318 
     ALIGN 6
2319 
     MARGINS (1,1)
2320 
     PARENT 4
2321 
    }
2322 
    TEXT  7, 0, 0
2323 
    {
2324 
     TEXT "$#NAME"
2325 
     RECT (25,70,60,94)
2326 
     ALIGN 4
2327 
     MARGINS (1,1)
2328 
     PARENT 6
2329 
    }
2330 
    TEXT  9, 0, 0
2331 
    {
2332 
     TEXT "$#NAME"
2333 
     RECT (25,110,192,134)
2334 
     ALIGN 4
2335 
     MARGINS (1,1)
2336 
     PARENT 8
2337 
    }
2338 
    PIN  2, 0, 0
2339 
    {
2340 
     COORD (0,40)
2341 
     VARIABLES
2342 
     {
2343 
      #DIRECTION="IN"
2344 
      #LENGTH="20"
2345 
      #MDA_RECORD_TOKEN="OTHER"
2346 
      #NAME="clk"
2347 
      #NUMBER="0"
2348 
      #VERILOG_TYPE="wire"
2349 
     }
2350 
     LINE  2, 0, 0
2351 
     {
2352 
      POINTS ( (0,0), (20,0) )
2353 
     }
2354 
    }
2355 
    PIN  4, 0, 0
2356 
    {
2357 
     COORD (240,40)
2358 
     VARIABLES
2359 
     {
2360 
      #DIRECTION="OUT"
2361 
      #DOWNTO="1"
2362 
      #LENGTH="20"
2363 
      #MDA_RECORD_TOKEN="OTHER"
2364 
      #NAME="dmem_ctl_o(3:0)"
2365 
      #NUMBER="0"
2366 
      #VERILOG_TYPE="reg"
2367 
     }
2368 
     LINE  2, 0, 0
2369 
     {
2370 
      POINTS ( (-20,0), (0,0) )
2371 
     }
2372 
    }
2373 
    PIN  6, 0, 0
2374 
    {
2375 
     COORD (0,80)
2376 
     VARIABLES
2377 
     {
2378 
      #DIRECTION="IN"
2379 
      #LENGTH="20"
2380 
      #MDA_RECORD_TOKEN="OTHER"
2381 
      #NAME="clr"
2382 
      #NUMBER="0"
2383 
      #VERILOG_TYPE="wire"
2384 
     }
2385 
     LINE  2, 0, 0
2386 
     {
2387 
      POINTS ( (0,0), (20,0) )
2388 
     }
2389 
    }
2390 
    PIN  8, 0, 0
2391 
    {
2392 
     COORD (0,120)
2393 
     VARIABLES
2394 
     {
2395 
      #DIRECTION="IN"
2396 
      #DOWNTO="1"
2397 
      #LENGTH="20"
2398 
      #MDA_RECORD_TOKEN="OTHER"
2399 
      #NAME="dmem_ctl_i(3:0)"
2400 
      #NUMBER="0"
2401 
      #VERILOG_TYPE="wire"
2402 
     }
2403 
     LINE  2, 0, 0
2404 
     {
2405 
      POINTS ( (0,0), (20,0) )
2406 
     }
2407 
    }
2408 
   }
2409 
  }
2410 
 }
2411 
 SYMBOL "#default" "muxb_ctl_reg_clr" "muxb_ctl_reg_clr"
2412 
 {
2413 
  HEADER
2414 
  {
2415 
   VARIABLES
2416 
   {
2417 
    #DESCRIPTION=""
2418 
    #LANGUAGE="VERILOG"
2419 
    #MODIFIED="1194391146"
2420 
   }
2421 
  }
2422 
  PAGE ""
2423 
  {
2424 
   PAGEHEADER
2425 
   {
2426 
    RECT (0,0,240,160)
2427 
    FREEID 10
2428 
   }
2429 
 
2430 
   BODY
2431 
   {
2432 
    RECT  1, -1, 0
2433 
    {
2434 
     VARIABLES
2435 
     {
2436 
      #OUTLINE_FILLING="1"
2437 
     }
2438 
     AREA (20,0,220,160)
2439 
    }
2440 
    TEXT  3, 0, 0
2441 
    {
2442 
     TEXT "$#NAME"
2443 
     RECT (25,30,60,54)
2444 
     ALIGN 4
2445 
     MARGINS (1,1)
2446 
     PARENT 2
2447 
    }
2448 
    TEXT  5, 0, 0
2449 
    {
2450 
     TEXT "$#NAME"
2451 
     RECT (48,30,215,54)
2452 
     ALIGN 6
2453 
     MARGINS (1,1)
2454 
     PARENT 4
2455 
    }
2456 
    TEXT  7, 0, 0
2457 
    {
2458 
     TEXT "$#NAME"
2459 
     RECT (25,70,60,94)
2460 
     ALIGN 4
2461 
     MARGINS (1,1)
2462 
     PARENT 6
2463 
    }
2464 
    TEXT  9, 0, 0
2465 
    {
2466 
     TEXT "$#NAME"
2467 
     RECT (25,110,192,134)
2468 
     ALIGN 4
2469 
     MARGINS (1,1)
2470 
     PARENT 8
2471 
    }
2472 
    PIN  2, 0, 0
2473 
    {
2474 
     COORD (0,40)
2475 
     VARIABLES
2476 
     {
2477 
      #DIRECTION="IN"
2478 
      #LENGTH="20"
2479 
      #MDA_RECORD_TOKEN="OTHER"
2480 
      #NAME="clk"
2481 
      #NUMBER="0"
2482 
      #VERILOG_TYPE="wire"
2483 
     }
2484 
     LINE  2, 0, 0
2485 
     {
2486 
      POINTS ( (0,0), (20,0) )
2487 
     }
2488 
    }
2489 
    PIN  4, 0, 0
2490 
    {
2491 
     COORD (240,40)
2492 
     VARIABLES
2493 
     {
2494 
      #DIRECTION="OUT"
2495 
      #DOWNTO="1"
2496 
      #LENGTH="20"
2497 
      #MDA_RECORD_TOKEN="OTHER"
2498 
      #NAME="muxb_ctl_o(1:0)"
2499 
      #NUMBER="0"
2500 
      #VERILOG_TYPE="reg"
2501 
     }
2502 
     LINE  2, 0, 0
2503 
     {
2504 
      POINTS ( (-20,0), (0,0) )
2505 
     }
2506 
    }
2507 
    PIN  6, 0, 0
2508 
    {
2509 
     COORD (0,80)
2510 
     VARIABLES
2511 
     {
2512 
      #DIRECTION="IN"
2513 
      #LENGTH="20"
2514 
      #MDA_RECORD_TOKEN="OTHER"
2515 
      #NAME="clr"
2516 
      #NUMBER="0"
2517 
      #VERILOG_TYPE="wire"
2518 
     }
2519 
     LINE  2, 0, 0
2520 
     {
2521 
      POINTS ( (0,0), (20,0) )
2522 
     }
2523 
    }
2524 
    PIN  8, 0, 0
2525 
    {
2526 
     COORD (0,120)
2527 
     VARIABLES
2528 
     {
2529 
      #DIRECTION="IN"
2530 
      #DOWNTO="1"
2531 
      #LENGTH="20"
2532 
      #MDA_RECORD_TOKEN="OTHER"
2533 
      #NAME="muxb_ctl_i(1:0)"
2534 
      #NUMBER="0"
2535 
      #VERILOG_TYPE="wire"
2536 
     }
2537 
     LINE  2, 0, 0
2538 
     {
2539 
      POINTS ( (0,0), (20,0) )
2540 
     }
2541 
    }
2542 
   }
2543 
  }
2544 
 }
2545 
 SYMBOL "#default" "muxa_ctl_reg_clr" "muxa_ctl_reg_clr"
2546 
 {
2547 
  HEADER
2548 
  {
2549 
   VARIABLES
2550 
   {
2551 
    #DESCRIPTION=""
2552 
    #LANGUAGE="VERILOG"
2553 
    #MODIFIED="1194391170"
2554 
   }
2555 
  }
2556 
  PAGE ""
2557 
  {
2558 
   PAGEHEADER
2559 
   {
2560 
    RECT (0,0,240,160)
2561 
    FREEID 10
2562 
   }
2563 
 
2564 
   BODY
2565 
   {
2566 
    RECT  1, -1, 0
2567 
    {
2568 
     VARIABLES
2569 
     {
2570 
      #OUTLINE_FILLING="1"
2571 
     }
2572 
     AREA (20,0,220,160)
2573 
    }
2574 
    TEXT  3, 0, 0
2575 
    {
2576 
     TEXT "$#NAME"
2577 
     RECT (25,30,60,54)
2578 
     ALIGN 4
2579 
     MARGINS (1,1)
2580 
     PARENT 2
2581 
    }
2582 
    TEXT  5, 0, 0
2583 
    {
2584 
     TEXT "$#NAME"
2585 
     RECT (48,30,215,54)
2586 
     ALIGN 6
2587 
     MARGINS (1,1)
2588 
     PARENT 4
2589 
    }
2590 
    TEXT  7, 0, 0
2591 
    {
2592 
     TEXT "$#NAME"
2593 
     RECT (25,70,60,94)
2594 
     ALIGN 4
2595 
     MARGINS (1,1)
2596 
     PARENT 6
2597 
    }
2598 
    TEXT  9, 0, 0
2599 
    {
2600 
     TEXT "$#NAME"
2601 
     RECT (25,110,192,134)
2602 
     ALIGN 4
2603 
     MARGINS (1,1)
2604 
     PARENT 8
2605 
    }
2606 
    PIN  2, 0, 0
2607 
    {
2608 
     COORD (0,40)
2609 
     VARIABLES
2610 
     {
2611 
      #DIRECTION="IN"
2612 
      #LENGTH="20"
2613 
      #MDA_RECORD_TOKEN="OTHER"
2614 
      #NAME="clk"
2615 
      #NUMBER="0"
2616 
      #VERILOG_TYPE="wire"
2617 
     }
2618 
     LINE  2, 0, 0
2619 
     {
2620 
      POINTS ( (0,0), (20,0) )
2621 
     }
2622 
    }
2623 
    PIN  4, 0, 0
2624 
    {
2625 
     COORD (240,40)
2626 
     VARIABLES
2627 
     {
2628 
      #DIRECTION="OUT"
2629 
      #DOWNTO="1"
2630 
      #LENGTH="20"
2631 
      #MDA_RECORD_TOKEN="OTHER"
2632 
      #NAME="muxa_ctl_o(1:0)"
2633 
      #NUMBER="0"
2634 
      #VERILOG_TYPE="reg"
2635 
     }
2636 
     LINE  2, 0, 0
2637 
     {
2638 
      POINTS ( (-20,0), (0,0) )
2639 
     }
2640 
    }
2641 
    PIN  6, 0, 0
2642 
    {
2643 
     COORD (0,80)
2644 
     VARIABLES
2645 
     {
2646 
      #DIRECTION="IN"
2647 
      #LENGTH="20"
2648 
      #MDA_RECORD_TOKEN="OTHER"
2649 
      #NAME="clr"
2650 
      #NUMBER="0"
2651 
      #VERILOG_TYPE="wire"
2652 
     }
2653 
     LINE  2, 0, 0
2654 
     {
2655 
      POINTS ( (0,0), (20,0) )
2656 
     }
2657 
    }
2658 
    PIN  8, 0, 0
2659 
    {
2660 
     COORD (0,120)
2661 
     VARIABLES
2662 
     {
2663 
      #DIRECTION="IN"
2664 
      #DOWNTO="1"
2665 
      #LENGTH="20"
2666 
      #MDA_RECORD_TOKEN="OTHER"
2667 
      #NAME="muxa_ctl_i(1:0)"
2668 
      #NUMBER="0"
2669 
      #VERILOG_TYPE="wire"
2670 
     }
2671 
     LINE  2, 0, 0
2672 
     {
2673 
      POINTS ( (0,0), (20,0) )
2674 
     }
2675 
    }
2676 
   }
2677 
  }
2678 
 }
2679 
 SYMBOL "#default" "wb_we_reg" "wb_we_reg"
2680 
 {
2681 
  HEADER
2682 
  {
2683 
   VARIABLES
2684 
   {
2685 
    #DESCRIPTION=""
2686 
    #LANGUAGE="VERILOG"
2687 
    #MODIFIED="1005227680"
2688 
   }
2689 
  }
2690 
  PAGE ""
2691 
  {
2692 
   PAGEHEADER
2693 
   {
2694 
    RECT (0,0,220,120)
2695 
    FREEID 8
2696 
   }
2697 
 
2698 
   BODY
2699 
   {
2700 
    RECT  1, -1, 0
2701 
    {
2702 
     VARIABLES
2703 
     {
2704 
      #OUTLINE_FILLING="1"
2705 
     }
2706 
     AREA (20,0,200,120)
2707 
    }
2708 
    TEXT  3, 0, 0
2709 
    {
2710 
     TEXT "$#NAME"
2711 
     RECT (25,30,60,54)
2712 
     ALIGN 4
2713 
     MARGINS (1,1)
2714 
     PARENT 2
2715 
    }
2716 
    TEXT  5, 0, 0
2717 
    {
2718 
     TEXT "$#NAME"
2719 
     RECT (61,30,195,54)
2720 
     ALIGN 6
2721 
     MARGINS (1,1)
2722 
     PARENT 4
2723 
    }
2724 
    TEXT  7, 0, 0
2725 
    {
2726 
     TEXT "$#NAME"
2727 
     RECT (25,70,159,94)
2728 
     ALIGN 4
2729 
     MARGINS (1,1)
2730 
     PARENT 6
2731 
    }
2732 
    PIN  2, 0, 0
2733 
    {
2734 
     COORD (0,40)
2735 
     VARIABLES
2736 
     {
2737 
      #DIRECTION="IN"
2738 
      #LENGTH="20"
2739 
      #MDA_RECORD_TOKEN="OTHER"
2740 
      #NAME="clk"
2741 
      #NUMBER="0"
2742 
      #VERILOG_TYPE="wire"
2743 
     }
2744 
     LINE  2, 0, 0
2745 
     {
2746 
      POINTS ( (0,0), (20,0) )
2747 
     }
2748 
    }
2749 
    PIN  4, 0, 0
2750 
    {
2751 
     COORD (220,40)
2752 
     VARIABLES
2753 
     {
2754 
      #DIRECTION="OUT"
2755 
      #DOWNTO="1"
2756 
      #LENGTH="20"
2757 
      #MDA_RECORD_TOKEN="OTHER"
2758 
      #NAME="wb_we_o(0:0)"
2759 
      #NUMBER="0"
2760 
      #VERILOG_TYPE="reg"
2761 
     }
2762 
     LINE  2, 0, 0
2763 
     {
2764 
      POINTS ( (-20,0), (0,0) )
2765 
     }
2766 
    }
2767 
    PIN  6, 0, 0
2768 
    {
2769 
     COORD (0,80)
2770 
     VARIABLES
2771 
     {
2772 
      #DIRECTION="IN"
2773 
      #DOWNTO="1"
2774 
      #LENGTH="20"
2775 
      #MDA_RECORD_TOKEN="OTHER"
2776 
      #NAME="wb_we_i(0:0)"
2777 
      #NUMBER="0"
2778 
      #VERILOG_TYPE="wire"
2779 
     }
2780 
     LINE  2, 0, 0
2781 
     {
2782 
      POINTS ( (0,0), (20,0) )
2783 
     }
2784 
    }
2785 
   }
2786 
  }
2787 
 }
2788 
 SYMBOL "#default" "wb_mux_ctl_reg" "wb_mux_ctl_reg"
2789 
 {
2790 
  HEADER
2791 
  {
2792 
   VARIABLES
2793 
   {
2794 
    #DESCRIPTION=""
2795 
    #LANGUAGE="VERILOG"
2796 
    #MODIFIED="1005227763"
2797 
   }
2798 
  }
2799 
  PAGE ""
2800 
  {
2801 
   PAGEHEADER
2802 
   {
2803 
    RECT (0,0,260,120)
2804 
    FREEID 8
2805 
   }
2806 
 
2807 
   BODY
2808 
   {
2809 
    RECT  1, -1, 0
2810 
    {
2811 
     VARIABLES
2812 
     {
2813 
      #OUTLINE_FILLING="1"
2814 
     }
2815 
     AREA (20,0,240,120)
2816 
    }
2817 
    TEXT  3, 0, 0
2818 
    {
2819 
     TEXT "$#NAME"
2820 
     RECT (25,30,60,54)
2821 
     ALIGN 4
2822 
     MARGINS (1,1)
2823 
     PARENT 2
2824 
    }
2825 
    TEXT  5, 0, 0
2826 
    {
2827 
     TEXT "$#NAME"
2828 
     RECT (46,30,235,54)
2829 
     ALIGN 6
2830 
     MARGINS (1,1)
2831 
     PARENT 4
2832 
    }
2833 
    TEXT  7, 0, 0
2834 
    {
2835 
     TEXT "$#NAME"
2836 
     RECT (25,70,214,94)
2837 
     ALIGN 4
2838 
     MARGINS (1,1)
2839 
     PARENT 6
2840 
    }
2841 
    PIN  2, 0, 0
2842 
    {
2843 
     COORD (0,40)
2844 
     VARIABLES
2845 
     {
2846 
      #DIRECTION="IN"
2847 
      #LENGTH="20"
2848 
      #MDA_RECORD_TOKEN="OTHER"
2849 
      #NAME="clk"
2850 
      #NUMBER="0"
2851 
      #VERILOG_TYPE="wire"
2852 
     }
2853 
     LINE  2, 0, 0
2854 
     {
2855 
      POINTS ( (0,0), (20,0) )
2856 
     }
2857 
    }
2858 
    PIN  4, 0, 0
2859 
    {
2860 
     COORD (260,40)
2861 
     VARIABLES
2862 
     {
2863 
      #DIRECTION="OUT"
2864 
      #DOWNTO="1"
2865 
      #LENGTH="20"
2866 
      #MDA_RECORD_TOKEN="OTHER"
2867 
      #NAME="wb_mux_ctl_o(0:0)"
2868 
      #NUMBER="0"
2869 
      #VERILOG_TYPE="reg"
2870 
     }
2871 
     LINE  2, 0, 0
2872 
     {
2873 
      POINTS ( (-20,0), (0,0) )
2874 
     }
2875 
    }
2876 
    PIN  6, 0, 0
2877 
    {
2878 
     COORD (0,80)
2879 
     VARIABLES
2880 
     {
2881 
      #DIRECTION="IN"
2882 
      #DOWNTO="1"
2883 
      #LENGTH="20"
2884 
      #MDA_RECORD_TOKEN="OTHER"
2885 
      #NAME="wb_mux_ctl_i(0:0)"
2886 
      #NUMBER="0"
2887 
      #VERILOG_TYPE="wire"
2888 
     }
2889 
     LINE  2, 0, 0
2890 
     {
2891 
      POINTS ( (0,0), (20,0) )
2892 
     }
2893 
    }
2894 
   }
2895 
  }
2896 
 }
2897 
 SYMBOL "#default" "wb_we_reg_clr" "wb_we_reg_clr"
2898 
 {
2899 
  HEADER
2900 
  {
2901 
   VARIABLES
2902 
   {
2903 
    #DESCRIPTION=""
2904 
    #LANGUAGE="VERILOG"
2905 
    #MODIFIED="1005233069"
2906 
   }
2907 
  }
2908 
  PAGE ""
2909 
  {
2910 
   PAGEHEADER
2911 
   {
2912 
    RECT (0,0,220,160)
2913 
    FREEID 10
2914 
   }
2915 
 
2916 
   BODY
2917 
   {
2918 
    RECT  1, -1, 0
2919 
    {
2920 
     VARIABLES
2921 
     {
2922 
      #OUTLINE_FILLING="1"
2923 
     }
2924 
     AREA (20,0,200,160)
2925 
    }
2926 
    TEXT  3, 0, 0
2927 
    {
2928 
     TEXT "$#NAME"
2929 
     RECT (25,30,60,54)
2930 
     ALIGN 4
2931 
     MARGINS (1,1)
2932 
     PARENT 2
2933 
    }
2934 
    TEXT  5, 0, 0
2935 
    {
2936 
     TEXT "$#NAME"
2937 
     RECT (61,30,195,54)
2938 
     ALIGN 6
2939 
     MARGINS (1,1)
2940 
     PARENT 4
2941 
    }
2942 
    TEXT  7, 0, 0
2943 
    {
2944 
     TEXT "$#NAME"
2945 
     RECT (25,70,60,94)
2946 
     ALIGN 4
2947 
     MARGINS (1,1)
2948 
     PARENT 6
2949 
    }
2950 
    TEXT  9, 0, 0
2951 
    {
2952 
     TEXT "$#NAME"
2953 
     RECT (25,110,159,134)
2954 
     ALIGN 4
2955 
     MARGINS (1,1)
2956 
     PARENT 8
2957 
    }
2958 
    PIN  2, 0, 0
2959 
    {
2960 
     COORD (0,40)
2961 
     VARIABLES
2962 
     {
2963 
      #DIRECTION="IN"
2964 
      #LENGTH="20"
2965 
      #MDA_RECORD_TOKEN="OTHER"
2966 
      #NAME="clk"
2967 
      #NUMBER="0"
2968 
      #VERILOG_TYPE="wire"
2969 
     }
2970 
     LINE  2, 0, 0
2971 
     {
2972 
      POINTS ( (0,0), (20,0) )
2973 
     }
2974 
    }
2975 
    PIN  4, 0, 0
2976 
    {
2977 
     COORD (220,40)
2978 
     VARIABLES
2979 
     {
2980 
      #DIRECTION="OUT"
2981 
      #DOWNTO="1"
2982 
      #LENGTH="20"
2983 
      #MDA_RECORD_TOKEN="OTHER"
2984 
      #NAME="wb_we_o(0:0)"
2985 
      #NUMBER="0"
2986 
      #VERILOG_TYPE="reg"
2987 
     }
2988 
     LINE  2, 0, 0
2989 
     {
2990 
      POINTS ( (-20,0), (0,0) )
2991 
     }
2992 
    }
2993 
    PIN  6, 0, 0
2994 
    {
2995 
     COORD (0,80)
2996 
     VARIABLES
2997 
     {
2998 
      #DIRECTION="IN"
2999 
      #LENGTH="20"
3000 
      #MDA_RECORD_TOKEN="OTHER"
3001 
      #NAME="clr"
3002 
      #NUMBER="0"
3003 
      #VERILOG_TYPE="wire"
3004 
     }
3005 
     LINE  2, 0, 0
3006 
     {
3007 
      POINTS ( (0,0), (20,0) )
3008 
     }
3009 
    }
3010 
    PIN  8, 0, 0
3011 
    {
3012 
     COORD (0,120)
3013 
     VARIABLES
3014 
     {
3015 
      #DIRECTION="IN"
3016 
      #DOWNTO="1"
3017 
      #LENGTH="20"
3018 
      #MDA_RECORD_TOKEN="OTHER"
3019 
      #NAME="wb_we_i(0:0)"
3020 
      #NUMBER="0"
3021 
      #VERILOG_TYPE="wire"
3022 
     }
3023 
     LINE  2, 0, 0
3024 
     {
3025 
      POINTS ( (0,0), (20,0) )
3026 
     }
3027 
    }
3028 
   }
3029 
  }
3030 
 }
3031 
}
3032 
 
3033 
PAGE ""
3034 
{
3035 
 PAGEHEADER
3036 
 {
3037 
  PAGESIZE (3307,3338)
3038 
  MARGINS (79,79,79,79)
3039 
  RECT (0,0,100,200)
3040 
 }
3041 
 
3042 
 BODY
3043 
 {
3044 
  INSTANCE  231, 0, 0
3045 
  {
3046 
   VARIABLES
3047 
   {
3048 
    #COMPONENT="Input"
3049 
    #LIBRARY="#terminals"
3050 
    #REFERENCE="clk"
3051 
    #SYMBOL="Input"
3052 
   }
3053 
   COORD (440,420)
3054 
   VERTEXES ( (2,6465) )
3055 
  }
3056 
  TEXT  232, 0, 0
3057 
  {
3058 
   TEXT "$#REFERENCE"
3059 
   RECT (336,403,389,438)
3060 
   ALIGN 6
3061 
   MARGINS (1,1)
3062 
   PARENT 231
3063 
  }
3064 
  INSTANCE  379, 0, 0
3065 
  {
3066 
   VARIABLES
3067 
   {
3068 
    #COMPONENT="Input"
3069 
    #LIBRARY="#terminals"
3070 
    #REFERENCE="id2ra_ctl_clr"
3071 
    #SYMBOL="Input"
3072 
   }
3073 
   COORD (440,380)
3074 
   VERTEXES ( (2,6480) )
3075 
  }
3076 
  TEXT  380, 0, 0
3077 
  {
3078 
   TEXT "$#REFERENCE"
3079 
   RECT (166,363,389,398)
3080 
   ALIGN 6
3081 
   MARGINS (1,1)
3082 
   PARENT 379
3083 
  }
3084 
  INSTANCE  384, 0, 0
3085 
  {
3086 
   VARIABLES
3087 
   {
3088 
    #COMPONENT="Input"
3089 
    #LIBRARY="#terminals"
3090 
    #REFERENCE="id2ra_ctl_cls"
3091 
    #SYMBOL="Input"
3092 
   }
3093 
   COORD (440,340)
3094 
   VERTEXES ( (2,6548) )
3095 
  }
3096 
  TEXT  385, 0, 0
3097 
  {
3098 
   TEXT "$#REFERENCE"
3099 
   RECT (166,323,389,358)
3100 
   ALIGN 6
3101 
   MARGINS (1,1)
3102 
   PARENT 384
3103 
  }
3104 
  INSTANCE  389, 0, 0
3105 
  {
3106 
   VARIABLES
3107 
   {
3108 
    #COMPONENT="Input"
3109 
    #LIBRARY="#terminals"
3110 
    #REFERENCE="ra2ex_ctl_clr"
3111 
    #SYMBOL="Input"
3112 
   }
3113 
   COORD (440,300)
3114 
   VERTEXES ( (2,6467) )
3115 
  }
3116 
  TEXT  390, 0, 0
3117 
  {
3118 
   TEXT "$#REFERENCE"
3119 
   RECT (166,283,389,318)
3120 
   ALIGN 6
3121 
   MARGINS (1,1)
3122 
   PARENT 389
3123 
  }
3124 
  INSTANCE  750, 0, 0
3125 
  {
3126 
   VARIABLES
3127 
   {
3128 
    #COMPONENT="BusInput"
3129 
    #LIBRARY="#terminals"
3130 
    #REFERENCE="wb_we_i(0:0)"
3131 
    #SYMBOL="BusInput"
3132 
    #VERILOG_TYPE="wire"
3133 
   }
3134 
   COORD (460,640)
3135 
   VERTEXES ( (2,6367) )
3136 
  }
3137 
  TEXT  751, 0, 0
3138 
  {
3139 
   TEXT "$#REFERENCE"
3140 
   RECT (203,623,409,658)
3141 
   ALIGN 6
3142 
   MARGINS (1,1)
3143 
   PARENT 750
3144 
  }
3145 
  INSTANCE  755, 0, 0
3146 
  {
3147 
   VARIABLES
3148 
   {
3149 
    #COMPONENT="BusInput"
3150 
    #LIBRARY="#terminals"
3151 
    #REFERENCE="wb_mux_ctl_i(0:0)"
3152 
    #SYMBOL="BusInput"
3153 
    #VERILOG_TYPE="wire"
3154 
   }
3155 
   COORD (460,900)
3156 
   VERTEXES ( (2,6377) )
3157 
  }
3158 
  TEXT  756, 0, 0
3159 
  {
3160 
   TEXT "$#REFERENCE"
3161 
   RECT (118,883,409,918)
3162 
   ALIGN 6
3163 
   MARGINS (1,1)
3164 
   PARENT 755
3165 
  }
3166 
  INSTANCE  760, 0, 0
3167 
  {
3168 
   VARIABLES
3169 
   {
3170 
    #COMPONENT="BusInput"
3171 
    #LIBRARY="#terminals"
3172 
    #REFERENCE="alu_func_i(4:0)"
3173 
    #SYMBOL="BusInput"
3174 
   }
3175 
   COORD (460,1240)
3176 
   VERTEXES ( (2,6383) )
3177 
  }
3178 
  TEXT  761, 0, 0
3179 
  {
3180 
   TEXT "$#REFERENCE"
3181 
   RECT (152,1223,409,1258)
3182 
   ALIGN 6
3183 
   MARGINS (1,1)
3184 
   PARENT 760
3185 
  }
3186 
  INSTANCE  765, 0, 0
3187 
  {
3188 
   VARIABLES
3189 
   {
3190 
    #COMPONENT="BusInput"
3191 
    #LIBRARY="#terminals"
3192 
    #REFERENCE="muxa_ctl_i(1:0)"
3193 
    #SYMBOL="BusInput"
3194 
    #VERILOG_TYPE="wire"
3195 
   }
3196 
   COORD (480,1860)
3197 
   VERTEXES ( (2,6389) )
3198 
  }
3199 
  TEXT  766, 0, 0
3200 
  {
3201 
   TEXT "$#REFERENCE"
3202 
   RECT (172,1843,429,1878)
3203 
   ALIGN 6
3204 
   MARGINS (1,1)
3205 
   PARENT 765
3206 
  }
3207 
  INSTANCE  770, 0, 0
3208 
  {
3209 
   VARIABLES
3210 
   {
3211 
    #COMPONENT="BusInput"
3212 
    #LIBRARY="#terminals"
3213 
    #REFERENCE="muxb_ctl_i(1:0)"
3214 
    #SYMBOL="BusInput"
3215 
    #VERILOG_TYPE="wire"
3216 
   }
3217 
   COORD (460,1620)
3218 
   VERTEXES ( (2,6386) )
3219 
  }
3220 
  TEXT  771, 0, 0
3221 
  {
3222 
   TEXT "$#REFERENCE"
3223 
   RECT (152,1603,409,1638)
3224 
   ALIGN 6
3225 
   MARGINS (1,1)
3226 
   PARENT 770
3227 
  }
3228 
  INSTANCE  775, 0, 0
3229 
  {
3230 
   VARIABLES
3231 
   {
3232 
    #COMPONENT="BusInput"
3233 
    #LIBRARY="#terminals"
3234 
    #REFERENCE="alu_we_i(0:0)"
3235 
    #SYMBOL="BusInput"
3236 
   }
3237 
   COORD (460,1960)
3238 
   VERTEXES ( (2,6392) )
3239 
  }
3240 
  TEXT  776, 0, 0
3241 
  {
3242 
   TEXT "$#REFERENCE"
3243 
   RECT (186,1943,409,1978)
3244 
   ALIGN 6
3245 
   MARGINS (1,1)
3246 
   PARENT 775
3247 
  }
3248 
  INSTANCE  780, 0, 0
3249 
  {
3250 
   VARIABLES
3251 
   {
3252 
    #COMPONENT="BusInput"
3253 
    #LIBRARY="#terminals"
3254 
    #REFERENCE="ext_ctl_i(2:0)"
3255 
    #SYMBOL="BusInput"
3256 
   }
3257 
   COORD (460,2320)
3258 
   VERTEXES ( (2,6395) )
3259 
  }
3260 
  TEXT  781, 0, 0
3261 
  {
3262 
   TEXT "$#REFERENCE"
3263 
   RECT (169,2303,409,2338)
3264 
   ALIGN 6
3265 
   MARGINS (1,1)
3266 
   PARENT 780
3267 
  }
3268 
  INSTANCE  785, 0, 0
3269 
  {
3270 
   VARIABLES
3271 
   {
3272 
    #COMPONENT="BusInput"
3273 
    #LIBRARY="#terminals"
3274 
    #REFERENCE="cmp_ctl_i(2:0)"
3275 
    #SYMBOL="BusInput"
3276 
    #VERILOG_TYPE="wire"
3277 
   }
3278 
   COORD (460,2560)
3279 
   VERTEXES ( (2,6398) )
3280 
  }
3281 
  TEXT  786, 0, 0
3282 
  {
3283 
   TEXT "$#REFERENCE"
3284 
   RECT (169,2543,409,2578)
3285 
   ALIGN 6
3286 
   MARGINS (1,1)
3287 
   PARENT 785
3288 
  }
3289 
  INSTANCE  790, 0, 0
3290 
  {
3291 
   VARIABLES
3292 
   {
3293 
    #COMPONENT="BusInput"
3294 
    #LIBRARY="#terminals"
3295 
    #REFERENCE="rd_sel_i(1:0)"
3296 
    #SYMBOL="BusInput"
3297 
    #VERILOG_TYPE="wire"
3298 
   }
3299 
   COORD (460,2800)
3300 
   VERTEXES ( (2,6401) )
3301 
  }
3302 
  TEXT  791, 0, 0
3303 
  {
3304 
   TEXT "$#REFERENCE"
3305 
   RECT (186,2783,409,2818)
3306 
   ALIGN 6
3307 
   MARGINS (1,1)
3308 
   PARENT 790
3309 
  }
3310 
  INSTANCE  792, 0, 0
3311 
  {
3312 
   VARIABLES
3313 
   {
3314 
    #COMPONENT="BusInput"
3315 
    #LIBRARY="#terminals"
3316 
    #REFERENCE="dmem_ctl_i(3:0)"
3317 
    #SYMBOL="BusInput"
3318 
    #VERILOG_TYPE="wire"
3319 
   }
3320 
   COORD (460,1140)
3321 
   VERTEXES ( (2,6380) )
3322 
  }
3323 
  TEXT  793, 0, 0
3324 
  {
3325 
   TEXT "$#REFERENCE"
3326 
   RECT (152,1123,409,1158)
3327 
   ALIGN 6
3328 
   MARGINS (1,1)
3329 
   PARENT 792
3330 
  }
3331 
  INSTANCE  874, 0, 0
3332 
  {
3333 
   VARIABLES
3334 
   {
3335 
    #COMPONENT="BusInput"
3336 
    #LIBRARY="#terminals"
3337 
    #REFERENCE="pc_gen_ctl_i(2:0)"
3338 
    #SYMBOL="BusInput"
3339 
    #VERILOG_TYPE="wire"
3340 
   }
3341 
   COORD (460,3060)
3342 
   VERTEXES ( (2,6404) )
3343 
  }
3344 
  TEXT  875, 0, 0
3345 
  {
3346 
   TEXT "$#REFERENCE"
3347 
   RECT (118,3043,409,3078)
3348 
   ALIGN 6
3349 
   MARGINS (1,1)
3350 
   PARENT 874
3351 
  }
3352 
  INSTANCE  885, 0, 0
3353 
  {
3354 
   VARIABLES
3355 
   {
3356 
    #COMPONENT="BusOutput"
3357 
    #LIBRARY="#terminals"
3358 
    #REFERENCE="wb_we_o(0:0)"
3359 
    #SYMBOL="BusOutput"
3360 
    #VERILOG_TYPE="wire"
3361 
   }
3362 
   COORD (2800,440)
3363 
   VERTEXES ( (2,7085) )
3364 
  }
3365 
  TEXT  886, 0, 0
3366 
  {
3367 
   TEXT "$#REFERENCE"
3368 
   RECT (2852,423,3058,458)
3369 
   ALIGN 4
3370 
   MARGINS (1,1)
3371 
   PARENT 885
3372 
  }
3373 
  INSTANCE  890, 0, 0
3374 
  {
3375 
   VARIABLES
3376 
   {
3377 
    #COMPONENT="BusOutput"
3378 
    #LIBRARY="#terminals"
3379 
    #REFERENCE="wb_mux_ctl_o(0:0)"
3380 
    #SYMBOL="BusOutput"
3381 
   }
3382 
   COORD (2820,740)
3383 
   VERTEXES ( (2,7055) )
3384 
  }
3385 
  TEXT  891, 0, 0
3386 
  {
3387 
   TEXT "$#REFERENCE"
3388 
   RECT (2872,723,3163,758)
3389 
   ALIGN 4
3390 
   MARGINS (1,1)
3391 
   PARENT 890
3392 
  }
3393 
  INSTANCE  895, 0, 0
3394 
  {
3395 
   VARIABLES
3396 
   {
3397 
    #COMPONENT="BusOutput"
3398 
    #LIBRARY="#terminals"
3399 
    #REFERENCE="dmem_ctl_o(3:0)"
3400 
    #SYMBOL="BusOutput"
3401 
    #VERILOG_TYPE="wire"
3402 
   }
3403 
   COORD (2360,1060)
3404 
   VERTEXES ( (2,6677) )
3405 
  }
3406 
  TEXT  896, 0, 0
3407 
  {
3408 
   TEXT "$#REFERENCE"
3409 
   RECT (2412,1043,2669,1078)
3410 
   ALIGN 4
3411 
   MARGINS (1,1)
3412 
   PARENT 895
3413 
  }
3414 
  INSTANCE  935, 0, 0
3415 
  {
3416 
   VARIABLES
3417 
   {
3418 
    #COMPONENT="BusOutput"
3419 
    #LIBRARY="#terminals"
3420 
    #REFERENCE="alu_func_o(4:0)"
3421 
    #SYMBOL="BusOutput"
3422 
    #VERILOG_TYPE="wire"
3423 
   }
3424 
   COORD (1740,1280)
3425 
   VERTEXES ( (2,6422) )
3426 
  }
3427 
  TEXT  936, 0, 0
3428 
  {
3429 
   TEXT "$#REFERENCE"
3430 
   RECT (1792,1263,2049,1298)
3431 
   ALIGN 4
3432 
   MARGINS (1,1)
3433 
   PARENT 935
3434 
  }
3435 
  INSTANCE  940, 0, 0
3436 
  {
3437 
   VARIABLES
3438 
   {
3439 
    #COMPONENT="BusOutput"
3440 
    #LIBRARY="#terminals"
3441 
    #REFERENCE="muxb_ctl_o(1:0)"
3442 
    #SYMBOL="BusOutput"
3443 
    #VERILOG_TYPE="wire"
3444 
   }
3445 
   COORD (1740,1560)
3446 
   VERTEXES ( (2,6419) )
3447 
  }
3448 
  TEXT  941, 0, 0
3449 
  {
3450 
   TEXT "$#REFERENCE"
3451 
   RECT (1792,1543,2049,1578)
3452 
   ALIGN 4
3453 
   MARGINS (1,1)
3454 
   PARENT 940
3455 
  }
3456 
  INSTANCE  942, 0, 0
3457 
  {
3458 
   VARIABLES
3459 
   {
3460 
    #COMPONENT="BusOutput"
3461 
    #LIBRARY="#terminals"
3462 
    #REFERENCE="alu_we_o(0:0)"
3463 
    #SYMBOL="BusOutput"
3464 
    #VERILOG_TYPE="wire"
3465 
   }
3466 
   COORD (2280,1940)
3467 
   VERTEXES ( (2,7411) )
3468 
  }
3469 
  TEXT  943, 0, 0
3470 
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  WIRE  4844, 0, 0
4098 
  {
4099 
   NET 4710
4100 
   VTX 4842, 4829
4101 
  }
4102 
  VTX  4845, 0, 0
4103 
  {
4104 
   COORD (660,2080)
4105 
  }
4106 
  VTX  4846, 0, 0
4107 
  {
4108 
   COORD (600,2080)
4109 
  }
4110 
  WIRE  4847, 0, 0
4111 
  {
4112 
   NET 4710
4113 
   VTX 4845, 4846
4114 
  }
4115 
  WIRE  4848, 0, 0
4116 
  {
4117 
   NET 4710
4118 
   VTX 4846, 4842
4119 
  }
4120 
  VTX  4849, 0, 0
4121 
  {
4122 
   COORD (680,2280)
4123 
  }
4124 
  VTX  4850, 0, 0
4125 
  {
4126 
   COORD (600,2280)
4127 
  }
4128 
  WIRE  4851, 0, 0
4129 
  {
4130 
   NET 4710
4131 
   VTX 4849, 4850
4132 
  }
4133 
  WIRE  4852, 0, 0
4134 
  {
4135 
   NET 4710
4136 
   VTX 4850, 4846
4137 
  }
4138 
  VTX  4853, 0, 0
4139 
  {
4140 
   COORD (680,2520)
4141 
  }
4142 
  VTX  4854, 0, 0
4143 
  {
4144 
   COORD (600,2520)
4145 
  }
4146 
  WIRE  4855, 0, 0
4147 
  {
4148 
   NET 4710
4149 
   VTX 4853, 4854
4150 
  }
4151 
  WIRE  4856, 0, 0
4152 
  {
4153 
   NET 4710
4154 
   VTX 4854, 4850
4155 
  }
4156 
  VTX  4863, 0, 0
4157 
  {
4158 
   COORD (680,2760)
4159 
  }
4160 
  VTX  4864, 0, 0
4161 
  {
4162 
   COORD (600,2760)
4163 
  }
4164 
  WIRE  4865, 0, 0
4165 
  {
4166 
   NET 4710
4167 
   VTX 4863, 4864
4168 
  }
4169 
  WIRE  4866, 0, 0
4170 
  {
4171 
   NET 4710
4172 
   VTX 4864, 4854
4173 
  }
4174 
  VTX  4867, 0, 0
4175 
  {
4176 
   COORD (680,3020)
4177 
  }
4178 
  VTX  4868, 0, 0
4179 
  {
4180 
   COORD (600,3020)
4181 
  }
4182 
  WIRE  4869, 0, 0
4183 
  {
4184 
   NET 4710
4185 
   VTX 4867, 4868
4186 
  }
4187 
  WIRE  4870, 0, 0
4188 
  {
4189 
   NET 4710
4190 
   VTX 4868, 4864
4191 
  }
4192 
  VTX  4871, 0, 0
4193 
  {
4194 
   COORD (640,420)
4195 
  }
4196 
  VTX  4872, 0, 0
4197 
  {
4198 
   COORD (680,520)
4199 
  }
4200 
  VTX  4876, 0, 0
4201 
  {
4202 
   COORD (640,520)
4203 
  }
4204 
  WIRE  4877, 0, 0
4205 
  {
4206 
   NET 7320
4207 
   VTX 4871, 4876
4208 
  }
4209 
  WIRE  4878, 0, 0
4210 
  {
4211 
   NET 7320
4212 
   VTX 4876, 4872
4213 
  }
4214 
  VTX  4880, 0, 0
4215 
  {
4216 
   COORD (680,780)
4217 
  }
4218 
  VTX  4881, 0, 0
4219 
  {
4220 
   COORD (640,780)
4221 
  }
4222 
  WIRE  4882, 0, 0
4223 
  {
4224 
   NET 7320
4225 
   VTX 4876, 4881
4226 
  }
4227 
  WIRE  4883, 0, 0
4228 
  {
4229 
   NET 7320
4230 
   VTX 4881, 4880
4231 
  }
4232 
  VTX  4884, 0, 0
4233 
  {
4234 
   COORD (680,1020)
4235 
  }
4236 
  VTX  4885, 0, 0
4237 
  {
4238 
   COORD (640,1020)
4239 
  }
4240 
  WIRE  4886, 0, 0
4241 
  {
4242 
   NET 7320
4243 
   VTX 4881, 4885
4244 
  }
4245 
  WIRE  4887, 0, 0
4246 
  {
4247 
   NET 7320
4248 
   VTX 4885, 4884
4249 
  }
4250 
  VTX  4888, 0, 0
4251 
  {
4252 
   COORD (680,1500)
4253 
  }
4254 
  VTX  4889, 0, 0
4255 
  {
4256 
   COORD (640,1500)
4257 
  }
4258 
  WIRE  4891, 0, 0
4259 
  {
4260 
   NET 7320
4261 
   VTX 4889, 4888
4262 
  }
4263 
  VTX  4892, 0, 0
4264 
  {
4265 
   COORD (660,1740)
4266 
  }
4267 
  VTX  4893, 0, 0
4268 
  {
4269 
   COORD (640,1740)
4270 
  }
4271 
  WIRE  4894, 0, 0
4272 
  {
4273 
   NET 7320
4274 
   VTX 4889, 4893
4275 
  }
4276 
  WIRE  4895, 0, 0
4277 
  {
4278 
   NET 7320
4279 
   VTX 4893, 4892
4280 
  }
4281 
  VTX  4896, 0, 0
4282 
  {
4283 
   COORD (660,2000)
4284 
  }
4285 
  VTX  4897, 0, 0
4286 
  {
4287 
   COORD (640,2000)
4288 
  }
4289 
  WIRE  4898, 0, 0
4290 
  {
4291 
   NET 7320
4292 
   VTX 4893, 4897
4293 
  }
4294 
  WIRE  4899, 0, 0
4295 
  {
4296 
   NET 7320
4297 
   VTX 4897, 4896
4298 
  }
4299 
  VTX  4900, 0, 0
4300 
  {
4301 
   COORD (680,2200)
4302 
  }
4303 
  VTX  4901, 0, 0
4304 
  {
4305 
   COORD (640,2200)
4306 
  }
4307 
  WIRE  4902, 0, 0
4308 
  {
4309 
   NET 7320
4310 
   VTX 4897, 4901
4311 
  }
4312 
  WIRE  4903, 0, 0
4313 
  {
4314 
   NET 7320
4315 
   VTX 4901, 4900
4316 
  }
4317 
  VTX  4904, 0, 0
4318 
  {
4319 
   COORD (680,2440)
4320 
  }
4321 
  VTX  4905, 0, 0
4322 
  {
4323 
   COORD (640,2440)
4324 
  }
4325 
  WIRE  4906, 0, 0
4326 
  {
4327 
   NET 7320
4328 
   VTX 4901, 4905
4329 
  }
4330 
  WIRE  4907, 0, 0
4331 
  {
4332 
   NET 7320
4333 
   VTX 4905, 4904
4334 
  }
4335 
  VTX  4908, 0, 0
4336 
  {
4337 
   COORD (680,2680)
4338 
  }
4339 
  VTX  4909, 0, 0
4340 
  {
4341 
   COORD (640,2680)
4342 
  }
4343 
  WIRE  4910, 0, 0
4344 
  {
4345 
   NET 7320
4346 
   VTX 4905, 4909
4347 
  }
4348 
  WIRE  4911, 0, 0
4349 
  {
4350 
   NET 7320
4351 
   VTX 4909, 4908
4352 
  }
4353 
  VTX  4912, 0, 0
4354 
  {
4355 
   COORD (680,2940)
4356 
  }
4357 
  VTX  4913, 0, 0
4358 
  {
4359 
   COORD (640,2940)
4360 
  }
4361 
  WIRE  4914, 0, 0
4362 
  {
4363 
   NET 7320
4364 
   VTX 4909, 4913
4365 
  }
4366 
  WIRE  4915, 0, 0
4367 
  {
4368 
   NET 7320
4369 
   VTX 4913, 4912
4370 
  }
4371 
  VTX  4916, 0, 0
4372 
  {
4373 
   COORD (940,2940)
4374 
  }
4375 
  VTX  4917, 0, 0
4376 
  {
4377 
   COORD (1100,2940)
4378 
  }
4379 
  NET BUS  4918, 0, 0
4380 
  BUS  4919, 0, 0
4381 
  {
4382 
   NET 4918
4383 
   VTX 4916, 4917
4384 
  }
4385 
  NET BUS  4922, 0, 0
4386 
  NET BUS  4930, 0, 0
4387 
  NET BUS  4938, 0, 0
4388 
  INSTANCE  4962, 0, 0
4389 
  {
4390 
   VARIABLES
4391 
   {
4392 
    #COMPONENT="alu_we_reg_clr"
4393 
    #LIBRARY="#default"
4394 
    #REFERENCE="U24"
4395 
    #SYMBOL="alu_we_reg_clr"
4396 
   }
4397 
   COORD (1320,1940)
4398 
   VERTEXES ( (2,7461), (6,7464), (8,7465), (4,7463) )
4399 
  }
4400 
  TEXT  4963, 0, 0
4401 
  {
4402 
   TEXT "$#REFERENCE"
4403 
   RECT (1320,1904,1373,1939)
4404 
   ALIGN 8
4405 
   MARGINS (1,1)
4406 
   PARENT 4962
4407 
  }
4408 
  TEXT  4967, 0, 0
4409 
  {
4410 
   TEXT "$#COMPONENT"
4411 
   RECT (1320,2100,1560,2135)
4412 
   MARGINS (1,1)
4413 
   PARENT 4962
4414 
  }
4415 
  NET BUS  4987, 0, 0
4416 
  NET BUS  5008, 0, 0
4417 
  VTX  5024, 0, 0
4418 
  {
4419 
   COORD (920,1500)
4420 
  }
4421 
  VTX  5026, 0, 0
4422 
  {
4423 
   COORD (940,1600)
4424 
  }
4425 
  VTX  5028, 0, 0
4426 
  {
4427 
   COORD (940,1500)
4428 
  }
4429 
  BUS  5029, 0, 0
4430 
  {
4431 
   NET 5483
4432 
   VTX 5026, 5028
4433 
  }
4434 
  BUS  5030, 0, 0
4435 
  {
4436 
   NET 5483
4437 
   VTX 5028, 5024
4438 
  }
4439 
  INSTANCE  5031, 0, 0
4440 
  {
4441 
   VARIABLES
4442 
   {
4443 
    #COMPONENT="alu_func_reg_clr"
4444 
    #LIBRARY="#default"
4445 
    #REFERENCE="U16"
4446 
    #SYMBOL="alu_func_reg_clr"
4447 
   }
4448 
   COORD (1200,1240)
4449 
   VERTEXES ( (8,5540), (6,5587), (2,5672), (4,6421) )
4450 
  }
4451 
  TEXT  5032, 0, 0
4452 
  {
4453 
   TEXT "$#REFERENCE"
4454 
   RECT (1200,1204,1253,1239)
4455 
   ALIGN 8
4456 
   MARGINS (1,1)
4457 
   PARENT 5031
4458 
  }
4459 
  TEXT  5036, 0, 0
4460 
  {
4461 
   TEXT "$#COMPONENT"
4462 
   RECT (1200,1400,1474,1435)
4463 
   MARGINS (1,1)
4464 
   PARENT 5031
4465 
  }
4466 
  INSTANCE  5058, 0, 0
4467 
  {
4468 
   VARIABLES
4469 
   {
4470 
    #COMPONENT="wb_mux_ctl_reg_clr"
4471 
    #LIBRARY="#default"
4472 
    #REFERENCE="U13"
4473 
    #SYMBOL="wb_mux_ctl_reg_clr"
4474 
   }
4475 
   COORD (1240,780)
4476 
   VERTEXES ( (8,5650), (2,5658), (6,6633), (4,7009) )
4477 
  }
4478 
  TEXT  5059, 0, 0
4479 
  {
4480 
   TEXT "$#REFERENCE"
4481 
   RECT (1240,744,1293,779)
4482 
   ALIGN 8
4483 
   MARGINS (1,1)
4484 
   PARENT 5058
4485 
  }
4486 
  TEXT  5063, 0, 0
4487 
  {
4488 
   TEXT "$#COMPONENT"
4489 
   RECT (1240,940,1548,975)
4490 
   MARGINS (1,1)
4491 
   PARENT 5058
4492 
  }
4493 
  INSTANCE  5104, 0, 0
4494 
  {
4495 
   VARIABLES
4496 
   {
4497 
    #COMPONENT="dmem_ctl_reg"
4498 
    #LIBRARY="#default"
4499 
    #REFERENCE="U9"
4500 
    #SYMBOL="dmem_ctl_reg"
4501 
   }
4502 
   COORD (1940,1020)
4503 
   VERTEXES ( (6,5428), (2,5742), (4,6676) )
4504 
  }
4505 
  TEXT  5105, 0, 0
4506 
  {
4507 
   TEXT "$#REFERENCE"
4508 
   RECT (1940,984,1976,1019)
4509 
   ALIGN 8
4510 
   MARGINS (1,1)
4511 
   PARENT 5104
4512 
  }
4513 
  TEXT  5109, 0, 0
4514 
  {
4515 
   TEXT "$#COMPONENT"
4516 
   RECT (1940,1140,2146,1175)
4517 
   MARGINS (1,1)
4518 
   PARENT 5104
4519 
  }
4520 
  INSTANCE  5150, 0, 0
4521 
  {
4522 
   VARIABLES
4523 
   {
4524 
    #COMPONENT="dmem_ctl_reg_clr"
4525 
    #LIBRARY="#default"
4526 
    #REFERENCE="U15"
4527 
    #SYMBOL="dmem_ctl_reg_clr"
4528 
   }
4529 
   COORD (1280,1020)
4530 
   VERTEXES ( (4,5429), (8,5664), (2,6611), (6,6622) )
4531 
  }
4532 
  TEXT  5151, 0, 0
4533 
  {
4534 
   TEXT "$#REFERENCE"
4535 
   RECT (1280,984,1333,1019)
4536 
   ALIGN 8
4537 
   MARGINS (1,1)
4538 
   PARENT 5150
4539 
  }
4540 
  TEXT  5155, 0, 0
4541 
  {
4542 
   TEXT "$#COMPONENT"
4543 
   RECT (1280,1180,1554,1215)
4544 
   MARGINS (1,1)
4545 
   PARENT 5150
4546 
  }
4547 
  INSTANCE  5190, 0, 0
4548 
  {
4549 
   VARIABLES
4550 
   {
4551 
    #COMPONENT="muxb_ctl_reg_clr"
4552 
    #LIBRARY="#default"
4553 
    #REFERENCE="U14"
4554 
    #SYMBOL="muxb_ctl_reg_clr"
4555 
   }
4556 
   COORD (1380,1520)
4557 
   VERTEXES ( (8,5476), (2,5594), (4,6418), (6,6591) )
4558 
  }
4559 
  TEXT  5191, 0, 0
4560 
  {
4561 
   TEXT "$#REFERENCE"
4562 
   RECT (1380,1484,1433,1519)
4563 
   ALIGN 8
4564 
   MARGINS (1,1)
4565 
   PARENT 5190
4566 
  }
4567 
  TEXT  5195, 0, 0
4568 
  {
4569 
   TEXT "$#COMPONENT"
4570 
   RECT (1380,1680,1654,1715)
4571 
   MARGINS (1,1)
4572 
   PARENT 5190
4573 
  }
4574 
  INSTANCE  5208, 0, 0
4575 
  {
4576 
   VARIABLES
4577 
   {
4578 
    #COMPONENT="muxa_ctl_reg_clr"
4579 
    #LIBRARY="#default"
4580 
    #REFERENCE="U17"
4581 
    #SYMBOL="muxa_ctl_reg_clr"
4582 
   }
4583 
   COORD (1340,1720)
4584 
   VERTEXES ( (8,5487), (6,5522), (2,5601), (4,6415) )
4585 
  }
4586 
  TEXT  5209, 0, 0
4587 
  {
4588 
   TEXT "$#REFERENCE"
4589 
   RECT (1340,1684,1393,1719)
4590 
   ALIGN 8
4591 
   MARGINS (1,1)
4592 
   PARENT 5208
4593 
  }
4594 
  TEXT  5213, 0, 0
4595 
  {
4596 
   TEXT "$#COMPONENT"
4597 
   RECT (1340,1880,1614,1915)
4598 
   MARGINS (1,1)
4599 
   PARENT 5208
4600 
  }
4601 
  NET BUS  5414, 0, 0
4602 
  VTX  5428, 0, 0
4603 
  {
4604 
   COORD (1940,1100)
4605 
  }
4606 
  VTX  5429, 0, 0
4607 
  {
4608 
   COORD (1520,1060)
4609 
  }
4610 
  VTX  5431, 0, 0
4611 
  {
4612 
   COORD (1540,1100)
4613 
  }
4614 
  VTX  5433, 0, 0
4615 
  {
4616 
   COORD (1540,1060)
4617 
  }
4618 
  BUS  5434, 0, 0
4619 
  {
4620 
   NET 5741
4621 
   VTX 5431, 5433
4622 
  }
4623 
  BUS  5435, 0, 0
4624 
  {
4625 
   NET 5741
4626 
   VTX 5433, 5429
4627 
  }
4628 
  NET BUS  5454, 0, 0
4629 
  NET BUS  5462, 0, 0
4630 
  VTX  5475, 0, 0
4631 
  {
4632 
   COORD (1220,1600)
4633 
  }
4634 
  VTX  5476, 0, 0
4635 
  {
4636 
   COORD (1380,1640)
4637 
  }
4638 
  BUS  5478, 0, 0
4639 
  {
4640 
   NET 5483
4641 
   VTX 5475, 5026
4642 
  }
4643 
  VTX  5480, 0, 0
4644 
  {
4645 
   COORD (1220,1640)
4646 
  }
4647 
  BUS  5481, 0, 0
4648 
  {
4649 
   NET 5483
4650 
   VTX 5475, 5480
4651 
  }
4652 
  BUS  5482, 0, 0
4653 
  {
4654 
   NET 5483
4655 
   VTX 5480, 5476
4656 
  }
4657 
  NET BUS  5483, 0, 0
4658 
  VTX  5486, 0, 0
4659 
  {
4660 
   COORD (900,1740)
4661 
  }
4662 
  VTX  5487, 0, 0
4663 
  {
4664 
   COORD (1340,1840)
4665 
  }
4666 
  VTX  5493, 0, 0
4667 
  {
4668 
   COORD (920,1740)
4669 
  }
4670 
  BUS  5494, 0, 0
4671 
  {
4672 
   NET 5008
4673 
   VTX 5486, 5493
4674 
  }
4675 
  VTX  5495, 0, 0
4676 
  {
4677 
   COORD (920,1840)
4678 
  }
4679 
  BUS  5496, 0, 0
4680 
  {
4681 
   NET 5008
4682 
   VTX 5493, 5495
4683 
  }
4684 
  BUS  5497, 0, 0
4685 
  {
4686 
   NET 5008
4687 
   VTX 5495, 5487
4688 
  }
4689 
  VTX  5522, 0, 0
4690 
  {
4691 
   COORD (1340,1800)
4692 
  }
4693 
  VTX  5540, 0, 0
4694 
  {
4695 
   COORD (1200,1360)
4696 
  }
4697 
  VTX  5557, 0, 0
4698 
  {
4699 
   COORD (1100,880)
4700 
  }
4701 
  VTX  5568, 0, 0
4702 
  {
4703 
   COORD (1100,580)
4704 
  }
4705 
  VTX  5569, 0, 0
4706 
  {
4707 
   COORD (1320,580)
4708 
  }
4709 
  WIRE  5571, 0, 0
4710 
  {
4711 
   NET 5574
4712 
   VTX 5568, 5557
4713 
  }
4714 
  WIRE  5573, 0, 0
4715 
  {
4716 
   NET 5574
4717 
   VTX 5568, 5569
4718 
  }
4719 
  NET WIRE  5574, 0, 0
4720 
  VTX  5575, 0, 0
4721 
  {
4722 
   COORD (1160,420)
4723 
  }
4724 
  WIRE  5578, 0, 0
4725 
  {
4726 
   NET 7320
4727 
   VTX 5575, 4871
4728 
  }
4729 
  VTX  5587, 0, 0
4730 
  {
4731 
   COORD (1200,1320)
4732 
  }
4733 
  VTX  5588, 0, 0
4734 
  {
4735 
   COORD (1160,1320)
4736 
  }
4737 
  WIRE  5592, 0, 0
4738 
  {
4739 
   NET 7320
4740 
   VTX 5587, 5588
4741 
  }
4742 
  VTX  5594, 0, 0
4743 
  {
4744 
   COORD (1380,1560)
4745 
  }
4746 
  VTX  5595, 0, 0
4747 
  {
4748 
   COORD (1160,1560)
4749 
  }
4750 
  WIRE  5596, 0, 0
4751 
  {
4752 
   NET 7320
4753 
   VTX 5588, 5595
4754 
  }
4755 
  WIRE  5599, 0, 0
4756 
  {
4757 
   NET 7320
4758 
   VTX 5594, 5595
4759 
  }
4760 
  VTX  5601, 0, 0
4761 
  {
4762 
   COORD (1340,1760)
4763 
  }
4764 
  VTX  5602, 0, 0
4765 
  {
4766 
   COORD (1160,1760)
4767 
  }
4768 
  WIRE  5603, 0, 0
4769 
  {
4770 
   NET 7320
4771 
   VTX 5595, 5602
4772 
  }
4773 
  WIRE  5606, 0, 0
4774 
  {
4775 
   NET 7320
4776 
   VTX 5601, 5602
4777 
  }
4778 
  WIRE  5611, 0, 0
4779 
  {
4780 
   NET 7320
4781 
   VTX 6612, 5588
4782 
  }
4783 
  VTX  5619, 0, 0
4784 
  {
4785 
   COORD (1320,540)
4786 
  }
4787 
  VTX  5620, 0, 0
4788 
  {
4789 
   COORD (1160,540)
4790 
  }
4791 
  WIRE  5621, 0, 0
4792 
  {
4793 
   NET 7320
4794 
   VTX 5575, 5620
4795 
  }
4796 
  WIRE  5624, 0, 0
4797 
  {
4798 
   NET 7320
4799 
   VTX 5619, 5620
4800 
  }
4801 
  NET BUS  5639, 0, 0
4802 
  VTX  5649, 0, 0
4803 
  {
4804 
   COORD (940,780)
4805 
  }
4806 
  VTX  5650, 0, 0
4807 
  {
4808 
   COORD (1240,900)
4809 
  }
4810 
  NET BUS  5651, 0, 0
4811 
  VTX  5652, 0, 0
4812 
  {
4813 
   COORD (1080,780)
4814 
  }
4815 
  BUS  5653, 0, 0
4816 
  {
4817 
   NET 5651
4818 
   VTX 5649, 5652
4819 
  }
4820 
  VTX  5654, 0, 0
4821 
  {
4822 
   COORD (1080,900)
4823 
  }
4824 
  BUS  5655, 0, 0
4825 
  {
4826 
   NET 5651
4827 
   VTX 5652, 5654
4828 
  }
4829 
  BUS  5656, 0, 0
4830 
  {
4831 
   NET 5651
4832 
   VTX 5654, 5650
4833 
  }
4834 
  VTX  5657, 0, 0
4835 
  {
4836 
   COORD (1160,820)
4837 
  }
4838 
  VTX  5658, 0, 0
4839 
  {
4840 
   COORD (1240,820)
4841 
  }
4842 
  WIRE  5659, 0, 0
4843 
  {
4844 
   NET 7320
4845 
   VTX 5620, 5657
4846 
  }
4847 
  WIRE  5662, 0, 0
4848 
  {
4849 
   NET 7320
4850 
   VTX 5657, 5658
4851 
  }
4852 
  VTX  5664, 0, 0
4853 
  {
4854 
   COORD (1280,1140)
4855 
  }
4856 
  VTX  5665, 0, 0
4857 
  {
4858 
   COORD (920,1020)
4859 
  }
4860 
  NET BUS  5666, 0, 0
4861 
  VTX  5667, 0, 0
4862 
  {
4863 
   COORD (940,1140)
4864 
  }
4865 
  BUS  5668, 0, 0
4866 
  {
4867 
   NET 5666
4868 
   VTX 5664, 5667
4869 
  }
4870 
  VTX  5669, 0, 0
4871 
  {
4872 
   COORD (940,1020)
4873 
  }
4874 
  BUS  5670, 0, 0
4875 
  {
4876 
   NET 5666
4877 
   VTX 5667, 5669
4878 
  }
4879 
  BUS  5671, 0, 0
4880 
  {
4881 
   NET 5666
4882 
   VTX 5669, 5665
4883 
  }
4884 
  VTX  5672, 0, 0
4885 
  {
4886 
   COORD (1200,1280)
4887 
  }
4888 
  VTX  5673, 0, 0
4889 
  {
4890 
   COORD (1000,1240)
4891 
  }
4892 
  NET BUS  5674, 0, 0
4893 
  VTX  5675, 0, 0
4894 
  {
4895 
   COORD (1020,1280)
4896 
  }
4897 
  BUS  5676, 0, 0
4898 
  {
4899 
   NET 5674
4900 
   VTX 5672, 5675
4901 
  }
4902 
  VTX  5677, 0, 0
4903 
  {
4904 
   COORD (1020,1240)
4905 
  }
4906 
  BUS  5678, 0, 0
4907 
  {
4908 
   NET 5674
4909 
   VTX 5675, 5677
4910 
  }
4911 
  BUS  5679, 0, 0
4912 
  {
4913 
   NET 5674
4914 
   VTX 5677, 5673
4915 
  }
4916 
  NET BUS  5682, 0, 0
4917 
  NET BUS  5690, 0, 0
4918 
  VTX  5734, 0, 0
4919 
  {
4920 
   COORD (2360,1200)
4921 
  }
4922 
  VTX  5735, 0, 0
4923 
  {
4924 
   COORD (1920,1100)
4925 
  }
4926 
  BUS  5736, 0, 0
4927 
  {
4928 
   NET 5741
4929 
   VTX 5428, 5735
4930 
  }
4931 
  BUS  5737, 0, 0
4932 
  {
4933 
   NET 5741
4934 
   VTX 5735, 5431
4935 
  }
4936 
  VTX  5738, 0, 0
4937 
  {
4938 
   COORD (1920,1200)
4939 
  }
4940 
  BUS  5739, 0, 0
4941 
  {
4942 
   NET 5741
4943 
   VTX 5734, 5738
4944 
  }
4945 
  BUS  5740, 0, 0
4946 
  {
4947 
   NET 5741
4948 
   VTX 5738, 5735
4949 
  }
4950 
  NET BUS  5741, 0, 0
4951 
  VTX  5742, 0, 0
4952 
  {
4953 
   COORD (1940,1060)
4954 
  }
4955 
  VTX  5743, 0, 0
4956 
  {
4957 
   COORD (1880,1060)
4958 
  }
4959 
  WIRE  5745, 0, 0
4960 
  {
4961 
   NET 7320
4962 
   VTX 5743, 5742
4963 
  }
4964 
  NET BUS  5790, 0, 0
4965 
  NET BUS  5887, 0, 0
4966 
  NET BUS  5895, 0, 0
4967 
  VTX  6366, 0, 0
4968 
  {
4969 
   COORD (680,640)
4970 
  }
4971 
  VTX  6367, 0, 0
4972 
  {
4973 
   COORD (460,640)
4974 
  }
4975 
  BUS  6368, 0, 0
4976 
  {
4977 
   NET 4399
4978 
   VTX 6366, 6367
4979 
  }
4980 
  VTX  6376, 0, 0
4981 
  {
4982 
   COORD (680,900)
4983 
  }
4984 
  VTX  6377, 0, 0
4985 
  {
4986 
   COORD (460,900)
4987 
  }
4988 
  BUS  6378, 0, 0
4989 
  {
4990 
   NET 4407
4991 
   VTX 6376, 6377
4992 
  }
4993 
  VTX  6379, 0, 0
4994 
  {
4995 
   COORD (680,1140)
4996 
  }
4997 
  VTX  6380, 0, 0
4998 
  {
4999 
   COORD (460,1140)
5000 
  }
5001 
  BUS  6381, 0, 0
5002 
  {
5003 
   NET 4421
5004 
   VTX 6379, 6380
5005 
  }
5006 
  VTX  6382, 0, 0
5007 
  {
5008 
   COORD (660,1240)
5009 
  }
5010 
  VTX  6383, 0, 0
5011 
  {
5012 
   COORD (460,1240)
5013 
  }
5014 
  BUS  6384, 0, 0
5015 
  {
5016 
   NET 4435
5017 
   VTX 6382, 6383
5018 
  }
5019 
  VTX  6385, 0, 0
5020 
  {
5021 
   COORD (680,1620)
5022 
  }
5023 
  VTX  6386, 0, 0
5024 
  {
5025 
   COORD (460,1620)
5026 
  }
5027 
  BUS  6387, 0, 0
5028 
  {
5029 
   NET 4567
5030 
   VTX 6385, 6386
5031 
  }
5032 
  VTX  6388, 0, 0
5033 
  {
5034 
   COORD (660,1860)
5035 
  }
5036 
  VTX  6389, 0, 0
5037 
  {
5038 
   COORD (480,1860)
5039 
  }
5040 
  BUS  6390, 0, 0
5041 
  {
5042 
   NET 4575
5043 
   VTX 6388, 6389
5044 
  }
5045 
  VTX  6391, 0, 0
5046 
  {
5047 
   COORD (660,1960)
5048 
  }
5049 
  VTX  6392, 0, 0
5050 
  {
5051 
   COORD (460,1960)
5052 
  }
5053 
  BUS  6393, 0, 0
5054 
  {
5055 
   NET 4591
5056 
   VTX 6391, 6392
5057 
  }
5058 
  VTX  6394, 0, 0
5059 
  {
5060 
   COORD (680,2320)
5061 
  }
5062 
  VTX  6395, 0, 0
5063 
  {
5064 
   COORD (460,2320)
5065 
  }
5066 
  BUS  6396, 0, 0
5067 
  {
5068 
   NET 4599
5069 
   VTX 6394, 6395
5070 
  }
5071 
  VTX  6397, 0, 0
5072 
  {
5073 
   COORD (680,2560)
5074 
  }
5075 
  VTX  6398, 0, 0
5076 
  {
5077 
   COORD (460,2560)
5078 
  }
5079 
  BUS  6399, 0, 0
5080 
  {
5081 
   NET 4607
5082 
   VTX 6397, 6398
5083 
  }
5084 
  VTX  6400, 0, 0
5085 
  {
5086 
   COORD (680,2800)
5087 
  }
5088 
  VTX  6401, 0, 0
5089 
  {
5090 
   COORD (460,2800)
5091 
  }
5092 
  BUS  6402, 0, 0
5093 
  {
5094 
   NET 4615
5095 
   VTX 6400, 6401
5096 
  }
5097 
  VTX  6403, 0, 0
5098 
  {
5099 
   COORD (680,3060)
5100 
  }
5101 
  VTX  6404, 0, 0
5102 
  {
5103 
   COORD (460,3060)
5104 
  }
5105 
  BUS  6405, 0, 0
5106 
  {
5107 
   NET 4623
5108 
   VTX 6403, 6404
5109 
  }
5110 
  VTX  6406, 0, 0
5111 
  {
5112 
   COORD (900,2440)
5113 
  }
5114 
  VTX  6407, 0, 0
5115 
  {
5116 
   COORD (1100,2440)
5117 
  }
5118 
  BUS  6408, 0, 0
5119 
  {
5120 
   NET 4930
5121 
   VTX 6406, 6407
5122 
  }
5123 
  VTX  6409, 0, 0
5124 
  {
5125 
   COORD (900,2680)
5126 
  }
5127 
  VTX  6410, 0, 0
5128 
  {
5129 
   COORD (1100,2680)
5130 
  }
5131 
  BUS  6411, 0, 0
5132 
  {
5133 
   NET 4922
5134 
   VTX 6409, 6410
5135 
  }
5136 
  VTX  6412, 0, 0
5137 
  {
5138 
   COORD (900,2200)
5139 
  }
5140 
  VTX  6413, 0, 0
5141 
  {
5142 
   COORD (1100,2200)
5143 
  }
5144 
  BUS  6414, 0, 0
5145 
  {
5146 
   NET 4938
5147 
   VTX 6412, 6413
5148 
  }
5149 
  VTX  6415, 0, 0
5150 
  {
5151 
   COORD (1580,1760)
5152 
  }
5153 
  VTX  6416, 0, 0
5154 
  {
5155 
   COORD (1740,1760)
5156 
  }
5157 
  BUS  6417, 0, 0
5158 
  {
5159 
   NET 5462
5160 
   VTX 6415, 6416
5161 
  }
5162 
  VTX  6418, 0, 0
5163 
  {
5164 
   COORD (1620,1560)
5165 
  }
5166 
  VTX  6419, 0, 0
5167 
  {
5168 
   COORD (1740,1560)
5169 
  }
5170 
  BUS  6420, 0, 0
5171 
  {
5172 
   NET 5454
5173 
   VTX 6418, 6419
5174 
  }
5175 
  VTX  6421, 0, 0
5176 
  {
5177 
   COORD (1540,1280)
5178 
  }
5179 
  VTX  6422, 0, 0
5180 
  {
5181 
   COORD (1740,1280)
5182 
  }
5183 
  BUS  6423, 0, 0
5184 
  {
5185 
   NET 984
5186 
   VTX 6421, 6422
5187 
  }
5188 
  VTX  6465, 0, 0
5189 
  {
5190 
   COORD (440,420)
5191 
  }
5192 
  VTX  6467, 0, 0
5193 
  {
5194 
   COORD (440,300)
5195 
  }
5196 
  WIRE  6473, 0, 0
5197 
  {
5198 
   NET 7320
5199 
   VTX 4871, 6465
5200 
  }
5201 
  VTX  6477, 0, 0
5202 
  {
5203 
   COORD (1100,300)
5204 
  }
5205 
  WIRE  6478, 0, 0
5206 
  {
5207 
   NET 5574
5208 
   VTX 5568, 6477
5209 
  }
5210 
  WIRE  6479, 0, 0
5211 
  {
5212 
   NET 5574
5213 
   VTX 6477, 6467
5214 
  }
5215 
  VTX  6480, 0, 0
5216 
  {
5217 
   COORD (440,380)
5218 
  }
5219 
  VTX  6481, 0, 0
5220 
  {
5221 
   COORD (500,380)
5222 
  }
5223 
  WIRE  6482, 0, 0
5224 
  {
5225 
   NET 6508
5226 
   VTX 4632, 6481
5227 
  }
5228 
  WIRE  6483, 0, 0
5229 
  {
5230 
   NET 6508
5231 
   VTX 6481, 6480
5232 
  }
5233 
  WIRE  6485, 0, 0
5234 
  {
5235 
   NET 6508
5236 
   VTX 4654, 6494
5237 
  }
5238 
  VTX  6494, 0, 0
5239 
  {
5240 
   COORD (500,2040)
5241 
  }
5242 
  WIRE  6496, 0, 0
5243 
  {
5244 
   NET 6508
5245 
   VTX 6494, 6519
5246 
  }
5247 
  WIRE  6500, 0, 0
5248 
  {
5249 
   NET 6508
5250 
   VTX 4657, 6494
5251 
  }
5252 
  NET WIRE  6508, 0, 0
5253 
  VTX  6519, 0, 0
5254 
  {
5255 
   COORD (500,2240)
5256 
  }
5257 
  WIRE  6520, 0, 0
5258 
  {
5259 
   NET 6508
5260 
   VTX 4676, 6519
5261 
  }
5262 
  WIRE  6522, 0, 0
5263 
  {
5264 
   NET 6508
5265 
   VTX 6519, 6537
5266 
  }
5267 
  WIRE  6534, 0, 0
5268 
  {
5269 
   NET 6508
5270 
   VTX 6537, 6546
5271 
  }
5272 
  VTX  6537, 0, 0
5273 
  {
5274 
   COORD (500,2480)
5275 
  }
5276 
  WIRE  6538, 0, 0
5277 
  {
5278 
   NET 6508
5279 
   VTX 4680, 6537
5280 
  }
5281 
  VTX  6539, 0, 0
5282 
  {
5283 
   COORD (680,2980)
5284 
  }
5285 
  VTX  6542, 0, 0
5286 
  {
5287 
   COORD (500,2980)
5288 
  }
5289 
  WIRE  6543, 0, 0
5290 
  {
5291 
   NET 6508
5292 
   VTX 6546, 6542
5293 
  }
5294 
  WIRE  6544, 0, 0
5295 
  {
5296 
   NET 6508
5297 
   VTX 6542, 6539
5298 
  }
5299 
  VTX  6546, 0, 0
5300 
  {
5301 
   COORD (500,2720)
5302 
  }
5303 
  WIRE  6547, 0, 0
5304 
  {
5305 
   NET 6508
5306 
   VTX 4684, 6546
5307 
  }
5308 
  VTX  6548, 0, 0
5309 
  {
5310 
   COORD (440,340)
5311 
  }
5312 
  VTX  6549, 0, 0
5313 
  {
5314 
   COORD (600,340)
5315 
  }
5316 
  WIRE  6550, 0, 0
5317 
  {
5318 
   NET 4710
5319 
   VTX 6548, 6549
5320 
  }
5321 
  VTX  6551, 0, 0
5322 
  {
5323 
   COORD (600,600)
5324 
  }
5325 
  WIRE  6552, 0, 0
5326 
  {
5327 
   NET 4710
5328 
   VTX 6549, 6551
5329 
  }
5330 
  WIRE  6554, 0, 0
5331 
  {
5332 
   NET 4710
5333 
   VTX 4813, 6551
5334 
  }
5335 
  WIRE  6556, 0, 0
5336 
  {
5337 
   NET 5574
5338 
   VTX 6623, 6571
5339 
  }
5340 
  VTX  6571, 0, 0
5341 
  {
5342 
   COORD (1100,1360)
5343 
  }
5344 
  WIRE  6572, 0, 0
5345 
  {
5346 
   NET 5574
5347 
   VTX 5540, 6571
5348 
  }
5349 
  VTX  6591, 0, 0
5350 
  {
5351 
   COORD (1380,1600)
5352 
  }
5353 
  VTX  6592, 0, 0
5354 
  {
5355 
   COORD (1100,1580)
5356 
  }
5357 
  VTX  6593, 0, 0
5358 
  {
5359 
   COORD (1360,1600)
5360 
  }
5361 
  WIRE  6594, 0, 0
5362 
  {
5363 
   NET 5574
5364 
   VTX 6591, 6593
5365 
  }
5366 
  VTX  6595, 0, 0
5367 
  {
5368 
   COORD (1360,1580)
5369 
  }
5370 
  WIRE  6596, 0, 0
5371 
  {
5372 
   NET 5574
5373 
   VTX 6593, 6595
5374 
  }
5375 
  WIRE  6597, 0, 0
5376 
  {
5377 
   NET 5574
5378 
   VTX 6595, 6592
5379 
  }
5380 
  WIRE  6598, 0, 0
5381 
  {
5382 
   NET 5574
5383 
   VTX 6571, 6592
5384 
  }
5385 
  WIRE  6601, 0, 0
5386 
  {
5387 
   NET 5574
5388 
   VTX 6609, 6592
5389 
  }
5390 
  VTX  6609, 0, 0
5391 
  {
5392 
   COORD (1100,1800)
5393 
  }
5394 
  WIRE  6610, 0, 0
5395 
  {
5396 
   NET 5574
5397 
   VTX 5522, 6609
5398 
  }
5399 
  VTX  6611, 0, 0
5400 
  {
5401 
   COORD (1280,1060)
5402 
  }
5403 
  VTX  6612, 0, 0
5404 
  {
5405 
   COORD (1160,1060)
5406 
  }
5407 
  WIRE  6614, 0, 0
5408 
  {
5409 
   NET 7320
5410 
   VTX 6612, 6611
5411 
  }
5412 
  WIRE  6615, 0, 0
5413 
  {
5414 
   NET 7320
5415 
   VTX 5657, 6612
5416 
  }
5417 
  VTX  6622, 0, 0
5418 
  {
5419 
   COORD (1280,1100)
5420 
  }
5421 
  VTX  6623, 0, 0
5422 
  {
5423 
   COORD (1100,1100)
5424 
  }
5425 
  WIRE  6625, 0, 0
5426 
  {
5427 
   NET 5574
5428 
   VTX 6623, 6622
5429 
  }
5430 
  WIRE  6626, 0, 0
5431 
  {
5432 
   NET 5574
5433 
   VTX 5557, 6623
5434 
  }
5435 
  VTX  6633, 0, 0
5436 
  {
5437 
   COORD (1240,860)
5438 
  }
5439 
  VTX  6634, 0, 0
5440 
  {
5441 
   COORD (1140,880)
5442 
  }
5443 
  WIRE  6635, 0, 0
5444 
  {
5445 
   NET 5574
5446 
   VTX 5557, 6634
5447 
  }
5448 
  VTX  6636, 0, 0
5449 
  {
5450 
   COORD (1140,860)
5451 
  }
5452 
  WIRE  6637, 0, 0
5453 
  {
5454 
   NET 5574
5455 
   VTX 6634, 6636
5456 
  }
5457 
  WIRE  6638, 0, 0
5458 
  {
5459 
   NET 5574
5460 
   VTX 6636, 6633
5461 
  }
5462 
  VTX  6676, 0, 0
5463 
  {
5464 
   COORD (2180,1060)
5465 
  }
5466 
  VTX  6677, 0, 0
5467 
  {
5468 
   COORD (2360,1060)
5469 
  }
5470 
  BUS  6678, 0, 0
5471 
  {
5472 
   NET 5414
5473 
   VTX 6676, 6677
5474 
  }
5475 
  VTX  6826, 0, 0
5476 
  {
5477 
   COORD (660,1280)
5478 
  }
5479 
  VTX  6827, 0, 0
5480 
  {
5481 
   COORD (640,1280)
5482 
  }
5483 
  WIRE  6828, 0, 0
5484 
  {
5485 
   NET 7320
5486 
   VTX 4885, 6827
5487 
  }
5488 
  WIRE  6829, 0, 0
5489 
  {
5490 
   NET 7320
5491 
   VTX 6827, 4889
5492 
  }
5493 
  WIRE  6831, 0, 0
5494 
  {
5495 
   NET 7320
5496 
   VTX 6826, 6827
5497 
  }
5498 
  INSTANCE  6896, 0, 0
5499 
  {
5500 
   VARIABLES
5501 
   {
5502 
    #COMPONENT="wb_we_reg"
5503 
    #LIBRARY="#default"
5504 
    #REFERENCE="U12"
5505 
    #SYMBOL="wb_we_reg"
5506 
   }
5507 
   COORD (2520,400)
5508 
   VERTEXES ( (2,7073), (4,7084), (6,7829) )
5509 
  }
5510 
  TEXT  6897, 0, 0
5511 
  {
5512 
   TEXT "$#REFERENCE"
5513 
   RECT (2520,364,2573,399)
5514 
   ALIGN 8
5515 
   MARGINS (1,1)
5516 
   PARENT 6896
5517 
  }
5518 
  TEXT  6901, 0, 0
5519 
  {
5520 
   TEXT "$#COMPONENT"
5521 
   RECT (2540,520,2695,555)
5522 
   MARGINS (1,1)
5523 
   PARENT 6896
5524 
  }
5525 
  INSTANCE  6905, 0, 0
5526 
  {
5527 
   VARIABLES
5528 
   {
5529 
    #COMPONENT="wb_we_reg"
5530 
    #LIBRARY="#default"
5531 
    #REFERENCE="U20"
5532 
    #SYMBOL="wb_we_reg"
5533 
   }
5534 
   COORD (1960,440)
5535 
   VERTEXES ( (2,7808), (6,7812), (4,7831) )
5536 
  }
5537 
  TEXT  6906, 0, 0
5538 
  {
5539 
   TEXT "$#REFERENCE"
5540 
   RECT (1960,404,2013,439)
5541 
   ALIGN 8
5542 
   MARGINS (1,1)
5543 
   PARENT 6905
5544 
  }
5545 
  TEXT  6910, 0, 0
5546 
  {
5547 
   TEXT "$#COMPONENT"
5548 
   RECT (1960,560,2115,595)
5549 
   MARGINS (1,1)
5550 
   PARENT 6905
5551 
  }
5552 
  VTX  6935, 0, 0
5553 
  {
5554 
   COORD (1880,420)
5555 
  }
5556 
  WIRE  6936, 0, 0
5557 
  {
5558 
   NET 7320
5559 
   VTX 5575, 6935
5560 
  }
5561 
  WIRE  6937, 0, 0
5562 
  {
5563 
   NET 7320
5564 
   VTX 6935, 7082
5565 
  }
5566 
  VTX  6948, 0, 0
5567 
  {
5568 
   COORD (1880,480)
5569 
  }
5570 
  WIRE  6949, 0, 0
5571 
  {
5572 
   NET 7320
5573 
   VTX 6935, 6948
5574 
  }
5575 
  INSTANCE  6983, 0, 0
5576 
  {
5577 
   VARIABLES
5578 
   {
5579 
    #COMPONENT="wb_mux_ctl_reg"
5580 
    #LIBRARY="#default"
5581 
    #REFERENCE="U21"
5582 
    #SYMBOL="wb_mux_ctl_reg"
5583 
   }
5584 
   COORD (2000,740)
5585 
   VERTEXES ( (6,7010), (2,7017), (4,7043) )
5586 
  }
5587 
  TEXT  6984, 0, 0
5588 
  {
5589 
   TEXT "$#REFERENCE"
5590 
   RECT (2000,704,2053,739)
5591 
   ALIGN 8
5592 
   MARGINS (1,1)
5593 
   PARENT 6983
5594 
  }
5595 
  TEXT  6988, 0, 0
5596 
  {
5597 
   TEXT "$#COMPONENT"
5598 
   RECT (2000,860,2240,895)
5599 
   MARGINS (1,1)
5600 
   PARENT 6983
5601 
  }
5602 
  VTX  7009, 0, 0
5603 
  {
5604 
   COORD (1500,820)
5605 
  }
5606 
  VTX  7010, 0, 0
5607 
  {
5608 
   COORD (2000,820)
5609 
  }
5610 
  BUS  7016, 0, 0
5611 
  {
5612 
   NET 5690
5613 
   VTX 7009, 7010
5614 
  }
5615 
  VTX  7017, 0, 0
5616 
  {
5617 
   COORD (2000,780)
5618 
  }
5619 
  VTX  7018, 0, 0
5620 
  {
5621 
   COORD (1880,780)
5622 
  }
5623 
  WIRE  7019, 0, 0
5624 
  {
5625 
   NET 7320
5626 
   VTX 6948, 7018
5627 
  }
5628 
  WIRE  7020, 0, 0
5629 
  {
5630 
   NET 7320
5631 
   VTX 7018, 5743
5632 
  }
5633 
  WIRE  7022, 0, 0
5634 
  {
5635 
   NET 7320
5636 
   VTX 7017, 7018
5637 
  }
5638 
  INSTANCE  7024, 0, 0
5639 
  {
5640 
   VARIABLES
5641 
   {
5642 
    #COMPONENT="wb_mux_ctl_reg"
5643 
    #LIBRARY="#default"
5644 
    #REFERENCE="U18"
5645 
    #SYMBOL="wb_mux_ctl_reg"
5646 
   }
5647 
   COORD (2520,700)
5648 
   VERTEXES ( (2,7040), (6,7044), (4,7054) )
5649 
  }
5650 
  TEXT  7025, 0, 0
5651 
  {
5652 
   TEXT "$#REFERENCE"
5653 
   RECT (2520,664,2573,699)
5654 
   ALIGN 8
5655 
   MARGINS (1,1)
5656 
   PARENT 7024
5657 
  }
5658 
  TEXT  7029, 0, 0
5659 
  {
5660 
   TEXT "$#COMPONENT"
5661 
   RECT (2520,820,2760,855)
5662 
   MARGINS (1,1)
5663 
   PARENT 7024
5664 
  }
5665 
  VTX  7040, 0, 0
5666 
  {
5667 
   COORD (2520,740)
5668 
  }
5669 
  VTX  7043, 0, 0
5670 
  {
5671 
   COORD (2260,780)
5672 
  }
5673 
  VTX  7044, 0, 0
5674 
  {
5675 
   COORD (2520,780)
5676 
  }
5677 
  VTX  7045, 0, 0
5678 
  {
5679 
   COORD (2480,740)
5680 
  }
5681 
  WIRE  7047, 0, 0
5682 
  {
5683 
   NET 7320
5684 
   VTX 7045, 7040
5685 
  }
5686 
  BUS  7053, 0, 0
5687 
  {
5688 
   NET 5790
5689 
   VTX 7043, 7044
5690 
  }
5691 
  VTX  7054, 0, 0
5692 
  {
5693 
   COORD (2780,740)
5694 
  }
5695 
  VTX  7055, 0, 0
5696 
  {
5697 
   COORD (2820,740)
5698 
  }
5699 
  BUS  7056, 0, 0
5700 
  {
5701 
   NET 5887
5702 
   VTX 7054, 7055
5703 
  }
5704 
  VTX  7073, 0, 0
5705 
  {
5706 
   COORD (2520,440)
5707 
  }
5708 
  VTX  7076, 0, 0
5709 
  {
5710 
   COORD (2500,420)
5711 
  }
5712 
  WIRE  7077, 0, 0
5713 
  {
5714 
   NET 7320
5715 
   VTX 7082, 7076
5716 
  }
5717 
  VTX  7078, 0, 0
5718 
  {
5719 
   COORD (2500,440)
5720 
  }
5721 
  WIRE  7079, 0, 0
5722 
  {
5723 
   NET 7320
5724 
   VTX 7076, 7078
5725 
  }
5726 
  WIRE  7080, 0, 0
5727 
  {
5728 
   NET 7320
5729 
   VTX 7078, 7073
5730 
  }
5731 
  VTX  7082, 0, 0
5732 
  {
5733 
   COORD (2480,420)
5734 
  }
5735 
  WIRE  7083, 0, 0
5736 
  {
5737 
   NET 7320
5738 
   VTX 7045, 7082
5739 
  }
5740 
  VTX  7084, 0, 0
5741 
  {
5742 
   COORD (2740,440)
5743 
  }
5744 
  VTX  7085, 0, 0
5745 
  {
5746 
   COORD (2800,440)
5747 
  }
5748 
  BUS  7086, 0, 0
5749 
  {
5750 
   NET 5895
5751 
   VTX 7084, 7085
5752 
  }
5753 
  INSTANCE  7181, 0, 0
5754 
  {
5755 
   VARIABLES
5756 
   {
5757 
    #COMPONENT="wb_we_reg_clr"
5758 
    #LIBRARY="#default"
5759 
    #REFERENCE="U19"
5760 
    #SYMBOL="wb_we_reg_clr"
5761 
   }
5762 
   COORD (1320,500)
5763 
   VERTEXES ( (2,5619), (6,5569), (8,7202), (4,7811) )
5764 
  }
5765 
  TEXT  7182, 0, 0
5766 
  {
5767 
   TEXT "$#REFERENCE"
5768 
   RECT (1320,464,1373,499)
5769 
   ALIGN 8
5770 
   MARGINS (1,1)
5771 
   PARENT 7181
5772 
  }
5773 
  TEXT  7186, 0, 0
5774 
  {
5775 
   TEXT "$#COMPONENT"
5776 
   RECT (1320,660,1543,695)
5777 
   MARGINS (1,1)
5778 
   PARENT 7181
5779 
  }
5780 
  VTX  7201, 0, 0
5781 
  {
5782 
   COORD (900,520)
5783 
  }
5784 
  VTX  7202, 0, 0
5785 
  {
5786 
   COORD (1320,620)
5787 
  }
5788 
  VTX  7203, 0, 0
5789 
  {
5790 
   COORD (1080,520)
5791 
  }
5792 
  BUS  7204, 0, 0
5793 
  {
5794 
   NET 5639
5795 
   VTX 7201, 7203
5796 
  }
5797 
  VTX  7205, 0, 0
5798 
  {
5799 
   COORD (1080,600)
5800 
  }
5801 
  BUS  7206, 0, 0
5802 
  {
5803 
   NET 5639
5804 
   VTX 7203, 7205
5805 
  }
5806 
  VTX  7207, 0, 0
5807 
  {
5808 
   COORD (1280,600)
5809 
  }
5810 
  BUS  7208, 0, 0
5811 
  {
5812 
   NET 5639
5813 
   VTX 7205, 7207
5814 
  }
5815 
  VTX  7209, 0, 0
5816 
  {
5817 
   COORD (1280,620)
5818 
  }
5819 
  BUS  7210, 0, 0
5820 
  {
5821 
   NET 5639
5822 
   VTX 7207, 7209
5823 
  }
5824 
  BUS  7211, 0, 0
5825 
  {
5826 
   NET 5639
5827 
   VTX 7209, 7202
5828 
  }
5829 
  INSTANCE  7296, 0, 0
5830 
  {
5831 
   VARIABLES
5832 
   {
5833 
    #COMPONENT="wb_we_reg"
5834 
    #LIBRARY="#default"
5835 
    #REFERENCE="U22"
5836 
    #SYMBOL="wb_we_reg"
5837 
   }
5838 
   COORD (1980,1900)
5839 
   VERTEXES ( (2,7410), (4,7412), (6,7462) )
5840 
  }
5841 
  TEXT  7297, 0, 0
5842 
  {
5843 
   TEXT "$#REFERENCE"
5844 
   RECT (1980,1864,2033,1899)
5845 
   ALIGN 8
5846 
   MARGINS (1,1)
5847 
   PARENT 7296
5848 
  }
5849 
  TEXT  7298, 0, 0
5850 
  {
5851 
   TEXT "$#COMPONENT"
5852 
   RECT (1980,2020,2135,2055)
5853 
   MARGINS (1,1)
5854 
   PARENT 7296
5855 
  }
5856 
  NET BUS  7299, 0, 0
5857 
  VTX  7307, 0, 0
5858 
  {
5859 
   COORD (1160,1940)
5860 
  }
5861 
  WIRE  7308, 0, 0
5862 
  {
5863 
   NET 7320
5864 
   VTX 5602, 7307
5865 
  }
5866 
  NET WIRE  7320, 0, 0
5867 
  VTX  7410, 0, 0
5868 
  {
5869 
   COORD (1980,1940)
5870 
  }
5871 
  VTX  7411, 0, 0
5872 
  {
5873 
   COORD (2280,1940)
5874 
  }
5875 
  VTX  7412, 0, 0
5876 
  {
5877 
   COORD (2200,1940)
5878 
  }
5879 
  VTX  7415, 0, 0
5880 
  {
5881 
   COORD (1180,1940)
5882 
  }
5883 
  WIRE  7416, 0, 0
5884 
  {
5885 
   NET 7320
5886 
   VTX 7307, 7415
5887 
  }
5888 
  VTX  7417, 0, 0
5889 
  {
5890 
   COORD (1180,1920)
5891 
  }
5892 
  WIRE  7418, 0, 0
5893 
  {
5894 
   NET 7320
5895 
   VTX 7415, 7417
5896 
  }
5897 
  VTX  7419, 0, 0
5898 
  {
5899 
   COORD (1660,1920)
5900 
  }
5901 
  WIRE  7420, 0, 0
5902 
  {
5903 
   NET 7320
5904 
   VTX 7417, 7419
5905 
  }
5906 
  VTX  7421, 0, 0
5907 
  {
5908 
   COORD (1660,1940)
5909 
  }
5910 
  WIRE  7422, 0, 0
5911 
  {
5912 
   NET 7320
5913 
   VTX 7419, 7421
5914 
  }
5915 
  WIRE  7423, 0, 0
5916 
  {
5917 
   NET 7320
5918 
   VTX 7421, 7410
5919 
  }
5920 
  VTX  7460, 0, 0
5921 
  {
5922 
   COORD (980,1960)
5923 
  }
5924 
  VTX  7461, 0, 0
5925 
  {
5926 
   COORD (1320,1980)
5927 
  }
5928 
  VTX  7462, 0, 0
5929 
  {
5930 
   COORD (1980,1980)
5931 
  }
5932 
  VTX  7463, 0, 0
5933 
  {
5934 
   COORD (1640,1980)
5935 
  }
5936 
  VTX  7464, 0, 0
5937 
  {
5938 
   COORD (1320,2020)
5939 
  }
5940 
  VTX  7465, 0, 0
5941 
  {
5942 
   COORD (1320,2060)
5943 
  }
5944 
  VTX  7466, 0, 0
5945 
  {
5946 
   COORD (1000,1960)
5947 
  }
5948 
  BUS  7467, 0, 0
5949 
  {
5950 
   NET 4987
5951 
   VTX 7460, 7466
5952 
  }
5953 
  VTX  7468, 0, 0
5954 
  {
5955 
   COORD (1000,1980)
5956 
  }
5957 
  BUS  7469, 0, 0
5958 
  {
5959 
   NET 4987
5960 
   VTX 7466, 7468
5961 
  }
5962 
  BUS  7470, 0, 0
5963 
  {
5964 
   NET 4987
5965 
   VTX 7468, 7461
5966 
  }
5967 
  BUS  7471, 0, 0
5968 
  {
5969 
   NET 7299
5970 
   VTX 7462, 7463
5971 
  }
5972 
  VTX  7472, 0, 0
5973 
  {
5974 
   COORD (1160,2020)
5975 
  }
5976 
  WIRE  7473, 0, 0
5977 
  {
5978 
   NET 7320
5979 
   VTX 7307, 7472
5980 
  }
5981 
  WIRE  7474, 0, 0
5982 
  {
5983 
   NET 7320
5984 
   VTX 7472, 7464
5985 
  }
5986 
  VTX  7475, 0, 0
5987 
  {
5988 
   COORD (1100,2060)
5989 
  }
5990 
  WIRE  7476, 0, 0
5991 
  {
5992 
   NET 5574
5993 
   VTX 6609, 7475
5994 
  }
5995 
  WIRE  7477, 0, 0
5996 
  {
5997 
   NET 5574
5998 
   VTX 7475, 7465
5999 
  }
6000 
  INSTANCE  7634, 0, 0
6001 
  {
6002 
   VARIABLES
6003 
   {
6004 
    #COMPONENT="or2"
6005 
    #LIBRARY="#builtin"
6006 
    #REFERENCE="U23"
6007 
    #SYMBOL="or2"
6008 
   }
6009 
   COORD (2300,580)
6010 
   VERTEXES ( (6,7832), (2,7828), (4,7830) )
6011 
  }
6012 
  NET WIRE  7643, 0, 0
6013 
  BUS  7734, 0, 0
6014 
  {
6015 
   NET 7740
6016 
   VTX 7411, 7737
6017 
  }
6018 
  VTX  7737, 0, 0
6019 
  {
6020 
   COORD (2280,1940)
6021 
  }
6022 
  NET BUS  7740, 0, 0
6023 
  BUS  7741, 0, 0
6024 
  {
6025 
   NET 7740
6026 
   VTX 7737, 7412
6027 
  }
6028 
  VTX  7808, 0, 0
6029 
  {
6030 
   COORD (1960,480)
6031 
  }
6032 
  VTX  7811, 0, 0
6033 
  {
6034 
   COORD (1540,540)
6035 
  }
6036 
  VTX  7812, 0, 0
6037 
  {
6038 
   COORD (1960,520)
6039 
  }
6040 
  WIRE  7813, 0, 0
6041 
  {
6042 
   NET 7320
6043 
   VTX 6948, 7808
6044 
  }
6045 
  VTX  7815, 0, 0
6046 
  {
6047 
   COORD (1760,540)
6048 
  }
6049 
  BUS  7816, 0, 0
6050 
  {
6051 
   NET 5682
6052 
   VTX 7811, 7815
6053 
  }
6054 
  VTX  7817, 0, 0
6055 
  {
6056 
   COORD (1760,520)
6057 
  }
6058 
  BUS  7818, 0, 0
6059 
  {
6060 
   NET 5682
6061 
   VTX 7815, 7817
6062 
  }
6063 
  BUS  7819, 0, 0
6064 
  {
6065 
   NET 5682
6066 
   VTX 7817, 7812
6067 
  }
6068 
  NET BUS  7822, 0, 0
6069 
  VTX  7828, 0, 0
6070 
  {
6071 
   COORD (2300,640)
6072 
  }
6073 
  VTX  7829, 0, 0
6074 
  {
6075 
   COORD (2520,480)
6076 
  }
6077 
  VTX  7830, 0, 0
6078 
  {
6079 
   COORD (2460,620)
6080 
  }
6081 
  VTX  7831, 0, 0
6082 
  {
6083 
   COORD (2180,480)
6084 
  }
6085 
  VTX  7832, 0, 0
6086 
  {
6087 
   COORD (2300,600)
6088 
  }
6089 
  VTX  7833, 0, 0
6090 
  {
6091 
   COORD (2280,640)
6092 
  }
6093 
  BUS  7834, 0, 0
6094 
  {
6095 
   NET 7740
6096 
   VTX 7737, 7833
6097 
  }
6098 
  BUS  7835, 0, 0
6099 
  {
6100 
   NET 7740
6101 
   VTX 7833, 7828
6102 
  }
6103 
  VTX  7836, 0, 0
6104 
  {
6105 
   COORD (2500,480)
6106 
  }
6107 
  WIRE  7837, 0, 0
6108 
  {
6109 
   NET 7643
6110 
   VTX 7829, 7836
6111 
  }
6112 
  VTX  7838, 0, 0
6113 
  {
6114 
   COORD (2500,620)
6115 
  }
6116 
  WIRE  7839, 0, 0
6117 
  {
6118 
   NET 7643
6119 
   VTX 7836, 7838
6120 
  }
6121 
  WIRE  7840, 0, 0
6122 
  {
6123 
   NET 7643
6124 
   VTX 7838, 7830
6125 
  }
6126 
  VTX  7841, 0, 0
6127 
  {
6128 
   COORD (2260,480)
6129 
  }
6130 
  BUS  7842, 0, 0
6131 
  {
6132 
   NET 7822
6133 
   VTX 7831, 7841
6134 
  }
6135 
  VTX  7843, 0, 0
6136 
  {
6137 
   COORD (2260,600)
6138 
  }
6139 
  BUS  7844, 0, 0
6140 
  {
6141 
   NET 7822
6142 
   VTX 7841, 7843
6143 
  }
6144 
  BUS  7845, 0, 0
6145 
  {
6146 
   NET 7822
6147 
   VTX 7843, 7832
6148 
  }
6149 
 }
6150 
 
6151 
}
6152 
 
6153 
PAGE ""
6154 
{
6155 
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6156 
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6157 
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6158 
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6159 
  RECT (0,0,0,0)
6160 
  VARIABLES
6161 
  {
6162 
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6163 
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6164 
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6165 
   #BLOCKTABLE_VISIBLE="0"
6166 
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