| 1 |
15 |
mcupro |
--N1_txd is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|txd
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| 2 |
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--operation mode is normal
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| 3 |
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| 4 |
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N1_txd_lut_out = N1_txd_1_a & N1_txd # !N1_txd_1_a & N1_txd_8 # !sys_rst;
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| 5 |
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N1_txd = DFFEAS(N1_txd_lut_out, E1__clk0, VCC, , , , , , );
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| 6 |
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| 7 |
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| 8 |
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--H1_N_62_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_62_i
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| 9 |
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--operation mode is normal
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| 10 |
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| 11 |
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H1_N_62_i = F1_seg7data[7] # F1_seg7data[6] & !F1_seg7data[4] # !F1_seg7data[5] # !F1_seg7data[6] & F1_seg7data[5];
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| 12 |
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| 13 |
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| 14 |
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--H1_N_60_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_60_i
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| 15 |
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--operation mode is normal
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| 16 |
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| 17 |
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H1_N_60_i = F1_seg7data[5] & F1_seg7data[7] # !F1_seg7data[4] & F1_seg7data[6] # !F1_seg7data[5] & F1_seg7data[6] & !F1_seg7data[7] # !F1_seg7data[6] & F1_seg7data[7] # !F1_seg7data[4];
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| 18 |
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| 19 |
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| 20 |
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--H1_N_58_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_58_i
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| 21 |
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--operation mode is normal
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| 22 |
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| 23 |
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H1_N_58_i = F1_seg7data[5] & F1_seg7data[7] # !F1_seg7data[4] # !F1_seg7data[5] & F1_seg7data[6] & F1_seg7data[7] # !F1_seg7data[6] & !F1_seg7data[4];
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| 24 |
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| 25 |
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| 26 |
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--H1_m18_0 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m18_0
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| 27 |
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--operation mode is normal
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| 28 |
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| 29 |
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H1_m18_0 = F1_seg7data[4] & F1_seg7data[6] $ F1_seg7data[5] # !F1_seg7data[4] & F1_seg7data[6] & F1_seg7data[5] # F1_seg7data[7] # !F1_seg7data[6] & !F1_seg7data[7] # !F1_seg7data[5];
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| 30 |
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| 31 |
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| 32 |
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--H1_m15_0 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m15_0
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| 33 |
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--operation mode is normal
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| 34 |
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| 35 |
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H1_m15_0 = F1_seg7data[6] & !F1_seg7data[5] & F1_seg7data[4] # !F1_seg7data[7] # !F1_seg7data[6] & F1_seg7data[4] # F1_seg7data[7] # !F1_seg7data[5];
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| 36 |
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| 37 |
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| 38 |
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--H1_m11_0 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m11_0
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| 39 |
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--operation mode is normal
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| 40 |
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| 41 |
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H1_m11_0 = F1_seg7data[5] & F1_seg7data[4] & !F1_seg7data[7] # !F1_seg7data[4] & !F1_seg7data[6] # !F1_seg7data[5] & F1_seg7data[4] $ !F1_seg7data[7] # !F1_seg7data[6];
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| 42 |
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| 43 |
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| 44 |
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--H1_N_44_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_44_i
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| 45 |
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--operation mode is normal
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| 46 |
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| 47 |
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H1_N_44_i = F1_seg7data[6] & F1_seg7data[7] & F1_seg7data[5] # !F1_seg7data[7] & F1_seg7data[4] # !F1_seg7data[6] & F1_seg7data[5] $ F1_seg7data[7] # !F1_seg7data[4];
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| 48 |
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| 49 |
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| 50 |
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--H1_N_31_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_31_i
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| 51 |
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--operation mode is normal
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| 52 |
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| 53 |
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H1_N_31_i = F1_seg7data[3] # F1_seg7data[2] & !F1_seg7data[0] # !F1_seg7data[1] # !F1_seg7data[2] & F1_seg7data[1];
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| 54 |
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| 55 |
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| 56 |
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--H1_N_29_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_29_i
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| 57 |
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--operation mode is normal
|
| 58 |
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|
| 59 |
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H1_N_29_i = F1_seg7data[1] & F1_seg7data[3] # !F1_seg7data[0] & F1_seg7data[2] # !F1_seg7data[1] & F1_seg7data[2] & !F1_seg7data[3] # !F1_seg7data[2] & F1_seg7data[3] # !F1_seg7data[0];
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| 60 |
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| 61 |
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| 62 |
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--H1_N_27_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_27_i
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| 63 |
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--operation mode is normal
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| 64 |
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|
| 65 |
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H1_N_27_i = F1_seg7data[1] & F1_seg7data[3] # !F1_seg7data[0] # !F1_seg7data[1] & F1_seg7data[2] & F1_seg7data[3] # !F1_seg7data[2] & !F1_seg7data[0];
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| 66 |
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| 67 |
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| 68 |
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--H1_m18 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m18
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| 69 |
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--operation mode is normal
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| 70 |
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|
| 71 |
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H1_m18 = F1_seg7data[0] & F1_seg7data[2] $ F1_seg7data[1] # !F1_seg7data[0] & F1_seg7data[2] & F1_seg7data[1] # F1_seg7data[3] # !F1_seg7data[2] & !F1_seg7data[3] # !F1_seg7data[1];
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| 72 |
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| 73 |
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|
| 74 |
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--H1_m15 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m15
|
| 75 |
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--operation mode is normal
|
| 76 |
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|
|
| 77 |
|
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H1_m15 = F1_seg7data[2] & !F1_seg7data[1] & F1_seg7data[0] # !F1_seg7data[3] # !F1_seg7data[2] & F1_seg7data[0] # F1_seg7data[3] # !F1_seg7data[1];
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| 78 |
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|
| 79 |
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|
| 80 |
|
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--H1_m11 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m11
|
| 81 |
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--operation mode is normal
|
| 82 |
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|
| 83 |
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H1_m11 = F1_seg7data[1] & F1_seg7data[0] & !F1_seg7data[3] # !F1_seg7data[0] & !F1_seg7data[2] # !F1_seg7data[1] & F1_seg7data[0] $ !F1_seg7data[3] # !F1_seg7data[2];
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| 84 |
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|
| 85 |
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|
| 86 |
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--H1_N_13_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_13_i
|
| 87 |
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--operation mode is normal
|
| 88 |
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|
| 89 |
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H1_N_13_i = F1_seg7data[2] & F1_seg7data[3] & F1_seg7data[1] # !F1_seg7data[3] & F1_seg7data[0] # !F1_seg7data[2] & F1_seg7data[1] $ F1_seg7data[3] # !F1_seg7data[0];
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| 90 |
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|
| 91 |
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| 92 |
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--F1_lcd_data_7 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_7
|
| 93 |
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--operation mode is normal
|
| 94 |
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|
| 95 |
|
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F1_lcd_data_7_lut_out = CB1_r32_o_7;
|
| 96 |
|
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F1_lcd_data_7 = DFFEAS(F1_lcd_data_7_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
|
| 97 |
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| 98 |
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| 99 |
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--F1_lcd_data_6 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_6
|
| 100 |
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--operation mode is normal
|
| 101 |
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|
| 102 |
|
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F1_lcd_data_6_lut_out = CB1_r32_o_6;
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| 103 |
|
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F1_lcd_data_6 = DFFEAS(F1_lcd_data_6_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
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| 104 |
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| 105 |
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|
| 106 |
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--F1_lcd_data_5 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_5
|
| 107 |
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--operation mode is normal
|
| 108 |
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|
|
| 109 |
|
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F1_lcd_data_5_lut_out = CB1_r32_o_5;
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| 110 |
|
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F1_lcd_data_5 = DFFEAS(F1_lcd_data_5_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
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| 111 |
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|
| 112 |
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|
| 113 |
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--F1_lcd_data_4 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_4
|
| 114 |
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--operation mode is normal
|
| 115 |
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|
| 116 |
|
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F1_lcd_data_4_lut_out = CB1_r32_o_4;
|
| 117 |
|
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F1_lcd_data_4 = DFFEAS(F1_lcd_data_4_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
|
| 118 |
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|
| 119 |
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|
| 120 |
|
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--F1_lcd_data_3 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_3
|
| 121 |
|
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--operation mode is normal
|
| 122 |
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|
|
| 123 |
|
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F1_lcd_data_3_lut_out = CB1_r32_o_3;
|
| 124 |
|
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F1_lcd_data_3 = DFFEAS(F1_lcd_data_3_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
|
| 125 |
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|
| 126 |
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|
| 127 |
|
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--F1_lcd_data_2 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_2
|
| 128 |
|
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--operation mode is normal
|
| 129 |
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|
|
| 130 |
|
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F1_lcd_data_2_lut_out = CB1_r32_o_2;
|
| 131 |
|
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F1_lcd_data_2 = DFFEAS(F1_lcd_data_2_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
|
| 132 |
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|
| 133 |
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|
| 134 |
|
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--F1_lcd_data_1 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_1
|
| 135 |
|
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--operation mode is normal
|
| 136 |
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|
| 137 |
|
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F1_lcd_data_1_lut_out = CB1_r32_o_1;
|
| 138 |
|
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F1_lcd_data_1 = DFFEAS(F1_lcd_data_1_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
|
| 139 |
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|
| 140 |
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|
| 141 |
|
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--F1_lcd_data_0 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0
|
| 142 |
|
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--operation mode is normal
|
| 143 |
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|
| 144 |
|
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F1_lcd_data_0_lut_out = CB1_r32_o_0;
|
| 145 |
|
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F1_lcd_data_0 = DFFEAS(F1_lcd_data_0_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
|
| 146 |
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|
| 147 |
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|
| 148 |
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--F1_cmd_2 is mips_sys:isys|mips_dvc:imips_dvc|cmd_2
|
| 149 |
|
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--operation mode is normal
|
| 150 |
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|
| 151 |
|
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F1_cmd_2_lut_out = CB1_r32_o_2;
|
| 152 |
|
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F1_cmd_2 = DFFEAS(F1_cmd_2_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 153 |
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|
| 154 |
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|
| 155 |
|
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--F1_cmd_3 is mips_sys:isys|mips_dvc:imips_dvc|cmd_3
|
| 156 |
|
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--operation mode is normal
|
| 157 |
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|
|
| 158 |
|
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F1_cmd_3_lut_out = CB1_r32_o_3;
|
| 159 |
|
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F1_cmd_3 = DFFEAS(F1_cmd_3_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 160 |
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|
| 161 |
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|
| 162 |
|
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--F1_cmd_4 is mips_sys:isys|mips_dvc:imips_dvc|cmd_4
|
| 163 |
|
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--operation mode is normal
|
| 164 |
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|
| 165 |
|
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F1_cmd_4_lut_out = CB1_r32_o_4;
|
| 166 |
|
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F1_cmd_4 = DFFEAS(F1_cmd_4_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 167 |
|
|
|
| 168 |
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|
| 169 |
|
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--F1_cmd_5 is mips_sys:isys|mips_dvc:imips_dvc|cmd_5
|
| 170 |
|
|
--operation mode is normal
|
| 171 |
|
|
|
| 172 |
|
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F1_cmd_5_lut_out = CB1_r32_o_5;
|
| 173 |
|
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F1_cmd_5 = DFFEAS(F1_cmd_5_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 174 |
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|
|
| 175 |
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|
| 176 |
|
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--F1_cmd_6 is mips_sys:isys|mips_dvc:imips_dvc|cmd_6
|
| 177 |
|
|
--operation mode is normal
|
| 178 |
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|
|
| 179 |
|
|
F1_cmd_6_lut_out = CB1_r32_o_6;
|
| 180 |
|
|
F1_cmd_6 = DFFEAS(F1_cmd_6_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 181 |
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|
| 182 |
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|
| 183 |
|
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--E1__clk0 is pll50:Ipll|altpll:altpll_component|_clk0
|
| 184 |
|
|
E1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());
|
| 185 |
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|
| 186 |
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|
| 187 |
|
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--sys_rst is sys_rst
|
| 188 |
|
|
--operation mode is normal
|
| 189 |
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|
|
| 190 |
|
|
sys_rst_lut_out = r_rst;
|
| 191 |
|
|
sys_rst = DFFEAS(sys_rst_lut_out, E1__clk0, VCC, , , , , , );
|
| 192 |
|
|
|
| 193 |
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|
| 194 |
|
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--N1_txd_8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|txd_8
|
| 195 |
|
|
--operation mode is normal
|
| 196 |
|
|
|
| 197 |
|
|
N1_txd_8 = N1_ua_state[2] & N1_tx_sr[0] # !N1_ua_state[2] & !N1_clk_ctr_equ15_0_a2 # !N1_ua_state[1];
|
| 198 |
|
|
|
| 199 |
|
|
|
| 200 |
|
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--N1_txd_1_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|txd_1_a
|
| 201 |
|
|
--operation mode is normal
|
| 202 |
|
|
|
| 203 |
|
|
N1_txd_1_a = N1_ua_state_i[0] & !N1_ua_state[1] & !N1_bit_ctr23_i_0_o2 # !N1_clk_ctr_equ15_0_a2;
|
| 204 |
|
|
|
| 205 |
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|
|
| 206 |
|
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--F1_seg7data[6] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[6]
|
| 207 |
|
|
--operation mode is normal
|
| 208 |
|
|
|
| 209 |
|
|
F1_seg7data[6]_lut_out = CB1_r32_o_6;
|
| 210 |
|
|
F1_seg7data[6] = DFFEAS(F1_seg7data[6]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );
|
| 211 |
|
|
|
| 212 |
|
|
|
| 213 |
|
|
--F1_seg7data[5] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[5]
|
| 214 |
|
|
--operation mode is normal
|
| 215 |
|
|
|
| 216 |
|
|
F1_seg7data[5]_lut_out = CB1_r32_o_5;
|
| 217 |
|
|
F1_seg7data[5] = DFFEAS(F1_seg7data[5]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );
|
| 218 |
|
|
|
| 219 |
|
|
|
| 220 |
|
|
--F1_seg7data[4] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[4]
|
| 221 |
|
|
--operation mode is normal
|
| 222 |
|
|
|
| 223 |
|
|
F1_seg7data[4]_lut_out = CB1_r32_o_4;
|
| 224 |
|
|
F1_seg7data[4] = DFFEAS(F1_seg7data[4]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );
|
| 225 |
|
|
|
| 226 |
|
|
|
| 227 |
|
|
--F1_seg7data[7] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[7]
|
| 228 |
|
|
--operation mode is normal
|
| 229 |
|
|
|
| 230 |
|
|
F1_seg7data[7]_lut_out = CB1_r32_o_7;
|
| 231 |
|
|
F1_seg7data[7] = DFFEAS(F1_seg7data[7]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );
|
| 232 |
|
|
|
| 233 |
|
|
|
| 234 |
|
|
--F1_seg7data[2] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[2]
|
| 235 |
|
|
--operation mode is normal
|
| 236 |
|
|
|
| 237 |
|
|
F1_seg7data[2]_lut_out = CB1_r32_o_2;
|
| 238 |
|
|
F1_seg7data[2] = DFFEAS(F1_seg7data[2]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );
|
| 239 |
|
|
|
| 240 |
|
|
|
| 241 |
|
|
--F1_seg7data[1] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[1]
|
| 242 |
|
|
--operation mode is normal
|
| 243 |
|
|
|
| 244 |
|
|
F1_seg7data[1]_lut_out = CB1_r32_o_1;
|
| 245 |
|
|
F1_seg7data[1] = DFFEAS(F1_seg7data[1]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );
|
| 246 |
|
|
|
| 247 |
|
|
|
| 248 |
|
|
--F1_seg7data[0] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[0]
|
| 249 |
|
|
--operation mode is normal
|
| 250 |
|
|
|
| 251 |
|
|
F1_seg7data[0]_lut_out = CB1_r32_o_0;
|
| 252 |
|
|
F1_seg7data[0] = DFFEAS(F1_seg7data[0]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );
|
| 253 |
|
|
|
| 254 |
|
|
|
| 255 |
|
|
--F1_seg7data[3] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[3]
|
| 256 |
|
|
--operation mode is normal
|
| 257 |
|
|
|
| 258 |
|
|
F1_seg7data[3]_lut_out = CB1_r32_o_3;
|
| 259 |
|
|
F1_seg7data[3] = DFFEAS(F1_seg7data[3]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );
|
| 260 |
|
|
|
| 261 |
|
|
|
| 262 |
|
|
--CB1_dout_2_7 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_7
|
| 263 |
|
|
--operation mode is normal
|
| 264 |
|
|
|
| 265 |
|
|
CB1_dout_2_7 = ND1_dout7 & FD1_wb_o_7 # !ND1_dout7 & !ND1_dout_2_a_7;
|
| 266 |
|
|
|
| 267 |
|
|
--CB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_7
|
| 268 |
|
|
--operation mode is normal
|
| 269 |
|
|
|
| 270 |
|
|
CB1_r32_o_7 = DFFEAS(CB1_dout_2_7, E1__clk0, VCC, , , , , , );
|
| 271 |
|
|
|
| 272 |
|
|
|
| 273 |
|
|
--F1_lcd_data_0_sqmuxa_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0_sqmuxa_0_a2
|
| 274 |
|
|
--operation mode is normal
|
| 275 |
|
|
|
| 276 |
|
|
F1_lcd_data_0_sqmuxa_0_a2 = !AB1_r32_o_2 & AB1_r32_o_3 & F1_lcd_data_0_sqmuxa_0_a2_a & F1_wr_cmd_0_a2_0;
|
| 277 |
|
|
|
| 278 |
|
|
|
| 279 |
|
|
--CB1_dout_2_6 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_6
|
| 280 |
|
|
--operation mode is normal
|
| 281 |
|
|
|
| 282 |
|
|
CB1_dout_2_6 = ND1_dout7 & FD1_wb_o_6 # !ND1_dout7 & !ND1_dout_2_a_6;
|
| 283 |
|
|
|
| 284 |
|
|
--CB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_6
|
| 285 |
|
|
--operation mode is normal
|
| 286 |
|
|
|
| 287 |
|
|
CB1_r32_o_6 = DFFEAS(CB1_dout_2_6, E1__clk0, VCC, , , , , , );
|
| 288 |
|
|
|
| 289 |
|
|
|
| 290 |
|
|
--CB1_dout_2_5 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_5
|
| 291 |
|
|
--operation mode is normal
|
| 292 |
|
|
|
| 293 |
|
|
CB1_dout_2_5 = ND1_dout7 & FD1_wb_o_5 # !ND1_dout7 & !ND1_dout_2_a_5;
|
| 294 |
|
|
|
| 295 |
|
|
--CB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_5
|
| 296 |
|
|
--operation mode is normal
|
| 297 |
|
|
|
| 298 |
|
|
CB1_r32_o_5 = DFFEAS(CB1_dout_2_5, E1__clk0, VCC, , , , , , );
|
| 299 |
|
|
|
| 300 |
|
|
|
| 301 |
|
|
--CB1_dout_2_4 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_4
|
| 302 |
|
|
--operation mode is normal
|
| 303 |
|
|
|
| 304 |
|
|
CB1_dout_2_4 = ND1_dout7 & FD1_wb_o_4 # !ND1_dout7 & !ND1_dout_2_a_4;
|
| 305 |
|
|
|
| 306 |
|
|
--CB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_4
|
| 307 |
|
|
--operation mode is normal
|
| 308 |
|
|
|
| 309 |
|
|
CB1_r32_o_4 = DFFEAS(CB1_dout_2_4, E1__clk0, VCC, , , , , , );
|
| 310 |
|
|
|
| 311 |
|
|
|
| 312 |
|
|
--CB1_dout_2_3 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_3
|
| 313 |
|
|
--operation mode is normal
|
| 314 |
|
|
|
| 315 |
|
|
CB1_dout_2_3 = ND1_dout7 & FD1_wb_o_3 # !ND1_dout7 & !ND1_dout_2_a_3;
|
| 316 |
|
|
|
| 317 |
|
|
--CB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_3
|
| 318 |
|
|
--operation mode is normal
|
| 319 |
|
|
|
| 320 |
|
|
CB1_r32_o_3 = DFFEAS(CB1_dout_2_3, E1__clk0, VCC, , , , , , );
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
--CB1_dout_2_2 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_2
|
| 324 |
|
|
--operation mode is normal
|
| 325 |
|
|
|
| 326 |
|
|
CB1_dout_2_2 = ND1_dout7 & FD1_wb_o_2 # !ND1_dout7 & !ND1_dout_2_a_2;
|
| 327 |
|
|
|
| 328 |
|
|
--CB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_2
|
| 329 |
|
|
--operation mode is normal
|
| 330 |
|
|
|
| 331 |
|
|
CB1_r32_o_2 = DFFEAS(CB1_dout_2_2, E1__clk0, VCC, , , , , , );
|
| 332 |
|
|
|
| 333 |
|
|
|
| 334 |
|
|
--CB1_dout_2_1 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_1
|
| 335 |
|
|
--operation mode is normal
|
| 336 |
|
|
|
| 337 |
|
|
CB1_dout_2_1 = ND1_dout7 & FD1_wb_o_1 # !ND1_dout7 & !ND1_dout_2_a_1;
|
| 338 |
|
|
|
| 339 |
|
|
--CB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_1
|
| 340 |
|
|
--operation mode is normal
|
| 341 |
|
|
|
| 342 |
|
|
CB1_r32_o_1 = DFFEAS(CB1_dout_2_1, E1__clk0, VCC, , , , , , );
|
| 343 |
|
|
|
| 344 |
|
|
|
| 345 |
|
|
--CB1_dout_2_0 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_0
|
| 346 |
|
|
--operation mode is normal
|
| 347 |
|
|
|
| 348 |
|
|
CB1_dout_2_0 = ND1_dout7 & FD1_wb_o_0 # !ND1_dout7 & !ND1_dout_2_a_0;
|
| 349 |
|
|
|
| 350 |
|
|
--CB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_0
|
| 351 |
|
|
--operation mode is normal
|
| 352 |
|
|
|
| 353 |
|
|
CB1_r32_o_0 = DFFEAS(CB1_dout_2_0, E1__clk0, VCC, , , , , , );
|
| 354 |
|
|
|
| 355 |
|
|
|
| 356 |
|
|
--C1_G_602 is mips_sys:isys|G_602
|
| 357 |
|
|
--operation mode is normal
|
| 358 |
|
|
|
| 359 |
|
|
C1_G_602 = !AB1_r32_o_3 & F1_wr_tmr_data_0_a2_0 & F1_wr_cmd_0_a2_0 # !sys_rst;
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
--r_rst is r_rst
|
| 363 |
|
|
--operation mode is normal
|
| 364 |
|
|
|
| 365 |
|
|
r_rst_lut_out = rst;
|
| 366 |
|
|
r_rst = DFFEAS(r_rst_lut_out, E1__clk0, VCC, , , , , , );
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
--N1_ua_state[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[1]
|
| 370 |
|
|
--operation mode is normal
|
| 371 |
|
|
|
| 372 |
|
|
N1_ua_state[1]_lut_out = U1_b_non_empty & N1_ua_state[1] & !N1_clk_ctr_equ15_0_a2 # !N1_ua_state_i[0] # !U1_b_non_empty & N1_ua_state[1] & !N1_clk_ctr_equ15_0_a2;
|
| 373 |
|
|
N1_ua_state[1] = DFFEAS(N1_ua_state[1]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 374 |
|
|
|
| 375 |
|
|
|
| 376 |
|
|
--N1_ua_state[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[2]
|
| 377 |
|
|
--operation mode is normal
|
| 378 |
|
|
|
| 379 |
|
|
N1_ua_state[2]_lut_out = N1_clk_ctr_equ15_0_a2 & N1_ua_state[1] # N1_ua_state[2] & N1_ua_state_ns_0_a[2] # !N1_clk_ctr_equ15_0_a2 & N1_ua_state[2];
|
| 380 |
|
|
N1_ua_state[2] = DFFEAS(N1_ua_state[2]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 381 |
|
|
|
| 382 |
|
|
|
| 383 |
|
|
--N1_tx_sr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[0]
|
| 384 |
|
|
--operation mode is normal
|
| 385 |
|
|
|
| 386 |
|
|
N1_tx_sr[0]_lut_out = N1_read_request_ff & Y1_q_b[0] # !N1_read_request_ff & N1_tx_sr[1];
|
| 387 |
|
|
N1_tx_sr[0] = DFFEAS(N1_tx_sr[0]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
--N1_clk_ctr_equ15_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2
|
| 391 |
|
|
--operation mode is normal
|
| 392 |
|
|
|
| 393 |
|
|
N1_clk_ctr_equ15_0_a2 = N1_clk_ctr26_i_0_a2 & N1_clk_ctr_equ15_0_a2_7;
|
| 394 |
|
|
|
| 395 |
|
|
|
| 396 |
|
|
--N1_ua_state_i[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state_i[0]
|
| 397 |
|
|
--operation mode is normal
|
| 398 |
|
|
|
| 399 |
|
|
N1_ua_state_i[0]_lut_out = !N1_ua_state[7] & U1_b_non_empty # N1_ua_state_i[0];
|
| 400 |
|
|
N1_ua_state_i[0] = DFFEAS(N1_ua_state_i[0]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 401 |
|
|
|
| 402 |
|
|
|
| 403 |
|
|
--N1_bit_ctr23_i_0_o2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr23_i_0_o2
|
| 404 |
|
|
--operation mode is normal
|
| 405 |
|
|
|
| 406 |
|
|
N1_bit_ctr23_i_0_o2 = N1_ua_state[3] # N1_ua_state[2];
|
| 407 |
|
|
|
| 408 |
|
|
|
| 409 |
|
|
--C1_G_594 is mips_sys:isys|G_594
|
| 410 |
|
|
--operation mode is normal
|
| 411 |
|
|
|
| 412 |
|
|
C1_G_594 = !AB1_r32_o_3 & C1_G_594_a & F1_wr_cmd_0_a2_0 # !sys_rst;
|
| 413 |
|
|
|
| 414 |
|
|
|
| 415 |
|
|
--FD1_wb_o_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_7
|
| 416 |
|
|
--operation mode is normal
|
| 417 |
|
|
|
| 418 |
|
|
FD1_wb_o_7 = TC1_wb_mux_ctl_o_0 & F1_dout_7 # DB1_r32_o_7 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_7;
|
| 419 |
|
|
|
| 420 |
|
|
--FD1_r_data_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_7
|
| 421 |
|
|
--operation mode is normal
|
| 422 |
|
|
|
| 423 |
|
|
FD1_r_data_7 = DFFEAS(FD1_wb_o_7, E1__clk0, VCC, , , , , , );
|
| 424 |
|
|
|
| 425 |
|
|
|
| 426 |
|
|
--ND1_dout_2_a_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_7
|
| 427 |
|
|
--operation mode is normal
|
| 428 |
|
|
|
| 429 |
|
|
ND1_dout_2_a_7 = XD1_mux_fw_1 & !AB1_r32_o_5 # !XD1_mux_fw_1 & !QB1_r32_o_7;
|
| 430 |
|
|
|
| 431 |
|
|
|
| 432 |
|
|
--ND1_dout7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout7
|
| 433 |
|
|
--operation mode is normal
|
| 434 |
|
|
|
| 435 |
|
|
ND1_dout7 = MC1_wb_we_o_0 & !WD1_un30_mux_fw & !XD1_un17_mux_fw_NE & !XD1_mux_fw_1;
|
| 436 |
|
|
|
| 437 |
|
|
|
| 438 |
|
|
--AB1_c_2 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_2
|
| 439 |
|
|
--operation mode is normal
|
| 440 |
|
|
|
| 441 |
|
|
AB1_c_2 = MD1_c_1_4 # UD1_shift_out_4 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add4;
|
| 442 |
|
|
|
| 443 |
|
|
--AB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_2
|
| 444 |
|
|
--operation mode is normal
|
| 445 |
|
|
|
| 446 |
|
|
AB1_r32_o_2 = DFFEAS(AB1_c_2, E1__clk0, VCC, , , , , , );
|
| 447 |
|
|
|
| 448 |
|
|
|
| 449 |
|
|
--AB1_c_3 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_3
|
| 450 |
|
|
--operation mode is normal
|
| 451 |
|
|
|
| 452 |
|
|
AB1_c_3 = MD1_c_2_5 # UD1_shift_out_5 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add5;
|
| 453 |
|
|
|
| 454 |
|
|
--AB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_3
|
| 455 |
|
|
--operation mode is normal
|
| 456 |
|
|
|
| 457 |
|
|
AB1_r32_o_3 = DFFEAS(AB1_c_3, E1__clk0, VCC, , , , , , );
|
| 458 |
|
|
|
| 459 |
|
|
|
| 460 |
|
|
--F1_lcd_data_0_sqmuxa_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0_sqmuxa_0_a2_a
|
| 461 |
|
|
--operation mode is normal
|
| 462 |
|
|
|
| 463 |
|
|
F1_lcd_data_0_sqmuxa_0_a2_a = sys_rst & !JC1_dmem_ctl_o_2 & AB1_r32_o_0 & !AB1_r32_o_1;
|
| 464 |
|
|
|
| 465 |
|
|
|
| 466 |
|
|
--F1_wr_cmd_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|wr_cmd_0_a2_0
|
| 467 |
|
|
--operation mode is normal
|
| 468 |
|
|
|
| 469 |
|
|
F1_wr_cmd_0_a2_0 = JC1_dmem_ctl_o_0 & !JC1_dmem_ctl_o_1 & F1_rd_uartdata_0_a2_0;
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
--FD1_wb_o_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_6
|
| 473 |
|
|
--operation mode is normal
|
| 474 |
|
|
|
| 475 |
|
|
FD1_wb_o_6 = TC1_wb_mux_ctl_o_0 & F1_dout_6 # DB1_r32_o_6 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_6;
|
| 476 |
|
|
|
| 477 |
|
|
--FD1_r_data_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_6
|
| 478 |
|
|
--operation mode is normal
|
| 479 |
|
|
|
| 480 |
|
|
FD1_r_data_6 = DFFEAS(FD1_wb_o_6, E1__clk0, VCC, , , , , , );
|
| 481 |
|
|
|
| 482 |
|
|
|
| 483 |
|
|
--ND1_dout_2_a_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_6
|
| 484 |
|
|
--operation mode is normal
|
| 485 |
|
|
|
| 486 |
|
|
ND1_dout_2_a_6 = XD1_mux_fw_1 & !AB1_r32_o_4 # !XD1_mux_fw_1 & !QB1_r32_o_6;
|
| 487 |
|
|
|
| 488 |
|
|
|
| 489 |
|
|
--FD1_wb_o_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_5
|
| 490 |
|
|
--operation mode is normal
|
| 491 |
|
|
|
| 492 |
|
|
FD1_wb_o_5 = TC1_wb_mux_ctl_o_0 & F1_dout_5 # DB1_r32_o_5 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_5;
|
| 493 |
|
|
|
| 494 |
|
|
--FD1_r_data_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_5
|
| 495 |
|
|
--operation mode is normal
|
| 496 |
|
|
|
| 497 |
|
|
FD1_r_data_5 = DFFEAS(FD1_wb_o_5, E1__clk0, VCC, , , , , , );
|
| 498 |
|
|
|
| 499 |
|
|
|
| 500 |
|
|
--ND1_dout_2_a_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_5
|
| 501 |
|
|
--operation mode is normal
|
| 502 |
|
|
|
| 503 |
|
|
ND1_dout_2_a_5 = XD1_mux_fw_1 & !AB1_r32_o_3 # !XD1_mux_fw_1 & !QB1_r32_o_5;
|
| 504 |
|
|
|
| 505 |
|
|
|
| 506 |
|
|
--FD1_wb_o_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_4
|
| 507 |
|
|
--operation mode is normal
|
| 508 |
|
|
|
| 509 |
|
|
FD1_wb_o_4 = TC1_wb_mux_ctl_o_0 & F1_dout_4 # DB1_r32_o_4 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_4;
|
| 510 |
|
|
|
| 511 |
|
|
--FD1_r_data_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_4
|
| 512 |
|
|
--operation mode is normal
|
| 513 |
|
|
|
| 514 |
|
|
FD1_r_data_4 = DFFEAS(FD1_wb_o_4, E1__clk0, VCC, , , , , , );
|
| 515 |
|
|
|
| 516 |
|
|
|
| 517 |
|
|
--ND1_dout_2_a_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_4
|
| 518 |
|
|
--operation mode is normal
|
| 519 |
|
|
|
| 520 |
|
|
ND1_dout_2_a_4 = XD1_mux_fw_1 & !AB1_r32_o_2 # !XD1_mux_fw_1 & !QB1_r32_o_4;
|
| 521 |
|
|
|
| 522 |
|
|
|
| 523 |
|
|
--FD1_wb_o_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_3
|
| 524 |
|
|
--operation mode is normal
|
| 525 |
|
|
|
| 526 |
|
|
FD1_wb_o_3 = TC1_wb_mux_ctl_o_0 & F1_dout_3 # DB1_r32_o_3 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_3;
|
| 527 |
|
|
|
| 528 |
|
|
--FD1_r_data_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_3
|
| 529 |
|
|
--operation mode is normal
|
| 530 |
|
|
|
| 531 |
|
|
FD1_r_data_3 = DFFEAS(FD1_wb_o_3, E1__clk0, VCC, , , , , , );
|
| 532 |
|
|
|
| 533 |
|
|
|
| 534 |
|
|
--ND1_dout_2_a_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_3
|
| 535 |
|
|
--operation mode is normal
|
| 536 |
|
|
|
| 537 |
|
|
ND1_dout_2_a_3 = XD1_mux_fw_1 & !AB1_r32_o_1 # !XD1_mux_fw_1 & !QB1_r32_o_3;
|
| 538 |
|
|
|
| 539 |
|
|
|
| 540 |
|
|
--FD1_wb_o_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_2
|
| 541 |
|
|
--operation mode is normal
|
| 542 |
|
|
|
| 543 |
|
|
FD1_wb_o_2 = TC1_wb_mux_ctl_o_0 & F1_dout_2 # DB1_r32_o_2 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_2;
|
| 544 |
|
|
|
| 545 |
|
|
--FD1_r_data_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_2
|
| 546 |
|
|
--operation mode is normal
|
| 547 |
|
|
|
| 548 |
|
|
FD1_r_data_2 = DFFEAS(FD1_wb_o_2, E1__clk0, VCC, , , , , , );
|
| 549 |
|
|
|
| 550 |
|
|
|
| 551 |
|
|
--ND1_dout_2_a_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_2
|
| 552 |
|
|
--operation mode is normal
|
| 553 |
|
|
|
| 554 |
|
|
ND1_dout_2_a_2 = XD1_mux_fw_1 & !AB1_r32_o_0 # !XD1_mux_fw_1 & !QB1_r32_o_2;
|
| 555 |
|
|
|
| 556 |
|
|
|
| 557 |
|
|
--FD1_wb_o_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_1
|
| 558 |
|
|
--operation mode is normal
|
| 559 |
|
|
|
| 560 |
|
|
FD1_wb_o_1 = TC1_wb_mux_ctl_o_0 & F1_dout_1 # DB1_r32_o_1 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_1;
|
| 561 |
|
|
|
| 562 |
|
|
--FD1_r_data_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_1
|
| 563 |
|
|
--operation mode is normal
|
| 564 |
|
|
|
| 565 |
|
|
FD1_r_data_1 = DFFEAS(FD1_wb_o_1, E1__clk0, VCC, , , , , , );
|
| 566 |
|
|
|
| 567 |
|
|
|
| 568 |
|
|
--ND1_dout_2_a_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_1
|
| 569 |
|
|
--operation mode is normal
|
| 570 |
|
|
|
| 571 |
|
|
ND1_dout_2_a_1 = XD1_mux_fw_1 & !RB1_byte_addr_o_1 # !XD1_mux_fw_1 & !QB1_r32_o_1;
|
| 572 |
|
|
|
| 573 |
|
|
|
| 574 |
|
|
--FD1_wb_o_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_0
|
| 575 |
|
|
--operation mode is normal
|
| 576 |
|
|
|
| 577 |
|
|
FD1_wb_o_0 = TC1_wb_mux_ctl_o_0 & F1_dout_0 # DB1_r32_o_0 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_0;
|
| 578 |
|
|
|
| 579 |
|
|
--FD1_r_data_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_0
|
| 580 |
|
|
--operation mode is normal
|
| 581 |
|
|
|
| 582 |
|
|
FD1_r_data_0 = DFFEAS(FD1_wb_o_0, E1__clk0, VCC, , , , , , );
|
| 583 |
|
|
|
| 584 |
|
|
|
| 585 |
|
|
--ND1_dout_2_a_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_0
|
| 586 |
|
|
--operation mode is normal
|
| 587 |
|
|
|
| 588 |
|
|
ND1_dout_2_a_0 = XD1_mux_fw_1 & !RB1_byte_addr_o_0 # !XD1_mux_fw_1 & !QB1_r32_o_0;
|
| 589 |
|
|
|
| 590 |
|
|
|
| 591 |
|
|
--F1_wr_tmr_data_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|wr_tmr_data_0_a2_0
|
| 592 |
|
|
--operation mode is normal
|
| 593 |
|
|
|
| 594 |
|
|
F1_wr_tmr_data_0_a2_0 = JC1_dmem_ctl_o_2 & AB1_r32_o_0 & !AB1_r32_o_1 & AB1_r32_o_2;
|
| 595 |
|
|
|
| 596 |
|
|
|
| 597 |
|
|
--U1_b_non_empty is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_non_empty
|
| 598 |
|
|
--operation mode is normal
|
| 599 |
|
|
|
| 600 |
|
|
U1_b_non_empty_lut_out = F1_wr_uartdata_0_a2 # U1_b_full # U1_b_non_empty & U1L9;
|
| 601 |
|
|
U1_b_non_empty = DFFEAS(U1_b_non_empty_lut_out, E1__clk0, VCC, , , , , , );
|
| 602 |
|
|
|
| 603 |
|
|
|
| 604 |
|
|
--N1_ua_state_ns_0_a[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state_ns_0_a[2]
|
| 605 |
|
|
--operation mode is normal
|
| 606 |
|
|
|
| 607 |
|
|
N1_ua_state_ns_0_a[2] = !N1_bit_ctr[0] # !N1_bit_ctr[2] # !N1_bit_ctr[1];
|
| 608 |
|
|
|
| 609 |
|
|
|
| 610 |
|
|
--Y1_q_b[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[0]
|
| 611 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 612 |
|
|
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
|
| 613 |
|
|
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
|
| 614 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 615 |
|
|
Y1_q_b[0]_PORT_A_data_in = CB1_r32_o_0;
|
| 616 |
|
|
Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );
|
| 617 |
|
|
Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
|
| 618 |
|
|
Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );
|
| 619 |
|
|
Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
|
| 620 |
|
|
Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
|
| 621 |
|
|
Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;
|
| 622 |
|
|
Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );
|
| 623 |
|
|
Y1_q_b[0]_PORT_B_read_enable = VCC;
|
| 624 |
|
|
Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
|
| 625 |
|
|
Y1_q_b[0]_clock_0 = E1__clk0;
|
| 626 |
|
|
Y1_q_b[0]_clock_1 = E1__clk0;
|
| 627 |
|
|
Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;
|
| 628 |
|
|
Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );
|
| 629 |
|
|
Y1_q_b[0] = Y1_q_b[0]_PORT_B_data_out[0];
|
| 630 |
|
|
|
| 631 |
|
|
|
| 632 |
|
|
--N1_tx_sr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[1]
|
| 633 |
|
|
--operation mode is normal
|
| 634 |
|
|
|
| 635 |
|
|
N1_tx_sr[1]_lut_out = N1_read_request_ff & Y1_q_b[1] # !N1_read_request_ff & N1_tx_sr[2];
|
| 636 |
|
|
N1_tx_sr[1] = DFFEAS(N1_tx_sr[1]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );
|
| 637 |
|
|
|
| 638 |
|
|
|
| 639 |
|
|
--N1_read_request_ff is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|read_request_ff
|
| 640 |
|
|
--operation mode is normal
|
| 641 |
|
|
|
| 642 |
|
|
N1_read_request_ff_lut_out = U1_b_non_empty & !N1_ua_state_i[0];
|
| 643 |
|
|
N1_read_request_ff = DFFEAS(N1_read_request_ff_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 644 |
|
|
|
| 645 |
|
|
|
| 646 |
|
|
--C1_G_586 is mips_sys:isys|G_586
|
| 647 |
|
|
--operation mode is normal
|
| 648 |
|
|
|
| 649 |
|
|
C1_G_586 = N1_read_request_ff # N1_bit_ctr23_i_0_o2 & N1_clk_ctr_equ15_0_a2 # !sys_rst;
|
| 650 |
|
|
|
| 651 |
|
|
|
| 652 |
|
|
--N1_clk_ctr26_i_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a2
|
| 653 |
|
|
--operation mode is normal
|
| 654 |
|
|
|
| 655 |
|
|
N1_clk_ctr26_i_0_a2 = !N1_clk_ctr[15] & !N1_clk_ctr[6] & N1_clk_ctr[0] & N1_clk_ctr26_i_0_a2_a;
|
| 656 |
|
|
|
| 657 |
|
|
|
| 658 |
|
|
--N1_clk_ctr_equ15_0_a2_7 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2_7
|
| 659 |
|
|
--operation mode is normal
|
| 660 |
|
|
|
| 661 |
|
|
N1_clk_ctr_equ15_0_a2_7 = !N1_clk_ctr[5] & N1_clk_ctr[4] & N1_clk_ctr_equ15_0_a2_4 & N1_clk_ctr_equ15_0_a2_7_a;
|
| 662 |
|
|
|
| 663 |
|
|
|
| 664 |
|
|
--N1_ua_state[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[7]
|
| 665 |
|
|
--operation mode is normal
|
| 666 |
|
|
|
| 667 |
|
|
N1_ua_state[7]_lut_out = N1_ua_state[6] & N1_clk_ctr_equ15_0_a2;
|
| 668 |
|
|
N1_ua_state[7] = DFFEAS(N1_ua_state[7]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 669 |
|
|
|
| 670 |
|
|
|
| 671 |
|
|
--N1_ua_state[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[3]
|
| 672 |
|
|
--operation mode is normal
|
| 673 |
|
|
|
| 674 |
|
|
N1_ua_state[3]_lut_out = N1_ua_state[3] & !N1_clk_ctr_equ15_0_a2 # !N1_ua_state[3] & N1_ua_state[2] & !N1_ua_state_ns_0_a[2] & N1_clk_ctr_equ15_0_a2;
|
| 675 |
|
|
N1_ua_state[3] = DFFEAS(N1_ua_state[3]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 676 |
|
|
|
| 677 |
|
|
|
| 678 |
|
|
--C1_G_594_a is mips_sys:isys|G_594_a
|
| 679 |
|
|
--operation mode is normal
|
| 680 |
|
|
|
| 681 |
|
|
C1_G_594_a = !JC1_dmem_ctl_o_2 & AB1_r32_o_0 & AB1_r32_o_1 & AB1_r32_o_2;
|
| 682 |
|
|
|
| 683 |
|
|
|
| 684 |
|
|
--F1_dout_7 is mips_sys:isys|mips_dvc:imips_dvc|dout_7
|
| 685 |
|
|
--operation mode is normal
|
| 686 |
|
|
|
| 687 |
|
|
F1_dout_7_lut_out = K1_cntr_7 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[7];
|
| 688 |
|
|
F1_dout_7 = DFFEAS(F1_dout_7_lut_out, E1__clk0, VCC, , , , , , );
|
| 689 |
|
|
|
| 690 |
|
|
|
| 691 |
|
|
--DB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_7
|
| 692 |
|
|
--operation mode is normal
|
| 693 |
|
|
|
| 694 |
|
|
DB1_r32_o_7_lut_out = WB21L1;
|
| 695 |
|
|
DB1_r32_o_7 = DFFEAS(DB1_r32_o_7_lut_out, E1__clk0, VCC, , , , , , );
|
| 696 |
|
|
|
| 697 |
|
|
|
| 698 |
|
|
--BB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_7
|
| 699 |
|
|
--operation mode is normal
|
| 700 |
|
|
|
| 701 |
|
|
BB1_r32_o_7_lut_out = AB1_r32_o_5;
|
| 702 |
|
|
BB1_r32_o_7 = DFFEAS(BB1_r32_o_7_lut_out, E1__clk0, VCC, , , , , , );
|
| 703 |
|
|
|
| 704 |
|
|
|
| 705 |
|
|
--TC1_wb_mux_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg:U18|wb_mux_ctl_o_0
|
| 706 |
|
|
--operation mode is normal
|
| 707 |
|
|
|
| 708 |
|
|
TC1_wb_mux_ctl_o_0_lut_out = WC1_wb_mux_ctl_o_0;
|
| 709 |
|
|
TC1_wb_mux_ctl_o_0 = DFFEAS(TC1_wb_mux_ctl_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 710 |
|
|
|
| 711 |
|
|
|
| 712 |
|
|
--QB1_dout_iv_7 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_7
|
| 713 |
|
|
--operation mode is normal
|
| 714 |
|
|
|
| 715 |
|
|
QB1_dout_iv_7 = GD1_dout_iv_1_7 # FD1_wb_o_7 & GD1_dout7_0_a2;
|
| 716 |
|
|
|
| 717 |
|
|
--QB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_7
|
| 718 |
|
|
--operation mode is normal
|
| 719 |
|
|
|
| 720 |
|
|
QB1_r32_o_7 = DFFEAS(QB1_dout_iv_7, E1__clk0, VCC, , , , , , );
|
| 721 |
|
|
|
| 722 |
|
|
|
| 723 |
|
|
--AB1_c_5 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_5
|
| 724 |
|
|
--operation mode is normal
|
| 725 |
|
|
|
| 726 |
|
|
AB1_c_5 = MD1_c_0_6 # UD1_shift_out_sn_m31_i & !MD1_c_a_7 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_6;
|
| 727 |
|
|
|
| 728 |
|
|
--AB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_5
|
| 729 |
|
|
--operation mode is normal
|
| 730 |
|
|
|
| 731 |
|
|
AB1_r32_o_5 = DFFEAS(AB1_c_5, E1__clk0, VCC, , , , , , );
|
| 732 |
|
|
|
| 733 |
|
|
|
| 734 |
|
|
--XD1_mux_fw_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|mux_fw_1
|
| 735 |
|
|
--operation mode is normal
|
| 736 |
|
|
|
| 737 |
|
|
XD1_mux_fw_1 = !XD1_mux_fw_1_a & !XD1_un1_mux_fw_NE_2 & !XD1_un1_mux_fw_NE_1 & !WD1_un14_mux_fw;
|
| 738 |
|
|
|
| 739 |
|
|
|
| 740 |
|
|
--MC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg:U12|wb_we_o_0
|
| 741 |
|
|
--operation mode is normal
|
| 742 |
|
|
|
| 743 |
|
|
MC1_wb_we_o_0_lut_out = VC1_wb_we_o_0 # XC1_wb_we_o_0;
|
| 744 |
|
|
MC1_wb_we_o_0 = DFFEAS(MC1_wb_we_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 745 |
|
|
|
| 746 |
|
|
|
| 747 |
|
|
--WD1_un30_mux_fw is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un30_mux_fw
|
| 748 |
|
|
--operation mode is normal
|
| 749 |
|
|
|
| 750 |
|
|
WD1_un30_mux_fw = !NB1_r5_o_3 & !NB1_r5_o_0 & !NB1_r5_o_1 & WD1_un30_mux_fw_a;
|
| 751 |
|
|
|
| 752 |
|
|
|
| 753 |
|
|
--XD1_un17_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un17_mux_fw_NE
|
| 754 |
|
|
--operation mode is normal
|
| 755 |
|
|
|
| 756 |
|
|
XD1_un17_mux_fw_NE = XD1_un17_mux_fw_NE_1 # XD1_un17_mux_fw_NE_a # BE1_q_4 $ NB1_r5_o_4;
|
| 757 |
|
|
|
| 758 |
|
|
|
| 759 |
|
|
--TD1_alu_out_sn_m14_0_0_a4_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0_a4_0
|
| 760 |
|
|
--operation mode is normal
|
| 761 |
|
|
|
| 762 |
|
|
TD1_alu_out_sn_m14_0_0_a4_0 = !TD1_alu_out_sn_m14_0_0_a4_0_a & !RC1_alu_func_o_4 & RC1_alu_func_o_1 # !RC1_alu_func_o_0;
|
| 763 |
|
|
|
| 764 |
|
|
|
| 765 |
|
|
--MD1_c_1_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_4
|
| 766 |
|
|
--operation mode is normal
|
| 767 |
|
|
|
| 768 |
|
|
MD1_c_1_4 = MD1_c_0_Z[4] # TD1_alu_out_sn_m14_0_0 & TD1_alu_out_7_0_0_m2_1;
|
| 769 |
|
|
|
| 770 |
|
|
|
| 771 |
|
|
--TD1_un1_a_add4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add4
|
| 772 |
|
|
--operation mode is arithmetic
|
| 773 |
|
|
|
| 774 |
|
|
TD1_un1_a_add4_carry_eqn = TD1_un1_a_carry_3;
|
| 775 |
|
|
TD1_un1_a_add4 = PD1_a_o_4 $ TD1_un1_b_1_combout[4] $ !TD1_un1_a_add4_carry_eqn;
|
| 776 |
|
|
|
| 777 |
|
|
--TD1_un1_a_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_4
|
| 778 |
|
|
--operation mode is arithmetic
|
| 779 |
|
|
|
| 780 |
|
|
TD1_un1_a_carry_4 = CARRY(PD1_a_o_4 & TD1_un1_b_1_combout[4] # !TD1_un1_a_carry_3 # !PD1_a_o_4 & TD1_un1_b_1_combout[4] & !TD1_un1_a_carry_3);
|
| 781 |
|
|
|
| 782 |
|
|
|
| 783 |
|
|
--UD1_shift_out_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_4
|
| 784 |
|
|
--operation mode is normal
|
| 785 |
|
|
|
| 786 |
|
|
UD1_shift_out_4 = UD1_shift_out_sn_m31_i & !UD1_shift_out_a[4] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[4];
|
| 787 |
|
|
|
| 788 |
|
|
|
| 789 |
|
|
--MD1_c_2_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_5
|
| 790 |
|
|
--operation mode is normal
|
| 791 |
|
|
|
| 792 |
|
|
MD1_c_2_5 = MD1_c_0_Z[5] # TD1_alu_out_sn_m14_0_0 & MD1_c_2_a[5] # TD1_alu_out_7_0_0_m2_2;
|
| 793 |
|
|
|
| 794 |
|
|
|
| 795 |
|
|
--TD1_un1_a_add5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add5
|
| 796 |
|
|
--operation mode is arithmetic
|
| 797 |
|
|
|
| 798 |
|
|
TD1_un1_a_add5_carry_eqn = TD1_un1_a_carry_4;
|
| 799 |
|
|
TD1_un1_a_add5 = PD1_a_o_5 $ TD1_un1_b_1_combout[5] $ TD1_un1_a_add5_carry_eqn;
|
| 800 |
|
|
|
| 801 |
|
|
--TD1_un1_a_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_5
|
| 802 |
|
|
--operation mode is arithmetic
|
| 803 |
|
|
|
| 804 |
|
|
TD1_un1_a_carry_5 = CARRY(PD1_a_o_5 & !TD1_un1_b_1_combout[5] & !TD1_un1_a_carry_4 # !PD1_a_o_5 & !TD1_un1_a_carry_4 # !TD1_un1_b_1_combout[5]);
|
| 805 |
|
|
|
| 806 |
|
|
|
| 807 |
|
|
--UD1_shift_out_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_5
|
| 808 |
|
|
--operation mode is normal
|
| 809 |
|
|
|
| 810 |
|
|
UD1_shift_out_5 = UD1_shift_out_sn_m31_i & !UD1_shift_out_a[5] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[5];
|
| 811 |
|
|
|
| 812 |
|
|
|
| 813 |
|
|
--JC1_dmem_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_2
|
| 814 |
|
|
--operation mode is normal
|
| 815 |
|
|
|
| 816 |
|
|
JC1_dmem_ctl_o_2_lut_out = QC1_dmem_ctl_o_2;
|
| 817 |
|
|
JC1_dmem_ctl_o_2 = DFFEAS(JC1_dmem_ctl_o_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 818 |
|
|
|
| 819 |
|
|
|
| 820 |
|
|
--AB1_c_0 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_0
|
| 821 |
|
|
--operation mode is normal
|
| 822 |
|
|
|
| 823 |
|
|
AB1_c_0 = MD1_c_0_1 # UD1_shift_out_sn_m31_i & !MD1_c_a_2 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_1;
|
| 824 |
|
|
|
| 825 |
|
|
--AB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_0
|
| 826 |
|
|
--operation mode is normal
|
| 827 |
|
|
|
| 828 |
|
|
AB1_r32_o_0 = DFFEAS(AB1_c_0, E1__clk0, VCC, , , , , , );
|
| 829 |
|
|
|
| 830 |
|
|
|
| 831 |
|
|
--AB1_c_1 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_1
|
| 832 |
|
|
--operation mode is normal
|
| 833 |
|
|
|
| 834 |
|
|
AB1_c_1 = MD1_c_1_3 # UD1_shift_out_3 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add3;
|
| 835 |
|
|
|
| 836 |
|
|
--AB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_1
|
| 837 |
|
|
--operation mode is normal
|
| 838 |
|
|
|
| 839 |
|
|
AB1_r32_o_1 = DFFEAS(AB1_c_1, E1__clk0, VCC, , , , , , );
|
| 840 |
|
|
|
| 841 |
|
|
|
| 842 |
|
|
--JC1_dmem_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_0
|
| 843 |
|
|
--operation mode is normal
|
| 844 |
|
|
|
| 845 |
|
|
JC1_dmem_ctl_o_0_lut_out = QC1_dmem_ctl_o_0;
|
| 846 |
|
|
JC1_dmem_ctl_o_0 = DFFEAS(JC1_dmem_ctl_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 847 |
|
|
|
| 848 |
|
|
|
| 849 |
|
|
--JC1_dmem_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_1
|
| 850 |
|
|
--operation mode is normal
|
| 851 |
|
|
|
| 852 |
|
|
JC1_dmem_ctl_o_1_lut_out = QC1_dmem_ctl_o_1;
|
| 853 |
|
|
JC1_dmem_ctl_o_1 = DFFEAS(JC1_dmem_ctl_o_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 854 |
|
|
|
| 855 |
|
|
|
| 856 |
|
|
--F1_rd_uartdata_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|rd_uartdata_0_a2_0
|
| 857 |
|
|
--operation mode is normal
|
| 858 |
|
|
|
| 859 |
|
|
F1_rd_uartdata_0_a2_0 = F1_dout_0_0_a3_6_5_9[0] & F1_rd_status_29_0_a2_0_8 & F1_dout_0_0_a3_6_5_12[0] & F1_rd_uartdata_0_a2_0_a;
|
| 860 |
|
|
|
| 861 |
|
|
|
| 862 |
|
|
--F1_dout_6 is mips_sys:isys|mips_dvc:imips_dvc|dout_6
|
| 863 |
|
|
--operation mode is normal
|
| 864 |
|
|
|
| 865 |
|
|
F1_dout_6_lut_out = K1_cntr_6 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[6];
|
| 866 |
|
|
F1_dout_6 = DFFEAS(F1_dout_6_lut_out, E1__clk0, VCC, , , , , , );
|
| 867 |
|
|
|
| 868 |
|
|
|
| 869 |
|
|
--DB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_6
|
| 870 |
|
|
--operation mode is normal
|
| 871 |
|
|
|
| 872 |
|
|
DB1_r32_o_6_lut_out = WB11L1;
|
| 873 |
|
|
DB1_r32_o_6 = DFFEAS(DB1_r32_o_6_lut_out, E1__clk0, VCC, , , , , , );
|
| 874 |
|
|
|
| 875 |
|
|
|
| 876 |
|
|
--BB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_6
|
| 877 |
|
|
--operation mode is normal
|
| 878 |
|
|
|
| 879 |
|
|
BB1_r32_o_6_lut_out = AB1_r32_o_4;
|
| 880 |
|
|
BB1_r32_o_6 = DFFEAS(BB1_r32_o_6_lut_out, E1__clk0, VCC, , , , , , );
|
| 881 |
|
|
|
| 882 |
|
|
|
| 883 |
|
|
--QB1_dout_iv_6 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_6
|
| 884 |
|
|
--operation mode is normal
|
| 885 |
|
|
|
| 886 |
|
|
QB1_dout_iv_6 = GD1_dout_iv_1_6 # FD1_wb_o_6 & GD1_dout7_0_a2;
|
| 887 |
|
|
|
| 888 |
|
|
--QB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_6
|
| 889 |
|
|
--operation mode is normal
|
| 890 |
|
|
|
| 891 |
|
|
QB1_r32_o_6 = DFFEAS(QB1_dout_iv_6, E1__clk0, VCC, , , , , , );
|
| 892 |
|
|
|
| 893 |
|
|
|
| 894 |
|
|
--AB1_c_4 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_4
|
| 895 |
|
|
--operation mode is normal
|
| 896 |
|
|
|
| 897 |
|
|
AB1_c_4 = UD1_shift_out_sn_m31_i & UD1_shift_out_92_0 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_5 # !MD1_c_a_6;
|
| 898 |
|
|
|
| 899 |
|
|
--AB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_4
|
| 900 |
|
|
--operation mode is normal
|
| 901 |
|
|
|
| 902 |
|
|
AB1_r32_o_4 = DFFEAS(AB1_c_4, E1__clk0, VCC, , , , , , );
|
| 903 |
|
|
|
| 904 |
|
|
|
| 905 |
|
|
--F1_dout_5 is mips_sys:isys|mips_dvc:imips_dvc|dout_5
|
| 906 |
|
|
--operation mode is normal
|
| 907 |
|
|
|
| 908 |
|
|
F1_dout_5_lut_out = K1_cntr_5 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[5];
|
| 909 |
|
|
F1_dout_5 = DFFEAS(F1_dout_5_lut_out, E1__clk0, VCC, , , , , , );
|
| 910 |
|
|
|
| 911 |
|
|
|
| 912 |
|
|
--DB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_5
|
| 913 |
|
|
--operation mode is normal
|
| 914 |
|
|
|
| 915 |
|
|
DB1_r32_o_5_lut_out = WB01L1;
|
| 916 |
|
|
DB1_r32_o_5 = DFFEAS(DB1_r32_o_5_lut_out, E1__clk0, VCC, , , , , , );
|
| 917 |
|
|
|
| 918 |
|
|
|
| 919 |
|
|
--BB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_5
|
| 920 |
|
|
--operation mode is normal
|
| 921 |
|
|
|
| 922 |
|
|
BB1_r32_o_5_lut_out = AB1_r32_o_3;
|
| 923 |
|
|
BB1_r32_o_5 = DFFEAS(BB1_r32_o_5_lut_out, E1__clk0, VCC, , , , , , );
|
| 924 |
|
|
|
| 925 |
|
|
|
| 926 |
|
|
--QB1_dout_iv_5 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_5
|
| 927 |
|
|
--operation mode is normal
|
| 928 |
|
|
|
| 929 |
|
|
QB1_dout_iv_5 = GD1_dout_iv_1_5 # FD1_wb_o_5 & GD1_dout7_0_a2;
|
| 930 |
|
|
|
| 931 |
|
|
--QB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_5
|
| 932 |
|
|
--operation mode is normal
|
| 933 |
|
|
|
| 934 |
|
|
QB1_r32_o_5 = DFFEAS(QB1_dout_iv_5, E1__clk0, VCC, , , , , , );
|
| 935 |
|
|
|
| 936 |
|
|
|
| 937 |
|
|
--F1_dout_4 is mips_sys:isys|mips_dvc:imips_dvc|dout_4
|
| 938 |
|
|
--operation mode is normal
|
| 939 |
|
|
|
| 940 |
|
|
F1_dout_4_lut_out = K1_cntr_4 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[4];
|
| 941 |
|
|
F1_dout_4 = DFFEAS(F1_dout_4_lut_out, E1__clk0, VCC, , , , , , );
|
| 942 |
|
|
|
| 943 |
|
|
|
| 944 |
|
|
--DB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_4
|
| 945 |
|
|
--operation mode is normal
|
| 946 |
|
|
|
| 947 |
|
|
DB1_r32_o_4_lut_out = WB9L1;
|
| 948 |
|
|
DB1_r32_o_4 = DFFEAS(DB1_r32_o_4_lut_out, E1__clk0, VCC, , , , , , );
|
| 949 |
|
|
|
| 950 |
|
|
|
| 951 |
|
|
--BB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_4
|
| 952 |
|
|
--operation mode is normal
|
| 953 |
|
|
|
| 954 |
|
|
BB1_r32_o_4_lut_out = AB1_r32_o_2;
|
| 955 |
|
|
BB1_r32_o_4 = DFFEAS(BB1_r32_o_4_lut_out, E1__clk0, VCC, , , , , , );
|
| 956 |
|
|
|
| 957 |
|
|
|
| 958 |
|
|
--QB1_dout_iv_4 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_4
|
| 959 |
|
|
--operation mode is normal
|
| 960 |
|
|
|
| 961 |
|
|
QB1_dout_iv_4 = GD1_dout_iv_1_4 # FD1_wb_o_4 & GD1_dout7_0_a2;
|
| 962 |
|
|
|
| 963 |
|
|
--QB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_4
|
| 964 |
|
|
--operation mode is normal
|
| 965 |
|
|
|
| 966 |
|
|
QB1_r32_o_4 = DFFEAS(QB1_dout_iv_4, E1__clk0, VCC, , , , , , );
|
| 967 |
|
|
|
| 968 |
|
|
|
| 969 |
|
|
--F1_dout_3 is mips_sys:isys|mips_dvc:imips_dvc|dout_3
|
| 970 |
|
|
--operation mode is normal
|
| 971 |
|
|
|
| 972 |
|
|
F1_dout_3_lut_out = F1_dout_0_0_a3_0[3] # K1_cntr_3 & F1_dout_0_0_a3_4[0] # !L1_dout_0_0_a_0;
|
| 973 |
|
|
F1_dout_3 = DFFEAS(F1_dout_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 974 |
|
|
|
| 975 |
|
|
|
| 976 |
|
|
--DB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_3
|
| 977 |
|
|
--operation mode is normal
|
| 978 |
|
|
|
| 979 |
|
|
DB1_r32_o_3_lut_out = WB8L1;
|
| 980 |
|
|
DB1_r32_o_3 = DFFEAS(DB1_r32_o_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 981 |
|
|
|
| 982 |
|
|
|
| 983 |
|
|
--BB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_3
|
| 984 |
|
|
--operation mode is normal
|
| 985 |
|
|
|
| 986 |
|
|
BB1_r32_o_3_lut_out = AB1_r32_o_1;
|
| 987 |
|
|
BB1_r32_o_3 = DFFEAS(BB1_r32_o_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 988 |
|
|
|
| 989 |
|
|
|
| 990 |
|
|
--QB1_dout_iv_3 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_3
|
| 991 |
|
|
--operation mode is normal
|
| 992 |
|
|
|
| 993 |
|
|
QB1_dout_iv_3 = GD1_dout_iv_1_3 # FD1_wb_o_3 & GD1_dout7_0_a2;
|
| 994 |
|
|
|
| 995 |
|
|
--QB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_3
|
| 996 |
|
|
--operation mode is normal
|
| 997 |
|
|
|
| 998 |
|
|
QB1_r32_o_3 = DFFEAS(QB1_dout_iv_3, E1__clk0, VCC, , , , , , );
|
| 999 |
|
|
|
| 1000 |
|
|
|
| 1001 |
|
|
--F1_dout_2 is mips_sys:isys|mips_dvc:imips_dvc|dout_2
|
| 1002 |
|
|
--operation mode is normal
|
| 1003 |
|
|
|
| 1004 |
|
|
F1_dout_2_lut_out = F1_dout_0_0_a3_0[2] # K1_cntr_2 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[2];
|
| 1005 |
|
|
F1_dout_2 = DFFEAS(F1_dout_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 1006 |
|
|
|
| 1007 |
|
|
|
| 1008 |
|
|
--DB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_2
|
| 1009 |
|
|
--operation mode is normal
|
| 1010 |
|
|
|
| 1011 |
|
|
DB1_r32_o_2_lut_out = WB7L1;
|
| 1012 |
|
|
DB1_r32_o_2 = DFFEAS(DB1_r32_o_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 1013 |
|
|
|
| 1014 |
|
|
|
| 1015 |
|
|
--BB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_2
|
| 1016 |
|
|
--operation mode is normal
|
| 1017 |
|
|
|
| 1018 |
|
|
BB1_r32_o_2_lut_out = AB1_r32_o_0;
|
| 1019 |
|
|
BB1_r32_o_2 = DFFEAS(BB1_r32_o_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 1020 |
|
|
|
| 1021 |
|
|
|
| 1022 |
|
|
--QB1_dout_iv_2 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_2
|
| 1023 |
|
|
--operation mode is normal
|
| 1024 |
|
|
|
| 1025 |
|
|
QB1_dout_iv_2 = GD1_dout_iv_1_2 # FD1_wb_o_2 & GD1_dout7_0_a2;
|
| 1026 |
|
|
|
| 1027 |
|
|
--QB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_2
|
| 1028 |
|
|
--operation mode is normal
|
| 1029 |
|
|
|
| 1030 |
|
|
QB1_r32_o_2 = DFFEAS(QB1_dout_iv_2, E1__clk0, VCC, , , , , , );
|
| 1031 |
|
|
|
| 1032 |
|
|
|
| 1033 |
|
|
--F1_dout_1 is mips_sys:isys|mips_dvc:imips_dvc|dout_1
|
| 1034 |
|
|
--operation mode is normal
|
| 1035 |
|
|
|
| 1036 |
|
|
F1_dout_1_lut_out = F1_dout_0_0_a3_0[1] # K1_cntr_1 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[1];
|
| 1037 |
|
|
F1_dout_1 = DFFEAS(F1_dout_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 1038 |
|
|
|
| 1039 |
|
|
|
| 1040 |
|
|
--DB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_1
|
| 1041 |
|
|
--operation mode is normal
|
| 1042 |
|
|
|
| 1043 |
|
|
DB1_r32_o_1_lut_out = WB6L1;
|
| 1044 |
|
|
DB1_r32_o_1 = DFFEAS(DB1_r32_o_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 1045 |
|
|
|
| 1046 |
|
|
|
| 1047 |
|
|
--BB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_1
|
| 1048 |
|
|
--operation mode is normal
|
| 1049 |
|
|
|
| 1050 |
|
|
BB1_r32_o_1_lut_out = RB1_byte_addr_o_1;
|
| 1051 |
|
|
BB1_r32_o_1 = DFFEAS(BB1_r32_o_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 1052 |
|
|
|
| 1053 |
|
|
|
| 1054 |
|
|
--QB1_dout_iv_1 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_1
|
| 1055 |
|
|
--operation mode is normal
|
| 1056 |
|
|
|
| 1057 |
|
|
QB1_dout_iv_1 = GD1_dout_iv_1_1 # FD1_wb_o_1 & GD1_dout7_0_a2;
|
| 1058 |
|
|
|
| 1059 |
|
|
--QB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_1
|
| 1060 |
|
|
--operation mode is normal
|
| 1061 |
|
|
|
| 1062 |
|
|
QB1_r32_o_1 = DFFEAS(QB1_dout_iv_1, E1__clk0, VCC, , , , , , );
|
| 1063 |
|
|
|
| 1064 |
|
|
|
| 1065 |
|
|
--RB1_c_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|c_1
|
| 1066 |
|
|
--operation mode is normal
|
| 1067 |
|
|
|
| 1068 |
|
|
RB1_c_1 = MD1_c_0_0 # UD1_shift_out_sn_m31_i & !MD1_c_a_1 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_0;
|
| 1069 |
|
|
|
| 1070 |
|
|
--RB1_byte_addr_o_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|byte_addr_o_1
|
| 1071 |
|
|
--operation mode is normal
|
| 1072 |
|
|
|
| 1073 |
|
|
RB1_byte_addr_o_1 = DFFEAS(RB1_c_1, E1__clk0, VCC, , , , , , );
|
| 1074 |
|
|
|
| 1075 |
|
|
|
| 1076 |
|
|
--F1_dout_0 is mips_sys:isys|mips_dvc:imips_dvc|dout_0
|
| 1077 |
|
|
--operation mode is normal
|
| 1078 |
|
|
|
| 1079 |
|
|
F1_dout_0_lut_out = F1_dout_0_0_a3_0[0] # K1_cntr_0 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[0];
|
| 1080 |
|
|
F1_dout_0 = DFFEAS(F1_dout_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 1081 |
|
|
|
| 1082 |
|
|
|
| 1083 |
|
|
--DB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_0
|
| 1084 |
|
|
--operation mode is normal
|
| 1085 |
|
|
|
| 1086 |
|
|
DB1_r32_o_0_lut_out = WB5L1;
|
| 1087 |
|
|
DB1_r32_o_0 = DFFEAS(DB1_r32_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 1088 |
|
|
|
| 1089 |
|
|
|
| 1090 |
|
|
--BB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_0
|
| 1091 |
|
|
--operation mode is normal
|
| 1092 |
|
|
|
| 1093 |
|
|
BB1_r32_o_0_lut_out = RB1_byte_addr_o_0;
|
| 1094 |
|
|
BB1_r32_o_0 = DFFEAS(BB1_r32_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 1095 |
|
|
|
| 1096 |
|
|
|
| 1097 |
|
|
--QB1_dout_iv_0 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_0
|
| 1098 |
|
|
--operation mode is normal
|
| 1099 |
|
|
|
| 1100 |
|
|
QB1_dout_iv_0 = GD1_dout_iv_1_0 # FD1_wb_o_0 & GD1_dout7_0_a2;
|
| 1101 |
|
|
|
| 1102 |
|
|
--QB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_0
|
| 1103 |
|
|
--operation mode is normal
|
| 1104 |
|
|
|
| 1105 |
|
|
QB1_r32_o_0 = DFFEAS(QB1_dout_iv_0, E1__clk0, VCC, , , , , , );
|
| 1106 |
|
|
|
| 1107 |
|
|
|
| 1108 |
|
|
--RB1_c_0_d0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|c_0_d0
|
| 1109 |
|
|
--operation mode is normal
|
| 1110 |
|
|
|
| 1111 |
|
|
RB1_c_0_d0 = MD1_c_2_0 # UD1_shift_out_0 # TD1_alu_out_9_a2_0 # !MD1_c_a_0;
|
| 1112 |
|
|
|
| 1113 |
|
|
--RB1_byte_addr_o_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|byte_addr_o_0
|
| 1114 |
|
|
--operation mode is normal
|
| 1115 |
|
|
|
| 1116 |
|
|
RB1_byte_addr_o_0 = DFFEAS(RB1_c_0_d0, E1__clk0, VCC, , , , , , );
|
| 1117 |
|
|
|
| 1118 |
|
|
|
| 1119 |
|
|
--F1_wr_uartdata_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|wr_uartdata_0_a2
|
| 1120 |
|
|
--operation mode is normal
|
| 1121 |
|
|
|
| 1122 |
|
|
F1_wr_uartdata_0_a2 = AB1_r32_o_3 & F1_wr_uartdata_0_a2_1 & F1_wr_uartdata_0_a2_a & F1_rd_uartdata_0_a2_0;
|
| 1123 |
|
|
|
| 1124 |
|
|
|
| 1125 |
|
|
--U1_b_full is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_full
|
| 1126 |
|
|
--operation mode is normal
|
| 1127 |
|
|
|
| 1128 |
|
|
U1_b_full_lut_out = !N1_ua_state_ns_0_a2_0[1] & U1_b_full # U1_b_non_empty & U1L3;
|
| 1129 |
|
|
U1_b_full = DFFEAS(U1_b_full_lut_out, E1__clk0, VCC, , , , , , );
|
| 1130 |
|
|
|
| 1131 |
|
|
|
| 1132 |
|
|
--X1_safe_q[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[1]
|
| 1133 |
|
|
--operation mode is arithmetic
|
| 1134 |
|
|
|
| 1135 |
|
|
X1_safe_q[1]_carry_eqn = X1L2;
|
| 1136 |
|
|
X1_safe_q[1]_lut_out = X1_safe_q[1] $ (X1_safe_q[1]_carry_eqn);
|
| 1137 |
|
|
X1_safe_q[1] = DFFEAS(X1_safe_q[1]_lut_out, E1__clk0, VCC, , U1L1, , , , );
|
| 1138 |
|
|
|
| 1139 |
|
|
--X1L4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella1~COUT
|
| 1140 |
|
|
--operation mode is arithmetic
|
| 1141 |
|
|
|
| 1142 |
|
|
X1L4 = CARRY(X1_safe_q[1] $ T1_valid_wreq # !X1L2);
|
| 1143 |
|
|
|
| 1144 |
|
|
|
| 1145 |
|
|
--X1_safe_q[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[8]
|
| 1146 |
|
|
--operation mode is normal
|
| 1147 |
|
|
|
| 1148 |
|
|
X1_safe_q[8]_carry_eqn = X1L61;
|
| 1149 |
|
|
X1_safe_q[8]_lut_out = X1_safe_q[8] $ (!X1_safe_q[8]_carry_eqn);
|
| 1150 |
|
|
X1_safe_q[8] = DFFEAS(X1_safe_q[8]_lut_out, E1__clk0, VCC, , U1L1, , , , );
|
| 1151 |
|
|
|
| 1152 |
|
|
|
| 1153 |
|
|
--X1_safe_q[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[7]
|
| 1154 |
|
|
--operation mode is arithmetic
|
| 1155 |
|
|
|
| 1156 |
|
|
X1_safe_q[7]_carry_eqn = X1L41;
|
| 1157 |
|
|
X1_safe_q[7]_lut_out = X1_safe_q[7] $ (X1_safe_q[7]_carry_eqn);
|
| 1158 |
|
|
X1_safe_q[7] = DFFEAS(X1_safe_q[7]_lut_out, E1__clk0, VCC, , U1L1, , , , );
|
| 1159 |
|
|
|
| 1160 |
|
|
--X1L61 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella7~COUT
|
| 1161 |
|
|
--operation mode is arithmetic
|
| 1162 |
|
|
|
| 1163 |
|
|
X1L61 = CARRY(X1_safe_q[7] $ T1_valid_wreq # !X1L41);
|
| 1164 |
|
|
|
| 1165 |
|
|
|
| 1166 |
|
|
--X1_safe_q[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[6]
|
| 1167 |
|
|
--operation mode is arithmetic
|
| 1168 |
|
|
|
| 1169 |
|
|
X1_safe_q[6]_carry_eqn = X1L21;
|
| 1170 |
|
|
X1_safe_q[6]_lut_out = X1_safe_q[6] $ (!X1_safe_q[6]_carry_eqn);
|
| 1171 |
|
|
X1_safe_q[6] = DFFEAS(X1_safe_q[6]_lut_out, E1__clk0, VCC, , U1L1, , , , );
|
| 1172 |
|
|
|
| 1173 |
|
|
--X1L41 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella6~COUT
|
| 1174 |
|
|
--operation mode is arithmetic
|
| 1175 |
|
|
|
| 1176 |
|
|
X1L41 = CARRY(!X1L21 & X1_safe_q[6] $ !T1_valid_wreq);
|
| 1177 |
|
|
|
| 1178 |
|
|
|
| 1179 |
|
|
--N1_ua_state_ns_0_a2_0[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state_ns_0_a2_0[1]
|
| 1180 |
|
|
--operation mode is normal
|
| 1181 |
|
|
|
| 1182 |
|
|
N1_ua_state_ns_0_a2_0[1] = U1_b_non_empty & !N1_ua_state_i[0];
|
| 1183 |
|
|
|
| 1184 |
|
|
|
| 1185 |
|
|
--U1L7 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_non_empty~112
|
| 1186 |
|
|
--operation mode is normal
|
| 1187 |
|
|
|
| 1188 |
|
|
U1L7 = X1_safe_q[8] # X1_safe_q[7] # X1_safe_q[6] # !N1_ua_state_ns_0_a2_0[1];
|
| 1189 |
|
|
|
| 1190 |
|
|
|
| 1191 |
|
|
--X1_safe_q[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[5]
|
| 1192 |
|
|
--operation mode is arithmetic
|
| 1193 |
|
|
|
| 1194 |
|
|
X1_safe_q[5]_carry_eqn = X1L01;
|
| 1195 |
|
|
X1_safe_q[5]_lut_out = X1_safe_q[5] $ (X1_safe_q[5]_carry_eqn);
|
| 1196 |
|
|
X1_safe_q[5] = DFFEAS(X1_safe_q[5]_lut_out, E1__clk0, VCC, , U1L1, , , , );
|
| 1197 |
|
|
|
| 1198 |
|
|
--X1L21 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella5~COUT
|
| 1199 |
|
|
--operation mode is arithmetic
|
| 1200 |
|
|
|
| 1201 |
|
|
X1L21 = CARRY(X1_safe_q[5] $ T1_valid_wreq # !X1L01);
|
| 1202 |
|
|
|
| 1203 |
|
|
|
| 1204 |
|
|
--X1_safe_q[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[4]
|
| 1205 |
|
|
--operation mode is arithmetic
|
| 1206 |
|
|
|
| 1207 |
|
|
X1_safe_q[4]_carry_eqn = X1L8;
|
| 1208 |
|
|
X1_safe_q[4]_lut_out = X1_safe_q[4] $ (!X1_safe_q[4]_carry_eqn);
|
| 1209 |
|
|
X1_safe_q[4] = DFFEAS(X1_safe_q[4]_lut_out, E1__clk0, VCC, , U1L1, , , , );
|
| 1210 |
|
|
|
| 1211 |
|
|
--X1L01 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella4~COUT
|
| 1212 |
|
|
--operation mode is arithmetic
|
| 1213 |
|
|
|
| 1214 |
|
|
X1L01 = CARRY(!X1L8 & X1_safe_q[4] $ !T1_valid_wreq);
|
| 1215 |
|
|
|
| 1216 |
|
|
|
| 1217 |
|
|
--X1_safe_q[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[3]
|
| 1218 |
|
|
--operation mode is arithmetic
|
| 1219 |
|
|
|
| 1220 |
|
|
X1_safe_q[3]_carry_eqn = X1L6;
|
| 1221 |
|
|
X1_safe_q[3]_lut_out = X1_safe_q[3] $ (X1_safe_q[3]_carry_eqn);
|
| 1222 |
|
|
X1_safe_q[3] = DFFEAS(X1_safe_q[3]_lut_out, E1__clk0, VCC, , U1L1, , , , );
|
| 1223 |
|
|
|
| 1224 |
|
|
--X1L8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella3~COUT
|
| 1225 |
|
|
--operation mode is arithmetic
|
| 1226 |
|
|
|
| 1227 |
|
|
X1L8 = CARRY(X1_safe_q[3] $ T1_valid_wreq # !X1L6);
|
| 1228 |
|
|
|
| 1229 |
|
|
|
| 1230 |
|
|
--X1_safe_q[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[2]
|
| 1231 |
|
|
--operation mode is arithmetic
|
| 1232 |
|
|
|
| 1233 |
|
|
X1_safe_q[2]_carry_eqn = X1L4;
|
| 1234 |
|
|
X1_safe_q[2]_lut_out = X1_safe_q[2] $ (!X1_safe_q[2]_carry_eqn);
|
| 1235 |
|
|
X1_safe_q[2] = DFFEAS(X1_safe_q[2]_lut_out, E1__clk0, VCC, , U1L1, , , , );
|
| 1236 |
|
|
|
| 1237 |
|
|
--X1L6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella2~COUT
|
| 1238 |
|
|
--operation mode is arithmetic
|
| 1239 |
|
|
|
| 1240 |
|
|
X1L6 = CARRY(!X1L4 & X1_safe_q[2] $ !T1_valid_wreq);
|
| 1241 |
|
|
|
| 1242 |
|
|
|
| 1243 |
|
|
--U1L8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_non_empty~113
|
| 1244 |
|
|
--operation mode is normal
|
| 1245 |
|
|
|
| 1246 |
|
|
U1L8 = X1_safe_q[5] # X1_safe_q[4] # X1_safe_q[3] # X1_safe_q[2];
|
| 1247 |
|
|
|
| 1248 |
|
|
|
| 1249 |
|
|
--X1_safe_q[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[0]
|
| 1250 |
|
|
--operation mode is arithmetic
|
| 1251 |
|
|
|
| 1252 |
|
|
X1_safe_q[0]_lut_out = !X1_safe_q[0];
|
| 1253 |
|
|
X1_safe_q[0] = DFFEAS(X1_safe_q[0]_lut_out, E1__clk0, VCC, , U1L1, , , , );
|
| 1254 |
|
|
|
| 1255 |
|
|
--X1L2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella0~COUT
|
| 1256 |
|
|
--operation mode is arithmetic
|
| 1257 |
|
|
|
| 1258 |
|
|
X1L2 = CARRY(X1_safe_q[0] $ !T1_valid_wreq);
|
| 1259 |
|
|
|
| 1260 |
|
|
|
| 1261 |
|
|
--U1L9 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_non_empty~114
|
| 1262 |
|
|
--operation mode is normal
|
| 1263 |
|
|
|
| 1264 |
|
|
U1L9 = X1_safe_q[1] # U1L7 # U1L8 # !X1_safe_q[0];
|
| 1265 |
|
|
|
| 1266 |
|
|
|
| 1267 |
|
|
--N1_bit_ctr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr[1]
|
| 1268 |
|
|
--operation mode is arithmetic
|
| 1269 |
|
|
|
| 1270 |
|
|
N1_bit_ctr[1]_carry_eqn = N1_bit_ctr_cout_0[0];
|
| 1271 |
|
|
N1_bit_ctr[1]_lut_out = N1_bit_ctr[1] $ (N1_bit_ctr[1]_carry_eqn);
|
| 1272 |
|
|
N1_bit_ctr[1] = DFFEAS(N1_bit_ctr[1]_lut_out, E1__clk0, VCC, , , , , !N1_bit_ctr23_i_i, );
|
| 1273 |
|
|
|
| 1274 |
|
|
--N1_bit_ctr_cout_0[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr_cout_0[1]
|
| 1275 |
|
|
--operation mode is arithmetic
|
| 1276 |
|
|
|
| 1277 |
|
|
N1_bit_ctr_cout_0[1] = CARRY(!N1_bit_ctr_cout_0[0] # !N1_bit_ctr[1]);
|
| 1278 |
|
|
|
| 1279 |
|
|
|
| 1280 |
|
|
--N1_bit_ctr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr[2]
|
| 1281 |
|
|
--operation mode is normal
|
| 1282 |
|
|
|
| 1283 |
|
|
N1_bit_ctr[2]_carry_eqn = N1_bit_ctr_cout_0[1];
|
| 1284 |
|
|
N1_bit_ctr[2]_lut_out = N1_bit_ctr[2] $ (!N1_bit_ctr[2]_carry_eqn);
|
| 1285 |
|
|
N1_bit_ctr[2] = DFFEAS(N1_bit_ctr[2]_lut_out, E1__clk0, VCC, , , , , !N1_bit_ctr23_i_i, );
|
| 1286 |
|
|
|
| 1287 |
|
|
|
| 1288 |
|
|
--N1_bit_ctr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr[0]
|
| 1289 |
|
|
--operation mode is arithmetic
|
| 1290 |
|
|
|
| 1291 |
|
|
N1_bit_ctr[0]_lut_out = N1_bit_ctr[0] $ N1_clk_ctr_equ15_0_a2;
|
| 1292 |
|
|
N1_bit_ctr[0] = DFFEAS(N1_bit_ctr[0]_lut_out, E1__clk0, VCC, , , , , !N1_bit_ctr23_i_i, );
|
| 1293 |
|
|
|
| 1294 |
|
|
--N1_bit_ctr_cout_0[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr_cout_0[0]
|
| 1295 |
|
|
--operation mode is arithmetic
|
| 1296 |
|
|
|
| 1297 |
|
|
N1_bit_ctr_cout_0[0] = CARRY(N1_bit_ctr[0] & N1_clk_ctr_equ15_0_a2);
|
| 1298 |
|
|
|
| 1299 |
|
|
|
| 1300 |
|
|
--T1_valid_wreq is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|valid_wreq
|
| 1301 |
|
|
--operation mode is normal
|
| 1302 |
|
|
|
| 1303 |
|
|
T1_valid_wreq = F1_wr_uartdata_0_a2 & !U1_b_full;
|
| 1304 |
|
|
|
| 1305 |
|
|
|
| 1306 |
|
|
--T1_valid_rreq is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|valid_rreq
|
| 1307 |
|
|
--operation mode is normal
|
| 1308 |
|
|
|
| 1309 |
|
|
T1_valid_rreq = N1_ua_state_ns_0_a2_0[1] & U1_b_non_empty;
|
| 1310 |
|
|
|
| 1311 |
|
|
|
| 1312 |
|
|
--W2_safe_q[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[0]
|
| 1313 |
|
|
--operation mode is arithmetic
|
| 1314 |
|
|
|
| 1315 |
|
|
W2_safe_q[0]_lut_out = W2_safe_q[0] $ T1_valid_wreq;
|
| 1316 |
|
|
W2_safe_q[0] = DFFEAS(W2_safe_q[0]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1317 |
|
|
|
| 1318 |
|
|
--W2L2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella0~COUT
|
| 1319 |
|
|
--operation mode is arithmetic
|
| 1320 |
|
|
|
| 1321 |
|
|
W2L2 = CARRY(W2_safe_q[0]);
|
| 1322 |
|
|
|
| 1323 |
|
|
|
| 1324 |
|
|
--W2_safe_q[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[1]
|
| 1325 |
|
|
--operation mode is arithmetic
|
| 1326 |
|
|
|
| 1327 |
|
|
W2_safe_q[1]_carry_eqn = W2L2;
|
| 1328 |
|
|
W2_safe_q[1]_lut_out = W2_safe_q[1] $ (T1_valid_wreq & W2_safe_q[1]_carry_eqn);
|
| 1329 |
|
|
W2_safe_q[1] = DFFEAS(W2_safe_q[1]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1330 |
|
|
|
| 1331 |
|
|
--W2L4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella1~COUT
|
| 1332 |
|
|
--operation mode is arithmetic
|
| 1333 |
|
|
|
| 1334 |
|
|
W2L4 = CARRY(!W2L2 # !W2_safe_q[1]);
|
| 1335 |
|
|
|
| 1336 |
|
|
|
| 1337 |
|
|
--W2_safe_q[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[2]
|
| 1338 |
|
|
--operation mode is arithmetic
|
| 1339 |
|
|
|
| 1340 |
|
|
W2_safe_q[2]_carry_eqn = W2L4;
|
| 1341 |
|
|
W2_safe_q[2]_lut_out = W2_safe_q[2] $ (T1_valid_wreq & !W2_safe_q[2]_carry_eqn);
|
| 1342 |
|
|
W2_safe_q[2] = DFFEAS(W2_safe_q[2]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1343 |
|
|
|
| 1344 |
|
|
--W2L6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella2~COUT
|
| 1345 |
|
|
--operation mode is arithmetic
|
| 1346 |
|
|
|
| 1347 |
|
|
W2L6 = CARRY(W2_safe_q[2] & !W2L4);
|
| 1348 |
|
|
|
| 1349 |
|
|
|
| 1350 |
|
|
--W2_safe_q[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[3]
|
| 1351 |
|
|
--operation mode is arithmetic
|
| 1352 |
|
|
|
| 1353 |
|
|
W2_safe_q[3]_carry_eqn = W2L6;
|
| 1354 |
|
|
W2_safe_q[3]_lut_out = W2_safe_q[3] $ (T1_valid_wreq & W2_safe_q[3]_carry_eqn);
|
| 1355 |
|
|
W2_safe_q[3] = DFFEAS(W2_safe_q[3]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1356 |
|
|
|
| 1357 |
|
|
--W2L8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella3~COUT
|
| 1358 |
|
|
--operation mode is arithmetic
|
| 1359 |
|
|
|
| 1360 |
|
|
W2L8 = CARRY(!W2L6 # !W2_safe_q[3]);
|
| 1361 |
|
|
|
| 1362 |
|
|
|
| 1363 |
|
|
--W2_safe_q[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[4]
|
| 1364 |
|
|
--operation mode is arithmetic
|
| 1365 |
|
|
|
| 1366 |
|
|
W2_safe_q[4]_carry_eqn = W2L8;
|
| 1367 |
|
|
W2_safe_q[4]_lut_out = W2_safe_q[4] $ (T1_valid_wreq & !W2_safe_q[4]_carry_eqn);
|
| 1368 |
|
|
W2_safe_q[4] = DFFEAS(W2_safe_q[4]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1369 |
|
|
|
| 1370 |
|
|
--W2L01 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella4~COUT
|
| 1371 |
|
|
--operation mode is arithmetic
|
| 1372 |
|
|
|
| 1373 |
|
|
W2L01 = CARRY(W2_safe_q[4] & !W2L8);
|
| 1374 |
|
|
|
| 1375 |
|
|
|
| 1376 |
|
|
--W2_safe_q[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[5]
|
| 1377 |
|
|
--operation mode is arithmetic
|
| 1378 |
|
|
|
| 1379 |
|
|
W2_safe_q[5]_carry_eqn = W2L01;
|
| 1380 |
|
|
W2_safe_q[5]_lut_out = W2_safe_q[5] $ (T1_valid_wreq & W2_safe_q[5]_carry_eqn);
|
| 1381 |
|
|
W2_safe_q[5] = DFFEAS(W2_safe_q[5]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1382 |
|
|
|
| 1383 |
|
|
--W2L21 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella5~COUT
|
| 1384 |
|
|
--operation mode is arithmetic
|
| 1385 |
|
|
|
| 1386 |
|
|
W2L21 = CARRY(!W2L01 # !W2_safe_q[5]);
|
| 1387 |
|
|
|
| 1388 |
|
|
|
| 1389 |
|
|
--W2_safe_q[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[6]
|
| 1390 |
|
|
--operation mode is arithmetic
|
| 1391 |
|
|
|
| 1392 |
|
|
W2_safe_q[6]_carry_eqn = W2L21;
|
| 1393 |
|
|
W2_safe_q[6]_lut_out = W2_safe_q[6] $ (T1_valid_wreq & !W2_safe_q[6]_carry_eqn);
|
| 1394 |
|
|
W2_safe_q[6] = DFFEAS(W2_safe_q[6]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1395 |
|
|
|
| 1396 |
|
|
--W2L41 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella6~COUT
|
| 1397 |
|
|
--operation mode is arithmetic
|
| 1398 |
|
|
|
| 1399 |
|
|
W2L41 = CARRY(W2_safe_q[6] & !W2L21);
|
| 1400 |
|
|
|
| 1401 |
|
|
|
| 1402 |
|
|
--W2_safe_q[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[7]
|
| 1403 |
|
|
--operation mode is arithmetic
|
| 1404 |
|
|
|
| 1405 |
|
|
W2_safe_q[7]_carry_eqn = W2L41;
|
| 1406 |
|
|
W2_safe_q[7]_lut_out = W2_safe_q[7] $ (T1_valid_wreq & W2_safe_q[7]_carry_eqn);
|
| 1407 |
|
|
W2_safe_q[7] = DFFEAS(W2_safe_q[7]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1408 |
|
|
|
| 1409 |
|
|
--W2L61 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella7~COUT
|
| 1410 |
|
|
--operation mode is arithmetic
|
| 1411 |
|
|
|
| 1412 |
|
|
W2L61 = CARRY(!W2L41 # !W2_safe_q[7]);
|
| 1413 |
|
|
|
| 1414 |
|
|
|
| 1415 |
|
|
--W2_safe_q[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[8]
|
| 1416 |
|
|
--operation mode is normal
|
| 1417 |
|
|
|
| 1418 |
|
|
W2_safe_q[8]_carry_eqn = W2L61;
|
| 1419 |
|
|
W2_safe_q[8]_lut_out = W2_safe_q[8] $ (T1_valid_wreq & !W2_safe_q[8]_carry_eqn);
|
| 1420 |
|
|
W2_safe_q[8] = DFFEAS(W2_safe_q[8]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1421 |
|
|
|
| 1422 |
|
|
|
| 1423 |
|
|
--W1_safe_q[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[0]
|
| 1424 |
|
|
--operation mode is arithmetic
|
| 1425 |
|
|
|
| 1426 |
|
|
W1_safe_q[0]_lut_out = W1_safe_q[0] $ T1_valid_rreq;
|
| 1427 |
|
|
W1_safe_q[0] = DFFEAS(W1_safe_q[0]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1428 |
|
|
|
| 1429 |
|
|
--W1L2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella0~COUT
|
| 1430 |
|
|
--operation mode is arithmetic
|
| 1431 |
|
|
|
| 1432 |
|
|
W1L2 = CARRY(W1_safe_q[0]);
|
| 1433 |
|
|
|
| 1434 |
|
|
|
| 1435 |
|
|
--W1_safe_q[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[1]
|
| 1436 |
|
|
--operation mode is arithmetic
|
| 1437 |
|
|
|
| 1438 |
|
|
W1_safe_q[1]_carry_eqn = W1L2;
|
| 1439 |
|
|
W1_safe_q[1]_lut_out = W1_safe_q[1] $ (T1_valid_rreq & W1_safe_q[1]_carry_eqn);
|
| 1440 |
|
|
W1_safe_q[1] = DFFEAS(W1_safe_q[1]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1441 |
|
|
|
| 1442 |
|
|
--W1L4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella1~COUT
|
| 1443 |
|
|
--operation mode is arithmetic
|
| 1444 |
|
|
|
| 1445 |
|
|
W1L4 = CARRY(!W1L2 # !W1_safe_q[1]);
|
| 1446 |
|
|
|
| 1447 |
|
|
|
| 1448 |
|
|
--W1_safe_q[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[2]
|
| 1449 |
|
|
--operation mode is arithmetic
|
| 1450 |
|
|
|
| 1451 |
|
|
W1_safe_q[2]_carry_eqn = W1L4;
|
| 1452 |
|
|
W1_safe_q[2]_lut_out = W1_safe_q[2] $ (T1_valid_rreq & !W1_safe_q[2]_carry_eqn);
|
| 1453 |
|
|
W1_safe_q[2] = DFFEAS(W1_safe_q[2]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1454 |
|
|
|
| 1455 |
|
|
--W1L6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella2~COUT
|
| 1456 |
|
|
--operation mode is arithmetic
|
| 1457 |
|
|
|
| 1458 |
|
|
W1L6 = CARRY(W1_safe_q[2] & !W1L4);
|
| 1459 |
|
|
|
| 1460 |
|
|
|
| 1461 |
|
|
--W1_safe_q[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[3]
|
| 1462 |
|
|
--operation mode is arithmetic
|
| 1463 |
|
|
|
| 1464 |
|
|
W1_safe_q[3]_carry_eqn = W1L6;
|
| 1465 |
|
|
W1_safe_q[3]_lut_out = W1_safe_q[3] $ (T1_valid_rreq & W1_safe_q[3]_carry_eqn);
|
| 1466 |
|
|
W1_safe_q[3] = DFFEAS(W1_safe_q[3]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1467 |
|
|
|
| 1468 |
|
|
--W1L8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella3~COUT
|
| 1469 |
|
|
--operation mode is arithmetic
|
| 1470 |
|
|
|
| 1471 |
|
|
W1L8 = CARRY(!W1L6 # !W1_safe_q[3]);
|
| 1472 |
|
|
|
| 1473 |
|
|
|
| 1474 |
|
|
--W1_safe_q[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[4]
|
| 1475 |
|
|
--operation mode is arithmetic
|
| 1476 |
|
|
|
| 1477 |
|
|
W1_safe_q[4]_carry_eqn = W1L8;
|
| 1478 |
|
|
W1_safe_q[4]_lut_out = W1_safe_q[4] $ (T1_valid_rreq & !W1_safe_q[4]_carry_eqn);
|
| 1479 |
|
|
W1_safe_q[4] = DFFEAS(W1_safe_q[4]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1480 |
|
|
|
| 1481 |
|
|
--W1L01 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella4~COUT
|
| 1482 |
|
|
--operation mode is arithmetic
|
| 1483 |
|
|
|
| 1484 |
|
|
W1L01 = CARRY(W1_safe_q[4] & !W1L8);
|
| 1485 |
|
|
|
| 1486 |
|
|
|
| 1487 |
|
|
--W1_safe_q[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[5]
|
| 1488 |
|
|
--operation mode is arithmetic
|
| 1489 |
|
|
|
| 1490 |
|
|
W1_safe_q[5]_carry_eqn = W1L01;
|
| 1491 |
|
|
W1_safe_q[5]_lut_out = W1_safe_q[5] $ (T1_valid_rreq & W1_safe_q[5]_carry_eqn);
|
| 1492 |
|
|
W1_safe_q[5] = DFFEAS(W1_safe_q[5]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1493 |
|
|
|
| 1494 |
|
|
--W1L21 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella5~COUT
|
| 1495 |
|
|
--operation mode is arithmetic
|
| 1496 |
|
|
|
| 1497 |
|
|
W1L21 = CARRY(!W1L01 # !W1_safe_q[5]);
|
| 1498 |
|
|
|
| 1499 |
|
|
|
| 1500 |
|
|
--W1_safe_q[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[6]
|
| 1501 |
|
|
--operation mode is arithmetic
|
| 1502 |
|
|
|
| 1503 |
|
|
W1_safe_q[6]_carry_eqn = W1L21;
|
| 1504 |
|
|
W1_safe_q[6]_lut_out = W1_safe_q[6] $ (T1_valid_rreq & !W1_safe_q[6]_carry_eqn);
|
| 1505 |
|
|
W1_safe_q[6] = DFFEAS(W1_safe_q[6]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1506 |
|
|
|
| 1507 |
|
|
--W1L41 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella6~COUT
|
| 1508 |
|
|
--operation mode is arithmetic
|
| 1509 |
|
|
|
| 1510 |
|
|
W1L41 = CARRY(W1_safe_q[6] & !W1L21);
|
| 1511 |
|
|
|
| 1512 |
|
|
|
| 1513 |
|
|
--W1_safe_q[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[7]
|
| 1514 |
|
|
--operation mode is arithmetic
|
| 1515 |
|
|
|
| 1516 |
|
|
W1_safe_q[7]_carry_eqn = W1L41;
|
| 1517 |
|
|
W1_safe_q[7]_lut_out = W1_safe_q[7] $ (T1_valid_rreq & W1_safe_q[7]_carry_eqn);
|
| 1518 |
|
|
W1_safe_q[7] = DFFEAS(W1_safe_q[7]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1519 |
|
|
|
| 1520 |
|
|
--W1L61 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella7~COUT
|
| 1521 |
|
|
--operation mode is arithmetic
|
| 1522 |
|
|
|
| 1523 |
|
|
W1L61 = CARRY(!W1L41 # !W1_safe_q[7]);
|
| 1524 |
|
|
|
| 1525 |
|
|
|
| 1526 |
|
|
--W1_safe_q[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[8]
|
| 1527 |
|
|
--operation mode is normal
|
| 1528 |
|
|
|
| 1529 |
|
|
W1_safe_q[8]_carry_eqn = W1L61;
|
| 1530 |
|
|
W1_safe_q[8]_lut_out = W1_safe_q[8] $ (T1_valid_rreq & !W1_safe_q[8]_carry_eqn);
|
| 1531 |
|
|
W1_safe_q[8] = DFFEAS(W1_safe_q[8]_lut_out, E1__clk0, VCC, , , , , , );
|
| 1532 |
|
|
|
| 1533 |
|
|
|
| 1534 |
|
|
--Y1_q_b[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[1]
|
| 1535 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 1536 |
|
|
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
|
| 1537 |
|
|
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
|
| 1538 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 1539 |
|
|
Y1_q_b[1]_PORT_A_data_in = CB1_r32_o_1;
|
| 1540 |
|
|
Y1_q_b[1]_PORT_A_data_in_reg = DFFE(Y1_q_b[1]_PORT_A_data_in, Y1_q_b[1]_clock_0, , , );
|
| 1541 |
|
|
Y1_q_b[1]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
|
| 1542 |
|
|
Y1_q_b[1]_PORT_A_address_reg = DFFE(Y1_q_b[1]_PORT_A_address, Y1_q_b[1]_clock_0, , , );
|
| 1543 |
|
|
Y1_q_b[1]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
|
| 1544 |
|
|
Y1_q_b[1]_PORT_B_address_reg = DFFE(Y1_q_b[1]_PORT_B_address, Y1_q_b[1]_clock_1, , , Y1_q_b[1]_clock_enable_1);
|
| 1545 |
|
|
Y1_q_b[1]_PORT_A_write_enable = T1_valid_wreq;
|
| 1546 |
|
|
Y1_q_b[1]_PORT_A_write_enable_reg = DFFE(Y1_q_b[1]_PORT_A_write_enable, Y1_q_b[1]_clock_0, , , );
|
| 1547 |
|
|
Y1_q_b[1]_PORT_B_read_enable = VCC;
|
| 1548 |
|
|
Y1_q_b[1]_PORT_B_read_enable_reg = DFFE(Y1_q_b[1]_PORT_B_read_enable, Y1_q_b[1]_clock_1, , , Y1_q_b[1]_clock_enable_1);
|
| 1549 |
|
|
Y1_q_b[1]_clock_0 = E1__clk0;
|
| 1550 |
|
|
Y1_q_b[1]_clock_1 = E1__clk0;
|
| 1551 |
|
|
Y1_q_b[1]_clock_enable_1 = T1_valid_rreq;
|
| 1552 |
|
|
Y1_q_b[1]_PORT_B_data_out = MEMORY(Y1_q_b[1]_PORT_A_data_in_reg, , Y1_q_b[1]_PORT_A_address_reg, Y1_q_b[1]_PORT_B_address_reg, Y1_q_b[1]_PORT_A_write_enable_reg, Y1_q_b[1]_PORT_B_read_enable_reg, , , Y1_q_b[1]_clock_0, Y1_q_b[1]_clock_1, , Y1_q_b[1]_clock_enable_1, , );
|
| 1553 |
|
|
Y1_q_b[1] = Y1_q_b[1]_PORT_B_data_out[0];
|
| 1554 |
|
|
|
| 1555 |
|
|
|
| 1556 |
|
|
--N1_tx_sr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[2]
|
| 1557 |
|
|
--operation mode is normal
|
| 1558 |
|
|
|
| 1559 |
|
|
N1_tx_sr[2]_lut_out = N1_read_request_ff & Y1_q_b[2] # !N1_read_request_ff & N1_tx_sr[3];
|
| 1560 |
|
|
N1_tx_sr[2] = DFFEAS(N1_tx_sr[2]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );
|
| 1561 |
|
|
|
| 1562 |
|
|
|
| 1563 |
|
|
--N1_clk_ctr[15] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[15]
|
| 1564 |
|
|
--operation mode is normal
|
| 1565 |
|
|
|
| 1566 |
|
|
N1_clk_ctr[15]_carry_eqn = N1_clk_ctr_cout_0[14];
|
| 1567 |
|
|
N1_clk_ctr[15]_lut_out = N1_clk_ctr[15] $ (N1_clk_ctr[15]_carry_eqn);
|
| 1568 |
|
|
N1_clk_ctr[15] = DFFEAS(N1_clk_ctr[15]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 1569 |
|
|
|
| 1570 |
|
|
|
| 1571 |
|
|
--N1_clk_ctr[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[6]
|
| 1572 |
|
|
--operation mode is arithmetic
|
| 1573 |
|
|
|
| 1574 |
|
|
N1_clk_ctr[6]_carry_eqn = N1_clk_ctr_cout_0[5];
|
| 1575 |
|
|
N1_clk_ctr[6]_lut_out = N1_clk_ctr[6] $ (!N1_clk_ctr[6]_carry_eqn);
|
| 1576 |
|
|
N1_clk_ctr[6] = DFFEAS(N1_clk_ctr[6]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 1577 |
|
|
|
| 1578 |
|
|
--N1_clk_ctr_cout_0[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[6]
|
| 1579 |
|
|
--operation mode is arithmetic
|
| 1580 |
|
|
|
| 1581 |
|
|
N1_clk_ctr_cout_0[6] = CARRY(N1_clk_ctr[6] & !N1_clk_ctr_cout_0[5]);
|
| 1582 |
|
|
|
| 1583 |
|
|
|
| 1584 |
|
|
--N1_clk_ctr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[0]
|
| 1585 |
|
|
--operation mode is arithmetic
|
| 1586 |
|
|
|
| 1587 |
|
|
N1_clk_ctr[0]_lut_out = !N1_clk_ctr[0];
|
| 1588 |
|
|
N1_clk_ctr[0] = DFFEAS(N1_clk_ctr[0]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 1589 |
|
|
|
| 1590 |
|
|
--N1_clk_ctr_cout_0[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[0]
|
| 1591 |
|
|
--operation mode is arithmetic
|
| 1592 |
|
|
|
| 1593 |
|
|
N1_clk_ctr_cout_0[0] = CARRY(N1_clk_ctr[0]);
|
| 1594 |
|
|
|
| 1595 |
|
|
|
| 1596 |
|
|
--N1_clk_ctr26_i_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a2_a
|
| 1597 |
|
|
--operation mode is normal
|
| 1598 |
|
|
|
| 1599 |
|
|
N1_clk_ctr26_i_0_a2_a = !N1_clk_ctr[7] & !N1_clk_ctr[12] & !N1_clk_ctr[13] & !N1_clk_ctr[14];
|
| 1600 |
|
|
|
| 1601 |
|
|
|
| 1602 |
|
|
--N1_clk_ctr[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[5]
|
| 1603 |
|
|
--operation mode is arithmetic
|
| 1604 |
|
|
|
| 1605 |
|
|
N1_clk_ctr[5]_carry_eqn = N1_clk_ctr_cout_0[4];
|
| 1606 |
|
|
N1_clk_ctr[5]_lut_out = N1_clk_ctr[5] $ (N1_clk_ctr[5]_carry_eqn);
|
| 1607 |
|
|
N1_clk_ctr[5] = DFFEAS(N1_clk_ctr[5]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 1608 |
|
|
|
| 1609 |
|
|
--N1_clk_ctr_cout_0[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[5]
|
| 1610 |
|
|
--operation mode is arithmetic
|
| 1611 |
|
|
|
| 1612 |
|
|
N1_clk_ctr_cout_0[5] = CARRY(!N1_clk_ctr_cout_0[4] # !N1_clk_ctr[5]);
|
| 1613 |
|
|
|
| 1614 |
|
|
|
| 1615 |
|
|
--N1_clk_ctr[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[4]
|
| 1616 |
|
|
--operation mode is arithmetic
|
| 1617 |
|
|
|
| 1618 |
|
|
N1_clk_ctr[4]_carry_eqn = N1_clk_ctr_cout_0[3];
|
| 1619 |
|
|
N1_clk_ctr[4]_lut_out = N1_clk_ctr[4] $ (!N1_clk_ctr[4]_carry_eqn);
|
| 1620 |
|
|
N1_clk_ctr[4] = DFFEAS(N1_clk_ctr[4]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 1621 |
|
|
|
| 1622 |
|
|
--N1_clk_ctr_cout_0[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[4]
|
| 1623 |
|
|
--operation mode is arithmetic
|
| 1624 |
|
|
|
| 1625 |
|
|
N1_clk_ctr_cout_0[4] = CARRY(N1_clk_ctr[4] & !N1_clk_ctr_cout_0[3]);
|
| 1626 |
|
|
|
| 1627 |
|
|
|
| 1628 |
|
|
--N1_clk_ctr_equ15_0_a2_4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2_4
|
| 1629 |
|
|
--operation mode is normal
|
| 1630 |
|
|
|
| 1631 |
|
|
N1_clk_ctr_equ15_0_a2_4 = N1_clk_ctr[2] & N1_clk_ctr[10] & N1_clk_ctr[8];
|
| 1632 |
|
|
|
| 1633 |
|
|
|
| 1634 |
|
|
--N1_clk_ctr_equ15_0_a2_7_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2_7_a
|
| 1635 |
|
|
--operation mode is normal
|
| 1636 |
|
|
|
| 1637 |
|
|
N1_clk_ctr_equ15_0_a2_7_a = !N1_clk_ctr[3] & !N1_clk_ctr[11] & !N1_clk_ctr[1] & !N1_clk_ctr[9];
|
| 1638 |
|
|
|
| 1639 |
|
|
|
| 1640 |
|
|
--N1_ua_state[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[6]
|
| 1641 |
|
|
--operation mode is normal
|
| 1642 |
|
|
|
| 1643 |
|
|
N1_ua_state[6]_lut_out = N1_ua_state[5];
|
| 1644 |
|
|
N1_ua_state[6] = DFFEAS(N1_ua_state[6]_lut_out, E1__clk0, VCC, , C1_G_451_x, , , !sys_rst, );
|
| 1645 |
|
|
|
| 1646 |
|
|
|
| 1647 |
|
|
--K1_cntr_7 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_7
|
| 1648 |
|
|
--operation mode is arithmetic
|
| 1649 |
|
|
|
| 1650 |
|
|
K1_cntr_7_carry_eqn = K1_cntr_cout[6];
|
| 1651 |
|
|
K1_cntr_7_lut_out = K1_cntr_7 $ (!K1_cntr_7_carry_eqn);
|
| 1652 |
|
|
K1_cntr_7 = DFFEAS(K1_cntr_7_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[7], , , !K1_un1_ld_1);
|
| 1653 |
|
|
|
| 1654 |
|
|
--K1_cntr_cout[7] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[7]
|
| 1655 |
|
|
--operation mode is arithmetic
|
| 1656 |
|
|
|
| 1657 |
|
|
K1_cntr_cout[7] = CARRY(!K1_cntr_7 & !K1_cntr_cout[6]);
|
| 1658 |
|
|
|
| 1659 |
|
|
|
| 1660 |
|
|
--F1_dout_0_0_a3_4[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_4[0]
|
| 1661 |
|
|
--operation mode is normal
|
| 1662 |
|
|
|
| 1663 |
|
|
F1_dout_0_0_a3_4[0] = sys_rst & AB1_r32_o_3 & F1_rd_cmd_0_a2_2 & F1_rd_uartdata_0_a2_0;
|
| 1664 |
|
|
|
| 1665 |
|
|
|
| 1666 |
|
|
--F1_dout_0_0_a[7] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[7]
|
| 1667 |
|
|
--operation mode is normal
|
| 1668 |
|
|
|
| 1669 |
|
|
F1_dout_0_0_a[7] = F1_cmd[7] & !F1_dout_0_0_a3_3[0] & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_7 # !F1_cmd[7] & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_7;
|
| 1670 |
|
|
|
| 1671 |
|
|
|
| 1672 |
|
|
--WC1_wb_mux_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_1:U21|wb_mux_ctl_o_0
|
| 1673 |
|
|
--operation mode is normal
|
| 1674 |
|
|
|
| 1675 |
|
|
WC1_wb_mux_ctl_o_0_lut_out = NC1_wb_mux_ctl_o_0;
|
| 1676 |
|
|
WC1_wb_mux_ctl_o_0 = DFFEAS(WC1_wb_mux_ctl_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 1677 |
|
|
|
| 1678 |
|
|
|
| 1679 |
|
|
--GD1_dout_iv_1_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_7
|
| 1680 |
|
|
--operation mode is normal
|
| 1681 |
|
|
|
| 1682 |
|
|
GD1_dout_iv_1_7 = FD1_N_20_i_0_s3 & LD1_q_b[7] # !GD1_dout_iv_1_a[7];
|
| 1683 |
|
|
|
| 1684 |
|
|
|
| 1685 |
|
|
--GD1_dout7_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout7_0_a2
|
| 1686 |
|
|
--operation mode is normal
|
| 1687 |
|
|
|
| 1688 |
|
|
GD1_dout7_0_a2 = MC1_wb_we_o_0 & !WD1_un30_mux_fw & !ZD1_un17_mux_fw_NE & !ZD1_mux_fw_1;
|
| 1689 |
|
|
|
| 1690 |
|
|
|
| 1691 |
|
|
--UD1_shift_out_89_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_6
|
| 1692 |
|
|
--operation mode is normal
|
| 1693 |
|
|
|
| 1694 |
|
|
UD1_shift_out_89_6 = UD1_shift_out586 & !UD1_shift_out_89_a[7] # !UD1_shift_out586 & UD1_shift_out_87[7];
|
| 1695 |
|
|
|
| 1696 |
|
|
|
| 1697 |
|
|
--UD1_shift_out_sn_m31_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m31_i
|
| 1698 |
|
|
--operation mode is normal
|
| 1699 |
|
|
|
| 1700 |
|
|
UD1_shift_out_sn_m31_i = !PD1_a_o_2 & !PD1_a_o_1 & !PD1_a_o_0 # !UD1_shift_out_sn_m31_i_a;
|
| 1701 |
|
|
|
| 1702 |
|
|
|
| 1703 |
|
|
--MD1_c_a_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_7
|
| 1704 |
|
|
--operation mode is normal
|
| 1705 |
|
|
|
| 1706 |
|
|
MD1_c_a_7 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91_7 # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86_7;
|
| 1707 |
|
|
|
| 1708 |
|
|
|
| 1709 |
|
|
--MD1_c_0_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_6
|
| 1710 |
|
|
--operation mode is normal
|
| 1711 |
|
|
|
| 1712 |
|
|
MD1_c_0_6 = RC1_alu_func_o_4 & !TD1_m11 # !RC1_alu_func_o_4 & TD1_m1 # !MD1_c_0_a[7];
|
| 1713 |
|
|
|
| 1714 |
|
|
|
| 1715 |
|
|
--XD1_mux_fw_1_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|mux_fw_1_a
|
| 1716 |
|
|
--operation mode is normal
|
| 1717 |
|
|
|
| 1718 |
|
|
XD1_mux_fw_1_a = MB1_r5_o_4 $ BE1_q_4 # !XC1_wb_we_o_0;
|
| 1719 |
|
|
|
| 1720 |
|
|
|
| 1721 |
|
|
--XD1_un1_mux_fw_NE_2 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un1_mux_fw_NE_2
|
| 1722 |
|
|
--operation mode is normal
|
| 1723 |
|
|
|
| 1724 |
|
|
XD1_un1_mux_fw_NE_2 = MB1_r5_o_3 & MB1_r5_o_2 $ BE1_q_2 # !BE1_q_3 # !MB1_r5_o_3 & BE1_q_3 # MB1_r5_o_2 $ BE1_q_2;
|
| 1725 |
|
|
|
| 1726 |
|
|
|
| 1727 |
|
|
--XD1_un1_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un1_mux_fw_NE_1
|
| 1728 |
|
|
--operation mode is normal
|
| 1729 |
|
|
|
| 1730 |
|
|
XD1_un1_mux_fw_NE_1 = MB1_r5_o_1 & MB1_r5_o_0 $ BE1_q_0 # !BE1_q_1 # !MB1_r5_o_1 & BE1_q_1 # MB1_r5_o_0 $ BE1_q_0;
|
| 1731 |
|
|
|
| 1732 |
|
|
|
| 1733 |
|
|
--WD1_un14_mux_fw is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un14_mux_fw
|
| 1734 |
|
|
--operation mode is normal
|
| 1735 |
|
|
|
| 1736 |
|
|
WD1_un14_mux_fw = !MB1_r5_o_3 & !MB1_r5_o_0 & !MB1_r5_o_2 & WD1_un14_mux_fw_a;
|
| 1737 |
|
|
|
| 1738 |
|
|
|
| 1739 |
|
|
--VC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_1:U20|wb_we_o_0
|
| 1740 |
|
|
--operation mode is normal
|
| 1741 |
|
|
|
| 1742 |
|
|
VC1_wb_we_o_0_lut_out = UC1_wb_we_o_0;
|
| 1743 |
|
|
VC1_wb_we_o_0 = DFFEAS(VC1_wb_we_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 1744 |
|
|
|
| 1745 |
|
|
|
| 1746 |
|
|
--XC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_2:U22|wb_we_o_0
|
| 1747 |
|
|
--operation mode is normal
|
| 1748 |
|
|
|
| 1749 |
|
|
XC1_wb_we_o_0_lut_out = YC1_alu_we_o_0;
|
| 1750 |
|
|
XC1_wb_we_o_0 = DFFEAS(XC1_wb_we_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 1751 |
|
|
|
| 1752 |
|
|
|
| 1753 |
|
|
--NB1_r5_o_3 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_3
|
| 1754 |
|
|
--operation mode is normal
|
| 1755 |
|
|
|
| 1756 |
|
|
NB1_r5_o_3_lut_out = MB1_r5_o_3;
|
| 1757 |
|
|
NB1_r5_o_3 = DFFEAS(NB1_r5_o_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 1758 |
|
|
|
| 1759 |
|
|
|
| 1760 |
|
|
--NB1_r5_o_0 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_0
|
| 1761 |
|
|
--operation mode is normal
|
| 1762 |
|
|
|
| 1763 |
|
|
NB1_r5_o_0_lut_out = MB1_r5_o_0;
|
| 1764 |
|
|
NB1_r5_o_0 = DFFEAS(NB1_r5_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 1765 |
|
|
|
| 1766 |
|
|
|
| 1767 |
|
|
--NB1_r5_o_1 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_1
|
| 1768 |
|
|
--operation mode is normal
|
| 1769 |
|
|
|
| 1770 |
|
|
NB1_r5_o_1_lut_out = MB1_r5_o_1;
|
| 1771 |
|
|
NB1_r5_o_1 = DFFEAS(NB1_r5_o_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 1772 |
|
|
|
| 1773 |
|
|
|
| 1774 |
|
|
--WD1_un30_mux_fw_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un30_mux_fw_a
|
| 1775 |
|
|
--operation mode is normal
|
| 1776 |
|
|
|
| 1777 |
|
|
WD1_un30_mux_fw_a = !NB1_r5_o_2 & !NB1_r5_o_4;
|
| 1778 |
|
|
|
| 1779 |
|
|
|
| 1780 |
|
|
--BE1_q_4 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_4
|
| 1781 |
|
|
--operation mode is normal
|
| 1782 |
|
|
|
| 1783 |
|
|
BE1_q_4_lut_out = ED1_r32_o_20;
|
| 1784 |
|
|
BE1_q_4 = DFFEAS(BE1_q_4_lut_out, E1__clk0, VCC, , , , , , );
|
| 1785 |
|
|
|
| 1786 |
|
|
|
| 1787 |
|
|
--NB1_r5_o_4 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_4
|
| 1788 |
|
|
--operation mode is normal
|
| 1789 |
|
|
|
| 1790 |
|
|
NB1_r5_o_4_lut_out = MB1_r5_o_4;
|
| 1791 |
|
|
NB1_r5_o_4 = DFFEAS(NB1_r5_o_4_lut_out, E1__clk0, VCC, , , , , , );
|
| 1792 |
|
|
|
| 1793 |
|
|
|
| 1794 |
|
|
--XD1_un17_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un17_mux_fw_NE_1
|
| 1795 |
|
|
--operation mode is normal
|
| 1796 |
|
|
|
| 1797 |
|
|
XD1_un17_mux_fw_NE_1 = BE1_q_1 & BE1_q_0 $ NB1_r5_o_0 # !NB1_r5_o_1 # !BE1_q_1 & NB1_r5_o_1 # BE1_q_0 $ NB1_r5_o_0;
|
| 1798 |
|
|
|
| 1799 |
|
|
|
| 1800 |
|
|
--XD1_un17_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un17_mux_fw_NE_a
|
| 1801 |
|
|
--operation mode is normal
|
| 1802 |
|
|
|
| 1803 |
|
|
XD1_un17_mux_fw_NE_a = BE1_q_2 & BE1_q_3 $ NB1_r5_o_3 # !NB1_r5_o_2 # !BE1_q_2 & NB1_r5_o_2 # BE1_q_3 $ NB1_r5_o_3;
|
| 1804 |
|
|
|
| 1805 |
|
|
|
| 1806 |
|
|
--RC1_alu_func_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_1
|
| 1807 |
|
|
--operation mode is normal
|
| 1808 |
|
|
|
| 1809 |
|
|
RC1_alu_func_o_1_lut_out = ZC1_alu_func_o_1;
|
| 1810 |
|
|
RC1_alu_func_o_1 = DFFEAS(RC1_alu_func_o_1_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 1811 |
|
|
|
| 1812 |
|
|
|
| 1813 |
|
|
--TD1_alu_out_sn_m14_0_0_a4_0_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0_a4_0_a
|
| 1814 |
|
|
--operation mode is normal
|
| 1815 |
|
|
|
| 1816 |
|
|
TD1_alu_out_sn_m14_0_0_a4_0_a = !RC1_alu_func_o_3 # !RC1_alu_func_o_2;
|
| 1817 |
|
|
|
| 1818 |
|
|
|
| 1819 |
|
|
--RC1_alu_func_o_4 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_4
|
| 1820 |
|
|
--operation mode is normal
|
| 1821 |
|
|
|
| 1822 |
|
|
RC1_alu_func_o_4_lut_out = ZC1_alu_func_o_4;
|
| 1823 |
|
|
RC1_alu_func_o_4 = DFFEAS(RC1_alu_func_o_4_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 1824 |
|
|
|
| 1825 |
|
|
|
| 1826 |
|
|
--RC1_alu_func_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_0
|
| 1827 |
|
|
--operation mode is normal
|
| 1828 |
|
|
|
| 1829 |
|
|
RC1_alu_func_o_0_lut_out = ZC1_alu_func_o_0;
|
| 1830 |
|
|
RC1_alu_func_o_0 = DFFEAS(RC1_alu_func_o_0_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 1831 |
|
|
|
| 1832 |
|
|
|
| 1833 |
|
|
--TD1_alu_out_sn_m14_0_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0
|
| 1834 |
|
|
--operation mode is normal
|
| 1835 |
|
|
|
| 1836 |
|
|
TD1_alu_out_sn_m14_0_0 = TD1_alu_out_sn_m14_0_0_a4_0 # TD1_alu_out_sn_m14_0_0_a4 # UD1_shift_out588_0 & RC1_alu_func_o_4;
|
| 1837 |
|
|
|
| 1838 |
|
|
|
| 1839 |
|
|
--MD1_c_0_Z[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_Z[4]
|
| 1840 |
|
|
--operation mode is normal
|
| 1841 |
|
|
|
| 1842 |
|
|
MD1_c_0_Z[4] = TD1_alu_out_0_a3_0_0 & VD1_b_o_iv_4 # !MD1_c_0_a[4];
|
| 1843 |
|
|
|
| 1844 |
|
|
|
| 1845 |
|
|
--TD1_alu_out_7_0_0_m2_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_1
|
| 1846 |
|
|
--operation mode is normal
|
| 1847 |
|
|
|
| 1848 |
|
|
TD1_alu_out_7_0_0_m2_1 = PD1_a_o_4 & !TD1_alu_out_7_0_0_m2_a[4] # !PD1_a_o_4 & TD1_alu_out_7_0_0_m4_0[4];
|
| 1849 |
|
|
|
| 1850 |
|
|
|
| 1851 |
|
|
--PD1_a_o_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_4
|
| 1852 |
|
|
--operation mode is normal
|
| 1853 |
|
|
|
| 1854 |
|
|
PD1_a_o_4 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[4] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[4];
|
| 1855 |
|
|
|
| 1856 |
|
|
|
| 1857 |
|
|
--TD1_un1_b_1_combout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[4]
|
| 1858 |
|
|
--operation mode is normal
|
| 1859 |
|
|
|
| 1860 |
|
|
TD1_un1_b_1_combout[4] = TD1_sum13_0_a2 $ !VD1_b_o_iv_4;
|
| 1861 |
|
|
|
| 1862 |
|
|
|
| 1863 |
|
|
--TD1_un1_a_add3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add3
|
| 1864 |
|
|
--operation mode is arithmetic
|
| 1865 |
|
|
|
| 1866 |
|
|
TD1_un1_a_add3_carry_eqn = TD1_un1_a_carry_2;
|
| 1867 |
|
|
TD1_un1_a_add3 = PD1_a_o_3 $ TD1_un1_b_1_combout[3] $ TD1_un1_a_add3_carry_eqn;
|
| 1868 |
|
|
|
| 1869 |
|
|
--TD1_un1_a_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_3
|
| 1870 |
|
|
--operation mode is arithmetic
|
| 1871 |
|
|
|
| 1872 |
|
|
TD1_un1_a_carry_3 = CARRY(PD1_a_o_3 & !TD1_un1_b_1_combout[3] & !TD1_un1_a_carry_2 # !PD1_a_o_3 & !TD1_un1_a_carry_2 # !TD1_un1_b_1_combout[3]);
|
| 1873 |
|
|
|
| 1874 |
|
|
|
| 1875 |
|
|
--UD1_shift_out_89[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[4]
|
| 1876 |
|
|
--operation mode is normal
|
| 1877 |
|
|
|
| 1878 |
|
|
UD1_shift_out_89[4] = UD1_shift_out586 & UD1_shift_out_85[4] # !UD1_shift_out586 & UD1_shift_out_87[4];
|
| 1879 |
|
|
|
| 1880 |
|
|
|
| 1881 |
|
|
--UD1_shift_out_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[4]
|
| 1882 |
|
|
--operation mode is normal
|
| 1883 |
|
|
|
| 1884 |
|
|
UD1_shift_out_a[4] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91[4] # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86[4];
|
| 1885 |
|
|
|
| 1886 |
|
|
|
| 1887 |
|
|
--MD1_c_0_Z[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_Z[5]
|
| 1888 |
|
|
--operation mode is normal
|
| 1889 |
|
|
|
| 1890 |
|
|
MD1_c_0_Z[5] = VD1_hilo_5 & VD1_un11_res # VD1_hilo_37 & VD1_un24_res # !VD1_hilo_5 & VD1_hilo_37 & VD1_un24_res;
|
| 1891 |
|
|
|
| 1892 |
|
|
|
| 1893 |
|
|
--MD1_c_2_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_a[5]
|
| 1894 |
|
|
--operation mode is normal
|
| 1895 |
|
|
|
| 1896 |
|
|
MD1_c_2_a[5] = !TD1_alu_out_7_0_0_o3_0 & RC1_alu_func_o_4 & RC1_alu_func_o_0 & VD1_b_o_iv_5;
|
| 1897 |
|
|
|
| 1898 |
|
|
|
| 1899 |
|
|
--TD1_alu_out_7_0_0_m2_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_2
|
| 1900 |
|
|
--operation mode is normal
|
| 1901 |
|
|
|
| 1902 |
|
|
TD1_alu_out_7_0_0_m2_2 = PD1_a_o_5 & !TD1_alu_out_7_0_0_m2_a[5] # !PD1_a_o_5 & TD1_alu_out_7_0_0_m4_0[5];
|
| 1903 |
|
|
|
| 1904 |
|
|
|
| 1905 |
|
|
--PD1_a_o_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_5
|
| 1906 |
|
|
--operation mode is normal
|
| 1907 |
|
|
|
| 1908 |
|
|
PD1_a_o_5 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[5] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[5];
|
| 1909 |
|
|
|
| 1910 |
|
|
|
| 1911 |
|
|
--TD1_un1_b_1_combout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[5]
|
| 1912 |
|
|
--operation mode is normal
|
| 1913 |
|
|
|
| 1914 |
|
|
TD1_un1_b_1_combout[5] = TD1_sum13_0_a2 $ !VD1_b_o_iv_5;
|
| 1915 |
|
|
|
| 1916 |
|
|
|
| 1917 |
|
|
--UD1_shift_out_89[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[5]
|
| 1918 |
|
|
--operation mode is normal
|
| 1919 |
|
|
|
| 1920 |
|
|
UD1_shift_out_89[5] = UD1_shift_out586 & !UD1_shift_out_89_a[5] # !UD1_shift_out586 & UD1_shift_out_87[5];
|
| 1921 |
|
|
|
| 1922 |
|
|
|
| 1923 |
|
|
--UD1_shift_out_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[5]
|
| 1924 |
|
|
--operation mode is normal
|
| 1925 |
|
|
|
| 1926 |
|
|
UD1_shift_out_a[5] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91[5] # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86[5];
|
| 1927 |
|
|
|
| 1928 |
|
|
|
| 1929 |
|
|
--QC1_dmem_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15|dmem_ctl_o_2
|
| 1930 |
|
|
--operation mode is normal
|
| 1931 |
|
|
|
| 1932 |
|
|
QC1_dmem_ctl_o_2_lut_out = CC1_dmem_ctl_o_2;
|
| 1933 |
|
|
QC1_dmem_ctl_o_2 = DFFEAS(QC1_dmem_ctl_o_2_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 1934 |
|
|
|
| 1935 |
|
|
|
| 1936 |
|
|
--UD1_shift_out_89_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_1
|
| 1937 |
|
|
--operation mode is normal
|
| 1938 |
|
|
|
| 1939 |
|
|
UD1_shift_out_89_1 = UD1_shift_out586 & !PD1_a_o_2 & UD1_shift_out_89_a[2] # !UD1_shift_out586 & UD1_shift_out_87[2];
|
| 1940 |
|
|
|
| 1941 |
|
|
|
| 1942 |
|
|
--MD1_c_a_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_2
|
| 1943 |
|
|
--operation mode is normal
|
| 1944 |
|
|
|
| 1945 |
|
|
MD1_c_a_2 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91_2 # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86_2;
|
| 1946 |
|
|
|
| 1947 |
|
|
|
| 1948 |
|
|
--MD1_c_0_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_1
|
| 1949 |
|
|
--operation mode is normal
|
| 1950 |
|
|
|
| 1951 |
|
|
MD1_c_0_1 = RC1_alu_func_o_4 & !TD1_m112 # !RC1_alu_func_o_4 & TD1_m109 # !MD1_c_0_a[2];
|
| 1952 |
|
|
|
| 1953 |
|
|
|
| 1954 |
|
|
--MD1_c_1_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_3
|
| 1955 |
|
|
--operation mode is normal
|
| 1956 |
|
|
|
| 1957 |
|
|
MD1_c_1_3 = MD1_c_0_Z[3] # TD1_alu_out_sn_m14_0_0 & TD1_alu_out_7_0_0_m2_0;
|
| 1958 |
|
|
|
| 1959 |
|
|
|
| 1960 |
|
|
--UD1_shift_out_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_3
|
| 1961 |
|
|
--operation mode is normal
|
| 1962 |
|
|
|
| 1963 |
|
|
UD1_shift_out_3 = UD1_shift_out_sn_m31_i & !UD1_shift_out_a[3] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[3];
|
| 1964 |
|
|
|
| 1965 |
|
|
|
| 1966 |
|
|
--QC1_dmem_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15|dmem_ctl_o_0
|
| 1967 |
|
|
--operation mode is normal
|
| 1968 |
|
|
|
| 1969 |
|
|
QC1_dmem_ctl_o_0_lut_out = CC1_dmem_ctl_o_0;
|
| 1970 |
|
|
QC1_dmem_ctl_o_0 = DFFEAS(QC1_dmem_ctl_o_0_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 1971 |
|
|
|
| 1972 |
|
|
|
| 1973 |
|
|
--QC1_dmem_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15|dmem_ctl_o_1
|
| 1974 |
|
|
--operation mode is normal
|
| 1975 |
|
|
|
| 1976 |
|
|
QC1_dmem_ctl_o_1_lut_out = CC1_dmem_ctl_o_1;
|
| 1977 |
|
|
QC1_dmem_ctl_o_1 = DFFEAS(QC1_dmem_ctl_o_1_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 1978 |
|
|
|
| 1979 |
|
|
|
| 1980 |
|
|
--F1_dout_0_0_a3_6_5_9[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_9[0]
|
| 1981 |
|
|
--operation mode is normal
|
| 1982 |
|
|
|
| 1983 |
|
|
F1_dout_0_0_a3_6_5_9[0] = !AB1_r32_o_14 & !AB1_r32_o_15 & !AB1_r32_o_12 & !AB1_r32_o_13;
|
| 1984 |
|
|
|
| 1985 |
|
|
|
| 1986 |
|
|
--F1_rd_status_29_0_a2_0_8 is mips_sys:isys|mips_dvc:imips_dvc|rd_status_29_0_a2_0_8
|
| 1987 |
|
|
--operation mode is normal
|
| 1988 |
|
|
|
| 1989 |
|
|
F1_rd_status_29_0_a2_0_8 = !AB1_r32_o_5 & AB1_r32_o_29 & !RB1_byte_addr_o_1 & F1_rd_status_29_0_a2_0_8_a;
|
| 1990 |
|
|
|
| 1991 |
|
|
|
| 1992 |
|
|
--F1_dout_0_0_a3_6_5_12[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_12[0]
|
| 1993 |
|
|
--operation mode is normal
|
| 1994 |
|
|
|
| 1995 |
|
|
F1_dout_0_0_a3_6_5_12[0] = !AB1_r32_o_19 & !AB1_r32_o_18 & F1_dout_0_0_a3_6_5_2[0] & F1_dout_0_0_a3_6_5_12_a[0];
|
| 1996 |
|
|
|
| 1997 |
|
|
|
| 1998 |
|
|
--F1_rd_uartdata_0_a2_0_a is mips_sys:isys|mips_dvc:imips_dvc|rd_uartdata_0_a2_0_a
|
| 1999 |
|
|
--operation mode is normal
|
| 2000 |
|
|
|
| 2001 |
|
|
F1_rd_uartdata_0_a2_0_a = !AB1_r32_o_11 & !AB1_r32_o_28 & JC1_rd_status_29_0_a2_0_7 & F1_dout_0_0_a3_6_5_8[0];
|
| 2002 |
|
|
|
| 2003 |
|
|
|
| 2004 |
|
|
--K1_cntr_6 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_6
|
| 2005 |
|
|
--operation mode is arithmetic
|
| 2006 |
|
|
|
| 2007 |
|
|
K1_cntr_6_carry_eqn = K1_cntr_cout[5];
|
| 2008 |
|
|
K1_cntr_6_lut_out = K1_cntr_6 $ (K1_cntr_6_carry_eqn);
|
| 2009 |
|
|
K1_cntr_6 = DFFEAS(K1_cntr_6_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[6], , , !K1_un1_ld_1);
|
| 2010 |
|
|
|
| 2011 |
|
|
--K1_cntr_cout[6] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[6]
|
| 2012 |
|
|
--operation mode is arithmetic
|
| 2013 |
|
|
|
| 2014 |
|
|
K1_cntr_cout[6] = CARRY(K1_cntr_6 # !K1_cntr_cout[5]);
|
| 2015 |
|
|
|
| 2016 |
|
|
|
| 2017 |
|
|
--F1_dout_0_0_a[6] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[6]
|
| 2018 |
|
|
--operation mode is normal
|
| 2019 |
|
|
|
| 2020 |
|
|
F1_dout_0_0_a[6] = F1_cmd_6 & !F1_dout_0_0_a3_3[0] & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_6 # !F1_cmd_6 & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_6;
|
| 2021 |
|
|
|
| 2022 |
|
|
|
| 2023 |
|
|
--GD1_dout_iv_1_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_6
|
| 2024 |
|
|
--operation mode is normal
|
| 2025 |
|
|
|
| 2026 |
|
|
GD1_dout_iv_1_6 = FD1_N_20_i_0_s3 & LD1_q_b[6] # !GD1_dout_iv_1_a[6];
|
| 2027 |
|
|
|
| 2028 |
|
|
|
| 2029 |
|
|
--UD1_shift_out_89_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_5
|
| 2030 |
|
|
--operation mode is normal
|
| 2031 |
|
|
|
| 2032 |
|
|
UD1_shift_out_89_5 = UD1_shift_out586 & !UD1_shift_out_89_a[6] # !UD1_shift_out586 & UD1_shift_out_87[6];
|
| 2033 |
|
|
|
| 2034 |
|
|
|
| 2035 |
|
|
--MD1_c_a_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_6
|
| 2036 |
|
|
--operation mode is normal
|
| 2037 |
|
|
|
| 2038 |
|
|
MD1_c_a_6 = !MD1_c_1_Z[6] & !TD1_un1_a_add6 # !TD1_alu_out_sn_m14_0_0_a4_0;
|
| 2039 |
|
|
|
| 2040 |
|
|
|
| 2041 |
|
|
--UD1_shift_out_92_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_0
|
| 2042 |
|
|
--operation mode is normal
|
| 2043 |
|
|
|
| 2044 |
|
|
UD1_shift_out_92_0 = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[6] # !UD1_shift_out_sn_m25_0 & !UD1_shift_out586 & UD1_shift_out_86[6];
|
| 2045 |
|
|
|
| 2046 |
|
|
|
| 2047 |
|
|
--K1_cntr_5 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5
|
| 2048 |
|
|
--operation mode is arithmetic
|
| 2049 |
|
|
|
| 2050 |
|
|
K1_cntr_5_carry_eqn = K1_cntr_cout[4];
|
| 2051 |
|
|
K1_cntr_5_lut_out = K1_cntr_5 $ (!K1_cntr_5_carry_eqn);
|
| 2052 |
|
|
K1_cntr_5 = DFFEAS(K1_cntr_5_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[5], , , !K1_un1_ld_1);
|
| 2053 |
|
|
|
| 2054 |
|
|
--K1_cntr_cout[5] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[5]
|
| 2055 |
|
|
--operation mode is arithmetic
|
| 2056 |
|
|
|
| 2057 |
|
|
K1_cntr_cout[5] = CARRY(!K1_cntr_5 & !K1_cntr_cout[4]);
|
| 2058 |
|
|
|
| 2059 |
|
|
|
| 2060 |
|
|
--F1_dout_0_0_a[5] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[5]
|
| 2061 |
|
|
--operation mode is normal
|
| 2062 |
|
|
|
| 2063 |
|
|
F1_dout_0_0_a[5] = F1_cmd_5 & !F1_dout_0_0_a3_3[0] & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_5 # !F1_cmd_5 & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_5;
|
| 2064 |
|
|
|
| 2065 |
|
|
|
| 2066 |
|
|
--GD1_dout_iv_1_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_5
|
| 2067 |
|
|
--operation mode is normal
|
| 2068 |
|
|
|
| 2069 |
|
|
GD1_dout_iv_1_5 = FD1_N_20_i_0_s3 & LD1_q_b[5] # !GD1_dout_iv_1_a[5];
|
| 2070 |
|
|
|
| 2071 |
|
|
|
| 2072 |
|
|
--K1_cntr_4 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_4
|
| 2073 |
|
|
--operation mode is arithmetic
|
| 2074 |
|
|
|
| 2075 |
|
|
K1_cntr_4_carry_eqn = K1_cntr_cout[3];
|
| 2076 |
|
|
K1_cntr_4_lut_out = K1_cntr_4 $ (K1_cntr_4_carry_eqn);
|
| 2077 |
|
|
K1_cntr_4 = DFFEAS(K1_cntr_4_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[4], , , !K1_un1_ld_1);
|
| 2078 |
|
|
|
| 2079 |
|
|
--K1_cntr_cout[4] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[4]
|
| 2080 |
|
|
--operation mode is arithmetic
|
| 2081 |
|
|
|
| 2082 |
|
|
K1_cntr_cout[4] = CARRY(K1_cntr_4 # !K1_cntr_cout[3]);
|
| 2083 |
|
|
|
| 2084 |
|
|
|
| 2085 |
|
|
--F1_dout_0_0_a[4] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[4]
|
| 2086 |
|
|
--operation mode is normal
|
| 2087 |
|
|
|
| 2088 |
|
|
F1_dout_0_0_a[4] = F1_cmd_4 & !F1_dout_0_0_a3_3[0] & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_4 # !F1_cmd_4 & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_4;
|
| 2089 |
|
|
|
| 2090 |
|
|
|
| 2091 |
|
|
--GD1_dout_iv_1_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_4
|
| 2092 |
|
|
--operation mode is normal
|
| 2093 |
|
|
|
| 2094 |
|
|
GD1_dout_iv_1_4 = FD1_N_20_i_0_s3 & LD1_q_b[4] # !GD1_dout_iv_1_a[4];
|
| 2095 |
|
|
|
| 2096 |
|
|
|
| 2097 |
|
|
--K1_cntr_3 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_3
|
| 2098 |
|
|
--operation mode is arithmetic
|
| 2099 |
|
|
|
| 2100 |
|
|
K1_cntr_3_carry_eqn = K1_cntr_cout[2];
|
| 2101 |
|
|
K1_cntr_3_lut_out = K1_cntr_3 $ (!K1_cntr_3_carry_eqn);
|
| 2102 |
|
|
K1_cntr_3 = DFFEAS(K1_cntr_3_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[3], , , !K1_un1_ld_1);
|
| 2103 |
|
|
|
| 2104 |
|
|
--K1_cntr_cout[3] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[3]
|
| 2105 |
|
|
--operation mode is arithmetic
|
| 2106 |
|
|
|
| 2107 |
|
|
K1_cntr_cout[3] = CARRY(!K1_cntr_3 & !K1_cntr_cout[2]);
|
| 2108 |
|
|
|
| 2109 |
|
|
|
| 2110 |
|
|
--L1_dout_0_0_a_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|rxd_d:rxd_rdy_hold_lw|dout_0_0_a_0
|
| 2111 |
|
|
--operation mode is normal
|
| 2112 |
|
|
|
| 2113 |
|
|
L1_q_Z_qfbk = L1_q_Z;
|
| 2114 |
|
|
L1_dout_0_0_a_0 = M1_buffer_reg_3 & !F1_dout_0_0_a3_5_x[0] & !L1_q_Z_qfbk # !F1_dout_0_0_a3_6[0] # !M1_buffer_reg_3 & !L1_q_Z_qfbk # !F1_dout_0_0_a3_6[0];
|
| 2115 |
|
|
|
| 2116 |
|
|
--L1_q_Z is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|rxd_d:rxd_rdy_hold_lw|q_Z
|
| 2117 |
|
|
--operation mode is normal
|
| 2118 |
|
|
|
| 2119 |
|
|
L1_q_Z = DFFEAS(L1_dout_0_0_a_0, E1__clk0, !F1_cmd[1], , M1_int_req, VCC, , , VCC);
|
| 2120 |
|
|
|
| 2121 |
|
|
|
| 2122 |
|
|
--F1_dout_0_0_a3_0[3] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_0[3]
|
| 2123 |
|
|
--operation mode is normal
|
| 2124 |
|
|
|
| 2125 |
|
|
F1_dout_0_0_a3_0[3] = F1_cmd_3 & F1_dout_0_0_a3_3[0];
|
| 2126 |
|
|
|
| 2127 |
|
|
|
| 2128 |
|
|
--GD1_dout_iv_1_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_3
|
| 2129 |
|
|
--operation mode is normal
|
| 2130 |
|
|
|
| 2131 |
|
|
GD1_dout_iv_1_3 = FD1_N_20_i_0_s3 & LD1_q_b[3] # !GD1_dout_iv_1_a[3];
|
| 2132 |
|
|
|
| 2133 |
|
|
|
| 2134 |
|
|
--K1_cntr_2 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_2
|
| 2135 |
|
|
--operation mode is arithmetic
|
| 2136 |
|
|
|
| 2137 |
|
|
K1_cntr_2_carry_eqn = K1_cntr_cout[1];
|
| 2138 |
|
|
K1_cntr_2_lut_out = K1_cntr_2 $ (K1_cntr_2_carry_eqn);
|
| 2139 |
|
|
K1_cntr_2 = DFFEAS(K1_cntr_2_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[2], , , !K1_un1_ld_1);
|
| 2140 |
|
|
|
| 2141 |
|
|
--K1_cntr_cout[2] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[2]
|
| 2142 |
|
|
--operation mode is arithmetic
|
| 2143 |
|
|
|
| 2144 |
|
|
K1_cntr_cout[2] = CARRY(K1_cntr_2 # !K1_cntr_cout[1]);
|
| 2145 |
|
|
|
| 2146 |
|
|
|
| 2147 |
|
|
--F1_dout_0_0_a[2] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[2]
|
| 2148 |
|
|
--operation mode is normal
|
| 2149 |
|
|
|
| 2150 |
|
|
F1_dout_0_0_a[2] = U1_b_full & !F1_dout_0_0_a3_6[0] & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_2 # !U1_b_full & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_2;
|
| 2151 |
|
|
|
| 2152 |
|
|
|
| 2153 |
|
|
--F1_dout_0_0_a3_0[2] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_0[2]
|
| 2154 |
|
|
--operation mode is normal
|
| 2155 |
|
|
|
| 2156 |
|
|
F1_dout_0_0_a3_0[2] = F1_cmd_2 & F1_dout_0_0_a3_3[0];
|
| 2157 |
|
|
|
| 2158 |
|
|
|
| 2159 |
|
|
--GD1_dout_iv_1_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_2
|
| 2160 |
|
|
--operation mode is normal
|
| 2161 |
|
|
|
| 2162 |
|
|
GD1_dout_iv_1_2 = FD1_N_20_i_0_s3 & LD1_q_b[2] # !GD1_dout_iv_1_a[2];
|
| 2163 |
|
|
|
| 2164 |
|
|
|
| 2165 |
|
|
--K1_cntr_1 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_1
|
| 2166 |
|
|
--operation mode is arithmetic
|
| 2167 |
|
|
|
| 2168 |
|
|
K1_cntr_1_carry_eqn = K1_cntr_cout[0];
|
| 2169 |
|
|
K1_cntr_1_lut_out = K1_cntr_1 $ (!K1_cntr_1_carry_eqn);
|
| 2170 |
|
|
K1_cntr_1 = DFFEAS(K1_cntr_1_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[1], , , !K1_un1_ld_1);
|
| 2171 |
|
|
|
| 2172 |
|
|
--K1_cntr_cout[1] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[1]
|
| 2173 |
|
|
--operation mode is arithmetic
|
| 2174 |
|
|
|
| 2175 |
|
|
K1_cntr_cout[1] = CARRY(!K1_cntr_1 & !K1_cntr_cout[0]);
|
| 2176 |
|
|
|
| 2177 |
|
|
|
| 2178 |
|
|
--F1_dout_0_0_a[1] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[1]
|
| 2179 |
|
|
--operation mode is normal
|
| 2180 |
|
|
|
| 2181 |
|
|
F1_rr_key1_Z_qfbk = F1_rr_key1_Z;
|
| 2182 |
|
|
F1_dout_0_0_a[1] = M1_buffer_reg_1 & !F1_dout_0_0_a3_5_x[0] & !F1_rr_key1_Z_qfbk # !F1_dout_0_0_a3_6[0] # !M1_buffer_reg_1 & !F1_rr_key1_Z_qfbk # !F1_dout_0_0_a3_6[0];
|
| 2183 |
|
|
|
| 2184 |
|
|
--F1_rr_key1_Z is mips_sys:isys|mips_dvc:imips_dvc|rr_key1_Z
|
| 2185 |
|
|
--operation mode is normal
|
| 2186 |
|
|
|
| 2187 |
|
|
F1_rr_key1_Z = DFFEAS(F1_dout_0_0_a[1], E1__clk0, VCC, , , F1_r_key1, , , VCC);
|
| 2188 |
|
|
|
| 2189 |
|
|
|
| 2190 |
|
|
--F1_dout_0_0_a3_0[1] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_0[1]
|
| 2191 |
|
|
--operation mode is normal
|
| 2192 |
|
|
|
| 2193 |
|
|
F1_dout_0_0_a3_0[1] = F1_cmd[1] & F1_dout_0_0_a3_3[0];
|
| 2194 |
|
|
|
| 2195 |
|
|
|
| 2196 |
|
|
--GD1_dout_iv_1_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_1
|
| 2197 |
|
|
--operation mode is normal
|
| 2198 |
|
|
|
| 2199 |
|
|
GD1_dout_iv_1_1 = FD1_N_20_i_0_s3 & LD1_q_b[1] # !GD1_dout_iv_1_a[1];
|
| 2200 |
|
|
|
| 2201 |
|
|
|
| 2202 |
|
|
--UD1_shift_out_89_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_0
|
| 2203 |
|
|
--operation mode is normal
|
| 2204 |
|
|
|
| 2205 |
|
|
UD1_shift_out_89_0 = UD1_shift_out586 & !PD1_a_o_1 & UD1_shift_out_89_a[1] # !UD1_shift_out586 & UD1_shift_out_87[1];
|
| 2206 |
|
|
|
| 2207 |
|
|
|
| 2208 |
|
|
--MD1_c_a_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_1
|
| 2209 |
|
|
--operation mode is normal
|
| 2210 |
|
|
|
| 2211 |
|
|
MD1_c_a_1 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91_1 # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86_1;
|
| 2212 |
|
|
|
| 2213 |
|
|
|
| 2214 |
|
|
--MD1_c_0_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_0
|
| 2215 |
|
|
--operation mode is normal
|
| 2216 |
|
|
|
| 2217 |
|
|
MD1_c_0_0 = TD1_alu_out_sn_m14_0_0 & TD1_alu_out_7_0_0 # !MD1_c_0_a[1];
|
| 2218 |
|
|
|
| 2219 |
|
|
|
| 2220 |
|
|
--K1_cntr_0 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_0
|
| 2221 |
|
|
--operation mode is arithmetic
|
| 2222 |
|
|
|
| 2223 |
|
|
K1_cntr_0_lut_out = !K1_cntr_0;
|
| 2224 |
|
|
K1_cntr_0 = DFFEAS(K1_cntr_0_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[0], , , !K1_un1_ld_1);
|
| 2225 |
|
|
|
| 2226 |
|
|
--K1_cntr_cout[0] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[0]
|
| 2227 |
|
|
--operation mode is arithmetic
|
| 2228 |
|
|
|
| 2229 |
|
|
K1_cntr_cout[0] = CARRY(K1_cntr_0);
|
| 2230 |
|
|
|
| 2231 |
|
|
|
| 2232 |
|
|
--F1_dout_0_0_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[0]
|
| 2233 |
|
|
--operation mode is normal
|
| 2234 |
|
|
|
| 2235 |
|
|
F1_rr_key2_Z_qfbk = F1_rr_key2_Z;
|
| 2236 |
|
|
F1_dout_0_0_a[0] = M1_buffer_reg_0 & !F1_dout_0_0_a3_5_x[0] & !F1_rr_key2_Z_qfbk # !F1_dout_0_0_a3_6[0] # !M1_buffer_reg_0 & !F1_rr_key2_Z_qfbk # !F1_dout_0_0_a3_6[0];
|
| 2237 |
|
|
|
| 2238 |
|
|
--F1_rr_key2_Z is mips_sys:isys|mips_dvc:imips_dvc|rr_key2_Z
|
| 2239 |
|
|
--operation mode is normal
|
| 2240 |
|
|
|
| 2241 |
|
|
F1_rr_key2_Z = DFFEAS(F1_dout_0_0_a[0], E1__clk0, VCC, , , F1_r_key2, , , VCC);
|
| 2242 |
|
|
|
| 2243 |
|
|
|
| 2244 |
|
|
--F1_dout_0_0_a3_0[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_0[0]
|
| 2245 |
|
|
--operation mode is normal
|
| 2246 |
|
|
|
| 2247 |
|
|
F1_dout_0_0_a3_0[0] = F1_cmd[0] & F1_dout_0_0_a3_3[0];
|
| 2248 |
|
|
|
| 2249 |
|
|
|
| 2250 |
|
|
--GD1_dout_iv_1_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_0
|
| 2251 |
|
|
--operation mode is normal
|
| 2252 |
|
|
|
| 2253 |
|
|
GD1_dout_iv_1_0 = FD1_N_20_i_0_s3 & LD1_q_b[0] # !GD1_dout_iv_1_a[0];
|
| 2254 |
|
|
|
| 2255 |
|
|
|
| 2256 |
|
|
--MD1_c_2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_0
|
| 2257 |
|
|
--operation mode is normal
|
| 2258 |
|
|
|
| 2259 |
|
|
MD1_c_2_0 = MD1_c_1_Z[0] # !RC1_alu_func_o_1 & UD1_shift_out588_0 & MD1_c_2_a[0];
|
| 2260 |
|
|
|
| 2261 |
|
|
|
| 2262 |
|
|
--MD1_c_a_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_0
|
| 2263 |
|
|
--operation mode is normal
|
| 2264 |
|
|
|
| 2265 |
|
|
MD1_c_a_0 = !TD1_un1_a_add0 # !TD1_alu_out_sn_m14_0_0_a4_0;
|
| 2266 |
|
|
|
| 2267 |
|
|
|
| 2268 |
|
|
--UD1_shift_out_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_0
|
| 2269 |
|
|
--operation mode is normal
|
| 2270 |
|
|
|
| 2271 |
|
|
UD1_shift_out_0 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m31_i & UD1_shift_out_91[0] # !UD1_shift_out_sn_m31_i & UD1_shift_out_a[0] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_a[0];
|
| 2272 |
|
|
|
| 2273 |
|
|
|
| 2274 |
|
|
--TD1_alu_out_9_a2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_9_a2_0
|
| 2275 |
|
|
--operation mode is normal
|
| 2276 |
|
|
|
| 2277 |
|
|
TD1_alu_out_9_a2_0 = TD1_alu_out_9_a2_a[0] & RC1_alu_func_o_0 & TD1_sum_add32 # !RC1_alu_func_o_0 & TD1_lt31;
|
| 2278 |
|
|
|
| 2279 |
|
|
|
| 2280 |
|
|
--F1_wr_uartdata_0_a2_1 is mips_sys:isys|mips_dvc:imips_dvc|wr_uartdata_0_a2_1
|
| 2281 |
|
|
--operation mode is normal
|
| 2282 |
|
|
|
| 2283 |
|
|
F1_wr_uartdata_0_a2_1 = !AB1_r32_o_0 & AB1_r32_o_1;
|
| 2284 |
|
|
|
| 2285 |
|
|
|
| 2286 |
|
|
--F1_wr_uartdata_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|wr_uartdata_0_a2_a
|
| 2287 |
|
|
--operation mode is normal
|
| 2288 |
|
|
|
| 2289 |
|
|
F1_wr_uartdata_0_a2_a = JC1_dmem_ctl_o_0 & !JC1_dmem_ctl_o_1 & !JC1_dmem_ctl_o_2 & !AB1_r32_o_2;
|
| 2290 |
|
|
|
| 2291 |
|
|
|
| 2292 |
|
|
--U1L4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_full~105
|
| 2293 |
|
|
--operation mode is normal
|
| 2294 |
|
|
|
| 2295 |
|
|
U1L4 = X1_safe_q[7] & X1_safe_q[6] & X1_safe_q[5] & X1_safe_q[4];
|
| 2296 |
|
|
|
| 2297 |
|
|
|
| 2298 |
|
|
--U1L5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_full~106
|
| 2299 |
|
|
--operation mode is normal
|
| 2300 |
|
|
|
| 2301 |
|
|
U1L5 = X1_safe_q[3] & X1_safe_q[2] & X1_safe_q[0] & X1_safe_q[1];
|
| 2302 |
|
|
|
| 2303 |
|
|
|
| 2304 |
|
|
--U1L3 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_full~103
|
| 2305 |
|
|
--operation mode is normal
|
| 2306 |
|
|
|
| 2307 |
|
|
U1L3 = X1_safe_q[8] & F1_wr_uartdata_0_a2 & U1L4 & U1L5;
|
| 2308 |
|
|
|
| 2309 |
|
|
|
| 2310 |
|
|
--U1L1 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|_~14
|
| 2311 |
|
|
--operation mode is normal
|
| 2312 |
|
|
|
| 2313 |
|
|
U1L1 = N1_ua_state_ns_0_a2_0[1] & U1_b_non_empty $ (!U1_b_full & F1_wr_uartdata_0_a2) # !N1_ua_state_ns_0_a2_0[1] & !U1_b_full & F1_wr_uartdata_0_a2;
|
| 2314 |
|
|
|
| 2315 |
|
|
|
| 2316 |
|
|
--N1_bit_ctr23_i_i is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr23_i_i
|
| 2317 |
|
|
--operation mode is normal
|
| 2318 |
|
|
|
| 2319 |
|
|
N1_bit_ctr23_i_i = sys_rst & N1_ua_state[2] # N1_ua_state[3];
|
| 2320 |
|
|
|
| 2321 |
|
|
|
| 2322 |
|
|
--Y1_q_b[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[2]
|
| 2323 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 2324 |
|
|
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
|
| 2325 |
|
|
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
|
| 2326 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 2327 |
|
|
Y1_q_b[2]_PORT_A_data_in = CB1_r32_o_2;
|
| 2328 |
|
|
Y1_q_b[2]_PORT_A_data_in_reg = DFFE(Y1_q_b[2]_PORT_A_data_in, Y1_q_b[2]_clock_0, , , );
|
| 2329 |
|
|
Y1_q_b[2]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
|
| 2330 |
|
|
Y1_q_b[2]_PORT_A_address_reg = DFFE(Y1_q_b[2]_PORT_A_address, Y1_q_b[2]_clock_0, , , );
|
| 2331 |
|
|
Y1_q_b[2]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
|
| 2332 |
|
|
Y1_q_b[2]_PORT_B_address_reg = DFFE(Y1_q_b[2]_PORT_B_address, Y1_q_b[2]_clock_1, , , Y1_q_b[2]_clock_enable_1);
|
| 2333 |
|
|
Y1_q_b[2]_PORT_A_write_enable = T1_valid_wreq;
|
| 2334 |
|
|
Y1_q_b[2]_PORT_A_write_enable_reg = DFFE(Y1_q_b[2]_PORT_A_write_enable, Y1_q_b[2]_clock_0, , , );
|
| 2335 |
|
|
Y1_q_b[2]_PORT_B_read_enable = VCC;
|
| 2336 |
|
|
Y1_q_b[2]_PORT_B_read_enable_reg = DFFE(Y1_q_b[2]_PORT_B_read_enable, Y1_q_b[2]_clock_1, , , Y1_q_b[2]_clock_enable_1);
|
| 2337 |
|
|
Y1_q_b[2]_clock_0 = E1__clk0;
|
| 2338 |
|
|
Y1_q_b[2]_clock_1 = E1__clk0;
|
| 2339 |
|
|
Y1_q_b[2]_clock_enable_1 = T1_valid_rreq;
|
| 2340 |
|
|
Y1_q_b[2]_PORT_B_data_out = MEMORY(Y1_q_b[2]_PORT_A_data_in_reg, , Y1_q_b[2]_PORT_A_address_reg, Y1_q_b[2]_PORT_B_address_reg, Y1_q_b[2]_PORT_A_write_enable_reg, Y1_q_b[2]_PORT_B_read_enable_reg, , , Y1_q_b[2]_clock_0, Y1_q_b[2]_clock_1, , Y1_q_b[2]_clock_enable_1, , );
|
| 2341 |
|
|
Y1_q_b[2] = Y1_q_b[2]_PORT_B_data_out[0];
|
| 2342 |
|
|
|
| 2343 |
|
|
|
| 2344 |
|
|
--N1_tx_sr[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[3]
|
| 2345 |
|
|
--operation mode is normal
|
| 2346 |
|
|
|
| 2347 |
|
|
N1_tx_sr[3]_lut_out = N1_read_request_ff & Y1_q_b[3] # !N1_read_request_ff & N1_tx_sr[4];
|
| 2348 |
|
|
N1_tx_sr[3] = DFFEAS(N1_tx_sr[3]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );
|
| 2349 |
|
|
|
| 2350 |
|
|
|
| 2351 |
|
|
--N1_clk_ctr26_i_i is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_i
|
| 2352 |
|
|
--operation mode is normal
|
| 2353 |
|
|
|
| 2354 |
|
|
N1_clk_ctr26_i_i = !N1_clk_ctr26_i_0_0 & !N1_clk_ctr26_i_0_a2 # !N1_clk_ctr26_i_0_a4_0_6 # !N1_clk_ctr26_i_0_a4_0_5;
|
| 2355 |
|
|
|
| 2356 |
|
|
|
| 2357 |
|
|
--N1_clk_ctr[14] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[14]
|
| 2358 |
|
|
--operation mode is arithmetic
|
| 2359 |
|
|
|
| 2360 |
|
|
N1_clk_ctr[14]_carry_eqn = N1_clk_ctr_cout_0[13];
|
| 2361 |
|
|
N1_clk_ctr[14]_lut_out = N1_clk_ctr[14] $ (!N1_clk_ctr[14]_carry_eqn);
|
| 2362 |
|
|
N1_clk_ctr[14] = DFFEAS(N1_clk_ctr[14]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2363 |
|
|
|
| 2364 |
|
|
--N1_clk_ctr_cout_0[14] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[14]
|
| 2365 |
|
|
--operation mode is arithmetic
|
| 2366 |
|
|
|
| 2367 |
|
|
N1_clk_ctr_cout_0[14] = CARRY(N1_clk_ctr[14] & !N1_clk_ctr_cout_0[13]);
|
| 2368 |
|
|
|
| 2369 |
|
|
|
| 2370 |
|
|
--N1_clk_ctr[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[7]
|
| 2371 |
|
|
--operation mode is arithmetic
|
| 2372 |
|
|
|
| 2373 |
|
|
N1_clk_ctr[7]_carry_eqn = N1_clk_ctr_cout_0[6];
|
| 2374 |
|
|
N1_clk_ctr[7]_lut_out = N1_clk_ctr[7] $ (N1_clk_ctr[7]_carry_eqn);
|
| 2375 |
|
|
N1_clk_ctr[7] = DFFEAS(N1_clk_ctr[7]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2376 |
|
|
|
| 2377 |
|
|
--N1_clk_ctr_cout_0[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[7]
|
| 2378 |
|
|
--operation mode is arithmetic
|
| 2379 |
|
|
|
| 2380 |
|
|
N1_clk_ctr_cout_0[7] = CARRY(!N1_clk_ctr_cout_0[6] # !N1_clk_ctr[7]);
|
| 2381 |
|
|
|
| 2382 |
|
|
|
| 2383 |
|
|
--N1_clk_ctr[12] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[12]
|
| 2384 |
|
|
--operation mode is arithmetic
|
| 2385 |
|
|
|
| 2386 |
|
|
N1_clk_ctr[12]_carry_eqn = N1_clk_ctr_cout_0[11];
|
| 2387 |
|
|
N1_clk_ctr[12]_lut_out = N1_clk_ctr[12] $ (!N1_clk_ctr[12]_carry_eqn);
|
| 2388 |
|
|
N1_clk_ctr[12] = DFFEAS(N1_clk_ctr[12]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2389 |
|
|
|
| 2390 |
|
|
--N1_clk_ctr_cout_0[12] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[12]
|
| 2391 |
|
|
--operation mode is arithmetic
|
| 2392 |
|
|
|
| 2393 |
|
|
N1_clk_ctr_cout_0[12] = CARRY(N1_clk_ctr[12] & !N1_clk_ctr_cout_0[11]);
|
| 2394 |
|
|
|
| 2395 |
|
|
|
| 2396 |
|
|
--N1_clk_ctr[13] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[13]
|
| 2397 |
|
|
--operation mode is arithmetic
|
| 2398 |
|
|
|
| 2399 |
|
|
N1_clk_ctr[13]_carry_eqn = N1_clk_ctr_cout_0[12];
|
| 2400 |
|
|
N1_clk_ctr[13]_lut_out = N1_clk_ctr[13] $ (N1_clk_ctr[13]_carry_eqn);
|
| 2401 |
|
|
N1_clk_ctr[13] = DFFEAS(N1_clk_ctr[13]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2402 |
|
|
|
| 2403 |
|
|
--N1_clk_ctr_cout_0[13] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[13]
|
| 2404 |
|
|
--operation mode is arithmetic
|
| 2405 |
|
|
|
| 2406 |
|
|
N1_clk_ctr_cout_0[13] = CARRY(!N1_clk_ctr_cout_0[12] # !N1_clk_ctr[13]);
|
| 2407 |
|
|
|
| 2408 |
|
|
|
| 2409 |
|
|
--N1_clk_ctr[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[3]
|
| 2410 |
|
|
--operation mode is arithmetic
|
| 2411 |
|
|
|
| 2412 |
|
|
N1_clk_ctr[3]_carry_eqn = N1_clk_ctr_cout_0[2];
|
| 2413 |
|
|
N1_clk_ctr[3]_lut_out = N1_clk_ctr[3] $ (N1_clk_ctr[3]_carry_eqn);
|
| 2414 |
|
|
N1_clk_ctr[3] = DFFEAS(N1_clk_ctr[3]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2415 |
|
|
|
| 2416 |
|
|
--N1_clk_ctr_cout_0[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[3]
|
| 2417 |
|
|
--operation mode is arithmetic
|
| 2418 |
|
|
|
| 2419 |
|
|
N1_clk_ctr_cout_0[3] = CARRY(!N1_clk_ctr_cout_0[2] # !N1_clk_ctr[3]);
|
| 2420 |
|
|
|
| 2421 |
|
|
|
| 2422 |
|
|
--N1_clk_ctr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[2]
|
| 2423 |
|
|
--operation mode is arithmetic
|
| 2424 |
|
|
|
| 2425 |
|
|
N1_clk_ctr[2]_carry_eqn = N1_clk_ctr_cout_0[1];
|
| 2426 |
|
|
N1_clk_ctr[2]_lut_out = N1_clk_ctr[2] $ (!N1_clk_ctr[2]_carry_eqn);
|
| 2427 |
|
|
N1_clk_ctr[2] = DFFEAS(N1_clk_ctr[2]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2428 |
|
|
|
| 2429 |
|
|
--N1_clk_ctr_cout_0[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[2]
|
| 2430 |
|
|
--operation mode is arithmetic
|
| 2431 |
|
|
|
| 2432 |
|
|
N1_clk_ctr_cout_0[2] = CARRY(N1_clk_ctr[2] & !N1_clk_ctr_cout_0[1]);
|
| 2433 |
|
|
|
| 2434 |
|
|
|
| 2435 |
|
|
--N1_clk_ctr[10] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[10]
|
| 2436 |
|
|
--operation mode is arithmetic
|
| 2437 |
|
|
|
| 2438 |
|
|
N1_clk_ctr[10]_carry_eqn = N1_clk_ctr_cout_0[9];
|
| 2439 |
|
|
N1_clk_ctr[10]_lut_out = N1_clk_ctr[10] $ (!N1_clk_ctr[10]_carry_eqn);
|
| 2440 |
|
|
N1_clk_ctr[10] = DFFEAS(N1_clk_ctr[10]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2441 |
|
|
|
| 2442 |
|
|
--N1_clk_ctr_cout_0[10] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[10]
|
| 2443 |
|
|
--operation mode is arithmetic
|
| 2444 |
|
|
|
| 2445 |
|
|
N1_clk_ctr_cout_0[10] = CARRY(N1_clk_ctr[10] & !N1_clk_ctr_cout_0[9]);
|
| 2446 |
|
|
|
| 2447 |
|
|
|
| 2448 |
|
|
--N1_clk_ctr[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[8]
|
| 2449 |
|
|
--operation mode is arithmetic
|
| 2450 |
|
|
|
| 2451 |
|
|
N1_clk_ctr[8]_carry_eqn = N1_clk_ctr_cout_0[7];
|
| 2452 |
|
|
N1_clk_ctr[8]_lut_out = N1_clk_ctr[8] $ (!N1_clk_ctr[8]_carry_eqn);
|
| 2453 |
|
|
N1_clk_ctr[8] = DFFEAS(N1_clk_ctr[8]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2454 |
|
|
|
| 2455 |
|
|
--N1_clk_ctr_cout_0[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[8]
|
| 2456 |
|
|
--operation mode is arithmetic
|
| 2457 |
|
|
|
| 2458 |
|
|
N1_clk_ctr_cout_0[8] = CARRY(N1_clk_ctr[8] & !N1_clk_ctr_cout_0[7]);
|
| 2459 |
|
|
|
| 2460 |
|
|
|
| 2461 |
|
|
--N1_clk_ctr[11] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[11]
|
| 2462 |
|
|
--operation mode is arithmetic
|
| 2463 |
|
|
|
| 2464 |
|
|
N1_clk_ctr[11]_carry_eqn = N1_clk_ctr_cout_0[10];
|
| 2465 |
|
|
N1_clk_ctr[11]_lut_out = N1_clk_ctr[11] $ (N1_clk_ctr[11]_carry_eqn);
|
| 2466 |
|
|
N1_clk_ctr[11] = DFFEAS(N1_clk_ctr[11]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2467 |
|
|
|
| 2468 |
|
|
--N1_clk_ctr_cout_0[11] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[11]
|
| 2469 |
|
|
--operation mode is arithmetic
|
| 2470 |
|
|
|
| 2471 |
|
|
N1_clk_ctr_cout_0[11] = CARRY(!N1_clk_ctr_cout_0[10] # !N1_clk_ctr[11]);
|
| 2472 |
|
|
|
| 2473 |
|
|
|
| 2474 |
|
|
--N1_clk_ctr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[1]
|
| 2475 |
|
|
--operation mode is arithmetic
|
| 2476 |
|
|
|
| 2477 |
|
|
N1_clk_ctr[1]_carry_eqn = N1_clk_ctr_cout_0[0];
|
| 2478 |
|
|
N1_clk_ctr[1]_lut_out = N1_clk_ctr[1] $ (N1_clk_ctr[1]_carry_eqn);
|
| 2479 |
|
|
N1_clk_ctr[1] = DFFEAS(N1_clk_ctr[1]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2480 |
|
|
|
| 2481 |
|
|
--N1_clk_ctr_cout_0[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[1]
|
| 2482 |
|
|
--operation mode is arithmetic
|
| 2483 |
|
|
|
| 2484 |
|
|
N1_clk_ctr_cout_0[1] = CARRY(!N1_clk_ctr_cout_0[0] # !N1_clk_ctr[1]);
|
| 2485 |
|
|
|
| 2486 |
|
|
|
| 2487 |
|
|
--N1_clk_ctr[9] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[9]
|
| 2488 |
|
|
--operation mode is arithmetic
|
| 2489 |
|
|
|
| 2490 |
|
|
N1_clk_ctr[9]_carry_eqn = N1_clk_ctr_cout_0[8];
|
| 2491 |
|
|
N1_clk_ctr[9]_lut_out = N1_clk_ctr[9] $ (N1_clk_ctr[9]_carry_eqn);
|
| 2492 |
|
|
N1_clk_ctr[9] = DFFEAS(N1_clk_ctr[9]_lut_out, E1__clk0, VCC, , , , , !N1_clk_ctr26_i_i, );
|
| 2493 |
|
|
|
| 2494 |
|
|
--N1_clk_ctr_cout_0[9] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[9]
|
| 2495 |
|
|
--operation mode is arithmetic
|
| 2496 |
|
|
|
| 2497 |
|
|
N1_clk_ctr_cout_0[9] = CARRY(!N1_clk_ctr_cout_0[8] # !N1_clk_ctr[9]);
|
| 2498 |
|
|
|
| 2499 |
|
|
|
| 2500 |
|
|
--N1_ua_state[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[5]
|
| 2501 |
|
|
--operation mode is normal
|
| 2502 |
|
|
|
| 2503 |
|
|
N1_ua_state[5]_lut_out = N1_ua_state[4];
|
| 2504 |
|
|
N1_ua_state[5] = DFFEAS(N1_ua_state[5]_lut_out, E1__clk0, VCC, , C1_G_451_x, , , !sys_rst, );
|
| 2505 |
|
|
|
| 2506 |
|
|
|
| 2507 |
|
|
--C1_G_451_x is mips_sys:isys|G_451_x
|
| 2508 |
|
|
--operation mode is normal
|
| 2509 |
|
|
|
| 2510 |
|
|
C1_G_451_x = N1_clk_ctr_equ15_0_a2 # !sys_rst;
|
| 2511 |
|
|
|
| 2512 |
|
|
|
| 2513 |
|
|
--K1_cntr_5_0[7] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[7]
|
| 2514 |
|
|
--operation mode is normal
|
| 2515 |
|
|
|
| 2516 |
|
|
K1_s_cntr_7__Z_qfbk = K1_s_cntr_7__Z;
|
| 2517 |
|
|
K1_cntr_5_0[7] = F1_wr_tmr_data_0_a2 & CB1_r32_o_7 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_7__Z_qfbk;
|
| 2518 |
|
|
|
| 2519 |
|
|
--K1_s_cntr_7__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_7__Z
|
| 2520 |
|
|
--operation mode is normal
|
| 2521 |
|
|
|
| 2522 |
|
|
K1_s_cntr_7__Z = DFFEAS(K1_cntr_5_0[7], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_7, , , VCC);
|
| 2523 |
|
|
|
| 2524 |
|
|
|
| 2525 |
|
|
--K1_un1_ld_1 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un1_ld_1
|
| 2526 |
|
|
--operation mode is normal
|
| 2527 |
|
|
|
| 2528 |
|
|
K1_un1_ld_1 = !F1_wr_tmr_data_0_a2 & K1_un1_ld_1_a # !K1_un2_w_irq_28 # !K1_un2_w_irq_21;
|
| 2529 |
|
|
|
| 2530 |
|
|
|
| 2531 |
|
|
--K1_cntrlde is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntrlde
|
| 2532 |
|
|
--operation mode is normal
|
| 2533 |
|
|
|
| 2534 |
|
|
K1_cntrlde = F1_cmd[8] # !K1_un1_ld_1;
|
| 2535 |
|
|
|
| 2536 |
|
|
|
| 2537 |
|
|
--F1_rd_cmd_0_a2_2 is mips_sys:isys|mips_dvc:imips_dvc|rd_cmd_0_a2_2
|
| 2538 |
|
|
--operation mode is normal
|
| 2539 |
|
|
|
| 2540 |
|
|
F1_rd_cmd_0_a2_2 = JC1_dmem_ctl_o_1 & !JC1_dmem_ctl_o_0 & F1_wr_tmr_data_0_a2_0;
|
| 2541 |
|
|
|
| 2542 |
|
|
|
| 2543 |
|
|
--F1_cmd[7] is mips_sys:isys|mips_dvc:imips_dvc|cmd[7]
|
| 2544 |
|
|
--operation mode is normal
|
| 2545 |
|
|
|
| 2546 |
|
|
F1_cmd[7]_lut_out = CB1_r32_o_7;
|
| 2547 |
|
|
F1_cmd[7] = DFFEAS(F1_cmd[7]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 2548 |
|
|
|
| 2549 |
|
|
|
| 2550 |
|
|
--M1_buffer_reg_7 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_7
|
| 2551 |
|
|
--operation mode is normal
|
| 2552 |
|
|
|
| 2553 |
|
|
M1_buffer_reg_7_lut_out = M1_rx_sr[7];
|
| 2554 |
|
|
M1_buffer_reg_7 = DFFEAS(M1_buffer_reg_7_lut_out, E1__clk0, VCC, , C1_G_578, , , !sys_rst, );
|
| 2555 |
|
|
|
| 2556 |
|
|
|
| 2557 |
|
|
--F1_dout_0_0_a3_5_x[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_5_x[0]
|
| 2558 |
|
|
--operation mode is normal
|
| 2559 |
|
|
|
| 2560 |
|
|
F1_dout_0_0_a3_5_x[0] = sys_rst & F1_dout_0_0_a3_5_3[0] & F1_rd_uartdata_0_a2_0;
|
| 2561 |
|
|
|
| 2562 |
|
|
|
| 2563 |
|
|
--F1_dout_0_0_a3_3[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_3[0]
|
| 2564 |
|
|
--operation mode is normal
|
| 2565 |
|
|
|
| 2566 |
|
|
F1_dout_0_0_a3_3[0] = sys_rst & !AB1_r32_o_3 & F1_rd_cmd_0_a2_2 & F1_rd_uartdata_0_a2_0;
|
| 2567 |
|
|
|
| 2568 |
|
|
|
| 2569 |
|
|
--UB1_dout_2_i_i[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[7]
|
| 2570 |
|
|
--operation mode is normal
|
| 2571 |
|
|
|
| 2572 |
|
|
UB1_dout_2_i_i[7] = UB1_dout_2_i_i_0[7] # GE1_q_b[7] & UB1_dout_2_i_i_a3_1[7] # !UB1_dout_2_i_i_a[7];
|
| 2573 |
|
|
|
| 2574 |
|
|
|
| 2575 |
|
|
--UB1_un1_byte_addr_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_byte_addr_2
|
| 2576 |
|
|
--operation mode is normal
|
| 2577 |
|
|
|
| 2578 |
|
|
UB1_un1_byte_addr_2 = !RB1_byte_addr_o_0 # !RB1_ctl_o_3;
|
| 2579 |
|
|
|
| 2580 |
|
|
|
| 2581 |
|
|
--UB1_un1_dout98_i_0_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_dout98_i_0_0
|
| 2582 |
|
|
--operation mode is normal
|
| 2583 |
|
|
|
| 2584 |
|
|
UB1_un1_dout98_i_0_0 = RB1_ctl_o_0 # RB1_ctl_o_3 & RB1_ctl_o_2 # !RB1_ctl_o_3 & !RB1_ctl_o_1 & !RB1_ctl_o_2;
|
| 2585 |
|
|
|
| 2586 |
|
|
|
| 2587 |
|
|
--WB21L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_7__Z|lpm_latch:U1|q[0]~56
|
| 2588 |
|
|
--operation mode is normal
|
| 2589 |
|
|
|
| 2590 |
|
|
WB21L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[7] # !UB1_un1_byte_addr_2 & WB21L1;
|
| 2591 |
|
|
|
| 2592 |
|
|
|
| 2593 |
|
|
--NC1_wb_mux_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr:U13|wb_mux_ctl_o_0
|
| 2594 |
|
|
--operation mode is normal
|
| 2595 |
|
|
|
| 2596 |
|
|
NC1_wb_mux_ctl_o_0_lut_out = KC1_wb_mux_ctl_o_0;
|
| 2597 |
|
|
NC1_wb_mux_ctl_o_0 = DFFEAS(NC1_wb_mux_ctl_o_0_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 2598 |
|
|
|
| 2599 |
|
|
|
| 2600 |
|
|
--FD1_N_20_i_0_s3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_20_i_0_s3
|
| 2601 |
|
|
--operation mode is normal
|
| 2602 |
|
|
|
| 2603 |
|
|
FD1_N_20_i_0_s3 = !FD1_un23_qb_i_0_a2 & ZD1_un32_mux_fw & FD1_un14_qb_NE # !FD1_r_wren;
|
| 2604 |
|
|
|
| 2605 |
|
|
|
| 2606 |
|
|
--GD1_dout_iv_1_a[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[7]
|
| 2607 |
|
|
--operation mode is normal
|
| 2608 |
|
|
|
| 2609 |
|
|
GD1_dout_iv_1_a[7] = FD1_r_data_7 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_5 # !FD1_r_data_7 & !ZD1_mux_fw_1 # !AB1_r32_o_5;
|
| 2610 |
|
|
|
| 2611 |
|
|
|
| 2612 |
|
|
--LD1_q_b[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[7]
|
| 2613 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 2614 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 2615 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 2616 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 2617 |
|
|
LD1_q_b[7]_PORT_A_data_in = FD1_wb_o_7;
|
| 2618 |
|
|
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
|
| 2619 |
|
|
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 2620 |
|
|
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
|
| 2621 |
|
|
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 2622 |
|
|
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
|
| 2623 |
|
|
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 2624 |
|
|
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
|
| 2625 |
|
|
LD1_q_b[7]_PORT_B_read_enable = VCC;
|
| 2626 |
|
|
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
|
| 2627 |
|
|
LD1_q_b[7]_clock_0 = E1__clk0;
|
| 2628 |
|
|
LD1_q_b[7]_clock_1 = E1__clk0;
|
| 2629 |
|
|
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
|
| 2630 |
|
|
LD1_q_b[7] = LD1_q_b[7]_PORT_B_data_out[0];
|
| 2631 |
|
|
|
| 2632 |
|
|
|
| 2633 |
|
|
--ZD1_un17_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un17_mux_fw_NE
|
| 2634 |
|
|
--operation mode is normal
|
| 2635 |
|
|
|
| 2636 |
|
|
ZD1_un17_mux_fw_NE = ZD1_un17_mux_fw_NE_1 # ZD1_un17_mux_fw_NE_a # ED1_r32_o_20 $ NB1_r5_o_4;
|
| 2637 |
|
|
|
| 2638 |
|
|
|
| 2639 |
|
|
--ZD1_mux_fw_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|mux_fw_1
|
| 2640 |
|
|
--operation mode is normal
|
| 2641 |
|
|
|
| 2642 |
|
|
ZD1_mux_fw_1 = !ZD1_mux_fw_1_a & !ZD1_un1_mux_fw_NE_2 & !ZD1_un1_mux_fw_NE_1 & !WD1_un14_mux_fw;
|
| 2643 |
|
|
|
| 2644 |
|
|
|
| 2645 |
|
|
--UD1_shift_out586 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out586
|
| 2646 |
|
|
--operation mode is normal
|
| 2647 |
|
|
|
| 2648 |
|
|
UD1_shift_out586 = RC1_alu_func_o_1 & TD1_alu_out_9_a2_0_1_0 & !RC1_alu_func_o_4 & !RC1_alu_func_o_0;
|
| 2649 |
|
|
|
| 2650 |
|
|
|
| 2651 |
|
|
--UD1_shift_out_87[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[7]
|
| 2652 |
|
|
--operation mode is normal
|
| 2653 |
|
|
|
| 2654 |
|
|
UD1_shift_out_87[7] = PD1_a_o_2 & UD1_shift_out_87_d[7] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[7] # !PD1_a_o_0 & VD1_b_o_iv_9;
|
| 2655 |
|
|
|
| 2656 |
|
|
|
| 2657 |
|
|
--UD1_shift_out_89_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[7]
|
| 2658 |
|
|
--operation mode is normal
|
| 2659 |
|
|
|
| 2660 |
|
|
UD1_shift_out_89_a[7] = PD1_a_o_2 & !UD1_shift_out_85_d[7] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[7] # !PD1_a_o_1 & !VD1_b_o_iv_6;
|
| 2661 |
|
|
|
| 2662 |
|
|
|
| 2663 |
|
|
--UD1_shift_out_sn_m31_i_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m31_i_a
|
| 2664 |
|
|
--operation mode is normal
|
| 2665 |
|
|
|
| 2666 |
|
|
UD1_shift_out_sn_m31_i_a = !UD1_shift_out_sn_m25_0_a5_1 & !PD1_a_o_4 & !PD1_a_o_3;
|
| 2667 |
|
|
|
| 2668 |
|
|
|
| 2669 |
|
|
--PD1_a_o_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_2
|
| 2670 |
|
|
--operation mode is normal
|
| 2671 |
|
|
|
| 2672 |
|
|
PD1_a_o_2 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[2] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[2];
|
| 2673 |
|
|
|
| 2674 |
|
|
|
| 2675 |
|
|
--PD1_a_o_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_1
|
| 2676 |
|
|
--operation mode is normal
|
| 2677 |
|
|
|
| 2678 |
|
|
PD1_a_o_1 = SC1_muxa_ctl_o_0 & !RD1_a_o_a_1 # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[1];
|
| 2679 |
|
|
|
| 2680 |
|
|
|
| 2681 |
|
|
--PD1_a_o_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_0
|
| 2682 |
|
|
--operation mode is normal
|
| 2683 |
|
|
|
| 2684 |
|
|
PD1_a_o_0 = SC1_muxa_ctl_o_0 & !RD1_a_o_a_0 # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[0];
|
| 2685 |
|
|
|
| 2686 |
|
|
|
| 2687 |
|
|
--UD1_shift_out_86_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_7
|
| 2688 |
|
|
--operation mode is normal
|
| 2689 |
|
|
|
| 2690 |
|
|
UD1_shift_out_86_7 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[7] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[7];
|
| 2691 |
|
|
|
| 2692 |
|
|
|
| 2693 |
|
|
--UD1_shift_out_sn_m25_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0
|
| 2694 |
|
|
--operation mode is normal
|
| 2695 |
|
|
|
| 2696 |
|
|
UD1_shift_out_sn_m25_0 = UD1_shift_out_sn_m25_0_a5_0 # !UD1_shift_out586 & UD1_shift_out_sn_m17_0_a2 # !UD1_shift_out_sn_m25_0_a;
|
| 2697 |
|
|
|
| 2698 |
|
|
|
| 2699 |
|
|
--UD1_shift_out_91_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_7
|
| 2700 |
|
|
--operation mode is normal
|
| 2701 |
|
|
|
| 2702 |
|
|
UD1_shift_out_91_7 = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[7] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[7];
|
| 2703 |
|
|
|
| 2704 |
|
|
|
| 2705 |
|
|
--MD1_c_0_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[7]
|
| 2706 |
|
|
--operation mode is normal
|
| 2707 |
|
|
|
| 2708 |
|
|
MD1_c_0_a[7] = VD1_un24_res & !VD1_hilo_39 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_7;
|
| 2709 |
|
|
|
| 2710 |
|
|
|
| 2711 |
|
|
--TD1_m11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m11
|
| 2712 |
|
|
--operation mode is normal
|
| 2713 |
|
|
|
| 2714 |
|
|
TD1_m11 = PD1_a_o_7 & TD1_m11_a # !PD1_a_o_7 & TD1_m11_a & !TD1_m4 # !TD1_m11_a & TD1_m7;
|
| 2715 |
|
|
|
| 2716 |
|
|
|
| 2717 |
|
|
--TD1_m1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m1
|
| 2718 |
|
|
--operation mode is normal
|
| 2719 |
|
|
|
| 2720 |
|
|
TD1_m1 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add7;
|
| 2721 |
|
|
|
| 2722 |
|
|
|
| 2723 |
|
|
--MB1_r5_o_4 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_4
|
| 2724 |
|
|
--operation mode is normal
|
| 2725 |
|
|
|
| 2726 |
|
|
MB1_r5_o_4_lut_out = LB1_r5_o_4;
|
| 2727 |
|
|
MB1_r5_o_4 = DFFEAS(MB1_r5_o_4_lut_out, E1__clk0, VCC, , , , , , );
|
| 2728 |
|
|
|
| 2729 |
|
|
|
| 2730 |
|
|
--MB1_r5_o_3 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_3
|
| 2731 |
|
|
--operation mode is normal
|
| 2732 |
|
|
|
| 2733 |
|
|
MB1_r5_o_3_lut_out = LB1_r5_o_3;
|
| 2734 |
|
|
MB1_r5_o_3 = DFFEAS(MB1_r5_o_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 2735 |
|
|
|
| 2736 |
|
|
|
| 2737 |
|
|
--BE1_q_3 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_3
|
| 2738 |
|
|
--operation mode is normal
|
| 2739 |
|
|
|
| 2740 |
|
|
BE1_q_3_lut_out = ED1_r32_o_19;
|
| 2741 |
|
|
BE1_q_3 = DFFEAS(BE1_q_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 2742 |
|
|
|
| 2743 |
|
|
|
| 2744 |
|
|
--MB1_r5_o_2 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_2
|
| 2745 |
|
|
--operation mode is normal
|
| 2746 |
|
|
|
| 2747 |
|
|
MB1_r5_o_2_lut_out = LB1_r5_o_2;
|
| 2748 |
|
|
MB1_r5_o_2 = DFFEAS(MB1_r5_o_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 2749 |
|
|
|
| 2750 |
|
|
|
| 2751 |
|
|
--BE1_q_2 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_2
|
| 2752 |
|
|
--operation mode is normal
|
| 2753 |
|
|
|
| 2754 |
|
|
BE1_q_2_lut_out = ED1_r32_o_18;
|
| 2755 |
|
|
BE1_q_2 = DFFEAS(BE1_q_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 2756 |
|
|
|
| 2757 |
|
|
|
| 2758 |
|
|
--MB1_r5_o_1 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_1
|
| 2759 |
|
|
--operation mode is normal
|
| 2760 |
|
|
|
| 2761 |
|
|
MB1_r5_o_1_lut_out = LB1_r5_o_1;
|
| 2762 |
|
|
MB1_r5_o_1 = DFFEAS(MB1_r5_o_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 2763 |
|
|
|
| 2764 |
|
|
|
| 2765 |
|
|
--BE1_q_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_1
|
| 2766 |
|
|
--operation mode is normal
|
| 2767 |
|
|
|
| 2768 |
|
|
BE1_q_1_lut_out = ED1_r32_o_17;
|
| 2769 |
|
|
BE1_q_1 = DFFEAS(BE1_q_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 2770 |
|
|
|
| 2771 |
|
|
|
| 2772 |
|
|
--MB1_r5_o_0 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_0
|
| 2773 |
|
|
--operation mode is normal
|
| 2774 |
|
|
|
| 2775 |
|
|
MB1_r5_o_0_lut_out = LB1_r5_o_0;
|
| 2776 |
|
|
MB1_r5_o_0 = DFFEAS(MB1_r5_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 2777 |
|
|
|
| 2778 |
|
|
|
| 2779 |
|
|
--BE1_q_0 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_0
|
| 2780 |
|
|
--operation mode is normal
|
| 2781 |
|
|
|
| 2782 |
|
|
BE1_q_0_lut_out = ED1_r32_o_16;
|
| 2783 |
|
|
BE1_q_0 = DFFEAS(BE1_q_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 2784 |
|
|
|
| 2785 |
|
|
|
| 2786 |
|
|
--WD1_un14_mux_fw_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un14_mux_fw_a
|
| 2787 |
|
|
--operation mode is normal
|
| 2788 |
|
|
|
| 2789 |
|
|
WD1_un14_mux_fw_a = !MB1_r5_o_1 & !MB1_r5_o_4;
|
| 2790 |
|
|
|
| 2791 |
|
|
|
| 2792 |
|
|
--UC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr:U19|wb_we_o_0
|
| 2793 |
|
|
--operation mode is normal
|
| 2794 |
|
|
|
| 2795 |
|
|
UC1_wb_we_o_0_lut_out = LC1_wb_we_o_0;
|
| 2796 |
|
|
UC1_wb_we_o_0 = DFFEAS(UC1_wb_we_o_0_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 2797 |
|
|
|
| 2798 |
|
|
|
| 2799 |
|
|
--YC1_alu_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr:U24|alu_we_o_0
|
| 2800 |
|
|
--operation mode is normal
|
| 2801 |
|
|
|
| 2802 |
|
|
YC1_alu_we_o_0_lut_out = FC1_alu_we_o_0;
|
| 2803 |
|
|
YC1_alu_we_o_0 = DFFEAS(YC1_alu_we_o_0_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 2804 |
|
|
|
| 2805 |
|
|
|
| 2806 |
|
|
--NB1_r5_o_2 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_2
|
| 2807 |
|
|
--operation mode is normal
|
| 2808 |
|
|
|
| 2809 |
|
|
NB1_r5_o_2_lut_out = MB1_r5_o_2;
|
| 2810 |
|
|
NB1_r5_o_2 = DFFEAS(NB1_r5_o_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 2811 |
|
|
|
| 2812 |
|
|
|
| 2813 |
|
|
--ED1_r32_o_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_20
|
| 2814 |
|
|
--operation mode is normal
|
| 2815 |
|
|
|
| 2816 |
|
|
ED1_r32_o_20_lut_out = JE1_q_a[4];
|
| 2817 |
|
|
ED1_r32_o_20 = DFFEAS(ED1_r32_o_20_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 2818 |
|
|
|
| 2819 |
|
|
|
| 2820 |
|
|
--ZC1_alu_func_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_1
|
| 2821 |
|
|
--operation mode is normal
|
| 2822 |
|
|
|
| 2823 |
|
|
ZC1_alu_func_o_1_lut_out = WB83L1;
|
| 2824 |
|
|
ZC1_alu_func_o_1 = DFFEAS(ZC1_alu_func_o_1_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 2825 |
|
|
|
| 2826 |
|
|
|
| 2827 |
|
|
--AD1_NET1640_i is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|NET1640_i
|
| 2828 |
|
|
--operation mode is normal
|
| 2829 |
|
|
|
| 2830 |
|
|
AD1_NET1640_i = !AD1_CurrState_Sreg0_5 & !AD1_CurrState_Sreg0_2;
|
| 2831 |
|
|
|
| 2832 |
|
|
|
| 2833 |
|
|
--RC1_alu_func_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_2
|
| 2834 |
|
|
--operation mode is normal
|
| 2835 |
|
|
|
| 2836 |
|
|
RC1_alu_func_o_2_lut_out = ZC1_alu_func_o_2;
|
| 2837 |
|
|
RC1_alu_func_o_2 = DFFEAS(RC1_alu_func_o_2_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 2838 |
|
|
|
| 2839 |
|
|
|
| 2840 |
|
|
--RC1_alu_func_o_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_3
|
| 2841 |
|
|
--operation mode is normal
|
| 2842 |
|
|
|
| 2843 |
|
|
RC1_alu_func_o_3_lut_out = ZC1_alu_func_o_3;
|
| 2844 |
|
|
RC1_alu_func_o_3 = DFFEAS(RC1_alu_func_o_3_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 2845 |
|
|
|
| 2846 |
|
|
|
| 2847 |
|
|
--ZC1_alu_func_o_4 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_4
|
| 2848 |
|
|
--operation mode is normal
|
| 2849 |
|
|
|
| 2850 |
|
|
ZC1_alu_func_o_4_lut_out = WB14L1;
|
| 2851 |
|
|
ZC1_alu_func_o_4 = DFFEAS(ZC1_alu_func_o_4_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 2852 |
|
|
|
| 2853 |
|
|
|
| 2854 |
|
|
--ZC1_alu_func_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_0
|
| 2855 |
|
|
--operation mode is normal
|
| 2856 |
|
|
|
| 2857 |
|
|
ZC1_alu_func_o_0_lut_out = WB73L1;
|
| 2858 |
|
|
ZC1_alu_func_o_0 = DFFEAS(ZC1_alu_func_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 2859 |
|
|
|
| 2860 |
|
|
|
| 2861 |
|
|
--UD1_shift_out588_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out588_0
|
| 2862 |
|
|
--operation mode is normal
|
| 2863 |
|
|
|
| 2864 |
|
|
UD1_shift_out588_0 = RC1_alu_func_o_2 & !RC1_alu_func_o_3;
|
| 2865 |
|
|
|
| 2866 |
|
|
|
| 2867 |
|
|
--TD1_alu_out_sn_m14_0_0_a4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0_a4
|
| 2868 |
|
|
--operation mode is normal
|
| 2869 |
|
|
|
| 2870 |
|
|
TD1_alu_out_sn_m14_0_0_a4 = !RC1_alu_func_o_3 & TD1_m107;
|
| 2871 |
|
|
|
| 2872 |
|
|
|
| 2873 |
|
|
--MD1_c_0_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[4]
|
| 2874 |
|
|
--operation mode is normal
|
| 2875 |
|
|
|
| 2876 |
|
|
MD1_c_0_a[4] = VD1_un24_res & !VD1_hilo_36 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_4;
|
| 2877 |
|
|
|
| 2878 |
|
|
|
| 2879 |
|
|
--TD1_alu_out_0_a3_0_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a3_0_0
|
| 2880 |
|
|
--operation mode is normal
|
| 2881 |
|
|
|
| 2882 |
|
|
TD1_alu_out_0_a3_0_0 = !TD1_alu_out_7_0_0_o3_0 & RC1_alu_func_o_4 & RC1_alu_func_o_0 & TD1_alu_out_sn_m14_0_0;
|
| 2883 |
|
|
|
| 2884 |
|
|
|
| 2885 |
|
|
--VD1_b_o_iv_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_4
|
| 2886 |
|
|
--operation mode is normal
|
| 2887 |
|
|
|
| 2888 |
|
|
VD1_b_o_iv_4 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[4] & !G1_BUS15471_i_m[4] & AB1_r32_o_2 # !QD1_b_o_0_sqmuxa;
|
| 2889 |
|
|
|
| 2890 |
|
|
--VD1_op2_reged[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[4]
|
| 2891 |
|
|
--operation mode is normal
|
| 2892 |
|
|
|
| 2893 |
|
|
VD1_op2_reged[4] = DFFEAS(VD1_b_o_iv_4, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 2894 |
|
|
|
| 2895 |
|
|
|
| 2896 |
|
|
--TD1_alu_out_7_0_0_m4_0[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[4]
|
| 2897 |
|
|
--operation mode is normal
|
| 2898 |
|
|
|
| 2899 |
|
|
TD1_alu_out_7_0_0_m4_0[4] = VD1_b_o_iv_4 & TD1_alu_out_7_0_0_o3_0 & TD1_alu_out_0_a3[28] # !VD1_b_o_iv_4 & TD1_alu_out_7_0_0_m4_0_a[3];
|
| 2900 |
|
|
|
| 2901 |
|
|
|
| 2902 |
|
|
--TD1_alu_out_7_0_0_m2_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_a[4]
|
| 2903 |
|
|
--operation mode is normal
|
| 2904 |
|
|
|
| 2905 |
|
|
TD1_alu_out_7_0_0_m2_a[4] = VD1_b_o_iv_4 & !TD1_m107 # !VD1_b_o_iv_4 & !TD1_alu_out_0_a3[28];
|
| 2906 |
|
|
|
| 2907 |
|
|
|
| 2908 |
|
|
--SC1_muxa_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17|muxa_ctl_o_0
|
| 2909 |
|
|
--operation mode is normal
|
| 2910 |
|
|
|
| 2911 |
|
|
SC1_muxa_ctl_o_0_lut_out = GC1_muxa_ctl_o_0;
|
| 2912 |
|
|
SC1_muxa_ctl_o_0 = DFFEAS(SC1_muxa_ctl_o_0_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 2913 |
|
|
|
| 2914 |
|
|
|
| 2915 |
|
|
--PD1_a_o_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[4]
|
| 2916 |
|
|
--operation mode is normal
|
| 2917 |
|
|
|
| 2918 |
|
|
PD1_a_o_a[4] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_4 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_4;
|
| 2919 |
|
|
|
| 2920 |
|
|
|
| 2921 |
|
|
--PD1_a_o_3_Z[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[4]
|
| 2922 |
|
|
--operation mode is normal
|
| 2923 |
|
|
|
| 2924 |
|
|
PD1_a_o_3_Z[4] = PD1_a_o_3_s[0] & SD1_r32_o_4 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[4];
|
| 2925 |
|
|
|
| 2926 |
|
|
|
| 2927 |
|
|
--TD1_sum13_0_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum13_0_a2
|
| 2928 |
|
|
--operation mode is normal
|
| 2929 |
|
|
|
| 2930 |
|
|
TD1_sum13_0_a2 = !RC1_alu_func_o_1 & TD1_alu_out_sn_m14_0_0_a4_0;
|
| 2931 |
|
|
|
| 2932 |
|
|
|
| 2933 |
|
|
--PD1_a_o_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3
|
| 2934 |
|
|
--operation mode is normal
|
| 2935 |
|
|
|
| 2936 |
|
|
PD1_a_o_3 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[3] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[3];
|
| 2937 |
|
|
|
| 2938 |
|
|
|
| 2939 |
|
|
--TD1_un1_b_1_combout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[3]
|
| 2940 |
|
|
--operation mode is normal
|
| 2941 |
|
|
|
| 2942 |
|
|
TD1_un1_b_1_combout[3] = TD1_sum13_0_a2 $ !VD1_b_o_iv_3;
|
| 2943 |
|
|
|
| 2944 |
|
|
|
| 2945 |
|
|
--TD1_un1_a_add2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add2
|
| 2946 |
|
|
--operation mode is arithmetic
|
| 2947 |
|
|
|
| 2948 |
|
|
TD1_un1_a_add2_carry_eqn = TD1_un1_a_carry_1;
|
| 2949 |
|
|
TD1_un1_a_add2 = PD1_a_o_2 $ TD1_un1_b_1_combout[2] $ !TD1_un1_a_add2_carry_eqn;
|
| 2950 |
|
|
|
| 2951 |
|
|
--TD1_un1_a_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_2
|
| 2952 |
|
|
--operation mode is arithmetic
|
| 2953 |
|
|
|
| 2954 |
|
|
TD1_un1_a_carry_2 = CARRY(PD1_a_o_2 & TD1_un1_b_1_combout[2] # !TD1_un1_a_carry_1 # !PD1_a_o_2 & TD1_un1_b_1_combout[2] & !TD1_un1_a_carry_1);
|
| 2955 |
|
|
|
| 2956 |
|
|
|
| 2957 |
|
|
--UD1_shift_out_85[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[4]
|
| 2958 |
|
|
--operation mode is normal
|
| 2959 |
|
|
|
| 2960 |
|
|
UD1_shift_out_85[4] = PD1_a_o_2 & UD1_shift_out_85_d[4] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[4] # !PD1_a_o_1 & VD1_b_o_iv_3;
|
| 2961 |
|
|
|
| 2962 |
|
|
|
| 2963 |
|
|
--UD1_shift_out_87[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[4]
|
| 2964 |
|
|
--operation mode is normal
|
| 2965 |
|
|
|
| 2966 |
|
|
UD1_shift_out_87[4] = PD1_a_o_2 & UD1_shift_out_87_d[4] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[4] # !PD1_a_o_0 & VD1_b_o_iv_6;
|
| 2967 |
|
|
|
| 2968 |
|
|
|
| 2969 |
|
|
--UD1_shift_out_91[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[4]
|
| 2970 |
|
|
--operation mode is normal
|
| 2971 |
|
|
|
| 2972 |
|
|
UD1_shift_out_91[4] = UD1_shift_out_sn_m17_0 & UD1_shift_out_88[4] # !UD1_shift_out_sn_m17_0 & UD1_shift_out587 & UD1_shift_out_91_a[4];
|
| 2973 |
|
|
|
| 2974 |
|
|
|
| 2975 |
|
|
--UD1_shift_out_86[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[4]
|
| 2976 |
|
|
--operation mode is normal
|
| 2977 |
|
|
|
| 2978 |
|
|
UD1_shift_out_86[4] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[4] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[4];
|
| 2979 |
|
|
|
| 2980 |
|
|
|
| 2981 |
|
|
--VD1_hilo_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_5
|
| 2982 |
|
|
--operation mode is normal
|
| 2983 |
|
|
|
| 2984 |
|
|
VD1_hilo_5_lut_out = VD1_hilo_37_iv_0_0[5] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_5 # !VD1_hilo_37_iv_0_a[5];
|
| 2985 |
|
|
VD1_hilo_5 = DFFEAS(VD1_hilo_5_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 2986 |
|
|
|
| 2987 |
|
|
|
| 2988 |
|
|
--VD1_hilo_37 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37
|
| 2989 |
|
|
--operation mode is normal
|
| 2990 |
|
|
|
| 2991 |
|
|
VD1_hilo_37_lut_out = !VD1_hilo_37_iv_0_a2_7[37] & !VD1_hilo_37_iv_0_5[37] & !VD1_hilo_37_iv_0_a[37] & !VD1_hilo_37_iv_0_a3[57];
|
| 2992 |
|
|
VD1_hilo_37 = DFFEAS(VD1_hilo_37_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 2993 |
|
|
|
| 2994 |
|
|
|
| 2995 |
|
|
--VD1_un24_res is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un24_res
|
| 2996 |
|
|
--operation mode is normal
|
| 2997 |
|
|
|
| 2998 |
|
|
VD1_un24_res = !RC1_alu_func_o_3 & !TD1_alu_out_7_0_0_o3_0 & !RC1_alu_func_o_4 & !RC1_alu_func_o_0;
|
| 2999 |
|
|
|
| 3000 |
|
|
|
| 3001 |
|
|
--VD1_un11_res is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un11_res
|
| 3002 |
|
|
--operation mode is normal
|
| 3003 |
|
|
|
| 3004 |
|
|
VD1_un11_res = RC1_alu_func_o_1 & UD1_shift_out588_0 & !RC1_alu_func_o_4 & RC1_alu_func_o_0;
|
| 3005 |
|
|
|
| 3006 |
|
|
|
| 3007 |
|
|
--TD1_alu_out_7_0_0_o3_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_o3_0
|
| 3008 |
|
|
--operation mode is normal
|
| 3009 |
|
|
|
| 3010 |
|
|
TD1_alu_out_7_0_0_o3_0 = !RC1_alu_func_o_1 # !RC1_alu_func_o_2;
|
| 3011 |
|
|
|
| 3012 |
|
|
|
| 3013 |
|
|
--VD1_b_o_iv_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_5
|
| 3014 |
|
|
--operation mode is normal
|
| 3015 |
|
|
|
| 3016 |
|
|
VD1_b_o_iv_5 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[5] & !G1_BUS15471_i_m[5] & AB1_r32_o_3 # !QD1_b_o_0_sqmuxa;
|
| 3017 |
|
|
|
| 3018 |
|
|
--VD1_op2_reged[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[5]
|
| 3019 |
|
|
--operation mode is normal
|
| 3020 |
|
|
|
| 3021 |
|
|
VD1_op2_reged[5] = DFFEAS(VD1_b_o_iv_5, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 3022 |
|
|
|
| 3023 |
|
|
|
| 3024 |
|
|
--TD1_alu_out_7_0_0_m4_0[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[5]
|
| 3025 |
|
|
--operation mode is normal
|
| 3026 |
|
|
|
| 3027 |
|
|
TD1_alu_out_7_0_0_m4_0[5] = VD1_b_o_iv_5 & TD1_alu_out_7_0_0_o3_0 & TD1_alu_out_0_a3[28] # !VD1_b_o_iv_5 & TD1_alu_out_7_0_0_m4_0_a[3];
|
| 3028 |
|
|
|
| 3029 |
|
|
|
| 3030 |
|
|
--TD1_alu_out_7_0_0_m2_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_a[5]
|
| 3031 |
|
|
--operation mode is normal
|
| 3032 |
|
|
|
| 3033 |
|
|
TD1_alu_out_7_0_0_m2_a[5] = VD1_b_o_iv_5 & !TD1_m107 # !VD1_b_o_iv_5 & !TD1_alu_out_0_a3[28];
|
| 3034 |
|
|
|
| 3035 |
|
|
|
| 3036 |
|
|
--PD1_a_o_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[5]
|
| 3037 |
|
|
--operation mode is normal
|
| 3038 |
|
|
|
| 3039 |
|
|
PD1_a_o_a[5] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_5 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_5;
|
| 3040 |
|
|
|
| 3041 |
|
|
|
| 3042 |
|
|
--PD1_a_o_3_Z[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[5]
|
| 3043 |
|
|
--operation mode is normal
|
| 3044 |
|
|
|
| 3045 |
|
|
PD1_a_o_3_Z[5] = PD1_a_o_3_s[0] & SD1_r32_o_5 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[5];
|
| 3046 |
|
|
|
| 3047 |
|
|
|
| 3048 |
|
|
--UD1_shift_out_87[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[5]
|
| 3049 |
|
|
--operation mode is normal
|
| 3050 |
|
|
|
| 3051 |
|
|
UD1_shift_out_87[5] = PD1_a_o_2 & UD1_shift_out_87_d[5] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[5] # !PD1_a_o_0 & VD1_b_o_iv_7;
|
| 3052 |
|
|
|
| 3053 |
|
|
|
| 3054 |
|
|
--UD1_shift_out_89_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[5]
|
| 3055 |
|
|
--operation mode is normal
|
| 3056 |
|
|
|
| 3057 |
|
|
UD1_shift_out_89_a[5] = PD1_a_o_2 & !UD1_shift_out_85_d[5] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[5] # !PD1_a_o_1 & !VD1_b_o_iv_4;
|
| 3058 |
|
|
|
| 3059 |
|
|
|
| 3060 |
|
|
--UD1_shift_out_91[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[5]
|
| 3061 |
|
|
--operation mode is normal
|
| 3062 |
|
|
|
| 3063 |
|
|
UD1_shift_out_91[5] = UD1_shift_out_sn_m17_0 & UD1_shift_out_88[5] # !UD1_shift_out_sn_m17_0 & UD1_shift_out587 & UD1_shift_out_91_a[5];
|
| 3064 |
|
|
|
| 3065 |
|
|
|
| 3066 |
|
|
--UD1_shift_out_86[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[5]
|
| 3067 |
|
|
--operation mode is normal
|
| 3068 |
|
|
|
| 3069 |
|
|
UD1_shift_out_86[5] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[5] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[5];
|
| 3070 |
|
|
|
| 3071 |
|
|
|
| 3072 |
|
|
--CC1_dmem_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3|dmem_ctl_o_2
|
| 3073 |
|
|
--operation mode is normal
|
| 3074 |
|
|
|
| 3075 |
|
|
CC1_dmem_ctl_o_2_lut_out = WB84L2;
|
| 3076 |
|
|
CC1_dmem_ctl_o_2 = DFFEAS(CC1_dmem_ctl_o_2_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 3077 |
|
|
|
| 3078 |
|
|
|
| 3079 |
|
|
--UD1_shift_out_89_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[2]
|
| 3080 |
|
|
--operation mode is normal
|
| 3081 |
|
|
|
| 3082 |
|
|
UD1_shift_out_89_a[2] = PD1_a_o_1 & VD1_b_o_iv_0 & !PD1_a_o_0 # !PD1_a_o_1 & VD1_b_o_iv_1;
|
| 3083 |
|
|
|
| 3084 |
|
|
|
| 3085 |
|
|
--UD1_shift_out_87[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[2]
|
| 3086 |
|
|
--operation mode is normal
|
| 3087 |
|
|
|
| 3088 |
|
|
UD1_shift_out_87[2] = PD1_a_o_0 & UD1_shift_out_80[2] # !PD1_a_o_0 & UD1_shift_out_82[2];
|
| 3089 |
|
|
|
| 3090 |
|
|
|
| 3091 |
|
|
--UD1_shift_out_86_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_2
|
| 3092 |
|
|
--operation mode is normal
|
| 3093 |
|
|
|
| 3094 |
|
|
UD1_shift_out_86_2 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[2] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[2];
|
| 3095 |
|
|
|
| 3096 |
|
|
|
| 3097 |
|
|
--UD1_shift_out_91_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_2
|
| 3098 |
|
|
--operation mode is normal
|
| 3099 |
|
|
|
| 3100 |
|
|
UD1_shift_out_91_2 = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[2] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[2];
|
| 3101 |
|
|
|
| 3102 |
|
|
|
| 3103 |
|
|
--MD1_c_0_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[2]
|
| 3104 |
|
|
--operation mode is normal
|
| 3105 |
|
|
|
| 3106 |
|
|
MD1_c_0_a[2] = VD1_un24_res & !VD1_hilo_34 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_2;
|
| 3107 |
|
|
|
| 3108 |
|
|
|
| 3109 |
|
|
--TD1_m112 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m112
|
| 3110 |
|
|
--operation mode is normal
|
| 3111 |
|
|
|
| 3112 |
|
|
TD1_m112 = VD1_b_o_iv_2 & TD1_m112_a & TD1_m7 # !TD1_m112_a & !TD1_m9 # !VD1_b_o_iv_2 & TD1_m112_a;
|
| 3113 |
|
|
|
| 3114 |
|
|
|
| 3115 |
|
|
--TD1_m109 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m109
|
| 3116 |
|
|
--operation mode is normal
|
| 3117 |
|
|
|
| 3118 |
|
|
TD1_m109 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add2;
|
| 3119 |
|
|
|
| 3120 |
|
|
|
| 3121 |
|
|
--MD1_c_0_Z[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_Z[3]
|
| 3122 |
|
|
--operation mode is normal
|
| 3123 |
|
|
|
| 3124 |
|
|
MD1_c_0_Z[3] = TD1_alu_out_0_a3_0_0 & VD1_b_o_iv_3 # !MD1_c_0_a[3];
|
| 3125 |
|
|
|
| 3126 |
|
|
|
| 3127 |
|
|
--TD1_alu_out_7_0_0_m2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_0
|
| 3128 |
|
|
--operation mode is normal
|
| 3129 |
|
|
|
| 3130 |
|
|
TD1_alu_out_7_0_0_m2_0 = PD1_a_o_3 & !TD1_alu_out_7_0_0_m2_a[3] # !PD1_a_o_3 & TD1_alu_out_7_0_0_m4_0[3];
|
| 3131 |
|
|
|
| 3132 |
|
|
|
| 3133 |
|
|
--UD1_shift_out_89[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[3]
|
| 3134 |
|
|
--operation mode is normal
|
| 3135 |
|
|
|
| 3136 |
|
|
UD1_shift_out_89[3] = UD1_shift_out586 & UD1_shift_out_89_a[3] # !UD1_shift_out586 & PD1_a_o_0 & !UD1_shift_out_89_a[3] # !PD1_a_o_0 & UD1_shift_out_82[3];
|
| 3137 |
|
|
|
| 3138 |
|
|
|
| 3139 |
|
|
--UD1_shift_out_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[3]
|
| 3140 |
|
|
--operation mode is normal
|
| 3141 |
|
|
|
| 3142 |
|
|
UD1_shift_out_a[3] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91[3] # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86[3];
|
| 3143 |
|
|
|
| 3144 |
|
|
|
| 3145 |
|
|
--CC1_dmem_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3|dmem_ctl_o_0
|
| 3146 |
|
|
--operation mode is normal
|
| 3147 |
|
|
|
| 3148 |
|
|
CC1_dmem_ctl_o_0_lut_out = WB64L2;
|
| 3149 |
|
|
CC1_dmem_ctl_o_0 = DFFEAS(CC1_dmem_ctl_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 3150 |
|
|
|
| 3151 |
|
|
|
| 3152 |
|
|
--CC1_dmem_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3|dmem_ctl_o_1
|
| 3153 |
|
|
--operation mode is normal
|
| 3154 |
|
|
|
| 3155 |
|
|
CC1_dmem_ctl_o_1_lut_out = WB74L2;
|
| 3156 |
|
|
CC1_dmem_ctl_o_1 = DFFEAS(CC1_dmem_ctl_o_1_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 3157 |
|
|
|
| 3158 |
|
|
|
| 3159 |
|
|
--AB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_14
|
| 3160 |
|
|
--operation mode is normal
|
| 3161 |
|
|
|
| 3162 |
|
|
AB1_r32_o_14_lut_out = MD1_c_0_15 # UD1_shift_out_sn_m31_i & !MD1_c_a_16 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_15;
|
| 3163 |
|
|
AB1_r32_o_14 = DFFEAS(AB1_r32_o_14_lut_out, E1__clk0, VCC, , , , , , );
|
| 3164 |
|
|
|
| 3165 |
|
|
|
| 3166 |
|
|
--AB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_15
|
| 3167 |
|
|
--operation mode is normal
|
| 3168 |
|
|
|
| 3169 |
|
|
AB1_r32_o_15_lut_out = MD1_c_0_16 # UD1_shift_out_sn_m31_i & UD1_shift_out_92_11 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_16;
|
| 3170 |
|
|
AB1_r32_o_15 = DFFEAS(AB1_r32_o_15_lut_out, E1__clk0, VCC, , , , , , );
|
| 3171 |
|
|
|
| 3172 |
|
|
|
| 3173 |
|
|
--AB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_12
|
| 3174 |
|
|
--operation mode is normal
|
| 3175 |
|
|
|
| 3176 |
|
|
AB1_r32_o_12_lut_out = MD1_c_0_13 # UD1_shift_out_sn_m31_i & !MD1_c_a_14 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_13;
|
| 3177 |
|
|
AB1_r32_o_12 = DFFEAS(AB1_r32_o_12_lut_out, E1__clk0, VCC, , , , , , );
|
| 3178 |
|
|
|
| 3179 |
|
|
|
| 3180 |
|
|
--AB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_13
|
| 3181 |
|
|
--operation mode is normal
|
| 3182 |
|
|
|
| 3183 |
|
|
AB1_r32_o_13_lut_out = MD1_c_0_14 # UD1_shift_out_sn_m31_i & !MD1_c_a_15 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_14;
|
| 3184 |
|
|
AB1_r32_o_13 = DFFEAS(AB1_r32_o_13_lut_out, E1__clk0, VCC, , , , , , );
|
| 3185 |
|
|
|
| 3186 |
|
|
|
| 3187 |
|
|
--AB1_c_29 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_29
|
| 3188 |
|
|
--operation mode is normal
|
| 3189 |
|
|
|
| 3190 |
|
|
AB1_c_29 = MD1_c_0_30 # UD1_shift_out_sn_m31_i & UD1_shift_out_92_25 # !UD1_shift_out_sn_m31_i & !MD1_c_a_31;
|
| 3191 |
|
|
|
| 3192 |
|
|
--AB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_29
|
| 3193 |
|
|
--operation mode is normal
|
| 3194 |
|
|
|
| 3195 |
|
|
AB1_r32_o_29 = DFFEAS(AB1_c_29, E1__clk0, VCC, , , , , , );
|
| 3196 |
|
|
|
| 3197 |
|
|
|
| 3198 |
|
|
--F1_rd_status_29_0_a2_0_8_a is mips_sys:isys|mips_dvc:imips_dvc|rd_status_29_0_a2_0_8_a
|
| 3199 |
|
|
--operation mode is normal
|
| 3200 |
|
|
|
| 3201 |
|
|
F1_rd_status_29_0_a2_0_8_a = !AB1_r32_o_6 & !AB1_r32_o_7 & !AB1_r32_o_8 & !AB1_r32_o_9;
|
| 3202 |
|
|
|
| 3203 |
|
|
|
| 3204 |
|
|
--AB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_19
|
| 3205 |
|
|
--operation mode is normal
|
| 3206 |
|
|
|
| 3207 |
|
|
AB1_r32_o_19_lut_out = MD1_c_0_20 # UD1_shift_out_sn_m31_i & MD1_c_a_21 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_20;
|
| 3208 |
|
|
AB1_r32_o_19 = DFFEAS(AB1_r32_o_19_lut_out, E1__clk0, VCC, , , , , , );
|
| 3209 |
|
|
|
| 3210 |
|
|
|
| 3211 |
|
|
--AB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_18
|
| 3212 |
|
|
--operation mode is normal
|
| 3213 |
|
|
|
| 3214 |
|
|
AB1_r32_o_18_lut_out = MD1_c_1_20 # UD1_shift_out_sn_m31_i & MD1_c_a_20 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_19;
|
| 3215 |
|
|
AB1_r32_o_18 = DFFEAS(AB1_r32_o_18_lut_out, E1__clk0, VCC, , , , , , );
|
| 3216 |
|
|
|
| 3217 |
|
|
|
| 3218 |
|
|
--F1_dout_0_0_a3_6_5_2[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_2[0]
|
| 3219 |
|
|
--operation mode is normal
|
| 3220 |
|
|
|
| 3221 |
|
|
F1_dout_0_0_a3_6_5_2[0] = !AB1_r32_o_17 & !AB1_r32_o_16;
|
| 3222 |
|
|
|
| 3223 |
|
|
|
| 3224 |
|
|
--F1_dout_0_0_a3_6_5_12_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_12_a[0]
|
| 3225 |
|
|
--operation mode is normal
|
| 3226 |
|
|
|
| 3227 |
|
|
F1_dout_0_0_a3_6_5_12_a[0] = !AB1_r32_o_24 & !AB1_r32_o_25 & !AB1_r32_o_26 & !AB1_r32_o_27;
|
| 3228 |
|
|
|
| 3229 |
|
|
|
| 3230 |
|
|
--AB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_11
|
| 3231 |
|
|
--operation mode is normal
|
| 3232 |
|
|
|
| 3233 |
|
|
AB1_r32_o_11_lut_out = MD1_c_0_12 # UD1_shift_out_sn_m31_i & !MD1_c_a_13 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_12;
|
| 3234 |
|
|
AB1_r32_o_11 = DFFEAS(AB1_r32_o_11_lut_out, E1__clk0, VCC, , , , , , );
|
| 3235 |
|
|
|
| 3236 |
|
|
|
| 3237 |
|
|
--AB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_28
|
| 3238 |
|
|
--operation mode is normal
|
| 3239 |
|
|
|
| 3240 |
|
|
AB1_r32_o_28_lut_out = VD1_hilo_30 & VD1_un11_res # !TD1_m97 # !MD1_c_a_30;
|
| 3241 |
|
|
AB1_r32_o_28 = DFFEAS(AB1_r32_o_28_lut_out, E1__clk0, VCC, , , , , , );
|
| 3242 |
|
|
|
| 3243 |
|
|
|
| 3244 |
|
|
--JC1_rd_status_29_0_a2_0_7 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|rd_status_29_0_a2_0_7
|
| 3245 |
|
|
--operation mode is normal
|
| 3246 |
|
|
|
| 3247 |
|
|
JC1_dmem_ctl_o_3__Z_qfbk = JC1_dmem_ctl_o_3__Z;
|
| 3248 |
|
|
JC1_rd_status_29_0_a2_0_7 = !AB1_r32_o_10 & !AB1_r32_o_4 & !JC1_dmem_ctl_o_3__Z_qfbk & !RB1_byte_addr_o_0;
|
| 3249 |
|
|
|
| 3250 |
|
|
--JC1_dmem_ctl_o_3__Z is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_3__Z
|
| 3251 |
|
|
--operation mode is normal
|
| 3252 |
|
|
|
| 3253 |
|
|
JC1_dmem_ctl_o_3__Z = DFFEAS(JC1_rd_status_29_0_a2_0_7, E1__clk0, VCC, , , QC1_dmem_ctl_o_3, , , VCC);
|
| 3254 |
|
|
|
| 3255 |
|
|
|
| 3256 |
|
|
--F1_dout_0_0_a3_6_5_8[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_8[0]
|
| 3257 |
|
|
--operation mode is normal
|
| 3258 |
|
|
|
| 3259 |
|
|
F1_dout_0_0_a3_6_5_8[0] = !AB1_r32_o_22 & !AB1_r32_o_23 & !AB1_r32_o_20 & !AB1_r32_o_21;
|
| 3260 |
|
|
|
| 3261 |
|
|
|
| 3262 |
|
|
--K1_cntr_5_0[6] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[6]
|
| 3263 |
|
|
--operation mode is normal
|
| 3264 |
|
|
|
| 3265 |
|
|
K1_s_cntr_6__Z_qfbk = K1_s_cntr_6__Z;
|
| 3266 |
|
|
K1_cntr_5_0[6] = F1_wr_tmr_data_0_a2 & CB1_r32_o_6 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_6__Z_qfbk;
|
| 3267 |
|
|
|
| 3268 |
|
|
--K1_s_cntr_6__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_6__Z
|
| 3269 |
|
|
--operation mode is normal
|
| 3270 |
|
|
|
| 3271 |
|
|
K1_s_cntr_6__Z = DFFEAS(K1_cntr_5_0[6], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_6, , , VCC);
|
| 3272 |
|
|
|
| 3273 |
|
|
|
| 3274 |
|
|
--M1_buffer_reg_6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_6
|
| 3275 |
|
|
--operation mode is normal
|
| 3276 |
|
|
|
| 3277 |
|
|
M1_buffer_reg_6_lut_out = M1_rx_sr[6];
|
| 3278 |
|
|
M1_buffer_reg_6 = DFFEAS(M1_buffer_reg_6_lut_out, E1__clk0, VCC, , C1_G_578, , , !sys_rst, );
|
| 3279 |
|
|
|
| 3280 |
|
|
|
| 3281 |
|
|
--UB1_dout_2_i_0[6] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[6]
|
| 3282 |
|
|
--operation mode is normal
|
| 3283 |
|
|
|
| 3284 |
|
|
UB1_dout_2_i_0[6] = !UB1_dout_2_i_0_a2_x[6] & !UB1_dout_2_i_0_a[6] & JE1_q_b[6] # !UB1_dout_2_i_o2[3];
|
| 3285 |
|
|
|
| 3286 |
|
|
|
| 3287 |
|
|
--WB11L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_6__Z|lpm_latch:U1|q[0]~56
|
| 3288 |
|
|
--operation mode is normal
|
| 3289 |
|
|
|
| 3290 |
|
|
WB11L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[6] # !UB1_un1_byte_addr_2 & WB11L1;
|
| 3291 |
|
|
|
| 3292 |
|
|
|
| 3293 |
|
|
--GD1_dout_iv_1_a[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[6]
|
| 3294 |
|
|
--operation mode is normal
|
| 3295 |
|
|
|
| 3296 |
|
|
GD1_dout_iv_1_a[6] = FD1_r_data_6 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_4 # !FD1_r_data_6 & !ZD1_mux_fw_1 # !AB1_r32_o_4;
|
| 3297 |
|
|
|
| 3298 |
|
|
|
| 3299 |
|
|
--LD1_q_b[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[6]
|
| 3300 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 3301 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 3302 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 3303 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 3304 |
|
|
LD1_q_b[6]_PORT_A_data_in = FD1_wb_o_6;
|
| 3305 |
|
|
LD1_q_b[6]_PORT_A_data_in_reg = DFFE(LD1_q_b[6]_PORT_A_data_in, LD1_q_b[6]_clock_0, , , );
|
| 3306 |
|
|
LD1_q_b[6]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 3307 |
|
|
LD1_q_b[6]_PORT_A_address_reg = DFFE(LD1_q_b[6]_PORT_A_address, LD1_q_b[6]_clock_0, , , );
|
| 3308 |
|
|
LD1_q_b[6]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 3309 |
|
|
LD1_q_b[6]_PORT_B_address_reg = DFFE(LD1_q_b[6]_PORT_B_address, LD1_q_b[6]_clock_1, , , );
|
| 3310 |
|
|
LD1_q_b[6]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 3311 |
|
|
LD1_q_b[6]_PORT_A_write_enable_reg = DFFE(LD1_q_b[6]_PORT_A_write_enable, LD1_q_b[6]_clock_0, , , );
|
| 3312 |
|
|
LD1_q_b[6]_PORT_B_read_enable = VCC;
|
| 3313 |
|
|
LD1_q_b[6]_PORT_B_read_enable_reg = DFFE(LD1_q_b[6]_PORT_B_read_enable, LD1_q_b[6]_clock_1, , , );
|
| 3314 |
|
|
LD1_q_b[6]_clock_0 = E1__clk0;
|
| 3315 |
|
|
LD1_q_b[6]_clock_1 = E1__clk0;
|
| 3316 |
|
|
LD1_q_b[6]_PORT_B_data_out = MEMORY(LD1_q_b[6]_PORT_A_data_in_reg, , LD1_q_b[6]_PORT_A_address_reg, LD1_q_b[6]_PORT_B_address_reg, LD1_q_b[6]_PORT_A_write_enable_reg, LD1_q_b[6]_PORT_B_read_enable_reg, , , LD1_q_b[6]_clock_0, LD1_q_b[6]_clock_1, , , , );
|
| 3317 |
|
|
LD1_q_b[6] = LD1_q_b[6]_PORT_B_data_out[0];
|
| 3318 |
|
|
|
| 3319 |
|
|
|
| 3320 |
|
|
--UD1_shift_out_87[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[6]
|
| 3321 |
|
|
--operation mode is normal
|
| 3322 |
|
|
|
| 3323 |
|
|
UD1_shift_out_87[6] = PD1_a_o_2 & UD1_shift_out_87_d[6] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[6] # !PD1_a_o_0 & VD1_b_o_iv_8;
|
| 3324 |
|
|
|
| 3325 |
|
|
|
| 3326 |
|
|
--UD1_shift_out_89_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[6]
|
| 3327 |
|
|
--operation mode is normal
|
| 3328 |
|
|
|
| 3329 |
|
|
UD1_shift_out_89_a[6] = PD1_a_o_2 & !UD1_shift_out_85_d[6] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[6] # !PD1_a_o_1 & !VD1_b_o_iv_5;
|
| 3330 |
|
|
|
| 3331 |
|
|
|
| 3332 |
|
|
--MD1_c_1_Z[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_Z[6]
|
| 3333 |
|
|
--operation mode is normal
|
| 3334 |
|
|
|
| 3335 |
|
|
MD1_c_1_Z[6] = TD1_alu_out_0_a2_0 # TD1_alu_out_0_a3_0_0 & VD1_b_o_iv_6 # !MD1_c_1_a[6];
|
| 3336 |
|
|
|
| 3337 |
|
|
|
| 3338 |
|
|
--TD1_un1_a_add6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add6
|
| 3339 |
|
|
--operation mode is arithmetic
|
| 3340 |
|
|
|
| 3341 |
|
|
TD1_un1_a_add6_carry_eqn = TD1_un1_a_carry_5;
|
| 3342 |
|
|
TD1_un1_a_add6 = PD1_a_o_6 $ TD1_un1_b_1_combout[6] $ !TD1_un1_a_add6_carry_eqn;
|
| 3343 |
|
|
|
| 3344 |
|
|
--TD1_un1_a_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_6
|
| 3345 |
|
|
--operation mode is arithmetic
|
| 3346 |
|
|
|
| 3347 |
|
|
TD1_un1_a_carry_6 = CARRY(PD1_a_o_6 & TD1_un1_b_1_combout[6] # !TD1_un1_a_carry_5 # !PD1_a_o_6 & TD1_un1_b_1_combout[6] & !TD1_un1_a_carry_5);
|
| 3348 |
|
|
|
| 3349 |
|
|
|
| 3350 |
|
|
--UD1_shift_out_91[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[6]
|
| 3351 |
|
|
--operation mode is normal
|
| 3352 |
|
|
|
| 3353 |
|
|
UD1_shift_out_91[6] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[6] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[6];
|
| 3354 |
|
|
|
| 3355 |
|
|
|
| 3356 |
|
|
--UD1_shift_out_86[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[6]
|
| 3357 |
|
|
--operation mode is normal
|
| 3358 |
|
|
|
| 3359 |
|
|
UD1_shift_out_86[6] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[6] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[6];
|
| 3360 |
|
|
|
| 3361 |
|
|
|
| 3362 |
|
|
--K1_cntr_5_0[5] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[5]
|
| 3363 |
|
|
--operation mode is normal
|
| 3364 |
|
|
|
| 3365 |
|
|
K1_s_cntr_5__Z_qfbk = K1_s_cntr_5__Z;
|
| 3366 |
|
|
K1_cntr_5_0[5] = F1_wr_tmr_data_0_a2 & CB1_r32_o_5 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_5__Z_qfbk;
|
| 3367 |
|
|
|
| 3368 |
|
|
--K1_s_cntr_5__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_5__Z
|
| 3369 |
|
|
--operation mode is normal
|
| 3370 |
|
|
|
| 3371 |
|
|
K1_s_cntr_5__Z = DFFEAS(K1_cntr_5_0[5], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_5, , , VCC);
|
| 3372 |
|
|
|
| 3373 |
|
|
|
| 3374 |
|
|
--M1_buffer_reg_5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_5
|
| 3375 |
|
|
--operation mode is normal
|
| 3376 |
|
|
|
| 3377 |
|
|
M1_buffer_reg_5_lut_out = M1_rx_sr[5];
|
| 3378 |
|
|
M1_buffer_reg_5 = DFFEAS(M1_buffer_reg_5_lut_out, E1__clk0, VCC, , C1_G_578, , , !sys_rst, );
|
| 3379 |
|
|
|
| 3380 |
|
|
|
| 3381 |
|
|
--UB1_dout_2_i_0[5] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[5]
|
| 3382 |
|
|
--operation mode is normal
|
| 3383 |
|
|
|
| 3384 |
|
|
UB1_dout_2_i_0[5] = !UB1_dout_2_i_0_a2_x[5] & !UB1_dout_2_i_0_a[5] & JE1_q_b[5] # !UB1_dout_2_i_o2[3];
|
| 3385 |
|
|
|
| 3386 |
|
|
|
| 3387 |
|
|
--WB01L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_5__Z|lpm_latch:U1|q[0]~56
|
| 3388 |
|
|
--operation mode is normal
|
| 3389 |
|
|
|
| 3390 |
|
|
WB01L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[5] # !UB1_un1_byte_addr_2 & WB01L1;
|
| 3391 |
|
|
|
| 3392 |
|
|
|
| 3393 |
|
|
--GD1_dout_iv_1_a[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[5]
|
| 3394 |
|
|
--operation mode is normal
|
| 3395 |
|
|
|
| 3396 |
|
|
GD1_dout_iv_1_a[5] = FD1_r_data_5 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_3 # !FD1_r_data_5 & !ZD1_mux_fw_1 # !AB1_r32_o_3;
|
| 3397 |
|
|
|
| 3398 |
|
|
|
| 3399 |
|
|
--LD1_q_b[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[5]
|
| 3400 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 3401 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 3402 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 3403 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 3404 |
|
|
LD1_q_b[5]_PORT_A_data_in = FD1_wb_o_5;
|
| 3405 |
|
|
LD1_q_b[5]_PORT_A_data_in_reg = DFFE(LD1_q_b[5]_PORT_A_data_in, LD1_q_b[5]_clock_0, , , );
|
| 3406 |
|
|
LD1_q_b[5]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 3407 |
|
|
LD1_q_b[5]_PORT_A_address_reg = DFFE(LD1_q_b[5]_PORT_A_address, LD1_q_b[5]_clock_0, , , );
|
| 3408 |
|
|
LD1_q_b[5]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 3409 |
|
|
LD1_q_b[5]_PORT_B_address_reg = DFFE(LD1_q_b[5]_PORT_B_address, LD1_q_b[5]_clock_1, , , );
|
| 3410 |
|
|
LD1_q_b[5]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 3411 |
|
|
LD1_q_b[5]_PORT_A_write_enable_reg = DFFE(LD1_q_b[5]_PORT_A_write_enable, LD1_q_b[5]_clock_0, , , );
|
| 3412 |
|
|
LD1_q_b[5]_PORT_B_read_enable = VCC;
|
| 3413 |
|
|
LD1_q_b[5]_PORT_B_read_enable_reg = DFFE(LD1_q_b[5]_PORT_B_read_enable, LD1_q_b[5]_clock_1, , , );
|
| 3414 |
|
|
LD1_q_b[5]_clock_0 = E1__clk0;
|
| 3415 |
|
|
LD1_q_b[5]_clock_1 = E1__clk0;
|
| 3416 |
|
|
LD1_q_b[5]_PORT_B_data_out = MEMORY(LD1_q_b[5]_PORT_A_data_in_reg, , LD1_q_b[5]_PORT_A_address_reg, LD1_q_b[5]_PORT_B_address_reg, LD1_q_b[5]_PORT_A_write_enable_reg, LD1_q_b[5]_PORT_B_read_enable_reg, , , LD1_q_b[5]_clock_0, LD1_q_b[5]_clock_1, , , , );
|
| 3417 |
|
|
LD1_q_b[5] = LD1_q_b[5]_PORT_B_data_out[0];
|
| 3418 |
|
|
|
| 3419 |
|
|
|
| 3420 |
|
|
--K1_cntr_5_0[4] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[4]
|
| 3421 |
|
|
--operation mode is normal
|
| 3422 |
|
|
|
| 3423 |
|
|
K1_s_cntr_4__Z_qfbk = K1_s_cntr_4__Z;
|
| 3424 |
|
|
K1_cntr_5_0[4] = F1_wr_tmr_data_0_a2 & CB1_r32_o_4 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_4__Z_qfbk;
|
| 3425 |
|
|
|
| 3426 |
|
|
--K1_s_cntr_4__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_4__Z
|
| 3427 |
|
|
--operation mode is normal
|
| 3428 |
|
|
|
| 3429 |
|
|
K1_s_cntr_4__Z = DFFEAS(K1_cntr_5_0[4], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_4, , , VCC);
|
| 3430 |
|
|
|
| 3431 |
|
|
|
| 3432 |
|
|
--M1_buffer_reg_4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_4
|
| 3433 |
|
|
--operation mode is normal
|
| 3434 |
|
|
|
| 3435 |
|
|
M1_buffer_reg_4_lut_out = M1_rx_sr[4];
|
| 3436 |
|
|
M1_buffer_reg_4 = DFFEAS(M1_buffer_reg_4_lut_out, E1__clk0, VCC, , C1_G_578, , , !sys_rst, );
|
| 3437 |
|
|
|
| 3438 |
|
|
|
| 3439 |
|
|
--UB1_dout_2_i_0[4] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[4]
|
| 3440 |
|
|
--operation mode is normal
|
| 3441 |
|
|
|
| 3442 |
|
|
UB1_dout_2_i_0[4] = !UB1_dout_2_i_0_a2_x[4] & !UB1_dout_2_i_0_a[4] & JE1_q_b[4] # !UB1_dout_2_i_o2[3];
|
| 3443 |
|
|
|
| 3444 |
|
|
|
| 3445 |
|
|
--WB9L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_4__Z|lpm_latch:U1|q[0]~56
|
| 3446 |
|
|
--operation mode is normal
|
| 3447 |
|
|
|
| 3448 |
|
|
WB9L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[4] # !UB1_un1_byte_addr_2 & WB9L1;
|
| 3449 |
|
|
|
| 3450 |
|
|
|
| 3451 |
|
|
--GD1_dout_iv_1_a[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[4]
|
| 3452 |
|
|
--operation mode is normal
|
| 3453 |
|
|
|
| 3454 |
|
|
GD1_dout_iv_1_a[4] = FD1_r_data_4 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_2 # !FD1_r_data_4 & !ZD1_mux_fw_1 # !AB1_r32_o_2;
|
| 3455 |
|
|
|
| 3456 |
|
|
|
| 3457 |
|
|
--LD1_q_b[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[4]
|
| 3458 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 3459 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 3460 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 3461 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 3462 |
|
|
LD1_q_b[4]_PORT_A_data_in = FD1_wb_o_4;
|
| 3463 |
|
|
LD1_q_b[4]_PORT_A_data_in_reg = DFFE(LD1_q_b[4]_PORT_A_data_in, LD1_q_b[4]_clock_0, , , );
|
| 3464 |
|
|
LD1_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 3465 |
|
|
LD1_q_b[4]_PORT_A_address_reg = DFFE(LD1_q_b[4]_PORT_A_address, LD1_q_b[4]_clock_0, , , );
|
| 3466 |
|
|
LD1_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 3467 |
|
|
LD1_q_b[4]_PORT_B_address_reg = DFFE(LD1_q_b[4]_PORT_B_address, LD1_q_b[4]_clock_1, , , );
|
| 3468 |
|
|
LD1_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 3469 |
|
|
LD1_q_b[4]_PORT_A_write_enable_reg = DFFE(LD1_q_b[4]_PORT_A_write_enable, LD1_q_b[4]_clock_0, , , );
|
| 3470 |
|
|
LD1_q_b[4]_PORT_B_read_enable = VCC;
|
| 3471 |
|
|
LD1_q_b[4]_PORT_B_read_enable_reg = DFFE(LD1_q_b[4]_PORT_B_read_enable, LD1_q_b[4]_clock_1, , , );
|
| 3472 |
|
|
LD1_q_b[4]_clock_0 = E1__clk0;
|
| 3473 |
|
|
LD1_q_b[4]_clock_1 = E1__clk0;
|
| 3474 |
|
|
LD1_q_b[4]_PORT_B_data_out = MEMORY(LD1_q_b[4]_PORT_A_data_in_reg, , LD1_q_b[4]_PORT_A_address_reg, LD1_q_b[4]_PORT_B_address_reg, LD1_q_b[4]_PORT_A_write_enable_reg, LD1_q_b[4]_PORT_B_read_enable_reg, , , LD1_q_b[4]_clock_0, LD1_q_b[4]_clock_1, , , , );
|
| 3475 |
|
|
LD1_q_b[4] = LD1_q_b[4]_PORT_B_data_out[0];
|
| 3476 |
|
|
|
| 3477 |
|
|
|
| 3478 |
|
|
--K1_cntr_5_0[3] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[3]
|
| 3479 |
|
|
--operation mode is normal
|
| 3480 |
|
|
|
| 3481 |
|
|
K1_s_cntr_3__Z_qfbk = K1_s_cntr_3__Z;
|
| 3482 |
|
|
K1_cntr_5_0[3] = F1_wr_tmr_data_0_a2 & CB1_r32_o_3 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_3__Z_qfbk;
|
| 3483 |
|
|
|
| 3484 |
|
|
--K1_s_cntr_3__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_3__Z
|
| 3485 |
|
|
--operation mode is normal
|
| 3486 |
|
|
|
| 3487 |
|
|
K1_s_cntr_3__Z = DFFEAS(K1_cntr_5_0[3], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_3, , , VCC);
|
| 3488 |
|
|
|
| 3489 |
|
|
|
| 3490 |
|
|
--M1_buffer_reg_3 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_3
|
| 3491 |
|
|
--operation mode is normal
|
| 3492 |
|
|
|
| 3493 |
|
|
M1_buffer_reg_3_lut_out = M1_rx_sr[3];
|
| 3494 |
|
|
M1_buffer_reg_3 = DFFEAS(M1_buffer_reg_3_lut_out, E1__clk0, VCC, , C1_G_578, , , !sys_rst, );
|
| 3495 |
|
|
|
| 3496 |
|
|
|
| 3497 |
|
|
--F1_dout_0_0_a3_6[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6[0]
|
| 3498 |
|
|
--operation mode is normal
|
| 3499 |
|
|
|
| 3500 |
|
|
F1_dout_0_0_a3_6[0] = F1_rd_status_29_0_a2_0_8 & F1_dout_0_0_a3_6_5_12[0] & F1_dout_0_0_a3_6_5_14[0] & !F1_dout_0_0_a3_6_a[0];
|
| 3501 |
|
|
|
| 3502 |
|
|
|
| 3503 |
|
|
--F1_cmd[1] is mips_sys:isys|mips_dvc:imips_dvc|cmd[1]
|
| 3504 |
|
|
--operation mode is normal
|
| 3505 |
|
|
|
| 3506 |
|
|
F1_cmd[1]_lut_out = CB1_r32_o_1;
|
| 3507 |
|
|
F1_cmd[1] = DFFEAS(F1_cmd[1]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 3508 |
|
|
|
| 3509 |
|
|
|
| 3510 |
|
|
--M1_int_req is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|int_req
|
| 3511 |
|
|
--operation mode is normal
|
| 3512 |
|
|
|
| 3513 |
|
|
M1_int_req_lut_out = M1_ua_state[4];
|
| 3514 |
|
|
M1_int_req = DFFEAS(M1_int_req_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 3515 |
|
|
|
| 3516 |
|
|
|
| 3517 |
|
|
--UB1_dout_2_i[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i[3]
|
| 3518 |
|
|
--operation mode is normal
|
| 3519 |
|
|
|
| 3520 |
|
|
UB1_dout_2_i[3] = !UB1_dout_2_i_a2_x[3] & !UB1_dout_2_i_a[3] & JE1_q_b[3] # !UB1_dout_2_i_o2[3];
|
| 3521 |
|
|
|
| 3522 |
|
|
|
| 3523 |
|
|
--WB8L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_3__Z|lpm_latch:U1|q[0]~56
|
| 3524 |
|
|
--operation mode is normal
|
| 3525 |
|
|
|
| 3526 |
|
|
WB8L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i[3] # !UB1_un1_byte_addr_2 & WB8L1;
|
| 3527 |
|
|
|
| 3528 |
|
|
|
| 3529 |
|
|
--GD1_dout_iv_1_a[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[3]
|
| 3530 |
|
|
--operation mode is normal
|
| 3531 |
|
|
|
| 3532 |
|
|
GD1_dout_iv_1_a[3] = FD1_r_data_3 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_1 # !FD1_r_data_3 & !ZD1_mux_fw_1 # !AB1_r32_o_1;
|
| 3533 |
|
|
|
| 3534 |
|
|
|
| 3535 |
|
|
--LD1_q_b[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[3]
|
| 3536 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 3537 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 3538 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 3539 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 3540 |
|
|
LD1_q_b[3]_PORT_A_data_in = FD1_wb_o_3;
|
| 3541 |
|
|
LD1_q_b[3]_PORT_A_data_in_reg = DFFE(LD1_q_b[3]_PORT_A_data_in, LD1_q_b[3]_clock_0, , , );
|
| 3542 |
|
|
LD1_q_b[3]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 3543 |
|
|
LD1_q_b[3]_PORT_A_address_reg = DFFE(LD1_q_b[3]_PORT_A_address, LD1_q_b[3]_clock_0, , , );
|
| 3544 |
|
|
LD1_q_b[3]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 3545 |
|
|
LD1_q_b[3]_PORT_B_address_reg = DFFE(LD1_q_b[3]_PORT_B_address, LD1_q_b[3]_clock_1, , , );
|
| 3546 |
|
|
LD1_q_b[3]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 3547 |
|
|
LD1_q_b[3]_PORT_A_write_enable_reg = DFFE(LD1_q_b[3]_PORT_A_write_enable, LD1_q_b[3]_clock_0, , , );
|
| 3548 |
|
|
LD1_q_b[3]_PORT_B_read_enable = VCC;
|
| 3549 |
|
|
LD1_q_b[3]_PORT_B_read_enable_reg = DFFE(LD1_q_b[3]_PORT_B_read_enable, LD1_q_b[3]_clock_1, , , );
|
| 3550 |
|
|
LD1_q_b[3]_clock_0 = E1__clk0;
|
| 3551 |
|
|
LD1_q_b[3]_clock_1 = E1__clk0;
|
| 3552 |
|
|
LD1_q_b[3]_PORT_B_data_out = MEMORY(LD1_q_b[3]_PORT_A_data_in_reg, , LD1_q_b[3]_PORT_A_address_reg, LD1_q_b[3]_PORT_B_address_reg, LD1_q_b[3]_PORT_A_write_enable_reg, LD1_q_b[3]_PORT_B_read_enable_reg, , , LD1_q_b[3]_clock_0, LD1_q_b[3]_clock_1, , , , );
|
| 3553 |
|
|
LD1_q_b[3] = LD1_q_b[3]_PORT_B_data_out[0];
|
| 3554 |
|
|
|
| 3555 |
|
|
|
| 3556 |
|
|
--K1_cntr_5_0[2] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[2]
|
| 3557 |
|
|
--operation mode is normal
|
| 3558 |
|
|
|
| 3559 |
|
|
K1_s_cntr_2__Z_qfbk = K1_s_cntr_2__Z;
|
| 3560 |
|
|
K1_cntr_5_0[2] = F1_wr_tmr_data_0_a2 & CB1_r32_o_2 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_2__Z_qfbk;
|
| 3561 |
|
|
|
| 3562 |
|
|
--K1_s_cntr_2__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_2__Z
|
| 3563 |
|
|
--operation mode is normal
|
| 3564 |
|
|
|
| 3565 |
|
|
K1_s_cntr_2__Z = DFFEAS(K1_cntr_5_0[2], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_2, , , VCC);
|
| 3566 |
|
|
|
| 3567 |
|
|
|
| 3568 |
|
|
--M1_buffer_reg_2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_2
|
| 3569 |
|
|
--operation mode is normal
|
| 3570 |
|
|
|
| 3571 |
|
|
M1_buffer_reg_2_lut_out = M1_rx_sr[2];
|
| 3572 |
|
|
M1_buffer_reg_2 = DFFEAS(M1_buffer_reg_2_lut_out, E1__clk0, VCC, , C1_G_578, , , !sys_rst, );
|
| 3573 |
|
|
|
| 3574 |
|
|
|
| 3575 |
|
|
--UB1_dout_2_i_0[2] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[2]
|
| 3576 |
|
|
--operation mode is normal
|
| 3577 |
|
|
|
| 3578 |
|
|
UB1_dout_2_i_0[2] = !UB1_dout_2_i_0_a2_x[2] & !UB1_dout_2_i_0_a[2] & JE1_q_b[2] # !UB1_dout_2_i_o2[3];
|
| 3579 |
|
|
|
| 3580 |
|
|
|
| 3581 |
|
|
--WB7L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_2__Z|lpm_latch:U1|q[0]~56
|
| 3582 |
|
|
--operation mode is normal
|
| 3583 |
|
|
|
| 3584 |
|
|
WB7L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[2] # !UB1_un1_byte_addr_2 & WB7L1;
|
| 3585 |
|
|
|
| 3586 |
|
|
|
| 3587 |
|
|
--GD1_dout_iv_1_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[2]
|
| 3588 |
|
|
--operation mode is normal
|
| 3589 |
|
|
|
| 3590 |
|
|
GD1_dout_iv_1_a[2] = FD1_r_data_2 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_0 # !FD1_r_data_2 & !ZD1_mux_fw_1 # !AB1_r32_o_0;
|
| 3591 |
|
|
|
| 3592 |
|
|
|
| 3593 |
|
|
--LD1_q_b[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[2]
|
| 3594 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 3595 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 3596 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 3597 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 3598 |
|
|
LD1_q_b[2]_PORT_A_data_in = FD1_wb_o_2;
|
| 3599 |
|
|
LD1_q_b[2]_PORT_A_data_in_reg = DFFE(LD1_q_b[2]_PORT_A_data_in, LD1_q_b[2]_clock_0, , , );
|
| 3600 |
|
|
LD1_q_b[2]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 3601 |
|
|
LD1_q_b[2]_PORT_A_address_reg = DFFE(LD1_q_b[2]_PORT_A_address, LD1_q_b[2]_clock_0, , , );
|
| 3602 |
|
|
LD1_q_b[2]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 3603 |
|
|
LD1_q_b[2]_PORT_B_address_reg = DFFE(LD1_q_b[2]_PORT_B_address, LD1_q_b[2]_clock_1, , , );
|
| 3604 |
|
|
LD1_q_b[2]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 3605 |
|
|
LD1_q_b[2]_PORT_A_write_enable_reg = DFFE(LD1_q_b[2]_PORT_A_write_enable, LD1_q_b[2]_clock_0, , , );
|
| 3606 |
|
|
LD1_q_b[2]_PORT_B_read_enable = VCC;
|
| 3607 |
|
|
LD1_q_b[2]_PORT_B_read_enable_reg = DFFE(LD1_q_b[2]_PORT_B_read_enable, LD1_q_b[2]_clock_1, , , );
|
| 3608 |
|
|
LD1_q_b[2]_clock_0 = E1__clk0;
|
| 3609 |
|
|
LD1_q_b[2]_clock_1 = E1__clk0;
|
| 3610 |
|
|
LD1_q_b[2]_PORT_B_data_out = MEMORY(LD1_q_b[2]_PORT_A_data_in_reg, , LD1_q_b[2]_PORT_A_address_reg, LD1_q_b[2]_PORT_B_address_reg, LD1_q_b[2]_PORT_A_write_enable_reg, LD1_q_b[2]_PORT_B_read_enable_reg, , , LD1_q_b[2]_clock_0, LD1_q_b[2]_clock_1, , , , );
|
| 3611 |
|
|
LD1_q_b[2] = LD1_q_b[2]_PORT_B_data_out[0];
|
| 3612 |
|
|
|
| 3613 |
|
|
|
| 3614 |
|
|
--K1_cntr_5_0[1] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[1]
|
| 3615 |
|
|
--operation mode is normal
|
| 3616 |
|
|
|
| 3617 |
|
|
K1_s_cntr_1__Z_qfbk = K1_s_cntr_1__Z;
|
| 3618 |
|
|
K1_cntr_5_0[1] = F1_wr_tmr_data_0_a2 & CB1_r32_o_1 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_1__Z_qfbk;
|
| 3619 |
|
|
|
| 3620 |
|
|
--K1_s_cntr_1__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_1__Z
|
| 3621 |
|
|
--operation mode is normal
|
| 3622 |
|
|
|
| 3623 |
|
|
K1_s_cntr_1__Z = DFFEAS(K1_cntr_5_0[1], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_1, , , VCC);
|
| 3624 |
|
|
|
| 3625 |
|
|
|
| 3626 |
|
|
--M1_buffer_reg_1 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_1
|
| 3627 |
|
|
--operation mode is normal
|
| 3628 |
|
|
|
| 3629 |
|
|
M1_buffer_reg_1_lut_out = M1_rx_sr[1];
|
| 3630 |
|
|
M1_buffer_reg_1 = DFFEAS(M1_buffer_reg_1_lut_out, E1__clk0, VCC, , C1_G_578, , , !sys_rst, );
|
| 3631 |
|
|
|
| 3632 |
|
|
|
| 3633 |
|
|
--F1_r_key1 is mips_sys:isys|mips_dvc:imips_dvc|r_key1
|
| 3634 |
|
|
--operation mode is normal
|
| 3635 |
|
|
|
| 3636 |
|
|
F1_r_key1_lut_out = key1;
|
| 3637 |
|
|
F1_r_key1 = DFFEAS(F1_r_key1_lut_out, E1__clk0, VCC, , , , , , );
|
| 3638 |
|
|
|
| 3639 |
|
|
|
| 3640 |
|
|
--UB1_dout_2_i_0[1] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[1]
|
| 3641 |
|
|
--operation mode is normal
|
| 3642 |
|
|
|
| 3643 |
|
|
UB1_dout_2_i_0[1] = !UB1_dout_2_i_0_a2_x[1] & !UB1_dout_2_i_0_a[1] & JE1_q_b[1] # !UB1_dout_2_i_o2[3];
|
| 3644 |
|
|
|
| 3645 |
|
|
|
| 3646 |
|
|
--WB6L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_1__Z|lpm_latch:U1|q[0]~56
|
| 3647 |
|
|
--operation mode is normal
|
| 3648 |
|
|
|
| 3649 |
|
|
WB6L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[1] # !UB1_un1_byte_addr_2 & WB6L1;
|
| 3650 |
|
|
|
| 3651 |
|
|
|
| 3652 |
|
|
--GD1_dout_iv_1_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[1]
|
| 3653 |
|
|
--operation mode is normal
|
| 3654 |
|
|
|
| 3655 |
|
|
GD1_dout_iv_1_a[1] = FD1_r_data_1 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !RB1_byte_addr_o_1 # !FD1_r_data_1 & !ZD1_mux_fw_1 # !RB1_byte_addr_o_1;
|
| 3656 |
|
|
|
| 3657 |
|
|
|
| 3658 |
|
|
--LD1_q_b[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[1]
|
| 3659 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 3660 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 3661 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 3662 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 3663 |
|
|
LD1_q_b[1]_PORT_A_data_in = FD1_wb_o_1;
|
| 3664 |
|
|
LD1_q_b[1]_PORT_A_data_in_reg = DFFE(LD1_q_b[1]_PORT_A_data_in, LD1_q_b[1]_clock_0, , , );
|
| 3665 |
|
|
LD1_q_b[1]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 3666 |
|
|
LD1_q_b[1]_PORT_A_address_reg = DFFE(LD1_q_b[1]_PORT_A_address, LD1_q_b[1]_clock_0, , , );
|
| 3667 |
|
|
LD1_q_b[1]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 3668 |
|
|
LD1_q_b[1]_PORT_B_address_reg = DFFE(LD1_q_b[1]_PORT_B_address, LD1_q_b[1]_clock_1, , , );
|
| 3669 |
|
|
LD1_q_b[1]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 3670 |
|
|
LD1_q_b[1]_PORT_A_write_enable_reg = DFFE(LD1_q_b[1]_PORT_A_write_enable, LD1_q_b[1]_clock_0, , , );
|
| 3671 |
|
|
LD1_q_b[1]_PORT_B_read_enable = VCC;
|
| 3672 |
|
|
LD1_q_b[1]_PORT_B_read_enable_reg = DFFE(LD1_q_b[1]_PORT_B_read_enable, LD1_q_b[1]_clock_1, , , );
|
| 3673 |
|
|
LD1_q_b[1]_clock_0 = E1__clk0;
|
| 3674 |
|
|
LD1_q_b[1]_clock_1 = E1__clk0;
|
| 3675 |
|
|
LD1_q_b[1]_PORT_B_data_out = MEMORY(LD1_q_b[1]_PORT_A_data_in_reg, , LD1_q_b[1]_PORT_A_address_reg, LD1_q_b[1]_PORT_B_address_reg, LD1_q_b[1]_PORT_A_write_enable_reg, LD1_q_b[1]_PORT_B_read_enable_reg, , , LD1_q_b[1]_clock_0, LD1_q_b[1]_clock_1, , , , );
|
| 3676 |
|
|
LD1_q_b[1] = LD1_q_b[1]_PORT_B_data_out[0];
|
| 3677 |
|
|
|
| 3678 |
|
|
|
| 3679 |
|
|
--UD1_shift_out_89_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[1]
|
| 3680 |
|
|
--operation mode is normal
|
| 3681 |
|
|
|
| 3682 |
|
|
UD1_shift_out_89_a[1] = VD1_b_o_iv_0 & !PD1_a_o_2;
|
| 3683 |
|
|
|
| 3684 |
|
|
|
| 3685 |
|
|
--UD1_shift_out_87[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[1]
|
| 3686 |
|
|
--operation mode is normal
|
| 3687 |
|
|
|
| 3688 |
|
|
UD1_shift_out_87[1] = PD1_a_o_0 & UD1_shift_out_80[1] # !PD1_a_o_0 & UD1_shift_out_82[1];
|
| 3689 |
|
|
|
| 3690 |
|
|
|
| 3691 |
|
|
--UD1_shift_out_86_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_1
|
| 3692 |
|
|
--operation mode is normal
|
| 3693 |
|
|
|
| 3694 |
|
|
UD1_shift_out_86_1 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[1] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[1];
|
| 3695 |
|
|
|
| 3696 |
|
|
|
| 3697 |
|
|
--UD1_shift_out_91_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_1
|
| 3698 |
|
|
--operation mode is normal
|
| 3699 |
|
|
|
| 3700 |
|
|
UD1_shift_out_91_1 = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[1] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[1];
|
| 3701 |
|
|
|
| 3702 |
|
|
|
| 3703 |
|
|
--MD1_c_0_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[1]
|
| 3704 |
|
|
--operation mode is normal
|
| 3705 |
|
|
|
| 3706 |
|
|
MD1_c_0_a[1] = VD1_un24_res & !VD1_hilo_33 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_1;
|
| 3707 |
|
|
|
| 3708 |
|
|
|
| 3709 |
|
|
--TD1_alu_out_7_0_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0
|
| 3710 |
|
|
--operation mode is normal
|
| 3711 |
|
|
|
| 3712 |
|
|
TD1_alu_out_7_0_0 = TD1_m107 & !TD1_alu_out_7_0_a[1] # !TD1_m107 & TD1_alu_out_6_0[1];
|
| 3713 |
|
|
|
| 3714 |
|
|
|
| 3715 |
|
|
--K1_cntr_5_0[0] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[0]
|
| 3716 |
|
|
--operation mode is normal
|
| 3717 |
|
|
|
| 3718 |
|
|
K1_s_cntr_0__Z_qfbk = K1_s_cntr_0__Z;
|
| 3719 |
|
|
K1_cntr_5_0[0] = F1_wr_tmr_data_0_a2 & CB1_r32_o_0 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_0__Z_qfbk;
|
| 3720 |
|
|
|
| 3721 |
|
|
--K1_s_cntr_0__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_0__Z
|
| 3722 |
|
|
--operation mode is normal
|
| 3723 |
|
|
|
| 3724 |
|
|
K1_s_cntr_0__Z = DFFEAS(K1_cntr_5_0[0], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_0, , , VCC);
|
| 3725 |
|
|
|
| 3726 |
|
|
|
| 3727 |
|
|
--M1_buffer_reg_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_0
|
| 3728 |
|
|
--operation mode is normal
|
| 3729 |
|
|
|
| 3730 |
|
|
M1_buffer_reg_0_lut_out = M1_rx_sr[0];
|
| 3731 |
|
|
M1_buffer_reg_0 = DFFEAS(M1_buffer_reg_0_lut_out, E1__clk0, VCC, , C1_G_578, , , !sys_rst, );
|
| 3732 |
|
|
|
| 3733 |
|
|
|
| 3734 |
|
|
--F1_r_key2 is mips_sys:isys|mips_dvc:imips_dvc|r_key2
|
| 3735 |
|
|
--operation mode is normal
|
| 3736 |
|
|
|
| 3737 |
|
|
F1_r_key2_lut_out = key2;
|
| 3738 |
|
|
F1_r_key2 = DFFEAS(F1_r_key2_lut_out, E1__clk0, VCC, , , , , , );
|
| 3739 |
|
|
|
| 3740 |
|
|
|
| 3741 |
|
|
--F1_cmd[0] is mips_sys:isys|mips_dvc:imips_dvc|cmd[0]
|
| 3742 |
|
|
--operation mode is normal
|
| 3743 |
|
|
|
| 3744 |
|
|
F1_cmd[0]_lut_out = CB1_r32_o_0;
|
| 3745 |
|
|
F1_cmd[0] = DFFEAS(F1_cmd[0]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 3746 |
|
|
|
| 3747 |
|
|
|
| 3748 |
|
|
--UB1_dout_2_i_0[0] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[0]
|
| 3749 |
|
|
--operation mode is normal
|
| 3750 |
|
|
|
| 3751 |
|
|
UB1_dout_2_i_0[0] = !UB1_dout_2_i_0_a2_x[0] & !UB1_dout_2_i_0_a[0] & JE1_q_b[0] # !UB1_dout_2_i_o2[3];
|
| 3752 |
|
|
|
| 3753 |
|
|
|
| 3754 |
|
|
--WB5L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_0__Z|lpm_latch:U1|q[0]~56
|
| 3755 |
|
|
--operation mode is normal
|
| 3756 |
|
|
|
| 3757 |
|
|
WB5L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[0] # !UB1_un1_byte_addr_2 & WB5L1;
|
| 3758 |
|
|
|
| 3759 |
|
|
|
| 3760 |
|
|
--GD1_dout_iv_1_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[0]
|
| 3761 |
|
|
--operation mode is normal
|
| 3762 |
|
|
|
| 3763 |
|
|
GD1_dout_iv_1_a[0] = FD1_r_data_0 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !RB1_byte_addr_o_0 # !FD1_r_data_0 & !ZD1_mux_fw_1 # !RB1_byte_addr_o_0;
|
| 3764 |
|
|
|
| 3765 |
|
|
|
| 3766 |
|
|
--LD1_q_b[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[0]
|
| 3767 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 3768 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 3769 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 3770 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 3771 |
|
|
LD1_q_b[0]_PORT_A_data_in = FD1_wb_o_0;
|
| 3772 |
|
|
LD1_q_b[0]_PORT_A_data_in_reg = DFFE(LD1_q_b[0]_PORT_A_data_in, LD1_q_b[0]_clock_0, , , );
|
| 3773 |
|
|
LD1_q_b[0]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 3774 |
|
|
LD1_q_b[0]_PORT_A_address_reg = DFFE(LD1_q_b[0]_PORT_A_address, LD1_q_b[0]_clock_0, , , );
|
| 3775 |
|
|
LD1_q_b[0]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 3776 |
|
|
LD1_q_b[0]_PORT_B_address_reg = DFFE(LD1_q_b[0]_PORT_B_address, LD1_q_b[0]_clock_1, , , );
|
| 3777 |
|
|
LD1_q_b[0]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 3778 |
|
|
LD1_q_b[0]_PORT_A_write_enable_reg = DFFE(LD1_q_b[0]_PORT_A_write_enable, LD1_q_b[0]_clock_0, , , );
|
| 3779 |
|
|
LD1_q_b[0]_PORT_B_read_enable = VCC;
|
| 3780 |
|
|
LD1_q_b[0]_PORT_B_read_enable_reg = DFFE(LD1_q_b[0]_PORT_B_read_enable, LD1_q_b[0]_clock_1, , , );
|
| 3781 |
|
|
LD1_q_b[0]_clock_0 = E1__clk0;
|
| 3782 |
|
|
LD1_q_b[0]_clock_1 = E1__clk0;
|
| 3783 |
|
|
LD1_q_b[0]_PORT_B_data_out = MEMORY(LD1_q_b[0]_PORT_A_data_in_reg, , LD1_q_b[0]_PORT_A_address_reg, LD1_q_b[0]_PORT_B_address_reg, LD1_q_b[0]_PORT_A_write_enable_reg, LD1_q_b[0]_PORT_B_read_enable_reg, , , LD1_q_b[0]_clock_0, LD1_q_b[0]_clock_1, , , , );
|
| 3784 |
|
|
LD1_q_b[0] = LD1_q_b[0]_PORT_B_data_out[0];
|
| 3785 |
|
|
|
| 3786 |
|
|
|
| 3787 |
|
|
--MD1_c_1_Z[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_Z[0]
|
| 3788 |
|
|
--operation mode is normal
|
| 3789 |
|
|
|
| 3790 |
|
|
MD1_c_1_Z[0] = VD1_res_2_0 # !RC1_alu_func_o_3 & TD1_m107 & !MD1_c_1_a[0];
|
| 3791 |
|
|
|
| 3792 |
|
|
|
| 3793 |
|
|
--MD1_c_2_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_a[0]
|
| 3794 |
|
|
--operation mode is normal
|
| 3795 |
|
|
|
| 3796 |
|
|
MD1_c_2_a[0] = RC1_alu_func_o_4 & RC1_alu_func_o_0 & !VD1_b_o_iv_0 & !PD1_a_o_0 # !RC1_alu_func_o_0 & VD1_b_o_iv_0 $ PD1_a_o_0;
|
| 3797 |
|
|
|
| 3798 |
|
|
|
| 3799 |
|
|
--TD1_un1_a_add0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add0
|
| 3800 |
|
|
--operation mode is arithmetic
|
| 3801 |
|
|
|
| 3802 |
|
|
TD1_un1_a_add0_carry_eqn = TD1_un1_a_add0_start_cout;
|
| 3803 |
|
|
TD1_un1_a_add0 = PD1_a_o_0 $ TD1_un1_b_1_combout[0] $ !TD1_un1_a_add0_carry_eqn;
|
| 3804 |
|
|
|
| 3805 |
|
|
--TD1_un1_a_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_0
|
| 3806 |
|
|
--operation mode is arithmetic
|
| 3807 |
|
|
|
| 3808 |
|
|
TD1_un1_a_carry_0 = CARRY(PD1_a_o_0 & TD1_un1_b_1_combout[0] # !TD1_un1_a_add0_start_cout # !PD1_a_o_0 & TD1_un1_b_1_combout[0] & !TD1_un1_a_add0_start_cout);
|
| 3809 |
|
|
|
| 3810 |
|
|
|
| 3811 |
|
|
--UD1_shift_out_91[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[0]
|
| 3812 |
|
|
--operation mode is normal
|
| 3813 |
|
|
|
| 3814 |
|
|
UD1_shift_out_91[0] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[0] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[0];
|
| 3815 |
|
|
|
| 3816 |
|
|
|
| 3817 |
|
|
--UD1_shift_out_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[0]
|
| 3818 |
|
|
--operation mode is normal
|
| 3819 |
|
|
|
| 3820 |
|
|
UD1_shift_out_a[0] = !UD1_shift_out586 & UD1_shift_out_sn_m31_i & UD1_shift_out_86[0] # !UD1_shift_out_sn_m31_i & UD1_shift_out_87[0];
|
| 3821 |
|
|
|
| 3822 |
|
|
|
| 3823 |
|
|
--TD1_alu_out_9_a2_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_9_a2_a[0]
|
| 3824 |
|
|
--operation mode is normal
|
| 3825 |
|
|
|
| 3826 |
|
|
TD1_alu_out_9_a2_a[0] = !RC1_alu_func_o_2 & !RC1_alu_func_o_3 & !RC1_alu_func_o_1 & RC1_alu_func_o_4;
|
| 3827 |
|
|
|
| 3828 |
|
|
|
| 3829 |
|
|
--TD1_lt31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt31
|
| 3830 |
|
|
--operation mode is normal
|
| 3831 |
|
|
|
| 3832 |
|
|
TD1_lt31_carry_eqn = TD1_lt_30;
|
| 3833 |
|
|
TD1_lt31 = PD1_a_o_31 & VD1_b_o_iv_31 & TD1_lt31_carry_eqn # !PD1_a_o_31 & VD1_b_o_iv_31 # TD1_lt31_carry_eqn;
|
| 3834 |
|
|
|
| 3835 |
|
|
|
| 3836 |
|
|
--TD1_sum_add32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_add32
|
| 3837 |
|
|
--operation mode is normal
|
| 3838 |
|
|
|
| 3839 |
|
|
TD1_sum_add32_carry_eqn = TD1_sum_carry_31;
|
| 3840 |
|
|
TD1_sum_add32 = VD1_b_o_iv_31 $ PD1_a_o_31 $ TD1_sum_add32_carry_eqn;
|
| 3841 |
|
|
|
| 3842 |
|
|
|
| 3843 |
|
|
--Y1_q_b[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[3]
|
| 3844 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 3845 |
|
|
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
|
| 3846 |
|
|
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
|
| 3847 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 3848 |
|
|
Y1_q_b[3]_PORT_A_data_in = CB1_r32_o_3;
|
| 3849 |
|
|
Y1_q_b[3]_PORT_A_data_in_reg = DFFE(Y1_q_b[3]_PORT_A_data_in, Y1_q_b[3]_clock_0, , , );
|
| 3850 |
|
|
Y1_q_b[3]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
|
| 3851 |
|
|
Y1_q_b[3]_PORT_A_address_reg = DFFE(Y1_q_b[3]_PORT_A_address, Y1_q_b[3]_clock_0, , , );
|
| 3852 |
|
|
Y1_q_b[3]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
|
| 3853 |
|
|
Y1_q_b[3]_PORT_B_address_reg = DFFE(Y1_q_b[3]_PORT_B_address, Y1_q_b[3]_clock_1, , , Y1_q_b[3]_clock_enable_1);
|
| 3854 |
|
|
Y1_q_b[3]_PORT_A_write_enable = T1_valid_wreq;
|
| 3855 |
|
|
Y1_q_b[3]_PORT_A_write_enable_reg = DFFE(Y1_q_b[3]_PORT_A_write_enable, Y1_q_b[3]_clock_0, , , );
|
| 3856 |
|
|
Y1_q_b[3]_PORT_B_read_enable = VCC;
|
| 3857 |
|
|
Y1_q_b[3]_PORT_B_read_enable_reg = DFFE(Y1_q_b[3]_PORT_B_read_enable, Y1_q_b[3]_clock_1, , , Y1_q_b[3]_clock_enable_1);
|
| 3858 |
|
|
Y1_q_b[3]_clock_0 = E1__clk0;
|
| 3859 |
|
|
Y1_q_b[3]_clock_1 = E1__clk0;
|
| 3860 |
|
|
Y1_q_b[3]_clock_enable_1 = T1_valid_rreq;
|
| 3861 |
|
|
Y1_q_b[3]_PORT_B_data_out = MEMORY(Y1_q_b[3]_PORT_A_data_in_reg, , Y1_q_b[3]_PORT_A_address_reg, Y1_q_b[3]_PORT_B_address_reg, Y1_q_b[3]_PORT_A_write_enable_reg, Y1_q_b[3]_PORT_B_read_enable_reg, , , Y1_q_b[3]_clock_0, Y1_q_b[3]_clock_1, , Y1_q_b[3]_clock_enable_1, , );
|
| 3862 |
|
|
Y1_q_b[3] = Y1_q_b[3]_PORT_B_data_out[0];
|
| 3863 |
|
|
|
| 3864 |
|
|
|
| 3865 |
|
|
--N1_tx_sr[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[4]
|
| 3866 |
|
|
--operation mode is normal
|
| 3867 |
|
|
|
| 3868 |
|
|
N1_tx_sr[4]_lut_out = N1_read_request_ff & Y1_q_b[4] # !N1_read_request_ff & N1_tx_sr[5];
|
| 3869 |
|
|
N1_tx_sr[4] = DFFEAS(N1_tx_sr[4]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );
|
| 3870 |
|
|
|
| 3871 |
|
|
|
| 3872 |
|
|
--N1_clk_ctr26_i_0_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_0
|
| 3873 |
|
|
--operation mode is normal
|
| 3874 |
|
|
|
| 3875 |
|
|
N1_clk_ctr26_i_0_0 = !N1_ua_state[6] & !N1_ua_state[1] & N1_clk_ctr26_i_0_0_a # !sys_rst;
|
| 3876 |
|
|
|
| 3877 |
|
|
|
| 3878 |
|
|
--N1_clk_ctr26_i_0_a4_0_5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a4_0_5
|
| 3879 |
|
|
--operation mode is normal
|
| 3880 |
|
|
|
| 3881 |
|
|
N1_clk_ctr26_i_0_a4_0_5 = N1_clk_ctr[3] & !N1_clk_ctr[4] & N1_clk_ctr[11] & !N1_clk_ctr[8];
|
| 3882 |
|
|
|
| 3883 |
|
|
|
| 3884 |
|
|
--N1_clk_ctr26_i_0_a4_0_6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a4_0_6
|
| 3885 |
|
|
--operation mode is normal
|
| 3886 |
|
|
|
| 3887 |
|
|
N1_clk_ctr26_i_0_a4_0_6 = !N1_clk_ctr[10] & !N1_clk_ctr[2] & N1_clk_ctr[5] & !N1_clk_ctr26_i_0_a4_0_6_a;
|
| 3888 |
|
|
|
| 3889 |
|
|
|
| 3890 |
|
|
--N1_ua_state[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[4]
|
| 3891 |
|
|
--operation mode is normal
|
| 3892 |
|
|
|
| 3893 |
|
|
N1_ua_state[4]_lut_out = N1_ua_state[3];
|
| 3894 |
|
|
N1_ua_state[4] = DFFEAS(N1_ua_state[4]_lut_out, E1__clk0, VCC, , C1_G_451_x, , , !sys_rst, );
|
| 3895 |
|
|
|
| 3896 |
|
|
|
| 3897 |
|
|
--F1_wr_tmr_data_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|wr_tmr_data_0_a2
|
| 3898 |
|
|
--operation mode is normal
|
| 3899 |
|
|
|
| 3900 |
|
|
F1_wr_tmr_data_0_a2 = AB1_r32_o_3 & F1_wr_tmr_data_0_a2_0 & F1_wr_cmd_0_a2_0;
|
| 3901 |
|
|
|
| 3902 |
|
|
|
| 3903 |
|
|
--K1_un2_w_irq_21 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_21
|
| 3904 |
|
|
--operation mode is normal
|
| 3905 |
|
|
|
| 3906 |
|
|
K1_un2_w_irq_21 = !K1_cntr_30 & !K1_cntr_31 & !K1_cntr_28 & !K1_cntr_29;
|
| 3907 |
|
|
|
| 3908 |
|
|
|
| 3909 |
|
|
--K1_un1_ld_1_a is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un1_ld_1_a
|
| 3910 |
|
|
--operation mode is normal
|
| 3911 |
|
|
|
| 3912 |
|
|
K1_un1_ld_1_a = !K1_un2_w_irq_20 # !K1_un2_w_irq_23 # !K1_un2_w_irq_22;
|
| 3913 |
|
|
|
| 3914 |
|
|
|
| 3915 |
|
|
--K1_un2_w_irq_28 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_28
|
| 3916 |
|
|
--operation mode is normal
|
| 3917 |
|
|
|
| 3918 |
|
|
K1_un2_w_irq_28 = K1_un2_w_irq_16 & K1_un2_w_irq_17 & K1_un2_w_irq_18 & K1_un2_w_irq_19;
|
| 3919 |
|
|
|
| 3920 |
|
|
|
| 3921 |
|
|
--F1_cmd[8] is mips_sys:isys|mips_dvc:imips_dvc|cmd[8]
|
| 3922 |
|
|
--operation mode is normal
|
| 3923 |
|
|
|
| 3924 |
|
|
F1_cmd[8]_lut_out = CB1_r32_o_8;
|
| 3925 |
|
|
F1_cmd[8] = DFFEAS(F1_cmd[8]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 3926 |
|
|
|
| 3927 |
|
|
|
| 3928 |
|
|
--M1_rx_sr[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[7]
|
| 3929 |
|
|
--operation mode is normal
|
| 3930 |
|
|
|
| 3931 |
|
|
M1_rx_sr[7]_lut_out = M1_rxq1;
|
| 3932 |
|
|
M1_rx_sr[7] = DFFEAS(M1_rx_sr[7]_lut_out, E1__clk0, VCC, , C1_G_570_x, , , !sys_rst, );
|
| 3933 |
|
|
|
| 3934 |
|
|
|
| 3935 |
|
|
--C1_G_578 is mips_sys:isys|G_578
|
| 3936 |
|
|
--operation mode is normal
|
| 3937 |
|
|
|
| 3938 |
|
|
C1_G_578 = C1_G_578_a & M1_un1_clk_ctr_equ0_0_a2 & M1_un1_clk_ctr_equ0_0_a2_0 # !sys_rst;
|
| 3939 |
|
|
|
| 3940 |
|
|
|
| 3941 |
|
|
--F1_dout_0_0_a3_5_3[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_5_3[0]
|
| 3942 |
|
|
--operation mode is normal
|
| 3943 |
|
|
|
| 3944 |
|
|
F1_dout_0_0_a3_5_3[0] = !AB1_r32_o_0 & !AB1_r32_o_2 & AB1_r32_o_3 & F1_dout_0_0_a3_5_3_a[0];
|
| 3945 |
|
|
|
| 3946 |
|
|
|
| 3947 |
|
|
--GE1_q_a[7] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[7]
|
| 3948 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 3949 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 3950 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 3951 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 3952 |
|
|
GE1_q_a[7]_PORT_A_data_in = ~GND;
|
| 3953 |
|
|
GE1_q_a[7]_PORT_A_data_in_reg = DFFE(GE1_q_a[7]_PORT_A_data_in, GE1_q_a[7]_clock_0, , , );
|
| 3954 |
|
|
GE1_q_a[7]_PORT_B_data_in = CB1_dout_2_7;
|
| 3955 |
|
|
GE1_q_a[7]_PORT_B_data_in_reg = DFFE(GE1_q_a[7]_PORT_B_data_in, GE1_q_a[7]_clock_0, , , );
|
| 3956 |
|
|
GE1_q_a[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 3957 |
|
|
GE1_q_a[7]_PORT_A_address_reg = DFFE(GE1_q_a[7]_PORT_A_address, GE1_q_a[7]_clock_0, , , );
|
| 3958 |
|
|
GE1_q_a[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 3959 |
|
|
GE1_q_a[7]_PORT_B_address_reg = DFFE(GE1_q_a[7]_PORT_B_address, GE1_q_a[7]_clock_0, , , );
|
| 3960 |
|
|
GE1_q_a[7]_PORT_A_write_enable = GND;
|
| 3961 |
|
|
GE1_q_a[7]_PORT_A_write_enable_reg = DFFE(GE1_q_a[7]_PORT_A_write_enable, GE1_q_a[7]_clock_0, , , );
|
| 3962 |
|
|
GE1_q_a[7]_PORT_B_write_enable = WB1L2;
|
| 3963 |
|
|
GE1_q_a[7]_PORT_B_write_enable_reg = DFFE(GE1_q_a[7]_PORT_B_write_enable, GE1_q_a[7]_clock_0, , , );
|
| 3964 |
|
|
GE1_q_a[7]_clock_0 = E1__clk0;
|
| 3965 |
|
|
GE1_q_a[7]_PORT_A_data_out = MEMORY(GE1_q_a[7]_PORT_A_data_in_reg, GE1_q_a[7]_PORT_B_data_in_reg, GE1_q_a[7]_PORT_A_address_reg, GE1_q_a[7]_PORT_B_address_reg, GE1_q_a[7]_PORT_A_write_enable_reg, GE1_q_a[7]_PORT_B_write_enable_reg, , , GE1_q_a[7]_clock_0, , , , , );
|
| 3966 |
|
|
GE1_q_a[7] = GE1_q_a[7]_PORT_A_data_out[0];
|
| 3967 |
|
|
|
| 3968 |
|
|
--GE1_q_b[7] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[7]
|
| 3969 |
|
|
GE1_q_b[7]_PORT_A_data_in = ~GND;
|
| 3970 |
|
|
GE1_q_b[7]_PORT_A_data_in_reg = DFFE(GE1_q_b[7]_PORT_A_data_in, GE1_q_b[7]_clock_0, , , );
|
| 3971 |
|
|
GE1_q_b[7]_PORT_B_data_in = CB1_dout_2_7;
|
| 3972 |
|
|
GE1_q_b[7]_PORT_B_data_in_reg = DFFE(GE1_q_b[7]_PORT_B_data_in, GE1_q_b[7]_clock_0, , , );
|
| 3973 |
|
|
GE1_q_b[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 3974 |
|
|
GE1_q_b[7]_PORT_A_address_reg = DFFE(GE1_q_b[7]_PORT_A_address, GE1_q_b[7]_clock_0, , , );
|
| 3975 |
|
|
GE1_q_b[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 3976 |
|
|
GE1_q_b[7]_PORT_B_address_reg = DFFE(GE1_q_b[7]_PORT_B_address, GE1_q_b[7]_clock_0, , , );
|
| 3977 |
|
|
GE1_q_b[7]_PORT_A_write_enable = GND;
|
| 3978 |
|
|
GE1_q_b[7]_PORT_A_write_enable_reg = DFFE(GE1_q_b[7]_PORT_A_write_enable, GE1_q_b[7]_clock_0, , , );
|
| 3979 |
|
|
GE1_q_b[7]_PORT_B_write_enable = WB1L2;
|
| 3980 |
|
|
GE1_q_b[7]_PORT_B_write_enable_reg = DFFE(GE1_q_b[7]_PORT_B_write_enable, GE1_q_b[7]_clock_0, , , );
|
| 3981 |
|
|
GE1_q_b[7]_clock_0 = E1__clk0;
|
| 3982 |
|
|
GE1_q_b[7]_PORT_B_data_out = MEMORY(GE1_q_b[7]_PORT_A_data_in_reg, GE1_q_b[7]_PORT_B_data_in_reg, GE1_q_b[7]_PORT_A_address_reg, GE1_q_b[7]_PORT_B_address_reg, GE1_q_b[7]_PORT_A_write_enable_reg, GE1_q_b[7]_PORT_B_write_enable_reg, , , GE1_q_b[7]_clock_0, , , , , );
|
| 3983 |
|
|
GE1_q_b[7] = GE1_q_b[7]_PORT_B_data_out[0];
|
| 3984 |
|
|
|
| 3985 |
|
|
|
| 3986 |
|
|
--UB1_dout_2_i_i_0[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_0[7]
|
| 3987 |
|
|
--operation mode is normal
|
| 3988 |
|
|
|
| 3989 |
|
|
UB1_dout_2_i_i_0[7] = GE1_q_b[7] & RB1_byte_addr_o_1 & RB1_byte_addr_o_0 # UB1_dout_2_i_i_0_a[7];
|
| 3990 |
|
|
|
| 3991 |
|
|
|
| 3992 |
|
|
--UB1_dout_2_i_i_a3_1[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3_1[7]
|
| 3993 |
|
|
--operation mode is normal
|
| 3994 |
|
|
|
| 3995 |
|
|
UB1_dout_2_i_i_a3_1[7] = RB1_ctl_o_1 & RB1_ctl_o_2 & UB1_dout_2_i_i_o3_0[7];
|
| 3996 |
|
|
|
| 3997 |
|
|
|
| 3998 |
|
|
--UB1_dout_2_i_i_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a[7]
|
| 3999 |
|
|
--operation mode is normal
|
| 4000 |
|
|
|
| 4001 |
|
|
UB1_dout_2_i_i_a[7] = !UB1_dout_2_i_i_a2_2[7] & !UB1_dout_2_i_i_a2_1[7] & !UB1_dout_2_i_i_o2_0[7] # !JE1_q_b[7];
|
| 4002 |
|
|
|
| 4003 |
|
|
|
| 4004 |
|
|
--RB1_ctl_o_3 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|ctl_o_3
|
| 4005 |
|
|
--operation mode is normal
|
| 4006 |
|
|
|
| 4007 |
|
|
RB1_ctl_o_3_lut_out = QC1_dmem_ctl_o_3 & !AB1_c_29;
|
| 4008 |
|
|
RB1_ctl_o_3 = DFFEAS(RB1_ctl_o_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 4009 |
|
|
|
| 4010 |
|
|
|
| 4011 |
|
|
--RB1_ctl_o_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|ctl_o_0
|
| 4012 |
|
|
--operation mode is normal
|
| 4013 |
|
|
|
| 4014 |
|
|
RB1_ctl_o_0_lut_out = QC1_dmem_ctl_o_0 & !AB1_c_29;
|
| 4015 |
|
|
RB1_ctl_o_0 = DFFEAS(RB1_ctl_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 4016 |
|
|
|
| 4017 |
|
|
|
| 4018 |
|
|
--RB1_ctl_o_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|ctl_o_1
|
| 4019 |
|
|
--operation mode is normal
|
| 4020 |
|
|
|
| 4021 |
|
|
RB1_ctl_o_1_lut_out = QC1_dmem_ctl_o_1 & !AB1_c_29;
|
| 4022 |
|
|
RB1_ctl_o_1 = DFFEAS(RB1_ctl_o_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 4023 |
|
|
|
| 4024 |
|
|
|
| 4025 |
|
|
--RB1_ctl_o_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|ctl_o_2
|
| 4026 |
|
|
--operation mode is normal
|
| 4027 |
|
|
|
| 4028 |
|
|
RB1_ctl_o_2_lut_out = QC1_dmem_ctl_o_2 & !AB1_c_29;
|
| 4029 |
|
|
RB1_ctl_o_2 = DFFEAS(RB1_ctl_o_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 4030 |
|
|
|
| 4031 |
|
|
|
| 4032 |
|
|
--KC1_wb_mux_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr_cls:U10|wb_mux_ctl_o_0
|
| 4033 |
|
|
--operation mode is normal
|
| 4034 |
|
|
|
| 4035 |
|
|
KC1_wb_mux_ctl_o_0_lut_out = WB56L1;
|
| 4036 |
|
|
KC1_wb_mux_ctl_o_0 = DFFEAS(KC1_wb_mux_ctl_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4037 |
|
|
|
| 4038 |
|
|
|
| 4039 |
|
|
--FD1_r_wren is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wren
|
| 4040 |
|
|
--operation mode is normal
|
| 4041 |
|
|
|
| 4042 |
|
|
FD1_r_wren_lut_out = MC1_wb_we_o_0;
|
| 4043 |
|
|
FD1_r_wren = DFFEAS(FD1_r_wren_lut_out, E1__clk0, VCC, , , , , , );
|
| 4044 |
|
|
|
| 4045 |
|
|
|
| 4046 |
|
|
--FD1_un23_qb_i_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un23_qb_i_0_a2
|
| 4047 |
|
|
--operation mode is normal
|
| 4048 |
|
|
|
| 4049 |
|
|
FD1_un23_qb_i_0_a2 = !FD1_r_rdaddress_b[4] & !FD1_r_rdaddress_b[0] & !FD1_r_rdaddress_b[1] & FD1_un23_qb_i_0_a2_a;
|
| 4050 |
|
|
|
| 4051 |
|
|
|
| 4052 |
|
|
--FD1_un14_qb_NE is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qb_NE
|
| 4053 |
|
|
--operation mode is normal
|
| 4054 |
|
|
|
| 4055 |
|
|
FD1_un14_qb_NE = FD1_un14_qb_NE_1 # FD1_un14_qb_NE_a # FD1_r_wraddress[4] $ FD1_r_rdaddress_b[4];
|
| 4056 |
|
|
|
| 4057 |
|
|
|
| 4058 |
|
|
--ZD1_un32_mux_fw is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un32_mux_fw
|
| 4059 |
|
|
--operation mode is normal
|
| 4060 |
|
|
|
| 4061 |
|
|
ZD1_un32_mux_fw = !ZD1_mux_fw_1 & WD1_un30_mux_fw # ZD1_un17_mux_fw_NE # !MC1_wb_we_o_0;
|
| 4062 |
|
|
|
| 4063 |
|
|
|
| 4064 |
|
|
--FD1_N_16_i_0_s2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_16_i_0_s2
|
| 4065 |
|
|
--operation mode is normal
|
| 4066 |
|
|
|
| 4067 |
|
|
FD1_N_16_i_0_s2 = FD1_r_wren & !FD1_un23_qb_i_0_a2 & !FD1_un14_qb_NE & ZD1_un32_mux_fw;
|
| 4068 |
|
|
|
| 4069 |
|
|
|
| 4070 |
|
|
--FD1_r_rdaddress_b_0_x[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[0]
|
| 4071 |
|
|
--operation mode is normal
|
| 4072 |
|
|
|
| 4073 |
|
|
FD1_r_rdaddress_b_0_x[0] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[0] # !AD1_CurrState_Sreg0_2 & JE1_q_a[0];
|
| 4074 |
|
|
|
| 4075 |
|
|
|
| 4076 |
|
|
--FD1_r_rdaddress_b_0_x[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[1]
|
| 4077 |
|
|
--operation mode is normal
|
| 4078 |
|
|
|
| 4079 |
|
|
FD1_r_rdaddress_b_0_x[1] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[1] # !AD1_CurrState_Sreg0_2 & JE1_q_a[1];
|
| 4080 |
|
|
|
| 4081 |
|
|
|
| 4082 |
|
|
--FD1_r_rdaddress_b_0_x[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[2]
|
| 4083 |
|
|
--operation mode is normal
|
| 4084 |
|
|
|
| 4085 |
|
|
FD1_r_rdaddress_b_0_x[2] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[2] # !AD1_CurrState_Sreg0_2 & JE1_q_a[2];
|
| 4086 |
|
|
|
| 4087 |
|
|
|
| 4088 |
|
|
--FD1_r_rdaddress_b_0_x[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[3]
|
| 4089 |
|
|
--operation mode is normal
|
| 4090 |
|
|
|
| 4091 |
|
|
FD1_r_rdaddress_b_0_x[3] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[3] # !AD1_CurrState_Sreg0_2 & JE1_q_a[3];
|
| 4092 |
|
|
|
| 4093 |
|
|
|
| 4094 |
|
|
--FD1_r_rdaddress_b_0_x[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[4]
|
| 4095 |
|
|
--operation mode is normal
|
| 4096 |
|
|
|
| 4097 |
|
|
FD1_r_rdaddress_b_0_x[4] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[4] # !AD1_CurrState_Sreg0_2 & JE1_q_a[4];
|
| 4098 |
|
|
|
| 4099 |
|
|
|
| 4100 |
|
|
--ZD1_un17_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un17_mux_fw_NE_1
|
| 4101 |
|
|
--operation mode is normal
|
| 4102 |
|
|
|
| 4103 |
|
|
ZD1_un17_mux_fw_NE_1 = ED1_r32_o_17 & ED1_r32_o_16 $ NB1_r5_o_0 # !NB1_r5_o_1 # !ED1_r32_o_17 & NB1_r5_o_1 # ED1_r32_o_16 $ NB1_r5_o_0;
|
| 4104 |
|
|
|
| 4105 |
|
|
|
| 4106 |
|
|
--ZD1_un17_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un17_mux_fw_NE_a
|
| 4107 |
|
|
--operation mode is normal
|
| 4108 |
|
|
|
| 4109 |
|
|
ZD1_un17_mux_fw_NE_a = ED1_r32_o_18 & ED1_r32_o_19 $ NB1_r5_o_3 # !NB1_r5_o_2 # !ED1_r32_o_18 & NB1_r5_o_2 # ED1_r32_o_19 $ NB1_r5_o_3;
|
| 4110 |
|
|
|
| 4111 |
|
|
|
| 4112 |
|
|
--ZD1_mux_fw_1_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|mux_fw_1_a
|
| 4113 |
|
|
--operation mode is normal
|
| 4114 |
|
|
|
| 4115 |
|
|
ZD1_mux_fw_1_a = ED1_r32_o_20 $ MB1_r5_o_4 # !XC1_wb_we_o_0;
|
| 4116 |
|
|
|
| 4117 |
|
|
|
| 4118 |
|
|
--ZD1_un1_mux_fw_NE_2 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un1_mux_fw_NE_2
|
| 4119 |
|
|
--operation mode is normal
|
| 4120 |
|
|
|
| 4121 |
|
|
ZD1_un1_mux_fw_NE_2 = ED1_r32_o_19 & ED1_r32_o_18 $ MB1_r5_o_2 # !MB1_r5_o_3 # !ED1_r32_o_19 & MB1_r5_o_3 # ED1_r32_o_18 $ MB1_r5_o_2;
|
| 4122 |
|
|
|
| 4123 |
|
|
|
| 4124 |
|
|
--ZD1_un1_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un1_mux_fw_NE_1
|
| 4125 |
|
|
--operation mode is normal
|
| 4126 |
|
|
|
| 4127 |
|
|
ZD1_un1_mux_fw_NE_1 = ED1_r32_o_17 & ED1_r32_o_16 $ MB1_r5_o_0 # !MB1_r5_o_1 # !ED1_r32_o_17 & MB1_r5_o_1 # ED1_r32_o_16 $ MB1_r5_o_0;
|
| 4128 |
|
|
|
| 4129 |
|
|
|
| 4130 |
|
|
--TD1_alu_out_9_a2_0_1_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_9_a2_0_1_0
|
| 4131 |
|
|
--operation mode is normal
|
| 4132 |
|
|
|
| 4133 |
|
|
TD1_alu_out_9_a2_0_1_0 = !RC1_alu_func_o_2 & !RC1_alu_func_o_3;
|
| 4134 |
|
|
|
| 4135 |
|
|
|
| 4136 |
|
|
--VD1_b_o_iv_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_9
|
| 4137 |
|
|
--operation mode is normal
|
| 4138 |
|
|
|
| 4139 |
|
|
VD1_b_o_iv_9 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[9] & !G1_BUS15471_i_m[9] & AB1_r32_o_7 # !QD1_b_o_0_sqmuxa;
|
| 4140 |
|
|
|
| 4141 |
|
|
--VD1_op2_reged[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[9]
|
| 4142 |
|
|
--operation mode is normal
|
| 4143 |
|
|
|
| 4144 |
|
|
VD1_op2_reged[9] = DFFEAS(VD1_b_o_iv_9, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 4145 |
|
|
|
| 4146 |
|
|
|
| 4147 |
|
|
--UD1_shift_out_87_d[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[7]
|
| 4148 |
|
|
--operation mode is normal
|
| 4149 |
|
|
|
| 4150 |
|
|
UD1_shift_out_87_d[7] = PD1_a_o_0 & UD1_shift_out_80[7] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[7];
|
| 4151 |
|
|
|
| 4152 |
|
|
|
| 4153 |
|
|
--VD1_b_o_iv_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_6
|
| 4154 |
|
|
--operation mode is normal
|
| 4155 |
|
|
|
| 4156 |
|
|
VD1_b_o_iv_6 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[6] & !G1_BUS15471_i_m[6] & AB1_r32_o_4 # !QD1_b_o_0_sqmuxa;
|
| 4157 |
|
|
|
| 4158 |
|
|
--VD1_op2_reged[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[6]
|
| 4159 |
|
|
--operation mode is normal
|
| 4160 |
|
|
|
| 4161 |
|
|
VD1_op2_reged[6] = DFFEAS(VD1_b_o_iv_6, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 4162 |
|
|
|
| 4163 |
|
|
|
| 4164 |
|
|
--UD1_shift_out_85_d[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[7]
|
| 4165 |
|
|
--operation mode is normal
|
| 4166 |
|
|
|
| 4167 |
|
|
UD1_shift_out_85_d[7] = PD1_a_o_2 & UD1_shift_out_43[31] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[7];
|
| 4168 |
|
|
|
| 4169 |
|
|
|
| 4170 |
|
|
--UD1_shift_out_sn_m25_0_a5_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0_a5_1
|
| 4171 |
|
|
--operation mode is normal
|
| 4172 |
|
|
|
| 4173 |
|
|
UD1_shift_out_sn_m25_0_a5_1 = !UD1_shift_out588 & !UD1_shift_out587 & !UD1_shift_out586;
|
| 4174 |
|
|
|
| 4175 |
|
|
|
| 4176 |
|
|
--PD1_a_o_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[2]
|
| 4177 |
|
|
--operation mode is normal
|
| 4178 |
|
|
|
| 4179 |
|
|
PD1_a_o_a[2] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_2 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_2;
|
| 4180 |
|
|
|
| 4181 |
|
|
|
| 4182 |
|
|
--PD1_a_o_3_Z[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[2]
|
| 4183 |
|
|
--operation mode is normal
|
| 4184 |
|
|
|
| 4185 |
|
|
PD1_a_o_3_Z[2] = PD1_a_o_3_s[0] & SD1_r32_o_2 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[2];
|
| 4186 |
|
|
|
| 4187 |
|
|
|
| 4188 |
|
|
--RD1_a_o_a_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|a_o_a_1
|
| 4189 |
|
|
--operation mode is normal
|
| 4190 |
|
|
|
| 4191 |
|
|
RD1_r32_o_1__Z_qfbk = RD1_r32_o_1__Z;
|
| 4192 |
|
|
RD1_a_o_a_1 = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_1 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_1__Z_qfbk;
|
| 4193 |
|
|
|
| 4194 |
|
|
--RD1_r32_o_1__Z is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_1__Z
|
| 4195 |
|
|
--operation mode is normal
|
| 4196 |
|
|
|
| 4197 |
|
|
RD1_r32_o_1__Z = DFFEAS(RD1_a_o_a_1, E1__clk0, VCC, , , KB1_r32_o_1, , , VCC);
|
| 4198 |
|
|
|
| 4199 |
|
|
|
| 4200 |
|
|
--PD1_a_o_3_Z[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[1]
|
| 4201 |
|
|
--operation mode is normal
|
| 4202 |
|
|
|
| 4203 |
|
|
PD1_a_o_3_Z[1] = PD1_a_o_3_s[0] & SD1_r32_o_1 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[1];
|
| 4204 |
|
|
|
| 4205 |
|
|
|
| 4206 |
|
|
--RD1_a_o_a_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|a_o_a_0
|
| 4207 |
|
|
--operation mode is normal
|
| 4208 |
|
|
|
| 4209 |
|
|
RD1_r32_o_0__Z_qfbk = RD1_r32_o_0__Z;
|
| 4210 |
|
|
RD1_a_o_a_0 = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_0 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0__Z_qfbk;
|
| 4211 |
|
|
|
| 4212 |
|
|
--RD1_r32_o_0__Z is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0__Z
|
| 4213 |
|
|
--operation mode is normal
|
| 4214 |
|
|
|
| 4215 |
|
|
RD1_r32_o_0__Z = DFFEAS(RD1_a_o_a_0, E1__clk0, VCC, , , KB1_r32_o_0, , , VCC);
|
| 4216 |
|
|
|
| 4217 |
|
|
|
| 4218 |
|
|
--PD1_a_o_3_Z[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[0]
|
| 4219 |
|
|
--operation mode is normal
|
| 4220 |
|
|
|
| 4221 |
|
|
PD1_a_o_3_Z[0] = PD1_a_o_3_s[0] & SD1_r32_o_0 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[0];
|
| 4222 |
|
|
|
| 4223 |
|
|
|
| 4224 |
|
|
--UD1_shift_out_sn_b9_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_b9_0
|
| 4225 |
|
|
--operation mode is normal
|
| 4226 |
|
|
|
| 4227 |
|
|
UD1_shift_out_sn_b9_0 = !PD1_a_o_4 # !UD1_shift_out588;
|
| 4228 |
|
|
|
| 4229 |
|
|
|
| 4230 |
|
|
--UD1_shift_out_86_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[7]
|
| 4231 |
|
|
--operation mode is normal
|
| 4232 |
|
|
|
| 4233 |
|
|
UD1_shift_out_86_a[7] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[11] # !PD1_a_o_2 & !UD1_shift_out_79[15] # !UD1_shift_out587 & !UD1_shift_out_79[11];
|
| 4234 |
|
|
|
| 4235 |
|
|
|
| 4236 |
|
|
--UD1_shift_out_74[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[7]
|
| 4237 |
|
|
--operation mode is normal
|
| 4238 |
|
|
|
| 4239 |
|
|
UD1_shift_out_74[7] = PD1_a_o_3 & !UD1_shift_out_74_a[7] # !PD1_a_o_3 & UD1_shift_out_74_a[7] & UD1_shift_out_79[15] # !UD1_shift_out_74_a[7] & UD1_shift_out_79[19];
|
| 4240 |
|
|
|
| 4241 |
|
|
|
| 4242 |
|
|
--UD1_shift_out_sn_m25_0_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0_a
|
| 4243 |
|
|
--operation mode is normal
|
| 4244 |
|
|
|
| 4245 |
|
|
UD1_shift_out_sn_m25_0_a = !UD1_shift_out_sn_m25_0_a5_1 & UD1_shift_out588 # PD1_a_o_4 # PD1_a_o_3;
|
| 4246 |
|
|
|
| 4247 |
|
|
|
| 4248 |
|
|
--UD1_shift_out_sn_m17_0_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m17_0_a2
|
| 4249 |
|
|
--operation mode is normal
|
| 4250 |
|
|
|
| 4251 |
|
|
UD1_shift_out_sn_m17_0_a2 = !PD1_a_o_4 & !PD1_a_o_2;
|
| 4252 |
|
|
|
| 4253 |
|
|
|
| 4254 |
|
|
--UD1_shift_out_sn_m25_0_a5_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0_a5_0
|
| 4255 |
|
|
--operation mode is normal
|
| 4256 |
|
|
|
| 4257 |
|
|
UD1_shift_out_sn_m25_0_a5_0 = !UD1_shift_out588 & !UD1_shift_out586 & PD1_a_o_4 & UD1_shift_out_sn_m25_0_o2;
|
| 4258 |
|
|
|
| 4259 |
|
|
|
| 4260 |
|
|
--UD1_shift_out_91_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[7]
|
| 4261 |
|
|
--operation mode is normal
|
| 4262 |
|
|
|
| 4263 |
|
|
UD1_shift_out_91_a[7] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_7 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[7];
|
| 4264 |
|
|
|
| 4265 |
|
|
|
| 4266 |
|
|
--UD1_shift_out_76[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[7]
|
| 4267 |
|
|
--operation mode is normal
|
| 4268 |
|
|
|
| 4269 |
|
|
UD1_shift_out_76[7] = UD1_shift_out587 & UD1_shift_out_76_a[7] & UD1_shift_out_79[19] # !PD1_a_o_2;
|
| 4270 |
|
|
|
| 4271 |
|
|
|
| 4272 |
|
|
--UD1_shift_out_sn_m17_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m17_0
|
| 4273 |
|
|
--operation mode is normal
|
| 4274 |
|
|
|
| 4275 |
|
|
UD1_shift_out_sn_m17_0 = UD1_shift_out587 & UD1_shift_out_sn_m17_0_a2 # !UD1_shift_out587 & UD1_shift_out588 # UD1_shift_out586;
|
| 4276 |
|
|
|
| 4277 |
|
|
|
| 4278 |
|
|
--VD1_hilo_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_7
|
| 4279 |
|
|
--operation mode is normal
|
| 4280 |
|
|
|
| 4281 |
|
|
VD1_hilo_7_lut_out = VD1_hilo_37_iv_0[7] # VD1_hilo25 & VD1_hilo_8_Z[7] # !VD1_hilo_37_iv_a[7];
|
| 4282 |
|
|
VD1_hilo_7 = DFFEAS(VD1_hilo_7_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 4283 |
|
|
|
| 4284 |
|
|
|
| 4285 |
|
|
--VD1_hilo_39 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_39
|
| 4286 |
|
|
--operation mode is normal
|
| 4287 |
|
|
|
| 4288 |
|
|
VD1_hilo_39_lut_out = !VD1_hilo_37_iv_0_5[39] & !VD1_hilo_37_iv_0_4[39] & !VD1_hilo_37_iv_0_a[39] & !VD1_hilo_37_iv_0_a2[39];
|
| 4289 |
|
|
VD1_hilo_39 = DFFEAS(VD1_hilo_39_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 4290 |
|
|
|
| 4291 |
|
|
|
| 4292 |
|
|
--PD1_a_o_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_7
|
| 4293 |
|
|
--operation mode is normal
|
| 4294 |
|
|
|
| 4295 |
|
|
PD1_a_o_7 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[7] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[7];
|
| 4296 |
|
|
|
| 4297 |
|
|
|
| 4298 |
|
|
--TD1_m4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m4
|
| 4299 |
|
|
--operation mode is normal
|
| 4300 |
|
|
|
| 4301 |
|
|
TD1_m4 = !RC1_alu_func_o_1 & RC1_alu_func_o_0 & TD1_alu_out_sn_m14_0_0;
|
| 4302 |
|
|
|
| 4303 |
|
|
|
| 4304 |
|
|
--TD1_m11_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m11_a
|
| 4305 |
|
|
--operation mode is normal
|
| 4306 |
|
|
|
| 4307 |
|
|
TD1_m11_a = VD1_b_o_iv_7 & !TD1_m9 & PD1_a_o_7 # !VD1_b_o_iv_7 & !PD1_a_o_7 # !TD1_m5;
|
| 4308 |
|
|
|
| 4309 |
|
|
|
| 4310 |
|
|
--TD1_m7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m7
|
| 4311 |
|
|
--operation mode is normal
|
| 4312 |
|
|
|
| 4313 |
|
|
TD1_m7 = TD1_alu_out_7_0_0_o3_0 & !TD1_m5 # !TD1_alu_out_7_0_0_o3_0 & !TD1_alu_out_sn_m14_0_0 # !RC1_alu_func_o_0;
|
| 4314 |
|
|
|
| 4315 |
|
|
|
| 4316 |
|
|
--TD1_un1_a_add7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add7
|
| 4317 |
|
|
--operation mode is arithmetic
|
| 4318 |
|
|
|
| 4319 |
|
|
TD1_un1_a_add7_carry_eqn = TD1_un1_a_carry_6;
|
| 4320 |
|
|
TD1_un1_a_add7 = PD1_a_o_7 $ TD1_un1_b_1_combout[7] $ TD1_un1_a_add7_carry_eqn;
|
| 4321 |
|
|
|
| 4322 |
|
|
--TD1_un1_a_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_7
|
| 4323 |
|
|
--operation mode is arithmetic
|
| 4324 |
|
|
|
| 4325 |
|
|
TD1_un1_a_carry_7 = CARRY(PD1_a_o_7 & !TD1_un1_b_1_combout[7] & !TD1_un1_a_carry_6 # !PD1_a_o_7 & !TD1_un1_a_carry_6 # !TD1_un1_b_1_combout[7]);
|
| 4326 |
|
|
|
| 4327 |
|
|
|
| 4328 |
|
|
--LB1_r5_o_4 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_4
|
| 4329 |
|
|
--operation mode is normal
|
| 4330 |
|
|
|
| 4331 |
|
|
LB1_r5_o_4_lut_out = EC1_rd_sel_o_0 & ED1_r32_o_15 # EC1_rd_sel_o_1 # !EC1_rd_sel_o_0 & ED1_r32_o_20 & EC1_rd_sel_o_1;
|
| 4332 |
|
|
LB1_r5_o_4 = DFFEAS(LB1_r5_o_4_lut_out, E1__clk0, VCC, , , , , , );
|
| 4333 |
|
|
|
| 4334 |
|
|
|
| 4335 |
|
|
--LB1_r5_o_3 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_3
|
| 4336 |
|
|
--operation mode is normal
|
| 4337 |
|
|
|
| 4338 |
|
|
LB1_r5_o_3_lut_out = EC1_rd_sel_o_0 & ED1_r32_o_14 # EC1_rd_sel_o_1 # !EC1_rd_sel_o_0 & ED1_r32_o_19 & EC1_rd_sel_o_1;
|
| 4339 |
|
|
LB1_r5_o_3 = DFFEAS(LB1_r5_o_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 4340 |
|
|
|
| 4341 |
|
|
|
| 4342 |
|
|
--ED1_r32_o_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_19
|
| 4343 |
|
|
--operation mode is normal
|
| 4344 |
|
|
|
| 4345 |
|
|
ED1_r32_o_19_lut_out = JE1_q_a[3];
|
| 4346 |
|
|
ED1_r32_o_19 = DFFEAS(ED1_r32_o_19_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4347 |
|
|
|
| 4348 |
|
|
|
| 4349 |
|
|
--LB1_r5_o_2 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_2
|
| 4350 |
|
|
--operation mode is normal
|
| 4351 |
|
|
|
| 4352 |
|
|
LB1_r5_o_2_lut_out = EC1_rd_sel_o_0 & ED1_r32_o_13 # EC1_rd_sel_o_1 # !EC1_rd_sel_o_0 & ED1_r32_o_18 & EC1_rd_sel_o_1;
|
| 4353 |
|
|
LB1_r5_o_2 = DFFEAS(LB1_r5_o_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 4354 |
|
|
|
| 4355 |
|
|
|
| 4356 |
|
|
--ED1_r32_o_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_18
|
| 4357 |
|
|
--operation mode is normal
|
| 4358 |
|
|
|
| 4359 |
|
|
ED1_r32_o_18_lut_out = JE1_q_a[2];
|
| 4360 |
|
|
ED1_r32_o_18 = DFFEAS(ED1_r32_o_18_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4361 |
|
|
|
| 4362 |
|
|
|
| 4363 |
|
|
--LB1_r5_o_1 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_1
|
| 4364 |
|
|
--operation mode is normal
|
| 4365 |
|
|
|
| 4366 |
|
|
LB1_r5_o_1_lut_out = EC1_rd_sel_o_0 & ED1_r32_o_12 # EC1_rd_sel_o_1 # !EC1_rd_sel_o_0 & ED1_r32_o_17 & EC1_rd_sel_o_1;
|
| 4367 |
|
|
LB1_r5_o_1 = DFFEAS(LB1_r5_o_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 4368 |
|
|
|
| 4369 |
|
|
|
| 4370 |
|
|
--ED1_r32_o_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_17
|
| 4371 |
|
|
--operation mode is normal
|
| 4372 |
|
|
|
| 4373 |
|
|
ED1_r32_o_17_lut_out = JE1_q_a[1];
|
| 4374 |
|
|
ED1_r32_o_17 = DFFEAS(ED1_r32_o_17_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4375 |
|
|
|
| 4376 |
|
|
|
| 4377 |
|
|
--LB1_r5_o_0 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_0
|
| 4378 |
|
|
--operation mode is normal
|
| 4379 |
|
|
|
| 4380 |
|
|
LB1_r5_o_0_lut_out = EC1_rd_sel_o_0 & ED1_r32_o_11 # EC1_rd_sel_o_1 # !EC1_rd_sel_o_0 & ED1_r32_o_16 & EC1_rd_sel_o_1;
|
| 4381 |
|
|
LB1_r5_o_0 = DFFEAS(LB1_r5_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 4382 |
|
|
|
| 4383 |
|
|
|
| 4384 |
|
|
--ED1_r32_o_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_16
|
| 4385 |
|
|
--operation mode is normal
|
| 4386 |
|
|
|
| 4387 |
|
|
ED1_r32_o_16_lut_out = JE1_q_a[0];
|
| 4388 |
|
|
ED1_r32_o_16 = DFFEAS(ED1_r32_o_16_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4389 |
|
|
|
| 4390 |
|
|
|
| 4391 |
|
|
--LC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr_cls:U11|wb_we_o_0
|
| 4392 |
|
|
--operation mode is normal
|
| 4393 |
|
|
|
| 4394 |
|
|
LC1_wb_we_o_0_lut_out = WB66L1;
|
| 4395 |
|
|
LC1_wb_we_o_0 = DFFEAS(LC1_wb_we_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4396 |
|
|
|
| 4397 |
|
|
|
| 4398 |
|
|
--FC1_alu_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr_cls:U6|alu_we_o_0
|
| 4399 |
|
|
--operation mode is normal
|
| 4400 |
|
|
|
| 4401 |
|
|
FC1_alu_we_o_0_lut_out = WB24L1;
|
| 4402 |
|
|
FC1_alu_we_o_0 = DFFEAS(FC1_alu_we_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4403 |
|
|
|
| 4404 |
|
|
|
| 4405 |
|
|
--JE1_q_a[4] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[4]
|
| 4406 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 4407 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 4408 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 4409 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 4410 |
|
|
JE1_q_a[4]_PORT_A_data_in = ~GND;
|
| 4411 |
|
|
JE1_q_a[4]_PORT_A_data_in_reg = DFFE(JE1_q_a[4]_PORT_A_data_in, JE1_q_a[4]_clock_0, , , );
|
| 4412 |
|
|
JE1_q_a[4]_PORT_B_data_in = TB1_dout_1_4;
|
| 4413 |
|
|
JE1_q_a[4]_PORT_B_data_in_reg = DFFE(JE1_q_a[4]_PORT_B_data_in, JE1_q_a[4]_clock_0, , , );
|
| 4414 |
|
|
JE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 4415 |
|
|
JE1_q_a[4]_PORT_A_address_reg = DFFE(JE1_q_a[4]_PORT_A_address, JE1_q_a[4]_clock_0, , , );
|
| 4416 |
|
|
JE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 4417 |
|
|
JE1_q_a[4]_PORT_B_address_reg = DFFE(JE1_q_a[4]_PORT_B_address, JE1_q_a[4]_clock_0, , , );
|
| 4418 |
|
|
JE1_q_a[4]_PORT_A_write_enable = GND;
|
| 4419 |
|
|
JE1_q_a[4]_PORT_A_write_enable_reg = DFFE(JE1_q_a[4]_PORT_A_write_enable, JE1_q_a[4]_clock_0, , , );
|
| 4420 |
|
|
JE1_q_a[4]_PORT_B_write_enable = WB3L2;
|
| 4421 |
|
|
JE1_q_a[4]_PORT_B_write_enable_reg = DFFE(JE1_q_a[4]_PORT_B_write_enable, JE1_q_a[4]_clock_0, , , );
|
| 4422 |
|
|
JE1_q_a[4]_clock_0 = E1__clk0;
|
| 4423 |
|
|
JE1_q_a[4]_PORT_A_data_out = MEMORY(JE1_q_a[4]_PORT_A_data_in_reg, JE1_q_a[4]_PORT_B_data_in_reg, JE1_q_a[4]_PORT_A_address_reg, JE1_q_a[4]_PORT_B_address_reg, JE1_q_a[4]_PORT_A_write_enable_reg, JE1_q_a[4]_PORT_B_write_enable_reg, , , JE1_q_a[4]_clock_0, , , , , );
|
| 4424 |
|
|
JE1_q_a[4] = JE1_q_a[4]_PORT_A_data_out[0];
|
| 4425 |
|
|
|
| 4426 |
|
|
--JE1_q_b[4] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[4]
|
| 4427 |
|
|
JE1_q_b[4]_PORT_A_data_in = ~GND;
|
| 4428 |
|
|
JE1_q_b[4]_PORT_A_data_in_reg = DFFE(JE1_q_b[4]_PORT_A_data_in, JE1_q_b[4]_clock_0, , , );
|
| 4429 |
|
|
JE1_q_b[4]_PORT_B_data_in = TB1_dout_1_4;
|
| 4430 |
|
|
JE1_q_b[4]_PORT_B_data_in_reg = DFFE(JE1_q_b[4]_PORT_B_data_in, JE1_q_b[4]_clock_0, , , );
|
| 4431 |
|
|
JE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 4432 |
|
|
JE1_q_b[4]_PORT_A_address_reg = DFFE(JE1_q_b[4]_PORT_A_address, JE1_q_b[4]_clock_0, , , );
|
| 4433 |
|
|
JE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 4434 |
|
|
JE1_q_b[4]_PORT_B_address_reg = DFFE(JE1_q_b[4]_PORT_B_address, JE1_q_b[4]_clock_0, , , );
|
| 4435 |
|
|
JE1_q_b[4]_PORT_A_write_enable = GND;
|
| 4436 |
|
|
JE1_q_b[4]_PORT_A_write_enable_reg = DFFE(JE1_q_b[4]_PORT_A_write_enable, JE1_q_b[4]_clock_0, , , );
|
| 4437 |
|
|
JE1_q_b[4]_PORT_B_write_enable = WB3L2;
|
| 4438 |
|
|
JE1_q_b[4]_PORT_B_write_enable_reg = DFFE(JE1_q_b[4]_PORT_B_write_enable, JE1_q_b[4]_clock_0, , , );
|
| 4439 |
|
|
JE1_q_b[4]_clock_0 = E1__clk0;
|
| 4440 |
|
|
JE1_q_b[4]_PORT_B_data_out = MEMORY(JE1_q_b[4]_PORT_A_data_in_reg, JE1_q_b[4]_PORT_B_data_in_reg, JE1_q_b[4]_PORT_A_address_reg, JE1_q_b[4]_PORT_B_address_reg, JE1_q_b[4]_PORT_A_write_enable_reg, JE1_q_b[4]_PORT_B_write_enable_reg, , , JE1_q_b[4]_clock_0, , , , , );
|
| 4441 |
|
|
JE1_q_b[4] = JE1_q_b[4]_PORT_B_data_out[0];
|
| 4442 |
|
|
|
| 4443 |
|
|
|
| 4444 |
|
|
--AD1_id2ra_ins_clr_1_0_i_a2_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|id2ra_ins_clr_1_0_i_a2_0_a2
|
| 4445 |
|
|
--operation mode is normal
|
| 4446 |
|
|
|
| 4447 |
|
|
AD1_id2ra_ins_clr_1_0_i_a2_0_a2 = AD1_CurrState_Sreg0_i[0] & !AD1_CurrState_Sreg0_5 & !AD1_CurrState_Sreg0[7] & !AD1_CurrState_Sreg0[2];
|
| 4448 |
|
|
|
| 4449 |
|
|
|
| 4450 |
|
|
--C1_G_504 is mips_sys:isys|G_504
|
| 4451 |
|
|
--operation mode is normal
|
| 4452 |
|
|
|
| 4453 |
|
|
C1_G_504 = !AD1_id2ra_ins_clr_1_0_i_a2_0_a2 # !AD1_CurrState_Sreg0_2;
|
| 4454 |
|
|
|
| 4455 |
|
|
|
| 4456 |
|
|
--AD1_CurrState_Sreg0_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_5
|
| 4457 |
|
|
--operation mode is normal
|
| 4458 |
|
|
|
| 4459 |
|
|
AD1_CurrState_Sreg0_5_lut_out = !sys_rst;
|
| 4460 |
|
|
AD1_CurrState_Sreg0_5 = DFFEAS(AD1_CurrState_Sreg0_5_lut_out, E1__clk0, VCC, , , , , , );
|
| 4461 |
|
|
|
| 4462 |
|
|
|
| 4463 |
|
|
--AD1_CurrState_Sreg0_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_2
|
| 4464 |
|
|
--operation mode is normal
|
| 4465 |
|
|
|
| 4466 |
|
|
AD1_CurrState_Sreg0_2_lut_out = WB35L1 & !WB45L1 & !WB55L1 & AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
|
| 4467 |
|
|
AD1_CurrState_Sreg0_2 = DFFEAS(AD1_CurrState_Sreg0_2_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 4468 |
|
|
|
| 4469 |
|
|
|
| 4470 |
|
|
--ZC1_alu_func_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_2
|
| 4471 |
|
|
--operation mode is normal
|
| 4472 |
|
|
|
| 4473 |
|
|
ZC1_alu_func_o_2_lut_out = WB93L2;
|
| 4474 |
|
|
ZC1_alu_func_o_2 = DFFEAS(ZC1_alu_func_o_2_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4475 |
|
|
|
| 4476 |
|
|
|
| 4477 |
|
|
--ZC1_alu_func_o_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_3
|
| 4478 |
|
|
--operation mode is normal
|
| 4479 |
|
|
|
| 4480 |
|
|
ZC1_alu_func_o_3_lut_out = WB04L2;
|
| 4481 |
|
|
ZC1_alu_func_o_3 = DFFEAS(ZC1_alu_func_o_3_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4482 |
|
|
|
| 4483 |
|
|
|
| 4484 |
|
|
--TD1_m107 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m107
|
| 4485 |
|
|
--operation mode is normal
|
| 4486 |
|
|
|
| 4487 |
|
|
TD1_m107 = RC1_alu_func_o_1 & RC1_alu_func_o_4;
|
| 4488 |
|
|
|
| 4489 |
|
|
|
| 4490 |
|
|
--VD1_hilo_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_4
|
| 4491 |
|
|
--operation mode is normal
|
| 4492 |
|
|
|
| 4493 |
|
|
VD1_hilo_4_lut_out = VD1_hilo_37_iv_0_0[4] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_4 # !VD1_hilo_37_iv_0_a[4];
|
| 4494 |
|
|
VD1_hilo_4 = DFFEAS(VD1_hilo_4_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 4495 |
|
|
|
| 4496 |
|
|
|
| 4497 |
|
|
--VD1_hilo_36 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_36
|
| 4498 |
|
|
--operation mode is normal
|
| 4499 |
|
|
|
| 4500 |
|
|
VD1_hilo_36_lut_out = VD1_hilo_37_iv_0_a[36] & !VD1_hilo_37_iv_0_a3[57] & PD1_a_o_4 # !VD1_hilo_37_iv_0_a3_1[0];
|
| 4501 |
|
|
VD1_hilo_36 = DFFEAS(VD1_hilo_36_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 4502 |
|
|
|
| 4503 |
|
|
|
| 4504 |
|
|
--QD1_b_o_0_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_0_sqmuxa
|
| 4505 |
|
|
--operation mode is normal
|
| 4506 |
|
|
|
| 4507 |
|
|
QD1_b_o_0_sqmuxa = PC1_muxb_ctl_o_0 & !PC1_muxb_ctl_o_1 & XD1_mux_fw_1;
|
| 4508 |
|
|
|
| 4509 |
|
|
|
| 4510 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[4] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[4]
|
| 4511 |
|
|
--operation mode is normal
|
| 4512 |
|
|
|
| 4513 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[4] = QB1_r32_o_4 & !FB1_r32_o_0_4 & QD1_b_o18 # !QB1_r32_o_4 & QD1_un1_b_o18_2 # !FB1_r32_o_0_4 & QD1_b_o18;
|
| 4514 |
|
|
|
| 4515 |
|
|
|
| 4516 |
|
|
--G1_BUS15471_i_m[4] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[4]
|
| 4517 |
|
|
--operation mode is normal
|
| 4518 |
|
|
|
| 4519 |
|
|
G1_BUS15471_i_m[4] = !FD1_wb_o_4 & QD1_b_o_1_sqmuxa;
|
| 4520 |
|
|
|
| 4521 |
|
|
|
| 4522 |
|
|
--VD1_op1_sign_reged_0_sqmuxa_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op1_sign_reged_0_sqmuxa_i
|
| 4523 |
|
|
--operation mode is normal
|
| 4524 |
|
|
|
| 4525 |
|
|
VD1_op1_sign_reged_0_sqmuxa_i = VD1_rdy_0_sqmuxa # !sys_rst;
|
| 4526 |
|
|
|
| 4527 |
|
|
|
| 4528 |
|
|
--TD1_alu_out_7_0_0_m4_0_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0_a[3]
|
| 4529 |
|
|
--operation mode is normal
|
| 4530 |
|
|
|
| 4531 |
|
|
TD1_alu_out_7_0_0_m4_0_a[3] = !RC1_alu_func_o_1 & RC1_alu_func_o_4 & RC1_alu_func_o_0;
|
| 4532 |
|
|
|
| 4533 |
|
|
|
| 4534 |
|
|
--TD1_alu_out_0_a3[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a3[28]
|
| 4535 |
|
|
--operation mode is normal
|
| 4536 |
|
|
|
| 4537 |
|
|
TD1_alu_out_0_a3[28] = RC1_alu_func_o_4 & !RC1_alu_func_o_0;
|
| 4538 |
|
|
|
| 4539 |
|
|
|
| 4540 |
|
|
--GC1_muxa_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr_cls:U7|muxa_ctl_o_0
|
| 4541 |
|
|
--operation mode is normal
|
| 4542 |
|
|
|
| 4543 |
|
|
GC1_muxa_ctl_o_0_lut_out = WB65L1;
|
| 4544 |
|
|
GC1_muxa_ctl_o_0 = DFFEAS(GC1_muxa_ctl_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 4545 |
|
|
|
| 4546 |
|
|
|
| 4547 |
|
|
--RD1_r32_o_0_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_4
|
| 4548 |
|
|
--operation mode is arithmetic
|
| 4549 |
|
|
|
| 4550 |
|
|
RD1_r32_o_0_4_carry_eqn = HB1_BUS2446_cout[2];
|
| 4551 |
|
|
RD1_r32_o_0_4_lut_out = KB1_r32_o_4 $ (RD1_r32_o_0_4_carry_eqn);
|
| 4552 |
|
|
RD1_r32_o_0_4 = DFFEAS(RD1_r32_o_0_4_lut_out, E1__clk0, VCC, , , , , , );
|
| 4553 |
|
|
|
| 4554 |
|
|
--RD1_r32_o_cout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[4]
|
| 4555 |
|
|
--operation mode is arithmetic
|
| 4556 |
|
|
|
| 4557 |
|
|
RD1_r32_o_cout[4] = CARRY(!HB1_BUS2446_cout[2] # !KB1_r32_o_5 # !KB1_r32_o_4);
|
| 4558 |
|
|
|
| 4559 |
|
|
|
| 4560 |
|
|
--FB1_res_7_0_0_4 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_4
|
| 4561 |
|
|
--operation mode is normal
|
| 4562 |
|
|
|
| 4563 |
|
|
FB1_res_7_0_0_4 = CD1_res_7_0_0_0_2 # ED1_r32_o_2 & CD1_res_7_0_0_o3_0;
|
| 4564 |
|
|
|
| 4565 |
|
|
--FB1_r32_o_0_4 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_4
|
| 4566 |
|
|
--operation mode is normal
|
| 4567 |
|
|
|
| 4568 |
|
|
FB1_r32_o_0_4 = DFFEAS(FB1_res_7_0_0_4, E1__clk0, VCC, , , , , , );
|
| 4569 |
|
|
|
| 4570 |
|
|
|
| 4571 |
|
|
--SC1_muxa_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17|muxa_ctl_o_1
|
| 4572 |
|
|
--operation mode is normal
|
| 4573 |
|
|
|
| 4574 |
|
|
SC1_muxa_ctl_o_1_lut_out = GC1_muxa_ctl_o_1;
|
| 4575 |
|
|
SC1_muxa_ctl_o_1 = DFFEAS(SC1_muxa_ctl_o_1_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 4576 |
|
|
|
| 4577 |
|
|
|
| 4578 |
|
|
--SD1_r32_o_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_4
|
| 4579 |
|
|
--operation mode is normal
|
| 4580 |
|
|
|
| 4581 |
|
|
SD1_r32_o_4_lut_out = KB1_r32_o_4;
|
| 4582 |
|
|
SD1_r32_o_4 = DFFEAS(SD1_r32_o_4_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 4583 |
|
|
|
| 4584 |
|
|
|
| 4585 |
|
|
--PD1_a_o_3_d[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[4]
|
| 4586 |
|
|
--operation mode is normal
|
| 4587 |
|
|
|
| 4588 |
|
|
PD1_a_o_3_d[4] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_4 # !PD1_un6_a_o & !PD1_a_o_3_d_a[4] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[4];
|
| 4589 |
|
|
|
| 4590 |
|
|
|
| 4591 |
|
|
--PD1_a_o_3_s[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_s[0]
|
| 4592 |
|
|
--operation mode is normal
|
| 4593 |
|
|
|
| 4594 |
|
|
PD1_a_o_3_s[0] = !SC1_muxa_ctl_o_1 & !PD1_a_o_sn_m2;
|
| 4595 |
|
|
|
| 4596 |
|
|
|
| 4597 |
|
|
--PD1_a_o_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[3]
|
| 4598 |
|
|
--operation mode is normal
|
| 4599 |
|
|
|
| 4600 |
|
|
PD1_a_o_a[3] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_3 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_3;
|
| 4601 |
|
|
|
| 4602 |
|
|
|
| 4603 |
|
|
--PD1_a_o_3_Z[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[3]
|
| 4604 |
|
|
--operation mode is normal
|
| 4605 |
|
|
|
| 4606 |
|
|
PD1_a_o_3_Z[3] = PD1_a_o_3_s[0] & SD1_r32_o_3 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[3];
|
| 4607 |
|
|
|
| 4608 |
|
|
|
| 4609 |
|
|
--VD1_b_o_iv_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_3
|
| 4610 |
|
|
--operation mode is normal
|
| 4611 |
|
|
|
| 4612 |
|
|
VD1_b_o_iv_3 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[3] & !G1_BUS15471_i_m[3] & AB1_r32_o_1 # !QD1_b_o_0_sqmuxa;
|
| 4613 |
|
|
|
| 4614 |
|
|
--VD1_op2_reged[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[3]
|
| 4615 |
|
|
--operation mode is normal
|
| 4616 |
|
|
|
| 4617 |
|
|
VD1_op2_reged[3] = DFFEAS(VD1_b_o_iv_3, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 4618 |
|
|
|
| 4619 |
|
|
|
| 4620 |
|
|
--TD1_un1_b_1_combout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[2]
|
| 4621 |
|
|
--operation mode is normal
|
| 4622 |
|
|
|
| 4623 |
|
|
TD1_un1_b_1_combout[2] = TD1_sum13_0_a2 $ !VD1_b_o_iv_2;
|
| 4624 |
|
|
|
| 4625 |
|
|
|
| 4626 |
|
|
--TD1_un1_a_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add1
|
| 4627 |
|
|
--operation mode is arithmetic
|
| 4628 |
|
|
|
| 4629 |
|
|
TD1_un1_a_add1_carry_eqn = TD1_un1_a_carry_0;
|
| 4630 |
|
|
TD1_un1_a_add1 = PD1_a_o_1 $ TD1_un1_b_1_combout[1] $ TD1_un1_a_add1_carry_eqn;
|
| 4631 |
|
|
|
| 4632 |
|
|
--TD1_un1_a_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_1
|
| 4633 |
|
|
--operation mode is arithmetic
|
| 4634 |
|
|
|
| 4635 |
|
|
TD1_un1_a_carry_1 = CARRY(PD1_a_o_1 & !TD1_un1_b_1_combout[1] & !TD1_un1_a_carry_0 # !PD1_a_o_1 & !TD1_un1_a_carry_0 # !TD1_un1_b_1_combout[1]);
|
| 4636 |
|
|
|
| 4637 |
|
|
|
| 4638 |
|
|
--UD1_shift_out_85_d[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[4]
|
| 4639 |
|
|
--operation mode is normal
|
| 4640 |
|
|
|
| 4641 |
|
|
UD1_shift_out_85_d[4] = PD1_a_o_0 & VD1_b_o_iv_1 & !PD1_a_o_2 # !PD1_a_o_0 & PD1_a_o_2 $ !UD1_shift_out_85_d_a[4];
|
| 4642 |
|
|
|
| 4643 |
|
|
|
| 4644 |
|
|
--UD1_shift_out_87_d[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[4]
|
| 4645 |
|
|
--operation mode is normal
|
| 4646 |
|
|
|
| 4647 |
|
|
UD1_shift_out_87_d[4] = PD1_a_o_0 & UD1_shift_out_80[4] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[4];
|
| 4648 |
|
|
|
| 4649 |
|
|
|
| 4650 |
|
|
--UD1_shift_out587 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out587
|
| 4651 |
|
|
--operation mode is normal
|
| 4652 |
|
|
|
| 4653 |
|
|
UD1_shift_out587 = !RC1_alu_func_o_1 & TD1_alu_out_9_a2_0_1_0 & !RC1_alu_func_o_4 & RC1_alu_func_o_0;
|
| 4654 |
|
|
|
| 4655 |
|
|
|
| 4656 |
|
|
--UD1_shift_out_88[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[4]
|
| 4657 |
|
|
--operation mode is normal
|
| 4658 |
|
|
|
| 4659 |
|
|
UD1_shift_out_88[4] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_4 # !UD1_shift_out_sn_b10_0 & UD1_shift_out_79[4];
|
| 4660 |
|
|
|
| 4661 |
|
|
|
| 4662 |
|
|
--UD1_shift_out_91_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[4]
|
| 4663 |
|
|
--operation mode is normal
|
| 4664 |
|
|
|
| 4665 |
|
|
UD1_shift_out_91_a[4] = PD1_a_o_2 & !PD1_a_o_3 & UD1_shift_out_79[16] # !PD1_a_o_2 & UD1_shift_out_79[20];
|
| 4666 |
|
|
|
| 4667 |
|
|
|
| 4668 |
|
|
--UD1_shift_out_86_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[4]
|
| 4669 |
|
|
--operation mode is normal
|
| 4670 |
|
|
|
| 4671 |
|
|
UD1_shift_out_86_a[4] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[8] # !PD1_a_o_2 & !UD1_shift_out_47[0] # !UD1_shift_out587 & !UD1_shift_out_79[8];
|
| 4672 |
|
|
|
| 4673 |
|
|
|
| 4674 |
|
|
--UD1_shift_out_74[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[4]
|
| 4675 |
|
|
--operation mode is normal
|
| 4676 |
|
|
|
| 4677 |
|
|
UD1_shift_out_74[4] = PD1_a_o_2 & UD1_shift_out_74_c[4] & VD1_b_o_iv_31 # !UD1_shift_out_74_c[4] & UD1_shift_out_79[16] # !PD1_a_o_2 & UD1_shift_out_74_c[4];
|
| 4678 |
|
|
|
| 4679 |
|
|
|
| 4680 |
|
|
--VD1_hilo_37_iv_0_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[5]
|
| 4681 |
|
|
--operation mode is normal
|
| 4682 |
|
|
|
| 4683 |
|
|
VD1_hilo_37_iv_0_a[5] = VD1_hilo_6 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_4 # !VD1_hilo_6 & !VD1_hilo_2_sqmuxa # !VD1_hilo_4;
|
| 4684 |
|
|
|
| 4685 |
|
|
|
| 4686 |
|
|
--VD1_hilo_37_iv_0_o5_0[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5_0[0]
|
| 4687 |
|
|
--operation mode is normal
|
| 4688 |
|
|
|
| 4689 |
|
|
VD1_hilo_37_iv_0_o5_0[0] = VD1_addnop2109_0_a2 # VD1_hilo_37_iv_0_a3_1[62];
|
| 4690 |
|
|
|
| 4691 |
|
|
|
| 4692 |
|
|
--VD1_hilo_37_iv_0_0[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[5]
|
| 4693 |
|
|
--operation mode is normal
|
| 4694 |
|
|
|
| 4695 |
|
|
VD1_hilo_37_iv_0_0[5] = VD1_hilo_5 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[5] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_5 & VD1_un134_hilo_combout[5] & VD1_hilo_37_iv_0_a3_0[0];
|
| 4696 |
|
|
|
| 4697 |
|
|
|
| 4698 |
|
|
--C1_G_505 is mips_sys:isys|G_505
|
| 4699 |
|
|
--operation mode is normal
|
| 4700 |
|
|
|
| 4701 |
|
|
C1_G_505 = !C1_G_505_a & VD1_un17_mul_0 # !VD1_addnop2109_0_a2 # !sys_rst;
|
| 4702 |
|
|
|
| 4703 |
|
|
|
| 4704 |
|
|
--VD1_hilo_37_iv_0_a2_7[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_7[37]
|
| 4705 |
|
|
--operation mode is normal
|
| 4706 |
|
|
|
| 4707 |
|
|
VD1_hilo_37_iv_0_a2_7[37] = !VD1_sub_or_yn & VD1_hilo_37_iv_0_a2_7_2_1[37] & VD1_hilo_1_sqmuxa_1 & !VD1_un50_hilo_add6;
|
| 4708 |
|
|
|
| 4709 |
|
|
|
| 4710 |
|
|
--VD1_hilo_37_iv_0_5[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[37]
|
| 4711 |
|
|
--operation mode is normal
|
| 4712 |
|
|
|
| 4713 |
|
|
VD1_hilo_37_iv_0_5[37] = VD1_hilo_37_iv_0_1[37] # VD1_hilo_37_iv_0_5_a[37] # !VD1_un59_hilo_add6 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 4714 |
|
|
|
| 4715 |
|
|
|
| 4716 |
|
|
--VD1_hilo_37_iv_0_a[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[37]
|
| 4717 |
|
|
--operation mode is normal
|
| 4718 |
|
|
|
| 4719 |
|
|
VD1_hilo_37_iv_0_a[37] = VD1_hilo_38 & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_5 # !VD1_hilo_38 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_5;
|
| 4720 |
|
|
|
| 4721 |
|
|
|
| 4722 |
|
|
--VD1_hilo_37_iv_0_a3[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3[57]
|
| 4723 |
|
|
--operation mode is normal
|
| 4724 |
|
|
|
| 4725 |
|
|
VD1_hilo_37_iv_0_a3[57] = VD1_addnop2109_0_a2 & VD1_hilo_37_iv_0_o3[34] # !RC1_alu_func_o_0;
|
| 4726 |
|
|
|
| 4727 |
|
|
|
| 4728 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[5] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[5]
|
| 4729 |
|
|
--operation mode is normal
|
| 4730 |
|
|
|
| 4731 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[5] = QB1_r32_o_5 & !FB1_r32_o_0_5 & QD1_b_o18 # !QB1_r32_o_5 & QD1_un1_b_o18_2 # !FB1_r32_o_0_5 & QD1_b_o18;
|
| 4732 |
|
|
|
| 4733 |
|
|
|
| 4734 |
|
|
--G1_BUS15471_i_m[5] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[5]
|
| 4735 |
|
|
--operation mode is normal
|
| 4736 |
|
|
|
| 4737 |
|
|
G1_BUS15471_i_m[5] = !FD1_wb_o_5 & QD1_b_o_1_sqmuxa;
|
| 4738 |
|
|
|
| 4739 |
|
|
|
| 4740 |
|
|
--RD1_r32_o_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_5
|
| 4741 |
|
|
--operation mode is arithmetic
|
| 4742 |
|
|
|
| 4743 |
|
|
RD1_r32_o_5_carry_eqn = RD1_r32_o_cout[3];
|
| 4744 |
|
|
RD1_r32_o_5_lut_out = KB1_r32_o_5 $ (KB1_r32_o_4 & RD1_r32_o_5_carry_eqn);
|
| 4745 |
|
|
RD1_r32_o_5 = DFFEAS(RD1_r32_o_5_lut_out, E1__clk0, VCC, , , , , , );
|
| 4746 |
|
|
|
| 4747 |
|
|
--RD1_r32_o_cout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[5]
|
| 4748 |
|
|
--operation mode is arithmetic
|
| 4749 |
|
|
|
| 4750 |
|
|
RD1_r32_o_cout[5] = CARRY(!RD1_r32_o_cout[3] # !KB1_r32_o_5 # !KB1_r32_o_4);
|
| 4751 |
|
|
|
| 4752 |
|
|
|
| 4753 |
|
|
--FB1_res_7_0_0_5 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_5
|
| 4754 |
|
|
--operation mode is normal
|
| 4755 |
|
|
|
| 4756 |
|
|
FB1_res_7_0_0_5 = ED1_r32_o_3 & CD1_res_7_0_0_o3_0 # ED1_r32_o_5 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_3 & ED1_r32_o_5 & CD1_res_7_0_0_a2_0;
|
| 4757 |
|
|
|
| 4758 |
|
|
--FB1_r32_o_0_5 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_5
|
| 4759 |
|
|
--operation mode is normal
|
| 4760 |
|
|
|
| 4761 |
|
|
FB1_r32_o_0_5 = DFFEAS(FB1_res_7_0_0_5, E1__clk0, VCC, , , , , , );
|
| 4762 |
|
|
|
| 4763 |
|
|
|
| 4764 |
|
|
--SD1_r32_o_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_5
|
| 4765 |
|
|
--operation mode is normal
|
| 4766 |
|
|
|
| 4767 |
|
|
SD1_r32_o_5_lut_out = KB1_r32_o_5;
|
| 4768 |
|
|
SD1_r32_o_5 = DFFEAS(SD1_r32_o_5_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 4769 |
|
|
|
| 4770 |
|
|
|
| 4771 |
|
|
--PD1_a_o_3_d[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[5]
|
| 4772 |
|
|
--operation mode is normal
|
| 4773 |
|
|
|
| 4774 |
|
|
PD1_a_o_3_d[5] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_5 # !PD1_un6_a_o & !PD1_a_o_3_d_a[5] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[5];
|
| 4775 |
|
|
|
| 4776 |
|
|
|
| 4777 |
|
|
--VD1_b_o_iv_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_7
|
| 4778 |
|
|
--operation mode is normal
|
| 4779 |
|
|
|
| 4780 |
|
|
VD1_b_o_iv_7 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[7] & !G1_BUS15471_i_m[7] & AB1_r32_o_5 # !QD1_b_o_0_sqmuxa;
|
| 4781 |
|
|
|
| 4782 |
|
|
--VD1_op2_reged[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[7]
|
| 4783 |
|
|
--operation mode is normal
|
| 4784 |
|
|
|
| 4785 |
|
|
VD1_op2_reged[7] = DFFEAS(VD1_b_o_iv_7, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 4786 |
|
|
|
| 4787 |
|
|
|
| 4788 |
|
|
--UD1_shift_out_87_d[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[5]
|
| 4789 |
|
|
--operation mode is normal
|
| 4790 |
|
|
|
| 4791 |
|
|
UD1_shift_out_87_d[5] = PD1_a_o_0 & UD1_shift_out_80[5] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[5];
|
| 4792 |
|
|
|
| 4793 |
|
|
|
| 4794 |
|
|
--UD1_shift_out_85_d[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[5]
|
| 4795 |
|
|
--operation mode is normal
|
| 4796 |
|
|
|
| 4797 |
|
|
UD1_shift_out_85_d[5] = PD1_a_o_2 & !PD1_a_o_1 & !UD1_shift_out_85_d_a[5] # !PD1_a_o_2 & UD1_shift_out_68[5];
|
| 4798 |
|
|
|
| 4799 |
|
|
|
| 4800 |
|
|
--UD1_shift_out_88[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[5]
|
| 4801 |
|
|
--operation mode is normal
|
| 4802 |
|
|
|
| 4803 |
|
|
UD1_shift_out_88[5] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_5 # !UD1_shift_out_sn_b10_0 & UD1_shift_out_79[5];
|
| 4804 |
|
|
|
| 4805 |
|
|
|
| 4806 |
|
|
--UD1_shift_out_91_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[5]
|
| 4807 |
|
|
--operation mode is normal
|
| 4808 |
|
|
|
| 4809 |
|
|
UD1_shift_out_91_a[5] = PD1_a_o_2 & !PD1_a_o_3 & UD1_shift_out_79[17] # !PD1_a_o_2 & UD1_shift_out_42[1];
|
| 4810 |
|
|
|
| 4811 |
|
|
|
| 4812 |
|
|
--UD1_shift_out_86_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[5]
|
| 4813 |
|
|
--operation mode is normal
|
| 4814 |
|
|
|
| 4815 |
|
|
UD1_shift_out_86_a[5] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[9] # !PD1_a_o_2 & !UD1_shift_out_79[13] # !UD1_shift_out587 & !UD1_shift_out_79[9];
|
| 4816 |
|
|
|
| 4817 |
|
|
|
| 4818 |
|
|
--UD1_shift_out_74[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[5]
|
| 4819 |
|
|
--operation mode is normal
|
| 4820 |
|
|
|
| 4821 |
|
|
UD1_shift_out_74[5] = PD1_a_o_3 & !UD1_shift_out_74_a[5] # !PD1_a_o_3 & UD1_shift_out_61[5];
|
| 4822 |
|
|
|
| 4823 |
|
|
|
| 4824 |
|
|
--VD1_b_o_iv_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_0
|
| 4825 |
|
|
--operation mode is normal
|
| 4826 |
|
|
|
| 4827 |
|
|
VD1_b_o_iv_0 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[0] & !G1_BUS15471_i_m[0] & RB1_byte_addr_o_0 # !QD1_b_o_0_sqmuxa;
|
| 4828 |
|
|
|
| 4829 |
|
|
--VD1_op2_reged[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[0]
|
| 4830 |
|
|
--operation mode is normal
|
| 4831 |
|
|
|
| 4832 |
|
|
VD1_op2_reged[0] = DFFEAS(VD1_b_o_iv_0, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 4833 |
|
|
|
| 4834 |
|
|
|
| 4835 |
|
|
--VD1_b_o_iv_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_1
|
| 4836 |
|
|
--operation mode is normal
|
| 4837 |
|
|
|
| 4838 |
|
|
VD1_b_o_iv_1 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[1] & !QD1_b_o_iv_1_0 & FB1_r32_o_0_1 # !QD1_b_o18;
|
| 4839 |
|
|
|
| 4840 |
|
|
--VD1_op2_reged[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[1]
|
| 4841 |
|
|
--operation mode is normal
|
| 4842 |
|
|
|
| 4843 |
|
|
VD1_op2_reged[1] = DFFEAS(VD1_b_o_iv_1, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 4844 |
|
|
|
| 4845 |
|
|
|
| 4846 |
|
|
--UD1_shift_out_80[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[2]
|
| 4847 |
|
|
--operation mode is normal
|
| 4848 |
|
|
|
| 4849 |
|
|
UD1_shift_out_80[2] = PD1_a_o_2 & UD1_shift_out_80_a[2] & VD1_b_o_iv_7 # !UD1_shift_out_80_a[2] & VD1_b_o_iv_9 # !PD1_a_o_2 & !UD1_shift_out_80_a[2];
|
| 4850 |
|
|
|
| 4851 |
|
|
|
| 4852 |
|
|
--UD1_shift_out_82[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82[2]
|
| 4853 |
|
|
--operation mode is normal
|
| 4854 |
|
|
|
| 4855 |
|
|
UD1_shift_out_82[2] = PD1_a_o_2 & PD1_a_o_1 & VD1_b_o_iv_8 # !PD1_a_o_1 & !UD1_shift_out_82_a[2] # !PD1_a_o_2 & !UD1_shift_out_82_a[2];
|
| 4856 |
|
|
|
| 4857 |
|
|
|
| 4858 |
|
|
--UD1_shift_out_86_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[2]
|
| 4859 |
|
|
--operation mode is normal
|
| 4860 |
|
|
|
| 4861 |
|
|
UD1_shift_out_86_a[2] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[6] # !PD1_a_o_2 & !UD1_shift_out_79[10] # !UD1_shift_out587 & !UD1_shift_out_79[6];
|
| 4862 |
|
|
|
| 4863 |
|
|
|
| 4864 |
|
|
--UD1_shift_out_74[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[2]
|
| 4865 |
|
|
--operation mode is normal
|
| 4866 |
|
|
|
| 4867 |
|
|
UD1_shift_out_74[2] = PD1_a_o_3 & UD1_shift_out_74_a[2] & UD1_shift_out_79[18] # !UD1_shift_out_74_a[2] & UD1_shift_out_41[2] # !PD1_a_o_3 & !UD1_shift_out_74_a[2];
|
| 4868 |
|
|
|
| 4869 |
|
|
|
| 4870 |
|
|
--UD1_shift_out_91_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[2]
|
| 4871 |
|
|
--operation mode is normal
|
| 4872 |
|
|
|
| 4873 |
|
|
UD1_shift_out_91_a[2] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_2 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[2];
|
| 4874 |
|
|
|
| 4875 |
|
|
|
| 4876 |
|
|
--UD1_shift_out_76[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[2]
|
| 4877 |
|
|
--operation mode is normal
|
| 4878 |
|
|
|
| 4879 |
|
|
UD1_shift_out_76[2] = UD1_shift_out587 & PD1_a_o_2 & UD1_shift_out_76_a[2] # !PD1_a_o_2 & UD1_shift_out_79[18];
|
| 4880 |
|
|
|
| 4881 |
|
|
|
| 4882 |
|
|
--VD1_hilo_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_2
|
| 4883 |
|
|
--operation mode is normal
|
| 4884 |
|
|
|
| 4885 |
|
|
VD1_hilo_2_lut_out = VD1_hilo_37_iv_0_0[2] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_2 # !VD1_hilo_37_iv_0_a[2];
|
| 4886 |
|
|
VD1_hilo_2 = DFFEAS(VD1_hilo_2_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 4887 |
|
|
|
| 4888 |
|
|
|
| 4889 |
|
|
--VD1_hilo_34 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_34
|
| 4890 |
|
|
--operation mode is normal
|
| 4891 |
|
|
|
| 4892 |
|
|
VD1_hilo_34_lut_out = !VD1_hilo_37_iv_0_o3_0[34] & VD1_hilo_37_iv_0_a[34] & PD1_a_o_2 # !VD1_hilo_37_iv_0_a3_1[0];
|
| 4893 |
|
|
VD1_hilo_34 = DFFEAS(VD1_hilo_34_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 4894 |
|
|
|
| 4895 |
|
|
|
| 4896 |
|
|
--VD1_b_o_iv_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_2
|
| 4897 |
|
|
--operation mode is normal
|
| 4898 |
|
|
|
| 4899 |
|
|
VD1_b_o_iv_2 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[2] & !G1_BUS15471_i_m[2] & AB1_r32_o_0 # !QD1_b_o_0_sqmuxa;
|
| 4900 |
|
|
|
| 4901 |
|
|
--VD1_op2_reged[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[2]
|
| 4902 |
|
|
--operation mode is normal
|
| 4903 |
|
|
|
| 4904 |
|
|
VD1_op2_reged[2] = DFFEAS(VD1_b_o_iv_2, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 4905 |
|
|
|
| 4906 |
|
|
|
| 4907 |
|
|
--TD1_m9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m9
|
| 4908 |
|
|
--operation mode is normal
|
| 4909 |
|
|
|
| 4910 |
|
|
TD1_m9 = RC1_alu_func_o_1 & TD1_alu_out_sn_m14_0_0;
|
| 4911 |
|
|
|
| 4912 |
|
|
|
| 4913 |
|
|
--TD1_m112_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m112_a
|
| 4914 |
|
|
--operation mode is normal
|
| 4915 |
|
|
|
| 4916 |
|
|
TD1_m112_a = VD1_b_o_iv_2 & !PD1_a_o_2 # !VD1_b_o_iv_2 & PD1_a_o_2 & !TD1_m5 # !PD1_a_o_2 & !TD1_m4;
|
| 4917 |
|
|
|
| 4918 |
|
|
|
| 4919 |
|
|
--MD1_c_0_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[3]
|
| 4920 |
|
|
--operation mode is normal
|
| 4921 |
|
|
|
| 4922 |
|
|
MD1_c_0_a[3] = VD1_un24_res & !VD1_hilo_35 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_3;
|
| 4923 |
|
|
|
| 4924 |
|
|
|
| 4925 |
|
|
--TD1_alu_out_7_0_0_m4_0[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[3]
|
| 4926 |
|
|
--operation mode is normal
|
| 4927 |
|
|
|
| 4928 |
|
|
TD1_alu_out_7_0_0_m4_0[3] = VD1_b_o_iv_3 & TD1_alu_out_7_0_0_o3_0 & TD1_alu_out_0_a3[28] # !VD1_b_o_iv_3 & TD1_alu_out_7_0_0_m4_0_a[3];
|
| 4929 |
|
|
|
| 4930 |
|
|
|
| 4931 |
|
|
--TD1_alu_out_7_0_0_m2_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_a[3]
|
| 4932 |
|
|
--operation mode is normal
|
| 4933 |
|
|
|
| 4934 |
|
|
TD1_alu_out_7_0_0_m2_a[3] = VD1_b_o_iv_3 & !TD1_m107 # !VD1_b_o_iv_3 & !TD1_alu_out_0_a3[28];
|
| 4935 |
|
|
|
| 4936 |
|
|
|
| 4937 |
|
|
--UD1_shift_out_82[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82[3]
|
| 4938 |
|
|
--operation mode is normal
|
| 4939 |
|
|
|
| 4940 |
|
|
UD1_shift_out_82[3] = PD1_a_o_2 & PD1_a_o_1 & VD1_b_o_iv_9 # !PD1_a_o_1 & !UD1_shift_out_82_a[3] # !PD1_a_o_2 & !UD1_shift_out_82_a[3];
|
| 4941 |
|
|
|
| 4942 |
|
|
|
| 4943 |
|
|
--UD1_shift_out_89_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[3]
|
| 4944 |
|
|
--operation mode is normal
|
| 4945 |
|
|
|
| 4946 |
|
|
UD1_shift_out_89_a[3] = UD1_shift_out586 & !PD1_a_o_2 & UD1_shift_out_81[3] # !UD1_shift_out586 & !UD1_shift_out_80[3];
|
| 4947 |
|
|
|
| 4948 |
|
|
|
| 4949 |
|
|
--UD1_shift_out_91[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[3]
|
| 4950 |
|
|
--operation mode is normal
|
| 4951 |
|
|
|
| 4952 |
|
|
UD1_shift_out_91[3] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[3] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[3];
|
| 4953 |
|
|
|
| 4954 |
|
|
|
| 4955 |
|
|
--UD1_shift_out_86[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[3]
|
| 4956 |
|
|
--operation mode is normal
|
| 4957 |
|
|
|
| 4958 |
|
|
UD1_shift_out_86[3] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[3] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[3];
|
| 4959 |
|
|
|
| 4960 |
|
|
|
| 4961 |
|
|
--UD1_shift_out_89_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_15
|
| 4962 |
|
|
--operation mode is normal
|
| 4963 |
|
|
|
| 4964 |
|
|
UD1_shift_out_89_15 = UD1_shift_out586 & !UD1_shift_out_89_a[16] # !UD1_shift_out586 & UD1_shift_out_87[16];
|
| 4965 |
|
|
|
| 4966 |
|
|
|
| 4967 |
|
|
--MD1_c_a_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_16
|
| 4968 |
|
|
--operation mode is normal
|
| 4969 |
|
|
|
| 4970 |
|
|
MD1_c_a_16 = UD1_shift_out586 & !UD1_shift_out_92_d_8 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_8 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_16;
|
| 4971 |
|
|
|
| 4972 |
|
|
|
| 4973 |
|
|
--MD1_c_0_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_15
|
| 4974 |
|
|
--operation mode is normal
|
| 4975 |
|
|
|
| 4976 |
|
|
MD1_c_0_15 = RC1_alu_func_o_4 & !TD1_m36 # !RC1_alu_func_o_4 & TD1_m33 # !MD1_c_0_a[16];
|
| 4977 |
|
|
|
| 4978 |
|
|
|
| 4979 |
|
|
--UD1_shift_out_89_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_16
|
| 4980 |
|
|
--operation mode is normal
|
| 4981 |
|
|
|
| 4982 |
|
|
UD1_shift_out_89_16 = UD1_shift_out586 & !UD1_shift_out_89_a[17] # !UD1_shift_out586 & UD1_shift_out_87[17];
|
| 4983 |
|
|
|
| 4984 |
|
|
|
| 4985 |
|
|
--UD1_shift_out_92_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_11
|
| 4986 |
|
|
--operation mode is normal
|
| 4987 |
|
|
|
| 4988 |
|
|
UD1_shift_out_92_11 = UD1_shift_out586 & UD1_shift_out_92_d[17] # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d[17] # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_a[17];
|
| 4989 |
|
|
|
| 4990 |
|
|
|
| 4991 |
|
|
--MD1_c_0_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_16
|
| 4992 |
|
|
--operation mode is normal
|
| 4993 |
|
|
|
| 4994 |
|
|
MD1_c_0_16 = RC1_alu_func_o_4 & !TD1_m41 # !RC1_alu_func_o_4 & TD1_m38 # !MD1_c_0_a[17];
|
| 4995 |
|
|
|
| 4996 |
|
|
|
| 4997 |
|
|
--UD1_shift_out_89_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_13
|
| 4998 |
|
|
--operation mode is normal
|
| 4999 |
|
|
|
| 5000 |
|
|
UD1_shift_out_89_13 = UD1_shift_out586 & !UD1_shift_out_89_a[14] # !UD1_shift_out586 & UD1_shift_out_87[14];
|
| 5001 |
|
|
|
| 5002 |
|
|
|
| 5003 |
|
|
--MD1_c_a_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_14
|
| 5004 |
|
|
--operation mode is normal
|
| 5005 |
|
|
|
| 5006 |
|
|
MD1_c_a_14 = UD1_shift_out586 & !UD1_shift_out_92_d_6 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_6 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_14;
|
| 5007 |
|
|
|
| 5008 |
|
|
|
| 5009 |
|
|
--MD1_c_0_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_13
|
| 5010 |
|
|
--operation mode is normal
|
| 5011 |
|
|
|
| 5012 |
|
|
MD1_c_0_13 = RC1_alu_func_o_4 & !TD1_m26 # !RC1_alu_func_o_4 & TD1_m23 # !MD1_c_0_a[14];
|
| 5013 |
|
|
|
| 5014 |
|
|
|
| 5015 |
|
|
--UD1_shift_out_89_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_14
|
| 5016 |
|
|
--operation mode is normal
|
| 5017 |
|
|
|
| 5018 |
|
|
UD1_shift_out_89_14 = UD1_shift_out586 & !UD1_shift_out_89_a[15] # !UD1_shift_out586 & UD1_shift_out_87[15];
|
| 5019 |
|
|
|
| 5020 |
|
|
|
| 5021 |
|
|
--MD1_c_a_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_15
|
| 5022 |
|
|
--operation mode is normal
|
| 5023 |
|
|
|
| 5024 |
|
|
MD1_c_a_15 = UD1_shift_out586 & !UD1_shift_out_92_d_7 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_7 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_15;
|
| 5025 |
|
|
|
| 5026 |
|
|
|
| 5027 |
|
|
--MD1_c_0_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_14
|
| 5028 |
|
|
--operation mode is normal
|
| 5029 |
|
|
|
| 5030 |
|
|
MD1_c_0_14 = RC1_alu_func_o_4 & !TD1_m31 # !RC1_alu_func_o_4 & TD1_m28 # !MD1_c_0_a[15];
|
| 5031 |
|
|
|
| 5032 |
|
|
|
| 5033 |
|
|
--MD1_c_a_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_31
|
| 5034 |
|
|
--operation mode is normal
|
| 5035 |
|
|
|
| 5036 |
|
|
MD1_c_a_31 = UD1_shift_out586 & !UD1_shift_out_85_27 # !UD1_shift_out586 & !UD1_shift_out_36_0;
|
| 5037 |
|
|
|
| 5038 |
|
|
|
| 5039 |
|
|
--UD1_shift_out_92_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_25
|
| 5040 |
|
|
--operation mode is normal
|
| 5041 |
|
|
|
| 5042 |
|
|
UD1_shift_out_92_25 = UD1_shift_out586 & UD1_shift_out_92_d[31] # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d[31] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_83[31];
|
| 5043 |
|
|
|
| 5044 |
|
|
|
| 5045 |
|
|
--MD1_c_0_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_30
|
| 5046 |
|
|
--operation mode is normal
|
| 5047 |
|
|
|
| 5048 |
|
|
MD1_c_0_30 = RC1_alu_func_o_4 & !TD1_m101 # !RC1_alu_func_o_4 & TD1_m98 # !MD1_c_0_a[31];
|
| 5049 |
|
|
|
| 5050 |
|
|
|
| 5051 |
|
|
--AB1_c_6 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_6
|
| 5052 |
|
|
--operation mode is normal
|
| 5053 |
|
|
|
| 5054 |
|
|
AB1_c_6 = MD1_c_0_7 # UD1_shift_out_sn_m31_i & !MD1_c_a_8 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_7;
|
| 5055 |
|
|
|
| 5056 |
|
|
--AB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_6
|
| 5057 |
|
|
--operation mode is normal
|
| 5058 |
|
|
|
| 5059 |
|
|
AB1_r32_o_6 = DFFEAS(AB1_c_6, E1__clk0, VCC, , , , , , );
|
| 5060 |
|
|
|
| 5061 |
|
|
|
| 5062 |
|
|
--AB1_c_7 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_7
|
| 5063 |
|
|
--operation mode is normal
|
| 5064 |
|
|
|
| 5065 |
|
|
AB1_c_7 = MD1_c_0_8 # UD1_shift_out_sn_m31_i & !MD1_c_a_9 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_8;
|
| 5066 |
|
|
|
| 5067 |
|
|
--AB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_7
|
| 5068 |
|
|
--operation mode is normal
|
| 5069 |
|
|
|
| 5070 |
|
|
AB1_r32_o_7 = DFFEAS(AB1_c_7, E1__clk0, VCC, , , , , , );
|
| 5071 |
|
|
|
| 5072 |
|
|
|
| 5073 |
|
|
--AB1_c_8 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_8
|
| 5074 |
|
|
--operation mode is normal
|
| 5075 |
|
|
|
| 5076 |
|
|
AB1_c_8 = MD1_c_1_10 # UD1_shift_out_10 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add10;
|
| 5077 |
|
|
|
| 5078 |
|
|
--AB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_8
|
| 5079 |
|
|
--operation mode is normal
|
| 5080 |
|
|
|
| 5081 |
|
|
AB1_r32_o_8 = DFFEAS(AB1_c_8, E1__clk0, VCC, , , , , , );
|
| 5082 |
|
|
|
| 5083 |
|
|
|
| 5084 |
|
|
--AB1_c_9 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_9
|
| 5085 |
|
|
--operation mode is normal
|
| 5086 |
|
|
|
| 5087 |
|
|
AB1_c_9 = MD1_c_0_10 # UD1_shift_out_sn_m31_i & !MD1_c_a_11 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_10;
|
| 5088 |
|
|
|
| 5089 |
|
|
--AB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_9
|
| 5090 |
|
|
--operation mode is normal
|
| 5091 |
|
|
|
| 5092 |
|
|
AB1_r32_o_9 = DFFEAS(AB1_c_9, E1__clk0, VCC, , , , , , );
|
| 5093 |
|
|
|
| 5094 |
|
|
|
| 5095 |
|
|
--UD1_shift_out_89_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_20
|
| 5096 |
|
|
--operation mode is normal
|
| 5097 |
|
|
|
| 5098 |
|
|
UD1_shift_out_89_20 = UD1_shift_out586 & !UD1_shift_out_89_a[21] # !UD1_shift_out586 & UD1_shift_out_87[21];
|
| 5099 |
|
|
|
| 5100 |
|
|
|
| 5101 |
|
|
--MD1_c_a_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_21
|
| 5102 |
|
|
--operation mode is normal
|
| 5103 |
|
|
|
| 5104 |
|
|
MD1_c_a_21 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_13;
|
| 5105 |
|
|
|
| 5106 |
|
|
|
| 5107 |
|
|
--MD1_c_0_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_20
|
| 5108 |
|
|
--operation mode is normal
|
| 5109 |
|
|
|
| 5110 |
|
|
MD1_c_0_20 = RC1_alu_func_o_4 & !TD1_m132 # !RC1_alu_func_o_4 & TD1_m129 # !MD1_c_0_a[21];
|
| 5111 |
|
|
|
| 5112 |
|
|
|
| 5113 |
|
|
--UD1_shift_out_89_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_19
|
| 5114 |
|
|
--operation mode is normal
|
| 5115 |
|
|
|
| 5116 |
|
|
UD1_shift_out_89_19 = UD1_shift_out586 & !UD1_shift_out_89_a[20] # !UD1_shift_out586 & UD1_shift_out_87[20];
|
| 5117 |
|
|
|
| 5118 |
|
|
|
| 5119 |
|
|
--MD1_c_1_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_20
|
| 5120 |
|
|
--operation mode is normal
|
| 5121 |
|
|
|
| 5122 |
|
|
MD1_c_1_20 = RC1_alu_func_o_4 & !TD1_m56 # !RC1_alu_func_o_4 & TD1_m53 # !MD1_c_1_a[20];
|
| 5123 |
|
|
|
| 5124 |
|
|
|
| 5125 |
|
|
--MD1_c_a_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_20
|
| 5126 |
|
|
--operation mode is normal
|
| 5127 |
|
|
|
| 5128 |
|
|
MD1_c_a_20 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_12;
|
| 5129 |
|
|
|
| 5130 |
|
|
|
| 5131 |
|
|
--AB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_17
|
| 5132 |
|
|
--operation mode is normal
|
| 5133 |
|
|
|
| 5134 |
|
|
AB1_r32_o_17_lut_out = MD1_c_0_18 # UD1_shift_out_sn_m31_i & UD1_shift_out_92_13 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_18;
|
| 5135 |
|
|
AB1_r32_o_17 = DFFEAS(AB1_r32_o_17_lut_out, E1__clk0, VCC, , , , , , );
|
| 5136 |
|
|
|
| 5137 |
|
|
|
| 5138 |
|
|
--AB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_16
|
| 5139 |
|
|
--operation mode is normal
|
| 5140 |
|
|
|
| 5141 |
|
|
AB1_r32_o_16_lut_out = MD1_c_0_17 # UD1_shift_out_sn_m31_i & UD1_shift_out_92_12 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_17;
|
| 5142 |
|
|
AB1_r32_o_16 = DFFEAS(AB1_r32_o_16_lut_out, E1__clk0, VCC, , , , , , );
|
| 5143 |
|
|
|
| 5144 |
|
|
|
| 5145 |
|
|
--AB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_24
|
| 5146 |
|
|
--operation mode is normal
|
| 5147 |
|
|
|
| 5148 |
|
|
AB1_r32_o_24_lut_out = MD1_c_0_25 # UD1_shift_out_sn_m31_i & MD1_c_a_26 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_25;
|
| 5149 |
|
|
AB1_r32_o_24 = DFFEAS(AB1_r32_o_24_lut_out, E1__clk0, VCC, , , , , , );
|
| 5150 |
|
|
|
| 5151 |
|
|
|
| 5152 |
|
|
--AB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_25
|
| 5153 |
|
|
--operation mode is normal
|
| 5154 |
|
|
|
| 5155 |
|
|
AB1_r32_o_25_lut_out = MD1_c_0_26 # UD1_shift_out_sn_m31_i & MD1_c_a_27 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_26;
|
| 5156 |
|
|
AB1_r32_o_25 = DFFEAS(AB1_r32_o_25_lut_out, E1__clk0, VCC, , , , , , );
|
| 5157 |
|
|
|
| 5158 |
|
|
|
| 5159 |
|
|
--AB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_26
|
| 5160 |
|
|
--operation mode is normal
|
| 5161 |
|
|
|
| 5162 |
|
|
AB1_r32_o_26_lut_out = MD1_c_4_0 # UD1_shift_out_sn_m31_i & MD1_c_a_28 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_27;
|
| 5163 |
|
|
AB1_r32_o_26 = DFFEAS(AB1_r32_o_26_lut_out, E1__clk0, VCC, , , , , , );
|
| 5164 |
|
|
|
| 5165 |
|
|
|
| 5166 |
|
|
--AB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_27
|
| 5167 |
|
|
--operation mode is normal
|
| 5168 |
|
|
|
| 5169 |
|
|
AB1_r32_o_27_lut_out = MD1_c_0_28 # UD1_shift_out_sn_m31_i & MD1_c_a_29 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_28;
|
| 5170 |
|
|
AB1_r32_o_27 = DFFEAS(AB1_r32_o_27_lut_out, E1__clk0, VCC, , , , , , );
|
| 5171 |
|
|
|
| 5172 |
|
|
|
| 5173 |
|
|
--UD1_shift_out_89_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_12
|
| 5174 |
|
|
--operation mode is normal
|
| 5175 |
|
|
|
| 5176 |
|
|
UD1_shift_out_89_12 = UD1_shift_out586 & !UD1_shift_out_89_a[13] # !UD1_shift_out586 & UD1_shift_out_87[13];
|
| 5177 |
|
|
|
| 5178 |
|
|
|
| 5179 |
|
|
--MD1_c_a_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_13
|
| 5180 |
|
|
--operation mode is normal
|
| 5181 |
|
|
|
| 5182 |
|
|
MD1_c_a_13 = UD1_shift_out586 & !UD1_shift_out_92_d_5 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_5 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_13;
|
| 5183 |
|
|
|
| 5184 |
|
|
|
| 5185 |
|
|
--MD1_c_0_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_12
|
| 5186 |
|
|
--operation mode is normal
|
| 5187 |
|
|
|
| 5188 |
|
|
MD1_c_0_12 = RC1_alu_func_o_4 & !TD1_m127 # !RC1_alu_func_o_4 & TD1_m124 # !MD1_c_0_a[13];
|
| 5189 |
|
|
|
| 5190 |
|
|
|
| 5191 |
|
|
--VD1_hilo_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_30
|
| 5192 |
|
|
--operation mode is normal
|
| 5193 |
|
|
|
| 5194 |
|
|
VD1_hilo_30_lut_out = VD1_hilo_37_iv_0_0[30] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_30 # !VD1_hilo_37_iv_0_a[30];
|
| 5195 |
|
|
VD1_hilo_30 = DFFEAS(VD1_hilo_30_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 5196 |
|
|
|
| 5197 |
|
|
|
| 5198 |
|
|
--MD1_c_a_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_30
|
| 5199 |
|
|
--operation mode is normal
|
| 5200 |
|
|
|
| 5201 |
|
|
MD1_c_a_30 = !UD1_shift_out_30 & !VD1_un24_res # !VD1_hilo_62;
|
| 5202 |
|
|
|
| 5203 |
|
|
|
| 5204 |
|
|
--TD1_m97 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m97
|
| 5205 |
|
|
--operation mode is normal
|
| 5206 |
|
|
|
| 5207 |
|
|
TD1_m97 = RC1_alu_func_o_4 & TD1_m96 # !RC1_alu_func_o_4 & !TD1_un1_a_add30 # !TD1_alu_out_sn_m14_0_0;
|
| 5208 |
|
|
|
| 5209 |
|
|
|
| 5210 |
|
|
--AB1_c_10 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_10
|
| 5211 |
|
|
--operation mode is normal
|
| 5212 |
|
|
|
| 5213 |
|
|
AB1_c_10 = MD1_c_0_11 # UD1_shift_out_sn_m31_i & !MD1_c_a_12 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_11;
|
| 5214 |
|
|
|
| 5215 |
|
|
--AB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_10
|
| 5216 |
|
|
--operation mode is normal
|
| 5217 |
|
|
|
| 5218 |
|
|
AB1_r32_o_10 = DFFEAS(AB1_c_10, E1__clk0, VCC, , , , , , );
|
| 5219 |
|
|
|
| 5220 |
|
|
|
| 5221 |
|
|
--QC1_dmem_ctl_o_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15|dmem_ctl_o_3
|
| 5222 |
|
|
--operation mode is normal
|
| 5223 |
|
|
|
| 5224 |
|
|
QC1_dmem_ctl_o_3_lut_out = CC1_dmem_ctl_o_3;
|
| 5225 |
|
|
QC1_dmem_ctl_o_3 = DFFEAS(QC1_dmem_ctl_o_3_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 5226 |
|
|
|
| 5227 |
|
|
|
| 5228 |
|
|
--AB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_22
|
| 5229 |
|
|
--operation mode is normal
|
| 5230 |
|
|
|
| 5231 |
|
|
AB1_r32_o_22_lut_out = MD1_c_0_23 # UD1_shift_out_sn_m31_i & MD1_c_a_24 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_23;
|
| 5232 |
|
|
AB1_r32_o_22 = DFFEAS(AB1_r32_o_22_lut_out, E1__clk0, VCC, , , , , , );
|
| 5233 |
|
|
|
| 5234 |
|
|
|
| 5235 |
|
|
--AB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_23
|
| 5236 |
|
|
--operation mode is normal
|
| 5237 |
|
|
|
| 5238 |
|
|
AB1_r32_o_23_lut_out = MD1_c_0_24 # UD1_shift_out_sn_m31_i & MD1_c_a_25 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_24;
|
| 5239 |
|
|
AB1_r32_o_23 = DFFEAS(AB1_r32_o_23_lut_out, E1__clk0, VCC, , , , , , );
|
| 5240 |
|
|
|
| 5241 |
|
|
|
| 5242 |
|
|
--AB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_20
|
| 5243 |
|
|
--operation mode is normal
|
| 5244 |
|
|
|
| 5245 |
|
|
AB1_r32_o_20_lut_out = MD1_c_0_21 # UD1_shift_out_sn_m31_i & MD1_c_a_22 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_21;
|
| 5246 |
|
|
AB1_r32_o_20 = DFFEAS(AB1_r32_o_20_lut_out, E1__clk0, VCC, , , , , , );
|
| 5247 |
|
|
|
| 5248 |
|
|
|
| 5249 |
|
|
--AB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_21
|
| 5250 |
|
|
--operation mode is normal
|
| 5251 |
|
|
|
| 5252 |
|
|
AB1_r32_o_21_lut_out = MD1_c_0_22 # UD1_shift_out_sn_m31_i & MD1_c_a_23 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_22;
|
| 5253 |
|
|
AB1_r32_o_21 = DFFEAS(AB1_r32_o_21_lut_out, E1__clk0, VCC, , , , , , );
|
| 5254 |
|
|
|
| 5255 |
|
|
|
| 5256 |
|
|
--M1_rx_sr[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[6]
|
| 5257 |
|
|
--operation mode is normal
|
| 5258 |
|
|
|
| 5259 |
|
|
M1_rx_sr[6]_lut_out = M1_rx_sr[7];
|
| 5260 |
|
|
M1_rx_sr[6] = DFFEAS(M1_rx_sr[6]_lut_out, E1__clk0, VCC, , C1_G_570_x, , , !sys_rst, );
|
| 5261 |
|
|
|
| 5262 |
|
|
|
| 5263 |
|
|
--JE1_q_a[6] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[6]
|
| 5264 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 5265 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 5266 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 5267 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 5268 |
|
|
JE1_q_a[6]_PORT_A_data_in = ~GND;
|
| 5269 |
|
|
JE1_q_a[6]_PORT_A_data_in_reg = DFFE(JE1_q_a[6]_PORT_A_data_in, JE1_q_a[6]_clock_0, , , );
|
| 5270 |
|
|
JE1_q_a[6]_PORT_B_data_in = TB1_dout_1_6;
|
| 5271 |
|
|
JE1_q_a[6]_PORT_B_data_in_reg = DFFE(JE1_q_a[6]_PORT_B_data_in, JE1_q_a[6]_clock_0, , , );
|
| 5272 |
|
|
JE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5273 |
|
|
JE1_q_a[6]_PORT_A_address_reg = DFFE(JE1_q_a[6]_PORT_A_address, JE1_q_a[6]_clock_0, , , );
|
| 5274 |
|
|
JE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5275 |
|
|
JE1_q_a[6]_PORT_B_address_reg = DFFE(JE1_q_a[6]_PORT_B_address, JE1_q_a[6]_clock_0, , , );
|
| 5276 |
|
|
JE1_q_a[6]_PORT_A_write_enable = GND;
|
| 5277 |
|
|
JE1_q_a[6]_PORT_A_write_enable_reg = DFFE(JE1_q_a[6]_PORT_A_write_enable, JE1_q_a[6]_clock_0, , , );
|
| 5278 |
|
|
JE1_q_a[6]_PORT_B_write_enable = WB3L2;
|
| 5279 |
|
|
JE1_q_a[6]_PORT_B_write_enable_reg = DFFE(JE1_q_a[6]_PORT_B_write_enable, JE1_q_a[6]_clock_0, , , );
|
| 5280 |
|
|
JE1_q_a[6]_clock_0 = E1__clk0;
|
| 5281 |
|
|
JE1_q_a[6]_PORT_A_data_out = MEMORY(JE1_q_a[6]_PORT_A_data_in_reg, JE1_q_a[6]_PORT_B_data_in_reg, JE1_q_a[6]_PORT_A_address_reg, JE1_q_a[6]_PORT_B_address_reg, JE1_q_a[6]_PORT_A_write_enable_reg, JE1_q_a[6]_PORT_B_write_enable_reg, , , JE1_q_a[6]_clock_0, , , , , );
|
| 5282 |
|
|
JE1_q_a[6] = JE1_q_a[6]_PORT_A_data_out[0];
|
| 5283 |
|
|
|
| 5284 |
|
|
--JE1_q_b[6] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[6]
|
| 5285 |
|
|
JE1_q_b[6]_PORT_A_data_in = ~GND;
|
| 5286 |
|
|
JE1_q_b[6]_PORT_A_data_in_reg = DFFE(JE1_q_b[6]_PORT_A_data_in, JE1_q_b[6]_clock_0, , , );
|
| 5287 |
|
|
JE1_q_b[6]_PORT_B_data_in = TB1_dout_1_6;
|
| 5288 |
|
|
JE1_q_b[6]_PORT_B_data_in_reg = DFFE(JE1_q_b[6]_PORT_B_data_in, JE1_q_b[6]_clock_0, , , );
|
| 5289 |
|
|
JE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5290 |
|
|
JE1_q_b[6]_PORT_A_address_reg = DFFE(JE1_q_b[6]_PORT_A_address, JE1_q_b[6]_clock_0, , , );
|
| 5291 |
|
|
JE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5292 |
|
|
JE1_q_b[6]_PORT_B_address_reg = DFFE(JE1_q_b[6]_PORT_B_address, JE1_q_b[6]_clock_0, , , );
|
| 5293 |
|
|
JE1_q_b[6]_PORT_A_write_enable = GND;
|
| 5294 |
|
|
JE1_q_b[6]_PORT_A_write_enable_reg = DFFE(JE1_q_b[6]_PORT_A_write_enable, JE1_q_b[6]_clock_0, , , );
|
| 5295 |
|
|
JE1_q_b[6]_PORT_B_write_enable = WB3L2;
|
| 5296 |
|
|
JE1_q_b[6]_PORT_B_write_enable_reg = DFFE(JE1_q_b[6]_PORT_B_write_enable, JE1_q_b[6]_clock_0, , , );
|
| 5297 |
|
|
JE1_q_b[6]_clock_0 = E1__clk0;
|
| 5298 |
|
|
JE1_q_b[6]_PORT_B_data_out = MEMORY(JE1_q_b[6]_PORT_A_data_in_reg, JE1_q_b[6]_PORT_B_data_in_reg, JE1_q_b[6]_PORT_A_address_reg, JE1_q_b[6]_PORT_B_address_reg, JE1_q_b[6]_PORT_A_write_enable_reg, JE1_q_b[6]_PORT_B_write_enable_reg, , , JE1_q_b[6]_clock_0, , , , , );
|
| 5299 |
|
|
JE1_q_b[6] = JE1_q_b[6]_PORT_B_data_out[0];
|
| 5300 |
|
|
|
| 5301 |
|
|
|
| 5302 |
|
|
--UB1_dout_2_i_o2[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_o2[3]
|
| 5303 |
|
|
--operation mode is normal
|
| 5304 |
|
|
|
| 5305 |
|
|
UB1_dout_2_i_o2[3] = UB1_dout_2_i_i_o2_0[7] # !RB1_ctl_o_1 & !RB1_ctl_o_2 & !RB1_byte_addr_o_1;
|
| 5306 |
|
|
|
| 5307 |
|
|
|
| 5308 |
|
|
--UB1_dout_2_i_0_a2_x[6] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[6]
|
| 5309 |
|
|
--operation mode is normal
|
| 5310 |
|
|
|
| 5311 |
|
|
UB1_dout_2_i_0_a2_x[6] = !GE1_q_b[6] & UB1_dout_2_i_o2_0[3];
|
| 5312 |
|
|
|
| 5313 |
|
|
|
| 5314 |
|
|
--UB1_dout_2_i_0_a[6] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[6]
|
| 5315 |
|
|
--operation mode is normal
|
| 5316 |
|
|
|
| 5317 |
|
|
UB1_dout_2_i_0_a[6] = HE1_q_b[6] & !KE1_q_b[6] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[6] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[6] & UB1_dout_2_i_a3_0[3];
|
| 5318 |
|
|
|
| 5319 |
|
|
|
| 5320 |
|
|
--VD1_b_o_iv_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_8
|
| 5321 |
|
|
--operation mode is normal
|
| 5322 |
|
|
|
| 5323 |
|
|
VD1_b_o_iv_8 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[8] & !G1_BUS15471_i_m[8] & AB1_r32_o_6 # !QD1_b_o_0_sqmuxa;
|
| 5324 |
|
|
|
| 5325 |
|
|
--VD1_op2_reged[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[8]
|
| 5326 |
|
|
--operation mode is normal
|
| 5327 |
|
|
|
| 5328 |
|
|
VD1_op2_reged[8] = DFFEAS(VD1_b_o_iv_8, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 5329 |
|
|
|
| 5330 |
|
|
|
| 5331 |
|
|
--UD1_shift_out_87_d[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[6]
|
| 5332 |
|
|
--operation mode is normal
|
| 5333 |
|
|
|
| 5334 |
|
|
UD1_shift_out_87_d[6] = PD1_a_o_0 & UD1_shift_out_80[6] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[6];
|
| 5335 |
|
|
|
| 5336 |
|
|
|
| 5337 |
|
|
--UD1_shift_out_85_d[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[6]
|
| 5338 |
|
|
--operation mode is normal
|
| 5339 |
|
|
|
| 5340 |
|
|
UD1_shift_out_85_d[6] = PD1_a_o_2 & UD1_shift_out_43[30] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[6];
|
| 5341 |
|
|
|
| 5342 |
|
|
|
| 5343 |
|
|
--MD1_c_1_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_a[6]
|
| 5344 |
|
|
--operation mode is normal
|
| 5345 |
|
|
|
| 5346 |
|
|
MD1_c_1_a[6] = VD1_un24_res & !VD1_hilo_38 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_6;
|
| 5347 |
|
|
|
| 5348 |
|
|
|
| 5349 |
|
|
--TD1_alu_out_0_a2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_0
|
| 5350 |
|
|
--operation mode is normal
|
| 5351 |
|
|
|
| 5352 |
|
|
TD1_alu_out_0_a2_0 = TD1_alu_out_sn_m14_0_0 & PD1_a_o_6 & !TD1_alu_out_0_a2_a[6] # !PD1_a_o_6 & TD1_alu_out_7_0_0_m4_0[6];
|
| 5353 |
|
|
|
| 5354 |
|
|
|
| 5355 |
|
|
--PD1_a_o_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_6
|
| 5356 |
|
|
--operation mode is normal
|
| 5357 |
|
|
|
| 5358 |
|
|
PD1_a_o_6 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[6] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[6];
|
| 5359 |
|
|
|
| 5360 |
|
|
|
| 5361 |
|
|
--TD1_un1_b_1_combout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[6]
|
| 5362 |
|
|
--operation mode is normal
|
| 5363 |
|
|
|
| 5364 |
|
|
TD1_un1_b_1_combout[6] = TD1_sum13_0_a2 $ !VD1_b_o_iv_6;
|
| 5365 |
|
|
|
| 5366 |
|
|
|
| 5367 |
|
|
--UD1_shift_out_91_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[6]
|
| 5368 |
|
|
--operation mode is normal
|
| 5369 |
|
|
|
| 5370 |
|
|
UD1_shift_out_91_a[6] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_6 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[6];
|
| 5371 |
|
|
|
| 5372 |
|
|
|
| 5373 |
|
|
--UD1_shift_out_76[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[6]
|
| 5374 |
|
|
--operation mode is normal
|
| 5375 |
|
|
|
| 5376 |
|
|
UD1_shift_out_76[6] = UD1_shift_out587 & UD1_shift_out_76_a[6] & UD1_shift_out_79[18] # !PD1_a_o_2;
|
| 5377 |
|
|
|
| 5378 |
|
|
|
| 5379 |
|
|
--UD1_shift_out_86_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[6]
|
| 5380 |
|
|
--operation mode is normal
|
| 5381 |
|
|
|
| 5382 |
|
|
UD1_shift_out_86_a[6] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[10] # !PD1_a_o_2 & !UD1_shift_out_47[2] # !UD1_shift_out587 & !UD1_shift_out_79[10];
|
| 5383 |
|
|
|
| 5384 |
|
|
|
| 5385 |
|
|
--UD1_shift_out_74[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[6]
|
| 5386 |
|
|
--operation mode is normal
|
| 5387 |
|
|
|
| 5388 |
|
|
UD1_shift_out_74[6] = PD1_a_o_3 & !UD1_shift_out_74_a[6] # !PD1_a_o_3 & UD1_shift_out_61[6];
|
| 5389 |
|
|
|
| 5390 |
|
|
|
| 5391 |
|
|
--M1_rx_sr[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[5]
|
| 5392 |
|
|
--operation mode is normal
|
| 5393 |
|
|
|
| 5394 |
|
|
M1_rx_sr[5]_lut_out = M1_rx_sr[6];
|
| 5395 |
|
|
M1_rx_sr[5] = DFFEAS(M1_rx_sr[5]_lut_out, E1__clk0, VCC, , C1_G_570_x, , , !sys_rst, );
|
| 5396 |
|
|
|
| 5397 |
|
|
|
| 5398 |
|
|
--JE1_q_a[5] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[5]
|
| 5399 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 5400 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 5401 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 5402 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 5403 |
|
|
JE1_q_a[5]_PORT_A_data_in = ~GND;
|
| 5404 |
|
|
JE1_q_a[5]_PORT_A_data_in_reg = DFFE(JE1_q_a[5]_PORT_A_data_in, JE1_q_a[5]_clock_0, , , );
|
| 5405 |
|
|
JE1_q_a[5]_PORT_B_data_in = TB1_dout_1_5;
|
| 5406 |
|
|
JE1_q_a[5]_PORT_B_data_in_reg = DFFE(JE1_q_a[5]_PORT_B_data_in, JE1_q_a[5]_clock_0, , , );
|
| 5407 |
|
|
JE1_q_a[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5408 |
|
|
JE1_q_a[5]_PORT_A_address_reg = DFFE(JE1_q_a[5]_PORT_A_address, JE1_q_a[5]_clock_0, , , );
|
| 5409 |
|
|
JE1_q_a[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5410 |
|
|
JE1_q_a[5]_PORT_B_address_reg = DFFE(JE1_q_a[5]_PORT_B_address, JE1_q_a[5]_clock_0, , , );
|
| 5411 |
|
|
JE1_q_a[5]_PORT_A_write_enable = GND;
|
| 5412 |
|
|
JE1_q_a[5]_PORT_A_write_enable_reg = DFFE(JE1_q_a[5]_PORT_A_write_enable, JE1_q_a[5]_clock_0, , , );
|
| 5413 |
|
|
JE1_q_a[5]_PORT_B_write_enable = WB3L2;
|
| 5414 |
|
|
JE1_q_a[5]_PORT_B_write_enable_reg = DFFE(JE1_q_a[5]_PORT_B_write_enable, JE1_q_a[5]_clock_0, , , );
|
| 5415 |
|
|
JE1_q_a[5]_clock_0 = E1__clk0;
|
| 5416 |
|
|
JE1_q_a[5]_PORT_A_data_out = MEMORY(JE1_q_a[5]_PORT_A_data_in_reg, JE1_q_a[5]_PORT_B_data_in_reg, JE1_q_a[5]_PORT_A_address_reg, JE1_q_a[5]_PORT_B_address_reg, JE1_q_a[5]_PORT_A_write_enable_reg, JE1_q_a[5]_PORT_B_write_enable_reg, , , JE1_q_a[5]_clock_0, , , , , );
|
| 5417 |
|
|
JE1_q_a[5] = JE1_q_a[5]_PORT_A_data_out[0];
|
| 5418 |
|
|
|
| 5419 |
|
|
--JE1_q_b[5] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[5]
|
| 5420 |
|
|
JE1_q_b[5]_PORT_A_data_in = ~GND;
|
| 5421 |
|
|
JE1_q_b[5]_PORT_A_data_in_reg = DFFE(JE1_q_b[5]_PORT_A_data_in, JE1_q_b[5]_clock_0, , , );
|
| 5422 |
|
|
JE1_q_b[5]_PORT_B_data_in = TB1_dout_1_5;
|
| 5423 |
|
|
JE1_q_b[5]_PORT_B_data_in_reg = DFFE(JE1_q_b[5]_PORT_B_data_in, JE1_q_b[5]_clock_0, , , );
|
| 5424 |
|
|
JE1_q_b[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5425 |
|
|
JE1_q_b[5]_PORT_A_address_reg = DFFE(JE1_q_b[5]_PORT_A_address, JE1_q_b[5]_clock_0, , , );
|
| 5426 |
|
|
JE1_q_b[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5427 |
|
|
JE1_q_b[5]_PORT_B_address_reg = DFFE(JE1_q_b[5]_PORT_B_address, JE1_q_b[5]_clock_0, , , );
|
| 5428 |
|
|
JE1_q_b[5]_PORT_A_write_enable = GND;
|
| 5429 |
|
|
JE1_q_b[5]_PORT_A_write_enable_reg = DFFE(JE1_q_b[5]_PORT_A_write_enable, JE1_q_b[5]_clock_0, , , );
|
| 5430 |
|
|
JE1_q_b[5]_PORT_B_write_enable = WB3L2;
|
| 5431 |
|
|
JE1_q_b[5]_PORT_B_write_enable_reg = DFFE(JE1_q_b[5]_PORT_B_write_enable, JE1_q_b[5]_clock_0, , , );
|
| 5432 |
|
|
JE1_q_b[5]_clock_0 = E1__clk0;
|
| 5433 |
|
|
JE1_q_b[5]_PORT_B_data_out = MEMORY(JE1_q_b[5]_PORT_A_data_in_reg, JE1_q_b[5]_PORT_B_data_in_reg, JE1_q_b[5]_PORT_A_address_reg, JE1_q_b[5]_PORT_B_address_reg, JE1_q_b[5]_PORT_A_write_enable_reg, JE1_q_b[5]_PORT_B_write_enable_reg, , , JE1_q_b[5]_clock_0, , , , , );
|
| 5434 |
|
|
JE1_q_b[5] = JE1_q_b[5]_PORT_B_data_out[0];
|
| 5435 |
|
|
|
| 5436 |
|
|
|
| 5437 |
|
|
--UB1_dout_2_i_0_a2_x[5] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[5]
|
| 5438 |
|
|
--operation mode is normal
|
| 5439 |
|
|
|
| 5440 |
|
|
UB1_dout_2_i_0_a2_x[5] = !GE1_q_b[5] & UB1_dout_2_i_o2_0[3];
|
| 5441 |
|
|
|
| 5442 |
|
|
|
| 5443 |
|
|
--UB1_dout_2_i_0_a[5] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[5]
|
| 5444 |
|
|
--operation mode is normal
|
| 5445 |
|
|
|
| 5446 |
|
|
UB1_dout_2_i_0_a[5] = HE1_q_b[5] & !KE1_q_b[5] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[5] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[5] & UB1_dout_2_i_a3_0[3];
|
| 5447 |
|
|
|
| 5448 |
|
|
|
| 5449 |
|
|
--M1_rx_sr[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[4]
|
| 5450 |
|
|
--operation mode is normal
|
| 5451 |
|
|
|
| 5452 |
|
|
M1_rx_sr[4]_lut_out = M1_rx_sr[5];
|
| 5453 |
|
|
M1_rx_sr[4] = DFFEAS(M1_rx_sr[4]_lut_out, E1__clk0, VCC, , C1_G_570_x, , , !sys_rst, );
|
| 5454 |
|
|
|
| 5455 |
|
|
|
| 5456 |
|
|
--UB1_dout_2_i_0_a2_x[4] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[4]
|
| 5457 |
|
|
--operation mode is normal
|
| 5458 |
|
|
|
| 5459 |
|
|
UB1_dout_2_i_0_a2_x[4] = !GE1_q_b[4] & UB1_dout_2_i_o2_0[3];
|
| 5460 |
|
|
|
| 5461 |
|
|
|
| 5462 |
|
|
--UB1_dout_2_i_0_a[4] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[4]
|
| 5463 |
|
|
--operation mode is normal
|
| 5464 |
|
|
|
| 5465 |
|
|
UB1_dout_2_i_0_a[4] = KE1_q_b[4] & !HE1_q_b[4] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[4] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[4] & UB1_dout_2_i_a3_1[3];
|
| 5466 |
|
|
|
| 5467 |
|
|
|
| 5468 |
|
|
--M1_rx_sr[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[3]
|
| 5469 |
|
|
--operation mode is normal
|
| 5470 |
|
|
|
| 5471 |
|
|
M1_rx_sr[3]_lut_out = M1_rx_sr[4];
|
| 5472 |
|
|
M1_rx_sr[3] = DFFEAS(M1_rx_sr[3]_lut_out, E1__clk0, VCC, , C1_G_570_x, , , !sys_rst, );
|
| 5473 |
|
|
|
| 5474 |
|
|
|
| 5475 |
|
|
--F1_dout_0_0_a3_6_5_14[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_14[0]
|
| 5476 |
|
|
--operation mode is normal
|
| 5477 |
|
|
|
| 5478 |
|
|
F1_dout_0_0_a3_6_5_14[0] = !AB1_r32_o_0 & !AB1_r32_o_3 & F1_dout_0_0_a3_6_5_14_a[0] & F1_dout_0_0_a3_6_3[0];
|
| 5479 |
|
|
|
| 5480 |
|
|
|
| 5481 |
|
|
--F1_dout_0_0_a3_6_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_a[0]
|
| 5482 |
|
|
--operation mode is normal
|
| 5483 |
|
|
|
| 5484 |
|
|
F1_dout_0_0_a3_6_a[0] = !F1_dout_0_0_a3_6_5_9[0] # !F1_dout_0_0_a3_6_5_8[0] # !JC1_rd_status_29_0_a2_0_7;
|
| 5485 |
|
|
|
| 5486 |
|
|
|
| 5487 |
|
|
--M1_ua_state[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state[4]
|
| 5488 |
|
|
--operation mode is normal
|
| 5489 |
|
|
|
| 5490 |
|
|
M1_ua_state[4]_lut_out = M1_ua_state_2 & M1_clk_ctr_equ15_0_a2;
|
| 5491 |
|
|
M1_ua_state[4] = DFFEAS(M1_ua_state[4]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 5492 |
|
|
|
| 5493 |
|
|
|
| 5494 |
|
|
--JE1_q_a[3] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[3]
|
| 5495 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 5496 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 5497 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 5498 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 5499 |
|
|
JE1_q_a[3]_PORT_A_data_in = ~GND;
|
| 5500 |
|
|
JE1_q_a[3]_PORT_A_data_in_reg = DFFE(JE1_q_a[3]_PORT_A_data_in, JE1_q_a[3]_clock_0, , , );
|
| 5501 |
|
|
JE1_q_a[3]_PORT_B_data_in = TB1_dout_1_3;
|
| 5502 |
|
|
JE1_q_a[3]_PORT_B_data_in_reg = DFFE(JE1_q_a[3]_PORT_B_data_in, JE1_q_a[3]_clock_0, , , );
|
| 5503 |
|
|
JE1_q_a[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5504 |
|
|
JE1_q_a[3]_PORT_A_address_reg = DFFE(JE1_q_a[3]_PORT_A_address, JE1_q_a[3]_clock_0, , , );
|
| 5505 |
|
|
JE1_q_a[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5506 |
|
|
JE1_q_a[3]_PORT_B_address_reg = DFFE(JE1_q_a[3]_PORT_B_address, JE1_q_a[3]_clock_0, , , );
|
| 5507 |
|
|
JE1_q_a[3]_PORT_A_write_enable = GND;
|
| 5508 |
|
|
JE1_q_a[3]_PORT_A_write_enable_reg = DFFE(JE1_q_a[3]_PORT_A_write_enable, JE1_q_a[3]_clock_0, , , );
|
| 5509 |
|
|
JE1_q_a[3]_PORT_B_write_enable = WB3L2;
|
| 5510 |
|
|
JE1_q_a[3]_PORT_B_write_enable_reg = DFFE(JE1_q_a[3]_PORT_B_write_enable, JE1_q_a[3]_clock_0, , , );
|
| 5511 |
|
|
JE1_q_a[3]_clock_0 = E1__clk0;
|
| 5512 |
|
|
JE1_q_a[3]_PORT_A_data_out = MEMORY(JE1_q_a[3]_PORT_A_data_in_reg, JE1_q_a[3]_PORT_B_data_in_reg, JE1_q_a[3]_PORT_A_address_reg, JE1_q_a[3]_PORT_B_address_reg, JE1_q_a[3]_PORT_A_write_enable_reg, JE1_q_a[3]_PORT_B_write_enable_reg, , , JE1_q_a[3]_clock_0, , , , , );
|
| 5513 |
|
|
JE1_q_a[3] = JE1_q_a[3]_PORT_A_data_out[0];
|
| 5514 |
|
|
|
| 5515 |
|
|
--JE1_q_b[3] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[3]
|
| 5516 |
|
|
JE1_q_b[3]_PORT_A_data_in = ~GND;
|
| 5517 |
|
|
JE1_q_b[3]_PORT_A_data_in_reg = DFFE(JE1_q_b[3]_PORT_A_data_in, JE1_q_b[3]_clock_0, , , );
|
| 5518 |
|
|
JE1_q_b[3]_PORT_B_data_in = TB1_dout_1_3;
|
| 5519 |
|
|
JE1_q_b[3]_PORT_B_data_in_reg = DFFE(JE1_q_b[3]_PORT_B_data_in, JE1_q_b[3]_clock_0, , , );
|
| 5520 |
|
|
JE1_q_b[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5521 |
|
|
JE1_q_b[3]_PORT_A_address_reg = DFFE(JE1_q_b[3]_PORT_A_address, JE1_q_b[3]_clock_0, , , );
|
| 5522 |
|
|
JE1_q_b[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5523 |
|
|
JE1_q_b[3]_PORT_B_address_reg = DFFE(JE1_q_b[3]_PORT_B_address, JE1_q_b[3]_clock_0, , , );
|
| 5524 |
|
|
JE1_q_b[3]_PORT_A_write_enable = GND;
|
| 5525 |
|
|
JE1_q_b[3]_PORT_A_write_enable_reg = DFFE(JE1_q_b[3]_PORT_A_write_enable, JE1_q_b[3]_clock_0, , , );
|
| 5526 |
|
|
JE1_q_b[3]_PORT_B_write_enable = WB3L2;
|
| 5527 |
|
|
JE1_q_b[3]_PORT_B_write_enable_reg = DFFE(JE1_q_b[3]_PORT_B_write_enable, JE1_q_b[3]_clock_0, , , );
|
| 5528 |
|
|
JE1_q_b[3]_clock_0 = E1__clk0;
|
| 5529 |
|
|
JE1_q_b[3]_PORT_B_data_out = MEMORY(JE1_q_b[3]_PORT_A_data_in_reg, JE1_q_b[3]_PORT_B_data_in_reg, JE1_q_b[3]_PORT_A_address_reg, JE1_q_b[3]_PORT_B_address_reg, JE1_q_b[3]_PORT_A_write_enable_reg, JE1_q_b[3]_PORT_B_write_enable_reg, , , JE1_q_b[3]_clock_0, , , , , );
|
| 5530 |
|
|
JE1_q_b[3] = JE1_q_b[3]_PORT_B_data_out[0];
|
| 5531 |
|
|
|
| 5532 |
|
|
|
| 5533 |
|
|
--UB1_dout_2_i_a2_x[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_a2_x[3]
|
| 5534 |
|
|
--operation mode is normal
|
| 5535 |
|
|
|
| 5536 |
|
|
UB1_dout_2_i_a2_x[3] = !GE1_q_b[3] & UB1_dout_2_i_o2_0[3];
|
| 5537 |
|
|
|
| 5538 |
|
|
|
| 5539 |
|
|
--UB1_dout_2_i_a[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_a[3]
|
| 5540 |
|
|
--operation mode is normal
|
| 5541 |
|
|
|
| 5542 |
|
|
UB1_dout_2_i_a[3] = HE1_q_b[3] & !KE1_q_b[3] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[3] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[3] & UB1_dout_2_i_a3_0[3];
|
| 5543 |
|
|
|
| 5544 |
|
|
|
| 5545 |
|
|
--M1_rx_sr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[2]
|
| 5546 |
|
|
--operation mode is normal
|
| 5547 |
|
|
|
| 5548 |
|
|
M1_rx_sr[2]_lut_out = M1_rx_sr[3];
|
| 5549 |
|
|
M1_rx_sr[2] = DFFEAS(M1_rx_sr[2]_lut_out, E1__clk0, VCC, , C1_G_570_x, , , !sys_rst, );
|
| 5550 |
|
|
|
| 5551 |
|
|
|
| 5552 |
|
|
--JE1_q_a[2] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[2]
|
| 5553 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 5554 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 5555 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 5556 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 5557 |
|
|
JE1_q_a[2]_PORT_A_data_in = ~GND;
|
| 5558 |
|
|
JE1_q_a[2]_PORT_A_data_in_reg = DFFE(JE1_q_a[2]_PORT_A_data_in, JE1_q_a[2]_clock_0, , , );
|
| 5559 |
|
|
JE1_q_a[2]_PORT_B_data_in = TB1_dout_1_2;
|
| 5560 |
|
|
JE1_q_a[2]_PORT_B_data_in_reg = DFFE(JE1_q_a[2]_PORT_B_data_in, JE1_q_a[2]_clock_0, , , );
|
| 5561 |
|
|
JE1_q_a[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5562 |
|
|
JE1_q_a[2]_PORT_A_address_reg = DFFE(JE1_q_a[2]_PORT_A_address, JE1_q_a[2]_clock_0, , , );
|
| 5563 |
|
|
JE1_q_a[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5564 |
|
|
JE1_q_a[2]_PORT_B_address_reg = DFFE(JE1_q_a[2]_PORT_B_address, JE1_q_a[2]_clock_0, , , );
|
| 5565 |
|
|
JE1_q_a[2]_PORT_A_write_enable = GND;
|
| 5566 |
|
|
JE1_q_a[2]_PORT_A_write_enable_reg = DFFE(JE1_q_a[2]_PORT_A_write_enable, JE1_q_a[2]_clock_0, , , );
|
| 5567 |
|
|
JE1_q_a[2]_PORT_B_write_enable = WB3L2;
|
| 5568 |
|
|
JE1_q_a[2]_PORT_B_write_enable_reg = DFFE(JE1_q_a[2]_PORT_B_write_enable, JE1_q_a[2]_clock_0, , , );
|
| 5569 |
|
|
JE1_q_a[2]_clock_0 = E1__clk0;
|
| 5570 |
|
|
JE1_q_a[2]_PORT_A_data_out = MEMORY(JE1_q_a[2]_PORT_A_data_in_reg, JE1_q_a[2]_PORT_B_data_in_reg, JE1_q_a[2]_PORT_A_address_reg, JE1_q_a[2]_PORT_B_address_reg, JE1_q_a[2]_PORT_A_write_enable_reg, JE1_q_a[2]_PORT_B_write_enable_reg, , , JE1_q_a[2]_clock_0, , , , , );
|
| 5571 |
|
|
JE1_q_a[2] = JE1_q_a[2]_PORT_A_data_out[0];
|
| 5572 |
|
|
|
| 5573 |
|
|
--JE1_q_b[2] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[2]
|
| 5574 |
|
|
JE1_q_b[2]_PORT_A_data_in = ~GND;
|
| 5575 |
|
|
JE1_q_b[2]_PORT_A_data_in_reg = DFFE(JE1_q_b[2]_PORT_A_data_in, JE1_q_b[2]_clock_0, , , );
|
| 5576 |
|
|
JE1_q_b[2]_PORT_B_data_in = TB1_dout_1_2;
|
| 5577 |
|
|
JE1_q_b[2]_PORT_B_data_in_reg = DFFE(JE1_q_b[2]_PORT_B_data_in, JE1_q_b[2]_clock_0, , , );
|
| 5578 |
|
|
JE1_q_b[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5579 |
|
|
JE1_q_b[2]_PORT_A_address_reg = DFFE(JE1_q_b[2]_PORT_A_address, JE1_q_b[2]_clock_0, , , );
|
| 5580 |
|
|
JE1_q_b[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5581 |
|
|
JE1_q_b[2]_PORT_B_address_reg = DFFE(JE1_q_b[2]_PORT_B_address, JE1_q_b[2]_clock_0, , , );
|
| 5582 |
|
|
JE1_q_b[2]_PORT_A_write_enable = GND;
|
| 5583 |
|
|
JE1_q_b[2]_PORT_A_write_enable_reg = DFFE(JE1_q_b[2]_PORT_A_write_enable, JE1_q_b[2]_clock_0, , , );
|
| 5584 |
|
|
JE1_q_b[2]_PORT_B_write_enable = WB3L2;
|
| 5585 |
|
|
JE1_q_b[2]_PORT_B_write_enable_reg = DFFE(JE1_q_b[2]_PORT_B_write_enable, JE1_q_b[2]_clock_0, , , );
|
| 5586 |
|
|
JE1_q_b[2]_clock_0 = E1__clk0;
|
| 5587 |
|
|
JE1_q_b[2]_PORT_B_data_out = MEMORY(JE1_q_b[2]_PORT_A_data_in_reg, JE1_q_b[2]_PORT_B_data_in_reg, JE1_q_b[2]_PORT_A_address_reg, JE1_q_b[2]_PORT_B_address_reg, JE1_q_b[2]_PORT_A_write_enable_reg, JE1_q_b[2]_PORT_B_write_enable_reg, , , JE1_q_b[2]_clock_0, , , , , );
|
| 5588 |
|
|
JE1_q_b[2] = JE1_q_b[2]_PORT_B_data_out[0];
|
| 5589 |
|
|
|
| 5590 |
|
|
|
| 5591 |
|
|
--UB1_dout_2_i_0_a2_x[2] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[2]
|
| 5592 |
|
|
--operation mode is normal
|
| 5593 |
|
|
|
| 5594 |
|
|
UB1_dout_2_i_0_a2_x[2] = !GE1_q_b[2] & UB1_dout_2_i_o2_0[3];
|
| 5595 |
|
|
|
| 5596 |
|
|
|
| 5597 |
|
|
--UB1_dout_2_i_0_a[2] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[2]
|
| 5598 |
|
|
--operation mode is normal
|
| 5599 |
|
|
|
| 5600 |
|
|
UB1_dout_2_i_0_a[2] = KE1_q_b[2] & !HE1_q_b[2] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[2] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[2] & UB1_dout_2_i_a3_1[3];
|
| 5601 |
|
|
|
| 5602 |
|
|
|
| 5603 |
|
|
--M1_rx_sr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[1]
|
| 5604 |
|
|
--operation mode is normal
|
| 5605 |
|
|
|
| 5606 |
|
|
M1_rx_sr[1]_lut_out = M1_rx_sr[2];
|
| 5607 |
|
|
M1_rx_sr[1] = DFFEAS(M1_rx_sr[1]_lut_out, E1__clk0, VCC, , C1_G_570_x, , , !sys_rst, );
|
| 5608 |
|
|
|
| 5609 |
|
|
|
| 5610 |
|
|
--JE1_q_a[1] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[1]
|
| 5611 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 5612 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 5613 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 5614 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 5615 |
|
|
JE1_q_a[1]_PORT_A_data_in = ~GND;
|
| 5616 |
|
|
JE1_q_a[1]_PORT_A_data_in_reg = DFFE(JE1_q_a[1]_PORT_A_data_in, JE1_q_a[1]_clock_0, , , );
|
| 5617 |
|
|
JE1_q_a[1]_PORT_B_data_in = TB1_dout_1_1;
|
| 5618 |
|
|
JE1_q_a[1]_PORT_B_data_in_reg = DFFE(JE1_q_a[1]_PORT_B_data_in, JE1_q_a[1]_clock_0, , , );
|
| 5619 |
|
|
JE1_q_a[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5620 |
|
|
JE1_q_a[1]_PORT_A_address_reg = DFFE(JE1_q_a[1]_PORT_A_address, JE1_q_a[1]_clock_0, , , );
|
| 5621 |
|
|
JE1_q_a[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5622 |
|
|
JE1_q_a[1]_PORT_B_address_reg = DFFE(JE1_q_a[1]_PORT_B_address, JE1_q_a[1]_clock_0, , , );
|
| 5623 |
|
|
JE1_q_a[1]_PORT_A_write_enable = GND;
|
| 5624 |
|
|
JE1_q_a[1]_PORT_A_write_enable_reg = DFFE(JE1_q_a[1]_PORT_A_write_enable, JE1_q_a[1]_clock_0, , , );
|
| 5625 |
|
|
JE1_q_a[1]_PORT_B_write_enable = WB3L2;
|
| 5626 |
|
|
JE1_q_a[1]_PORT_B_write_enable_reg = DFFE(JE1_q_a[1]_PORT_B_write_enable, JE1_q_a[1]_clock_0, , , );
|
| 5627 |
|
|
JE1_q_a[1]_clock_0 = E1__clk0;
|
| 5628 |
|
|
JE1_q_a[1]_PORT_A_data_out = MEMORY(JE1_q_a[1]_PORT_A_data_in_reg, JE1_q_a[1]_PORT_B_data_in_reg, JE1_q_a[1]_PORT_A_address_reg, JE1_q_a[1]_PORT_B_address_reg, JE1_q_a[1]_PORT_A_write_enable_reg, JE1_q_a[1]_PORT_B_write_enable_reg, , , JE1_q_a[1]_clock_0, , , , , );
|
| 5629 |
|
|
JE1_q_a[1] = JE1_q_a[1]_PORT_A_data_out[0];
|
| 5630 |
|
|
|
| 5631 |
|
|
--JE1_q_b[1] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[1]
|
| 5632 |
|
|
JE1_q_b[1]_PORT_A_data_in = ~GND;
|
| 5633 |
|
|
JE1_q_b[1]_PORT_A_data_in_reg = DFFE(JE1_q_b[1]_PORT_A_data_in, JE1_q_b[1]_clock_0, , , );
|
| 5634 |
|
|
JE1_q_b[1]_PORT_B_data_in = TB1_dout_1_1;
|
| 5635 |
|
|
JE1_q_b[1]_PORT_B_data_in_reg = DFFE(JE1_q_b[1]_PORT_B_data_in, JE1_q_b[1]_clock_0, , , );
|
| 5636 |
|
|
JE1_q_b[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5637 |
|
|
JE1_q_b[1]_PORT_A_address_reg = DFFE(JE1_q_b[1]_PORT_A_address, JE1_q_b[1]_clock_0, , , );
|
| 5638 |
|
|
JE1_q_b[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5639 |
|
|
JE1_q_b[1]_PORT_B_address_reg = DFFE(JE1_q_b[1]_PORT_B_address, JE1_q_b[1]_clock_0, , , );
|
| 5640 |
|
|
JE1_q_b[1]_PORT_A_write_enable = GND;
|
| 5641 |
|
|
JE1_q_b[1]_PORT_A_write_enable_reg = DFFE(JE1_q_b[1]_PORT_A_write_enable, JE1_q_b[1]_clock_0, , , );
|
| 5642 |
|
|
JE1_q_b[1]_PORT_B_write_enable = WB3L2;
|
| 5643 |
|
|
JE1_q_b[1]_PORT_B_write_enable_reg = DFFE(JE1_q_b[1]_PORT_B_write_enable, JE1_q_b[1]_clock_0, , , );
|
| 5644 |
|
|
JE1_q_b[1]_clock_0 = E1__clk0;
|
| 5645 |
|
|
JE1_q_b[1]_PORT_B_data_out = MEMORY(JE1_q_b[1]_PORT_A_data_in_reg, JE1_q_b[1]_PORT_B_data_in_reg, JE1_q_b[1]_PORT_A_address_reg, JE1_q_b[1]_PORT_B_address_reg, JE1_q_b[1]_PORT_A_write_enable_reg, JE1_q_b[1]_PORT_B_write_enable_reg, , , JE1_q_b[1]_clock_0, , , , , );
|
| 5646 |
|
|
JE1_q_b[1] = JE1_q_b[1]_PORT_B_data_out[0];
|
| 5647 |
|
|
|
| 5648 |
|
|
|
| 5649 |
|
|
--UB1_dout_2_i_0_a2_x[1] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[1]
|
| 5650 |
|
|
--operation mode is normal
|
| 5651 |
|
|
|
| 5652 |
|
|
UB1_dout_2_i_0_a2_x[1] = !GE1_q_b[1] & UB1_dout_2_i_o2_0[3];
|
| 5653 |
|
|
|
| 5654 |
|
|
|
| 5655 |
|
|
--UB1_dout_2_i_0_a[1] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[1]
|
| 5656 |
|
|
--operation mode is normal
|
| 5657 |
|
|
|
| 5658 |
|
|
UB1_dout_2_i_0_a[1] = KE1_q_b[1] & !HE1_q_b[1] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[1] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[1] & UB1_dout_2_i_a3_1[3];
|
| 5659 |
|
|
|
| 5660 |
|
|
|
| 5661 |
|
|
--UD1_shift_out_80[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[1]
|
| 5662 |
|
|
--operation mode is normal
|
| 5663 |
|
|
|
| 5664 |
|
|
UD1_shift_out_80[1] = PD1_a_o_2 & UD1_shift_out_80_a[1] & VD1_b_o_iv_6 # !UD1_shift_out_80_a[1] & VD1_b_o_iv_8 # !PD1_a_o_2 & !UD1_shift_out_80_a[1];
|
| 5665 |
|
|
|
| 5666 |
|
|
|
| 5667 |
|
|
--UD1_shift_out_82[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82[1]
|
| 5668 |
|
|
--operation mode is normal
|
| 5669 |
|
|
|
| 5670 |
|
|
UD1_shift_out_82[1] = PD1_a_o_2 & PD1_a_o_1 & VD1_b_o_iv_7 # !PD1_a_o_1 & !UD1_shift_out_82_a[1] # !PD1_a_o_2 & !UD1_shift_out_82_a[1];
|
| 5671 |
|
|
|
| 5672 |
|
|
|
| 5673 |
|
|
--UD1_shift_out_86_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[1]
|
| 5674 |
|
|
--operation mode is normal
|
| 5675 |
|
|
|
| 5676 |
|
|
UD1_shift_out_86_a[1] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[5] # !PD1_a_o_2 & !UD1_shift_out_79[9] # !UD1_shift_out587 & !UD1_shift_out_79[5];
|
| 5677 |
|
|
|
| 5678 |
|
|
|
| 5679 |
|
|
--UD1_shift_out_74[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[1]
|
| 5680 |
|
|
--operation mode is normal
|
| 5681 |
|
|
|
| 5682 |
|
|
UD1_shift_out_74[1] = PD1_a_o_3 & UD1_shift_out_74_a[1] & UD1_shift_out_79[17] # !UD1_shift_out_74_a[1] & UD1_shift_out_41[1] # !PD1_a_o_3 & !UD1_shift_out_74_a[1];
|
| 5683 |
|
|
|
| 5684 |
|
|
|
| 5685 |
|
|
--UD1_shift_out_91_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[1]
|
| 5686 |
|
|
--operation mode is normal
|
| 5687 |
|
|
|
| 5688 |
|
|
UD1_shift_out_91_a[1] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_1 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[1];
|
| 5689 |
|
|
|
| 5690 |
|
|
|
| 5691 |
|
|
--UD1_shift_out_76[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[1]
|
| 5692 |
|
|
--operation mode is normal
|
| 5693 |
|
|
|
| 5694 |
|
|
UD1_shift_out_76[1] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_76_a[1] # !PD1_a_o_2 & UD1_shift_out_79[17] # !UD1_shift_out587 & !UD1_shift_out_76_a[1];
|
| 5695 |
|
|
|
| 5696 |
|
|
|
| 5697 |
|
|
--VD1_hilo_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1
|
| 5698 |
|
|
--operation mode is normal
|
| 5699 |
|
|
|
| 5700 |
|
|
VD1_hilo_1_lut_out = VD1_hilo_37_iv_0_0[1] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_1 # !VD1_hilo_37_iv_0_a[1];
|
| 5701 |
|
|
VD1_hilo_1 = DFFEAS(VD1_hilo_1_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 5702 |
|
|
|
| 5703 |
|
|
|
| 5704 |
|
|
--VD1_hilo_33 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33
|
| 5705 |
|
|
--operation mode is normal
|
| 5706 |
|
|
|
| 5707 |
|
|
VD1_hilo_33_lut_out = !VD1_hilo_37_iv_2[33] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[33] # !VD1_hilo25;
|
| 5708 |
|
|
VD1_hilo_33 = DFFEAS(VD1_hilo_33_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 5709 |
|
|
|
| 5710 |
|
|
|
| 5711 |
|
|
--TD1_alu_out_7_0_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_a[1]
|
| 5712 |
|
|
--operation mode is normal
|
| 5713 |
|
|
|
| 5714 |
|
|
TD1_alu_out_7_0_a[1] = VD1_b_o_iv_1 & !PD1_a_o_1 & RC1_alu_func_o_2 $ RC1_alu_func_o_0 # !VD1_b_o_iv_1 & RC1_alu_func_o_0 # !PD1_a_o_1;
|
| 5715 |
|
|
|
| 5716 |
|
|
|
| 5717 |
|
|
--TD1_alu_out_6_0[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_6_0[1]
|
| 5718 |
|
|
--operation mode is normal
|
| 5719 |
|
|
|
| 5720 |
|
|
TD1_alu_out_6_0[1] = RC1_alu_func_o_1 & TD1_un1_a_add1 # !RC1_alu_func_o_1 & RC1_alu_func_o_4 & TD1_alu_out_6_0_a[1] # !RC1_alu_func_o_4 & TD1_un1_a_add1;
|
| 5721 |
|
|
|
| 5722 |
|
|
|
| 5723 |
|
|
--M1_rx_sr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[0]
|
| 5724 |
|
|
--operation mode is normal
|
| 5725 |
|
|
|
| 5726 |
|
|
M1_rx_sr[0]_lut_out = M1_rx_sr[1];
|
| 5727 |
|
|
M1_rx_sr[0] = DFFEAS(M1_rx_sr[0]_lut_out, E1__clk0, VCC, , C1_G_570_x, , , !sys_rst, );
|
| 5728 |
|
|
|
| 5729 |
|
|
|
| 5730 |
|
|
--JE1_q_a[0] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[0]
|
| 5731 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 5732 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 5733 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 5734 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 5735 |
|
|
JE1_q_a[0]_PORT_A_data_in = ~GND;
|
| 5736 |
|
|
JE1_q_a[0]_PORT_A_data_in_reg = DFFE(JE1_q_a[0]_PORT_A_data_in, JE1_q_a[0]_clock_0, , , );
|
| 5737 |
|
|
JE1_q_a[0]_PORT_B_data_in = TB1_dout_1_0;
|
| 5738 |
|
|
JE1_q_a[0]_PORT_B_data_in_reg = DFFE(JE1_q_a[0]_PORT_B_data_in, JE1_q_a[0]_clock_0, , , );
|
| 5739 |
|
|
JE1_q_a[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5740 |
|
|
JE1_q_a[0]_PORT_A_address_reg = DFFE(JE1_q_a[0]_PORT_A_address, JE1_q_a[0]_clock_0, , , );
|
| 5741 |
|
|
JE1_q_a[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5742 |
|
|
JE1_q_a[0]_PORT_B_address_reg = DFFE(JE1_q_a[0]_PORT_B_address, JE1_q_a[0]_clock_0, , , );
|
| 5743 |
|
|
JE1_q_a[0]_PORT_A_write_enable = GND;
|
| 5744 |
|
|
JE1_q_a[0]_PORT_A_write_enable_reg = DFFE(JE1_q_a[0]_PORT_A_write_enable, JE1_q_a[0]_clock_0, , , );
|
| 5745 |
|
|
JE1_q_a[0]_PORT_B_write_enable = WB3L2;
|
| 5746 |
|
|
JE1_q_a[0]_PORT_B_write_enable_reg = DFFE(JE1_q_a[0]_PORT_B_write_enable, JE1_q_a[0]_clock_0, , , );
|
| 5747 |
|
|
JE1_q_a[0]_clock_0 = E1__clk0;
|
| 5748 |
|
|
JE1_q_a[0]_PORT_A_data_out = MEMORY(JE1_q_a[0]_PORT_A_data_in_reg, JE1_q_a[0]_PORT_B_data_in_reg, JE1_q_a[0]_PORT_A_address_reg, JE1_q_a[0]_PORT_B_address_reg, JE1_q_a[0]_PORT_A_write_enable_reg, JE1_q_a[0]_PORT_B_write_enable_reg, , , JE1_q_a[0]_clock_0, , , , , );
|
| 5749 |
|
|
JE1_q_a[0] = JE1_q_a[0]_PORT_A_data_out[0];
|
| 5750 |
|
|
|
| 5751 |
|
|
--JE1_q_b[0] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[0]
|
| 5752 |
|
|
JE1_q_b[0]_PORT_A_data_in = ~GND;
|
| 5753 |
|
|
JE1_q_b[0]_PORT_A_data_in_reg = DFFE(JE1_q_b[0]_PORT_A_data_in, JE1_q_b[0]_clock_0, , , );
|
| 5754 |
|
|
JE1_q_b[0]_PORT_B_data_in = TB1_dout_1_0;
|
| 5755 |
|
|
JE1_q_b[0]_PORT_B_data_in_reg = DFFE(JE1_q_b[0]_PORT_B_data_in, JE1_q_b[0]_clock_0, , , );
|
| 5756 |
|
|
JE1_q_b[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 5757 |
|
|
JE1_q_b[0]_PORT_A_address_reg = DFFE(JE1_q_b[0]_PORT_A_address, JE1_q_b[0]_clock_0, , , );
|
| 5758 |
|
|
JE1_q_b[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 5759 |
|
|
JE1_q_b[0]_PORT_B_address_reg = DFFE(JE1_q_b[0]_PORT_B_address, JE1_q_b[0]_clock_0, , , );
|
| 5760 |
|
|
JE1_q_b[0]_PORT_A_write_enable = GND;
|
| 5761 |
|
|
JE1_q_b[0]_PORT_A_write_enable_reg = DFFE(JE1_q_b[0]_PORT_A_write_enable, JE1_q_b[0]_clock_0, , , );
|
| 5762 |
|
|
JE1_q_b[0]_PORT_B_write_enable = WB3L2;
|
| 5763 |
|
|
JE1_q_b[0]_PORT_B_write_enable_reg = DFFE(JE1_q_b[0]_PORT_B_write_enable, JE1_q_b[0]_clock_0, , , );
|
| 5764 |
|
|
JE1_q_b[0]_clock_0 = E1__clk0;
|
| 5765 |
|
|
JE1_q_b[0]_PORT_B_data_out = MEMORY(JE1_q_b[0]_PORT_A_data_in_reg, JE1_q_b[0]_PORT_B_data_in_reg, JE1_q_b[0]_PORT_A_address_reg, JE1_q_b[0]_PORT_B_address_reg, JE1_q_b[0]_PORT_A_write_enable_reg, JE1_q_b[0]_PORT_B_write_enable_reg, , , JE1_q_b[0]_clock_0, , , , , );
|
| 5766 |
|
|
JE1_q_b[0] = JE1_q_b[0]_PORT_B_data_out[0];
|
| 5767 |
|
|
|
| 5768 |
|
|
|
| 5769 |
|
|
--UB1_dout_2_i_0_a2_x[0] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[0]
|
| 5770 |
|
|
--operation mode is normal
|
| 5771 |
|
|
|
| 5772 |
|
|
UB1_dout_2_i_0_a2_x[0] = !GE1_q_b[0] & UB1_dout_2_i_o2_0[3];
|
| 5773 |
|
|
|
| 5774 |
|
|
|
| 5775 |
|
|
--UB1_dout_2_i_0_a[0] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[0]
|
| 5776 |
|
|
--operation mode is normal
|
| 5777 |
|
|
|
| 5778 |
|
|
UB1_dout_2_i_0_a[0] = HE1_q_b[0] & !KE1_q_b[0] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[0] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[0] & UB1_dout_2_i_a3_0[3];
|
| 5779 |
|
|
|
| 5780 |
|
|
|
| 5781 |
|
|
--VD1_res_2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|res_2_0
|
| 5782 |
|
|
--operation mode is normal
|
| 5783 |
|
|
|
| 5784 |
|
|
VD1_res_2_0 = VD1_un24_res & VD1_hilo[32] # !VD1_un24_res & VD1_hilo[0] & VD1_un11_res;
|
| 5785 |
|
|
|
| 5786 |
|
|
|
| 5787 |
|
|
--MD1_c_1_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_a[0]
|
| 5788 |
|
|
--operation mode is normal
|
| 5789 |
|
|
|
| 5790 |
|
|
MD1_c_1_a[0] = VD1_b_o_iv_0 & !PD1_a_o_0 & RC1_alu_func_o_2 $ RC1_alu_func_o_0 # !VD1_b_o_iv_0 & RC1_alu_func_o_0 # !PD1_a_o_0;
|
| 5791 |
|
|
|
| 5792 |
|
|
|
| 5793 |
|
|
--TD1_un1_b_1_combout[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[0]
|
| 5794 |
|
|
--operation mode is normal
|
| 5795 |
|
|
|
| 5796 |
|
|
TD1_un1_b_1_combout[0] = TD1_sum13_0_a2 $ !VD1_b_o_iv_0;
|
| 5797 |
|
|
|
| 5798 |
|
|
|
| 5799 |
|
|
--TD1_un1_a_add0_start_cout is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add0_start_cout
|
| 5800 |
|
|
--operation mode is arithmetic
|
| 5801 |
|
|
|
| 5802 |
|
|
TD1_un1_a_add0_start_cout = CARRY(TD1_sum13_0_a2);
|
| 5803 |
|
|
|
| 5804 |
|
|
|
| 5805 |
|
|
--UD1_shift_out_91_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[0]
|
| 5806 |
|
|
--operation mode is normal
|
| 5807 |
|
|
|
| 5808 |
|
|
UD1_shift_out_91_a[0] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_0 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[0];
|
| 5809 |
|
|
|
| 5810 |
|
|
|
| 5811 |
|
|
--UD1_shift_out_76[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[0]
|
| 5812 |
|
|
--operation mode is normal
|
| 5813 |
|
|
|
| 5814 |
|
|
UD1_shift_out_76[0] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_76_a[0] # !PD1_a_o_2 & UD1_shift_out_79[16];
|
| 5815 |
|
|
|
| 5816 |
|
|
|
| 5817 |
|
|
--UD1_shift_out_87[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[0]
|
| 5818 |
|
|
--operation mode is normal
|
| 5819 |
|
|
|
| 5820 |
|
|
UD1_shift_out_87[0] = PD1_a_o_0 & UD1_shift_out_80[0] # !PD1_a_o_0 & UD1_shift_out_82[0];
|
| 5821 |
|
|
|
| 5822 |
|
|
|
| 5823 |
|
|
--UD1_shift_out_86[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[0]
|
| 5824 |
|
|
--operation mode is normal
|
| 5825 |
|
|
|
| 5826 |
|
|
UD1_shift_out_86[0] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[0] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[0];
|
| 5827 |
|
|
|
| 5828 |
|
|
|
| 5829 |
|
|
--PD1_a_o_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_31
|
| 5830 |
|
|
--operation mode is normal
|
| 5831 |
|
|
|
| 5832 |
|
|
PD1_a_o_31 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[31] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[31];
|
| 5833 |
|
|
|
| 5834 |
|
|
|
| 5835 |
|
|
--VD1_b_o_iv_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_31
|
| 5836 |
|
|
--operation mode is normal
|
| 5837 |
|
|
|
| 5838 |
|
|
VD1_b_o_iv_31 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[31] & !G1_BUS15471_i_m[31] & AB1_r32_o_29 # !QD1_b_o_0_sqmuxa;
|
| 5839 |
|
|
|
| 5840 |
|
|
--VD1_op2_reged[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[31]
|
| 5841 |
|
|
--operation mode is normal
|
| 5842 |
|
|
|
| 5843 |
|
|
VD1_op2_reged[31] = DFFEAS(VD1_b_o_iv_31, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 5844 |
|
|
|
| 5845 |
|
|
|
| 5846 |
|
|
--TD1_lt_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_30
|
| 5847 |
|
|
--operation mode is arithmetic
|
| 5848 |
|
|
|
| 5849 |
|
|
TD1_lt_30 = CARRY(PD1_a_o_30 & VD1_b_o_iv_30 & !TD1_lt_29 # !PD1_a_o_30 & VD1_b_o_iv_30 # !TD1_lt_29);
|
| 5850 |
|
|
|
| 5851 |
|
|
|
| 5852 |
|
|
--TD1_sum_carry_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_31
|
| 5853 |
|
|
--operation mode is arithmetic
|
| 5854 |
|
|
|
| 5855 |
|
|
TD1_sum_carry_31 = CARRY(VD1_b_o_iv_31 & !TD1_sum_carry_30 # !PD1_a_o_31 # !VD1_b_o_iv_31 & !PD1_a_o_31 & !TD1_sum_carry_30);
|
| 5856 |
|
|
|
| 5857 |
|
|
|
| 5858 |
|
|
--Y1_q_b[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[4]
|
| 5859 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 5860 |
|
|
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
|
| 5861 |
|
|
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
|
| 5862 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 5863 |
|
|
Y1_q_b[4]_PORT_A_data_in = CB1_r32_o_4;
|
| 5864 |
|
|
Y1_q_b[4]_PORT_A_data_in_reg = DFFE(Y1_q_b[4]_PORT_A_data_in, Y1_q_b[4]_clock_0, , , );
|
| 5865 |
|
|
Y1_q_b[4]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
|
| 5866 |
|
|
Y1_q_b[4]_PORT_A_address_reg = DFFE(Y1_q_b[4]_PORT_A_address, Y1_q_b[4]_clock_0, , , );
|
| 5867 |
|
|
Y1_q_b[4]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
|
| 5868 |
|
|
Y1_q_b[4]_PORT_B_address_reg = DFFE(Y1_q_b[4]_PORT_B_address, Y1_q_b[4]_clock_1, , , Y1_q_b[4]_clock_enable_1);
|
| 5869 |
|
|
Y1_q_b[4]_PORT_A_write_enable = T1_valid_wreq;
|
| 5870 |
|
|
Y1_q_b[4]_PORT_A_write_enable_reg = DFFE(Y1_q_b[4]_PORT_A_write_enable, Y1_q_b[4]_clock_0, , , );
|
| 5871 |
|
|
Y1_q_b[4]_PORT_B_read_enable = VCC;
|
| 5872 |
|
|
Y1_q_b[4]_PORT_B_read_enable_reg = DFFE(Y1_q_b[4]_PORT_B_read_enable, Y1_q_b[4]_clock_1, , , Y1_q_b[4]_clock_enable_1);
|
| 5873 |
|
|
Y1_q_b[4]_clock_0 = E1__clk0;
|
| 5874 |
|
|
Y1_q_b[4]_clock_1 = E1__clk0;
|
| 5875 |
|
|
Y1_q_b[4]_clock_enable_1 = T1_valid_rreq;
|
| 5876 |
|
|
Y1_q_b[4]_PORT_B_data_out = MEMORY(Y1_q_b[4]_PORT_A_data_in_reg, , Y1_q_b[4]_PORT_A_address_reg, Y1_q_b[4]_PORT_B_address_reg, Y1_q_b[4]_PORT_A_write_enable_reg, Y1_q_b[4]_PORT_B_read_enable_reg, , , Y1_q_b[4]_clock_0, Y1_q_b[4]_clock_1, , Y1_q_b[4]_clock_enable_1, , );
|
| 5877 |
|
|
Y1_q_b[4] = Y1_q_b[4]_PORT_B_data_out[0];
|
| 5878 |
|
|
|
| 5879 |
|
|
|
| 5880 |
|
|
--N1_tx_sr[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[5]
|
| 5881 |
|
|
--operation mode is normal
|
| 5882 |
|
|
|
| 5883 |
|
|
N1_tx_sr[5]_lut_out = N1_read_request_ff & Y1_q_b[5] # !N1_read_request_ff & N1_tx_sr[6];
|
| 5884 |
|
|
N1_tx_sr[5] = DFFEAS(N1_tx_sr[5]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );
|
| 5885 |
|
|
|
| 5886 |
|
|
|
| 5887 |
|
|
--N1_clk_ctr26_i_0_0_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_0_a
|
| 5888 |
|
|
--operation mode is normal
|
| 5889 |
|
|
|
| 5890 |
|
|
N1_clk_ctr26_i_0_0_a = !N1_ua_state[2] & !N1_ua_state[3] & !N1_ua_state[4] & !N1_ua_state[5];
|
| 5891 |
|
|
|
| 5892 |
|
|
|
| 5893 |
|
|
--N1_clk_ctr26_i_0_a4_0_6_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a4_0_6_a
|
| 5894 |
|
|
--operation mode is normal
|
| 5895 |
|
|
|
| 5896 |
|
|
N1_clk_ctr26_i_0_a4_0_6_a = !N1_clk_ctr[9] # !N1_clk_ctr[1];
|
| 5897 |
|
|
|
| 5898 |
|
|
|
| 5899 |
|
|
--K1_cntr_30 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_30
|
| 5900 |
|
|
--operation mode is arithmetic
|
| 5901 |
|
|
|
| 5902 |
|
|
K1_cntr_30_carry_eqn = K1_cntr_cout[29];
|
| 5903 |
|
|
K1_cntr_30_lut_out = K1_cntr_30 $ (K1_cntr_30_carry_eqn);
|
| 5904 |
|
|
K1_cntr_30 = DFFEAS(K1_cntr_30_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[30], , , !K1_un1_ld_1);
|
| 5905 |
|
|
|
| 5906 |
|
|
--K1_cntr_cout[30] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[30]
|
| 5907 |
|
|
--operation mode is arithmetic
|
| 5908 |
|
|
|
| 5909 |
|
|
K1_cntr_cout[30] = CARRY(K1_cntr_30 # !K1_cntr_cout[29]);
|
| 5910 |
|
|
|
| 5911 |
|
|
|
| 5912 |
|
|
--K1_cntr_31 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_31
|
| 5913 |
|
|
--operation mode is normal
|
| 5914 |
|
|
|
| 5915 |
|
|
K1_cntr_31_carry_eqn = K1_cntr_cout[30];
|
| 5916 |
|
|
K1_cntr_31_lut_out = K1_cntr_31 $ (!K1_cntr_31_carry_eqn);
|
| 5917 |
|
|
K1_cntr_31 = DFFEAS(K1_cntr_31_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[31], , , !K1_un1_ld_1);
|
| 5918 |
|
|
|
| 5919 |
|
|
|
| 5920 |
|
|
--K1_cntr_28 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_28
|
| 5921 |
|
|
--operation mode is arithmetic
|
| 5922 |
|
|
|
| 5923 |
|
|
K1_cntr_28_carry_eqn = K1_cntr_cout[27];
|
| 5924 |
|
|
K1_cntr_28_lut_out = K1_cntr_28 $ (K1_cntr_28_carry_eqn);
|
| 5925 |
|
|
K1_cntr_28 = DFFEAS(K1_cntr_28_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[28], , , !K1_un1_ld_1);
|
| 5926 |
|
|
|
| 5927 |
|
|
--K1_cntr_cout[28] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[28]
|
| 5928 |
|
|
--operation mode is arithmetic
|
| 5929 |
|
|
|
| 5930 |
|
|
K1_cntr_cout[28] = CARRY(K1_cntr_28 # !K1_cntr_cout[27]);
|
| 5931 |
|
|
|
| 5932 |
|
|
|
| 5933 |
|
|
--K1_cntr_29 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_29
|
| 5934 |
|
|
--operation mode is arithmetic
|
| 5935 |
|
|
|
| 5936 |
|
|
K1_cntr_29_carry_eqn = K1_cntr_cout[28];
|
| 5937 |
|
|
K1_cntr_29_lut_out = K1_cntr_29 $ (!K1_cntr_29_carry_eqn);
|
| 5938 |
|
|
K1_cntr_29 = DFFEAS(K1_cntr_29_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[29], , , !K1_un1_ld_1);
|
| 5939 |
|
|
|
| 5940 |
|
|
--K1_cntr_cout[29] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[29]
|
| 5941 |
|
|
--operation mode is arithmetic
|
| 5942 |
|
|
|
| 5943 |
|
|
K1_cntr_cout[29] = CARRY(!K1_cntr_29 & !K1_cntr_cout[28]);
|
| 5944 |
|
|
|
| 5945 |
|
|
|
| 5946 |
|
|
--K1_un2_w_irq_22 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_22
|
| 5947 |
|
|
--operation mode is normal
|
| 5948 |
|
|
|
| 5949 |
|
|
K1_un2_w_irq_22 = !K1_cntr_18 & !K1_cntr_19 & !K1_cntr_16 & !K1_cntr_17;
|
| 5950 |
|
|
|
| 5951 |
|
|
|
| 5952 |
|
|
--K1_un2_w_irq_23 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_23
|
| 5953 |
|
|
--operation mode is normal
|
| 5954 |
|
|
|
| 5955 |
|
|
K1_un2_w_irq_23 = !K1_cntr_22 & !K1_cntr_23 & !K1_cntr_20 & !K1_cntr_21;
|
| 5956 |
|
|
|
| 5957 |
|
|
|
| 5958 |
|
|
--K1_un2_w_irq_20 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_20
|
| 5959 |
|
|
--operation mode is normal
|
| 5960 |
|
|
|
| 5961 |
|
|
K1_un2_w_irq_20 = !K1_cntr_26 & !K1_cntr_27 & !K1_cntr_24 & !K1_cntr_25;
|
| 5962 |
|
|
|
| 5963 |
|
|
|
| 5964 |
|
|
--K1_un2_w_irq_16 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_16
|
| 5965 |
|
|
--operation mode is normal
|
| 5966 |
|
|
|
| 5967 |
|
|
K1_un2_w_irq_16 = !K1_cntr_10 & !K1_cntr_11 & !K1_cntr_8 & !K1_cntr_9;
|
| 5968 |
|
|
|
| 5969 |
|
|
|
| 5970 |
|
|
--K1_un2_w_irq_17 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_17
|
| 5971 |
|
|
--operation mode is normal
|
| 5972 |
|
|
|
| 5973 |
|
|
K1_un2_w_irq_17 = !K1_cntr_14 & !K1_cntr_15 & !K1_cntr_12 & !K1_cntr_13;
|
| 5974 |
|
|
|
| 5975 |
|
|
|
| 5976 |
|
|
--K1_un2_w_irq_18 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_18
|
| 5977 |
|
|
--operation mode is normal
|
| 5978 |
|
|
|
| 5979 |
|
|
K1_un2_w_irq_18 = !K1_cntr_2 & !K1_cntr_3 & !K1_cntr_0 & !K1_cntr_1;
|
| 5980 |
|
|
|
| 5981 |
|
|
|
| 5982 |
|
|
--K1_un2_w_irq_19 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_19
|
| 5983 |
|
|
--operation mode is normal
|
| 5984 |
|
|
|
| 5985 |
|
|
K1_un2_w_irq_19 = !K1_cntr_6 & !K1_cntr_7 & !K1_cntr_4 & !K1_cntr_5;
|
| 5986 |
|
|
|
| 5987 |
|
|
|
| 5988 |
|
|
--CB1_dout_2_8 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_8
|
| 5989 |
|
|
--operation mode is normal
|
| 5990 |
|
|
|
| 5991 |
|
|
CB1_dout_2_8 = ND1_dout7 & FD1_wb_o_8 # !ND1_dout7 & !ND1_dout_2_a_8;
|
| 5992 |
|
|
|
| 5993 |
|
|
--CB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_8
|
| 5994 |
|
|
--operation mode is normal
|
| 5995 |
|
|
|
| 5996 |
|
|
CB1_r32_o_8 = DFFEAS(CB1_dout_2_8, E1__clk0, VCC, , , , , , );
|
| 5997 |
|
|
|
| 5998 |
|
|
|
| 5999 |
|
|
--M1_rxq1 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rxq1
|
| 6000 |
|
|
--operation mode is normal
|
| 6001 |
|
|
|
| 6002 |
|
|
M1_rxq1_lut_out = ser_rxd;
|
| 6003 |
|
|
M1_rxq1 = DFFEAS(M1_rxq1_lut_out, E1__clk0, VCC, , , , , , );
|
| 6004 |
|
|
|
| 6005 |
|
|
|
| 6006 |
|
|
--C1_G_570_x is mips_sys:isys|G_570_x
|
| 6007 |
|
|
--operation mode is normal
|
| 6008 |
|
|
|
| 6009 |
|
|
C1_G_570_x = M1_clk_ctr_equ15_0_a2 # !sys_rst;
|
| 6010 |
|
|
|
| 6011 |
|
|
|
| 6012 |
|
|
--C1_G_578_a is mips_sys:isys|G_578_a
|
| 6013 |
|
|
--operation mode is normal
|
| 6014 |
|
|
|
| 6015 |
|
|
C1_G_578_a = M1_clk_ctr_3 & !M1_clk_ctr_2 & !M1_clk_ctr_0 & M1_ua_state_2;
|
| 6016 |
|
|
|
| 6017 |
|
|
|
| 6018 |
|
|
--M1_un1_clk_ctr_equ0_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|un1_clk_ctr_equ0_0_a2
|
| 6019 |
|
|
--operation mode is normal
|
| 6020 |
|
|
|
| 6021 |
|
|
M1_un1_clk_ctr_equ0_0_a2 = !M1_clk_ctr[15] & !M1_clk_ctr[14] & !M1_clk_ctr[13] & M1_un1_clk_ctr_equ0_0_a2_a;
|
| 6022 |
|
|
|
| 6023 |
|
|
|
| 6024 |
|
|
--M1_un1_clk_ctr_equ0_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|un1_clk_ctr_equ0_0_a2_0
|
| 6025 |
|
|
--operation mode is normal
|
| 6026 |
|
|
|
| 6027 |
|
|
M1_un1_clk_ctr_equ0_0_a2_0 = !M1_clk_ctr[5] & M1_clk_ctr[10] & M1_clk_ctr[8] & M1_un1_clk_ctr_equ0_0_a2_0_a;
|
| 6028 |
|
|
|
| 6029 |
|
|
|
| 6030 |
|
|
--F1_dout_0_0_a3_5_3_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_5_3_a[0]
|
| 6031 |
|
|
--operation mode is normal
|
| 6032 |
|
|
|
| 6033 |
|
|
F1_dout_0_0_a3_5_3_a[0] = !JC1_dmem_ctl_o_0 & AB1_r32_o_1 & JC1_dmem_ctl_o_1 $ JC1_dmem_ctl_o_2;
|
| 6034 |
|
|
|
| 6035 |
|
|
|
| 6036 |
|
|
--KB1_pc_next_0_iv_2 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_2
|
| 6037 |
|
|
--operation mode is normal
|
| 6038 |
|
|
|
| 6039 |
|
|
KB1_pc_next_0_iv_2 = DD1_pc_next_0_iv_1_2 # DD1_un1_pc_next46_0 & DD1_un1_pc_add2;
|
| 6040 |
|
|
|
| 6041 |
|
|
--KB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_2
|
| 6042 |
|
|
--operation mode is normal
|
| 6043 |
|
|
|
| 6044 |
|
|
KB1_r32_o_2 = DFFEAS(KB1_pc_next_0_iv_2, E1__clk0, VCC, , , , , , );
|
| 6045 |
|
|
|
| 6046 |
|
|
|
| 6047 |
|
|
--KB1_pc_next_0_iv_3 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_3
|
| 6048 |
|
|
--operation mode is normal
|
| 6049 |
|
|
|
| 6050 |
|
|
KB1_pc_next_0_iv_3 = DD1_pc_next_0_iv_1_3 # DD1_un1_pc_next46_0 & DD1_un1_pc_add3;
|
| 6051 |
|
|
|
| 6052 |
|
|
--KB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_3
|
| 6053 |
|
|
--operation mode is normal
|
| 6054 |
|
|
|
| 6055 |
|
|
KB1_r32_o_3 = DFFEAS(KB1_pc_next_0_iv_3, E1__clk0, VCC, , , , , , );
|
| 6056 |
|
|
|
| 6057 |
|
|
|
| 6058 |
|
|
--KB1_pc_next_0_iv_4 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_4
|
| 6059 |
|
|
--operation mode is normal
|
| 6060 |
|
|
|
| 6061 |
|
|
KB1_pc_next_0_iv_4 = DD1_pc_next_0_iv_1_4 # DD1_un1_pc_next46_0 & DD1_un1_pc_add4;
|
| 6062 |
|
|
|
| 6063 |
|
|
--KB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_4
|
| 6064 |
|
|
--operation mode is normal
|
| 6065 |
|
|
|
| 6066 |
|
|
KB1_r32_o_4 = DFFEAS(KB1_pc_next_0_iv_4, E1__clk0, VCC, , , , , , );
|
| 6067 |
|
|
|
| 6068 |
|
|
|
| 6069 |
|
|
--KB1_pc_next_0_iv_5 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_5
|
| 6070 |
|
|
--operation mode is normal
|
| 6071 |
|
|
|
| 6072 |
|
|
KB1_pc_next_0_iv_5 = DD1_pc_next_0_iv_1_5 # DD1_un1_pc_next46_0 & DD1_un1_pc_add5;
|
| 6073 |
|
|
|
| 6074 |
|
|
--KB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_5
|
| 6075 |
|
|
--operation mode is normal
|
| 6076 |
|
|
|
| 6077 |
|
|
KB1_r32_o_5 = DFFEAS(KB1_pc_next_0_iv_5, E1__clk0, VCC, , , , , , );
|
| 6078 |
|
|
|
| 6079 |
|
|
|
| 6080 |
|
|
--KB1_pc_next_0_iv_6 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_6
|
| 6081 |
|
|
--operation mode is normal
|
| 6082 |
|
|
|
| 6083 |
|
|
KB1_pc_next_0_iv_6 = DD1_pc_next_0_iv_1_6 # DD1_un1_pc_next46_0 & DD1_un1_pc_add6;
|
| 6084 |
|
|
|
| 6085 |
|
|
--KB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_6
|
| 6086 |
|
|
--operation mode is normal
|
| 6087 |
|
|
|
| 6088 |
|
|
KB1_r32_o_6 = DFFEAS(KB1_pc_next_0_iv_6, E1__clk0, VCC, , , , , , );
|
| 6089 |
|
|
|
| 6090 |
|
|
|
| 6091 |
|
|
--KB1_pc_next_0_iv_7 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_7
|
| 6092 |
|
|
--operation mode is normal
|
| 6093 |
|
|
|
| 6094 |
|
|
KB1_pc_next_0_iv_7 = DD1_pc_next_0_iv_1_7 # DD1_un1_pc_next46_0 & DD1_un1_pc_add7;
|
| 6095 |
|
|
|
| 6096 |
|
|
--KB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_7
|
| 6097 |
|
|
--operation mode is normal
|
| 6098 |
|
|
|
| 6099 |
|
|
KB1_r32_o_7 = DFFEAS(KB1_pc_next_0_iv_7, E1__clk0, VCC, , , , , , );
|
| 6100 |
|
|
|
| 6101 |
|
|
|
| 6102 |
|
|
--KB1_pc_next_0_iv_8 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_8
|
| 6103 |
|
|
--operation mode is normal
|
| 6104 |
|
|
|
| 6105 |
|
|
KB1_pc_next_0_iv_8 = DD1_pc_next_0_iv_1_8 # DD1_un1_pc_next46_0 & DD1_un1_pc_add8;
|
| 6106 |
|
|
|
| 6107 |
|
|
--KB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_8
|
| 6108 |
|
|
--operation mode is normal
|
| 6109 |
|
|
|
| 6110 |
|
|
KB1_r32_o_8 = DFFEAS(KB1_pc_next_0_iv_8, E1__clk0, VCC, , , , , , );
|
| 6111 |
|
|
|
| 6112 |
|
|
|
| 6113 |
|
|
--KB1_pc_next_0_iv_9 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_9
|
| 6114 |
|
|
--operation mode is normal
|
| 6115 |
|
|
|
| 6116 |
|
|
KB1_pc_next_0_iv_9 = DD1_pc_next_0_iv_1_9 # DD1_un1_pc_next46_0 & DD1_un1_pc_add9;
|
| 6117 |
|
|
|
| 6118 |
|
|
--KB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_9
|
| 6119 |
|
|
--operation mode is normal
|
| 6120 |
|
|
|
| 6121 |
|
|
KB1_r32_o_9 = DFFEAS(KB1_pc_next_0_iv_9, E1__clk0, VCC, , , , , , );
|
| 6122 |
|
|
|
| 6123 |
|
|
|
| 6124 |
|
|
--KB1_pc_next_0_iv_10 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_10
|
| 6125 |
|
|
--operation mode is normal
|
| 6126 |
|
|
|
| 6127 |
|
|
KB1_pc_next_0_iv_10 = DD1_pc_next_0_iv_1_10 # DD1_un1_pc_next46_0 & DD1_un1_pc_add10;
|
| 6128 |
|
|
|
| 6129 |
|
|
--KB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_10
|
| 6130 |
|
|
--operation mode is normal
|
| 6131 |
|
|
|
| 6132 |
|
|
KB1_r32_o_10 = DFFEAS(KB1_pc_next_0_iv_10, E1__clk0, VCC, , , , , , );
|
| 6133 |
|
|
|
| 6134 |
|
|
|
| 6135 |
|
|
--KB1_pc_next_0_iv_11 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_11
|
| 6136 |
|
|
--operation mode is normal
|
| 6137 |
|
|
|
| 6138 |
|
|
KB1_pc_next_0_iv_11 = DD1_pc_next_0_iv_1_11 # DD1_un1_pc_next46_0 & DD1_un1_pc_add11;
|
| 6139 |
|
|
|
| 6140 |
|
|
--KB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_11
|
| 6141 |
|
|
--operation mode is normal
|
| 6142 |
|
|
|
| 6143 |
|
|
KB1_r32_o_11 = DFFEAS(KB1_pc_next_0_iv_11, E1__clk0, VCC, , , , , , );
|
| 6144 |
|
|
|
| 6145 |
|
|
|
| 6146 |
|
|
--KB1_pc_next_0_iv_12 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_12
|
| 6147 |
|
|
--operation mode is normal
|
| 6148 |
|
|
|
| 6149 |
|
|
KB1_pc_next_0_iv_12 = DD1_pc_next_0_iv_1_12 # DD1_un1_pc_next46_0 & DD1_un1_pc_add12;
|
| 6150 |
|
|
|
| 6151 |
|
|
--KB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_12
|
| 6152 |
|
|
--operation mode is normal
|
| 6153 |
|
|
|
| 6154 |
|
|
KB1_r32_o_12 = DFFEAS(KB1_pc_next_0_iv_12, E1__clk0, VCC, , , , , , );
|
| 6155 |
|
|
|
| 6156 |
|
|
|
| 6157 |
|
|
--UB1_dout_2_i_i_0_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_0_a[7]
|
| 6158 |
|
|
--operation mode is normal
|
| 6159 |
|
|
|
| 6160 |
|
|
UB1_dout_2_i_i_0_a[7] = RB1_ctl_o_3 & !RB1_ctl_o_2;
|
| 6161 |
|
|
|
| 6162 |
|
|
|
| 6163 |
|
|
--UB1_dout_2_i_i_o3_0[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_o3_0[7]
|
| 6164 |
|
|
--operation mode is normal
|
| 6165 |
|
|
|
| 6166 |
|
|
UB1_dout_2_i_i_o3_0[7] = RB1_byte_addr_o_1 # RB1_byte_addr_o_0 # !RB1_ctl_o_3;
|
| 6167 |
|
|
|
| 6168 |
|
|
|
| 6169 |
|
|
--JE1_q_a[7] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[7]
|
| 6170 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 6171 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 6172 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 6173 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 6174 |
|
|
JE1_q_a[7]_PORT_A_data_in = ~GND;
|
| 6175 |
|
|
JE1_q_a[7]_PORT_A_data_in_reg = DFFE(JE1_q_a[7]_PORT_A_data_in, JE1_q_a[7]_clock_0, , , );
|
| 6176 |
|
|
JE1_q_a[7]_PORT_B_data_in = TB1_dout_1_7;
|
| 6177 |
|
|
JE1_q_a[7]_PORT_B_data_in_reg = DFFE(JE1_q_a[7]_PORT_B_data_in, JE1_q_a[7]_clock_0, , , );
|
| 6178 |
|
|
JE1_q_a[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 6179 |
|
|
JE1_q_a[7]_PORT_A_address_reg = DFFE(JE1_q_a[7]_PORT_A_address, JE1_q_a[7]_clock_0, , , );
|
| 6180 |
|
|
JE1_q_a[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 6181 |
|
|
JE1_q_a[7]_PORT_B_address_reg = DFFE(JE1_q_a[7]_PORT_B_address, JE1_q_a[7]_clock_0, , , );
|
| 6182 |
|
|
JE1_q_a[7]_PORT_A_write_enable = GND;
|
| 6183 |
|
|
JE1_q_a[7]_PORT_A_write_enable_reg = DFFE(JE1_q_a[7]_PORT_A_write_enable, JE1_q_a[7]_clock_0, , , );
|
| 6184 |
|
|
JE1_q_a[7]_PORT_B_write_enable = WB3L2;
|
| 6185 |
|
|
JE1_q_a[7]_PORT_B_write_enable_reg = DFFE(JE1_q_a[7]_PORT_B_write_enable, JE1_q_a[7]_clock_0, , , );
|
| 6186 |
|
|
JE1_q_a[7]_clock_0 = E1__clk0;
|
| 6187 |
|
|
JE1_q_a[7]_PORT_A_data_out = MEMORY(JE1_q_a[7]_PORT_A_data_in_reg, JE1_q_a[7]_PORT_B_data_in_reg, JE1_q_a[7]_PORT_A_address_reg, JE1_q_a[7]_PORT_B_address_reg, JE1_q_a[7]_PORT_A_write_enable_reg, JE1_q_a[7]_PORT_B_write_enable_reg, , , JE1_q_a[7]_clock_0, , , , , );
|
| 6188 |
|
|
JE1_q_a[7] = JE1_q_a[7]_PORT_A_data_out[0];
|
| 6189 |
|
|
|
| 6190 |
|
|
--JE1_q_b[7] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[7]
|
| 6191 |
|
|
JE1_q_b[7]_PORT_A_data_in = ~GND;
|
| 6192 |
|
|
JE1_q_b[7]_PORT_A_data_in_reg = DFFE(JE1_q_b[7]_PORT_A_data_in, JE1_q_b[7]_clock_0, , , );
|
| 6193 |
|
|
JE1_q_b[7]_PORT_B_data_in = TB1_dout_1_7;
|
| 6194 |
|
|
JE1_q_b[7]_PORT_B_data_in_reg = DFFE(JE1_q_b[7]_PORT_B_data_in, JE1_q_b[7]_clock_0, , , );
|
| 6195 |
|
|
JE1_q_b[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 6196 |
|
|
JE1_q_b[7]_PORT_A_address_reg = DFFE(JE1_q_b[7]_PORT_A_address, JE1_q_b[7]_clock_0, , , );
|
| 6197 |
|
|
JE1_q_b[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 6198 |
|
|
JE1_q_b[7]_PORT_B_address_reg = DFFE(JE1_q_b[7]_PORT_B_address, JE1_q_b[7]_clock_0, , , );
|
| 6199 |
|
|
JE1_q_b[7]_PORT_A_write_enable = GND;
|
| 6200 |
|
|
JE1_q_b[7]_PORT_A_write_enable_reg = DFFE(JE1_q_b[7]_PORT_A_write_enable, JE1_q_b[7]_clock_0, , , );
|
| 6201 |
|
|
JE1_q_b[7]_PORT_B_write_enable = WB3L2;
|
| 6202 |
|
|
JE1_q_b[7]_PORT_B_write_enable_reg = DFFE(JE1_q_b[7]_PORT_B_write_enable, JE1_q_b[7]_clock_0, , , );
|
| 6203 |
|
|
JE1_q_b[7]_clock_0 = E1__clk0;
|
| 6204 |
|
|
JE1_q_b[7]_PORT_B_data_out = MEMORY(JE1_q_b[7]_PORT_A_data_in_reg, JE1_q_b[7]_PORT_B_data_in_reg, JE1_q_b[7]_PORT_A_address_reg, JE1_q_b[7]_PORT_B_address_reg, JE1_q_b[7]_PORT_A_write_enable_reg, JE1_q_b[7]_PORT_B_write_enable_reg, , , JE1_q_b[7]_clock_0, , , , , );
|
| 6205 |
|
|
JE1_q_b[7] = JE1_q_b[7]_PORT_B_data_out[0];
|
| 6206 |
|
|
|
| 6207 |
|
|
|
| 6208 |
|
|
--UB1_dout_2_i_i_a2_2[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_2[7]
|
| 6209 |
|
|
--operation mode is normal
|
| 6210 |
|
|
|
| 6211 |
|
|
UB1_dout_2_i_i_a2_2[7] = UB1_dout_2_i_i_a2_2_a[7] & RB1_byte_addr_o_1 & GE1_q_b[7] # !RB1_byte_addr_o_1 & JE1_q_b[7];
|
| 6212 |
|
|
|
| 6213 |
|
|
|
| 6214 |
|
|
--UB1_dout_2_i_i_a2_1[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_1[7]
|
| 6215 |
|
|
--operation mode is normal
|
| 6216 |
|
|
|
| 6217 |
|
|
UB1_dout_2_i_i_a2_1[7] = UB1_dout_2_i_i_a2_1_a[7] & RB1_byte_addr_o_1 & HE1_q_b[7] # !RB1_byte_addr_o_1 & KE1_q_b[7];
|
| 6218 |
|
|
|
| 6219 |
|
|
|
| 6220 |
|
|
--UB1_dout_2_i_i_o2_0[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_o2_0[7]
|
| 6221 |
|
|
--operation mode is normal
|
| 6222 |
|
|
|
| 6223 |
|
|
UB1_dout_2_i_i_o2_0[7] = !RB1_byte_addr_o_1 & UB1_dout_2_i_i_o2_0_a[7];
|
| 6224 |
|
|
|
| 6225 |
|
|
|
| 6226 |
|
|
--FD1_r_rdaddress_b[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[4]
|
| 6227 |
|
|
--operation mode is normal
|
| 6228 |
|
|
|
| 6229 |
|
|
FD1_r_rdaddress_b[4]_lut_out = JE1_q_a[4];
|
| 6230 |
|
|
FD1_r_rdaddress_b[4] = DFFEAS(FD1_r_rdaddress_b[4]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 6231 |
|
|
|
| 6232 |
|
|
|
| 6233 |
|
|
--FD1_r_rdaddress_b[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[0]
|
| 6234 |
|
|
--operation mode is normal
|
| 6235 |
|
|
|
| 6236 |
|
|
FD1_r_rdaddress_b[0]_lut_out = JE1_q_a[0];
|
| 6237 |
|
|
FD1_r_rdaddress_b[0] = DFFEAS(FD1_r_rdaddress_b[0]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 6238 |
|
|
|
| 6239 |
|
|
|
| 6240 |
|
|
--FD1_r_rdaddress_b[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[1]
|
| 6241 |
|
|
--operation mode is normal
|
| 6242 |
|
|
|
| 6243 |
|
|
FD1_r_rdaddress_b[1]_lut_out = JE1_q_a[1];
|
| 6244 |
|
|
FD1_r_rdaddress_b[1] = DFFEAS(FD1_r_rdaddress_b[1]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 6245 |
|
|
|
| 6246 |
|
|
|
| 6247 |
|
|
--FD1_un23_qb_i_0_a2_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un23_qb_i_0_a2_a
|
| 6248 |
|
|
--operation mode is normal
|
| 6249 |
|
|
|
| 6250 |
|
|
FD1_un23_qb_i_0_a2_a = !FD1_r_rdaddress_b[2] & !FD1_r_rdaddress_b[3];
|
| 6251 |
|
|
|
| 6252 |
|
|
|
| 6253 |
|
|
--FD1_r_wraddress[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[4]
|
| 6254 |
|
|
--operation mode is normal
|
| 6255 |
|
|
|
| 6256 |
|
|
FD1_r_wraddress[4]_lut_out = NB1_r5_o_4;
|
| 6257 |
|
|
FD1_r_wraddress[4] = DFFEAS(FD1_r_wraddress[4]_lut_out, E1__clk0, VCC, , , , , , );
|
| 6258 |
|
|
|
| 6259 |
|
|
|
| 6260 |
|
|
--FD1_un14_qb_NE_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qb_NE_1
|
| 6261 |
|
|
--operation mode is normal
|
| 6262 |
|
|
|
| 6263 |
|
|
FD1_un14_qb_NE_1 = FD1_r_rdaddress_b[1] & FD1_r_rdaddress_b[0] $ FD1_r_wraddress[0] # !FD1_r_wraddress[1] # !FD1_r_rdaddress_b[1] & FD1_r_wraddress[1] # FD1_r_rdaddress_b[0] $ FD1_r_wraddress[0];
|
| 6264 |
|
|
|
| 6265 |
|
|
|
| 6266 |
|
|
--FD1_un14_qb_NE_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qb_NE_a
|
| 6267 |
|
|
--operation mode is normal
|
| 6268 |
|
|
|
| 6269 |
|
|
FD1_un14_qb_NE_a = FD1_r_rdaddress_b[2] & FD1_r_rdaddress_b[3] $ FD1_r_wraddress[3] # !FD1_r_wraddress[2] # !FD1_r_rdaddress_b[2] & FD1_r_wraddress[2] # FD1_r_rdaddress_b[3] $ FD1_r_wraddress[3];
|
| 6270 |
|
|
|
| 6271 |
|
|
|
| 6272 |
|
|
--FD1_r_rdaddress_b[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[2]
|
| 6273 |
|
|
--operation mode is normal
|
| 6274 |
|
|
|
| 6275 |
|
|
FD1_r_rdaddress_b[2]_lut_out = JE1_q_a[2];
|
| 6276 |
|
|
FD1_r_rdaddress_b[2] = DFFEAS(FD1_r_rdaddress_b[2]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 6277 |
|
|
|
| 6278 |
|
|
|
| 6279 |
|
|
--FD1_r_rdaddress_b[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[3]
|
| 6280 |
|
|
--operation mode is normal
|
| 6281 |
|
|
|
| 6282 |
|
|
FD1_r_rdaddress_b[3]_lut_out = JE1_q_a[3];
|
| 6283 |
|
|
FD1_r_rdaddress_b[3] = DFFEAS(FD1_r_rdaddress_b[3]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 6284 |
|
|
|
| 6285 |
|
|
|
| 6286 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[9] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[9]
|
| 6287 |
|
|
--operation mode is normal
|
| 6288 |
|
|
|
| 6289 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[9] = QB1_r32_o_9 & !FB1_r32_o_0_9 & QD1_b_o18 # !QB1_r32_o_9 & QD1_un1_b_o18_2 # !FB1_r32_o_0_9 & QD1_b_o18;
|
| 6290 |
|
|
|
| 6291 |
|
|
|
| 6292 |
|
|
--G1_BUS15471_i_m[9] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[9]
|
| 6293 |
|
|
--operation mode is normal
|
| 6294 |
|
|
|
| 6295 |
|
|
G1_BUS15471_i_m[9] = !FD1_wb_o_9 & QD1_b_o_1_sqmuxa;
|
| 6296 |
|
|
|
| 6297 |
|
|
|
| 6298 |
|
|
--UD1_shift_out_87_d_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[7]
|
| 6299 |
|
|
--operation mode is normal
|
| 6300 |
|
|
|
| 6301 |
|
|
UD1_shift_out_87_d_a[7] = PD1_a_o_1 & !VD1_b_o_iv_13 # !PD1_a_o_1 & !VD1_b_o_iv_11;
|
| 6302 |
|
|
|
| 6303 |
|
|
|
| 6304 |
|
|
--UD1_shift_out_80[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[7]
|
| 6305 |
|
|
--operation mode is normal
|
| 6306 |
|
|
|
| 6307 |
|
|
UD1_shift_out_80[7] = PD1_a_o_2 & UD1_shift_out_80_a[7] & VD1_b_o_iv_12 # !UD1_shift_out_80_a[7] & VD1_b_o_iv_14 # !PD1_a_o_2 & !UD1_shift_out_80_a[7];
|
| 6308 |
|
|
|
| 6309 |
|
|
|
| 6310 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[6] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[6]
|
| 6311 |
|
|
--operation mode is normal
|
| 6312 |
|
|
|
| 6313 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[6] = QB1_r32_o_6 & !FB1_r32_o_0_6 & QD1_b_o18 # !QB1_r32_o_6 & QD1_un1_b_o18_2 # !FB1_r32_o_0_6 & QD1_b_o18;
|
| 6314 |
|
|
|
| 6315 |
|
|
|
| 6316 |
|
|
--G1_BUS15471_i_m[6] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[6]
|
| 6317 |
|
|
--operation mode is normal
|
| 6318 |
|
|
|
| 6319 |
|
|
G1_BUS15471_i_m[6] = !FD1_wb_o_6 & QD1_b_o_1_sqmuxa;
|
| 6320 |
|
|
|
| 6321 |
|
|
|
| 6322 |
|
|
--UD1_shift_out_85_d_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[7]
|
| 6323 |
|
|
--operation mode is normal
|
| 6324 |
|
|
|
| 6325 |
|
|
UD1_shift_out_85_d_a[7] = PD1_a_o_0 & !VD1_b_o_iv_4 # !PD1_a_o_0 & !VD1_b_o_iv_5;
|
| 6326 |
|
|
|
| 6327 |
|
|
|
| 6328 |
|
|
--UD1_shift_out_43[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43[31]
|
| 6329 |
|
|
--operation mode is normal
|
| 6330 |
|
|
|
| 6331 |
|
|
UD1_shift_out_43[31] = PD1_a_o_1 & !UD1_shift_out_43_a[31] # !PD1_a_o_1 & UD1_shift_out_43_a[31] & VD1_b_o_iv_3 # !UD1_shift_out_43_a[31] & VD1_b_o_iv_2;
|
| 6332 |
|
|
|
| 6333 |
|
|
|
| 6334 |
|
|
--UD1_shift_out588 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out588
|
| 6335 |
|
|
--operation mode is normal
|
| 6336 |
|
|
|
| 6337 |
|
|
UD1_shift_out588 = !RC1_alu_func_o_1 & UD1_shift_out588_0 & !RC1_alu_func_o_4 & !RC1_alu_func_o_0;
|
| 6338 |
|
|
|
| 6339 |
|
|
|
| 6340 |
|
|
--RD1_r32_o_0_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_2
|
| 6341 |
|
|
--operation mode is normal
|
| 6342 |
|
|
|
| 6343 |
|
|
RD1_r32_o_0_2_lut_out = !KB1_r32_o_2;
|
| 6344 |
|
|
RD1_r32_o_0_2 = DFFEAS(RD1_r32_o_0_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 6345 |
|
|
|
| 6346 |
|
|
|
| 6347 |
|
|
--FB1_res_7_0_0_2 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_2
|
| 6348 |
|
|
--operation mode is normal
|
| 6349 |
|
|
|
| 6350 |
|
|
FB1_res_7_0_0_2 = CD1_res_7_0_0_0_0 # ED1_r32_o_0 & CD1_res_7_0_0_o3_0;
|
| 6351 |
|
|
|
| 6352 |
|
|
--FB1_r32_o_0_2 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_2
|
| 6353 |
|
|
--operation mode is normal
|
| 6354 |
|
|
|
| 6355 |
|
|
FB1_r32_o_0_2 = DFFEAS(FB1_res_7_0_0_2, E1__clk0, VCC, , , , , , );
|
| 6356 |
|
|
|
| 6357 |
|
|
|
| 6358 |
|
|
--SD1_r32_o_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_2
|
| 6359 |
|
|
--operation mode is normal
|
| 6360 |
|
|
|
| 6361 |
|
|
SD1_r32_o_2_lut_out = KB1_r32_o_2;
|
| 6362 |
|
|
SD1_r32_o_2 = DFFEAS(SD1_r32_o_2_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 6363 |
|
|
|
| 6364 |
|
|
|
| 6365 |
|
|
--PD1_a_o_3_d[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[2]
|
| 6366 |
|
|
--operation mode is normal
|
| 6367 |
|
|
|
| 6368 |
|
|
PD1_a_o_3_d[2] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_2 # !PD1_un6_a_o & !PD1_a_o_3_d_a[2] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[2];
|
| 6369 |
|
|
|
| 6370 |
|
|
|
| 6371 |
|
|
--FB1_res_7_0_0_1 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_1
|
| 6372 |
|
|
--operation mode is normal
|
| 6373 |
|
|
|
| 6374 |
|
|
FB1_res_7_0_0_1 = ED1_r32_o_7 & CD1_res_7_0_0_0_a_0 # ED1_r32_o_1 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_7 & ED1_r32_o_1 & CD1_res_7_0_0_a2_0;
|
| 6375 |
|
|
|
| 6376 |
|
|
--FB1_r32_o_0_1 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_1
|
| 6377 |
|
|
--operation mode is normal
|
| 6378 |
|
|
|
| 6379 |
|
|
FB1_r32_o_0_1 = DFFEAS(FB1_res_7_0_0_1, E1__clk0, VCC, , , , , , );
|
| 6380 |
|
|
|
| 6381 |
|
|
|
| 6382 |
|
|
--KB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_1
|
| 6383 |
|
|
--operation mode is normal
|
| 6384 |
|
|
|
| 6385 |
|
|
KB1_r32_o_1_lut_out = DD1_pc_next_0_iv_1_1 # DD1_un1_pc_next46_0 & DD1_un1_pc_add1;
|
| 6386 |
|
|
KB1_r32_o_1 = DFFEAS(KB1_r32_o_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 6387 |
|
|
|
| 6388 |
|
|
|
| 6389 |
|
|
--SD1_r32_o_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_1
|
| 6390 |
|
|
--operation mode is normal
|
| 6391 |
|
|
|
| 6392 |
|
|
SD1_r32_o_1_lut_out = KB1_r32_o_1;
|
| 6393 |
|
|
SD1_r32_o_1 = DFFEAS(SD1_r32_o_1_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 6394 |
|
|
|
| 6395 |
|
|
|
| 6396 |
|
|
--PD1_a_o_3_d[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[1]
|
| 6397 |
|
|
--operation mode is normal
|
| 6398 |
|
|
|
| 6399 |
|
|
PD1_a_o_3_d[1] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_1 # !PD1_un6_a_o & !PD1_a_o_3_d_a[1] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[1];
|
| 6400 |
|
|
|
| 6401 |
|
|
|
| 6402 |
|
|
--FB1_res_7_0_0_0_d0 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_0_d0
|
| 6403 |
|
|
--operation mode is normal
|
| 6404 |
|
|
|
| 6405 |
|
|
FB1_res_7_0_0_0_d0 = ED1_r32_o_6 & CD1_res_7_0_0_0_a_0 # ED1_r32_o_0 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_6 & ED1_r32_o_0 & CD1_res_7_0_0_a2_0;
|
| 6406 |
|
|
|
| 6407 |
|
|
--FB1_r32_o_0_0 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_0
|
| 6408 |
|
|
--operation mode is normal
|
| 6409 |
|
|
|
| 6410 |
|
|
FB1_r32_o_0_0 = DFFEAS(FB1_res_7_0_0_0_d0, E1__clk0, VCC, , , , , , );
|
| 6411 |
|
|
|
| 6412 |
|
|
|
| 6413 |
|
|
--KB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_0
|
| 6414 |
|
|
--operation mode is normal
|
| 6415 |
|
|
|
| 6416 |
|
|
KB1_r32_o_0_lut_out = DD1_pc_next_0_iv_1_0 # DD1_un1_pc_next46_0 & DD1_un1_pc_add0;
|
| 6417 |
|
|
KB1_r32_o_0 = DFFEAS(KB1_r32_o_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 6418 |
|
|
|
| 6419 |
|
|
|
| 6420 |
|
|
--SD1_r32_o_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_0
|
| 6421 |
|
|
--operation mode is normal
|
| 6422 |
|
|
|
| 6423 |
|
|
SD1_r32_o_0_lut_out = KB1_r32_o_0;
|
| 6424 |
|
|
SD1_r32_o_0 = DFFEAS(SD1_r32_o_0_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 6425 |
|
|
|
| 6426 |
|
|
|
| 6427 |
|
|
--PD1_a_o_3_d[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[0]
|
| 6428 |
|
|
--operation mode is normal
|
| 6429 |
|
|
|
| 6430 |
|
|
PD1_a_o_3_d[0] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_0 # !PD1_un6_a_o & !PD1_a_o_3_d_a[0] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[0];
|
| 6431 |
|
|
|
| 6432 |
|
|
|
| 6433 |
|
|
--UD1_shift_out_79[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[11]
|
| 6434 |
|
|
--operation mode is normal
|
| 6435 |
|
|
|
| 6436 |
|
|
UD1_shift_out_79[11] = PD1_a_o_1 & UD1_shift_out_79_a[11] & VD1_b_o_iv_21 # !UD1_shift_out_79_a[11] & VD1_b_o_iv_22 # !PD1_a_o_1 & !UD1_shift_out_79_a[11];
|
| 6437 |
|
|
|
| 6438 |
|
|
|
| 6439 |
|
|
--UD1_shift_out_79[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[15]
|
| 6440 |
|
|
--operation mode is normal
|
| 6441 |
|
|
|
| 6442 |
|
|
UD1_shift_out_79[15] = PD1_a_o_1 & UD1_shift_out_79_a[15] & VD1_b_o_iv_25 # !UD1_shift_out_79_a[15] & VD1_b_o_iv_26 # !PD1_a_o_1 & !UD1_shift_out_79_a[15];
|
| 6443 |
|
|
|
| 6444 |
|
|
|
| 6445 |
|
|
--UD1_shift_out_74_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[7]
|
| 6446 |
|
|
--operation mode is normal
|
| 6447 |
|
|
|
| 6448 |
|
|
UD1_shift_out_74_a[7] = PD1_a_o_3 & !VD1_b_o_iv_31 # !PD1_a_o_3 & !PD1_a_o_2;
|
| 6449 |
|
|
|
| 6450 |
|
|
|
| 6451 |
|
|
--UD1_shift_out_79[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[19]
|
| 6452 |
|
|
--operation mode is normal
|
| 6453 |
|
|
|
| 6454 |
|
|
UD1_shift_out_79[19] = PD1_a_o_1 & UD1_shift_out_79_a[19] & VD1_b_o_iv_29 # !UD1_shift_out_79_a[19] & VD1_b_o_iv_30 # !PD1_a_o_1 & !UD1_shift_out_79_a[19];
|
| 6455 |
|
|
|
| 6456 |
|
|
|
| 6457 |
|
|
--UD1_shift_out_sn_m25_0_o2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0_o2
|
| 6458 |
|
|
--operation mode is normal
|
| 6459 |
|
|
|
| 6460 |
|
|
UD1_shift_out_sn_m25_0_o2 = PD1_a_o_3 # PD1_a_o_2;
|
| 6461 |
|
|
|
| 6462 |
|
|
|
| 6463 |
|
|
--UD1_shift_out_sn_b10_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_b10_0
|
| 6464 |
|
|
--operation mode is normal
|
| 6465 |
|
|
|
| 6466 |
|
|
UD1_shift_out_sn_b10_0 = !UD1_shift_out588 & !UD1_shift_out587 # !PD1_a_o_3;
|
| 6467 |
|
|
|
| 6468 |
|
|
|
| 6469 |
|
|
--UD1_shift_out_79[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[7]
|
| 6470 |
|
|
--operation mode is normal
|
| 6471 |
|
|
|
| 6472 |
|
|
UD1_shift_out_79[7] = PD1_a_o_1 & UD1_shift_out_79_a[7] & VD1_b_o_iv_17 # !UD1_shift_out_79_a[7] & VD1_b_o_iv_18 # !PD1_a_o_1 & !UD1_shift_out_79_a[7];
|
| 6473 |
|
|
|
| 6474 |
|
|
|
| 6475 |
|
|
--UD1_shift_out_76_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[7]
|
| 6476 |
|
|
--operation mode is normal
|
| 6477 |
|
|
|
| 6478 |
|
|
UD1_shift_out_76_a[7] = PD1_a_o_2 & !PD1_a_o_3 # !PD1_a_o_2 & !PD1_a_o_1 & UD1_shift_out_39[19];
|
| 6479 |
|
|
|
| 6480 |
|
|
|
| 6481 |
|
|
--VD1_hilo25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo25
|
| 6482 |
|
|
--operation mode is normal
|
| 6483 |
|
|
|
| 6484 |
|
|
VD1_hilo25 = RC1_alu_func_o_3 & !TD1_alu_out_7_0_0_o3_0 & RC1_alu_func_o_4;
|
| 6485 |
|
|
|
| 6486 |
|
|
|
| 6487 |
|
|
--VD1_hilo_37_iv_0[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[7]
|
| 6488 |
|
|
--operation mode is normal
|
| 6489 |
|
|
|
| 6490 |
|
|
VD1_hilo_37_iv_0[7] = VD1_hilo_8 & VD1_hilo_1_sqmuxa_1 # VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[7] # !VD1_hilo_8 & VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[7];
|
| 6491 |
|
|
|
| 6492 |
|
|
|
| 6493 |
|
|
--VD1_hilo_8_Z[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[7]
|
| 6494 |
|
|
--operation mode is normal
|
| 6495 |
|
|
|
| 6496 |
|
|
VD1_hilo_8_Z[7] = RC1_alu_func_o_0 & VD1_hilo_7 # !RC1_alu_func_o_0 & PD1_a_o_7;
|
| 6497 |
|
|
|
| 6498 |
|
|
|
| 6499 |
|
|
--VD1_hilo_37_iv_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[7]
|
| 6500 |
|
|
--operation mode is normal
|
| 6501 |
|
|
|
| 6502 |
|
|
VD1_hilo_37_iv_a[7] = VD1_hilo_6 & !VD1_hilo_2_sqmuxa & !PD1_a_o_7 # !VD1_addnop2109_0_a2 # !VD1_hilo_6 & !PD1_a_o_7 # !VD1_addnop2109_0_a2;
|
| 6503 |
|
|
|
| 6504 |
|
|
|
| 6505 |
|
|
--VD1_hilo_37_iv_0_5[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[39]
|
| 6506 |
|
|
--operation mode is normal
|
| 6507 |
|
|
|
| 6508 |
|
|
VD1_hilo_37_iv_0_5[39] = VD1_hilo_40 & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add8 # !VD1_hilo_40 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add8;
|
| 6509 |
|
|
|
| 6510 |
|
|
|
| 6511 |
|
|
--VD1_hilo_37_iv_0_4[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4[39]
|
| 6512 |
|
|
--operation mode is normal
|
| 6513 |
|
|
|
| 6514 |
|
|
VD1_hilo_37_iv_0_4[39] = VD1_hilo_37_iv_0_1[39] # VD1_hilo_37_iv_0_4_a[39] # !VD1_un59_hilo_add8 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 6515 |
|
|
|
| 6516 |
|
|
|
| 6517 |
|
|
--VD1_hilo_37_iv_0_a[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[39]
|
| 6518 |
|
|
--operation mode is normal
|
| 6519 |
|
|
|
| 6520 |
|
|
VD1_hilo_37_iv_0_a[39] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_7 # !VD1_hilo_24_add7 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_7;
|
| 6521 |
|
|
|
| 6522 |
|
|
|
| 6523 |
|
|
--VD1_hilo_37_iv_0_a2[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2[39]
|
| 6524 |
|
|
--operation mode is normal
|
| 6525 |
|
|
|
| 6526 |
|
|
VD1_hilo_37_iv_0_a2[39] = VD1_addnop2109_0_a2 & VD1_hilo_37_iv_0_o3[34];
|
| 6527 |
|
|
|
| 6528 |
|
|
|
| 6529 |
|
|
--PD1_a_o_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[7]
|
| 6530 |
|
|
--operation mode is normal
|
| 6531 |
|
|
|
| 6532 |
|
|
PD1_a_o_a[7] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_7 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_7;
|
| 6533 |
|
|
|
| 6534 |
|
|
|
| 6535 |
|
|
--PD1_a_o_3_Z[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[7]
|
| 6536 |
|
|
--operation mode is normal
|
| 6537 |
|
|
|
| 6538 |
|
|
PD1_a_o_3_Z[7] = PD1_a_o_3_s[0] & SD1_r32_o_7 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[7];
|
| 6539 |
|
|
|
| 6540 |
|
|
|
| 6541 |
|
|
--TD1_m5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m5
|
| 6542 |
|
|
--operation mode is normal
|
| 6543 |
|
|
|
| 6544 |
|
|
TD1_m5 = !RC1_alu_func_o_0 & TD1_alu_out_sn_m14_0_0;
|
| 6545 |
|
|
|
| 6546 |
|
|
|
| 6547 |
|
|
--TD1_un1_b_1_combout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[7]
|
| 6548 |
|
|
--operation mode is normal
|
| 6549 |
|
|
|
| 6550 |
|
|
TD1_un1_b_1_combout[7] = TD1_sum13_0_a2 $ !VD1_b_o_iv_7;
|
| 6551 |
|
|
|
| 6552 |
|
|
|
| 6553 |
|
|
--ED1_r32_o_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_15
|
| 6554 |
|
|
--operation mode is normal
|
| 6555 |
|
|
|
| 6556 |
|
|
ED1_r32_o_15_lut_out = HE1_q_a[7];
|
| 6557 |
|
|
ED1_r32_o_15 = DFFEAS(ED1_r32_o_15_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 6558 |
|
|
|
| 6559 |
|
|
|
| 6560 |
|
|
--EC1_rd_sel_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|rd_sel_reg_clr_cls:U5|rd_sel_o_0
|
| 6561 |
|
|
--operation mode is normal
|
| 6562 |
|
|
|
| 6563 |
|
|
EC1_rd_sel_o_0_lut_out = WB36L1;
|
| 6564 |
|
|
EC1_rd_sel_o_0 = DFFEAS(EC1_rd_sel_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 6565 |
|
|
|
| 6566 |
|
|
|
| 6567 |
|
|
--EC1_rd_sel_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|rd_sel_reg_clr_cls:U5|rd_sel_o_1
|
| 6568 |
|
|
--operation mode is normal
|
| 6569 |
|
|
|
| 6570 |
|
|
EC1_rd_sel_o_1_lut_out = WB46L2;
|
| 6571 |
|
|
EC1_rd_sel_o_1 = DFFEAS(EC1_rd_sel_o_1_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 6572 |
|
|
|
| 6573 |
|
|
|
| 6574 |
|
|
--ED1_r32_o_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_14
|
| 6575 |
|
|
--operation mode is normal
|
| 6576 |
|
|
|
| 6577 |
|
|
ED1_r32_o_14_lut_out = HE1_q_a[6];
|
| 6578 |
|
|
ED1_r32_o_14 = DFFEAS(ED1_r32_o_14_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 6579 |
|
|
|
| 6580 |
|
|
|
| 6581 |
|
|
--ED1_r32_o_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_13
|
| 6582 |
|
|
--operation mode is normal
|
| 6583 |
|
|
|
| 6584 |
|
|
ED1_r32_o_13_lut_out = HE1_q_a[5];
|
| 6585 |
|
|
ED1_r32_o_13 = DFFEAS(ED1_r32_o_13_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 6586 |
|
|
|
| 6587 |
|
|
|
| 6588 |
|
|
--ED1_r32_o_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_12
|
| 6589 |
|
|
--operation mode is normal
|
| 6590 |
|
|
|
| 6591 |
|
|
ED1_r32_o_12_lut_out = HE1_q_a[4];
|
| 6592 |
|
|
ED1_r32_o_12 = DFFEAS(ED1_r32_o_12_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 6593 |
|
|
|
| 6594 |
|
|
|
| 6595 |
|
|
--ED1_r32_o_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_11
|
| 6596 |
|
|
--operation mode is normal
|
| 6597 |
|
|
|
| 6598 |
|
|
ED1_r32_o_11_lut_out = HE1_q_a[3];
|
| 6599 |
|
|
ED1_r32_o_11 = DFFEAS(ED1_r32_o_11_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 6600 |
|
|
|
| 6601 |
|
|
|
| 6602 |
|
|
--TB1_dout_1_4 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_4
|
| 6603 |
|
|
--operation mode is normal
|
| 6604 |
|
|
|
| 6605 |
|
|
TB1_dout_1_4 = TB1_dout21 & CB1_dout_2_4 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_4 # !TB1_dout22 & CB1_dout_2_20;
|
| 6606 |
|
|
|
| 6607 |
|
|
|
| 6608 |
|
|
--AD1_CurrState_Sreg0_i[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_i[0]
|
| 6609 |
|
|
--operation mode is normal
|
| 6610 |
|
|
|
| 6611 |
|
|
AD1_CurrState_Sreg0_i[0]_lut_out = !AD1_CurrState_Sreg0[2] & AD1_CurrState_Sreg0_ns_0_i_o2[0] # !sys_rst;
|
| 6612 |
|
|
AD1_CurrState_Sreg0_i[0] = DFFEAS(AD1_CurrState_Sreg0_i[0]_lut_out, E1__clk0, VCC, , , , , , );
|
| 6613 |
|
|
|
| 6614 |
|
|
|
| 6615 |
|
|
--AD1_CurrState_Sreg0[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0[7]
|
| 6616 |
|
|
--operation mode is normal
|
| 6617 |
|
|
|
| 6618 |
|
|
AD1_CurrState_Sreg0[7]_lut_out = WB35L1 & !WB45L1 & WB55L1 & AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
|
| 6619 |
|
|
AD1_CurrState_Sreg0[7] = DFFEAS(AD1_CurrState_Sreg0[7]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 6620 |
|
|
|
| 6621 |
|
|
|
| 6622 |
|
|
--AD1_CurrState_Sreg0[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0[2]
|
| 6623 |
|
|
--operation mode is normal
|
| 6624 |
|
|
|
| 6625 |
|
|
AD1_CurrState_Sreg0[2]_lut_out = !WB35L1 & WB45L1 & !WB55L1 & AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
|
| 6626 |
|
|
AD1_CurrState_Sreg0[2] = DFFEAS(AD1_CurrState_Sreg0[2]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 6627 |
|
|
|
| 6628 |
|
|
|
| 6629 |
|
|
--YB1_alu_func_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1
|
| 6630 |
|
|
--operation mode is normal
|
| 6631 |
|
|
|
| 6632 |
|
|
YB1_alu_func_2_0_0_1 = YB1_alu_func_2_0_0_3_Z[1] # YB1_alu_func_2_0_0_a3_1[1] # WB83L1 & YB1_alu_func_2_0_0_a2_3[1];
|
| 6633 |
|
|
|
| 6634 |
|
|
|
| 6635 |
|
|
--YB1_un1_muxa_ctl370_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_x
|
| 6636 |
|
|
--operation mode is normal
|
| 6637 |
|
|
|
| 6638 |
|
|
YB1_un1_muxa_ctl370_x = YB1_un1_muxa_ctl370_6 # YB1_un1_muxa_ctl370_5;
|
| 6639 |
|
|
|
| 6640 |
|
|
|
| 6641 |
|
|
--YB1_un1_ins_i_22_1_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_22_1_x
|
| 6642 |
|
|
--operation mode is normal
|
| 6643 |
|
|
|
| 6644 |
|
|
YB1_un1_ins_i_22_1_x = !KE1_q_a[6] & KE1_q_a[7] & YB1_un1_ins_i_22_1_a;
|
| 6645 |
|
|
|
| 6646 |
|
|
|
| 6647 |
|
|
--WB83L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_1_|lpm_latch:U1|q[0]~56
|
| 6648 |
|
|
--operation mode is normal
|
| 6649 |
|
|
|
| 6650 |
|
|
WB83L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_alu_func_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB83L1;
|
| 6651 |
|
|
|
| 6652 |
|
|
|
| 6653 |
|
|
--AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_a3_0_o2_0
|
| 6654 |
|
|
--operation mode is normal
|
| 6655 |
|
|
|
| 6656 |
|
|
AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 = AD1_CurrState_Sreg0[8] # AD1_CurrState_Sreg0[1];
|
| 6657 |
|
|
|
| 6658 |
|
|
|
| 6659 |
|
|
--YB1_alu_func_2_0_0_4 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_4
|
| 6660 |
|
|
--operation mode is normal
|
| 6661 |
|
|
|
| 6662 |
|
|
YB1_alu_func_2_0_0_4 = YB1_alu_func_2_0_0_2[4] # WB14L1 & YB1_alu_func_2_0_0_a2_3[1] # !YB1_alu_func_2_0_0_a[4];
|
| 6663 |
|
|
|
| 6664 |
|
|
|
| 6665 |
|
|
--WB14L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_4_|lpm_latch:U1|q[0]~56
|
| 6666 |
|
|
--operation mode is normal
|
| 6667 |
|
|
|
| 6668 |
|
|
WB14L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_alu_func_2_0_0_4 # !YB1_un1_muxa_ctl370_x & WB14L1;
|
| 6669 |
|
|
|
| 6670 |
|
|
|
| 6671 |
|
|
--YB1_alu_func_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_0
|
| 6672 |
|
|
--operation mode is normal
|
| 6673 |
|
|
|
| 6674 |
|
|
YB1_alu_func_2_0_0_0 = YB1_alu_func_2_0_0_a3[0] # YB1_alu_func_2_0_0_2_x[0] # YB1_alu_func_2_0_0_a3_0[0] # !YB1_alu_func_2_0_0_a[0];
|
| 6675 |
|
|
|
| 6676 |
|
|
|
| 6677 |
|
|
--WB73L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_0_|lpm_latch:U1|q[0]~56
|
| 6678 |
|
|
--operation mode is normal
|
| 6679 |
|
|
|
| 6680 |
|
|
WB73L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_alu_func_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB73L1;
|
| 6681 |
|
|
|
| 6682 |
|
|
|
| 6683 |
|
|
--VD1_hilo_37_iv_0_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[4]
|
| 6684 |
|
|
--operation mode is normal
|
| 6685 |
|
|
|
| 6686 |
|
|
VD1_hilo_37_iv_0_a[4] = VD1_hilo_5 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_3 # !VD1_hilo_5 & !VD1_hilo_2_sqmuxa # !VD1_hilo_3;
|
| 6687 |
|
|
|
| 6688 |
|
|
|
| 6689 |
|
|
--VD1_hilo_37_iv_0_0[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[4]
|
| 6690 |
|
|
--operation mode is normal
|
| 6691 |
|
|
|
| 6692 |
|
|
VD1_hilo_37_iv_0_0[4] = VD1_hilo_4 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[4] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_4 & VD1_un134_hilo_combout[4] & VD1_hilo_37_iv_0_a3_0[0];
|
| 6693 |
|
|
|
| 6694 |
|
|
|
| 6695 |
|
|
--VD1_hilo_37_iv_0_a3_1[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_1[0]
|
| 6696 |
|
|
--operation mode is normal
|
| 6697 |
|
|
|
| 6698 |
|
|
VD1_hilo_37_iv_0_a3_1[0] = RC1_alu_func_o_0 & VD1_hilo25;
|
| 6699 |
|
|
|
| 6700 |
|
|
|
| 6701 |
|
|
--VD1_hilo_37_iv_0_a[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[36]
|
| 6702 |
|
|
--operation mode is normal
|
| 6703 |
|
|
|
| 6704 |
|
|
VD1_hilo_37_iv_0_a[36] = !VD1_hilo_37_iv_0_a2_7[36] & !VD1_hilo_37_iv_0_5[36] & VD1_hilo_37 # !VD1_hilo_37_iv_0_a6_0_1[40];
|
| 6705 |
|
|
|
| 6706 |
|
|
|
| 6707 |
|
|
--PC1_muxb_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr:U14|muxb_ctl_o_0
|
| 6708 |
|
|
--operation mode is normal
|
| 6709 |
|
|
|
| 6710 |
|
|
PC1_muxb_ctl_o_0_lut_out = AC1_muxb_ctl_o_0;
|
| 6711 |
|
|
PC1_muxb_ctl_o_0 = DFFEAS(PC1_muxb_ctl_o_0_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 6712 |
|
|
|
| 6713 |
|
|
|
| 6714 |
|
|
--PC1_muxb_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr:U14|muxb_ctl_o_1
|
| 6715 |
|
|
--operation mode is normal
|
| 6716 |
|
|
|
| 6717 |
|
|
PC1_muxb_ctl_o_1_lut_out = AC1_muxb_ctl_o_1;
|
| 6718 |
|
|
PC1_muxb_ctl_o_1 = DFFEAS(PC1_muxb_ctl_o_1_lut_out, E1__clk0, VCC, , , , , !AD1_NET1640_i, );
|
| 6719 |
|
|
|
| 6720 |
|
|
|
| 6721 |
|
|
--QD1_b_o18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o18
|
| 6722 |
|
|
--operation mode is normal
|
| 6723 |
|
|
|
| 6724 |
|
|
QD1_b_o18 = !PC1_muxb_ctl_o_0 & PC1_muxb_ctl_o_1;
|
| 6725 |
|
|
|
| 6726 |
|
|
|
| 6727 |
|
|
--QD1_un1_b_o18_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|un1_b_o18_2
|
| 6728 |
|
|
--operation mode is normal
|
| 6729 |
|
|
|
| 6730 |
|
|
QD1_un1_b_o18_2 = PC1_muxb_ctl_o_0 & PC1_muxb_ctl_o_1 & !QD1_b_o18 # !PC1_muxb_ctl_o_1 & XD1_un32_mux_fw # !PC1_muxb_ctl_o_0 & !QD1_b_o18;
|
| 6731 |
|
|
|
| 6732 |
|
|
|
| 6733 |
|
|
--QD1_b_o_1_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_1_sqmuxa
|
| 6734 |
|
|
--operation mode is normal
|
| 6735 |
|
|
|
| 6736 |
|
|
QD1_b_o_1_sqmuxa = PC1_muxb_ctl_o_0 & !PC1_muxb_ctl_o_1 & ND1_dout7;
|
| 6737 |
|
|
|
| 6738 |
|
|
|
| 6739 |
|
|
--VD1_rdy_0_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|rdy_0_sqmuxa
|
| 6740 |
|
|
--operation mode is normal
|
| 6741 |
|
|
|
| 6742 |
|
|
VD1_rdy_0_sqmuxa = !RC1_alu_func_o_2 & RC1_alu_func_o_3 & !RC1_alu_func_o_4 & VD1_addnop2109_0_a2;
|
| 6743 |
|
|
|
| 6744 |
|
|
|
| 6745 |
|
|
--HB1_BUS2446_cout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|BUS2446_cout[2]
|
| 6746 |
|
|
--operation mode is arithmetic
|
| 6747 |
|
|
|
| 6748 |
|
|
HB1_BUS2446_cout[2] = CARRY(KB1_r32_o_2 & KB1_r32_o_3);
|
| 6749 |
|
|
|
| 6750 |
|
|
|
| 6751 |
|
|
--ED1_r32_o_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_2
|
| 6752 |
|
|
--operation mode is normal
|
| 6753 |
|
|
|
| 6754 |
|
|
ED1_r32_o_2_lut_out = GE1_q_a[2];
|
| 6755 |
|
|
ED1_r32_o_2 = DFFEAS(ED1_r32_o_2_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 6756 |
|
|
|
| 6757 |
|
|
|
| 6758 |
|
|
--CD1_res_7_0_0_0_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_2
|
| 6759 |
|
|
--operation mode is normal
|
| 6760 |
|
|
|
| 6761 |
|
|
CD1_res_7_0_0_0_2 = ED1_r32_o_4 & CD1_res_7_0_0_a2_0 # ED1_r32_o_10 & CD1_res_7_0_0_0_a_0 # !ED1_r32_o_4 & ED1_r32_o_10 & CD1_res_7_0_0_0_a_0;
|
| 6762 |
|
|
|
| 6763 |
|
|
|
| 6764 |
|
|
--CD1_res_7_0_0_o3_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_o3_0
|
| 6765 |
|
|
--operation mode is normal
|
| 6766 |
|
|
|
| 6767 |
|
|
CD1_res_7_0_0_o3_0 = CD1_res_7_0_0_a2[18] # !DC1_ext_ctl_o_1 & DC1_ext_ctl_o_2 & !DC1_ext_ctl_o_0;
|
| 6768 |
|
|
|
| 6769 |
|
|
|
| 6770 |
|
|
--GC1_muxa_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr_cls:U7|muxa_ctl_o_1
|
| 6771 |
|
|
--operation mode is normal
|
| 6772 |
|
|
|
| 6773 |
|
|
GC1_muxa_ctl_o_1_lut_out = WB75L2;
|
| 6774 |
|
|
GC1_muxa_ctl_o_1 = DFFEAS(GC1_muxa_ctl_o_1_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 6775 |
|
|
|
| 6776 |
|
|
|
| 6777 |
|
|
--PD1_a_o_sn_m2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_sn_m2
|
| 6778 |
|
|
--operation mode is normal
|
| 6779 |
|
|
|
| 6780 |
|
|
PD1_a_o_sn_m2 = SC1_muxa_ctl_o_1 & WD1_un14_mux_fw # WD1_un1_mux_fw_NE # !XC1_wb_we_o_0;
|
| 6781 |
|
|
|
| 6782 |
|
|
|
| 6783 |
|
|
--PD1_a_o_3_d_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[4]
|
| 6784 |
|
|
--operation mode is normal
|
| 6785 |
|
|
|
| 6786 |
|
|
PD1_a_o_3_d_a[4] = PD1_a_o_sn_m2 & !PB1_r32_o_4 # !PD1_a_o_sn_m2 & !AB1_r32_o_2;
|
| 6787 |
|
|
|
| 6788 |
|
|
|
| 6789 |
|
|
--PD1_un6_a_o is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|un6_a_o
|
| 6790 |
|
|
--operation mode is normal
|
| 6791 |
|
|
|
| 6792 |
|
|
PD1_un6_a_o = PD1_un6_a_o_a & WD1_un14_mux_fw # WD1_un1_mux_fw_NE # !XC1_wb_we_o_0;
|
| 6793 |
|
|
|
| 6794 |
|
|
|
| 6795 |
|
|
--RD1_r32_o_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_3
|
| 6796 |
|
|
--operation mode is arithmetic
|
| 6797 |
|
|
|
| 6798 |
|
|
RD1_r32_o_3_lut_out = KB1_r32_o_2 $ KB1_r32_o_3;
|
| 6799 |
|
|
RD1_r32_o_3 = DFFEAS(RD1_r32_o_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 6800 |
|
|
|
| 6801 |
|
|
--RD1_r32_o_cout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[3]
|
| 6802 |
|
|
--operation mode is arithmetic
|
| 6803 |
|
|
|
| 6804 |
|
|
RD1_r32_o_cout[3] = CARRY(KB1_r32_o_2 & KB1_r32_o_3);
|
| 6805 |
|
|
|
| 6806 |
|
|
|
| 6807 |
|
|
--FB1_res_7_0_0_3 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_3
|
| 6808 |
|
|
--operation mode is normal
|
| 6809 |
|
|
|
| 6810 |
|
|
FB1_res_7_0_0_3 = ED1_r32_o_1 & CD1_res_7_0_0_o3_0 # !CD1_res_7_0_0_a_0;
|
| 6811 |
|
|
|
| 6812 |
|
|
--FB1_r32_o_0_3 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_3
|
| 6813 |
|
|
--operation mode is normal
|
| 6814 |
|
|
|
| 6815 |
|
|
FB1_r32_o_0_3 = DFFEAS(FB1_res_7_0_0_3, E1__clk0, VCC, , , , , , );
|
| 6816 |
|
|
|
| 6817 |
|
|
|
| 6818 |
|
|
--SD1_r32_o_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_3
|
| 6819 |
|
|
--operation mode is normal
|
| 6820 |
|
|
|
| 6821 |
|
|
SD1_r32_o_3_lut_out = KB1_r32_o_3;
|
| 6822 |
|
|
SD1_r32_o_3 = DFFEAS(SD1_r32_o_3_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 6823 |
|
|
|
| 6824 |
|
|
|
| 6825 |
|
|
--PD1_a_o_3_d[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[3]
|
| 6826 |
|
|
--operation mode is normal
|
| 6827 |
|
|
|
| 6828 |
|
|
PD1_a_o_3_d[3] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_3 # !PD1_un6_a_o & !PD1_a_o_3_d_a[3] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[3];
|
| 6829 |
|
|
|
| 6830 |
|
|
|
| 6831 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[3] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[3]
|
| 6832 |
|
|
--operation mode is normal
|
| 6833 |
|
|
|
| 6834 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[3] = QB1_r32_o_3 & !FB1_r32_o_0_3 & QD1_b_o18 # !QB1_r32_o_3 & QD1_un1_b_o18_2 # !FB1_r32_o_0_3 & QD1_b_o18;
|
| 6835 |
|
|
|
| 6836 |
|
|
|
| 6837 |
|
|
--G1_BUS15471_i_m[3] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[3]
|
| 6838 |
|
|
--operation mode is normal
|
| 6839 |
|
|
|
| 6840 |
|
|
G1_BUS15471_i_m[3] = !FD1_wb_o_3 & QD1_b_o_1_sqmuxa;
|
| 6841 |
|
|
|
| 6842 |
|
|
|
| 6843 |
|
|
--TD1_un1_b_1_combout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[1]
|
| 6844 |
|
|
--operation mode is normal
|
| 6845 |
|
|
|
| 6846 |
|
|
TD1_un1_b_1_combout[1] = TD1_sum13_0_a2 $ !VD1_b_o_iv_1;
|
| 6847 |
|
|
|
| 6848 |
|
|
|
| 6849 |
|
|
--UD1_shift_out_85_d_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[4]
|
| 6850 |
|
|
--operation mode is normal
|
| 6851 |
|
|
|
| 6852 |
|
|
UD1_shift_out_85_d_a[4] = PD1_a_o_2 & VD1_b_o_iv_0 & !PD1_a_o_1 # !PD1_a_o_2 & !VD1_b_o_iv_2;
|
| 6853 |
|
|
|
| 6854 |
|
|
|
| 6855 |
|
|
--UD1_shift_out_87_d_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[4]
|
| 6856 |
|
|
--operation mode is normal
|
| 6857 |
|
|
|
| 6858 |
|
|
UD1_shift_out_87_d_a[4] = PD1_a_o_1 & !VD1_b_o_iv_10 # !PD1_a_o_1 & !VD1_b_o_iv_8;
|
| 6859 |
|
|
|
| 6860 |
|
|
|
| 6861 |
|
|
--UD1_shift_out_80[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[4]
|
| 6862 |
|
|
--operation mode is normal
|
| 6863 |
|
|
|
| 6864 |
|
|
UD1_shift_out_80[4] = PD1_a_o_2 & UD1_shift_out_80_a[4] & VD1_b_o_iv_9 # !UD1_shift_out_80_a[4] & VD1_b_o_iv_11 # !PD1_a_o_2 & !UD1_shift_out_80_a[4];
|
| 6865 |
|
|
|
| 6866 |
|
|
|
| 6867 |
|
|
--UD1_shift_out_79[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[4]
|
| 6868 |
|
|
--operation mode is normal
|
| 6869 |
|
|
|
| 6870 |
|
|
UD1_shift_out_79[4] = PD1_a_o_1 & UD1_shift_out_79_a[4] & VD1_b_o_iv_14 # !UD1_shift_out_79_a[4] & VD1_b_o_iv_15 # !PD1_a_o_1 & !UD1_shift_out_79_a[4];
|
| 6871 |
|
|
|
| 6872 |
|
|
|
| 6873 |
|
|
--UD1_shift_out_79[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[16]
|
| 6874 |
|
|
--operation mode is normal
|
| 6875 |
|
|
|
| 6876 |
|
|
UD1_shift_out_79[16] = PD1_a_o_1 & UD1_shift_out_79_a[16] & VD1_b_o_iv_26 # !UD1_shift_out_79_a[16] & VD1_b_o_iv_27 # !PD1_a_o_1 & !UD1_shift_out_79_a[16];
|
| 6877 |
|
|
|
| 6878 |
|
|
|
| 6879 |
|
|
--UD1_shift_out_79[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[20]
|
| 6880 |
|
|
--operation mode is normal
|
| 6881 |
|
|
|
| 6882 |
|
|
UD1_shift_out_79[20] = PD1_a_o_1 & UD1_shift_out_79_a[20] & VD1_b_o_iv_30 # !UD1_shift_out_79_a[20] & VD1_b_o_iv_31 # !PD1_a_o_1 & !UD1_shift_out_79_a[20];
|
| 6883 |
|
|
|
| 6884 |
|
|
|
| 6885 |
|
|
--UD1_shift_out_79[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[8]
|
| 6886 |
|
|
--operation mode is normal
|
| 6887 |
|
|
|
| 6888 |
|
|
UD1_shift_out_79[8] = PD1_a_o_1 & UD1_shift_out_79_a[8] & VD1_b_o_iv_18 # !UD1_shift_out_79_a[8] & VD1_b_o_iv_19 # !PD1_a_o_1 & !UD1_shift_out_79_a[8];
|
| 6889 |
|
|
|
| 6890 |
|
|
|
| 6891 |
|
|
--UD1_shift_out_47[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_47[0]
|
| 6892 |
|
|
--operation mode is normal
|
| 6893 |
|
|
|
| 6894 |
|
|
UD1_shift_out_47[0] = PD1_a_o_1 & !UD1_shift_out_47_a[0] # !PD1_a_o_1 & UD1_shift_out_47_a[0] & VD1_b_o_iv_20 # !UD1_shift_out_47_a[0] & VD1_b_o_iv_21;
|
| 6895 |
|
|
|
| 6896 |
|
|
|
| 6897 |
|
|
--UD1_shift_out_74_c[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_c[4]
|
| 6898 |
|
|
--operation mode is normal
|
| 6899 |
|
|
|
| 6900 |
|
|
UD1_shift_out_74_c[4] = PD1_a_o_2 & PD1_a_o_3 # !PD1_a_o_2 & PD1_a_o_3 & UD1_shift_out_79[20] # !PD1_a_o_3 & UD1_shift_out_47[0];
|
| 6901 |
|
|
|
| 6902 |
|
|
|
| 6903 |
|
|
--VD1_hilo_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_6
|
| 6904 |
|
|
--operation mode is normal
|
| 6905 |
|
|
|
| 6906 |
|
|
VD1_hilo_6_lut_out = VD1_hilo_37_iv_0_0[6] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_6 # !VD1_hilo_37_iv_0_a[6];
|
| 6907 |
|
|
VD1_hilo_6 = DFFEAS(VD1_hilo_6_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 6908 |
|
|
|
| 6909 |
|
|
|
| 6910 |
|
|
--VD1_hilo_1_sqmuxa_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1_sqmuxa_1
|
| 6911 |
|
|
--operation mode is normal
|
| 6912 |
|
|
|
| 6913 |
|
|
VD1_hilo_1_sqmuxa_1 = !VD1_count[5] & !VD1_overflow & VD1_mul & VD1_addnop2110;
|
| 6914 |
|
|
|
| 6915 |
|
|
|
| 6916 |
|
|
--VD1_hilo_2_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_2_sqmuxa
|
| 6917 |
|
|
--operation mode is normal
|
| 6918 |
|
|
|
| 6919 |
|
|
VD1_hilo_2_sqmuxa = !VD1_count[5] & !VD1_overflow & !VD1_mul & VD1_addnop2110;
|
| 6920 |
|
|
|
| 6921 |
|
|
|
| 6922 |
|
|
--VD1_addnop2109_0_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop2109_0_a2
|
| 6923 |
|
|
--operation mode is normal
|
| 6924 |
|
|
|
| 6925 |
|
|
VD1_addnop2109_0_a2 = VD1_rdy & !VD1_hilo25;
|
| 6926 |
|
|
|
| 6927 |
|
|
|
| 6928 |
|
|
--VD1_hilo_37_iv_0_a3_1[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_1[62]
|
| 6929 |
|
|
--operation mode is normal
|
| 6930 |
|
|
|
| 6931 |
|
|
VD1_hilo_37_iv_0_a3_1[62] = !RC1_alu_func_o_0 & VD1_hilo25;
|
| 6932 |
|
|
|
| 6933 |
|
|
|
| 6934 |
|
|
--VD1_un134_hilo_combout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[5]
|
| 6935 |
|
|
--operation mode is arithmetic
|
| 6936 |
|
|
|
| 6937 |
|
|
VD1_un134_hilo_combout[5]_carry_eqn = VD1_un134_hilo_cout[3];
|
| 6938 |
|
|
VD1_un134_hilo_combout[5] = VD1_hilo_5 $ (VD1_hilo_4 & !VD1_un134_hilo_combout[5]_carry_eqn);
|
| 6939 |
|
|
|
| 6940 |
|
|
--VD1_un134_hilo_cout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[5]
|
| 6941 |
|
|
--operation mode is arithmetic
|
| 6942 |
|
|
|
| 6943 |
|
|
VD1_un134_hilo_cout[5] = CARRY(VD1_hilo_4 & VD1_hilo_5 & !VD1_un134_hilo_cout[3]);
|
| 6944 |
|
|
|
| 6945 |
|
|
|
| 6946 |
|
|
--VD1_hilo_37_iv_0_a3_0[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_0[0]
|
| 6947 |
|
|
--operation mode is normal
|
| 6948 |
|
|
|
| 6949 |
|
|
VD1_hilo_37_iv_0_a3_0[0] = VD1_add1 & VD1_hilo_3_sqmuxa;
|
| 6950 |
|
|
|
| 6951 |
|
|
|
| 6952 |
|
|
--VD1_hilo_37_iv_0_o5[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5[0]
|
| 6953 |
|
|
--operation mode is normal
|
| 6954 |
|
|
|
| 6955 |
|
|
VD1_hilo_37_iv_0_o5[0] = VD1_hilo_37_iv_0_a3_1[0] # !VD1_add1 & VD1_hilo_3_sqmuxa;
|
| 6956 |
|
|
|
| 6957 |
|
|
|
| 6958 |
|
|
--VD1_un17_mul_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un17_mul_0
|
| 6959 |
|
|
--operation mode is normal
|
| 6960 |
|
|
|
| 6961 |
|
|
VD1_un17_mul_0 = !RC1_alu_func_o_2 & RC1_alu_func_o_3 & !RC1_alu_func_o_4;
|
| 6962 |
|
|
|
| 6963 |
|
|
--VD1_start is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|start
|
| 6964 |
|
|
--operation mode is normal
|
| 6965 |
|
|
|
| 6966 |
|
|
VD1_start = DFFEAS(VD1_un17_mul_0, E1__clk0, VCC, , VD1_mul_0_sqmuxa_i, , , , );
|
| 6967 |
|
|
|
| 6968 |
|
|
|
| 6969 |
|
|
--C1_G_505_a is mips_sys:isys|G_505_a
|
| 6970 |
|
|
--operation mode is normal
|
| 6971 |
|
|
|
| 6972 |
|
|
C1_G_505_a = !VD1_rdy & !VD1_hilo25 & VD1_hilo_4_sqmuxa_0 # !VD1_start;
|
| 6973 |
|
|
|
| 6974 |
|
|
|
| 6975 |
|
|
--VD1_sub_or_yn is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sub_or_yn
|
| 6976 |
|
|
--operation mode is normal
|
| 6977 |
|
|
|
| 6978 |
|
|
VD1_sub_or_yn_lut_out = C1_I_437_a_x & VD1_mul & VD1_hilo[0] # !VD1_mul & !VD1_eqop2_2_32;
|
| 6979 |
|
|
VD1_sub_or_yn = DFFEAS(VD1_sub_or_yn_lut_out, E1__clk0, VCC, , VD1_sub_or_yn_0_sqmuxa_1_i, , , , );
|
| 6980 |
|
|
|
| 6981 |
|
|
|
| 6982 |
|
|
--VD1_hilo_37_iv_0_a2_7_2_1[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_7_2_1[37]
|
| 6983 |
|
|
--operation mode is normal
|
| 6984 |
|
|
|
| 6985 |
|
|
VD1_hilo_37_iv_0_a2_7_2_1[37] = VD1_sign & VD1_hilo[0];
|
| 6986 |
|
|
|
| 6987 |
|
|
|
| 6988 |
|
|
--VD1_un50_hilo_add6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add6
|
| 6989 |
|
|
--operation mode is arithmetic
|
| 6990 |
|
|
|
| 6991 |
|
|
VD1_un50_hilo_add6_carry_eqn = VD1_un50_hilo_carry_5;
|
| 6992 |
|
|
VD1_un50_hilo_add6 = VD1_hilo_38 $ VD1_nop2_reged[6] $ !VD1_un50_hilo_add6_carry_eqn;
|
| 6993 |
|
|
|
| 6994 |
|
|
--VD1_un50_hilo_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_6
|
| 6995 |
|
|
--operation mode is arithmetic
|
| 6996 |
|
|
|
| 6997 |
|
|
VD1_un50_hilo_carry_6 = CARRY(VD1_hilo_38 & VD1_nop2_reged[6] # !VD1_un50_hilo_carry_5 # !VD1_hilo_38 & VD1_nop2_reged[6] & !VD1_un50_hilo_carry_5);
|
| 6998 |
|
|
|
| 6999 |
|
|
|
| 7000 |
|
|
--VD1_un59_hilo_add6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add6
|
| 7001 |
|
|
--operation mode is arithmetic
|
| 7002 |
|
|
|
| 7003 |
|
|
VD1_un59_hilo_add6_carry_eqn = VD1_un59_hilo_carry_5;
|
| 7004 |
|
|
VD1_un59_hilo_add6 = VD1_hilo_38 $ VD1_op2_reged[6] $ !VD1_un59_hilo_add6_carry_eqn;
|
| 7005 |
|
|
|
| 7006 |
|
|
--VD1_un59_hilo_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_6
|
| 7007 |
|
|
--operation mode is arithmetic
|
| 7008 |
|
|
|
| 7009 |
|
|
VD1_un59_hilo_carry_6 = CARRY(VD1_hilo_38 & VD1_op2_reged[6] # !VD1_un59_hilo_carry_5 # !VD1_hilo_38 & VD1_op2_reged[6] & !VD1_un59_hilo_carry_5);
|
| 7010 |
|
|
|
| 7011 |
|
|
|
| 7012 |
|
|
--VD1_hilo_37_iv_0_1[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[37]
|
| 7013 |
|
|
--operation mode is normal
|
| 7014 |
|
|
|
| 7015 |
|
|
VD1_hilo_37_iv_0_1[37] = VD1_hilo_37_iv_0_1_a[37] # VD1_addop2 & !VD1_un59_hilo_add5 & VD1_hilo_37_iv_0_a2_7[34];
|
| 7016 |
|
|
|
| 7017 |
|
|
|
| 7018 |
|
|
--VD1_hilo_37_iv_0_a6_1_0[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a6_1_0[40]
|
| 7019 |
|
|
--operation mode is normal
|
| 7020 |
|
|
|
| 7021 |
|
|
VD1_hilo_37_iv_0_a6_1_0[40] = VD1_hilo_1_sqmuxa_1 & VD1_sign & VD1_sub_or_yn & !VD1_hilo[0] # !VD1_sign & VD1_hilo[0];
|
| 7022 |
|
|
|
| 7023 |
|
|
|
| 7024 |
|
|
--VD1_hilo_37_iv_0_5_a[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[37]
|
| 7025 |
|
|
--operation mode is normal
|
| 7026 |
|
|
|
| 7027 |
|
|
VD1_hilo_37_iv_0_5_a[37] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add5 # !VD1_hilo_24_add5 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add5;
|
| 7028 |
|
|
|
| 7029 |
|
|
|
| 7030 |
|
|
--VD1_hilo_38 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_38
|
| 7031 |
|
|
--operation mode is normal
|
| 7032 |
|
|
|
| 7033 |
|
|
VD1_hilo_38_lut_out = !VD1_hilo_37_iv_0_5[38] & !VD1_hilo_37_iv_0_4[38] & !VD1_hilo_37_iv_0_a[38] & !VD1_hilo_37_iv_0_a2[39];
|
| 7034 |
|
|
VD1_hilo_38 = DFFEAS(VD1_hilo_38_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 7035 |
|
|
|
| 7036 |
|
|
|
| 7037 |
|
|
--VD1_hilo_37_iv_0_a6_0_1[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a6_0_1[40]
|
| 7038 |
|
|
--operation mode is normal
|
| 7039 |
|
|
|
| 7040 |
|
|
VD1_hilo_37_iv_0_a6_0_1[40] = VD1_hilo_1_sqmuxa_1 & VD1_hilo[0] $ (!VD1_sub_or_yn # !VD1_sign);
|
| 7041 |
|
|
|
| 7042 |
|
|
|
| 7043 |
|
|
--VD1_hilo_37_iv_0_o3[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3[34]
|
| 7044 |
|
|
--operation mode is normal
|
| 7045 |
|
|
|
| 7046 |
|
|
VD1_hilo_37_iv_0_o3[34] = VD1_un29_sign_0_o2_0 # !PD1_a_o_31 # !RC1_alu_func_o_1 # !RC1_alu_func_o_3;
|
| 7047 |
|
|
|
| 7048 |
|
|
|
| 7049 |
|
|
--ED1_r32_o_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_3
|
| 7050 |
|
|
--operation mode is normal
|
| 7051 |
|
|
|
| 7052 |
|
|
ED1_r32_o_3_lut_out = GE1_q_a[3];
|
| 7053 |
|
|
ED1_r32_o_3 = DFFEAS(ED1_r32_o_3_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 7054 |
|
|
|
| 7055 |
|
|
|
| 7056 |
|
|
--ED1_r32_o_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_5
|
| 7057 |
|
|
--operation mode is normal
|
| 7058 |
|
|
|
| 7059 |
|
|
ED1_r32_o_5_lut_out = GE1_q_a[5];
|
| 7060 |
|
|
ED1_r32_o_5 = DFFEAS(ED1_r32_o_5_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 7061 |
|
|
|
| 7062 |
|
|
|
| 7063 |
|
|
--CD1_res_7_0_0_a2_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a2_0
|
| 7064 |
|
|
--operation mode is normal
|
| 7065 |
|
|
|
| 7066 |
|
|
CD1_res_7_0_0_a2_0 = !DC1_ext_ctl_o_2 & DC1_ext_ctl_o_1 $ DC1_ext_ctl_o_0;
|
| 7067 |
|
|
|
| 7068 |
|
|
|
| 7069 |
|
|
--PD1_a_o_3_d_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[5]
|
| 7070 |
|
|
--operation mode is normal
|
| 7071 |
|
|
|
| 7072 |
|
|
PD1_a_o_3_d_a[5] = PD1_a_o_sn_m2 & !PB1_r32_o_5 # !PD1_a_o_sn_m2 & !AB1_r32_o_3;
|
| 7073 |
|
|
|
| 7074 |
|
|
|
| 7075 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[7] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[7]
|
| 7076 |
|
|
--operation mode is normal
|
| 7077 |
|
|
|
| 7078 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[7] = QB1_r32_o_7 & !FB1_r32_o_0_7 & QD1_b_o18 # !QB1_r32_o_7 & QD1_un1_b_o18_2 # !FB1_r32_o_0_7 & QD1_b_o18;
|
| 7079 |
|
|
|
| 7080 |
|
|
|
| 7081 |
|
|
--G1_BUS15471_i_m[7] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[7]
|
| 7082 |
|
|
--operation mode is normal
|
| 7083 |
|
|
|
| 7084 |
|
|
G1_BUS15471_i_m[7] = !FD1_wb_o_7 & QD1_b_o_1_sqmuxa;
|
| 7085 |
|
|
|
| 7086 |
|
|
|
| 7087 |
|
|
--UD1_shift_out_87_d_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[5]
|
| 7088 |
|
|
--operation mode is normal
|
| 7089 |
|
|
|
| 7090 |
|
|
UD1_shift_out_87_d_a[5] = PD1_a_o_1 & !VD1_b_o_iv_11 # !PD1_a_o_1 & !VD1_b_o_iv_9;
|
| 7091 |
|
|
|
| 7092 |
|
|
|
| 7093 |
|
|
--UD1_shift_out_80[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[5]
|
| 7094 |
|
|
--operation mode is normal
|
| 7095 |
|
|
|
| 7096 |
|
|
UD1_shift_out_80[5] = PD1_a_o_2 & UD1_shift_out_80_a[5] & VD1_b_o_iv_10 # !UD1_shift_out_80_a[5] & VD1_b_o_iv_12 # !PD1_a_o_2 & !UD1_shift_out_80_a[5];
|
| 7097 |
|
|
|
| 7098 |
|
|
|
| 7099 |
|
|
--UD1_shift_out_85_d_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[5]
|
| 7100 |
|
|
--operation mode is normal
|
| 7101 |
|
|
|
| 7102 |
|
|
UD1_shift_out_85_d_a[5] = PD1_a_o_0 & !VD1_b_o_iv_0 # !PD1_a_o_0 & !VD1_b_o_iv_1;
|
| 7103 |
|
|
|
| 7104 |
|
|
|
| 7105 |
|
|
--UD1_shift_out_68[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[5]
|
| 7106 |
|
|
--operation mode is normal
|
| 7107 |
|
|
|
| 7108 |
|
|
UD1_shift_out_68[5] = PD1_a_o_0 & VD1_b_o_iv_2 # !PD1_a_o_0 & VD1_b_o_iv_3;
|
| 7109 |
|
|
|
| 7110 |
|
|
|
| 7111 |
|
|
--UD1_shift_out_79[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[5]
|
| 7112 |
|
|
--operation mode is normal
|
| 7113 |
|
|
|
| 7114 |
|
|
UD1_shift_out_79[5] = PD1_a_o_1 & UD1_shift_out_79_a[5] & VD1_b_o_iv_15 # !UD1_shift_out_79_a[5] & VD1_b_o_iv_16 # !PD1_a_o_1 & !UD1_shift_out_79_a[5];
|
| 7115 |
|
|
|
| 7116 |
|
|
|
| 7117 |
|
|
--UD1_shift_out_79[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[17]
|
| 7118 |
|
|
--operation mode is normal
|
| 7119 |
|
|
|
| 7120 |
|
|
UD1_shift_out_79[17] = PD1_a_o_1 & UD1_shift_out_79_a[17] & VD1_b_o_iv_27 # !UD1_shift_out_79_a[17] & VD1_b_o_iv_28 # !PD1_a_o_1 & !UD1_shift_out_79_a[17];
|
| 7121 |
|
|
|
| 7122 |
|
|
|
| 7123 |
|
|
--UD1_shift_out_42[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_42[1]
|
| 7124 |
|
|
--operation mode is normal
|
| 7125 |
|
|
|
| 7126 |
|
|
UD1_shift_out_42[1] = PD1_a_o_1 & VD1_b_o_iv_31 & !PD1_a_o_0 # !PD1_a_o_1 & UD1_shift_out_39[17];
|
| 7127 |
|
|
|
| 7128 |
|
|
|
| 7129 |
|
|
--UD1_shift_out_79[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[9]
|
| 7130 |
|
|
--operation mode is normal
|
| 7131 |
|
|
|
| 7132 |
|
|
UD1_shift_out_79[9] = PD1_a_o_1 & UD1_shift_out_79_a[9] & VD1_b_o_iv_19 # !UD1_shift_out_79_a[9] & VD1_b_o_iv_20 # !PD1_a_o_1 & !UD1_shift_out_79_a[9];
|
| 7133 |
|
|
|
| 7134 |
|
|
|
| 7135 |
|
|
--UD1_shift_out_79[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[13]
|
| 7136 |
|
|
--operation mode is normal
|
| 7137 |
|
|
|
| 7138 |
|
|
UD1_shift_out_79[13] = PD1_a_o_1 & UD1_shift_out_79_a[13] & VD1_b_o_iv_23 # !UD1_shift_out_79_a[13] & VD1_b_o_iv_24 # !PD1_a_o_1 & !UD1_shift_out_79_a[13];
|
| 7139 |
|
|
|
| 7140 |
|
|
|
| 7141 |
|
|
--UD1_shift_out_74_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[5]
|
| 7142 |
|
|
--operation mode is normal
|
| 7143 |
|
|
|
| 7144 |
|
|
UD1_shift_out_74_a[5] = PD1_a_o_2 & !VD1_b_o_iv_31 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_31 # !PD1_a_o_1 & !UD1_shift_out_39[17];
|
| 7145 |
|
|
|
| 7146 |
|
|
|
| 7147 |
|
|
--UD1_shift_out_61[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_61[5]
|
| 7148 |
|
|
--operation mode is normal
|
| 7149 |
|
|
|
| 7150 |
|
|
UD1_shift_out_61[5] = PD1_a_o_2 & UD1_shift_out_79[17] # !PD1_a_o_2 & UD1_shift_out_79[13];
|
| 7151 |
|
|
|
| 7152 |
|
|
|
| 7153 |
|
|
--YB1_un1_ins_i_15_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_15_x
|
| 7154 |
|
|
--operation mode is normal
|
| 7155 |
|
|
|
| 7156 |
|
|
YB1_un1_ins_i_15_x = !KE1_q_a[4] & KE1_q_a[2] & YB1_un1_ins_i_18_0_0_a2_x;
|
| 7157 |
|
|
|
| 7158 |
|
|
|
| 7159 |
|
|
--YB1_dmem_ctl_2_0_0_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_2
|
| 7160 |
|
|
--operation mode is normal
|
| 7161 |
|
|
|
| 7162 |
|
|
YB1_dmem_ctl_2_0_0_2 = YB1_dmem_ctl_2_0_0_a3[2] # !KE1_q_a[5] & !KE1_q_a[6] & YB1_dmem_ctl_2_0_0_a[2];
|
| 7163 |
|
|
|
| 7164 |
|
|
|
| 7165 |
|
|
--WB84L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1|q[0]~68
|
| 7166 |
|
|
--operation mode is normal
|
| 7167 |
|
|
|
| 7168 |
|
|
WB84L1 = YB1_un1_ins_i_15_x # YB1_un1_muxa_ctl370_x & YB1_dmem_ctl_2_0_0_2 # !YB1_un1_muxa_ctl370_x & WB84L2;
|
| 7169 |
|
|
|
| 7170 |
|
|
|
| 7171 |
|
|
--YB1_un1_ins_i_18_m_0_0_a3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_18_m_0_0_a3
|
| 7172 |
|
|
--operation mode is normal
|
| 7173 |
|
|
|
| 7174 |
|
|
YB1_un1_ins_i_18_m_0_0_a3 = KE1_q_a[7] & !KE1_q_a[6] & !KE1_q_a[2] & !YB1_un1_ins_i_18_m_0_0_a3_a_x;
|
| 7175 |
|
|
|
| 7176 |
|
|
|
| 7177 |
|
|
--WB84L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1|q[0]~69
|
| 7178 |
|
|
--operation mode is normal
|
| 7179 |
|
|
|
| 7180 |
|
|
WB84L2 = WB84L1 & !YB1_un1_ins_i_18_m_0_0_a3;
|
| 7181 |
|
|
|
| 7182 |
|
|
|
| 7183 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[0] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[0]
|
| 7184 |
|
|
--operation mode is normal
|
| 7185 |
|
|
|
| 7186 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[0] = QB1_r32_o_0 & !FB1_r32_o_0_0 & QD1_b_o18 # !QB1_r32_o_0 & QD1_un1_b_o18_2 # !FB1_r32_o_0_0 & QD1_b_o18;
|
| 7187 |
|
|
|
| 7188 |
|
|
|
| 7189 |
|
|
--G1_BUS15471_i_m[0] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[0]
|
| 7190 |
|
|
--operation mode is normal
|
| 7191 |
|
|
|
| 7192 |
|
|
G1_BUS15471_i_m[0] = !FD1_wb_o_0 & QD1_b_o_1_sqmuxa;
|
| 7193 |
|
|
|
| 7194 |
|
|
|
| 7195 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[1] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[1]
|
| 7196 |
|
|
--operation mode is normal
|
| 7197 |
|
|
|
| 7198 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[1] = !QB1_r32_o_1 & QD1_un1_b_o18_2;
|
| 7199 |
|
|
|
| 7200 |
|
|
|
| 7201 |
|
|
--QD1_b_o_iv_1_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_iv_1_0
|
| 7202 |
|
|
--operation mode is normal
|
| 7203 |
|
|
|
| 7204 |
|
|
QD1_b_o_iv_1_0 = RB1_byte_addr_o_1 & !FD1_wb_o_1 & QD1_b_o_1_sqmuxa # !RB1_byte_addr_o_1 & QD1_b_o_0_sqmuxa # !FD1_wb_o_1 & QD1_b_o_1_sqmuxa;
|
| 7205 |
|
|
|
| 7206 |
|
|
|
| 7207 |
|
|
--UD1_shift_out_80_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[2]
|
| 7208 |
|
|
--operation mode is normal
|
| 7209 |
|
|
|
| 7210 |
|
|
UD1_shift_out_80_a[2] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_5 # !PD1_a_o_1 & !VD1_b_o_iv_3;
|
| 7211 |
|
|
|
| 7212 |
|
|
|
| 7213 |
|
|
--UD1_shift_out_82_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82_a[2]
|
| 7214 |
|
|
--operation mode is normal
|
| 7215 |
|
|
|
| 7216 |
|
|
UD1_shift_out_82_a[2] = PD1_a_o_2 & !VD1_b_o_iv_6 # !PD1_a_o_2 & !VD1_b_o_iv_4;
|
| 7217 |
|
|
|
| 7218 |
|
|
|
| 7219 |
|
|
--UD1_shift_out_79[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[6]
|
| 7220 |
|
|
--operation mode is normal
|
| 7221 |
|
|
|
| 7222 |
|
|
UD1_shift_out_79[6] = PD1_a_o_1 & UD1_shift_out_79_a[6] & VD1_b_o_iv_16 # !UD1_shift_out_79_a[6] & VD1_b_o_iv_17 # !PD1_a_o_1 & !UD1_shift_out_79_a[6];
|
| 7223 |
|
|
|
| 7224 |
|
|
|
| 7225 |
|
|
--UD1_shift_out_79[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[10]
|
| 7226 |
|
|
--operation mode is normal
|
| 7227 |
|
|
|
| 7228 |
|
|
UD1_shift_out_79[10] = PD1_a_o_1 & UD1_shift_out_79_a[10] & VD1_b_o_iv_20 # !UD1_shift_out_79_a[10] & VD1_b_o_iv_21 # !PD1_a_o_1 & !UD1_shift_out_79_a[10];
|
| 7229 |
|
|
|
| 7230 |
|
|
|
| 7231 |
|
|
--UD1_shift_out_41[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_41[2]
|
| 7232 |
|
|
--operation mode is normal
|
| 7233 |
|
|
|
| 7234 |
|
|
UD1_shift_out_41[2] = PD1_a_o_1 & VD1_b_o_iv_31 # !PD1_a_o_1 & PD1_a_o_0 & VD1_b_o_iv_31 # !PD1_a_o_0 & VD1_b_o_iv_30;
|
| 7235 |
|
|
|
| 7236 |
|
|
|
| 7237 |
|
|
--UD1_shift_out_79[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[18]
|
| 7238 |
|
|
--operation mode is normal
|
| 7239 |
|
|
|
| 7240 |
|
|
UD1_shift_out_79[18] = PD1_a_o_1 & UD1_shift_out_79_a[18] & VD1_b_o_iv_28 # !UD1_shift_out_79_a[18] & VD1_b_o_iv_29 # !PD1_a_o_1 & !UD1_shift_out_79_a[18];
|
| 7241 |
|
|
|
| 7242 |
|
|
|
| 7243 |
|
|
--UD1_shift_out_74_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[2]
|
| 7244 |
|
|
--operation mode is normal
|
| 7245 |
|
|
|
| 7246 |
|
|
UD1_shift_out_74_a[2] = PD1_a_o_3 & !PD1_a_o_2 # !PD1_a_o_3 & PD1_a_o_2 & !UD1_shift_out_47[2] # !PD1_a_o_2 & !UD1_shift_out_79[10];
|
| 7247 |
|
|
|
| 7248 |
|
|
|
| 7249 |
|
|
--UD1_shift_out_79[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[2]
|
| 7250 |
|
|
--operation mode is normal
|
| 7251 |
|
|
|
| 7252 |
|
|
UD1_shift_out_79[2] = PD1_a_o_1 & UD1_shift_out_79_a[2] & VD1_b_o_iv_12 # !UD1_shift_out_79_a[2] & VD1_b_o_iv_13 # !PD1_a_o_1 & !UD1_shift_out_79_a[2];
|
| 7253 |
|
|
|
| 7254 |
|
|
|
| 7255 |
|
|
--UD1_shift_out_76_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[2]
|
| 7256 |
|
|
--operation mode is normal
|
| 7257 |
|
|
|
| 7258 |
|
|
UD1_shift_out_76_a[2] = PD1_a_o_3 & !PD1_a_o_1 & UD1_shift_out_39[18] # !PD1_a_o_3 & UD1_shift_out_47[2];
|
| 7259 |
|
|
|
| 7260 |
|
|
|
| 7261 |
|
|
--VD1_hilo_37_iv_0_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[2]
|
| 7262 |
|
|
--operation mode is normal
|
| 7263 |
|
|
|
| 7264 |
|
|
VD1_hilo_37_iv_0_a[2] = VD1_hilo_1 & !VD1_hilo_2_sqmuxa & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_3 # !VD1_hilo_1 & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_3;
|
| 7265 |
|
|
|
| 7266 |
|
|
|
| 7267 |
|
|
--VD1_hilo_37_iv_0_0[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[2]
|
| 7268 |
|
|
--operation mode is normal
|
| 7269 |
|
|
|
| 7270 |
|
|
VD1_hilo_37_iv_0_0[2] = VD1_hilo_2 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[2] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_2 & VD1_un134_hilo_combout[2] & VD1_hilo_37_iv_0_a3_0[0];
|
| 7271 |
|
|
|
| 7272 |
|
|
|
| 7273 |
|
|
--VD1_hilo_37_iv_0_o3_0[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_0[34]
|
| 7274 |
|
|
--operation mode is normal
|
| 7275 |
|
|
|
| 7276 |
|
|
VD1_hilo_37_iv_0_o3_0[34] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add3 # !VD1_hilo_24_add2 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add3;
|
| 7277 |
|
|
|
| 7278 |
|
|
|
| 7279 |
|
|
--VD1_hilo_37_iv_0_a[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[34]
|
| 7280 |
|
|
--operation mode is normal
|
| 7281 |
|
|
|
| 7282 |
|
|
VD1_hilo_37_iv_0_a[34] = !VD1_hilo_37_iv_0_2[34] & !VD1_hilo_37_iv_0_o3_1[34] & !VD1_hilo_37_iv_0_o3[34] # !VD1_addnop2109_0_a2;
|
| 7283 |
|
|
|
| 7284 |
|
|
|
| 7285 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[2] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[2]
|
| 7286 |
|
|
--operation mode is normal
|
| 7287 |
|
|
|
| 7288 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[2] = QB1_r32_o_2 & !FB1_r32_o_0_2 & QD1_b_o18 # !QB1_r32_o_2 & QD1_un1_b_o18_2 # !FB1_r32_o_0_2 & QD1_b_o18;
|
| 7289 |
|
|
|
| 7290 |
|
|
|
| 7291 |
|
|
--G1_BUS15471_i_m[2] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[2]
|
| 7292 |
|
|
--operation mode is normal
|
| 7293 |
|
|
|
| 7294 |
|
|
G1_BUS15471_i_m[2] = !FD1_wb_o_2 & QD1_b_o_1_sqmuxa;
|
| 7295 |
|
|
|
| 7296 |
|
|
|
| 7297 |
|
|
--VD1_hilo_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_3
|
| 7298 |
|
|
--operation mode is normal
|
| 7299 |
|
|
|
| 7300 |
|
|
VD1_hilo_3_lut_out = VD1_hilo_37_iv_0[3] # VD1_hilo25 & VD1_hilo_8_Z[3] # !VD1_hilo_37_iv_a[3];
|
| 7301 |
|
|
VD1_hilo_3 = DFFEAS(VD1_hilo_3_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 7302 |
|
|
|
| 7303 |
|
|
|
| 7304 |
|
|
--VD1_hilo_35 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_35
|
| 7305 |
|
|
--operation mode is normal
|
| 7306 |
|
|
|
| 7307 |
|
|
VD1_hilo_35_lut_out = !VD1_hilo_37_iv_2[35] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[35] # !VD1_hilo25;
|
| 7308 |
|
|
VD1_hilo_35 = DFFEAS(VD1_hilo_35_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 7309 |
|
|
|
| 7310 |
|
|
|
| 7311 |
|
|
--UD1_shift_out_82_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82_a[3]
|
| 7312 |
|
|
--operation mode is normal
|
| 7313 |
|
|
|
| 7314 |
|
|
UD1_shift_out_82_a[3] = PD1_a_o_2 & !VD1_b_o_iv_7 # !PD1_a_o_2 & !VD1_b_o_iv_5;
|
| 7315 |
|
|
|
| 7316 |
|
|
|
| 7317 |
|
|
--UD1_shift_out_80[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[3]
|
| 7318 |
|
|
--operation mode is normal
|
| 7319 |
|
|
|
| 7320 |
|
|
UD1_shift_out_80[3] = PD1_a_o_2 & UD1_shift_out_80_a[3] & VD1_b_o_iv_8 # !UD1_shift_out_80_a[3] & VD1_b_o_iv_10 # !PD1_a_o_2 & !UD1_shift_out_80_a[3];
|
| 7321 |
|
|
|
| 7322 |
|
|
|
| 7323 |
|
|
--UD1_shift_out_81[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_81[3]
|
| 7324 |
|
|
--operation mode is normal
|
| 7325 |
|
|
|
| 7326 |
|
|
UD1_shift_out_81[3] = PD1_a_o_1 & !UD1_shift_out_85_d_a[5] # !PD1_a_o_1 & VD1_b_o_iv_2;
|
| 7327 |
|
|
|
| 7328 |
|
|
|
| 7329 |
|
|
--UD1_shift_out_91_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[3]
|
| 7330 |
|
|
--operation mode is normal
|
| 7331 |
|
|
|
| 7332 |
|
|
UD1_shift_out_91_a[3] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_3 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[3];
|
| 7333 |
|
|
|
| 7334 |
|
|
|
| 7335 |
|
|
--UD1_shift_out_76[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[3]
|
| 7336 |
|
|
--operation mode is normal
|
| 7337 |
|
|
|
| 7338 |
|
|
UD1_shift_out_76[3] = UD1_shift_out587 & PD1_a_o_2 & UD1_shift_out_76_a[3] # !PD1_a_o_2 & UD1_shift_out_79[19];
|
| 7339 |
|
|
|
| 7340 |
|
|
|
| 7341 |
|
|
--UD1_shift_out_86_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[3]
|
| 7342 |
|
|
--operation mode is normal
|
| 7343 |
|
|
|
| 7344 |
|
|
UD1_shift_out_86_a[3] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[7] # !PD1_a_o_2 & !UD1_shift_out_79[11] # !UD1_shift_out587 & !UD1_shift_out_79[7];
|
| 7345 |
|
|
|
| 7346 |
|
|
|
| 7347 |
|
|
--UD1_shift_out_74[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[3]
|
| 7348 |
|
|
--operation mode is normal
|
| 7349 |
|
|
|
| 7350 |
|
|
UD1_shift_out_74[3] = PD1_a_o_2 & UD1_shift_out_74_c[3] & VD1_b_o_iv_31 # !UD1_shift_out_74_c[3] & UD1_shift_out_79[15] # !PD1_a_o_2 & UD1_shift_out_74_c[3];
|
| 7351 |
|
|
|
| 7352 |
|
|
|
| 7353 |
|
|
--YB1_un1_ins_i_20 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_20
|
| 7354 |
|
|
--operation mode is normal
|
| 7355 |
|
|
|
| 7356 |
|
|
YB1_un1_ins_i_20 = !KE1_q_a[4] & YB1_un1_ins_i_18_0_0_a2_x & KE1_q_a[2] # !KE1_q_a[3];
|
| 7357 |
|
|
|
| 7358 |
|
|
|
| 7359 |
|
|
--YB1_dmem_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_0
|
| 7360 |
|
|
--operation mode is normal
|
| 7361 |
|
|
|
| 7362 |
|
|
YB1_dmem_ctl_2_0_0_0 = YB1_alu_func_2_0_0_a3_1_x[4] # YB1_alu_func_2_0_0_a2_0[1] & WB64L2 & YB1_fsm_dly_2_0_0_o2_x[2];
|
| 7363 |
|
|
|
| 7364 |
|
|
|
| 7365 |
|
|
--WB64L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1|q[0]~68
|
| 7366 |
|
|
--operation mode is normal
|
| 7367 |
|
|
|
| 7368 |
|
|
WB64L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_dmem_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB64L2;
|
| 7369 |
|
|
|
| 7370 |
|
|
|
| 7371 |
|
|
--YB1_un1_ins_i_23_2_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_23_2_0
|
| 7372 |
|
|
--operation mode is normal
|
| 7373 |
|
|
|
| 7374 |
|
|
YB1_un1_ins_i_23_2_0 = KE1_q_a[3] & YB1_un1_ins_i_23_2_0_a_x & KE1_q_a[4] # KE1_q_a[5];
|
| 7375 |
|
|
|
| 7376 |
|
|
|
| 7377 |
|
|
--WB64L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1|q[0]~69
|
| 7378 |
|
|
--operation mode is normal
|
| 7379 |
|
|
|
| 7380 |
|
|
WB64L2 = WB64L1 & !YB1_un1_ins_i_23_2_0;
|
| 7381 |
|
|
|
| 7382 |
|
|
|
| 7383 |
|
|
--YB1_muxa_ctl373 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl373
|
| 7384 |
|
|
--operation mode is normal
|
| 7385 |
|
|
|
| 7386 |
|
|
YB1_muxa_ctl373 = !KE1_q_a[6] & !KE1_q_a[4] & !KE1_q_a[3] & !YB1_muxa_ctl373_a_x;
|
| 7387 |
|
|
|
| 7388 |
|
|
|
| 7389 |
|
|
--YB1_dmem_ctl_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_1
|
| 7390 |
|
|
--operation mode is normal
|
| 7391 |
|
|
|
| 7392 |
|
|
YB1_dmem_ctl_2_0_0_1 = YB1_dmem_ctl_2_0_0_1_Z[1] # WB74L2 & YB1_alu_func_2_0_0_a2_0[1] & !YB1_dmem_ctl_2_0_0_a_x[1];
|
| 7393 |
|
|
|
| 7394 |
|
|
|
| 7395 |
|
|
--WB74L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1|q[0]~68
|
| 7396 |
|
|
--operation mode is normal
|
| 7397 |
|
|
|
| 7398 |
|
|
WB74L1 = YB1_muxa_ctl373 # YB1_un1_muxa_ctl370_x & YB1_dmem_ctl_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB74L2;
|
| 7399 |
|
|
|
| 7400 |
|
|
|
| 7401 |
|
|
--YB1_un1_ins_i_22_u_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_22_u_x
|
| 7402 |
|
|
--operation mode is normal
|
| 7403 |
|
|
|
| 7404 |
|
|
YB1_un1_ins_i_22_u_x = YB1_un1_ins_i_22_1_x & KE1_q_a[3] # !KE1_q_a[2];
|
| 7405 |
|
|
|
| 7406 |
|
|
|
| 7407 |
|
|
--WB74L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1|q[0]~69
|
| 7408 |
|
|
--operation mode is normal
|
| 7409 |
|
|
|
| 7410 |
|
|
WB74L2 = WB74L1 & !YB1_un1_ins_i_22_u_x;
|
| 7411 |
|
|
|
| 7412 |
|
|
|
| 7413 |
|
|
--UD1_shift_out_87[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[16]
|
| 7414 |
|
|
--operation mode is normal
|
| 7415 |
|
|
|
| 7416 |
|
|
UD1_shift_out_87[16] = PD1_a_o_2 & UD1_shift_out_87_d[16] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[16] # !PD1_a_o_0 & VD1_b_o_iv_18;
|
| 7417 |
|
|
|
| 7418 |
|
|
|
| 7419 |
|
|
--UD1_shift_out_89_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[16]
|
| 7420 |
|
|
--operation mode is normal
|
| 7421 |
|
|
|
| 7422 |
|
|
UD1_shift_out_89_a[16] = PD1_a_o_2 & !UD1_shift_out_85_d[16] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[16] # !PD1_a_o_1 & !VD1_b_o_iv_15;
|
| 7423 |
|
|
|
| 7424 |
|
|
|
| 7425 |
|
|
--UD1_shift_out_86_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_16
|
| 7426 |
|
|
--operation mode is normal
|
| 7427 |
|
|
|
| 7428 |
|
|
UD1_shift_out_86_16 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[16] & UD1_shift_out_79[20] # !UD1_shift_out_sn_b9_0 & VD1_b_o_iv_31;
|
| 7429 |
|
|
|
| 7430 |
|
|
|
| 7431 |
|
|
--UD1_shift_out_92_d_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_8
|
| 7432 |
|
|
--operation mode is normal
|
| 7433 |
|
|
|
| 7434 |
|
|
UD1_shift_out_92_d_8 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[16] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[16];
|
| 7435 |
|
|
|
| 7436 |
|
|
|
| 7437 |
|
|
--MD1_c_0_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[16]
|
| 7438 |
|
|
--operation mode is normal
|
| 7439 |
|
|
|
| 7440 |
|
|
MD1_c_0_a[16] = VD1_un24_res & !VD1_hilo_48 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_16;
|
| 7441 |
|
|
|
| 7442 |
|
|
|
| 7443 |
|
|
--TD1_m36 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m36
|
| 7444 |
|
|
--operation mode is normal
|
| 7445 |
|
|
|
| 7446 |
|
|
TD1_m36 = PD1_a_o_16 & TD1_m36_a # !PD1_a_o_16 & TD1_m36_a & !TD1_m4 # !TD1_m36_a & TD1_m7;
|
| 7447 |
|
|
|
| 7448 |
|
|
|
| 7449 |
|
|
--TD1_m33 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m33
|
| 7450 |
|
|
--operation mode is normal
|
| 7451 |
|
|
|
| 7452 |
|
|
TD1_m33 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add16;
|
| 7453 |
|
|
|
| 7454 |
|
|
|
| 7455 |
|
|
--UD1_shift_out_87[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[17]
|
| 7456 |
|
|
--operation mode is normal
|
| 7457 |
|
|
|
| 7458 |
|
|
UD1_shift_out_87[17] = PD1_a_o_2 & UD1_shift_out_87_d[17] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[17] # !PD1_a_o_0 & VD1_b_o_iv_19;
|
| 7459 |
|
|
|
| 7460 |
|
|
|
| 7461 |
|
|
--UD1_shift_out_89_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[17]
|
| 7462 |
|
|
--operation mode is normal
|
| 7463 |
|
|
|
| 7464 |
|
|
UD1_shift_out_89_a[17] = PD1_a_o_2 & !UD1_shift_out_85_d[17] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[17] # !PD1_a_o_1 & !VD1_b_o_iv_16;
|
| 7465 |
|
|
|
| 7466 |
|
|
|
| 7467 |
|
|
--UD1_shift_out_92_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_a[17]
|
| 7468 |
|
|
--operation mode is normal
|
| 7469 |
|
|
|
| 7470 |
|
|
UD1_shift_out_92_a[17] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_83[17] # !UD1_shift_out_sn_b9_0 & !VD1_b_o_iv_31;
|
| 7471 |
|
|
|
| 7472 |
|
|
|
| 7473 |
|
|
--UD1_shift_out_92_d[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[17]
|
| 7474 |
|
|
--operation mode is normal
|
| 7475 |
|
|
|
| 7476 |
|
|
UD1_shift_out_92_d[17] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[17] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[17];
|
| 7477 |
|
|
|
| 7478 |
|
|
|
| 7479 |
|
|
--MD1_c_0_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[17]
|
| 7480 |
|
|
--operation mode is normal
|
| 7481 |
|
|
|
| 7482 |
|
|
MD1_c_0_a[17] = VD1_un24_res & !VD1_hilo_49 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_17;
|
| 7483 |
|
|
|
| 7484 |
|
|
|
| 7485 |
|
|
--TD1_m41 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m41
|
| 7486 |
|
|
--operation mode is normal
|
| 7487 |
|
|
|
| 7488 |
|
|
TD1_m41 = PD1_a_o_17 & TD1_m41_a # !PD1_a_o_17 & TD1_m41_a & !TD1_m4 # !TD1_m41_a & TD1_m7;
|
| 7489 |
|
|
|
| 7490 |
|
|
|
| 7491 |
|
|
--TD1_m38 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m38
|
| 7492 |
|
|
--operation mode is normal
|
| 7493 |
|
|
|
| 7494 |
|
|
TD1_m38 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add17;
|
| 7495 |
|
|
|
| 7496 |
|
|
|
| 7497 |
|
|
--UD1_shift_out_87[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[14]
|
| 7498 |
|
|
--operation mode is normal
|
| 7499 |
|
|
|
| 7500 |
|
|
UD1_shift_out_87[14] = PD1_a_o_2 & UD1_shift_out_87_d[14] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[14] # !PD1_a_o_0 & VD1_b_o_iv_16;
|
| 7501 |
|
|
|
| 7502 |
|
|
|
| 7503 |
|
|
--UD1_shift_out_89_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[14]
|
| 7504 |
|
|
--operation mode is normal
|
| 7505 |
|
|
|
| 7506 |
|
|
UD1_shift_out_89_a[14] = PD1_a_o_2 & !UD1_shift_out_85_d[14] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[14] # !PD1_a_o_1 & !VD1_b_o_iv_13;
|
| 7507 |
|
|
|
| 7508 |
|
|
|
| 7509 |
|
|
--UD1_shift_out_86_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_14
|
| 7510 |
|
|
--operation mode is normal
|
| 7511 |
|
|
|
| 7512 |
|
|
UD1_shift_out_86_14 = UD1_shift_out_sn_b9_0 & UD1_shift_out_83[14] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[14];
|
| 7513 |
|
|
|
| 7514 |
|
|
|
| 7515 |
|
|
--UD1_shift_out_92_d_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_6
|
| 7516 |
|
|
--operation mode is normal
|
| 7517 |
|
|
|
| 7518 |
|
|
UD1_shift_out_92_d_6 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[14] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_63[22];
|
| 7519 |
|
|
|
| 7520 |
|
|
|
| 7521 |
|
|
--MD1_c_0_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[14]
|
| 7522 |
|
|
--operation mode is normal
|
| 7523 |
|
|
|
| 7524 |
|
|
MD1_c_0_a[14] = VD1_un24_res & !VD1_hilo_46 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_14;
|
| 7525 |
|
|
|
| 7526 |
|
|
|
| 7527 |
|
|
--TD1_m26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m26
|
| 7528 |
|
|
--operation mode is normal
|
| 7529 |
|
|
|
| 7530 |
|
|
TD1_m26 = PD1_a_o_14 & TD1_m26_a # !PD1_a_o_14 & TD1_m26_a & !TD1_m4 # !TD1_m26_a & TD1_m7;
|
| 7531 |
|
|
|
| 7532 |
|
|
|
| 7533 |
|
|
--TD1_m23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m23
|
| 7534 |
|
|
--operation mode is normal
|
| 7535 |
|
|
|
| 7536 |
|
|
TD1_m23 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add14;
|
| 7537 |
|
|
|
| 7538 |
|
|
|
| 7539 |
|
|
--UD1_shift_out_87[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[15]
|
| 7540 |
|
|
--operation mode is normal
|
| 7541 |
|
|
|
| 7542 |
|
|
UD1_shift_out_87[15] = PD1_a_o_2 & UD1_shift_out_87_d[15] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[15] # !PD1_a_o_0 & VD1_b_o_iv_17;
|
| 7543 |
|
|
|
| 7544 |
|
|
|
| 7545 |
|
|
--UD1_shift_out_89_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[15]
|
| 7546 |
|
|
--operation mode is normal
|
| 7547 |
|
|
|
| 7548 |
|
|
UD1_shift_out_89_a[15] = PD1_a_o_2 & !UD1_shift_out_85_d[15] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[15] # !PD1_a_o_1 & !VD1_b_o_iv_14;
|
| 7549 |
|
|
|
| 7550 |
|
|
|
| 7551 |
|
|
--UD1_shift_out_86_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_15
|
| 7552 |
|
|
--operation mode is normal
|
| 7553 |
|
|
|
| 7554 |
|
|
UD1_shift_out_86_15 = UD1_shift_out_sn_b9_0 & UD1_shift_out_83[15] # !UD1_shift_out_sn_b9_0 & VD1_b_o_iv_31;
|
| 7555 |
|
|
|
| 7556 |
|
|
|
| 7557 |
|
|
--UD1_shift_out_92_d_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_7
|
| 7558 |
|
|
--operation mode is normal
|
| 7559 |
|
|
|
| 7560 |
|
|
UD1_shift_out_92_d_7 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[15] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_63[23];
|
| 7561 |
|
|
|
| 7562 |
|
|
|
| 7563 |
|
|
--MD1_c_0_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[15]
|
| 7564 |
|
|
--operation mode is normal
|
| 7565 |
|
|
|
| 7566 |
|
|
MD1_c_0_a[15] = VD1_un24_res & !VD1_hilo_47 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_15;
|
| 7567 |
|
|
|
| 7568 |
|
|
|
| 7569 |
|
|
--TD1_m31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m31
|
| 7570 |
|
|
--operation mode is normal
|
| 7571 |
|
|
|
| 7572 |
|
|
TD1_m31 = PD1_a_o_15 & TD1_m31_a # !PD1_a_o_15 & TD1_m31_a & !TD1_m4 # !TD1_m31_a & TD1_m7;
|
| 7573 |
|
|
|
| 7574 |
|
|
|
| 7575 |
|
|
--TD1_m28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m28
|
| 7576 |
|
|
--operation mode is normal
|
| 7577 |
|
|
|
| 7578 |
|
|
TD1_m28 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add15;
|
| 7579 |
|
|
|
| 7580 |
|
|
|
| 7581 |
|
|
--UD1_shift_out_36_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_36_0
|
| 7582 |
|
|
--operation mode is normal
|
| 7583 |
|
|
|
| 7584 |
|
|
UD1_shift_out_36_0 = UD1_shift_out588 & VD1_b_o_iv_31;
|
| 7585 |
|
|
|
| 7586 |
|
|
|
| 7587 |
|
|
--UD1_shift_out_85_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_27
|
| 7588 |
|
|
--operation mode is normal
|
| 7589 |
|
|
|
| 7590 |
|
|
UD1_shift_out_85_27 = PD1_a_o_2 & UD1_shift_out_85_c[31] & UD1_shift_out_68[27] # !UD1_shift_out_85_c[31] & UD1_shift_out_68[29] # !PD1_a_o_2 & UD1_shift_out_85_c[31];
|
| 7591 |
|
|
|
| 7592 |
|
|
|
| 7593 |
|
|
--UD1_shift_out_83[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[31]
|
| 7594 |
|
|
--operation mode is normal
|
| 7595 |
|
|
|
| 7596 |
|
|
UD1_shift_out_83[31] = !UD1_shift_out587 & VD1_b_o_iv_31;
|
| 7597 |
|
|
|
| 7598 |
|
|
|
| 7599 |
|
|
--UD1_shift_out_92_d[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[31]
|
| 7600 |
|
|
--operation mode is normal
|
| 7601 |
|
|
|
| 7602 |
|
|
UD1_shift_out_92_d[31] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[31] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[31];
|
| 7603 |
|
|
|
| 7604 |
|
|
|
| 7605 |
|
|
--MD1_c_0_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[31]
|
| 7606 |
|
|
--operation mode is normal
|
| 7607 |
|
|
|
| 7608 |
|
|
MD1_c_0_a[31] = VD1_un24_res & !VD1_hilo_63 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_31;
|
| 7609 |
|
|
|
| 7610 |
|
|
|
| 7611 |
|
|
--TD1_m101 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m101
|
| 7612 |
|
|
--operation mode is normal
|
| 7613 |
|
|
|
| 7614 |
|
|
TD1_m101 = VD1_b_o_iv_31 & TD1_m101_a & TD1_m7 # !TD1_m101_a & !TD1_m9 # !VD1_b_o_iv_31 & TD1_m101_a;
|
| 7615 |
|
|
|
| 7616 |
|
|
|
| 7617 |
|
|
--TD1_m98 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m98
|
| 7618 |
|
|
--operation mode is normal
|
| 7619 |
|
|
|
| 7620 |
|
|
TD1_m98 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add31;
|
| 7621 |
|
|
|
| 7622 |
|
|
|
| 7623 |
|
|
--UD1_shift_out_89_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_7
|
| 7624 |
|
|
--operation mode is normal
|
| 7625 |
|
|
|
| 7626 |
|
|
UD1_shift_out_89_7 = UD1_shift_out586 & !UD1_shift_out_89_a[8] # !UD1_shift_out586 & UD1_shift_out_87[8];
|
| 7627 |
|
|
|
| 7628 |
|
|
|
| 7629 |
|
|
--MD1_c_a_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_8
|
| 7630 |
|
|
--operation mode is normal
|
| 7631 |
|
|
|
| 7632 |
|
|
MD1_c_a_8 = UD1_shift_out586 & !UD1_shift_out_92_d_0 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_0 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_8;
|
| 7633 |
|
|
|
| 7634 |
|
|
|
| 7635 |
|
|
--MD1_c_0_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_7
|
| 7636 |
|
|
--operation mode is normal
|
| 7637 |
|
|
|
| 7638 |
|
|
MD1_c_0_7 = RC1_alu_func_o_4 & !TD1_m16 # !RC1_alu_func_o_4 & TD1_m13 # !MD1_c_0_a[8];
|
| 7639 |
|
|
|
| 7640 |
|
|
|
| 7641 |
|
|
--UD1_shift_out_89_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_8
|
| 7642 |
|
|
--operation mode is normal
|
| 7643 |
|
|
|
| 7644 |
|
|
UD1_shift_out_89_8 = UD1_shift_out586 & !UD1_shift_out_89_a[9] # !UD1_shift_out586 & UD1_shift_out_87[9];
|
| 7645 |
|
|
|
| 7646 |
|
|
|
| 7647 |
|
|
--MD1_c_a_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_9
|
| 7648 |
|
|
--operation mode is normal
|
| 7649 |
|
|
|
| 7650 |
|
|
MD1_c_a_9 = UD1_shift_out586 & !UD1_shift_out_92_d_1 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_1 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_9;
|
| 7651 |
|
|
|
| 7652 |
|
|
|
| 7653 |
|
|
--MD1_c_0_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_8
|
| 7654 |
|
|
--operation mode is normal
|
| 7655 |
|
|
|
| 7656 |
|
|
MD1_c_0_8 = RC1_alu_func_o_4 & !TD1_m117 # !RC1_alu_func_o_4 & TD1_m114 # !MD1_c_0_a[9];
|
| 7657 |
|
|
|
| 7658 |
|
|
|
| 7659 |
|
|
--MD1_c_1_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_10
|
| 7660 |
|
|
--operation mode is normal
|
| 7661 |
|
|
|
| 7662 |
|
|
MD1_c_1_10 = TD1_alu_out_0_a2_4 # TD1_alu_out_0_a3_0_0 & VD1_b_o_iv_10 # !MD1_c_1_a[10];
|
| 7663 |
|
|
|
| 7664 |
|
|
|
| 7665 |
|
|
--TD1_un1_a_add10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add10
|
| 7666 |
|
|
--operation mode is arithmetic
|
| 7667 |
|
|
|
| 7668 |
|
|
TD1_un1_a_add10_carry_eqn = TD1_un1_a_carry_9;
|
| 7669 |
|
|
TD1_un1_a_add10 = PD1_a_o_10 $ TD1_un1_b_1_combout[10] $ !TD1_un1_a_add10_carry_eqn;
|
| 7670 |
|
|
|
| 7671 |
|
|
--TD1_un1_a_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_10
|
| 7672 |
|
|
--operation mode is arithmetic
|
| 7673 |
|
|
|
| 7674 |
|
|
TD1_un1_a_carry_10 = CARRY(PD1_a_o_10 & TD1_un1_b_1_combout[10] # !TD1_un1_a_carry_9 # !PD1_a_o_10 & TD1_un1_b_1_combout[10] & !TD1_un1_a_carry_9);
|
| 7675 |
|
|
|
| 7676 |
|
|
|
| 7677 |
|
|
--UD1_shift_out_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_10
|
| 7678 |
|
|
--operation mode is normal
|
| 7679 |
|
|
|
| 7680 |
|
|
UD1_shift_out_10 = UD1_shift_out_sn_m31_i & UD1_shift_out_92[10] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[10];
|
| 7681 |
|
|
|
| 7682 |
|
|
|
| 7683 |
|
|
--UD1_shift_out_89_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_10
|
| 7684 |
|
|
--operation mode is normal
|
| 7685 |
|
|
|
| 7686 |
|
|
UD1_shift_out_89_10 = UD1_shift_out586 & !UD1_shift_out_89_a[11] # !UD1_shift_out586 & UD1_shift_out_87[11];
|
| 7687 |
|
|
|
| 7688 |
|
|
|
| 7689 |
|
|
--MD1_c_a_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_11
|
| 7690 |
|
|
--operation mode is normal
|
| 7691 |
|
|
|
| 7692 |
|
|
MD1_c_a_11 = UD1_shift_out586 & !UD1_shift_out_92_d_3 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_3 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_11;
|
| 7693 |
|
|
|
| 7694 |
|
|
|
| 7695 |
|
|
--MD1_c_0_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_10
|
| 7696 |
|
|
--operation mode is normal
|
| 7697 |
|
|
|
| 7698 |
|
|
MD1_c_0_10 = RC1_alu_func_o_4 & !TD1_m21 # !RC1_alu_func_o_4 & TD1_m18 # !MD1_c_0_a[11];
|
| 7699 |
|
|
|
| 7700 |
|
|
|
| 7701 |
|
|
--UD1_shift_out_87[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[21]
|
| 7702 |
|
|
--operation mode is normal
|
| 7703 |
|
|
|
| 7704 |
|
|
UD1_shift_out_87[21] = PD1_a_o_2 & UD1_shift_out_87_d[21] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[21] # !PD1_a_o_0 & VD1_b_o_iv_23;
|
| 7705 |
|
|
|
| 7706 |
|
|
|
| 7707 |
|
|
--UD1_shift_out_89_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[21]
|
| 7708 |
|
|
--operation mode is normal
|
| 7709 |
|
|
|
| 7710 |
|
|
UD1_shift_out_89_a[21] = PD1_a_o_2 & !UD1_shift_out_85_d[21] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[21] # !PD1_a_o_1 & !VD1_b_o_iv_20;
|
| 7711 |
|
|
|
| 7712 |
|
|
|
| 7713 |
|
|
--UD1_shift_out_92_d_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_13
|
| 7714 |
|
|
--operation mode is normal
|
| 7715 |
|
|
|
| 7716 |
|
|
UD1_shift_out_92_d_13 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[21] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[21];
|
| 7717 |
|
|
|
| 7718 |
|
|
|
| 7719 |
|
|
--UD1_shift_out_92_s_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_s_0
|
| 7720 |
|
|
--operation mode is normal
|
| 7721 |
|
|
|
| 7722 |
|
|
UD1_shift_out_92_s_0 = !UD1_shift_out586 & !UD1_shift_out_sn_m25_0;
|
| 7723 |
|
|
|
| 7724 |
|
|
|
| 7725 |
|
|
--MD1_c_0_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[21]
|
| 7726 |
|
|
--operation mode is normal
|
| 7727 |
|
|
|
| 7728 |
|
|
MD1_c_0_a[21] = VD1_un24_res & !VD1_hilo_53 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_21;
|
| 7729 |
|
|
|
| 7730 |
|
|
|
| 7731 |
|
|
--TD1_m132 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m132
|
| 7732 |
|
|
--operation mode is normal
|
| 7733 |
|
|
|
| 7734 |
|
|
TD1_m132 = PD1_a_o_21 & TD1_m132_a # !PD1_a_o_21 & TD1_m132_a & !TD1_m4 # !TD1_m132_a & TD1_m7;
|
| 7735 |
|
|
|
| 7736 |
|
|
|
| 7737 |
|
|
--TD1_m129 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m129
|
| 7738 |
|
|
--operation mode is normal
|
| 7739 |
|
|
|
| 7740 |
|
|
TD1_m129 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add21;
|
| 7741 |
|
|
|
| 7742 |
|
|
|
| 7743 |
|
|
--UD1_shift_out_87[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[20]
|
| 7744 |
|
|
--operation mode is normal
|
| 7745 |
|
|
|
| 7746 |
|
|
UD1_shift_out_87[20] = PD1_a_o_2 & UD1_shift_out_87_d[20] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[20] # !PD1_a_o_0 & VD1_b_o_iv_22;
|
| 7747 |
|
|
|
| 7748 |
|
|
|
| 7749 |
|
|
--UD1_shift_out_89_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[20]
|
| 7750 |
|
|
--operation mode is normal
|
| 7751 |
|
|
|
| 7752 |
|
|
UD1_shift_out_89_a[20] = PD1_a_o_2 & !UD1_shift_out_85_d[20] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[20] # !PD1_a_o_1 & !VD1_b_o_iv_19;
|
| 7753 |
|
|
|
| 7754 |
|
|
|
| 7755 |
|
|
--MD1_c_1_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_a[20]
|
| 7756 |
|
|
--operation mode is normal
|
| 7757 |
|
|
|
| 7758 |
|
|
MD1_c_1_a[20] = VD1_hilo_20 & !VD1_un11_res & !VD1_un24_res # !VD1_hilo_52 # !VD1_hilo_20 & !VD1_un24_res # !VD1_hilo_52;
|
| 7759 |
|
|
|
| 7760 |
|
|
|
| 7761 |
|
|
--TD1_m56 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m56
|
| 7762 |
|
|
--operation mode is normal
|
| 7763 |
|
|
|
| 7764 |
|
|
TD1_m56 = PD1_a_o_20 & TD1_m56_a # !PD1_a_o_20 & TD1_m56_a & !TD1_m4 # !TD1_m56_a & TD1_m7;
|
| 7765 |
|
|
|
| 7766 |
|
|
|
| 7767 |
|
|
--TD1_m53 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m53
|
| 7768 |
|
|
--operation mode is normal
|
| 7769 |
|
|
|
| 7770 |
|
|
TD1_m53 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add20;
|
| 7771 |
|
|
|
| 7772 |
|
|
|
| 7773 |
|
|
--UD1_shift_out_92_d_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_12
|
| 7774 |
|
|
--operation mode is normal
|
| 7775 |
|
|
|
| 7776 |
|
|
UD1_shift_out_92_d_12 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[20] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[20];
|
| 7777 |
|
|
|
| 7778 |
|
|
|
| 7779 |
|
|
--UD1_shift_out_89_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_18
|
| 7780 |
|
|
--operation mode is normal
|
| 7781 |
|
|
|
| 7782 |
|
|
UD1_shift_out_89_18 = UD1_shift_out586 & !UD1_shift_out_89_a[19] # !UD1_shift_out586 & UD1_shift_out_87[19];
|
| 7783 |
|
|
|
| 7784 |
|
|
|
| 7785 |
|
|
--MD1_c_0_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_18
|
| 7786 |
|
|
--operation mode is normal
|
| 7787 |
|
|
|
| 7788 |
|
|
MD1_c_0_18 = RC1_alu_func_o_4 & !TD1_m51 # !RC1_alu_func_o_4 & TD1_m48 # !MD1_c_0_a[19];
|
| 7789 |
|
|
|
| 7790 |
|
|
|
| 7791 |
|
|
--UD1_shift_out_92_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_13
|
| 7792 |
|
|
--operation mode is normal
|
| 7793 |
|
|
|
| 7794 |
|
|
UD1_shift_out_92_13 = UD1_shift_out_92_s_0 & VD1_b_o_iv_31 & UD1_shift_out_92_a[19] # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d[19];
|
| 7795 |
|
|
|
| 7796 |
|
|
|
| 7797 |
|
|
--UD1_shift_out_89_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_17
|
| 7798 |
|
|
--operation mode is normal
|
| 7799 |
|
|
|
| 7800 |
|
|
UD1_shift_out_89_17 = UD1_shift_out586 & !UD1_shift_out_89_a[18] # !UD1_shift_out586 & UD1_shift_out_87[18];
|
| 7801 |
|
|
|
| 7802 |
|
|
|
| 7803 |
|
|
--UD1_shift_out_92_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_12
|
| 7804 |
|
|
--operation mode is normal
|
| 7805 |
|
|
|
| 7806 |
|
|
UD1_shift_out_92_12 = UD1_shift_out586 & UD1_shift_out_92_d[18] # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d[18] # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_a[18];
|
| 7807 |
|
|
|
| 7808 |
|
|
|
| 7809 |
|
|
--MD1_c_0_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_17
|
| 7810 |
|
|
--operation mode is normal
|
| 7811 |
|
|
|
| 7812 |
|
|
MD1_c_0_17 = RC1_alu_func_o_4 & !TD1_m46 # !RC1_alu_func_o_4 & TD1_m43 # !MD1_c_0_a[18];
|
| 7813 |
|
|
|
| 7814 |
|
|
|
| 7815 |
|
|
--UD1_shift_out_89_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_25
|
| 7816 |
|
|
--operation mode is normal
|
| 7817 |
|
|
|
| 7818 |
|
|
UD1_shift_out_89_25 = UD1_shift_out586 & UD1_shift_out_85[26] # !UD1_shift_out586 & !UD1_shift_out_89_a[26];
|
| 7819 |
|
|
|
| 7820 |
|
|
|
| 7821 |
|
|
--MD1_c_a_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_26
|
| 7822 |
|
|
--operation mode is normal
|
| 7823 |
|
|
|
| 7824 |
|
|
MD1_c_a_26 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_18;
|
| 7825 |
|
|
|
| 7826 |
|
|
|
| 7827 |
|
|
--MD1_c_0_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_25
|
| 7828 |
|
|
--operation mode is normal
|
| 7829 |
|
|
|
| 7830 |
|
|
MD1_c_0_25 = RC1_alu_func_o_4 & !TD1_m81 # !RC1_alu_func_o_4 & TD1_m78 # !MD1_c_0_a[26];
|
| 7831 |
|
|
|
| 7832 |
|
|
|
| 7833 |
|
|
--UD1_shift_out_89_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_26
|
| 7834 |
|
|
--operation mode is normal
|
| 7835 |
|
|
|
| 7836 |
|
|
UD1_shift_out_89_26 = UD1_shift_out586 & UD1_shift_out_85[27] # !UD1_shift_out586 & !UD1_shift_out_89_a[27];
|
| 7837 |
|
|
|
| 7838 |
|
|
|
| 7839 |
|
|
--MD1_c_a_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_27
|
| 7840 |
|
|
--operation mode is normal
|
| 7841 |
|
|
|
| 7842 |
|
|
MD1_c_a_27 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_19;
|
| 7843 |
|
|
|
| 7844 |
|
|
|
| 7845 |
|
|
--MD1_c_0_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_26
|
| 7846 |
|
|
--operation mode is normal
|
| 7847 |
|
|
|
| 7848 |
|
|
MD1_c_0_26 = RC1_alu_func_o_4 & !TD1_m86 # !RC1_alu_func_o_4 & TD1_m83 # !MD1_c_0_a[27];
|
| 7849 |
|
|
|
| 7850 |
|
|
|
| 7851 |
|
|
--UD1_shift_out_89_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_27
|
| 7852 |
|
|
--operation mode is normal
|
| 7853 |
|
|
|
| 7854 |
|
|
UD1_shift_out_89_27 = UD1_shift_out586 & UD1_shift_out_85[28] # !UD1_shift_out586 & UD1_shift_out_87[28];
|
| 7855 |
|
|
|
| 7856 |
|
|
|
| 7857 |
|
|
--MD1_c_4_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_4_0
|
| 7858 |
|
|
--operation mode is normal
|
| 7859 |
|
|
|
| 7860 |
|
|
MD1_c_4_0 = TD1_alu_out_0_a2_22 # MD1_c_2[28] # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add28;
|
| 7861 |
|
|
|
| 7862 |
|
|
|
| 7863 |
|
|
--MD1_c_a_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_28
|
| 7864 |
|
|
--operation mode is normal
|
| 7865 |
|
|
|
| 7866 |
|
|
MD1_c_a_28 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_20;
|
| 7867 |
|
|
|
| 7868 |
|
|
|
| 7869 |
|
|
--UD1_shift_out_89_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_28
|
| 7870 |
|
|
--operation mode is normal
|
| 7871 |
|
|
|
| 7872 |
|
|
UD1_shift_out_89_28 = UD1_shift_out586 & UD1_shift_out_85[29] # !UD1_shift_out586 & UD1_shift_out_87[29];
|
| 7873 |
|
|
|
| 7874 |
|
|
|
| 7875 |
|
|
--MD1_c_a_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_29
|
| 7876 |
|
|
--operation mode is normal
|
| 7877 |
|
|
|
| 7878 |
|
|
MD1_c_a_29 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_21;
|
| 7879 |
|
|
|
| 7880 |
|
|
|
| 7881 |
|
|
--MD1_c_0_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_28
|
| 7882 |
|
|
--operation mode is normal
|
| 7883 |
|
|
|
| 7884 |
|
|
MD1_c_0_28 = RC1_alu_func_o_4 & !TD1_m91 # !RC1_alu_func_o_4 & TD1_m88 # !MD1_c_0_a[29];
|
| 7885 |
|
|
|
| 7886 |
|
|
|
| 7887 |
|
|
--UD1_shift_out_87[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[13]
|
| 7888 |
|
|
--operation mode is normal
|
| 7889 |
|
|
|
| 7890 |
|
|
UD1_shift_out_87[13] = PD1_a_o_2 & UD1_shift_out_87_d[13] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[13] # !PD1_a_o_0 & VD1_b_o_iv_15;
|
| 7891 |
|
|
|
| 7892 |
|
|
|
| 7893 |
|
|
--UD1_shift_out_89_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[13]
|
| 7894 |
|
|
--operation mode is normal
|
| 7895 |
|
|
|
| 7896 |
|
|
UD1_shift_out_89_a[13] = PD1_a_o_2 & !UD1_shift_out_85_d[13] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[13] # !PD1_a_o_1 & !VD1_b_o_iv_12;
|
| 7897 |
|
|
|
| 7898 |
|
|
|
| 7899 |
|
|
--UD1_shift_out_86_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_13
|
| 7900 |
|
|
--operation mode is normal
|
| 7901 |
|
|
|
| 7902 |
|
|
UD1_shift_out_86_13 = UD1_shift_out_sn_b9_0 & UD1_shift_out_86_a[13] & UD1_shift_out_42[1] # !UD1_shift_out_86_a[13] & UD1_shift_out_79[17] # !UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[13];
|
| 7903 |
|
|
|
| 7904 |
|
|
|
| 7905 |
|
|
--UD1_shift_out_92_d_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_5
|
| 7906 |
|
|
--operation mode is normal
|
| 7907 |
|
|
|
| 7908 |
|
|
UD1_shift_out_92_d_5 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[13] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_63[21];
|
| 7909 |
|
|
|
| 7910 |
|
|
|
| 7911 |
|
|
--MD1_c_0_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[13]
|
| 7912 |
|
|
--operation mode is normal
|
| 7913 |
|
|
|
| 7914 |
|
|
MD1_c_0_a[13] = VD1_un24_res & !VD1_hilo_45 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_13;
|
| 7915 |
|
|
|
| 7916 |
|
|
|
| 7917 |
|
|
--TD1_m127 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m127
|
| 7918 |
|
|
--operation mode is normal
|
| 7919 |
|
|
|
| 7920 |
|
|
TD1_m127 = PD1_a_o_13 & TD1_m127_a # !PD1_a_o_13 & TD1_m127_a & !TD1_m4 # !TD1_m127_a & TD1_m7;
|
| 7921 |
|
|
|
| 7922 |
|
|
|
| 7923 |
|
|
--TD1_m124 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m124
|
| 7924 |
|
|
--operation mode is normal
|
| 7925 |
|
|
|
| 7926 |
|
|
TD1_m124 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add13;
|
| 7927 |
|
|
|
| 7928 |
|
|
|
| 7929 |
|
|
--VD1_hilo_37_iv_0_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[30]
|
| 7930 |
|
|
--operation mode is normal
|
| 7931 |
|
|
|
| 7932 |
|
|
VD1_hilo_37_iv_0_a[30] = VD1_hilo_31 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_29 # !VD1_hilo_31 & !VD1_hilo_2_sqmuxa # !VD1_hilo_29;
|
| 7933 |
|
|
|
| 7934 |
|
|
|
| 7935 |
|
|
--VD1_hilo_37_iv_0_0[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[30]
|
| 7936 |
|
|
--operation mode is normal
|
| 7937 |
|
|
|
| 7938 |
|
|
VD1_hilo_37_iv_0_0[30] = VD1_hilo_30 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[30] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_30 & VD1_un134_hilo_combout[30] & VD1_hilo_37_iv_0_a3_0[0];
|
| 7939 |
|
|
|
| 7940 |
|
|
|
| 7941 |
|
|
--PD1_a_o_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_30
|
| 7942 |
|
|
--operation mode is normal
|
| 7943 |
|
|
|
| 7944 |
|
|
PD1_a_o_30 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[30] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[30];
|
| 7945 |
|
|
|
| 7946 |
|
|
|
| 7947 |
|
|
--VD1_hilo_62 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_62
|
| 7948 |
|
|
--operation mode is normal
|
| 7949 |
|
|
|
| 7950 |
|
|
VD1_hilo_62_lut_out = VD1_hilo_37_iv_0_a[62] & !VD1_hilo_37_iv_0_o5_0[62] & VD1_hilo_62 # !VD1_hilo_37_iv_0_a3_4[62];
|
| 7951 |
|
|
VD1_hilo_62 = DFFEAS(VD1_hilo_62_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 7952 |
|
|
|
| 7953 |
|
|
|
| 7954 |
|
|
--UD1_shift_out_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_30
|
| 7955 |
|
|
--operation mode is normal
|
| 7956 |
|
|
|
| 7957 |
|
|
UD1_shift_out_30 = UD1_shift_out_sn_m31_i & UD1_shift_out_a[30] & UD1_shift_out_83[31] # !UD1_shift_out_a[30] & UD1_shift_out_92_d[30] # !UD1_shift_out_sn_m31_i & !UD1_shift_out_a[30];
|
| 7958 |
|
|
|
| 7959 |
|
|
|
| 7960 |
|
|
--TD1_m96 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m96
|
| 7961 |
|
|
--operation mode is normal
|
| 7962 |
|
|
|
| 7963 |
|
|
TD1_m96 = PD1_a_o_30 & TD1_m96_a # !PD1_a_o_30 & TD1_m96_a & !TD1_m4 # !TD1_m96_a & TD1_m7;
|
| 7964 |
|
|
|
| 7965 |
|
|
|
| 7966 |
|
|
--TD1_un1_a_add30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add30
|
| 7967 |
|
|
--operation mode is arithmetic
|
| 7968 |
|
|
|
| 7969 |
|
|
TD1_un1_a_add30_carry_eqn = TD1_un1_a_carry_29;
|
| 7970 |
|
|
TD1_un1_a_add30 = PD1_a_o_30 $ TD1_un1_b_1_combout[30] $ !TD1_un1_a_add30_carry_eqn;
|
| 7971 |
|
|
|
| 7972 |
|
|
--TD1_un1_a_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_30
|
| 7973 |
|
|
--operation mode is arithmetic
|
| 7974 |
|
|
|
| 7975 |
|
|
TD1_un1_a_carry_30 = CARRY(PD1_a_o_30 & TD1_un1_b_1_combout[30] # !TD1_un1_a_carry_29 # !PD1_a_o_30 & TD1_un1_b_1_combout[30] & !TD1_un1_a_carry_29);
|
| 7976 |
|
|
|
| 7977 |
|
|
|
| 7978 |
|
|
--UD1_shift_out_89_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_11
|
| 7979 |
|
|
--operation mode is normal
|
| 7980 |
|
|
|
| 7981 |
|
|
UD1_shift_out_89_11 = UD1_shift_out586 & !UD1_shift_out_89_a[12] # !UD1_shift_out586 & UD1_shift_out_87[12];
|
| 7982 |
|
|
|
| 7983 |
|
|
|
| 7984 |
|
|
--MD1_c_a_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_12
|
| 7985 |
|
|
--operation mode is normal
|
| 7986 |
|
|
|
| 7987 |
|
|
MD1_c_a_12 = UD1_shift_out586 & !UD1_shift_out_92_d_4 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_4 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_12;
|
| 7988 |
|
|
|
| 7989 |
|
|
|
| 7990 |
|
|
--MD1_c_0_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_11
|
| 7991 |
|
|
--operation mode is normal
|
| 7992 |
|
|
|
| 7993 |
|
|
MD1_c_0_11 = RC1_alu_func_o_4 & !TD1_m122 # !RC1_alu_func_o_4 & TD1_m119 # !MD1_c_0_a[12];
|
| 7994 |
|
|
|
| 7995 |
|
|
|
| 7996 |
|
|
--CC1_dmem_ctl_o_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3|dmem_ctl_o_3
|
| 7997 |
|
|
--operation mode is normal
|
| 7998 |
|
|
|
| 7999 |
|
|
CC1_dmem_ctl_o_3_lut_out = WB94L1;
|
| 8000 |
|
|
CC1_dmem_ctl_o_3 = DFFEAS(CC1_dmem_ctl_o_3_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 8001 |
|
|
|
| 8002 |
|
|
|
| 8003 |
|
|
--UD1_shift_out_89_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_23
|
| 8004 |
|
|
--operation mode is normal
|
| 8005 |
|
|
|
| 8006 |
|
|
UD1_shift_out_89_23 = UD1_shift_out586 & UD1_shift_out_85[24] # !UD1_shift_out586 & !UD1_shift_out_89_a[24];
|
| 8007 |
|
|
|
| 8008 |
|
|
|
| 8009 |
|
|
--MD1_c_a_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_24
|
| 8010 |
|
|
--operation mode is normal
|
| 8011 |
|
|
|
| 8012 |
|
|
MD1_c_a_24 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_16;
|
| 8013 |
|
|
|
| 8014 |
|
|
|
| 8015 |
|
|
--MD1_c_0_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_23
|
| 8016 |
|
|
--operation mode is normal
|
| 8017 |
|
|
|
| 8018 |
|
|
MD1_c_0_23 = RC1_alu_func_o_4 & !TD1_m71 # !RC1_alu_func_o_4 & TD1_m68 # !MD1_c_0_a[24];
|
| 8019 |
|
|
|
| 8020 |
|
|
|
| 8021 |
|
|
--UD1_shift_out_89_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_24
|
| 8022 |
|
|
--operation mode is normal
|
| 8023 |
|
|
|
| 8024 |
|
|
UD1_shift_out_89_24 = UD1_shift_out586 & UD1_shift_out_85[25] # !UD1_shift_out586 & !UD1_shift_out_89_a[25];
|
| 8025 |
|
|
|
| 8026 |
|
|
|
| 8027 |
|
|
--MD1_c_a_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_25
|
| 8028 |
|
|
--operation mode is normal
|
| 8029 |
|
|
|
| 8030 |
|
|
MD1_c_a_25 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_17;
|
| 8031 |
|
|
|
| 8032 |
|
|
|
| 8033 |
|
|
--MD1_c_0_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_24
|
| 8034 |
|
|
--operation mode is normal
|
| 8035 |
|
|
|
| 8036 |
|
|
MD1_c_0_24 = RC1_alu_func_o_4 & !TD1_m76 # !RC1_alu_func_o_4 & TD1_m73 # !MD1_c_0_a[25];
|
| 8037 |
|
|
|
| 8038 |
|
|
|
| 8039 |
|
|
--UD1_shift_out_89_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_21
|
| 8040 |
|
|
--operation mode is normal
|
| 8041 |
|
|
|
| 8042 |
|
|
UD1_shift_out_89_21 = UD1_shift_out586 & UD1_shift_out_85[22] # !UD1_shift_out586 & UD1_shift_out_87[22];
|
| 8043 |
|
|
|
| 8044 |
|
|
|
| 8045 |
|
|
--MD1_c_a_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_22
|
| 8046 |
|
|
--operation mode is normal
|
| 8047 |
|
|
|
| 8048 |
|
|
MD1_c_a_22 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_14;
|
| 8049 |
|
|
|
| 8050 |
|
|
|
| 8051 |
|
|
--MD1_c_0_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_21
|
| 8052 |
|
|
--operation mode is normal
|
| 8053 |
|
|
|
| 8054 |
|
|
MD1_c_0_21 = RC1_alu_func_o_4 & !TD1_m61 # !RC1_alu_func_o_4 & TD1_m58 # !MD1_c_0_a[22];
|
| 8055 |
|
|
|
| 8056 |
|
|
|
| 8057 |
|
|
--UD1_shift_out_89_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_22
|
| 8058 |
|
|
--operation mode is normal
|
| 8059 |
|
|
|
| 8060 |
|
|
UD1_shift_out_89_22 = UD1_shift_out586 & UD1_shift_out_85[23] # !UD1_shift_out586 & !UD1_shift_out_89_a[23];
|
| 8061 |
|
|
|
| 8062 |
|
|
|
| 8063 |
|
|
--MD1_c_a_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_23
|
| 8064 |
|
|
--operation mode is normal
|
| 8065 |
|
|
|
| 8066 |
|
|
MD1_c_a_23 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_15;
|
| 8067 |
|
|
|
| 8068 |
|
|
|
| 8069 |
|
|
--MD1_c_0_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_22
|
| 8070 |
|
|
--operation mode is normal
|
| 8071 |
|
|
|
| 8072 |
|
|
MD1_c_0_22 = RC1_alu_func_o_4 & !TD1_m66 # !RC1_alu_func_o_4 & TD1_m63 # !MD1_c_0_a[23];
|
| 8073 |
|
|
|
| 8074 |
|
|
|
| 8075 |
|
|
--TB1_dout_1_6 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_6
|
| 8076 |
|
|
--operation mode is normal
|
| 8077 |
|
|
|
| 8078 |
|
|
TB1_dout_1_6 = TB1_dout21 & CB1_dout_2_6 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_6 # !TB1_dout22 & CB1_dout_2_22;
|
| 8079 |
|
|
|
| 8080 |
|
|
|
| 8081 |
|
|
--GE1_q_a[6] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[6]
|
| 8082 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8083 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8084 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8085 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8086 |
|
|
GE1_q_a[6]_PORT_A_data_in = ~GND;
|
| 8087 |
|
|
GE1_q_a[6]_PORT_A_data_in_reg = DFFE(GE1_q_a[6]_PORT_A_data_in, GE1_q_a[6]_clock_0, , , );
|
| 8088 |
|
|
GE1_q_a[6]_PORT_B_data_in = CB1_dout_2_6;
|
| 8089 |
|
|
GE1_q_a[6]_PORT_B_data_in_reg = DFFE(GE1_q_a[6]_PORT_B_data_in, GE1_q_a[6]_clock_0, , , );
|
| 8090 |
|
|
GE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8091 |
|
|
GE1_q_a[6]_PORT_A_address_reg = DFFE(GE1_q_a[6]_PORT_A_address, GE1_q_a[6]_clock_0, , , );
|
| 8092 |
|
|
GE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8093 |
|
|
GE1_q_a[6]_PORT_B_address_reg = DFFE(GE1_q_a[6]_PORT_B_address, GE1_q_a[6]_clock_0, , , );
|
| 8094 |
|
|
GE1_q_a[6]_PORT_A_write_enable = GND;
|
| 8095 |
|
|
GE1_q_a[6]_PORT_A_write_enable_reg = DFFE(GE1_q_a[6]_PORT_A_write_enable, GE1_q_a[6]_clock_0, , , );
|
| 8096 |
|
|
GE1_q_a[6]_PORT_B_write_enable = WB1L2;
|
| 8097 |
|
|
GE1_q_a[6]_PORT_B_write_enable_reg = DFFE(GE1_q_a[6]_PORT_B_write_enable, GE1_q_a[6]_clock_0, , , );
|
| 8098 |
|
|
GE1_q_a[6]_clock_0 = E1__clk0;
|
| 8099 |
|
|
GE1_q_a[6]_PORT_A_data_out = MEMORY(GE1_q_a[6]_PORT_A_data_in_reg, GE1_q_a[6]_PORT_B_data_in_reg, GE1_q_a[6]_PORT_A_address_reg, GE1_q_a[6]_PORT_B_address_reg, GE1_q_a[6]_PORT_A_write_enable_reg, GE1_q_a[6]_PORT_B_write_enable_reg, , , GE1_q_a[6]_clock_0, , , , , );
|
| 8100 |
|
|
GE1_q_a[6] = GE1_q_a[6]_PORT_A_data_out[0];
|
| 8101 |
|
|
|
| 8102 |
|
|
--GE1_q_b[6] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[6]
|
| 8103 |
|
|
GE1_q_b[6]_PORT_A_data_in = ~GND;
|
| 8104 |
|
|
GE1_q_b[6]_PORT_A_data_in_reg = DFFE(GE1_q_b[6]_PORT_A_data_in, GE1_q_b[6]_clock_0, , , );
|
| 8105 |
|
|
GE1_q_b[6]_PORT_B_data_in = CB1_dout_2_6;
|
| 8106 |
|
|
GE1_q_b[6]_PORT_B_data_in_reg = DFFE(GE1_q_b[6]_PORT_B_data_in, GE1_q_b[6]_clock_0, , , );
|
| 8107 |
|
|
GE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8108 |
|
|
GE1_q_b[6]_PORT_A_address_reg = DFFE(GE1_q_b[6]_PORT_A_address, GE1_q_b[6]_clock_0, , , );
|
| 8109 |
|
|
GE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8110 |
|
|
GE1_q_b[6]_PORT_B_address_reg = DFFE(GE1_q_b[6]_PORT_B_address, GE1_q_b[6]_clock_0, , , );
|
| 8111 |
|
|
GE1_q_b[6]_PORT_A_write_enable = GND;
|
| 8112 |
|
|
GE1_q_b[6]_PORT_A_write_enable_reg = DFFE(GE1_q_b[6]_PORT_A_write_enable, GE1_q_b[6]_clock_0, , , );
|
| 8113 |
|
|
GE1_q_b[6]_PORT_B_write_enable = WB1L2;
|
| 8114 |
|
|
GE1_q_b[6]_PORT_B_write_enable_reg = DFFE(GE1_q_b[6]_PORT_B_write_enable, GE1_q_b[6]_clock_0, , , );
|
| 8115 |
|
|
GE1_q_b[6]_clock_0 = E1__clk0;
|
| 8116 |
|
|
GE1_q_b[6]_PORT_B_data_out = MEMORY(GE1_q_b[6]_PORT_A_data_in_reg, GE1_q_b[6]_PORT_B_data_in_reg, GE1_q_b[6]_PORT_A_address_reg, GE1_q_b[6]_PORT_B_address_reg, GE1_q_b[6]_PORT_A_write_enable_reg, GE1_q_b[6]_PORT_B_write_enable_reg, , , GE1_q_b[6]_clock_0, , , , , );
|
| 8117 |
|
|
GE1_q_b[6] = GE1_q_b[6]_PORT_B_data_out[0];
|
| 8118 |
|
|
|
| 8119 |
|
|
|
| 8120 |
|
|
--UB1_dout_2_i_o2_0[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_o2_0[3]
|
| 8121 |
|
|
--operation mode is normal
|
| 8122 |
|
|
|
| 8123 |
|
|
UB1_dout_2_i_o2_0[3] = RB1_byte_addr_o_1 & RB1_byte_addr_o_0 # !UB1_dout_2_i_o2_0_a[3] # !RB1_byte_addr_o_1 & !UB1_dout_2_i_o2_0_a[3] & RB1_byte_addr_o_0 # !RB1_ctl_o_3;
|
| 8124 |
|
|
|
| 8125 |
|
|
|
| 8126 |
|
|
--HE1_q_a[6] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[6]
|
| 8127 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8128 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8129 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8130 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8131 |
|
|
HE1_q_a[6]_PORT_A_data_in = ~GND;
|
| 8132 |
|
|
HE1_q_a[6]_PORT_A_data_in_reg = DFFE(HE1_q_a[6]_PORT_A_data_in, HE1_q_a[6]_clock_0, , , );
|
| 8133 |
|
|
HE1_q_a[6]_PORT_B_data_in = TB1_dout_1_x_6;
|
| 8134 |
|
|
HE1_q_a[6]_PORT_B_data_in_reg = DFFE(HE1_q_a[6]_PORT_B_data_in, HE1_q_a[6]_clock_0, , , );
|
| 8135 |
|
|
HE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8136 |
|
|
HE1_q_a[6]_PORT_A_address_reg = DFFE(HE1_q_a[6]_PORT_A_address, HE1_q_a[6]_clock_0, , , );
|
| 8137 |
|
|
HE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8138 |
|
|
HE1_q_a[6]_PORT_B_address_reg = DFFE(HE1_q_a[6]_PORT_B_address, HE1_q_a[6]_clock_0, , , );
|
| 8139 |
|
|
HE1_q_a[6]_PORT_A_write_enable = GND;
|
| 8140 |
|
|
HE1_q_a[6]_PORT_A_write_enable_reg = DFFE(HE1_q_a[6]_PORT_A_write_enable, HE1_q_a[6]_clock_0, , , );
|
| 8141 |
|
|
HE1_q_a[6]_PORT_B_write_enable = WB2L2;
|
| 8142 |
|
|
HE1_q_a[6]_PORT_B_write_enable_reg = DFFE(HE1_q_a[6]_PORT_B_write_enable, HE1_q_a[6]_clock_0, , , );
|
| 8143 |
|
|
HE1_q_a[6]_clock_0 = E1__clk0;
|
| 8144 |
|
|
HE1_q_a[6]_PORT_A_data_out = MEMORY(HE1_q_a[6]_PORT_A_data_in_reg, HE1_q_a[6]_PORT_B_data_in_reg, HE1_q_a[6]_PORT_A_address_reg, HE1_q_a[6]_PORT_B_address_reg, HE1_q_a[6]_PORT_A_write_enable_reg, HE1_q_a[6]_PORT_B_write_enable_reg, , , HE1_q_a[6]_clock_0, , , , , );
|
| 8145 |
|
|
HE1_q_a[6] = HE1_q_a[6]_PORT_A_data_out[0];
|
| 8146 |
|
|
|
| 8147 |
|
|
--HE1_q_b[6] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[6]
|
| 8148 |
|
|
HE1_q_b[6]_PORT_A_data_in = ~GND;
|
| 8149 |
|
|
HE1_q_b[6]_PORT_A_data_in_reg = DFFE(HE1_q_b[6]_PORT_A_data_in, HE1_q_b[6]_clock_0, , , );
|
| 8150 |
|
|
HE1_q_b[6]_PORT_B_data_in = TB1_dout_1_x_6;
|
| 8151 |
|
|
HE1_q_b[6]_PORT_B_data_in_reg = DFFE(HE1_q_b[6]_PORT_B_data_in, HE1_q_b[6]_clock_0, , , );
|
| 8152 |
|
|
HE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8153 |
|
|
HE1_q_b[6]_PORT_A_address_reg = DFFE(HE1_q_b[6]_PORT_A_address, HE1_q_b[6]_clock_0, , , );
|
| 8154 |
|
|
HE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8155 |
|
|
HE1_q_b[6]_PORT_B_address_reg = DFFE(HE1_q_b[6]_PORT_B_address, HE1_q_b[6]_clock_0, , , );
|
| 8156 |
|
|
HE1_q_b[6]_PORT_A_write_enable = GND;
|
| 8157 |
|
|
HE1_q_b[6]_PORT_A_write_enable_reg = DFFE(HE1_q_b[6]_PORT_A_write_enable, HE1_q_b[6]_clock_0, , , );
|
| 8158 |
|
|
HE1_q_b[6]_PORT_B_write_enable = WB2L2;
|
| 8159 |
|
|
HE1_q_b[6]_PORT_B_write_enable_reg = DFFE(HE1_q_b[6]_PORT_B_write_enable, HE1_q_b[6]_clock_0, , , );
|
| 8160 |
|
|
HE1_q_b[6]_clock_0 = E1__clk0;
|
| 8161 |
|
|
HE1_q_b[6]_PORT_B_data_out = MEMORY(HE1_q_b[6]_PORT_A_data_in_reg, HE1_q_b[6]_PORT_B_data_in_reg, HE1_q_b[6]_PORT_A_address_reg, HE1_q_b[6]_PORT_B_address_reg, HE1_q_b[6]_PORT_A_write_enable_reg, HE1_q_b[6]_PORT_B_write_enable_reg, , , HE1_q_b[6]_clock_0, , , , , );
|
| 8162 |
|
|
HE1_q_b[6] = HE1_q_b[6]_PORT_B_data_out[0];
|
| 8163 |
|
|
|
| 8164 |
|
|
|
| 8165 |
|
|
--KE1_q_a[6] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[6]
|
| 8166 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8167 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8168 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8169 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8170 |
|
|
KE1_q_a[6]_PORT_A_data_in = ~GND;
|
| 8171 |
|
|
KE1_q_a[6]_PORT_A_data_in_reg = DFFE(KE1_q_a[6]_PORT_A_data_in, KE1_q_a[6]_clock_0, , , );
|
| 8172 |
|
|
KE1_q_a[6]_PORT_B_data_in = TB1_dout_1_2_6;
|
| 8173 |
|
|
KE1_q_a[6]_PORT_B_data_in_reg = DFFE(KE1_q_a[6]_PORT_B_data_in, KE1_q_a[6]_clock_0, , , );
|
| 8174 |
|
|
KE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8175 |
|
|
KE1_q_a[6]_PORT_A_address_reg = DFFE(KE1_q_a[6]_PORT_A_address, KE1_q_a[6]_clock_0, , , );
|
| 8176 |
|
|
KE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8177 |
|
|
KE1_q_a[6]_PORT_B_address_reg = DFFE(KE1_q_a[6]_PORT_B_address, KE1_q_a[6]_clock_0, , , );
|
| 8178 |
|
|
KE1_q_a[6]_PORT_A_write_enable = GND;
|
| 8179 |
|
|
KE1_q_a[6]_PORT_A_write_enable_reg = DFFE(KE1_q_a[6]_PORT_A_write_enable, KE1_q_a[6]_clock_0, , , );
|
| 8180 |
|
|
KE1_q_a[6]_PORT_B_write_enable = WB4L2;
|
| 8181 |
|
|
KE1_q_a[6]_PORT_B_write_enable_reg = DFFE(KE1_q_a[6]_PORT_B_write_enable, KE1_q_a[6]_clock_0, , , );
|
| 8182 |
|
|
KE1_q_a[6]_clock_0 = E1__clk0;
|
| 8183 |
|
|
KE1_q_a[6]_PORT_A_data_out = MEMORY(KE1_q_a[6]_PORT_A_data_in_reg, KE1_q_a[6]_PORT_B_data_in_reg, KE1_q_a[6]_PORT_A_address_reg, KE1_q_a[6]_PORT_B_address_reg, KE1_q_a[6]_PORT_A_write_enable_reg, KE1_q_a[6]_PORT_B_write_enable_reg, , , KE1_q_a[6]_clock_0, , , , , );
|
| 8184 |
|
|
KE1_q_a[6] = KE1_q_a[6]_PORT_A_data_out[0];
|
| 8185 |
|
|
|
| 8186 |
|
|
--KE1_q_b[6] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[6]
|
| 8187 |
|
|
KE1_q_b[6]_PORT_A_data_in = ~GND;
|
| 8188 |
|
|
KE1_q_b[6]_PORT_A_data_in_reg = DFFE(KE1_q_b[6]_PORT_A_data_in, KE1_q_b[6]_clock_0, , , );
|
| 8189 |
|
|
KE1_q_b[6]_PORT_B_data_in = TB1_dout_1_2_6;
|
| 8190 |
|
|
KE1_q_b[6]_PORT_B_data_in_reg = DFFE(KE1_q_b[6]_PORT_B_data_in, KE1_q_b[6]_clock_0, , , );
|
| 8191 |
|
|
KE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8192 |
|
|
KE1_q_b[6]_PORT_A_address_reg = DFFE(KE1_q_b[6]_PORT_A_address, KE1_q_b[6]_clock_0, , , );
|
| 8193 |
|
|
KE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8194 |
|
|
KE1_q_b[6]_PORT_B_address_reg = DFFE(KE1_q_b[6]_PORT_B_address, KE1_q_b[6]_clock_0, , , );
|
| 8195 |
|
|
KE1_q_b[6]_PORT_A_write_enable = GND;
|
| 8196 |
|
|
KE1_q_b[6]_PORT_A_write_enable_reg = DFFE(KE1_q_b[6]_PORT_A_write_enable, KE1_q_b[6]_clock_0, , , );
|
| 8197 |
|
|
KE1_q_b[6]_PORT_B_write_enable = WB4L2;
|
| 8198 |
|
|
KE1_q_b[6]_PORT_B_write_enable_reg = DFFE(KE1_q_b[6]_PORT_B_write_enable, KE1_q_b[6]_clock_0, , , );
|
| 8199 |
|
|
KE1_q_b[6]_clock_0 = E1__clk0;
|
| 8200 |
|
|
KE1_q_b[6]_PORT_B_data_out = MEMORY(KE1_q_b[6]_PORT_A_data_in_reg, KE1_q_b[6]_PORT_B_data_in_reg, KE1_q_b[6]_PORT_A_address_reg, KE1_q_b[6]_PORT_B_address_reg, KE1_q_b[6]_PORT_A_write_enable_reg, KE1_q_b[6]_PORT_B_write_enable_reg, , , KE1_q_b[6]_clock_0, , , , , );
|
| 8201 |
|
|
KE1_q_b[6] = KE1_q_b[6]_PORT_B_data_out[0];
|
| 8202 |
|
|
|
| 8203 |
|
|
|
| 8204 |
|
|
--UB1_dout_2_i_a3_1[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_a3_1[3]
|
| 8205 |
|
|
--operation mode is normal
|
| 8206 |
|
|
|
| 8207 |
|
|
UB1_dout_2_i_a3_1[3] = RB1_byte_addr_o_1 & !RB1_byte_addr_o_0 & UB1_dout_2_i_i_o3[7];
|
| 8208 |
|
|
|
| 8209 |
|
|
|
| 8210 |
|
|
--UB1_dout_2_i_a3_0[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_a3_0[3]
|
| 8211 |
|
|
--operation mode is normal
|
| 8212 |
|
|
|
| 8213 |
|
|
UB1_dout_2_i_a3_0[3] = !RB1_byte_addr_o_1 & !RB1_byte_addr_o_0 & UB1_dout_2_i_i_o3[7];
|
| 8214 |
|
|
|
| 8215 |
|
|
|
| 8216 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[8] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[8]
|
| 8217 |
|
|
--operation mode is normal
|
| 8218 |
|
|
|
| 8219 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[8] = QB1_r32_o_8 & !FB1_r32_o_0_8 & QD1_b_o18 # !QB1_r32_o_8 & QD1_un1_b_o18_2 # !FB1_r32_o_0_8 & QD1_b_o18;
|
| 8220 |
|
|
|
| 8221 |
|
|
|
| 8222 |
|
|
--G1_BUS15471_i_m[8] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[8]
|
| 8223 |
|
|
--operation mode is normal
|
| 8224 |
|
|
|
| 8225 |
|
|
G1_BUS15471_i_m[8] = !FD1_wb_o_8 & QD1_b_o_1_sqmuxa;
|
| 8226 |
|
|
|
| 8227 |
|
|
|
| 8228 |
|
|
--UD1_shift_out_87_d_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[6]
|
| 8229 |
|
|
--operation mode is normal
|
| 8230 |
|
|
|
| 8231 |
|
|
UD1_shift_out_87_d_a[6] = PD1_a_o_1 & !VD1_b_o_iv_12 # !PD1_a_o_1 & !VD1_b_o_iv_10;
|
| 8232 |
|
|
|
| 8233 |
|
|
|
| 8234 |
|
|
--UD1_shift_out_80[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[6]
|
| 8235 |
|
|
--operation mode is normal
|
| 8236 |
|
|
|
| 8237 |
|
|
UD1_shift_out_80[6] = PD1_a_o_2 & UD1_shift_out_80_a[6] & VD1_b_o_iv_11 # !UD1_shift_out_80_a[6] & VD1_b_o_iv_13 # !PD1_a_o_2 & !UD1_shift_out_80_a[6];
|
| 8238 |
|
|
|
| 8239 |
|
|
|
| 8240 |
|
|
--UD1_shift_out_85_d_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[6]
|
| 8241 |
|
|
--operation mode is normal
|
| 8242 |
|
|
|
| 8243 |
|
|
UD1_shift_out_85_d_a[6] = PD1_a_o_0 & !VD1_b_o_iv_3 # !PD1_a_o_0 & !VD1_b_o_iv_4;
|
| 8244 |
|
|
|
| 8245 |
|
|
|
| 8246 |
|
|
--UD1_shift_out_43[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43[30]
|
| 8247 |
|
|
--operation mode is normal
|
| 8248 |
|
|
|
| 8249 |
|
|
UD1_shift_out_43[30] = PD1_a_o_0 & VD1_b_o_iv_1 & !PD1_a_o_1 # !PD1_a_o_0 & !UD1_shift_out_43_a[30];
|
| 8250 |
|
|
|
| 8251 |
|
|
|
| 8252 |
|
|
--TD1_alu_out_7_0_0_m4_0[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[6]
|
| 8253 |
|
|
--operation mode is normal
|
| 8254 |
|
|
|
| 8255 |
|
|
TD1_alu_out_7_0_0_m4_0[6] = VD1_b_o_iv_6 & TD1_alu_out_7_0_0_o3_0 & TD1_alu_out_0_a3[28] # !VD1_b_o_iv_6 & TD1_alu_out_7_0_0_m4_0_a[3];
|
| 8256 |
|
|
|
| 8257 |
|
|
|
| 8258 |
|
|
--TD1_alu_out_0_a2_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_a[6]
|
| 8259 |
|
|
--operation mode is normal
|
| 8260 |
|
|
|
| 8261 |
|
|
TD1_alu_out_0_a2_a[6] = VD1_b_o_iv_6 & !TD1_m107 # !VD1_b_o_iv_6 & !TD1_alu_out_0_a3[28];
|
| 8262 |
|
|
|
| 8263 |
|
|
|
| 8264 |
|
|
--PD1_a_o_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[6]
|
| 8265 |
|
|
--operation mode is normal
|
| 8266 |
|
|
|
| 8267 |
|
|
PD1_a_o_a[6] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_6 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_6;
|
| 8268 |
|
|
|
| 8269 |
|
|
|
| 8270 |
|
|
--PD1_a_o_3_Z[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[6]
|
| 8271 |
|
|
--operation mode is normal
|
| 8272 |
|
|
|
| 8273 |
|
|
PD1_a_o_3_Z[6] = PD1_a_o_3_s[0] & SD1_r32_o_6 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[6];
|
| 8274 |
|
|
|
| 8275 |
|
|
|
| 8276 |
|
|
--UD1_shift_out_76_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[6]
|
| 8277 |
|
|
--operation mode is normal
|
| 8278 |
|
|
|
| 8279 |
|
|
UD1_shift_out_76_a[6] = PD1_a_o_2 & !PD1_a_o_3 # !PD1_a_o_2 & !PD1_a_o_1 & UD1_shift_out_39[18];
|
| 8280 |
|
|
|
| 8281 |
|
|
|
| 8282 |
|
|
--UD1_shift_out_47[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_47[2]
|
| 8283 |
|
|
--operation mode is normal
|
| 8284 |
|
|
|
| 8285 |
|
|
UD1_shift_out_47[2] = PD1_a_o_1 & !UD1_shift_out_47_a[2] # !PD1_a_o_1 & UD1_shift_out_47_a[2] & VD1_b_o_iv_22 # !UD1_shift_out_47_a[2] & VD1_b_o_iv_23;
|
| 8286 |
|
|
|
| 8287 |
|
|
|
| 8288 |
|
|
--UD1_shift_out_61[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_61[6]
|
| 8289 |
|
|
--operation mode is normal
|
| 8290 |
|
|
|
| 8291 |
|
|
UD1_shift_out_61[6] = PD1_a_o_2 & UD1_shift_out_79[18] # !PD1_a_o_2 & UD1_shift_out_47[2];
|
| 8292 |
|
|
|
| 8293 |
|
|
|
| 8294 |
|
|
--UD1_shift_out_74_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[6]
|
| 8295 |
|
|
--operation mode is normal
|
| 8296 |
|
|
|
| 8297 |
|
|
UD1_shift_out_74_a[6] = PD1_a_o_0 & !VD1_b_o_iv_31 # !PD1_a_o_0 & UD1_shift_out_63_a[17] & !VD1_b_o_iv_30 # !UD1_shift_out_63_a[17] & !VD1_b_o_iv_31;
|
| 8298 |
|
|
|
| 8299 |
|
|
|
| 8300 |
|
|
--TB1_dout_1_5 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_5
|
| 8301 |
|
|
--operation mode is normal
|
| 8302 |
|
|
|
| 8303 |
|
|
TB1_dout_1_5 = TB1_dout21 & CB1_dout_2_5 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_5 # !TB1_dout22 & CB1_dout_2_21;
|
| 8304 |
|
|
|
| 8305 |
|
|
|
| 8306 |
|
|
--GE1_q_a[5] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[5]
|
| 8307 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8308 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8309 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8310 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8311 |
|
|
GE1_q_a[5]_PORT_A_data_in = ~GND;
|
| 8312 |
|
|
GE1_q_a[5]_PORT_A_data_in_reg = DFFE(GE1_q_a[5]_PORT_A_data_in, GE1_q_a[5]_clock_0, , , );
|
| 8313 |
|
|
GE1_q_a[5]_PORT_B_data_in = CB1_dout_2_5;
|
| 8314 |
|
|
GE1_q_a[5]_PORT_B_data_in_reg = DFFE(GE1_q_a[5]_PORT_B_data_in, GE1_q_a[5]_clock_0, , , );
|
| 8315 |
|
|
GE1_q_a[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8316 |
|
|
GE1_q_a[5]_PORT_A_address_reg = DFFE(GE1_q_a[5]_PORT_A_address, GE1_q_a[5]_clock_0, , , );
|
| 8317 |
|
|
GE1_q_a[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8318 |
|
|
GE1_q_a[5]_PORT_B_address_reg = DFFE(GE1_q_a[5]_PORT_B_address, GE1_q_a[5]_clock_0, , , );
|
| 8319 |
|
|
GE1_q_a[5]_PORT_A_write_enable = GND;
|
| 8320 |
|
|
GE1_q_a[5]_PORT_A_write_enable_reg = DFFE(GE1_q_a[5]_PORT_A_write_enable, GE1_q_a[5]_clock_0, , , );
|
| 8321 |
|
|
GE1_q_a[5]_PORT_B_write_enable = WB1L2;
|
| 8322 |
|
|
GE1_q_a[5]_PORT_B_write_enable_reg = DFFE(GE1_q_a[5]_PORT_B_write_enable, GE1_q_a[5]_clock_0, , , );
|
| 8323 |
|
|
GE1_q_a[5]_clock_0 = E1__clk0;
|
| 8324 |
|
|
GE1_q_a[5]_PORT_A_data_out = MEMORY(GE1_q_a[5]_PORT_A_data_in_reg, GE1_q_a[5]_PORT_B_data_in_reg, GE1_q_a[5]_PORT_A_address_reg, GE1_q_a[5]_PORT_B_address_reg, GE1_q_a[5]_PORT_A_write_enable_reg, GE1_q_a[5]_PORT_B_write_enable_reg, , , GE1_q_a[5]_clock_0, , , , , );
|
| 8325 |
|
|
GE1_q_a[5] = GE1_q_a[5]_PORT_A_data_out[0];
|
| 8326 |
|
|
|
| 8327 |
|
|
--GE1_q_b[5] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[5]
|
| 8328 |
|
|
GE1_q_b[5]_PORT_A_data_in = ~GND;
|
| 8329 |
|
|
GE1_q_b[5]_PORT_A_data_in_reg = DFFE(GE1_q_b[5]_PORT_A_data_in, GE1_q_b[5]_clock_0, , , );
|
| 8330 |
|
|
GE1_q_b[5]_PORT_B_data_in = CB1_dout_2_5;
|
| 8331 |
|
|
GE1_q_b[5]_PORT_B_data_in_reg = DFFE(GE1_q_b[5]_PORT_B_data_in, GE1_q_b[5]_clock_0, , , );
|
| 8332 |
|
|
GE1_q_b[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8333 |
|
|
GE1_q_b[5]_PORT_A_address_reg = DFFE(GE1_q_b[5]_PORT_A_address, GE1_q_b[5]_clock_0, , , );
|
| 8334 |
|
|
GE1_q_b[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8335 |
|
|
GE1_q_b[5]_PORT_B_address_reg = DFFE(GE1_q_b[5]_PORT_B_address, GE1_q_b[5]_clock_0, , , );
|
| 8336 |
|
|
GE1_q_b[5]_PORT_A_write_enable = GND;
|
| 8337 |
|
|
GE1_q_b[5]_PORT_A_write_enable_reg = DFFE(GE1_q_b[5]_PORT_A_write_enable, GE1_q_b[5]_clock_0, , , );
|
| 8338 |
|
|
GE1_q_b[5]_PORT_B_write_enable = WB1L2;
|
| 8339 |
|
|
GE1_q_b[5]_PORT_B_write_enable_reg = DFFE(GE1_q_b[5]_PORT_B_write_enable, GE1_q_b[5]_clock_0, , , );
|
| 8340 |
|
|
GE1_q_b[5]_clock_0 = E1__clk0;
|
| 8341 |
|
|
GE1_q_b[5]_PORT_B_data_out = MEMORY(GE1_q_b[5]_PORT_A_data_in_reg, GE1_q_b[5]_PORT_B_data_in_reg, GE1_q_b[5]_PORT_A_address_reg, GE1_q_b[5]_PORT_B_address_reg, GE1_q_b[5]_PORT_A_write_enable_reg, GE1_q_b[5]_PORT_B_write_enable_reg, , , GE1_q_b[5]_clock_0, , , , , );
|
| 8342 |
|
|
GE1_q_b[5] = GE1_q_b[5]_PORT_B_data_out[0];
|
| 8343 |
|
|
|
| 8344 |
|
|
|
| 8345 |
|
|
--HE1_q_a[5] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[5]
|
| 8346 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8347 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8348 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8349 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8350 |
|
|
HE1_q_a[5]_PORT_A_data_in = ~GND;
|
| 8351 |
|
|
HE1_q_a[5]_PORT_A_data_in_reg = DFFE(HE1_q_a[5]_PORT_A_data_in, HE1_q_a[5]_clock_0, , , );
|
| 8352 |
|
|
HE1_q_a[5]_PORT_B_data_in = TB1_dout_1_x_5;
|
| 8353 |
|
|
HE1_q_a[5]_PORT_B_data_in_reg = DFFE(HE1_q_a[5]_PORT_B_data_in, HE1_q_a[5]_clock_0, , , );
|
| 8354 |
|
|
HE1_q_a[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8355 |
|
|
HE1_q_a[5]_PORT_A_address_reg = DFFE(HE1_q_a[5]_PORT_A_address, HE1_q_a[5]_clock_0, , , );
|
| 8356 |
|
|
HE1_q_a[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8357 |
|
|
HE1_q_a[5]_PORT_B_address_reg = DFFE(HE1_q_a[5]_PORT_B_address, HE1_q_a[5]_clock_0, , , );
|
| 8358 |
|
|
HE1_q_a[5]_PORT_A_write_enable = GND;
|
| 8359 |
|
|
HE1_q_a[5]_PORT_A_write_enable_reg = DFFE(HE1_q_a[5]_PORT_A_write_enable, HE1_q_a[5]_clock_0, , , );
|
| 8360 |
|
|
HE1_q_a[5]_PORT_B_write_enable = WB2L2;
|
| 8361 |
|
|
HE1_q_a[5]_PORT_B_write_enable_reg = DFFE(HE1_q_a[5]_PORT_B_write_enable, HE1_q_a[5]_clock_0, , , );
|
| 8362 |
|
|
HE1_q_a[5]_clock_0 = E1__clk0;
|
| 8363 |
|
|
HE1_q_a[5]_PORT_A_data_out = MEMORY(HE1_q_a[5]_PORT_A_data_in_reg, HE1_q_a[5]_PORT_B_data_in_reg, HE1_q_a[5]_PORT_A_address_reg, HE1_q_a[5]_PORT_B_address_reg, HE1_q_a[5]_PORT_A_write_enable_reg, HE1_q_a[5]_PORT_B_write_enable_reg, , , HE1_q_a[5]_clock_0, , , , , );
|
| 8364 |
|
|
HE1_q_a[5] = HE1_q_a[5]_PORT_A_data_out[0];
|
| 8365 |
|
|
|
| 8366 |
|
|
--HE1_q_b[5] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[5]
|
| 8367 |
|
|
HE1_q_b[5]_PORT_A_data_in = ~GND;
|
| 8368 |
|
|
HE1_q_b[5]_PORT_A_data_in_reg = DFFE(HE1_q_b[5]_PORT_A_data_in, HE1_q_b[5]_clock_0, , , );
|
| 8369 |
|
|
HE1_q_b[5]_PORT_B_data_in = TB1_dout_1_x_5;
|
| 8370 |
|
|
HE1_q_b[5]_PORT_B_data_in_reg = DFFE(HE1_q_b[5]_PORT_B_data_in, HE1_q_b[5]_clock_0, , , );
|
| 8371 |
|
|
HE1_q_b[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8372 |
|
|
HE1_q_b[5]_PORT_A_address_reg = DFFE(HE1_q_b[5]_PORT_A_address, HE1_q_b[5]_clock_0, , , );
|
| 8373 |
|
|
HE1_q_b[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8374 |
|
|
HE1_q_b[5]_PORT_B_address_reg = DFFE(HE1_q_b[5]_PORT_B_address, HE1_q_b[5]_clock_0, , , );
|
| 8375 |
|
|
HE1_q_b[5]_PORT_A_write_enable = GND;
|
| 8376 |
|
|
HE1_q_b[5]_PORT_A_write_enable_reg = DFFE(HE1_q_b[5]_PORT_A_write_enable, HE1_q_b[5]_clock_0, , , );
|
| 8377 |
|
|
HE1_q_b[5]_PORT_B_write_enable = WB2L2;
|
| 8378 |
|
|
HE1_q_b[5]_PORT_B_write_enable_reg = DFFE(HE1_q_b[5]_PORT_B_write_enable, HE1_q_b[5]_clock_0, , , );
|
| 8379 |
|
|
HE1_q_b[5]_clock_0 = E1__clk0;
|
| 8380 |
|
|
HE1_q_b[5]_PORT_B_data_out = MEMORY(HE1_q_b[5]_PORT_A_data_in_reg, HE1_q_b[5]_PORT_B_data_in_reg, HE1_q_b[5]_PORT_A_address_reg, HE1_q_b[5]_PORT_B_address_reg, HE1_q_b[5]_PORT_A_write_enable_reg, HE1_q_b[5]_PORT_B_write_enable_reg, , , HE1_q_b[5]_clock_0, , , , , );
|
| 8381 |
|
|
HE1_q_b[5] = HE1_q_b[5]_PORT_B_data_out[0];
|
| 8382 |
|
|
|
| 8383 |
|
|
|
| 8384 |
|
|
--KE1_q_a[5] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[5]
|
| 8385 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8386 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8387 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8388 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8389 |
|
|
KE1_q_a[5]_PORT_A_data_in = ~GND;
|
| 8390 |
|
|
KE1_q_a[5]_PORT_A_data_in_reg = DFFE(KE1_q_a[5]_PORT_A_data_in, KE1_q_a[5]_clock_0, , , );
|
| 8391 |
|
|
KE1_q_a[5]_PORT_B_data_in = TB1_dout_1_2_5;
|
| 8392 |
|
|
KE1_q_a[5]_PORT_B_data_in_reg = DFFE(KE1_q_a[5]_PORT_B_data_in, KE1_q_a[5]_clock_0, , , );
|
| 8393 |
|
|
KE1_q_a[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8394 |
|
|
KE1_q_a[5]_PORT_A_address_reg = DFFE(KE1_q_a[5]_PORT_A_address, KE1_q_a[5]_clock_0, , , );
|
| 8395 |
|
|
KE1_q_a[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8396 |
|
|
KE1_q_a[5]_PORT_B_address_reg = DFFE(KE1_q_a[5]_PORT_B_address, KE1_q_a[5]_clock_0, , , );
|
| 8397 |
|
|
KE1_q_a[5]_PORT_A_write_enable = GND;
|
| 8398 |
|
|
KE1_q_a[5]_PORT_A_write_enable_reg = DFFE(KE1_q_a[5]_PORT_A_write_enable, KE1_q_a[5]_clock_0, , , );
|
| 8399 |
|
|
KE1_q_a[5]_PORT_B_write_enable = WB4L2;
|
| 8400 |
|
|
KE1_q_a[5]_PORT_B_write_enable_reg = DFFE(KE1_q_a[5]_PORT_B_write_enable, KE1_q_a[5]_clock_0, , , );
|
| 8401 |
|
|
KE1_q_a[5]_clock_0 = E1__clk0;
|
| 8402 |
|
|
KE1_q_a[5]_PORT_A_data_out = MEMORY(KE1_q_a[5]_PORT_A_data_in_reg, KE1_q_a[5]_PORT_B_data_in_reg, KE1_q_a[5]_PORT_A_address_reg, KE1_q_a[5]_PORT_B_address_reg, KE1_q_a[5]_PORT_A_write_enable_reg, KE1_q_a[5]_PORT_B_write_enable_reg, , , KE1_q_a[5]_clock_0, , , , , );
|
| 8403 |
|
|
KE1_q_a[5] = KE1_q_a[5]_PORT_A_data_out[0];
|
| 8404 |
|
|
|
| 8405 |
|
|
--KE1_q_b[5] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[5]
|
| 8406 |
|
|
KE1_q_b[5]_PORT_A_data_in = ~GND;
|
| 8407 |
|
|
KE1_q_b[5]_PORT_A_data_in_reg = DFFE(KE1_q_b[5]_PORT_A_data_in, KE1_q_b[5]_clock_0, , , );
|
| 8408 |
|
|
KE1_q_b[5]_PORT_B_data_in = TB1_dout_1_2_5;
|
| 8409 |
|
|
KE1_q_b[5]_PORT_B_data_in_reg = DFFE(KE1_q_b[5]_PORT_B_data_in, KE1_q_b[5]_clock_0, , , );
|
| 8410 |
|
|
KE1_q_b[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8411 |
|
|
KE1_q_b[5]_PORT_A_address_reg = DFFE(KE1_q_b[5]_PORT_A_address, KE1_q_b[5]_clock_0, , , );
|
| 8412 |
|
|
KE1_q_b[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8413 |
|
|
KE1_q_b[5]_PORT_B_address_reg = DFFE(KE1_q_b[5]_PORT_B_address, KE1_q_b[5]_clock_0, , , );
|
| 8414 |
|
|
KE1_q_b[5]_PORT_A_write_enable = GND;
|
| 8415 |
|
|
KE1_q_b[5]_PORT_A_write_enable_reg = DFFE(KE1_q_b[5]_PORT_A_write_enable, KE1_q_b[5]_clock_0, , , );
|
| 8416 |
|
|
KE1_q_b[5]_PORT_B_write_enable = WB4L2;
|
| 8417 |
|
|
KE1_q_b[5]_PORT_B_write_enable_reg = DFFE(KE1_q_b[5]_PORT_B_write_enable, KE1_q_b[5]_clock_0, , , );
|
| 8418 |
|
|
KE1_q_b[5]_clock_0 = E1__clk0;
|
| 8419 |
|
|
KE1_q_b[5]_PORT_B_data_out = MEMORY(KE1_q_b[5]_PORT_A_data_in_reg, KE1_q_b[5]_PORT_B_data_in_reg, KE1_q_b[5]_PORT_A_address_reg, KE1_q_b[5]_PORT_B_address_reg, KE1_q_b[5]_PORT_A_write_enable_reg, KE1_q_b[5]_PORT_B_write_enable_reg, , , KE1_q_b[5]_clock_0, , , , , );
|
| 8420 |
|
|
KE1_q_b[5] = KE1_q_b[5]_PORT_B_data_out[0];
|
| 8421 |
|
|
|
| 8422 |
|
|
|
| 8423 |
|
|
--GE1_q_a[4] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[4]
|
| 8424 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8425 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8426 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8427 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8428 |
|
|
GE1_q_a[4]_PORT_A_data_in = ~GND;
|
| 8429 |
|
|
GE1_q_a[4]_PORT_A_data_in_reg = DFFE(GE1_q_a[4]_PORT_A_data_in, GE1_q_a[4]_clock_0, , , );
|
| 8430 |
|
|
GE1_q_a[4]_PORT_B_data_in = CB1_dout_2_4;
|
| 8431 |
|
|
GE1_q_a[4]_PORT_B_data_in_reg = DFFE(GE1_q_a[4]_PORT_B_data_in, GE1_q_a[4]_clock_0, , , );
|
| 8432 |
|
|
GE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8433 |
|
|
GE1_q_a[4]_PORT_A_address_reg = DFFE(GE1_q_a[4]_PORT_A_address, GE1_q_a[4]_clock_0, , , );
|
| 8434 |
|
|
GE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8435 |
|
|
GE1_q_a[4]_PORT_B_address_reg = DFFE(GE1_q_a[4]_PORT_B_address, GE1_q_a[4]_clock_0, , , );
|
| 8436 |
|
|
GE1_q_a[4]_PORT_A_write_enable = GND;
|
| 8437 |
|
|
GE1_q_a[4]_PORT_A_write_enable_reg = DFFE(GE1_q_a[4]_PORT_A_write_enable, GE1_q_a[4]_clock_0, , , );
|
| 8438 |
|
|
GE1_q_a[4]_PORT_B_write_enable = WB1L2;
|
| 8439 |
|
|
GE1_q_a[4]_PORT_B_write_enable_reg = DFFE(GE1_q_a[4]_PORT_B_write_enable, GE1_q_a[4]_clock_0, , , );
|
| 8440 |
|
|
GE1_q_a[4]_clock_0 = E1__clk0;
|
| 8441 |
|
|
GE1_q_a[4]_PORT_A_data_out = MEMORY(GE1_q_a[4]_PORT_A_data_in_reg, GE1_q_a[4]_PORT_B_data_in_reg, GE1_q_a[4]_PORT_A_address_reg, GE1_q_a[4]_PORT_B_address_reg, GE1_q_a[4]_PORT_A_write_enable_reg, GE1_q_a[4]_PORT_B_write_enable_reg, , , GE1_q_a[4]_clock_0, , , , , );
|
| 8442 |
|
|
GE1_q_a[4] = GE1_q_a[4]_PORT_A_data_out[0];
|
| 8443 |
|
|
|
| 8444 |
|
|
--GE1_q_b[4] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[4]
|
| 8445 |
|
|
GE1_q_b[4]_PORT_A_data_in = ~GND;
|
| 8446 |
|
|
GE1_q_b[4]_PORT_A_data_in_reg = DFFE(GE1_q_b[4]_PORT_A_data_in, GE1_q_b[4]_clock_0, , , );
|
| 8447 |
|
|
GE1_q_b[4]_PORT_B_data_in = CB1_dout_2_4;
|
| 8448 |
|
|
GE1_q_b[4]_PORT_B_data_in_reg = DFFE(GE1_q_b[4]_PORT_B_data_in, GE1_q_b[4]_clock_0, , , );
|
| 8449 |
|
|
GE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8450 |
|
|
GE1_q_b[4]_PORT_A_address_reg = DFFE(GE1_q_b[4]_PORT_A_address, GE1_q_b[4]_clock_0, , , );
|
| 8451 |
|
|
GE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8452 |
|
|
GE1_q_b[4]_PORT_B_address_reg = DFFE(GE1_q_b[4]_PORT_B_address, GE1_q_b[4]_clock_0, , , );
|
| 8453 |
|
|
GE1_q_b[4]_PORT_A_write_enable = GND;
|
| 8454 |
|
|
GE1_q_b[4]_PORT_A_write_enable_reg = DFFE(GE1_q_b[4]_PORT_A_write_enable, GE1_q_b[4]_clock_0, , , );
|
| 8455 |
|
|
GE1_q_b[4]_PORT_B_write_enable = WB1L2;
|
| 8456 |
|
|
GE1_q_b[4]_PORT_B_write_enable_reg = DFFE(GE1_q_b[4]_PORT_B_write_enable, GE1_q_b[4]_clock_0, , , );
|
| 8457 |
|
|
GE1_q_b[4]_clock_0 = E1__clk0;
|
| 8458 |
|
|
GE1_q_b[4]_PORT_B_data_out = MEMORY(GE1_q_b[4]_PORT_A_data_in_reg, GE1_q_b[4]_PORT_B_data_in_reg, GE1_q_b[4]_PORT_A_address_reg, GE1_q_b[4]_PORT_B_address_reg, GE1_q_b[4]_PORT_A_write_enable_reg, GE1_q_b[4]_PORT_B_write_enable_reg, , , GE1_q_b[4]_clock_0, , , , , );
|
| 8459 |
|
|
GE1_q_b[4] = GE1_q_b[4]_PORT_B_data_out[0];
|
| 8460 |
|
|
|
| 8461 |
|
|
|
| 8462 |
|
|
--KE1_q_a[4] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[4]
|
| 8463 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8464 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8465 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8466 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8467 |
|
|
KE1_q_a[4]_PORT_A_data_in = ~GND;
|
| 8468 |
|
|
KE1_q_a[4]_PORT_A_data_in_reg = DFFE(KE1_q_a[4]_PORT_A_data_in, KE1_q_a[4]_clock_0, , , );
|
| 8469 |
|
|
KE1_q_a[4]_PORT_B_data_in = TB1_dout_1_2_4;
|
| 8470 |
|
|
KE1_q_a[4]_PORT_B_data_in_reg = DFFE(KE1_q_a[4]_PORT_B_data_in, KE1_q_a[4]_clock_0, , , );
|
| 8471 |
|
|
KE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8472 |
|
|
KE1_q_a[4]_PORT_A_address_reg = DFFE(KE1_q_a[4]_PORT_A_address, KE1_q_a[4]_clock_0, , , );
|
| 8473 |
|
|
KE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8474 |
|
|
KE1_q_a[4]_PORT_B_address_reg = DFFE(KE1_q_a[4]_PORT_B_address, KE1_q_a[4]_clock_0, , , );
|
| 8475 |
|
|
KE1_q_a[4]_PORT_A_write_enable = GND;
|
| 8476 |
|
|
KE1_q_a[4]_PORT_A_write_enable_reg = DFFE(KE1_q_a[4]_PORT_A_write_enable, KE1_q_a[4]_clock_0, , , );
|
| 8477 |
|
|
KE1_q_a[4]_PORT_B_write_enable = WB4L2;
|
| 8478 |
|
|
KE1_q_a[4]_PORT_B_write_enable_reg = DFFE(KE1_q_a[4]_PORT_B_write_enable, KE1_q_a[4]_clock_0, , , );
|
| 8479 |
|
|
KE1_q_a[4]_clock_0 = E1__clk0;
|
| 8480 |
|
|
KE1_q_a[4]_PORT_A_data_out = MEMORY(KE1_q_a[4]_PORT_A_data_in_reg, KE1_q_a[4]_PORT_B_data_in_reg, KE1_q_a[4]_PORT_A_address_reg, KE1_q_a[4]_PORT_B_address_reg, KE1_q_a[4]_PORT_A_write_enable_reg, KE1_q_a[4]_PORT_B_write_enable_reg, , , KE1_q_a[4]_clock_0, , , , , );
|
| 8481 |
|
|
KE1_q_a[4] = KE1_q_a[4]_PORT_A_data_out[0];
|
| 8482 |
|
|
|
| 8483 |
|
|
--KE1_q_b[4] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[4]
|
| 8484 |
|
|
KE1_q_b[4]_PORT_A_data_in = ~GND;
|
| 8485 |
|
|
KE1_q_b[4]_PORT_A_data_in_reg = DFFE(KE1_q_b[4]_PORT_A_data_in, KE1_q_b[4]_clock_0, , , );
|
| 8486 |
|
|
KE1_q_b[4]_PORT_B_data_in = TB1_dout_1_2_4;
|
| 8487 |
|
|
KE1_q_b[4]_PORT_B_data_in_reg = DFFE(KE1_q_b[4]_PORT_B_data_in, KE1_q_b[4]_clock_0, , , );
|
| 8488 |
|
|
KE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8489 |
|
|
KE1_q_b[4]_PORT_A_address_reg = DFFE(KE1_q_b[4]_PORT_A_address, KE1_q_b[4]_clock_0, , , );
|
| 8490 |
|
|
KE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8491 |
|
|
KE1_q_b[4]_PORT_B_address_reg = DFFE(KE1_q_b[4]_PORT_B_address, KE1_q_b[4]_clock_0, , , );
|
| 8492 |
|
|
KE1_q_b[4]_PORT_A_write_enable = GND;
|
| 8493 |
|
|
KE1_q_b[4]_PORT_A_write_enable_reg = DFFE(KE1_q_b[4]_PORT_A_write_enable, KE1_q_b[4]_clock_0, , , );
|
| 8494 |
|
|
KE1_q_b[4]_PORT_B_write_enable = WB4L2;
|
| 8495 |
|
|
KE1_q_b[4]_PORT_B_write_enable_reg = DFFE(KE1_q_b[4]_PORT_B_write_enable, KE1_q_b[4]_clock_0, , , );
|
| 8496 |
|
|
KE1_q_b[4]_clock_0 = E1__clk0;
|
| 8497 |
|
|
KE1_q_b[4]_PORT_B_data_out = MEMORY(KE1_q_b[4]_PORT_A_data_in_reg, KE1_q_b[4]_PORT_B_data_in_reg, KE1_q_b[4]_PORT_A_address_reg, KE1_q_b[4]_PORT_B_address_reg, KE1_q_b[4]_PORT_A_write_enable_reg, KE1_q_b[4]_PORT_B_write_enable_reg, , , KE1_q_b[4]_clock_0, , , , , );
|
| 8498 |
|
|
KE1_q_b[4] = KE1_q_b[4]_PORT_B_data_out[0];
|
| 8499 |
|
|
|
| 8500 |
|
|
|
| 8501 |
|
|
--HE1_q_a[4] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[4]
|
| 8502 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8503 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8504 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8505 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8506 |
|
|
HE1_q_a[4]_PORT_A_data_in = ~GND;
|
| 8507 |
|
|
HE1_q_a[4]_PORT_A_data_in_reg = DFFE(HE1_q_a[4]_PORT_A_data_in, HE1_q_a[4]_clock_0, , , );
|
| 8508 |
|
|
HE1_q_a[4]_PORT_B_data_in = TB1_dout_1_x_4;
|
| 8509 |
|
|
HE1_q_a[4]_PORT_B_data_in_reg = DFFE(HE1_q_a[4]_PORT_B_data_in, HE1_q_a[4]_clock_0, , , );
|
| 8510 |
|
|
HE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8511 |
|
|
HE1_q_a[4]_PORT_A_address_reg = DFFE(HE1_q_a[4]_PORT_A_address, HE1_q_a[4]_clock_0, , , );
|
| 8512 |
|
|
HE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8513 |
|
|
HE1_q_a[4]_PORT_B_address_reg = DFFE(HE1_q_a[4]_PORT_B_address, HE1_q_a[4]_clock_0, , , );
|
| 8514 |
|
|
HE1_q_a[4]_PORT_A_write_enable = GND;
|
| 8515 |
|
|
HE1_q_a[4]_PORT_A_write_enable_reg = DFFE(HE1_q_a[4]_PORT_A_write_enable, HE1_q_a[4]_clock_0, , , );
|
| 8516 |
|
|
HE1_q_a[4]_PORT_B_write_enable = WB2L2;
|
| 8517 |
|
|
HE1_q_a[4]_PORT_B_write_enable_reg = DFFE(HE1_q_a[4]_PORT_B_write_enable, HE1_q_a[4]_clock_0, , , );
|
| 8518 |
|
|
HE1_q_a[4]_clock_0 = E1__clk0;
|
| 8519 |
|
|
HE1_q_a[4]_PORT_A_data_out = MEMORY(HE1_q_a[4]_PORT_A_data_in_reg, HE1_q_a[4]_PORT_B_data_in_reg, HE1_q_a[4]_PORT_A_address_reg, HE1_q_a[4]_PORT_B_address_reg, HE1_q_a[4]_PORT_A_write_enable_reg, HE1_q_a[4]_PORT_B_write_enable_reg, , , HE1_q_a[4]_clock_0, , , , , );
|
| 8520 |
|
|
HE1_q_a[4] = HE1_q_a[4]_PORT_A_data_out[0];
|
| 8521 |
|
|
|
| 8522 |
|
|
--HE1_q_b[4] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[4]
|
| 8523 |
|
|
HE1_q_b[4]_PORT_A_data_in = ~GND;
|
| 8524 |
|
|
HE1_q_b[4]_PORT_A_data_in_reg = DFFE(HE1_q_b[4]_PORT_A_data_in, HE1_q_b[4]_clock_0, , , );
|
| 8525 |
|
|
HE1_q_b[4]_PORT_B_data_in = TB1_dout_1_x_4;
|
| 8526 |
|
|
HE1_q_b[4]_PORT_B_data_in_reg = DFFE(HE1_q_b[4]_PORT_B_data_in, HE1_q_b[4]_clock_0, , , );
|
| 8527 |
|
|
HE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8528 |
|
|
HE1_q_b[4]_PORT_A_address_reg = DFFE(HE1_q_b[4]_PORT_A_address, HE1_q_b[4]_clock_0, , , );
|
| 8529 |
|
|
HE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8530 |
|
|
HE1_q_b[4]_PORT_B_address_reg = DFFE(HE1_q_b[4]_PORT_B_address, HE1_q_b[4]_clock_0, , , );
|
| 8531 |
|
|
HE1_q_b[4]_PORT_A_write_enable = GND;
|
| 8532 |
|
|
HE1_q_b[4]_PORT_A_write_enable_reg = DFFE(HE1_q_b[4]_PORT_A_write_enable, HE1_q_b[4]_clock_0, , , );
|
| 8533 |
|
|
HE1_q_b[4]_PORT_B_write_enable = WB2L2;
|
| 8534 |
|
|
HE1_q_b[4]_PORT_B_write_enable_reg = DFFE(HE1_q_b[4]_PORT_B_write_enable, HE1_q_b[4]_clock_0, , , );
|
| 8535 |
|
|
HE1_q_b[4]_clock_0 = E1__clk0;
|
| 8536 |
|
|
HE1_q_b[4]_PORT_B_data_out = MEMORY(HE1_q_b[4]_PORT_A_data_in_reg, HE1_q_b[4]_PORT_B_data_in_reg, HE1_q_b[4]_PORT_A_address_reg, HE1_q_b[4]_PORT_B_address_reg, HE1_q_b[4]_PORT_A_write_enable_reg, HE1_q_b[4]_PORT_B_write_enable_reg, , , HE1_q_b[4]_clock_0, , , , , );
|
| 8537 |
|
|
HE1_q_b[4] = HE1_q_b[4]_PORT_B_data_out[0];
|
| 8538 |
|
|
|
| 8539 |
|
|
|
| 8540 |
|
|
--F1_dout_0_0_a3_6_5_14_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_14_a[0]
|
| 8541 |
|
|
--operation mode is normal
|
| 8542 |
|
|
|
| 8543 |
|
|
F1_dout_0_0_a3_6_5_14_a[0] = sys_rst & !AB1_r32_o_11 & !AB1_r32_o_28 & AB1_r32_o_1;
|
| 8544 |
|
|
|
| 8545 |
|
|
|
| 8546 |
|
|
--F1_dout_0_0_a3_6_3[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_3[0]
|
| 8547 |
|
|
--operation mode is normal
|
| 8548 |
|
|
|
| 8549 |
|
|
F1_dout_0_0_a3_6_3[0] = JC1_dmem_ctl_o_1 & !JC1_dmem_ctl_o_0 & JC1_dmem_ctl_o_2 & AB1_r32_o_2;
|
| 8550 |
|
|
|
| 8551 |
|
|
|
| 8552 |
|
|
--M1_ua_state_2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state_2
|
| 8553 |
|
|
--operation mode is normal
|
| 8554 |
|
|
|
| 8555 |
|
|
M1_ua_state_2_lut_out = M1_ua_state_2 & !M1_clk_ctr_equ15_0_a2 # !M1_ua_state_2 & M1_ua_state[2] & !M1_ua_state_ns_0_a[2] & M1_clk_ctr_equ15_0_a2;
|
| 8556 |
|
|
M1_ua_state_2 = DFFEAS(M1_ua_state_2_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 8557 |
|
|
|
| 8558 |
|
|
|
| 8559 |
|
|
--M1_clk_ctr_equ15_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_equ15_0_a2
|
| 8560 |
|
|
--operation mode is normal
|
| 8561 |
|
|
|
| 8562 |
|
|
M1_clk_ctr_equ15_0_a2 = M1_clk_ctr_0 & M1_clk_ctr_equ15_0_a2_a & M1_un1_clk_ctr_equ0_0_a2 & M1_un1_clk_ctr_equ0_0_a2_0;
|
| 8563 |
|
|
|
| 8564 |
|
|
|
| 8565 |
|
|
--TB1_dout_1_3 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_3
|
| 8566 |
|
|
--operation mode is normal
|
| 8567 |
|
|
|
| 8568 |
|
|
TB1_dout_1_3 = TB1_dout21 & CB1_dout_2_3 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_3 # !TB1_dout22 & CB1_dout_2_19;
|
| 8569 |
|
|
|
| 8570 |
|
|
|
| 8571 |
|
|
--GE1_q_a[3] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[3]
|
| 8572 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8573 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8574 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8575 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8576 |
|
|
GE1_q_a[3]_PORT_A_data_in = ~GND;
|
| 8577 |
|
|
GE1_q_a[3]_PORT_A_data_in_reg = DFFE(GE1_q_a[3]_PORT_A_data_in, GE1_q_a[3]_clock_0, , , );
|
| 8578 |
|
|
GE1_q_a[3]_PORT_B_data_in = CB1_dout_2_3;
|
| 8579 |
|
|
GE1_q_a[3]_PORT_B_data_in_reg = DFFE(GE1_q_a[3]_PORT_B_data_in, GE1_q_a[3]_clock_0, , , );
|
| 8580 |
|
|
GE1_q_a[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8581 |
|
|
GE1_q_a[3]_PORT_A_address_reg = DFFE(GE1_q_a[3]_PORT_A_address, GE1_q_a[3]_clock_0, , , );
|
| 8582 |
|
|
GE1_q_a[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8583 |
|
|
GE1_q_a[3]_PORT_B_address_reg = DFFE(GE1_q_a[3]_PORT_B_address, GE1_q_a[3]_clock_0, , , );
|
| 8584 |
|
|
GE1_q_a[3]_PORT_A_write_enable = GND;
|
| 8585 |
|
|
GE1_q_a[3]_PORT_A_write_enable_reg = DFFE(GE1_q_a[3]_PORT_A_write_enable, GE1_q_a[3]_clock_0, , , );
|
| 8586 |
|
|
GE1_q_a[3]_PORT_B_write_enable = WB1L2;
|
| 8587 |
|
|
GE1_q_a[3]_PORT_B_write_enable_reg = DFFE(GE1_q_a[3]_PORT_B_write_enable, GE1_q_a[3]_clock_0, , , );
|
| 8588 |
|
|
GE1_q_a[3]_clock_0 = E1__clk0;
|
| 8589 |
|
|
GE1_q_a[3]_PORT_A_data_out = MEMORY(GE1_q_a[3]_PORT_A_data_in_reg, GE1_q_a[3]_PORT_B_data_in_reg, GE1_q_a[3]_PORT_A_address_reg, GE1_q_a[3]_PORT_B_address_reg, GE1_q_a[3]_PORT_A_write_enable_reg, GE1_q_a[3]_PORT_B_write_enable_reg, , , GE1_q_a[3]_clock_0, , , , , );
|
| 8590 |
|
|
GE1_q_a[3] = GE1_q_a[3]_PORT_A_data_out[0];
|
| 8591 |
|
|
|
| 8592 |
|
|
--GE1_q_b[3] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[3]
|
| 8593 |
|
|
GE1_q_b[3]_PORT_A_data_in = ~GND;
|
| 8594 |
|
|
GE1_q_b[3]_PORT_A_data_in_reg = DFFE(GE1_q_b[3]_PORT_A_data_in, GE1_q_b[3]_clock_0, , , );
|
| 8595 |
|
|
GE1_q_b[3]_PORT_B_data_in = CB1_dout_2_3;
|
| 8596 |
|
|
GE1_q_b[3]_PORT_B_data_in_reg = DFFE(GE1_q_b[3]_PORT_B_data_in, GE1_q_b[3]_clock_0, , , );
|
| 8597 |
|
|
GE1_q_b[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8598 |
|
|
GE1_q_b[3]_PORT_A_address_reg = DFFE(GE1_q_b[3]_PORT_A_address, GE1_q_b[3]_clock_0, , , );
|
| 8599 |
|
|
GE1_q_b[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8600 |
|
|
GE1_q_b[3]_PORT_B_address_reg = DFFE(GE1_q_b[3]_PORT_B_address, GE1_q_b[3]_clock_0, , , );
|
| 8601 |
|
|
GE1_q_b[3]_PORT_A_write_enable = GND;
|
| 8602 |
|
|
GE1_q_b[3]_PORT_A_write_enable_reg = DFFE(GE1_q_b[3]_PORT_A_write_enable, GE1_q_b[3]_clock_0, , , );
|
| 8603 |
|
|
GE1_q_b[3]_PORT_B_write_enable = WB1L2;
|
| 8604 |
|
|
GE1_q_b[3]_PORT_B_write_enable_reg = DFFE(GE1_q_b[3]_PORT_B_write_enable, GE1_q_b[3]_clock_0, , , );
|
| 8605 |
|
|
GE1_q_b[3]_clock_0 = E1__clk0;
|
| 8606 |
|
|
GE1_q_b[3]_PORT_B_data_out = MEMORY(GE1_q_b[3]_PORT_A_data_in_reg, GE1_q_b[3]_PORT_B_data_in_reg, GE1_q_b[3]_PORT_A_address_reg, GE1_q_b[3]_PORT_B_address_reg, GE1_q_b[3]_PORT_A_write_enable_reg, GE1_q_b[3]_PORT_B_write_enable_reg, , , GE1_q_b[3]_clock_0, , , , , );
|
| 8607 |
|
|
GE1_q_b[3] = GE1_q_b[3]_PORT_B_data_out[0];
|
| 8608 |
|
|
|
| 8609 |
|
|
|
| 8610 |
|
|
--HE1_q_a[3] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[3]
|
| 8611 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8612 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8613 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8614 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8615 |
|
|
HE1_q_a[3]_PORT_A_data_in = ~GND;
|
| 8616 |
|
|
HE1_q_a[3]_PORT_A_data_in_reg = DFFE(HE1_q_a[3]_PORT_A_data_in, HE1_q_a[3]_clock_0, , , );
|
| 8617 |
|
|
HE1_q_a[3]_PORT_B_data_in = TB1_dout_1_x_3;
|
| 8618 |
|
|
HE1_q_a[3]_PORT_B_data_in_reg = DFFE(HE1_q_a[3]_PORT_B_data_in, HE1_q_a[3]_clock_0, , , );
|
| 8619 |
|
|
HE1_q_a[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8620 |
|
|
HE1_q_a[3]_PORT_A_address_reg = DFFE(HE1_q_a[3]_PORT_A_address, HE1_q_a[3]_clock_0, , , );
|
| 8621 |
|
|
HE1_q_a[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8622 |
|
|
HE1_q_a[3]_PORT_B_address_reg = DFFE(HE1_q_a[3]_PORT_B_address, HE1_q_a[3]_clock_0, , , );
|
| 8623 |
|
|
HE1_q_a[3]_PORT_A_write_enable = GND;
|
| 8624 |
|
|
HE1_q_a[3]_PORT_A_write_enable_reg = DFFE(HE1_q_a[3]_PORT_A_write_enable, HE1_q_a[3]_clock_0, , , );
|
| 8625 |
|
|
HE1_q_a[3]_PORT_B_write_enable = WB2L2;
|
| 8626 |
|
|
HE1_q_a[3]_PORT_B_write_enable_reg = DFFE(HE1_q_a[3]_PORT_B_write_enable, HE1_q_a[3]_clock_0, , , );
|
| 8627 |
|
|
HE1_q_a[3]_clock_0 = E1__clk0;
|
| 8628 |
|
|
HE1_q_a[3]_PORT_A_data_out = MEMORY(HE1_q_a[3]_PORT_A_data_in_reg, HE1_q_a[3]_PORT_B_data_in_reg, HE1_q_a[3]_PORT_A_address_reg, HE1_q_a[3]_PORT_B_address_reg, HE1_q_a[3]_PORT_A_write_enable_reg, HE1_q_a[3]_PORT_B_write_enable_reg, , , HE1_q_a[3]_clock_0, , , , , );
|
| 8629 |
|
|
HE1_q_a[3] = HE1_q_a[3]_PORT_A_data_out[0];
|
| 8630 |
|
|
|
| 8631 |
|
|
--HE1_q_b[3] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[3]
|
| 8632 |
|
|
HE1_q_b[3]_PORT_A_data_in = ~GND;
|
| 8633 |
|
|
HE1_q_b[3]_PORT_A_data_in_reg = DFFE(HE1_q_b[3]_PORT_A_data_in, HE1_q_b[3]_clock_0, , , );
|
| 8634 |
|
|
HE1_q_b[3]_PORT_B_data_in = TB1_dout_1_x_3;
|
| 8635 |
|
|
HE1_q_b[3]_PORT_B_data_in_reg = DFFE(HE1_q_b[3]_PORT_B_data_in, HE1_q_b[3]_clock_0, , , );
|
| 8636 |
|
|
HE1_q_b[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8637 |
|
|
HE1_q_b[3]_PORT_A_address_reg = DFFE(HE1_q_b[3]_PORT_A_address, HE1_q_b[3]_clock_0, , , );
|
| 8638 |
|
|
HE1_q_b[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8639 |
|
|
HE1_q_b[3]_PORT_B_address_reg = DFFE(HE1_q_b[3]_PORT_B_address, HE1_q_b[3]_clock_0, , , );
|
| 8640 |
|
|
HE1_q_b[3]_PORT_A_write_enable = GND;
|
| 8641 |
|
|
HE1_q_b[3]_PORT_A_write_enable_reg = DFFE(HE1_q_b[3]_PORT_A_write_enable, HE1_q_b[3]_clock_0, , , );
|
| 8642 |
|
|
HE1_q_b[3]_PORT_B_write_enable = WB2L2;
|
| 8643 |
|
|
HE1_q_b[3]_PORT_B_write_enable_reg = DFFE(HE1_q_b[3]_PORT_B_write_enable, HE1_q_b[3]_clock_0, , , );
|
| 8644 |
|
|
HE1_q_b[3]_clock_0 = E1__clk0;
|
| 8645 |
|
|
HE1_q_b[3]_PORT_B_data_out = MEMORY(HE1_q_b[3]_PORT_A_data_in_reg, HE1_q_b[3]_PORT_B_data_in_reg, HE1_q_b[3]_PORT_A_address_reg, HE1_q_b[3]_PORT_B_address_reg, HE1_q_b[3]_PORT_A_write_enable_reg, HE1_q_b[3]_PORT_B_write_enable_reg, , , HE1_q_b[3]_clock_0, , , , , );
|
| 8646 |
|
|
HE1_q_b[3] = HE1_q_b[3]_PORT_B_data_out[0];
|
| 8647 |
|
|
|
| 8648 |
|
|
|
| 8649 |
|
|
--KE1_q_a[3] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[3]
|
| 8650 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8651 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8652 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8653 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8654 |
|
|
KE1_q_a[3]_PORT_A_data_in = ~GND;
|
| 8655 |
|
|
KE1_q_a[3]_PORT_A_data_in_reg = DFFE(KE1_q_a[3]_PORT_A_data_in, KE1_q_a[3]_clock_0, , , );
|
| 8656 |
|
|
KE1_q_a[3]_PORT_B_data_in = TB1_dout_1_2_3;
|
| 8657 |
|
|
KE1_q_a[3]_PORT_B_data_in_reg = DFFE(KE1_q_a[3]_PORT_B_data_in, KE1_q_a[3]_clock_0, , , );
|
| 8658 |
|
|
KE1_q_a[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8659 |
|
|
KE1_q_a[3]_PORT_A_address_reg = DFFE(KE1_q_a[3]_PORT_A_address, KE1_q_a[3]_clock_0, , , );
|
| 8660 |
|
|
KE1_q_a[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8661 |
|
|
KE1_q_a[3]_PORT_B_address_reg = DFFE(KE1_q_a[3]_PORT_B_address, KE1_q_a[3]_clock_0, , , );
|
| 8662 |
|
|
KE1_q_a[3]_PORT_A_write_enable = GND;
|
| 8663 |
|
|
KE1_q_a[3]_PORT_A_write_enable_reg = DFFE(KE1_q_a[3]_PORT_A_write_enable, KE1_q_a[3]_clock_0, , , );
|
| 8664 |
|
|
KE1_q_a[3]_PORT_B_write_enable = WB4L2;
|
| 8665 |
|
|
KE1_q_a[3]_PORT_B_write_enable_reg = DFFE(KE1_q_a[3]_PORT_B_write_enable, KE1_q_a[3]_clock_0, , , );
|
| 8666 |
|
|
KE1_q_a[3]_clock_0 = E1__clk0;
|
| 8667 |
|
|
KE1_q_a[3]_PORT_A_data_out = MEMORY(KE1_q_a[3]_PORT_A_data_in_reg, KE1_q_a[3]_PORT_B_data_in_reg, KE1_q_a[3]_PORT_A_address_reg, KE1_q_a[3]_PORT_B_address_reg, KE1_q_a[3]_PORT_A_write_enable_reg, KE1_q_a[3]_PORT_B_write_enable_reg, , , KE1_q_a[3]_clock_0, , , , , );
|
| 8668 |
|
|
KE1_q_a[3] = KE1_q_a[3]_PORT_A_data_out[0];
|
| 8669 |
|
|
|
| 8670 |
|
|
--KE1_q_b[3] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[3]
|
| 8671 |
|
|
KE1_q_b[3]_PORT_A_data_in = ~GND;
|
| 8672 |
|
|
KE1_q_b[3]_PORT_A_data_in_reg = DFFE(KE1_q_b[3]_PORT_A_data_in, KE1_q_b[3]_clock_0, , , );
|
| 8673 |
|
|
KE1_q_b[3]_PORT_B_data_in = TB1_dout_1_2_3;
|
| 8674 |
|
|
KE1_q_b[3]_PORT_B_data_in_reg = DFFE(KE1_q_b[3]_PORT_B_data_in, KE1_q_b[3]_clock_0, , , );
|
| 8675 |
|
|
KE1_q_b[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8676 |
|
|
KE1_q_b[3]_PORT_A_address_reg = DFFE(KE1_q_b[3]_PORT_A_address, KE1_q_b[3]_clock_0, , , );
|
| 8677 |
|
|
KE1_q_b[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8678 |
|
|
KE1_q_b[3]_PORT_B_address_reg = DFFE(KE1_q_b[3]_PORT_B_address, KE1_q_b[3]_clock_0, , , );
|
| 8679 |
|
|
KE1_q_b[3]_PORT_A_write_enable = GND;
|
| 8680 |
|
|
KE1_q_b[3]_PORT_A_write_enable_reg = DFFE(KE1_q_b[3]_PORT_A_write_enable, KE1_q_b[3]_clock_0, , , );
|
| 8681 |
|
|
KE1_q_b[3]_PORT_B_write_enable = WB4L2;
|
| 8682 |
|
|
KE1_q_b[3]_PORT_B_write_enable_reg = DFFE(KE1_q_b[3]_PORT_B_write_enable, KE1_q_b[3]_clock_0, , , );
|
| 8683 |
|
|
KE1_q_b[3]_clock_0 = E1__clk0;
|
| 8684 |
|
|
KE1_q_b[3]_PORT_B_data_out = MEMORY(KE1_q_b[3]_PORT_A_data_in_reg, KE1_q_b[3]_PORT_B_data_in_reg, KE1_q_b[3]_PORT_A_address_reg, KE1_q_b[3]_PORT_B_address_reg, KE1_q_b[3]_PORT_A_write_enable_reg, KE1_q_b[3]_PORT_B_write_enable_reg, , , KE1_q_b[3]_clock_0, , , , , );
|
| 8685 |
|
|
KE1_q_b[3] = KE1_q_b[3]_PORT_B_data_out[0];
|
| 8686 |
|
|
|
| 8687 |
|
|
|
| 8688 |
|
|
--TB1_dout_1_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2
|
| 8689 |
|
|
--operation mode is normal
|
| 8690 |
|
|
|
| 8691 |
|
|
TB1_dout_1_2 = TB1_dout21 & CB1_dout_2_2 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_2 # !TB1_dout22 & CB1_dout_2_18;
|
| 8692 |
|
|
|
| 8693 |
|
|
|
| 8694 |
|
|
--GE1_q_a[2] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[2]
|
| 8695 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8696 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8697 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8698 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8699 |
|
|
GE1_q_a[2]_PORT_A_data_in = ~GND;
|
| 8700 |
|
|
GE1_q_a[2]_PORT_A_data_in_reg = DFFE(GE1_q_a[2]_PORT_A_data_in, GE1_q_a[2]_clock_0, , , );
|
| 8701 |
|
|
GE1_q_a[2]_PORT_B_data_in = CB1_dout_2_2;
|
| 8702 |
|
|
GE1_q_a[2]_PORT_B_data_in_reg = DFFE(GE1_q_a[2]_PORT_B_data_in, GE1_q_a[2]_clock_0, , , );
|
| 8703 |
|
|
GE1_q_a[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8704 |
|
|
GE1_q_a[2]_PORT_A_address_reg = DFFE(GE1_q_a[2]_PORT_A_address, GE1_q_a[2]_clock_0, , , );
|
| 8705 |
|
|
GE1_q_a[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8706 |
|
|
GE1_q_a[2]_PORT_B_address_reg = DFFE(GE1_q_a[2]_PORT_B_address, GE1_q_a[2]_clock_0, , , );
|
| 8707 |
|
|
GE1_q_a[2]_PORT_A_write_enable = GND;
|
| 8708 |
|
|
GE1_q_a[2]_PORT_A_write_enable_reg = DFFE(GE1_q_a[2]_PORT_A_write_enable, GE1_q_a[2]_clock_0, , , );
|
| 8709 |
|
|
GE1_q_a[2]_PORT_B_write_enable = WB1L2;
|
| 8710 |
|
|
GE1_q_a[2]_PORT_B_write_enable_reg = DFFE(GE1_q_a[2]_PORT_B_write_enable, GE1_q_a[2]_clock_0, , , );
|
| 8711 |
|
|
GE1_q_a[2]_clock_0 = E1__clk0;
|
| 8712 |
|
|
GE1_q_a[2]_PORT_A_data_out = MEMORY(GE1_q_a[2]_PORT_A_data_in_reg, GE1_q_a[2]_PORT_B_data_in_reg, GE1_q_a[2]_PORT_A_address_reg, GE1_q_a[2]_PORT_B_address_reg, GE1_q_a[2]_PORT_A_write_enable_reg, GE1_q_a[2]_PORT_B_write_enable_reg, , , GE1_q_a[2]_clock_0, , , , , );
|
| 8713 |
|
|
GE1_q_a[2] = GE1_q_a[2]_PORT_A_data_out[0];
|
| 8714 |
|
|
|
| 8715 |
|
|
--GE1_q_b[2] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[2]
|
| 8716 |
|
|
GE1_q_b[2]_PORT_A_data_in = ~GND;
|
| 8717 |
|
|
GE1_q_b[2]_PORT_A_data_in_reg = DFFE(GE1_q_b[2]_PORT_A_data_in, GE1_q_b[2]_clock_0, , , );
|
| 8718 |
|
|
GE1_q_b[2]_PORT_B_data_in = CB1_dout_2_2;
|
| 8719 |
|
|
GE1_q_b[2]_PORT_B_data_in_reg = DFFE(GE1_q_b[2]_PORT_B_data_in, GE1_q_b[2]_clock_0, , , );
|
| 8720 |
|
|
GE1_q_b[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8721 |
|
|
GE1_q_b[2]_PORT_A_address_reg = DFFE(GE1_q_b[2]_PORT_A_address, GE1_q_b[2]_clock_0, , , );
|
| 8722 |
|
|
GE1_q_b[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8723 |
|
|
GE1_q_b[2]_PORT_B_address_reg = DFFE(GE1_q_b[2]_PORT_B_address, GE1_q_b[2]_clock_0, , , );
|
| 8724 |
|
|
GE1_q_b[2]_PORT_A_write_enable = GND;
|
| 8725 |
|
|
GE1_q_b[2]_PORT_A_write_enable_reg = DFFE(GE1_q_b[2]_PORT_A_write_enable, GE1_q_b[2]_clock_0, , , );
|
| 8726 |
|
|
GE1_q_b[2]_PORT_B_write_enable = WB1L2;
|
| 8727 |
|
|
GE1_q_b[2]_PORT_B_write_enable_reg = DFFE(GE1_q_b[2]_PORT_B_write_enable, GE1_q_b[2]_clock_0, , , );
|
| 8728 |
|
|
GE1_q_b[2]_clock_0 = E1__clk0;
|
| 8729 |
|
|
GE1_q_b[2]_PORT_B_data_out = MEMORY(GE1_q_b[2]_PORT_A_data_in_reg, GE1_q_b[2]_PORT_B_data_in_reg, GE1_q_b[2]_PORT_A_address_reg, GE1_q_b[2]_PORT_B_address_reg, GE1_q_b[2]_PORT_A_write_enable_reg, GE1_q_b[2]_PORT_B_write_enable_reg, , , GE1_q_b[2]_clock_0, , , , , );
|
| 8730 |
|
|
GE1_q_b[2] = GE1_q_b[2]_PORT_B_data_out[0];
|
| 8731 |
|
|
|
| 8732 |
|
|
|
| 8733 |
|
|
--KE1_q_a[2] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[2]
|
| 8734 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8735 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8736 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8737 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8738 |
|
|
KE1_q_a[2]_PORT_A_data_in = ~GND;
|
| 8739 |
|
|
KE1_q_a[2]_PORT_A_data_in_reg = DFFE(KE1_q_a[2]_PORT_A_data_in, KE1_q_a[2]_clock_0, , , );
|
| 8740 |
|
|
KE1_q_a[2]_PORT_B_data_in = TB1_dout_1_2_2;
|
| 8741 |
|
|
KE1_q_a[2]_PORT_B_data_in_reg = DFFE(KE1_q_a[2]_PORT_B_data_in, KE1_q_a[2]_clock_0, , , );
|
| 8742 |
|
|
KE1_q_a[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8743 |
|
|
KE1_q_a[2]_PORT_A_address_reg = DFFE(KE1_q_a[2]_PORT_A_address, KE1_q_a[2]_clock_0, , , );
|
| 8744 |
|
|
KE1_q_a[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8745 |
|
|
KE1_q_a[2]_PORT_B_address_reg = DFFE(KE1_q_a[2]_PORT_B_address, KE1_q_a[2]_clock_0, , , );
|
| 8746 |
|
|
KE1_q_a[2]_PORT_A_write_enable = GND;
|
| 8747 |
|
|
KE1_q_a[2]_PORT_A_write_enable_reg = DFFE(KE1_q_a[2]_PORT_A_write_enable, KE1_q_a[2]_clock_0, , , );
|
| 8748 |
|
|
KE1_q_a[2]_PORT_B_write_enable = WB4L2;
|
| 8749 |
|
|
KE1_q_a[2]_PORT_B_write_enable_reg = DFFE(KE1_q_a[2]_PORT_B_write_enable, KE1_q_a[2]_clock_0, , , );
|
| 8750 |
|
|
KE1_q_a[2]_clock_0 = E1__clk0;
|
| 8751 |
|
|
KE1_q_a[2]_PORT_A_data_out = MEMORY(KE1_q_a[2]_PORT_A_data_in_reg, KE1_q_a[2]_PORT_B_data_in_reg, KE1_q_a[2]_PORT_A_address_reg, KE1_q_a[2]_PORT_B_address_reg, KE1_q_a[2]_PORT_A_write_enable_reg, KE1_q_a[2]_PORT_B_write_enable_reg, , , KE1_q_a[2]_clock_0, , , , , );
|
| 8752 |
|
|
KE1_q_a[2] = KE1_q_a[2]_PORT_A_data_out[0];
|
| 8753 |
|
|
|
| 8754 |
|
|
--KE1_q_b[2] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[2]
|
| 8755 |
|
|
KE1_q_b[2]_PORT_A_data_in = ~GND;
|
| 8756 |
|
|
KE1_q_b[2]_PORT_A_data_in_reg = DFFE(KE1_q_b[2]_PORT_A_data_in, KE1_q_b[2]_clock_0, , , );
|
| 8757 |
|
|
KE1_q_b[2]_PORT_B_data_in = TB1_dout_1_2_2;
|
| 8758 |
|
|
KE1_q_b[2]_PORT_B_data_in_reg = DFFE(KE1_q_b[2]_PORT_B_data_in, KE1_q_b[2]_clock_0, , , );
|
| 8759 |
|
|
KE1_q_b[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8760 |
|
|
KE1_q_b[2]_PORT_A_address_reg = DFFE(KE1_q_b[2]_PORT_A_address, KE1_q_b[2]_clock_0, , , );
|
| 8761 |
|
|
KE1_q_b[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8762 |
|
|
KE1_q_b[2]_PORT_B_address_reg = DFFE(KE1_q_b[2]_PORT_B_address, KE1_q_b[2]_clock_0, , , );
|
| 8763 |
|
|
KE1_q_b[2]_PORT_A_write_enable = GND;
|
| 8764 |
|
|
KE1_q_b[2]_PORT_A_write_enable_reg = DFFE(KE1_q_b[2]_PORT_A_write_enable, KE1_q_b[2]_clock_0, , , );
|
| 8765 |
|
|
KE1_q_b[2]_PORT_B_write_enable = WB4L2;
|
| 8766 |
|
|
KE1_q_b[2]_PORT_B_write_enable_reg = DFFE(KE1_q_b[2]_PORT_B_write_enable, KE1_q_b[2]_clock_0, , , );
|
| 8767 |
|
|
KE1_q_b[2]_clock_0 = E1__clk0;
|
| 8768 |
|
|
KE1_q_b[2]_PORT_B_data_out = MEMORY(KE1_q_b[2]_PORT_A_data_in_reg, KE1_q_b[2]_PORT_B_data_in_reg, KE1_q_b[2]_PORT_A_address_reg, KE1_q_b[2]_PORT_B_address_reg, KE1_q_b[2]_PORT_A_write_enable_reg, KE1_q_b[2]_PORT_B_write_enable_reg, , , KE1_q_b[2]_clock_0, , , , , );
|
| 8769 |
|
|
KE1_q_b[2] = KE1_q_b[2]_PORT_B_data_out[0];
|
| 8770 |
|
|
|
| 8771 |
|
|
|
| 8772 |
|
|
--HE1_q_a[2] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[2]
|
| 8773 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8774 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8775 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8776 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8777 |
|
|
HE1_q_a[2]_PORT_A_data_in = ~GND;
|
| 8778 |
|
|
HE1_q_a[2]_PORT_A_data_in_reg = DFFE(HE1_q_a[2]_PORT_A_data_in, HE1_q_a[2]_clock_0, , , );
|
| 8779 |
|
|
HE1_q_a[2]_PORT_B_data_in = TB1_dout_1_x_2;
|
| 8780 |
|
|
HE1_q_a[2]_PORT_B_data_in_reg = DFFE(HE1_q_a[2]_PORT_B_data_in, HE1_q_a[2]_clock_0, , , );
|
| 8781 |
|
|
HE1_q_a[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8782 |
|
|
HE1_q_a[2]_PORT_A_address_reg = DFFE(HE1_q_a[2]_PORT_A_address, HE1_q_a[2]_clock_0, , , );
|
| 8783 |
|
|
HE1_q_a[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8784 |
|
|
HE1_q_a[2]_PORT_B_address_reg = DFFE(HE1_q_a[2]_PORT_B_address, HE1_q_a[2]_clock_0, , , );
|
| 8785 |
|
|
HE1_q_a[2]_PORT_A_write_enable = GND;
|
| 8786 |
|
|
HE1_q_a[2]_PORT_A_write_enable_reg = DFFE(HE1_q_a[2]_PORT_A_write_enable, HE1_q_a[2]_clock_0, , , );
|
| 8787 |
|
|
HE1_q_a[2]_PORT_B_write_enable = WB2L2;
|
| 8788 |
|
|
HE1_q_a[2]_PORT_B_write_enable_reg = DFFE(HE1_q_a[2]_PORT_B_write_enable, HE1_q_a[2]_clock_0, , , );
|
| 8789 |
|
|
HE1_q_a[2]_clock_0 = E1__clk0;
|
| 8790 |
|
|
HE1_q_a[2]_PORT_A_data_out = MEMORY(HE1_q_a[2]_PORT_A_data_in_reg, HE1_q_a[2]_PORT_B_data_in_reg, HE1_q_a[2]_PORT_A_address_reg, HE1_q_a[2]_PORT_B_address_reg, HE1_q_a[2]_PORT_A_write_enable_reg, HE1_q_a[2]_PORT_B_write_enable_reg, , , HE1_q_a[2]_clock_0, , , , , );
|
| 8791 |
|
|
HE1_q_a[2] = HE1_q_a[2]_PORT_A_data_out[0];
|
| 8792 |
|
|
|
| 8793 |
|
|
--HE1_q_b[2] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[2]
|
| 8794 |
|
|
HE1_q_b[2]_PORT_A_data_in = ~GND;
|
| 8795 |
|
|
HE1_q_b[2]_PORT_A_data_in_reg = DFFE(HE1_q_b[2]_PORT_A_data_in, HE1_q_b[2]_clock_0, , , );
|
| 8796 |
|
|
HE1_q_b[2]_PORT_B_data_in = TB1_dout_1_x_2;
|
| 8797 |
|
|
HE1_q_b[2]_PORT_B_data_in_reg = DFFE(HE1_q_b[2]_PORT_B_data_in, HE1_q_b[2]_clock_0, , , );
|
| 8798 |
|
|
HE1_q_b[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8799 |
|
|
HE1_q_b[2]_PORT_A_address_reg = DFFE(HE1_q_b[2]_PORT_A_address, HE1_q_b[2]_clock_0, , , );
|
| 8800 |
|
|
HE1_q_b[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8801 |
|
|
HE1_q_b[2]_PORT_B_address_reg = DFFE(HE1_q_b[2]_PORT_B_address, HE1_q_b[2]_clock_0, , , );
|
| 8802 |
|
|
HE1_q_b[2]_PORT_A_write_enable = GND;
|
| 8803 |
|
|
HE1_q_b[2]_PORT_A_write_enable_reg = DFFE(HE1_q_b[2]_PORT_A_write_enable, HE1_q_b[2]_clock_0, , , );
|
| 8804 |
|
|
HE1_q_b[2]_PORT_B_write_enable = WB2L2;
|
| 8805 |
|
|
HE1_q_b[2]_PORT_B_write_enable_reg = DFFE(HE1_q_b[2]_PORT_B_write_enable, HE1_q_b[2]_clock_0, , , );
|
| 8806 |
|
|
HE1_q_b[2]_clock_0 = E1__clk0;
|
| 8807 |
|
|
HE1_q_b[2]_PORT_B_data_out = MEMORY(HE1_q_b[2]_PORT_A_data_in_reg, HE1_q_b[2]_PORT_B_data_in_reg, HE1_q_b[2]_PORT_A_address_reg, HE1_q_b[2]_PORT_B_address_reg, HE1_q_b[2]_PORT_A_write_enable_reg, HE1_q_b[2]_PORT_B_write_enable_reg, , , HE1_q_b[2]_clock_0, , , , , );
|
| 8808 |
|
|
HE1_q_b[2] = HE1_q_b[2]_PORT_B_data_out[0];
|
| 8809 |
|
|
|
| 8810 |
|
|
|
| 8811 |
|
|
--TB1_dout_1_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_1
|
| 8812 |
|
|
--operation mode is normal
|
| 8813 |
|
|
|
| 8814 |
|
|
TB1_dout_1_1 = TB1_dout21 & CB1_dout_2_1 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_1 # !TB1_dout22 & CB1_dout_2_17;
|
| 8815 |
|
|
|
| 8816 |
|
|
|
| 8817 |
|
|
--GE1_q_a[1] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[1]
|
| 8818 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8819 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8820 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8821 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8822 |
|
|
GE1_q_a[1]_PORT_A_data_in = ~GND;
|
| 8823 |
|
|
GE1_q_a[1]_PORT_A_data_in_reg = DFFE(GE1_q_a[1]_PORT_A_data_in, GE1_q_a[1]_clock_0, , , );
|
| 8824 |
|
|
GE1_q_a[1]_PORT_B_data_in = CB1_dout_2_1;
|
| 8825 |
|
|
GE1_q_a[1]_PORT_B_data_in_reg = DFFE(GE1_q_a[1]_PORT_B_data_in, GE1_q_a[1]_clock_0, , , );
|
| 8826 |
|
|
GE1_q_a[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8827 |
|
|
GE1_q_a[1]_PORT_A_address_reg = DFFE(GE1_q_a[1]_PORT_A_address, GE1_q_a[1]_clock_0, , , );
|
| 8828 |
|
|
GE1_q_a[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8829 |
|
|
GE1_q_a[1]_PORT_B_address_reg = DFFE(GE1_q_a[1]_PORT_B_address, GE1_q_a[1]_clock_0, , , );
|
| 8830 |
|
|
GE1_q_a[1]_PORT_A_write_enable = GND;
|
| 8831 |
|
|
GE1_q_a[1]_PORT_A_write_enable_reg = DFFE(GE1_q_a[1]_PORT_A_write_enable, GE1_q_a[1]_clock_0, , , );
|
| 8832 |
|
|
GE1_q_a[1]_PORT_B_write_enable = WB1L2;
|
| 8833 |
|
|
GE1_q_a[1]_PORT_B_write_enable_reg = DFFE(GE1_q_a[1]_PORT_B_write_enable, GE1_q_a[1]_clock_0, , , );
|
| 8834 |
|
|
GE1_q_a[1]_clock_0 = E1__clk0;
|
| 8835 |
|
|
GE1_q_a[1]_PORT_A_data_out = MEMORY(GE1_q_a[1]_PORT_A_data_in_reg, GE1_q_a[1]_PORT_B_data_in_reg, GE1_q_a[1]_PORT_A_address_reg, GE1_q_a[1]_PORT_B_address_reg, GE1_q_a[1]_PORT_A_write_enable_reg, GE1_q_a[1]_PORT_B_write_enable_reg, , , GE1_q_a[1]_clock_0, , , , , );
|
| 8836 |
|
|
GE1_q_a[1] = GE1_q_a[1]_PORT_A_data_out[0];
|
| 8837 |
|
|
|
| 8838 |
|
|
--GE1_q_b[1] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[1]
|
| 8839 |
|
|
GE1_q_b[1]_PORT_A_data_in = ~GND;
|
| 8840 |
|
|
GE1_q_b[1]_PORT_A_data_in_reg = DFFE(GE1_q_b[1]_PORT_A_data_in, GE1_q_b[1]_clock_0, , , );
|
| 8841 |
|
|
GE1_q_b[1]_PORT_B_data_in = CB1_dout_2_1;
|
| 8842 |
|
|
GE1_q_b[1]_PORT_B_data_in_reg = DFFE(GE1_q_b[1]_PORT_B_data_in, GE1_q_b[1]_clock_0, , , );
|
| 8843 |
|
|
GE1_q_b[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8844 |
|
|
GE1_q_b[1]_PORT_A_address_reg = DFFE(GE1_q_b[1]_PORT_A_address, GE1_q_b[1]_clock_0, , , );
|
| 8845 |
|
|
GE1_q_b[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8846 |
|
|
GE1_q_b[1]_PORT_B_address_reg = DFFE(GE1_q_b[1]_PORT_B_address, GE1_q_b[1]_clock_0, , , );
|
| 8847 |
|
|
GE1_q_b[1]_PORT_A_write_enable = GND;
|
| 8848 |
|
|
GE1_q_b[1]_PORT_A_write_enable_reg = DFFE(GE1_q_b[1]_PORT_A_write_enable, GE1_q_b[1]_clock_0, , , );
|
| 8849 |
|
|
GE1_q_b[1]_PORT_B_write_enable = WB1L2;
|
| 8850 |
|
|
GE1_q_b[1]_PORT_B_write_enable_reg = DFFE(GE1_q_b[1]_PORT_B_write_enable, GE1_q_b[1]_clock_0, , , );
|
| 8851 |
|
|
GE1_q_b[1]_clock_0 = E1__clk0;
|
| 8852 |
|
|
GE1_q_b[1]_PORT_B_data_out = MEMORY(GE1_q_b[1]_PORT_A_data_in_reg, GE1_q_b[1]_PORT_B_data_in_reg, GE1_q_b[1]_PORT_A_address_reg, GE1_q_b[1]_PORT_B_address_reg, GE1_q_b[1]_PORT_A_write_enable_reg, GE1_q_b[1]_PORT_B_write_enable_reg, , , GE1_q_b[1]_clock_0, , , , , );
|
| 8853 |
|
|
GE1_q_b[1] = GE1_q_b[1]_PORT_B_data_out[0];
|
| 8854 |
|
|
|
| 8855 |
|
|
|
| 8856 |
|
|
--KE1_q_a[1] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[1]
|
| 8857 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8858 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8859 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8860 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8861 |
|
|
KE1_q_a[1]_PORT_A_data_in = ~GND;
|
| 8862 |
|
|
KE1_q_a[1]_PORT_A_data_in_reg = DFFE(KE1_q_a[1]_PORT_A_data_in, KE1_q_a[1]_clock_0, , , );
|
| 8863 |
|
|
KE1_q_a[1]_PORT_B_data_in = TB1_dout_1_2_1;
|
| 8864 |
|
|
KE1_q_a[1]_PORT_B_data_in_reg = DFFE(KE1_q_a[1]_PORT_B_data_in, KE1_q_a[1]_clock_0, , , );
|
| 8865 |
|
|
KE1_q_a[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8866 |
|
|
KE1_q_a[1]_PORT_A_address_reg = DFFE(KE1_q_a[1]_PORT_A_address, KE1_q_a[1]_clock_0, , , );
|
| 8867 |
|
|
KE1_q_a[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8868 |
|
|
KE1_q_a[1]_PORT_B_address_reg = DFFE(KE1_q_a[1]_PORT_B_address, KE1_q_a[1]_clock_0, , , );
|
| 8869 |
|
|
KE1_q_a[1]_PORT_A_write_enable = GND;
|
| 8870 |
|
|
KE1_q_a[1]_PORT_A_write_enable_reg = DFFE(KE1_q_a[1]_PORT_A_write_enable, KE1_q_a[1]_clock_0, , , );
|
| 8871 |
|
|
KE1_q_a[1]_PORT_B_write_enable = WB4L2;
|
| 8872 |
|
|
KE1_q_a[1]_PORT_B_write_enable_reg = DFFE(KE1_q_a[1]_PORT_B_write_enable, KE1_q_a[1]_clock_0, , , );
|
| 8873 |
|
|
KE1_q_a[1]_clock_0 = E1__clk0;
|
| 8874 |
|
|
KE1_q_a[1]_PORT_A_data_out = MEMORY(KE1_q_a[1]_PORT_A_data_in_reg, KE1_q_a[1]_PORT_B_data_in_reg, KE1_q_a[1]_PORT_A_address_reg, KE1_q_a[1]_PORT_B_address_reg, KE1_q_a[1]_PORT_A_write_enable_reg, KE1_q_a[1]_PORT_B_write_enable_reg, , , KE1_q_a[1]_clock_0, , , , , );
|
| 8875 |
|
|
KE1_q_a[1] = KE1_q_a[1]_PORT_A_data_out[0];
|
| 8876 |
|
|
|
| 8877 |
|
|
--KE1_q_b[1] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[1]
|
| 8878 |
|
|
KE1_q_b[1]_PORT_A_data_in = ~GND;
|
| 8879 |
|
|
KE1_q_b[1]_PORT_A_data_in_reg = DFFE(KE1_q_b[1]_PORT_A_data_in, KE1_q_b[1]_clock_0, , , );
|
| 8880 |
|
|
KE1_q_b[1]_PORT_B_data_in = TB1_dout_1_2_1;
|
| 8881 |
|
|
KE1_q_b[1]_PORT_B_data_in_reg = DFFE(KE1_q_b[1]_PORT_B_data_in, KE1_q_b[1]_clock_0, , , );
|
| 8882 |
|
|
KE1_q_b[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8883 |
|
|
KE1_q_b[1]_PORT_A_address_reg = DFFE(KE1_q_b[1]_PORT_A_address, KE1_q_b[1]_clock_0, , , );
|
| 8884 |
|
|
KE1_q_b[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8885 |
|
|
KE1_q_b[1]_PORT_B_address_reg = DFFE(KE1_q_b[1]_PORT_B_address, KE1_q_b[1]_clock_0, , , );
|
| 8886 |
|
|
KE1_q_b[1]_PORT_A_write_enable = GND;
|
| 8887 |
|
|
KE1_q_b[1]_PORT_A_write_enable_reg = DFFE(KE1_q_b[1]_PORT_A_write_enable, KE1_q_b[1]_clock_0, , , );
|
| 8888 |
|
|
KE1_q_b[1]_PORT_B_write_enable = WB4L2;
|
| 8889 |
|
|
KE1_q_b[1]_PORT_B_write_enable_reg = DFFE(KE1_q_b[1]_PORT_B_write_enable, KE1_q_b[1]_clock_0, , , );
|
| 8890 |
|
|
KE1_q_b[1]_clock_0 = E1__clk0;
|
| 8891 |
|
|
KE1_q_b[1]_PORT_B_data_out = MEMORY(KE1_q_b[1]_PORT_A_data_in_reg, KE1_q_b[1]_PORT_B_data_in_reg, KE1_q_b[1]_PORT_A_address_reg, KE1_q_b[1]_PORT_B_address_reg, KE1_q_b[1]_PORT_A_write_enable_reg, KE1_q_b[1]_PORT_B_write_enable_reg, , , KE1_q_b[1]_clock_0, , , , , );
|
| 8892 |
|
|
KE1_q_b[1] = KE1_q_b[1]_PORT_B_data_out[0];
|
| 8893 |
|
|
|
| 8894 |
|
|
|
| 8895 |
|
|
--HE1_q_a[1] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[1]
|
| 8896 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 8897 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 8898 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 8899 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 8900 |
|
|
HE1_q_a[1]_PORT_A_data_in = ~GND;
|
| 8901 |
|
|
HE1_q_a[1]_PORT_A_data_in_reg = DFFE(HE1_q_a[1]_PORT_A_data_in, HE1_q_a[1]_clock_0, , , );
|
| 8902 |
|
|
HE1_q_a[1]_PORT_B_data_in = TB1_dout_1_x_1;
|
| 8903 |
|
|
HE1_q_a[1]_PORT_B_data_in_reg = DFFE(HE1_q_a[1]_PORT_B_data_in, HE1_q_a[1]_clock_0, , , );
|
| 8904 |
|
|
HE1_q_a[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8905 |
|
|
HE1_q_a[1]_PORT_A_address_reg = DFFE(HE1_q_a[1]_PORT_A_address, HE1_q_a[1]_clock_0, , , );
|
| 8906 |
|
|
HE1_q_a[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8907 |
|
|
HE1_q_a[1]_PORT_B_address_reg = DFFE(HE1_q_a[1]_PORT_B_address, HE1_q_a[1]_clock_0, , , );
|
| 8908 |
|
|
HE1_q_a[1]_PORT_A_write_enable = GND;
|
| 8909 |
|
|
HE1_q_a[1]_PORT_A_write_enable_reg = DFFE(HE1_q_a[1]_PORT_A_write_enable, HE1_q_a[1]_clock_0, , , );
|
| 8910 |
|
|
HE1_q_a[1]_PORT_B_write_enable = WB2L2;
|
| 8911 |
|
|
HE1_q_a[1]_PORT_B_write_enable_reg = DFFE(HE1_q_a[1]_PORT_B_write_enable, HE1_q_a[1]_clock_0, , , );
|
| 8912 |
|
|
HE1_q_a[1]_clock_0 = E1__clk0;
|
| 8913 |
|
|
HE1_q_a[1]_PORT_A_data_out = MEMORY(HE1_q_a[1]_PORT_A_data_in_reg, HE1_q_a[1]_PORT_B_data_in_reg, HE1_q_a[1]_PORT_A_address_reg, HE1_q_a[1]_PORT_B_address_reg, HE1_q_a[1]_PORT_A_write_enable_reg, HE1_q_a[1]_PORT_B_write_enable_reg, , , HE1_q_a[1]_clock_0, , , , , );
|
| 8914 |
|
|
HE1_q_a[1] = HE1_q_a[1]_PORT_A_data_out[0];
|
| 8915 |
|
|
|
| 8916 |
|
|
--HE1_q_b[1] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[1]
|
| 8917 |
|
|
HE1_q_b[1]_PORT_A_data_in = ~GND;
|
| 8918 |
|
|
HE1_q_b[1]_PORT_A_data_in_reg = DFFE(HE1_q_b[1]_PORT_A_data_in, HE1_q_b[1]_clock_0, , , );
|
| 8919 |
|
|
HE1_q_b[1]_PORT_B_data_in = TB1_dout_1_x_1;
|
| 8920 |
|
|
HE1_q_b[1]_PORT_B_data_in_reg = DFFE(HE1_q_b[1]_PORT_B_data_in, HE1_q_b[1]_clock_0, , , );
|
| 8921 |
|
|
HE1_q_b[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 8922 |
|
|
HE1_q_b[1]_PORT_A_address_reg = DFFE(HE1_q_b[1]_PORT_A_address, HE1_q_b[1]_clock_0, , , );
|
| 8923 |
|
|
HE1_q_b[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 8924 |
|
|
HE1_q_b[1]_PORT_B_address_reg = DFFE(HE1_q_b[1]_PORT_B_address, HE1_q_b[1]_clock_0, , , );
|
| 8925 |
|
|
HE1_q_b[1]_PORT_A_write_enable = GND;
|
| 8926 |
|
|
HE1_q_b[1]_PORT_A_write_enable_reg = DFFE(HE1_q_b[1]_PORT_A_write_enable, HE1_q_b[1]_clock_0, , , );
|
| 8927 |
|
|
HE1_q_b[1]_PORT_B_write_enable = WB2L2;
|
| 8928 |
|
|
HE1_q_b[1]_PORT_B_write_enable_reg = DFFE(HE1_q_b[1]_PORT_B_write_enable, HE1_q_b[1]_clock_0, , , );
|
| 8929 |
|
|
HE1_q_b[1]_clock_0 = E1__clk0;
|
| 8930 |
|
|
HE1_q_b[1]_PORT_B_data_out = MEMORY(HE1_q_b[1]_PORT_A_data_in_reg, HE1_q_b[1]_PORT_B_data_in_reg, HE1_q_b[1]_PORT_A_address_reg, HE1_q_b[1]_PORT_B_address_reg, HE1_q_b[1]_PORT_A_write_enable_reg, HE1_q_b[1]_PORT_B_write_enable_reg, , , HE1_q_b[1]_clock_0, , , , , );
|
| 8931 |
|
|
HE1_q_b[1] = HE1_q_b[1]_PORT_B_data_out[0];
|
| 8932 |
|
|
|
| 8933 |
|
|
|
| 8934 |
|
|
--UD1_shift_out_80_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[1]
|
| 8935 |
|
|
--operation mode is normal
|
| 8936 |
|
|
|
| 8937 |
|
|
UD1_shift_out_80_a[1] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_4 # !PD1_a_o_1 & !VD1_b_o_iv_2;
|
| 8938 |
|
|
|
| 8939 |
|
|
|
| 8940 |
|
|
--UD1_shift_out_82_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82_a[1]
|
| 8941 |
|
|
--operation mode is normal
|
| 8942 |
|
|
|
| 8943 |
|
|
UD1_shift_out_82_a[1] = PD1_a_o_2 & !VD1_b_o_iv_5 # !PD1_a_o_2 & !VD1_b_o_iv_3;
|
| 8944 |
|
|
|
| 8945 |
|
|
|
| 8946 |
|
|
--UD1_shift_out_41[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_41[1]
|
| 8947 |
|
|
--operation mode is normal
|
| 8948 |
|
|
|
| 8949 |
|
|
UD1_shift_out_41[1] = PD1_a_o_1 & VD1_b_o_iv_31 # !PD1_a_o_1 & UD1_shift_out_39[17];
|
| 8950 |
|
|
|
| 8951 |
|
|
|
| 8952 |
|
|
--UD1_shift_out_74_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[1]
|
| 8953 |
|
|
--operation mode is normal
|
| 8954 |
|
|
|
| 8955 |
|
|
UD1_shift_out_74_a[1] = PD1_a_o_3 & !PD1_a_o_2 # !PD1_a_o_3 & PD1_a_o_2 & !UD1_shift_out_79[13] # !PD1_a_o_2 & !UD1_shift_out_79[9];
|
| 8956 |
|
|
|
| 8957 |
|
|
|
| 8958 |
|
|
--UD1_shift_out_79[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[1]
|
| 8959 |
|
|
--operation mode is normal
|
| 8960 |
|
|
|
| 8961 |
|
|
UD1_shift_out_79[1] = PD1_a_o_1 & UD1_shift_out_79_a[1] & VD1_b_o_iv_11 # !UD1_shift_out_79_a[1] & VD1_b_o_iv_12 # !PD1_a_o_1 & !UD1_shift_out_79_a[1];
|
| 8962 |
|
|
|
| 8963 |
|
|
|
| 8964 |
|
|
--UD1_shift_out_76_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[1]
|
| 8965 |
|
|
--operation mode is normal
|
| 8966 |
|
|
|
| 8967 |
|
|
UD1_shift_out_76_a[1] = UD1_shift_out587 & PD1_a_o_3 & !UD1_shift_out_59[1] # !PD1_a_o_3 & !UD1_shift_out_79[13] # !UD1_shift_out587 & !UD1_shift_out_59[1];
|
| 8968 |
|
|
|
| 8969 |
|
|
|
| 8970 |
|
|
--VD1_hilo_37_iv_0_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[1]
|
| 8971 |
|
|
--operation mode is normal
|
| 8972 |
|
|
|
| 8973 |
|
|
VD1_hilo_37_iv_0_a[1] = VD1_hilo_2 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo[0] # !VD1_hilo_2 & !VD1_hilo_2_sqmuxa # !VD1_hilo[0];
|
| 8974 |
|
|
|
| 8975 |
|
|
|
| 8976 |
|
|
--VD1_hilo_37_iv_0_0[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[1]
|
| 8977 |
|
|
--operation mode is normal
|
| 8978 |
|
|
|
| 8979 |
|
|
VD1_hilo_37_iv_0_0[1] = VD1_hilo_1 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[1] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_1 & VD1_un134_hilo_combout[1] & VD1_hilo_37_iv_0_a3_0[0];
|
| 8980 |
|
|
|
| 8981 |
|
|
|
| 8982 |
|
|
--VD1_hilo_37_iv_2[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[33]
|
| 8983 |
|
|
--operation mode is normal
|
| 8984 |
|
|
|
| 8985 |
|
|
VD1_hilo_37_iv_2[33] = VD1_hilo_33_i_m[33] # VD1_hilo_37_iv_2_a[33] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[33];
|
| 8986 |
|
|
|
| 8987 |
|
|
|
| 8988 |
|
|
--VD1_hilo_37_iv_a[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[33]
|
| 8989 |
|
|
--operation mode is normal
|
| 8990 |
|
|
|
| 8991 |
|
|
VD1_hilo_37_iv_a[33] = RC1_alu_func_o_0 & !PD1_a_o_1 # !RC1_alu_func_o_0 & !VD1_hilo_33;
|
| 8992 |
|
|
|
| 8993 |
|
|
|
| 8994 |
|
|
--TD1_alu_out_6_0_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_6_0_a[1]
|
| 8995 |
|
|
--operation mode is normal
|
| 8996 |
|
|
|
| 8997 |
|
|
TD1_alu_out_6_0_a[1] = RC1_alu_func_o_0 & !VD1_b_o_iv_1 & !PD1_a_o_1 # !RC1_alu_func_o_0 & VD1_b_o_iv_1 $ PD1_a_o_1;
|
| 8998 |
|
|
|
| 8999 |
|
|
|
| 9000 |
|
|
--TB1_dout_1_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_0
|
| 9001 |
|
|
--operation mode is normal
|
| 9002 |
|
|
|
| 9003 |
|
|
TB1_dout_1_0 = TB1_dout21 & CB1_dout_2_0 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_0 # !TB1_dout22 & CB1_dout_2_16;
|
| 9004 |
|
|
|
| 9005 |
|
|
|
| 9006 |
|
|
--GE1_q_a[0] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[0]
|
| 9007 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 9008 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 9009 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 9010 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 9011 |
|
|
GE1_q_a[0]_PORT_A_data_in = ~GND;
|
| 9012 |
|
|
GE1_q_a[0]_PORT_A_data_in_reg = DFFE(GE1_q_a[0]_PORT_A_data_in, GE1_q_a[0]_clock_0, , , );
|
| 9013 |
|
|
GE1_q_a[0]_PORT_B_data_in = CB1_dout_2_0;
|
| 9014 |
|
|
GE1_q_a[0]_PORT_B_data_in_reg = DFFE(GE1_q_a[0]_PORT_B_data_in, GE1_q_a[0]_clock_0, , , );
|
| 9015 |
|
|
GE1_q_a[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 9016 |
|
|
GE1_q_a[0]_PORT_A_address_reg = DFFE(GE1_q_a[0]_PORT_A_address, GE1_q_a[0]_clock_0, , , );
|
| 9017 |
|
|
GE1_q_a[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 9018 |
|
|
GE1_q_a[0]_PORT_B_address_reg = DFFE(GE1_q_a[0]_PORT_B_address, GE1_q_a[0]_clock_0, , , );
|
| 9019 |
|
|
GE1_q_a[0]_PORT_A_write_enable = GND;
|
| 9020 |
|
|
GE1_q_a[0]_PORT_A_write_enable_reg = DFFE(GE1_q_a[0]_PORT_A_write_enable, GE1_q_a[0]_clock_0, , , );
|
| 9021 |
|
|
GE1_q_a[0]_PORT_B_write_enable = WB1L2;
|
| 9022 |
|
|
GE1_q_a[0]_PORT_B_write_enable_reg = DFFE(GE1_q_a[0]_PORT_B_write_enable, GE1_q_a[0]_clock_0, , , );
|
| 9023 |
|
|
GE1_q_a[0]_clock_0 = E1__clk0;
|
| 9024 |
|
|
GE1_q_a[0]_PORT_A_data_out = MEMORY(GE1_q_a[0]_PORT_A_data_in_reg, GE1_q_a[0]_PORT_B_data_in_reg, GE1_q_a[0]_PORT_A_address_reg, GE1_q_a[0]_PORT_B_address_reg, GE1_q_a[0]_PORT_A_write_enable_reg, GE1_q_a[0]_PORT_B_write_enable_reg, , , GE1_q_a[0]_clock_0, , , , , );
|
| 9025 |
|
|
GE1_q_a[0] = GE1_q_a[0]_PORT_A_data_out[0];
|
| 9026 |
|
|
|
| 9027 |
|
|
--GE1_q_b[0] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[0]
|
| 9028 |
|
|
GE1_q_b[0]_PORT_A_data_in = ~GND;
|
| 9029 |
|
|
GE1_q_b[0]_PORT_A_data_in_reg = DFFE(GE1_q_b[0]_PORT_A_data_in, GE1_q_b[0]_clock_0, , , );
|
| 9030 |
|
|
GE1_q_b[0]_PORT_B_data_in = CB1_dout_2_0;
|
| 9031 |
|
|
GE1_q_b[0]_PORT_B_data_in_reg = DFFE(GE1_q_b[0]_PORT_B_data_in, GE1_q_b[0]_clock_0, , , );
|
| 9032 |
|
|
GE1_q_b[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 9033 |
|
|
GE1_q_b[0]_PORT_A_address_reg = DFFE(GE1_q_b[0]_PORT_A_address, GE1_q_b[0]_clock_0, , , );
|
| 9034 |
|
|
GE1_q_b[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 9035 |
|
|
GE1_q_b[0]_PORT_B_address_reg = DFFE(GE1_q_b[0]_PORT_B_address, GE1_q_b[0]_clock_0, , , );
|
| 9036 |
|
|
GE1_q_b[0]_PORT_A_write_enable = GND;
|
| 9037 |
|
|
GE1_q_b[0]_PORT_A_write_enable_reg = DFFE(GE1_q_b[0]_PORT_A_write_enable, GE1_q_b[0]_clock_0, , , );
|
| 9038 |
|
|
GE1_q_b[0]_PORT_B_write_enable = WB1L2;
|
| 9039 |
|
|
GE1_q_b[0]_PORT_B_write_enable_reg = DFFE(GE1_q_b[0]_PORT_B_write_enable, GE1_q_b[0]_clock_0, , , );
|
| 9040 |
|
|
GE1_q_b[0]_clock_0 = E1__clk0;
|
| 9041 |
|
|
GE1_q_b[0]_PORT_B_data_out = MEMORY(GE1_q_b[0]_PORT_A_data_in_reg, GE1_q_b[0]_PORT_B_data_in_reg, GE1_q_b[0]_PORT_A_address_reg, GE1_q_b[0]_PORT_B_address_reg, GE1_q_b[0]_PORT_A_write_enable_reg, GE1_q_b[0]_PORT_B_write_enable_reg, , , GE1_q_b[0]_clock_0, , , , , );
|
| 9042 |
|
|
GE1_q_b[0] = GE1_q_b[0]_PORT_B_data_out[0];
|
| 9043 |
|
|
|
| 9044 |
|
|
|
| 9045 |
|
|
--HE1_q_a[0] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[0]
|
| 9046 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 9047 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 9048 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 9049 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 9050 |
|
|
HE1_q_a[0]_PORT_A_data_in = ~GND;
|
| 9051 |
|
|
HE1_q_a[0]_PORT_A_data_in_reg = DFFE(HE1_q_a[0]_PORT_A_data_in, HE1_q_a[0]_clock_0, , , );
|
| 9052 |
|
|
HE1_q_a[0]_PORT_B_data_in = TB1_dout_1_x_0;
|
| 9053 |
|
|
HE1_q_a[0]_PORT_B_data_in_reg = DFFE(HE1_q_a[0]_PORT_B_data_in, HE1_q_a[0]_clock_0, , , );
|
| 9054 |
|
|
HE1_q_a[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 9055 |
|
|
HE1_q_a[0]_PORT_A_address_reg = DFFE(HE1_q_a[0]_PORT_A_address, HE1_q_a[0]_clock_0, , , );
|
| 9056 |
|
|
HE1_q_a[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 9057 |
|
|
HE1_q_a[0]_PORT_B_address_reg = DFFE(HE1_q_a[0]_PORT_B_address, HE1_q_a[0]_clock_0, , , );
|
| 9058 |
|
|
HE1_q_a[0]_PORT_A_write_enable = GND;
|
| 9059 |
|
|
HE1_q_a[0]_PORT_A_write_enable_reg = DFFE(HE1_q_a[0]_PORT_A_write_enable, HE1_q_a[0]_clock_0, , , );
|
| 9060 |
|
|
HE1_q_a[0]_PORT_B_write_enable = WB2L2;
|
| 9061 |
|
|
HE1_q_a[0]_PORT_B_write_enable_reg = DFFE(HE1_q_a[0]_PORT_B_write_enable, HE1_q_a[0]_clock_0, , , );
|
| 9062 |
|
|
HE1_q_a[0]_clock_0 = E1__clk0;
|
| 9063 |
|
|
HE1_q_a[0]_PORT_A_data_out = MEMORY(HE1_q_a[0]_PORT_A_data_in_reg, HE1_q_a[0]_PORT_B_data_in_reg, HE1_q_a[0]_PORT_A_address_reg, HE1_q_a[0]_PORT_B_address_reg, HE1_q_a[0]_PORT_A_write_enable_reg, HE1_q_a[0]_PORT_B_write_enable_reg, , , HE1_q_a[0]_clock_0, , , , , );
|
| 9064 |
|
|
HE1_q_a[0] = HE1_q_a[0]_PORT_A_data_out[0];
|
| 9065 |
|
|
|
| 9066 |
|
|
--HE1_q_b[0] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[0]
|
| 9067 |
|
|
HE1_q_b[0]_PORT_A_data_in = ~GND;
|
| 9068 |
|
|
HE1_q_b[0]_PORT_A_data_in_reg = DFFE(HE1_q_b[0]_PORT_A_data_in, HE1_q_b[0]_clock_0, , , );
|
| 9069 |
|
|
HE1_q_b[0]_PORT_B_data_in = TB1_dout_1_x_0;
|
| 9070 |
|
|
HE1_q_b[0]_PORT_B_data_in_reg = DFFE(HE1_q_b[0]_PORT_B_data_in, HE1_q_b[0]_clock_0, , , );
|
| 9071 |
|
|
HE1_q_b[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 9072 |
|
|
HE1_q_b[0]_PORT_A_address_reg = DFFE(HE1_q_b[0]_PORT_A_address, HE1_q_b[0]_clock_0, , , );
|
| 9073 |
|
|
HE1_q_b[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 9074 |
|
|
HE1_q_b[0]_PORT_B_address_reg = DFFE(HE1_q_b[0]_PORT_B_address, HE1_q_b[0]_clock_0, , , );
|
| 9075 |
|
|
HE1_q_b[0]_PORT_A_write_enable = GND;
|
| 9076 |
|
|
HE1_q_b[0]_PORT_A_write_enable_reg = DFFE(HE1_q_b[0]_PORT_A_write_enable, HE1_q_b[0]_clock_0, , , );
|
| 9077 |
|
|
HE1_q_b[0]_PORT_B_write_enable = WB2L2;
|
| 9078 |
|
|
HE1_q_b[0]_PORT_B_write_enable_reg = DFFE(HE1_q_b[0]_PORT_B_write_enable, HE1_q_b[0]_clock_0, , , );
|
| 9079 |
|
|
HE1_q_b[0]_clock_0 = E1__clk0;
|
| 9080 |
|
|
HE1_q_b[0]_PORT_B_data_out = MEMORY(HE1_q_b[0]_PORT_A_data_in_reg, HE1_q_b[0]_PORT_B_data_in_reg, HE1_q_b[0]_PORT_A_address_reg, HE1_q_b[0]_PORT_B_address_reg, HE1_q_b[0]_PORT_A_write_enable_reg, HE1_q_b[0]_PORT_B_write_enable_reg, , , HE1_q_b[0]_clock_0, , , , , );
|
| 9081 |
|
|
HE1_q_b[0] = HE1_q_b[0]_PORT_B_data_out[0];
|
| 9082 |
|
|
|
| 9083 |
|
|
|
| 9084 |
|
|
--KE1_q_a[0] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[0]
|
| 9085 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 9086 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 9087 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 9088 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 9089 |
|
|
KE1_q_a[0]_PORT_A_data_in = ~GND;
|
| 9090 |
|
|
KE1_q_a[0]_PORT_A_data_in_reg = DFFE(KE1_q_a[0]_PORT_A_data_in, KE1_q_a[0]_clock_0, , , );
|
| 9091 |
|
|
KE1_q_a[0]_PORT_B_data_in = TB1_dout_1_2_0;
|
| 9092 |
|
|
KE1_q_a[0]_PORT_B_data_in_reg = DFFE(KE1_q_a[0]_PORT_B_data_in, KE1_q_a[0]_clock_0, , , );
|
| 9093 |
|
|
KE1_q_a[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 9094 |
|
|
KE1_q_a[0]_PORT_A_address_reg = DFFE(KE1_q_a[0]_PORT_A_address, KE1_q_a[0]_clock_0, , , );
|
| 9095 |
|
|
KE1_q_a[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 9096 |
|
|
KE1_q_a[0]_PORT_B_address_reg = DFFE(KE1_q_a[0]_PORT_B_address, KE1_q_a[0]_clock_0, , , );
|
| 9097 |
|
|
KE1_q_a[0]_PORT_A_write_enable = GND;
|
| 9098 |
|
|
KE1_q_a[0]_PORT_A_write_enable_reg = DFFE(KE1_q_a[0]_PORT_A_write_enable, KE1_q_a[0]_clock_0, , , );
|
| 9099 |
|
|
KE1_q_a[0]_PORT_B_write_enable = WB4L2;
|
| 9100 |
|
|
KE1_q_a[0]_PORT_B_write_enable_reg = DFFE(KE1_q_a[0]_PORT_B_write_enable, KE1_q_a[0]_clock_0, , , );
|
| 9101 |
|
|
KE1_q_a[0]_clock_0 = E1__clk0;
|
| 9102 |
|
|
KE1_q_a[0]_PORT_A_data_out = MEMORY(KE1_q_a[0]_PORT_A_data_in_reg, KE1_q_a[0]_PORT_B_data_in_reg, KE1_q_a[0]_PORT_A_address_reg, KE1_q_a[0]_PORT_B_address_reg, KE1_q_a[0]_PORT_A_write_enable_reg, KE1_q_a[0]_PORT_B_write_enable_reg, , , KE1_q_a[0]_clock_0, , , , , );
|
| 9103 |
|
|
KE1_q_a[0] = KE1_q_a[0]_PORT_A_data_out[0];
|
| 9104 |
|
|
|
| 9105 |
|
|
--KE1_q_b[0] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[0]
|
| 9106 |
|
|
KE1_q_b[0]_PORT_A_data_in = ~GND;
|
| 9107 |
|
|
KE1_q_b[0]_PORT_A_data_in_reg = DFFE(KE1_q_b[0]_PORT_A_data_in, KE1_q_b[0]_clock_0, , , );
|
| 9108 |
|
|
KE1_q_b[0]_PORT_B_data_in = TB1_dout_1_2_0;
|
| 9109 |
|
|
KE1_q_b[0]_PORT_B_data_in_reg = DFFE(KE1_q_b[0]_PORT_B_data_in, KE1_q_b[0]_clock_0, , , );
|
| 9110 |
|
|
KE1_q_b[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 9111 |
|
|
KE1_q_b[0]_PORT_A_address_reg = DFFE(KE1_q_b[0]_PORT_A_address, KE1_q_b[0]_clock_0, , , );
|
| 9112 |
|
|
KE1_q_b[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 9113 |
|
|
KE1_q_b[0]_PORT_B_address_reg = DFFE(KE1_q_b[0]_PORT_B_address, KE1_q_b[0]_clock_0, , , );
|
| 9114 |
|
|
KE1_q_b[0]_PORT_A_write_enable = GND;
|
| 9115 |
|
|
KE1_q_b[0]_PORT_A_write_enable_reg = DFFE(KE1_q_b[0]_PORT_A_write_enable, KE1_q_b[0]_clock_0, , , );
|
| 9116 |
|
|
KE1_q_b[0]_PORT_B_write_enable = WB4L2;
|
| 9117 |
|
|
KE1_q_b[0]_PORT_B_write_enable_reg = DFFE(KE1_q_b[0]_PORT_B_write_enable, KE1_q_b[0]_clock_0, , , );
|
| 9118 |
|
|
KE1_q_b[0]_clock_0 = E1__clk0;
|
| 9119 |
|
|
KE1_q_b[0]_PORT_B_data_out = MEMORY(KE1_q_b[0]_PORT_A_data_in_reg, KE1_q_b[0]_PORT_B_data_in_reg, KE1_q_b[0]_PORT_A_address_reg, KE1_q_b[0]_PORT_B_address_reg, KE1_q_b[0]_PORT_A_write_enable_reg, KE1_q_b[0]_PORT_B_write_enable_reg, , , KE1_q_b[0]_clock_0, , , , , );
|
| 9120 |
|
|
KE1_q_b[0] = KE1_q_b[0]_PORT_B_data_out[0];
|
| 9121 |
|
|
|
| 9122 |
|
|
|
| 9123 |
|
|
--VD1_hilo[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo[32]
|
| 9124 |
|
|
--operation mode is normal
|
| 9125 |
|
|
|
| 9126 |
|
|
VD1_hilo[32]_lut_out = !VD1_hilo_37_iv_2[32] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[32] # !VD1_hilo25;
|
| 9127 |
|
|
VD1_hilo[32] = DFFEAS(VD1_hilo[32]_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 9128 |
|
|
|
| 9129 |
|
|
|
| 9130 |
|
|
--VD1_hilo[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo[0]
|
| 9131 |
|
|
--operation mode is normal
|
| 9132 |
|
|
|
| 9133 |
|
|
VD1_hilo[0]_lut_out = PD1_a_o_0 & VD1_addnop2109_0_a2 # VD1_hilo_37_iv_0_a3_1[62] # !VD1_hilo_37_iv_0_a[0];
|
| 9134 |
|
|
VD1_hilo[0] = DFFEAS(VD1_hilo[0]_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 9135 |
|
|
|
| 9136 |
|
|
|
| 9137 |
|
|
--UD1_shift_out_79[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[0]
|
| 9138 |
|
|
--operation mode is normal
|
| 9139 |
|
|
|
| 9140 |
|
|
UD1_shift_out_79[0] = PD1_a_o_1 & UD1_shift_out_79_a[0] & VD1_b_o_iv_10 # !UD1_shift_out_79_a[0] & VD1_b_o_iv_11 # !PD1_a_o_1 & !UD1_shift_out_79_a[0];
|
| 9141 |
|
|
|
| 9142 |
|
|
|
| 9143 |
|
|
--UD1_shift_out_76_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[0]
|
| 9144 |
|
|
--operation mode is normal
|
| 9145 |
|
|
|
| 9146 |
|
|
UD1_shift_out_76_a[0] = PD1_a_o_3 & !UD1_shift_out_79[20] # !PD1_a_o_3 & !UD1_shift_out_47[0];
|
| 9147 |
|
|
|
| 9148 |
|
|
|
| 9149 |
|
|
--UD1_shift_out_80[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[0]
|
| 9150 |
|
|
--operation mode is normal
|
| 9151 |
|
|
|
| 9152 |
|
|
UD1_shift_out_80[0] = PD1_a_o_2 & UD1_shift_out_80_a[0] & VD1_b_o_iv_5 # !UD1_shift_out_80_a[0] & VD1_b_o_iv_7 # !PD1_a_o_2 & !UD1_shift_out_80_a[0];
|
| 9153 |
|
|
|
| 9154 |
|
|
|
| 9155 |
|
|
--UD1_shift_out_82[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82[0]
|
| 9156 |
|
|
--operation mode is normal
|
| 9157 |
|
|
|
| 9158 |
|
|
UD1_shift_out_82[0] = PD1_a_o_2 & PD1_a_o_1 & VD1_b_o_iv_6 # !PD1_a_o_1 & !UD1_shift_out_82_a[0] # !PD1_a_o_2 & !UD1_shift_out_82_a[0];
|
| 9159 |
|
|
|
| 9160 |
|
|
|
| 9161 |
|
|
--UD1_shift_out_86_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[0]
|
| 9162 |
|
|
--operation mode is normal
|
| 9163 |
|
|
|
| 9164 |
|
|
UD1_shift_out_86_a[0] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[4] # !PD1_a_o_2 & !UD1_shift_out_79[8] # !UD1_shift_out587 & !UD1_shift_out_79[4];
|
| 9165 |
|
|
|
| 9166 |
|
|
|
| 9167 |
|
|
--UD1_shift_out_74[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[0]
|
| 9168 |
|
|
--operation mode is normal
|
| 9169 |
|
|
|
| 9170 |
|
|
UD1_shift_out_74[0] = PD1_a_o_3 & UD1_shift_out_74_a[0] & UD1_shift_out_79[16] # !UD1_shift_out_74_a[0] & UD1_shift_out_79[20] # !PD1_a_o_3 & !UD1_shift_out_74_a[0];
|
| 9171 |
|
|
|
| 9172 |
|
|
|
| 9173 |
|
|
--PD1_a_o_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[31]
|
| 9174 |
|
|
--operation mode is normal
|
| 9175 |
|
|
|
| 9176 |
|
|
PD1_a_o_a[31] = SC1_muxa_ctl_o_1 & !FB1_r32_o_31 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_31;
|
| 9177 |
|
|
|
| 9178 |
|
|
|
| 9179 |
|
|
--PD1_a_o_3_Z[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[31]
|
| 9180 |
|
|
--operation mode is normal
|
| 9181 |
|
|
|
| 9182 |
|
|
PD1_a_o_3_Z[31] = PD1_a_o_3_s[0] & SD1_r32_o_31 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[31];
|
| 9183 |
|
|
|
| 9184 |
|
|
|
| 9185 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[31] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[31]
|
| 9186 |
|
|
--operation mode is normal
|
| 9187 |
|
|
|
| 9188 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[31] = QB1_r32_o_31 & !FB1_r32_o_31 & QD1_b_o18 # !QB1_r32_o_31 & QD1_un1_b_o18_2 # !FB1_r32_o_31 & QD1_b_o18;
|
| 9189 |
|
|
|
| 9190 |
|
|
|
| 9191 |
|
|
--G1_BUS15471_i_m[31] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[31]
|
| 9192 |
|
|
--operation mode is normal
|
| 9193 |
|
|
|
| 9194 |
|
|
G1_BUS15471_i_m[31] = !FD1_wb_o_31 & QD1_b_o_1_sqmuxa;
|
| 9195 |
|
|
|
| 9196 |
|
|
|
| 9197 |
|
|
--VD1_b_o_iv_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_30
|
| 9198 |
|
|
--operation mode is normal
|
| 9199 |
|
|
|
| 9200 |
|
|
VD1_b_o_iv_30 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[30] & !G1_BUS15471_i_m[30] & AB1_r32_o_28 # !QD1_b_o_0_sqmuxa;
|
| 9201 |
|
|
|
| 9202 |
|
|
--VD1_op2_reged[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[30]
|
| 9203 |
|
|
--operation mode is normal
|
| 9204 |
|
|
|
| 9205 |
|
|
VD1_op2_reged[30] = DFFEAS(VD1_b_o_iv_30, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 9206 |
|
|
|
| 9207 |
|
|
|
| 9208 |
|
|
--TD1_lt_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_29
|
| 9209 |
|
|
--operation mode is arithmetic
|
| 9210 |
|
|
|
| 9211 |
|
|
TD1_lt_29 = CARRY(PD1_a_o_29 & !TD1_lt_28 # !VD1_b_o_iv_29 # !PD1_a_o_29 & !VD1_b_o_iv_29 & !TD1_lt_28);
|
| 9212 |
|
|
|
| 9213 |
|
|
|
| 9214 |
|
|
--TD1_sum_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_30
|
| 9215 |
|
|
--operation mode is arithmetic
|
| 9216 |
|
|
|
| 9217 |
|
|
TD1_sum_carry_30 = CARRY(VD1_b_o_iv_30 & PD1_a_o_30 & !TD1_sum_carry_29 # !VD1_b_o_iv_30 & PD1_a_o_30 # !TD1_sum_carry_29);
|
| 9218 |
|
|
|
| 9219 |
|
|
|
| 9220 |
|
|
--Y1_q_b[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[5]
|
| 9221 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 9222 |
|
|
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
|
| 9223 |
|
|
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
|
| 9224 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 9225 |
|
|
Y1_q_b[5]_PORT_A_data_in = CB1_r32_o_5;
|
| 9226 |
|
|
Y1_q_b[5]_PORT_A_data_in_reg = DFFE(Y1_q_b[5]_PORT_A_data_in, Y1_q_b[5]_clock_0, , , );
|
| 9227 |
|
|
Y1_q_b[5]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
|
| 9228 |
|
|
Y1_q_b[5]_PORT_A_address_reg = DFFE(Y1_q_b[5]_PORT_A_address, Y1_q_b[5]_clock_0, , , );
|
| 9229 |
|
|
Y1_q_b[5]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
|
| 9230 |
|
|
Y1_q_b[5]_PORT_B_address_reg = DFFE(Y1_q_b[5]_PORT_B_address, Y1_q_b[5]_clock_1, , , Y1_q_b[5]_clock_enable_1);
|
| 9231 |
|
|
Y1_q_b[5]_PORT_A_write_enable = T1_valid_wreq;
|
| 9232 |
|
|
Y1_q_b[5]_PORT_A_write_enable_reg = DFFE(Y1_q_b[5]_PORT_A_write_enable, Y1_q_b[5]_clock_0, , , );
|
| 9233 |
|
|
Y1_q_b[5]_PORT_B_read_enable = VCC;
|
| 9234 |
|
|
Y1_q_b[5]_PORT_B_read_enable_reg = DFFE(Y1_q_b[5]_PORT_B_read_enable, Y1_q_b[5]_clock_1, , , Y1_q_b[5]_clock_enable_1);
|
| 9235 |
|
|
Y1_q_b[5]_clock_0 = E1__clk0;
|
| 9236 |
|
|
Y1_q_b[5]_clock_1 = E1__clk0;
|
| 9237 |
|
|
Y1_q_b[5]_clock_enable_1 = T1_valid_rreq;
|
| 9238 |
|
|
Y1_q_b[5]_PORT_B_data_out = MEMORY(Y1_q_b[5]_PORT_A_data_in_reg, , Y1_q_b[5]_PORT_A_address_reg, Y1_q_b[5]_PORT_B_address_reg, Y1_q_b[5]_PORT_A_write_enable_reg, Y1_q_b[5]_PORT_B_read_enable_reg, , , Y1_q_b[5]_clock_0, Y1_q_b[5]_clock_1, , Y1_q_b[5]_clock_enable_1, , );
|
| 9239 |
|
|
Y1_q_b[5] = Y1_q_b[5]_PORT_B_data_out[0];
|
| 9240 |
|
|
|
| 9241 |
|
|
|
| 9242 |
|
|
--N1_tx_sr[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[6]
|
| 9243 |
|
|
--operation mode is normal
|
| 9244 |
|
|
|
| 9245 |
|
|
N1_tx_sr[6]_lut_out = N1_read_request_ff & Y1_q_b[6] # !N1_read_request_ff & N1_tx_sr[7];
|
| 9246 |
|
|
N1_tx_sr[6] = DFFEAS(N1_tx_sr[6]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );
|
| 9247 |
|
|
|
| 9248 |
|
|
|
| 9249 |
|
|
--K1_cntr_5_0[30] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[30]
|
| 9250 |
|
|
--operation mode is normal
|
| 9251 |
|
|
|
| 9252 |
|
|
K1_s_cntr_30__Z_qfbk = K1_s_cntr_30__Z;
|
| 9253 |
|
|
K1_cntr_5_0[30] = F1_wr_tmr_data_0_a2 & CB1_r32_o_30 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_30__Z_qfbk;
|
| 9254 |
|
|
|
| 9255 |
|
|
--K1_s_cntr_30__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_30__Z
|
| 9256 |
|
|
--operation mode is normal
|
| 9257 |
|
|
|
| 9258 |
|
|
K1_s_cntr_30__Z = DFFEAS(K1_cntr_5_0[30], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_30, , , VCC);
|
| 9259 |
|
|
|
| 9260 |
|
|
|
| 9261 |
|
|
--K1_cntr_5_0[31] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[31]
|
| 9262 |
|
|
--operation mode is normal
|
| 9263 |
|
|
|
| 9264 |
|
|
K1_s_cntr_31__Z_qfbk = K1_s_cntr_31__Z;
|
| 9265 |
|
|
K1_cntr_5_0[31] = F1_wr_tmr_data_0_a2 & CB1_r32_o_31 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_31__Z_qfbk;
|
| 9266 |
|
|
|
| 9267 |
|
|
--K1_s_cntr_31__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_31__Z
|
| 9268 |
|
|
--operation mode is normal
|
| 9269 |
|
|
|
| 9270 |
|
|
K1_s_cntr_31__Z = DFFEAS(K1_cntr_5_0[31], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_31, , , VCC);
|
| 9271 |
|
|
|
| 9272 |
|
|
|
| 9273 |
|
|
--K1_cntr_5_0[28] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[28]
|
| 9274 |
|
|
--operation mode is normal
|
| 9275 |
|
|
|
| 9276 |
|
|
K1_s_cntr_28__Z_qfbk = K1_s_cntr_28__Z;
|
| 9277 |
|
|
K1_cntr_5_0[28] = F1_wr_tmr_data_0_a2 & CB1_r32_o_28 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_28__Z_qfbk;
|
| 9278 |
|
|
|
| 9279 |
|
|
--K1_s_cntr_28__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_28__Z
|
| 9280 |
|
|
--operation mode is normal
|
| 9281 |
|
|
|
| 9282 |
|
|
K1_s_cntr_28__Z = DFFEAS(K1_cntr_5_0[28], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_28, , , VCC);
|
| 9283 |
|
|
|
| 9284 |
|
|
|
| 9285 |
|
|
--K1_cntr_27 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_27
|
| 9286 |
|
|
--operation mode is arithmetic
|
| 9287 |
|
|
|
| 9288 |
|
|
K1_cntr_27_carry_eqn = K1_cntr_cout[26];
|
| 9289 |
|
|
K1_cntr_27_lut_out = K1_cntr_27 $ (!K1_cntr_27_carry_eqn);
|
| 9290 |
|
|
K1_cntr_27 = DFFEAS(K1_cntr_27_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[27], , , !K1_un1_ld_1);
|
| 9291 |
|
|
|
| 9292 |
|
|
--K1_cntr_cout[27] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[27]
|
| 9293 |
|
|
--operation mode is arithmetic
|
| 9294 |
|
|
|
| 9295 |
|
|
K1_cntr_cout[27] = CARRY(!K1_cntr_27 & !K1_cntr_cout[26]);
|
| 9296 |
|
|
|
| 9297 |
|
|
|
| 9298 |
|
|
--K1_cntr_5_0[29] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[29]
|
| 9299 |
|
|
--operation mode is normal
|
| 9300 |
|
|
|
| 9301 |
|
|
K1_s_cntr_29__Z_qfbk = K1_s_cntr_29__Z;
|
| 9302 |
|
|
K1_cntr_5_0[29] = F1_wr_tmr_data_0_a2 & CB1_r32_o_29 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_29__Z_qfbk;
|
| 9303 |
|
|
|
| 9304 |
|
|
--K1_s_cntr_29__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_29__Z
|
| 9305 |
|
|
--operation mode is normal
|
| 9306 |
|
|
|
| 9307 |
|
|
K1_s_cntr_29__Z = DFFEAS(K1_cntr_5_0[29], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_29, , , VCC);
|
| 9308 |
|
|
|
| 9309 |
|
|
|
| 9310 |
|
|
--K1_cntr_18 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_18
|
| 9311 |
|
|
--operation mode is arithmetic
|
| 9312 |
|
|
|
| 9313 |
|
|
K1_cntr_18_carry_eqn = K1_cntr_cout[17];
|
| 9314 |
|
|
K1_cntr_18_lut_out = K1_cntr_18 $ (K1_cntr_18_carry_eqn);
|
| 9315 |
|
|
K1_cntr_18 = DFFEAS(K1_cntr_18_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[18], , , !K1_un1_ld_1);
|
| 9316 |
|
|
|
| 9317 |
|
|
--K1_cntr_cout[18] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[18]
|
| 9318 |
|
|
--operation mode is arithmetic
|
| 9319 |
|
|
|
| 9320 |
|
|
K1_cntr_cout[18] = CARRY(K1_cntr_18 # !K1_cntr_cout[17]);
|
| 9321 |
|
|
|
| 9322 |
|
|
|
| 9323 |
|
|
--K1_cntr_19 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_19
|
| 9324 |
|
|
--operation mode is arithmetic
|
| 9325 |
|
|
|
| 9326 |
|
|
K1_cntr_19_carry_eqn = K1_cntr_cout[18];
|
| 9327 |
|
|
K1_cntr_19_lut_out = K1_cntr_19 $ (!K1_cntr_19_carry_eqn);
|
| 9328 |
|
|
K1_cntr_19 = DFFEAS(K1_cntr_19_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[19], , , !K1_un1_ld_1);
|
| 9329 |
|
|
|
| 9330 |
|
|
--K1_cntr_cout[19] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[19]
|
| 9331 |
|
|
--operation mode is arithmetic
|
| 9332 |
|
|
|
| 9333 |
|
|
K1_cntr_cout[19] = CARRY(!K1_cntr_19 & !K1_cntr_cout[18]);
|
| 9334 |
|
|
|
| 9335 |
|
|
|
| 9336 |
|
|
--K1_cntr_16 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_16
|
| 9337 |
|
|
--operation mode is arithmetic
|
| 9338 |
|
|
|
| 9339 |
|
|
K1_cntr_16_carry_eqn = K1_cntr_cout[15];
|
| 9340 |
|
|
K1_cntr_16_lut_out = K1_cntr_16 $ (K1_cntr_16_carry_eqn);
|
| 9341 |
|
|
K1_cntr_16 = DFFEAS(K1_cntr_16_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[16], , , !K1_un1_ld_1);
|
| 9342 |
|
|
|
| 9343 |
|
|
--K1_cntr_cout[16] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[16]
|
| 9344 |
|
|
--operation mode is arithmetic
|
| 9345 |
|
|
|
| 9346 |
|
|
K1_cntr_cout[16] = CARRY(K1_cntr_16 # !K1_cntr_cout[15]);
|
| 9347 |
|
|
|
| 9348 |
|
|
|
| 9349 |
|
|
--K1_cntr_17 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_17
|
| 9350 |
|
|
--operation mode is arithmetic
|
| 9351 |
|
|
|
| 9352 |
|
|
K1_cntr_17_carry_eqn = K1_cntr_cout[16];
|
| 9353 |
|
|
K1_cntr_17_lut_out = K1_cntr_17 $ (!K1_cntr_17_carry_eqn);
|
| 9354 |
|
|
K1_cntr_17 = DFFEAS(K1_cntr_17_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[17], , , !K1_un1_ld_1);
|
| 9355 |
|
|
|
| 9356 |
|
|
--K1_cntr_cout[17] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[17]
|
| 9357 |
|
|
--operation mode is arithmetic
|
| 9358 |
|
|
|
| 9359 |
|
|
K1_cntr_cout[17] = CARRY(!K1_cntr_17 & !K1_cntr_cout[16]);
|
| 9360 |
|
|
|
| 9361 |
|
|
|
| 9362 |
|
|
--K1_cntr_22 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_22
|
| 9363 |
|
|
--operation mode is arithmetic
|
| 9364 |
|
|
|
| 9365 |
|
|
K1_cntr_22_carry_eqn = K1_cntr_cout[21];
|
| 9366 |
|
|
K1_cntr_22_lut_out = K1_cntr_22 $ (K1_cntr_22_carry_eqn);
|
| 9367 |
|
|
K1_cntr_22 = DFFEAS(K1_cntr_22_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[22], , , !K1_un1_ld_1);
|
| 9368 |
|
|
|
| 9369 |
|
|
--K1_cntr_cout[22] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[22]
|
| 9370 |
|
|
--operation mode is arithmetic
|
| 9371 |
|
|
|
| 9372 |
|
|
K1_cntr_cout[22] = CARRY(K1_cntr_22 # !K1_cntr_cout[21]);
|
| 9373 |
|
|
|
| 9374 |
|
|
|
| 9375 |
|
|
--K1_cntr_23 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_23
|
| 9376 |
|
|
--operation mode is arithmetic
|
| 9377 |
|
|
|
| 9378 |
|
|
K1_cntr_23_carry_eqn = K1_cntr_cout[22];
|
| 9379 |
|
|
K1_cntr_23_lut_out = K1_cntr_23 $ (!K1_cntr_23_carry_eqn);
|
| 9380 |
|
|
K1_cntr_23 = DFFEAS(K1_cntr_23_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[23], , , !K1_un1_ld_1);
|
| 9381 |
|
|
|
| 9382 |
|
|
--K1_cntr_cout[23] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[23]
|
| 9383 |
|
|
--operation mode is arithmetic
|
| 9384 |
|
|
|
| 9385 |
|
|
K1_cntr_cout[23] = CARRY(!K1_cntr_23 & !K1_cntr_cout[22]);
|
| 9386 |
|
|
|
| 9387 |
|
|
|
| 9388 |
|
|
--K1_cntr_20 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_20
|
| 9389 |
|
|
--operation mode is arithmetic
|
| 9390 |
|
|
|
| 9391 |
|
|
K1_cntr_20_carry_eqn = K1_cntr_cout[19];
|
| 9392 |
|
|
K1_cntr_20_lut_out = K1_cntr_20 $ (K1_cntr_20_carry_eqn);
|
| 9393 |
|
|
K1_cntr_20 = DFFEAS(K1_cntr_20_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[20], , , !K1_un1_ld_1);
|
| 9394 |
|
|
|
| 9395 |
|
|
--K1_cntr_cout[20] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[20]
|
| 9396 |
|
|
--operation mode is arithmetic
|
| 9397 |
|
|
|
| 9398 |
|
|
K1_cntr_cout[20] = CARRY(K1_cntr_20 # !K1_cntr_cout[19]);
|
| 9399 |
|
|
|
| 9400 |
|
|
|
| 9401 |
|
|
--K1_cntr_21 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_21
|
| 9402 |
|
|
--operation mode is arithmetic
|
| 9403 |
|
|
|
| 9404 |
|
|
K1_cntr_21_carry_eqn = K1_cntr_cout[20];
|
| 9405 |
|
|
K1_cntr_21_lut_out = K1_cntr_21 $ (!K1_cntr_21_carry_eqn);
|
| 9406 |
|
|
K1_cntr_21 = DFFEAS(K1_cntr_21_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[21], , , !K1_un1_ld_1);
|
| 9407 |
|
|
|
| 9408 |
|
|
--K1_cntr_cout[21] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[21]
|
| 9409 |
|
|
--operation mode is arithmetic
|
| 9410 |
|
|
|
| 9411 |
|
|
K1_cntr_cout[21] = CARRY(!K1_cntr_21 & !K1_cntr_cout[20]);
|
| 9412 |
|
|
|
| 9413 |
|
|
|
| 9414 |
|
|
--K1_cntr_26 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_26
|
| 9415 |
|
|
--operation mode is arithmetic
|
| 9416 |
|
|
|
| 9417 |
|
|
K1_cntr_26_carry_eqn = K1_cntr_cout[25];
|
| 9418 |
|
|
K1_cntr_26_lut_out = K1_cntr_26 $ (K1_cntr_26_carry_eqn);
|
| 9419 |
|
|
K1_cntr_26 = DFFEAS(K1_cntr_26_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[26], , , !K1_un1_ld_1);
|
| 9420 |
|
|
|
| 9421 |
|
|
--K1_cntr_cout[26] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[26]
|
| 9422 |
|
|
--operation mode is arithmetic
|
| 9423 |
|
|
|
| 9424 |
|
|
K1_cntr_cout[26] = CARRY(K1_cntr_26 # !K1_cntr_cout[25]);
|
| 9425 |
|
|
|
| 9426 |
|
|
|
| 9427 |
|
|
--K1_cntr_24 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_24
|
| 9428 |
|
|
--operation mode is arithmetic
|
| 9429 |
|
|
|
| 9430 |
|
|
K1_cntr_24_carry_eqn = K1_cntr_cout[23];
|
| 9431 |
|
|
K1_cntr_24_lut_out = K1_cntr_24 $ (K1_cntr_24_carry_eqn);
|
| 9432 |
|
|
K1_cntr_24 = DFFEAS(K1_cntr_24_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[24], , , !K1_un1_ld_1);
|
| 9433 |
|
|
|
| 9434 |
|
|
--K1_cntr_cout[24] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[24]
|
| 9435 |
|
|
--operation mode is arithmetic
|
| 9436 |
|
|
|
| 9437 |
|
|
K1_cntr_cout[24] = CARRY(K1_cntr_24 # !K1_cntr_cout[23]);
|
| 9438 |
|
|
|
| 9439 |
|
|
|
| 9440 |
|
|
--K1_cntr_25 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_25
|
| 9441 |
|
|
--operation mode is arithmetic
|
| 9442 |
|
|
|
| 9443 |
|
|
K1_cntr_25_carry_eqn = K1_cntr_cout[24];
|
| 9444 |
|
|
K1_cntr_25_lut_out = K1_cntr_25 $ (!K1_cntr_25_carry_eqn);
|
| 9445 |
|
|
K1_cntr_25 = DFFEAS(K1_cntr_25_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[25], , , !K1_un1_ld_1);
|
| 9446 |
|
|
|
| 9447 |
|
|
--K1_cntr_cout[25] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[25]
|
| 9448 |
|
|
--operation mode is arithmetic
|
| 9449 |
|
|
|
| 9450 |
|
|
K1_cntr_cout[25] = CARRY(!K1_cntr_25 & !K1_cntr_cout[24]);
|
| 9451 |
|
|
|
| 9452 |
|
|
|
| 9453 |
|
|
--K1_cntr_10 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_10
|
| 9454 |
|
|
--operation mode is arithmetic
|
| 9455 |
|
|
|
| 9456 |
|
|
K1_cntr_10_carry_eqn = K1_cntr_cout[9];
|
| 9457 |
|
|
K1_cntr_10_lut_out = K1_cntr_10 $ (K1_cntr_10_carry_eqn);
|
| 9458 |
|
|
K1_cntr_10 = DFFEAS(K1_cntr_10_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[10], , , !K1_un1_ld_1);
|
| 9459 |
|
|
|
| 9460 |
|
|
--K1_cntr_cout[10] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[10]
|
| 9461 |
|
|
--operation mode is arithmetic
|
| 9462 |
|
|
|
| 9463 |
|
|
K1_cntr_cout[10] = CARRY(K1_cntr_10 # !K1_cntr_cout[9]);
|
| 9464 |
|
|
|
| 9465 |
|
|
|
| 9466 |
|
|
--K1_cntr_11 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_11
|
| 9467 |
|
|
--operation mode is arithmetic
|
| 9468 |
|
|
|
| 9469 |
|
|
K1_cntr_11_carry_eqn = K1_cntr_cout[10];
|
| 9470 |
|
|
K1_cntr_11_lut_out = K1_cntr_11 $ (!K1_cntr_11_carry_eqn);
|
| 9471 |
|
|
K1_cntr_11 = DFFEAS(K1_cntr_11_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[11], , , !K1_un1_ld_1);
|
| 9472 |
|
|
|
| 9473 |
|
|
--K1_cntr_cout[11] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[11]
|
| 9474 |
|
|
--operation mode is arithmetic
|
| 9475 |
|
|
|
| 9476 |
|
|
K1_cntr_cout[11] = CARRY(!K1_cntr_11 & !K1_cntr_cout[10]);
|
| 9477 |
|
|
|
| 9478 |
|
|
|
| 9479 |
|
|
--K1_cntr_8 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_8
|
| 9480 |
|
|
--operation mode is arithmetic
|
| 9481 |
|
|
|
| 9482 |
|
|
K1_cntr_8_carry_eqn = K1_cntr_cout[7];
|
| 9483 |
|
|
K1_cntr_8_lut_out = K1_cntr_8 $ (K1_cntr_8_carry_eqn);
|
| 9484 |
|
|
K1_cntr_8 = DFFEAS(K1_cntr_8_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[8], , , !K1_un1_ld_1);
|
| 9485 |
|
|
|
| 9486 |
|
|
--K1_cntr_cout[8] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[8]
|
| 9487 |
|
|
--operation mode is arithmetic
|
| 9488 |
|
|
|
| 9489 |
|
|
K1_cntr_cout[8] = CARRY(K1_cntr_8 # !K1_cntr_cout[7]);
|
| 9490 |
|
|
|
| 9491 |
|
|
|
| 9492 |
|
|
--K1_cntr_9 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_9
|
| 9493 |
|
|
--operation mode is arithmetic
|
| 9494 |
|
|
|
| 9495 |
|
|
K1_cntr_9_carry_eqn = K1_cntr_cout[8];
|
| 9496 |
|
|
K1_cntr_9_lut_out = K1_cntr_9 $ (!K1_cntr_9_carry_eqn);
|
| 9497 |
|
|
K1_cntr_9 = DFFEAS(K1_cntr_9_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[9], , , !K1_un1_ld_1);
|
| 9498 |
|
|
|
| 9499 |
|
|
--K1_cntr_cout[9] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[9]
|
| 9500 |
|
|
--operation mode is arithmetic
|
| 9501 |
|
|
|
| 9502 |
|
|
K1_cntr_cout[9] = CARRY(!K1_cntr_9 & !K1_cntr_cout[8]);
|
| 9503 |
|
|
|
| 9504 |
|
|
|
| 9505 |
|
|
--K1_cntr_14 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_14
|
| 9506 |
|
|
--operation mode is arithmetic
|
| 9507 |
|
|
|
| 9508 |
|
|
K1_cntr_14_carry_eqn = K1_cntr_cout[13];
|
| 9509 |
|
|
K1_cntr_14_lut_out = K1_cntr_14 $ (K1_cntr_14_carry_eqn);
|
| 9510 |
|
|
K1_cntr_14 = DFFEAS(K1_cntr_14_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[14], , , !K1_un1_ld_1);
|
| 9511 |
|
|
|
| 9512 |
|
|
--K1_cntr_cout[14] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[14]
|
| 9513 |
|
|
--operation mode is arithmetic
|
| 9514 |
|
|
|
| 9515 |
|
|
K1_cntr_cout[14] = CARRY(K1_cntr_14 # !K1_cntr_cout[13]);
|
| 9516 |
|
|
|
| 9517 |
|
|
|
| 9518 |
|
|
--K1_cntr_15 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_15
|
| 9519 |
|
|
--operation mode is arithmetic
|
| 9520 |
|
|
|
| 9521 |
|
|
K1_cntr_15_carry_eqn = K1_cntr_cout[14];
|
| 9522 |
|
|
K1_cntr_15_lut_out = K1_cntr_15 $ (!K1_cntr_15_carry_eqn);
|
| 9523 |
|
|
K1_cntr_15 = DFFEAS(K1_cntr_15_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[15], , , !K1_un1_ld_1);
|
| 9524 |
|
|
|
| 9525 |
|
|
--K1_cntr_cout[15] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[15]
|
| 9526 |
|
|
--operation mode is arithmetic
|
| 9527 |
|
|
|
| 9528 |
|
|
K1_cntr_cout[15] = CARRY(!K1_cntr_15 & !K1_cntr_cout[14]);
|
| 9529 |
|
|
|
| 9530 |
|
|
|
| 9531 |
|
|
--K1_cntr_12 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_12
|
| 9532 |
|
|
--operation mode is arithmetic
|
| 9533 |
|
|
|
| 9534 |
|
|
K1_cntr_12_carry_eqn = K1_cntr_cout[11];
|
| 9535 |
|
|
K1_cntr_12_lut_out = K1_cntr_12 $ (K1_cntr_12_carry_eqn);
|
| 9536 |
|
|
K1_cntr_12 = DFFEAS(K1_cntr_12_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[12], , , !K1_un1_ld_1);
|
| 9537 |
|
|
|
| 9538 |
|
|
--K1_cntr_cout[12] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[12]
|
| 9539 |
|
|
--operation mode is arithmetic
|
| 9540 |
|
|
|
| 9541 |
|
|
K1_cntr_cout[12] = CARRY(K1_cntr_12 # !K1_cntr_cout[11]);
|
| 9542 |
|
|
|
| 9543 |
|
|
|
| 9544 |
|
|
--K1_cntr_13 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_13
|
| 9545 |
|
|
--operation mode is arithmetic
|
| 9546 |
|
|
|
| 9547 |
|
|
K1_cntr_13_carry_eqn = K1_cntr_cout[12];
|
| 9548 |
|
|
K1_cntr_13_lut_out = K1_cntr_13 $ (!K1_cntr_13_carry_eqn);
|
| 9549 |
|
|
K1_cntr_13 = DFFEAS(K1_cntr_13_lut_out, E1__clk0, VCC, , K1_cntrlde, K1_cntr_5_0[13], , , !K1_un1_ld_1);
|
| 9550 |
|
|
|
| 9551 |
|
|
--K1_cntr_cout[13] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[13]
|
| 9552 |
|
|
--operation mode is arithmetic
|
| 9553 |
|
|
|
| 9554 |
|
|
K1_cntr_cout[13] = CARRY(!K1_cntr_13 & !K1_cntr_cout[12]);
|
| 9555 |
|
|
|
| 9556 |
|
|
|
| 9557 |
|
|
--FD1_wb_o_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_8
|
| 9558 |
|
|
--operation mode is normal
|
| 9559 |
|
|
|
| 9560 |
|
|
FD1_wb_o_8 = TC1_wb_mux_ctl_o_0 & F1_dout_8 # DB1_r32_o_8 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_8;
|
| 9561 |
|
|
|
| 9562 |
|
|
--FD1_r_data_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_8
|
| 9563 |
|
|
--operation mode is normal
|
| 9564 |
|
|
|
| 9565 |
|
|
FD1_r_data_8 = DFFEAS(FD1_wb_o_8, E1__clk0, VCC, , , , , , );
|
| 9566 |
|
|
|
| 9567 |
|
|
|
| 9568 |
|
|
--ND1_dout_2_a_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_8
|
| 9569 |
|
|
--operation mode is normal
|
| 9570 |
|
|
|
| 9571 |
|
|
ND1_dout_2_a_8 = XD1_mux_fw_1 & !AB1_r32_o_6 # !XD1_mux_fw_1 & !QB1_r32_o_8;
|
| 9572 |
|
|
|
| 9573 |
|
|
|
| 9574 |
|
|
--M1_clk_ctr_3 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_3
|
| 9575 |
|
|
--operation mode is arithmetic
|
| 9576 |
|
|
|
| 9577 |
|
|
M1_clk_ctr_3_carry_eqn = M1_clk_ctr_cout[2];
|
| 9578 |
|
|
M1_clk_ctr_3_lut_out = M1_clk_ctr_3 $ (M1_clk_ctr_3_carry_eqn);
|
| 9579 |
|
|
M1_clk_ctr_3 = DFFEAS(M1_clk_ctr_3_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 9580 |
|
|
|
| 9581 |
|
|
--M1_clk_ctr_cout[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[3]
|
| 9582 |
|
|
--operation mode is arithmetic
|
| 9583 |
|
|
|
| 9584 |
|
|
M1_clk_ctr_cout[3] = CARRY(!M1_clk_ctr_cout[2] # !M1_clk_ctr_3);
|
| 9585 |
|
|
|
| 9586 |
|
|
|
| 9587 |
|
|
--M1_clk_ctr_2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_2
|
| 9588 |
|
|
--operation mode is arithmetic
|
| 9589 |
|
|
|
| 9590 |
|
|
M1_clk_ctr_2_carry_eqn = M1_clk_ctr_cout[1];
|
| 9591 |
|
|
M1_clk_ctr_2_lut_out = M1_clk_ctr_2 $ (!M1_clk_ctr_2_carry_eqn);
|
| 9592 |
|
|
M1_clk_ctr_2 = DFFEAS(M1_clk_ctr_2_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 9593 |
|
|
|
| 9594 |
|
|
--M1_clk_ctr_cout[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[2]
|
| 9595 |
|
|
--operation mode is arithmetic
|
| 9596 |
|
|
|
| 9597 |
|
|
M1_clk_ctr_cout[2] = CARRY(M1_clk_ctr_2 & !M1_clk_ctr_cout[1]);
|
| 9598 |
|
|
|
| 9599 |
|
|
|
| 9600 |
|
|
--M1_clk_ctr_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_0
|
| 9601 |
|
|
--operation mode is arithmetic
|
| 9602 |
|
|
|
| 9603 |
|
|
M1_clk_ctr_0_lut_out = !M1_clk_ctr_0;
|
| 9604 |
|
|
M1_clk_ctr_0 = DFFEAS(M1_clk_ctr_0_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 9605 |
|
|
|
| 9606 |
|
|
--M1_clk_ctr_cout[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[0]
|
| 9607 |
|
|
--operation mode is arithmetic
|
| 9608 |
|
|
|
| 9609 |
|
|
M1_clk_ctr_cout[0] = CARRY(M1_clk_ctr_0);
|
| 9610 |
|
|
|
| 9611 |
|
|
|
| 9612 |
|
|
--M1_clk_ctr[15] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[15]
|
| 9613 |
|
|
--operation mode is normal
|
| 9614 |
|
|
|
| 9615 |
|
|
M1_clk_ctr[15]_carry_eqn = M1_clk_ctr_cout[14];
|
| 9616 |
|
|
M1_clk_ctr[15]_lut_out = M1_clk_ctr[15] $ (M1_clk_ctr[15]_carry_eqn);
|
| 9617 |
|
|
M1_clk_ctr[15] = DFFEAS(M1_clk_ctr[15]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 9618 |
|
|
|
| 9619 |
|
|
|
| 9620 |
|
|
--M1_clk_ctr[14] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[14]
|
| 9621 |
|
|
--operation mode is arithmetic
|
| 9622 |
|
|
|
| 9623 |
|
|
M1_clk_ctr[14]_carry_eqn = M1_clk_ctr_cout[13];
|
| 9624 |
|
|
M1_clk_ctr[14]_lut_out = M1_clk_ctr[14] $ (!M1_clk_ctr[14]_carry_eqn);
|
| 9625 |
|
|
M1_clk_ctr[14] = DFFEAS(M1_clk_ctr[14]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 9626 |
|
|
|
| 9627 |
|
|
--M1_clk_ctr_cout[14] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[14]
|
| 9628 |
|
|
--operation mode is arithmetic
|
| 9629 |
|
|
|
| 9630 |
|
|
M1_clk_ctr_cout[14] = CARRY(M1_clk_ctr[14] & !M1_clk_ctr_cout[13]);
|
| 9631 |
|
|
|
| 9632 |
|
|
|
| 9633 |
|
|
--M1_clk_ctr[13] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[13]
|
| 9634 |
|
|
--operation mode is arithmetic
|
| 9635 |
|
|
|
| 9636 |
|
|
M1_clk_ctr[13]_carry_eqn = M1_clk_ctr_cout[12];
|
| 9637 |
|
|
M1_clk_ctr[13]_lut_out = M1_clk_ctr[13] $ (M1_clk_ctr[13]_carry_eqn);
|
| 9638 |
|
|
M1_clk_ctr[13] = DFFEAS(M1_clk_ctr[13]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 9639 |
|
|
|
| 9640 |
|
|
--M1_clk_ctr_cout[13] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[13]
|
| 9641 |
|
|
--operation mode is arithmetic
|
| 9642 |
|
|
|
| 9643 |
|
|
M1_clk_ctr_cout[13] = CARRY(!M1_clk_ctr_cout[12] # !M1_clk_ctr[13]);
|
| 9644 |
|
|
|
| 9645 |
|
|
|
| 9646 |
|
|
--M1_un1_clk_ctr_equ0_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|un1_clk_ctr_equ0_0_a2_a
|
| 9647 |
|
|
--operation mode is normal
|
| 9648 |
|
|
|
| 9649 |
|
|
M1_un1_clk_ctr_equ0_0_a2_a = !M1_clk_ctr[6] & !M1_clk_ctr[7] & !M1_clk_ctr[12];
|
| 9650 |
|
|
|
| 9651 |
|
|
|
| 9652 |
|
|
--M1_clk_ctr[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[5]
|
| 9653 |
|
|
--operation mode is arithmetic
|
| 9654 |
|
|
|
| 9655 |
|
|
M1_clk_ctr[5]_carry_eqn = M1_clk_ctr_cout[4];
|
| 9656 |
|
|
M1_clk_ctr[5]_lut_out = M1_clk_ctr[5] $ (M1_clk_ctr[5]_carry_eqn);
|
| 9657 |
|
|
M1_clk_ctr[5] = DFFEAS(M1_clk_ctr[5]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 9658 |
|
|
|
| 9659 |
|
|
--M1_clk_ctr_cout[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[5]
|
| 9660 |
|
|
--operation mode is arithmetic
|
| 9661 |
|
|
|
| 9662 |
|
|
M1_clk_ctr_cout[5] = CARRY(!M1_clk_ctr_cout[4] # !M1_clk_ctr[5]);
|
| 9663 |
|
|
|
| 9664 |
|
|
|
| 9665 |
|
|
--M1_clk_ctr[10] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[10]
|
| 9666 |
|
|
--operation mode is arithmetic
|
| 9667 |
|
|
|
| 9668 |
|
|
M1_clk_ctr[10]_carry_eqn = M1_clk_ctr_cout[9];
|
| 9669 |
|
|
M1_clk_ctr[10]_lut_out = M1_clk_ctr[10] $ (!M1_clk_ctr[10]_carry_eqn);
|
| 9670 |
|
|
M1_clk_ctr[10] = DFFEAS(M1_clk_ctr[10]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 9671 |
|
|
|
| 9672 |
|
|
--M1_clk_ctr_cout[10] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[10]
|
| 9673 |
|
|
--operation mode is arithmetic
|
| 9674 |
|
|
|
| 9675 |
|
|
M1_clk_ctr_cout[10] = CARRY(M1_clk_ctr[10] & !M1_clk_ctr_cout[9]);
|
| 9676 |
|
|
|
| 9677 |
|
|
|
| 9678 |
|
|
--M1_clk_ctr[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[8]
|
| 9679 |
|
|
--operation mode is arithmetic
|
| 9680 |
|
|
|
| 9681 |
|
|
M1_clk_ctr[8]_carry_eqn = M1_clk_ctr_cout[7];
|
| 9682 |
|
|
M1_clk_ctr[8]_lut_out = M1_clk_ctr[8] $ (!M1_clk_ctr[8]_carry_eqn);
|
| 9683 |
|
|
M1_clk_ctr[8] = DFFEAS(M1_clk_ctr[8]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 9684 |
|
|
|
| 9685 |
|
|
--M1_clk_ctr_cout[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[8]
|
| 9686 |
|
|
--operation mode is arithmetic
|
| 9687 |
|
|
|
| 9688 |
|
|
M1_clk_ctr_cout[8] = CARRY(M1_clk_ctr[8] & !M1_clk_ctr_cout[7]);
|
| 9689 |
|
|
|
| 9690 |
|
|
|
| 9691 |
|
|
--M1_un1_clk_ctr_equ0_0_a2_0_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|un1_clk_ctr_equ0_0_a2_0_a
|
| 9692 |
|
|
--operation mode is normal
|
| 9693 |
|
|
|
| 9694 |
|
|
M1_un1_clk_ctr_equ0_0_a2_0_a = M1_clk_ctr[4] & !M1_clk_ctr[9] & !M1_clk_ctr[1] & !M1_clk_ctr[11];
|
| 9695 |
|
|
|
| 9696 |
|
|
|
| 9697 |
|
|
--SB1_un1_wr_en46_4_combout is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_wr_en46_4_combout
|
| 9698 |
|
|
--operation mode is normal
|
| 9699 |
|
|
|
| 9700 |
|
|
SB1_un1_wr_en46_4_combout = TB1_dout21 & !RB1_c_0_d0 & QC1_dmem_ctl_o_3 # !SB1_wr_en46_0 # !TB1_dout21 & QC1_dmem_ctl_o_3 # !SB1_wr_en46_0;
|
| 9701 |
|
|
|
| 9702 |
|
|
|
| 9703 |
|
|
--SB1_un1_addr_i_1_combout is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_addr_i_1_combout
|
| 9704 |
|
|
--operation mode is normal
|
| 9705 |
|
|
|
| 9706 |
|
|
SB1_un1_addr_i_1_combout = !RB1_c_0_d0 # !QC1_dmem_ctl_o_2;
|
| 9707 |
|
|
|
| 9708 |
|
|
|
| 9709 |
|
|
--WB1L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1|q[0]~94
|
| 9710 |
|
|
--operation mode is normal
|
| 9711 |
|
|
|
| 9712 |
|
|
WB1L1 = SB1_un1_wr_en46_4_combout # SB1_un1_addr_i_1_combout & !RB1_c_1 # !SB1_un1_addr_i_1_combout & !WB1L2;
|
| 9713 |
|
|
|
| 9714 |
|
|
|
| 9715 |
|
|
--SB1_wr_en47 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|wr_en47
|
| 9716 |
|
|
--operation mode is normal
|
| 9717 |
|
|
|
| 9718 |
|
|
SB1_wr_en47 = !QC1_dmem_ctl_o_1 & !QC1_dmem_ctl_o_3 & QC1_dmem_ctl_o_0 & QC1_dmem_ctl_o_2;
|
| 9719 |
|
|
|
| 9720 |
|
|
|
| 9721 |
|
|
--WB1L2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1|q[0]~95
|
| 9722 |
|
|
--operation mode is normal
|
| 9723 |
|
|
|
| 9724 |
|
|
WB1L2 = SB1_wr_en47 # !WB1L1;
|
| 9725 |
|
|
|
| 9726 |
|
|
|
| 9727 |
|
|
--DD1_un1_pc_next46_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_next46_0
|
| 9728 |
|
|
--operation mode is normal
|
| 9729 |
|
|
|
| 9730 |
|
|
DD1_un1_pc_next46_0 = !AD1_CurrState_Sreg0_5 & AD1_pc_prectl_1_0_i_a2_0_a2_0 & !AD1_pc_prectl_1_0_i_a2_0_a2_1 # !AD1_pc_prectl_1_0_i_a2_0_a2_0 & !DD1_un1_pc_next46_0_a & AD1_pc_prectl_1_0_i_a2_0_a2_1;
|
| 9731 |
|
|
|
| 9732 |
|
|
|
| 9733 |
|
|
--DD1_pc_next_0_iv_1_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_2
|
| 9734 |
|
|
--operation mode is normal
|
| 9735 |
|
|
|
| 9736 |
|
|
DD1_pc_next_0_iv_1_2 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_2 # !DD1_pc_next_0_iv_1_a[2];
|
| 9737 |
|
|
|
| 9738 |
|
|
|
| 9739 |
|
|
--DD1_un1_pc_add2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add2
|
| 9740 |
|
|
--operation mode is arithmetic
|
| 9741 |
|
|
|
| 9742 |
|
|
DD1_un1_pc_add2_carry_eqn = DD1_un1_pc_carry_1;
|
| 9743 |
|
|
DD1_un1_pc_add2 = DD1_un1_pc_prectl_1_i[2] $ KB1_r32_o_2 $ DD1_un1_pc_add2_carry_eqn;
|
| 9744 |
|
|
|
| 9745 |
|
|
--DD1_un1_pc_carry_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_2
|
| 9746 |
|
|
--operation mode is arithmetic
|
| 9747 |
|
|
|
| 9748 |
|
|
DD1_un1_pc_carry_2 = CARRY(DD1_un1_pc_prectl_1_i[2] & KB1_r32_o_2 & !DD1_un1_pc_carry_1 # !DD1_un1_pc_prectl_1_i[2] & KB1_r32_o_2 # !DD1_un1_pc_carry_1);
|
| 9749 |
|
|
|
| 9750 |
|
|
|
| 9751 |
|
|
--DD1_pc_next_0_iv_1_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_3
|
| 9752 |
|
|
--operation mode is normal
|
| 9753 |
|
|
|
| 9754 |
|
|
DD1_pc_next_0_iv_1_3 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_3 # !DD1_pc_next_0_iv_1_a[3];
|
| 9755 |
|
|
|
| 9756 |
|
|
|
| 9757 |
|
|
--DD1_un1_pc_add3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add3
|
| 9758 |
|
|
--operation mode is arithmetic
|
| 9759 |
|
|
|
| 9760 |
|
|
DD1_un1_pc_add3_carry_eqn = DD1_un1_pc_carry_2;
|
| 9761 |
|
|
DD1_un1_pc_add3 = KB1_r32_o_3 $ DD1_un1_pc_prectl_1_0_a4[3] $ DD1_un1_pc_add3_carry_eqn;
|
| 9762 |
|
|
|
| 9763 |
|
|
--DD1_un1_pc_carry_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_3
|
| 9764 |
|
|
--operation mode is arithmetic
|
| 9765 |
|
|
|
| 9766 |
|
|
DD1_un1_pc_carry_3 = CARRY(KB1_r32_o_3 & !DD1_un1_pc_prectl_1_0_a4[3] & !DD1_un1_pc_carry_2 # !KB1_r32_o_3 & !DD1_un1_pc_carry_2 # !DD1_un1_pc_prectl_1_0_a4[3]);
|
| 9767 |
|
|
|
| 9768 |
|
|
|
| 9769 |
|
|
--DD1_pc_next_0_iv_1_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_4
|
| 9770 |
|
|
--operation mode is normal
|
| 9771 |
|
|
|
| 9772 |
|
|
DD1_pc_next_0_iv_1_4 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_4 # !DD1_pc_next_0_iv_1_a[4];
|
| 9773 |
|
|
|
| 9774 |
|
|
|
| 9775 |
|
|
--DD1_un1_pc_add4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add4
|
| 9776 |
|
|
--operation mode is arithmetic
|
| 9777 |
|
|
|
| 9778 |
|
|
DD1_un1_pc_add4_carry_eqn = DD1_un1_pc_carry_3;
|
| 9779 |
|
|
DD1_un1_pc_add4 = KB1_r32_o_4 $ DD1_un1_pc_prectl_1_0_a4[4] $ !DD1_un1_pc_add4_carry_eqn;
|
| 9780 |
|
|
|
| 9781 |
|
|
--DD1_un1_pc_carry_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_4
|
| 9782 |
|
|
--operation mode is arithmetic
|
| 9783 |
|
|
|
| 9784 |
|
|
DD1_un1_pc_carry_4 = CARRY(KB1_r32_o_4 & DD1_un1_pc_prectl_1_0_a4[4] # !DD1_un1_pc_carry_3 # !KB1_r32_o_4 & DD1_un1_pc_prectl_1_0_a4[4] & !DD1_un1_pc_carry_3);
|
| 9785 |
|
|
|
| 9786 |
|
|
|
| 9787 |
|
|
--DD1_pc_next_0_iv_1_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_5
|
| 9788 |
|
|
--operation mode is normal
|
| 9789 |
|
|
|
| 9790 |
|
|
DD1_pc_next_0_iv_1_5 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_5 # !DD1_pc_next_0_iv_1_a[5];
|
| 9791 |
|
|
|
| 9792 |
|
|
|
| 9793 |
|
|
--DD1_un1_pc_add5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add5
|
| 9794 |
|
|
--operation mode is arithmetic
|
| 9795 |
|
|
|
| 9796 |
|
|
DD1_un1_pc_add5_carry_eqn = DD1_un1_pc_carry_4;
|
| 9797 |
|
|
DD1_un1_pc_add5 = KB1_r32_o_5 $ DD1_un1_pc_prectl_1_0_a4[5] $ DD1_un1_pc_add5_carry_eqn;
|
| 9798 |
|
|
|
| 9799 |
|
|
--DD1_un1_pc_carry_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_5
|
| 9800 |
|
|
--operation mode is arithmetic
|
| 9801 |
|
|
|
| 9802 |
|
|
DD1_un1_pc_carry_5 = CARRY(KB1_r32_o_5 & !DD1_un1_pc_prectl_1_0_a4[5] & !DD1_un1_pc_carry_4 # !KB1_r32_o_5 & !DD1_un1_pc_carry_4 # !DD1_un1_pc_prectl_1_0_a4[5]);
|
| 9803 |
|
|
|
| 9804 |
|
|
|
| 9805 |
|
|
--DD1_pc_next_0_iv_1_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_6
|
| 9806 |
|
|
--operation mode is normal
|
| 9807 |
|
|
|
| 9808 |
|
|
DD1_pc_next_0_iv_1_6 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_6 # !DD1_pc_next_0_iv_1_a[6];
|
| 9809 |
|
|
|
| 9810 |
|
|
|
| 9811 |
|
|
--DD1_un1_pc_add6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add6
|
| 9812 |
|
|
--operation mode is arithmetic
|
| 9813 |
|
|
|
| 9814 |
|
|
DD1_un1_pc_add6_carry_eqn = DD1_un1_pc_carry_5;
|
| 9815 |
|
|
DD1_un1_pc_add6 = KB1_r32_o_6 $ DD1_un1_pc_prectl_1_0_a4[6] $ !DD1_un1_pc_add6_carry_eqn;
|
| 9816 |
|
|
|
| 9817 |
|
|
--DD1_un1_pc_carry_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_6
|
| 9818 |
|
|
--operation mode is arithmetic
|
| 9819 |
|
|
|
| 9820 |
|
|
DD1_un1_pc_carry_6 = CARRY(KB1_r32_o_6 & DD1_un1_pc_prectl_1_0_a4[6] # !DD1_un1_pc_carry_5 # !KB1_r32_o_6 & DD1_un1_pc_prectl_1_0_a4[6] & !DD1_un1_pc_carry_5);
|
| 9821 |
|
|
|
| 9822 |
|
|
|
| 9823 |
|
|
--DD1_pc_next_0_iv_1_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_7
|
| 9824 |
|
|
--operation mode is normal
|
| 9825 |
|
|
|
| 9826 |
|
|
DD1_pc_next_0_iv_1_7 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_7 # !DD1_pc_next_0_iv_1_a[7];
|
| 9827 |
|
|
|
| 9828 |
|
|
|
| 9829 |
|
|
--DD1_un1_pc_add7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add7
|
| 9830 |
|
|
--operation mode is arithmetic
|
| 9831 |
|
|
|
| 9832 |
|
|
DD1_un1_pc_add7_carry_eqn = DD1_un1_pc_carry_6;
|
| 9833 |
|
|
DD1_un1_pc_add7 = KB1_r32_o_7 $ DD1_un1_pc_prectl_1_0_a4[7] $ DD1_un1_pc_add7_carry_eqn;
|
| 9834 |
|
|
|
| 9835 |
|
|
--DD1_un1_pc_carry_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_7
|
| 9836 |
|
|
--operation mode is arithmetic
|
| 9837 |
|
|
|
| 9838 |
|
|
DD1_un1_pc_carry_7 = CARRY(KB1_r32_o_7 & !DD1_un1_pc_prectl_1_0_a4[7] & !DD1_un1_pc_carry_6 # !KB1_r32_o_7 & !DD1_un1_pc_carry_6 # !DD1_un1_pc_prectl_1_0_a4[7]);
|
| 9839 |
|
|
|
| 9840 |
|
|
|
| 9841 |
|
|
--DD1_pc_next_0_iv_1_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_8
|
| 9842 |
|
|
--operation mode is normal
|
| 9843 |
|
|
|
| 9844 |
|
|
DD1_pc_next_0_iv_1_8 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_8 # !DD1_pc_next_0_iv_1_a[8];
|
| 9845 |
|
|
|
| 9846 |
|
|
|
| 9847 |
|
|
--DD1_un1_pc_add8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add8
|
| 9848 |
|
|
--operation mode is arithmetic
|
| 9849 |
|
|
|
| 9850 |
|
|
DD1_un1_pc_add8_carry_eqn = DD1_un1_pc_carry_7;
|
| 9851 |
|
|
DD1_un1_pc_add8 = KB1_r32_o_8 $ DD1_un1_pc_prectl_1_0_a4[8] $ !DD1_un1_pc_add8_carry_eqn;
|
| 9852 |
|
|
|
| 9853 |
|
|
--DD1_un1_pc_carry_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_8
|
| 9854 |
|
|
--operation mode is arithmetic
|
| 9855 |
|
|
|
| 9856 |
|
|
DD1_un1_pc_carry_8 = CARRY(KB1_r32_o_8 & DD1_un1_pc_prectl_1_0_a4[8] # !DD1_un1_pc_carry_7 # !KB1_r32_o_8 & DD1_un1_pc_prectl_1_0_a4[8] & !DD1_un1_pc_carry_7);
|
| 9857 |
|
|
|
| 9858 |
|
|
|
| 9859 |
|
|
--DD1_pc_next_0_iv_1_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_9
|
| 9860 |
|
|
--operation mode is normal
|
| 9861 |
|
|
|
| 9862 |
|
|
DD1_pc_next_0_iv_1_9 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_9 # !DD1_pc_next_0_iv_1_a[9];
|
| 9863 |
|
|
|
| 9864 |
|
|
|
| 9865 |
|
|
--DD1_un1_pc_add9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add9
|
| 9866 |
|
|
--operation mode is arithmetic
|
| 9867 |
|
|
|
| 9868 |
|
|
DD1_un1_pc_add9_carry_eqn = DD1_un1_pc_carry_8;
|
| 9869 |
|
|
DD1_un1_pc_add9 = KB1_r32_o_9 $ DD1_un1_pc_prectl_1_0_a4[9] $ DD1_un1_pc_add9_carry_eqn;
|
| 9870 |
|
|
|
| 9871 |
|
|
--DD1_un1_pc_carry_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_9
|
| 9872 |
|
|
--operation mode is arithmetic
|
| 9873 |
|
|
|
| 9874 |
|
|
DD1_un1_pc_carry_9 = CARRY(KB1_r32_o_9 & !DD1_un1_pc_prectl_1_0_a4[9] & !DD1_un1_pc_carry_8 # !KB1_r32_o_9 & !DD1_un1_pc_carry_8 # !DD1_un1_pc_prectl_1_0_a4[9]);
|
| 9875 |
|
|
|
| 9876 |
|
|
|
| 9877 |
|
|
--DD1_pc_next_0_iv_1_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_10
|
| 9878 |
|
|
--operation mode is normal
|
| 9879 |
|
|
|
| 9880 |
|
|
DD1_pc_next_0_iv_1_10 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_10 # !DD1_pc_next_0_iv_1_a[10];
|
| 9881 |
|
|
|
| 9882 |
|
|
|
| 9883 |
|
|
--DD1_un1_pc_add10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add10
|
| 9884 |
|
|
--operation mode is arithmetic
|
| 9885 |
|
|
|
| 9886 |
|
|
DD1_un1_pc_add10_carry_eqn = DD1_un1_pc_carry_9;
|
| 9887 |
|
|
DD1_un1_pc_add10 = KB1_r32_o_10 $ DD1_un1_pc_prectl_1_0_a4[10] $ !DD1_un1_pc_add10_carry_eqn;
|
| 9888 |
|
|
|
| 9889 |
|
|
--DD1_un1_pc_carry_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_10
|
| 9890 |
|
|
--operation mode is arithmetic
|
| 9891 |
|
|
|
| 9892 |
|
|
DD1_un1_pc_carry_10 = CARRY(KB1_r32_o_10 & DD1_un1_pc_prectl_1_0_a4[10] # !DD1_un1_pc_carry_9 # !KB1_r32_o_10 & DD1_un1_pc_prectl_1_0_a4[10] & !DD1_un1_pc_carry_9);
|
| 9893 |
|
|
|
| 9894 |
|
|
|
| 9895 |
|
|
--DD1_pc_next_0_iv_1_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_11
|
| 9896 |
|
|
--operation mode is normal
|
| 9897 |
|
|
|
| 9898 |
|
|
DD1_pc_next_0_iv_1_11 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_11 # !DD1_pc_next_0_iv_1_a[11];
|
| 9899 |
|
|
|
| 9900 |
|
|
|
| 9901 |
|
|
--DD1_un1_pc_add11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add11
|
| 9902 |
|
|
--operation mode is arithmetic
|
| 9903 |
|
|
|
| 9904 |
|
|
DD1_un1_pc_add11_carry_eqn = DD1_un1_pc_carry_10;
|
| 9905 |
|
|
DD1_un1_pc_add11 = KB1_r32_o_11 $ DD1_un1_pc_prectl_1_0_a4[11] $ DD1_un1_pc_add11_carry_eqn;
|
| 9906 |
|
|
|
| 9907 |
|
|
--DD1_un1_pc_carry_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_11
|
| 9908 |
|
|
--operation mode is arithmetic
|
| 9909 |
|
|
|
| 9910 |
|
|
DD1_un1_pc_carry_11 = CARRY(KB1_r32_o_11 & !DD1_un1_pc_prectl_1_0_a4[11] & !DD1_un1_pc_carry_10 # !KB1_r32_o_11 & !DD1_un1_pc_carry_10 # !DD1_un1_pc_prectl_1_0_a4[11]);
|
| 9911 |
|
|
|
| 9912 |
|
|
|
| 9913 |
|
|
--DD1_pc_next_0_iv_1_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_12
|
| 9914 |
|
|
--operation mode is normal
|
| 9915 |
|
|
|
| 9916 |
|
|
DD1_pc_next_0_iv_1_12 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_12 # !DD1_pc_next_0_iv_1_a[12];
|
| 9917 |
|
|
|
| 9918 |
|
|
|
| 9919 |
|
|
--DD1_un1_pc_add12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add12
|
| 9920 |
|
|
--operation mode is arithmetic
|
| 9921 |
|
|
|
| 9922 |
|
|
DD1_un1_pc_add12_carry_eqn = DD1_un1_pc_carry_11;
|
| 9923 |
|
|
DD1_un1_pc_add12 = KB1_r32_o_12 $ DD1_un1_pc_prectl_1_0_a4[12] $ !DD1_un1_pc_add12_carry_eqn;
|
| 9924 |
|
|
|
| 9925 |
|
|
--DD1_un1_pc_carry_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_12
|
| 9926 |
|
|
--operation mode is arithmetic
|
| 9927 |
|
|
|
| 9928 |
|
|
DD1_un1_pc_carry_12 = CARRY(KB1_r32_o_12 & DD1_un1_pc_prectl_1_0_a4[12] # !DD1_un1_pc_carry_11 # !KB1_r32_o_12 & DD1_un1_pc_prectl_1_0_a4[12] & !DD1_un1_pc_carry_11);
|
| 9929 |
|
|
|
| 9930 |
|
|
|
| 9931 |
|
|
--TB1_dout_1_7 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_7
|
| 9932 |
|
|
--operation mode is normal
|
| 9933 |
|
|
|
| 9934 |
|
|
TB1_dout_1_7 = TB1_dout21 & CB1_dout_2_7 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_7 # !TB1_dout22 & CB1_dout_2_23;
|
| 9935 |
|
|
|
| 9936 |
|
|
|
| 9937 |
|
|
--UB1_dout_2_i_i_a2_2_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_2_a[7]
|
| 9938 |
|
|
--operation mode is normal
|
| 9939 |
|
|
|
| 9940 |
|
|
UB1_dout_2_i_i_a2_2_a[7] = !RB1_ctl_o_1 & !RB1_ctl_o_2;
|
| 9941 |
|
|
|
| 9942 |
|
|
|
| 9943 |
|
|
--HE1_q_a[7] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[7]
|
| 9944 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 9945 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 9946 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 9947 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 9948 |
|
|
HE1_q_a[7]_PORT_A_data_in = ~GND;
|
| 9949 |
|
|
HE1_q_a[7]_PORT_A_data_in_reg = DFFE(HE1_q_a[7]_PORT_A_data_in, HE1_q_a[7]_clock_0, , , );
|
| 9950 |
|
|
HE1_q_a[7]_PORT_B_data_in = TB1_dout_1_x_7;
|
| 9951 |
|
|
HE1_q_a[7]_PORT_B_data_in_reg = DFFE(HE1_q_a[7]_PORT_B_data_in, HE1_q_a[7]_clock_0, , , );
|
| 9952 |
|
|
HE1_q_a[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 9953 |
|
|
HE1_q_a[7]_PORT_A_address_reg = DFFE(HE1_q_a[7]_PORT_A_address, HE1_q_a[7]_clock_0, , , );
|
| 9954 |
|
|
HE1_q_a[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 9955 |
|
|
HE1_q_a[7]_PORT_B_address_reg = DFFE(HE1_q_a[7]_PORT_B_address, HE1_q_a[7]_clock_0, , , );
|
| 9956 |
|
|
HE1_q_a[7]_PORT_A_write_enable = GND;
|
| 9957 |
|
|
HE1_q_a[7]_PORT_A_write_enable_reg = DFFE(HE1_q_a[7]_PORT_A_write_enable, HE1_q_a[7]_clock_0, , , );
|
| 9958 |
|
|
HE1_q_a[7]_PORT_B_write_enable = WB2L2;
|
| 9959 |
|
|
HE1_q_a[7]_PORT_B_write_enable_reg = DFFE(HE1_q_a[7]_PORT_B_write_enable, HE1_q_a[7]_clock_0, , , );
|
| 9960 |
|
|
HE1_q_a[7]_clock_0 = E1__clk0;
|
| 9961 |
|
|
HE1_q_a[7]_PORT_A_data_out = MEMORY(HE1_q_a[7]_PORT_A_data_in_reg, HE1_q_a[7]_PORT_B_data_in_reg, HE1_q_a[7]_PORT_A_address_reg, HE1_q_a[7]_PORT_B_address_reg, HE1_q_a[7]_PORT_A_write_enable_reg, HE1_q_a[7]_PORT_B_write_enable_reg, , , HE1_q_a[7]_clock_0, , , , , );
|
| 9962 |
|
|
HE1_q_a[7] = HE1_q_a[7]_PORT_A_data_out[0];
|
| 9963 |
|
|
|
| 9964 |
|
|
--HE1_q_b[7] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[7]
|
| 9965 |
|
|
HE1_q_b[7]_PORT_A_data_in = ~GND;
|
| 9966 |
|
|
HE1_q_b[7]_PORT_A_data_in_reg = DFFE(HE1_q_b[7]_PORT_A_data_in, HE1_q_b[7]_clock_0, , , );
|
| 9967 |
|
|
HE1_q_b[7]_PORT_B_data_in = TB1_dout_1_x_7;
|
| 9968 |
|
|
HE1_q_b[7]_PORT_B_data_in_reg = DFFE(HE1_q_b[7]_PORT_B_data_in, HE1_q_b[7]_clock_0, , , );
|
| 9969 |
|
|
HE1_q_b[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 9970 |
|
|
HE1_q_b[7]_PORT_A_address_reg = DFFE(HE1_q_b[7]_PORT_A_address, HE1_q_b[7]_clock_0, , , );
|
| 9971 |
|
|
HE1_q_b[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 9972 |
|
|
HE1_q_b[7]_PORT_B_address_reg = DFFE(HE1_q_b[7]_PORT_B_address, HE1_q_b[7]_clock_0, , , );
|
| 9973 |
|
|
HE1_q_b[7]_PORT_A_write_enable = GND;
|
| 9974 |
|
|
HE1_q_b[7]_PORT_A_write_enable_reg = DFFE(HE1_q_b[7]_PORT_A_write_enable, HE1_q_b[7]_clock_0, , , );
|
| 9975 |
|
|
HE1_q_b[7]_PORT_B_write_enable = WB2L2;
|
| 9976 |
|
|
HE1_q_b[7]_PORT_B_write_enable_reg = DFFE(HE1_q_b[7]_PORT_B_write_enable, HE1_q_b[7]_clock_0, , , );
|
| 9977 |
|
|
HE1_q_b[7]_clock_0 = E1__clk0;
|
| 9978 |
|
|
HE1_q_b[7]_PORT_B_data_out = MEMORY(HE1_q_b[7]_PORT_A_data_in_reg, HE1_q_b[7]_PORT_B_data_in_reg, HE1_q_b[7]_PORT_A_address_reg, HE1_q_b[7]_PORT_B_address_reg, HE1_q_b[7]_PORT_A_write_enable_reg, HE1_q_b[7]_PORT_B_write_enable_reg, , , HE1_q_b[7]_clock_0, , , , , );
|
| 9979 |
|
|
HE1_q_b[7] = HE1_q_b[7]_PORT_B_data_out[0];
|
| 9980 |
|
|
|
| 9981 |
|
|
|
| 9982 |
|
|
--KE1_q_a[7] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[7]
|
| 9983 |
|
|
--RAM Block Operation Mode: True Dual-Port
|
| 9984 |
|
|
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
|
| 9985 |
|
|
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
|
| 9986 |
|
|
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
|
| 9987 |
|
|
KE1_q_a[7]_PORT_A_data_in = ~GND;
|
| 9988 |
|
|
KE1_q_a[7]_PORT_A_data_in_reg = DFFE(KE1_q_a[7]_PORT_A_data_in, KE1_q_a[7]_clock_0, , , );
|
| 9989 |
|
|
KE1_q_a[7]_PORT_B_data_in = TB1_dout_1_2_7;
|
| 9990 |
|
|
KE1_q_a[7]_PORT_B_data_in_reg = DFFE(KE1_q_a[7]_PORT_B_data_in, KE1_q_a[7]_clock_0, , , );
|
| 9991 |
|
|
KE1_q_a[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 9992 |
|
|
KE1_q_a[7]_PORT_A_address_reg = DFFE(KE1_q_a[7]_PORT_A_address, KE1_q_a[7]_clock_0, , , );
|
| 9993 |
|
|
KE1_q_a[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 9994 |
|
|
KE1_q_a[7]_PORT_B_address_reg = DFFE(KE1_q_a[7]_PORT_B_address, KE1_q_a[7]_clock_0, , , );
|
| 9995 |
|
|
KE1_q_a[7]_PORT_A_write_enable = GND;
|
| 9996 |
|
|
KE1_q_a[7]_PORT_A_write_enable_reg = DFFE(KE1_q_a[7]_PORT_A_write_enable, KE1_q_a[7]_clock_0, , , );
|
| 9997 |
|
|
KE1_q_a[7]_PORT_B_write_enable = WB4L2;
|
| 9998 |
|
|
KE1_q_a[7]_PORT_B_write_enable_reg = DFFE(KE1_q_a[7]_PORT_B_write_enable, KE1_q_a[7]_clock_0, , , );
|
| 9999 |
|
|
KE1_q_a[7]_clock_0 = E1__clk0;
|
| 10000 |
|
|
KE1_q_a[7]_PORT_A_data_out = MEMORY(KE1_q_a[7]_PORT_A_data_in_reg, KE1_q_a[7]_PORT_B_data_in_reg, KE1_q_a[7]_PORT_A_address_reg, KE1_q_a[7]_PORT_B_address_reg, KE1_q_a[7]_PORT_A_write_enable_reg, KE1_q_a[7]_PORT_B_write_enable_reg, , , KE1_q_a[7]_clock_0, , , , , );
|
| 10001 |
|
|
KE1_q_a[7] = KE1_q_a[7]_PORT_A_data_out[0];
|
| 10002 |
|
|
|
| 10003 |
|
|
--KE1_q_b[7] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[7]
|
| 10004 |
|
|
KE1_q_b[7]_PORT_A_data_in = ~GND;
|
| 10005 |
|
|
KE1_q_b[7]_PORT_A_data_in_reg = DFFE(KE1_q_b[7]_PORT_A_data_in, KE1_q_b[7]_clock_0, , , );
|
| 10006 |
|
|
KE1_q_b[7]_PORT_B_data_in = TB1_dout_1_2_7;
|
| 10007 |
|
|
KE1_q_b[7]_PORT_B_data_in_reg = DFFE(KE1_q_b[7]_PORT_B_data_in, KE1_q_b[7]_clock_0, , , );
|
| 10008 |
|
|
KE1_q_b[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
|
| 10009 |
|
|
KE1_q_b[7]_PORT_A_address_reg = DFFE(KE1_q_b[7]_PORT_A_address, KE1_q_b[7]_clock_0, , , );
|
| 10010 |
|
|
KE1_q_b[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
|
| 10011 |
|
|
KE1_q_b[7]_PORT_B_address_reg = DFFE(KE1_q_b[7]_PORT_B_address, KE1_q_b[7]_clock_0, , , );
|
| 10012 |
|
|
KE1_q_b[7]_PORT_A_write_enable = GND;
|
| 10013 |
|
|
KE1_q_b[7]_PORT_A_write_enable_reg = DFFE(KE1_q_b[7]_PORT_A_write_enable, KE1_q_b[7]_clock_0, , , );
|
| 10014 |
|
|
KE1_q_b[7]_PORT_B_write_enable = WB4L2;
|
| 10015 |
|
|
KE1_q_b[7]_PORT_B_write_enable_reg = DFFE(KE1_q_b[7]_PORT_B_write_enable, KE1_q_b[7]_clock_0, , , );
|
| 10016 |
|
|
KE1_q_b[7]_clock_0 = E1__clk0;
|
| 10017 |
|
|
KE1_q_b[7]_PORT_B_data_out = MEMORY(KE1_q_b[7]_PORT_A_data_in_reg, KE1_q_b[7]_PORT_B_data_in_reg, KE1_q_b[7]_PORT_A_address_reg, KE1_q_b[7]_PORT_B_address_reg, KE1_q_b[7]_PORT_A_write_enable_reg, KE1_q_b[7]_PORT_B_write_enable_reg, , , KE1_q_b[7]_clock_0, , , , , );
|
| 10018 |
|
|
KE1_q_b[7] = KE1_q_b[7]_PORT_B_data_out[0];
|
| 10019 |
|
|
|
| 10020 |
|
|
|
| 10021 |
|
|
--UB1_dout_2_i_i_a2_1_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_1_a[7]
|
| 10022 |
|
|
--operation mode is normal
|
| 10023 |
|
|
|
| 10024 |
|
|
UB1_dout_2_i_i_a2_1_a[7] = !RB1_byte_addr_o_0 & RB1_ctl_o_1 & !RB1_ctl_o_3 & !RB1_ctl_o_2 # !RB1_ctl_o_1 & RB1_ctl_o_2;
|
| 10025 |
|
|
|
| 10026 |
|
|
|
| 10027 |
|
|
--UB1_dout_2_i_i_o2_0_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_o2_0_a[7]
|
| 10028 |
|
|
--operation mode is normal
|
| 10029 |
|
|
|
| 10030 |
|
|
UB1_dout_2_i_i_o2_0_a[7] = RB1_ctl_o_1 & RB1_byte_addr_o_0 & !RB1_ctl_o_2 # !RB1_byte_addr_o_0 & RB1_ctl_o_3 # !RB1_ctl_o_1 & RB1_byte_addr_o_0;
|
| 10031 |
|
|
|
| 10032 |
|
|
|
| 10033 |
|
|
--YB1_wb_mux_1_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_mux_1_0_0_0
|
| 10034 |
|
|
--operation mode is normal
|
| 10035 |
|
|
|
| 10036 |
|
|
YB1_wb_mux_1_0_0_0 = YB1_wb_mux_1_0_0_a3[0] # YB1_alu_func_2_0_0_a2_0[1] & WB56L1 & YB1_fsm_dly_2_0_0_o2_x[2];
|
| 10037 |
|
|
|
| 10038 |
|
|
|
| 10039 |
|
|
--WB56L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_mux_0_|lpm_latch:U1|q[0]~56
|
| 10040 |
|
|
--operation mode is normal
|
| 10041 |
|
|
|
| 10042 |
|
|
WB56L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_wb_mux_1_0_0_0 # !YB1_un1_muxa_ctl370_x & WB56L1;
|
| 10043 |
|
|
|
| 10044 |
|
|
|
| 10045 |
|
|
--FD1_r_wraddress[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[1]
|
| 10046 |
|
|
--operation mode is normal
|
| 10047 |
|
|
|
| 10048 |
|
|
FD1_r_wraddress[1]_lut_out = NB1_r5_o_1;
|
| 10049 |
|
|
FD1_r_wraddress[1] = DFFEAS(FD1_r_wraddress[1]_lut_out, E1__clk0, VCC, , , , , , );
|
| 10050 |
|
|
|
| 10051 |
|
|
|
| 10052 |
|
|
--FD1_r_wraddress[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[0]
|
| 10053 |
|
|
--operation mode is normal
|
| 10054 |
|
|
|
| 10055 |
|
|
FD1_r_wraddress[0]_lut_out = NB1_r5_o_0;
|
| 10056 |
|
|
FD1_r_wraddress[0] = DFFEAS(FD1_r_wraddress[0]_lut_out, E1__clk0, VCC, , , , , , );
|
| 10057 |
|
|
|
| 10058 |
|
|
|
| 10059 |
|
|
--FD1_r_wraddress[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[2]
|
| 10060 |
|
|
--operation mode is normal
|
| 10061 |
|
|
|
| 10062 |
|
|
FD1_r_wraddress[2]_lut_out = NB1_r5_o_2;
|
| 10063 |
|
|
FD1_r_wraddress[2] = DFFEAS(FD1_r_wraddress[2]_lut_out, E1__clk0, VCC, , , , , , );
|
| 10064 |
|
|
|
| 10065 |
|
|
|
| 10066 |
|
|
--FD1_r_wraddress[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[3]
|
| 10067 |
|
|
--operation mode is normal
|
| 10068 |
|
|
|
| 10069 |
|
|
FD1_r_wraddress[3]_lut_out = NB1_r5_o_3;
|
| 10070 |
|
|
FD1_r_wraddress[3] = DFFEAS(FD1_r_wraddress[3]_lut_out, E1__clk0, VCC, , , , , , );
|
| 10071 |
|
|
|
| 10072 |
|
|
|
| 10073 |
|
|
--QB1_dout_iv_9 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_9
|
| 10074 |
|
|
--operation mode is normal
|
| 10075 |
|
|
|
| 10076 |
|
|
QB1_dout_iv_9 = GD1_dout_iv_1_9 # FD1_wb_o_9 & GD1_dout7_0_a2;
|
| 10077 |
|
|
|
| 10078 |
|
|
--QB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_9
|
| 10079 |
|
|
--operation mode is normal
|
| 10080 |
|
|
|
| 10081 |
|
|
QB1_r32_o_9 = DFFEAS(QB1_dout_iv_9, E1__clk0, VCC, , , , , , );
|
| 10082 |
|
|
|
| 10083 |
|
|
|
| 10084 |
|
|
--FB1_res_7_0_0_9 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_9
|
| 10085 |
|
|
--operation mode is normal
|
| 10086 |
|
|
|
| 10087 |
|
|
FB1_res_7_0_0_9 = ED1_r32_o_7 & CD1_res_7_0_0_o3_0 # ED1_r32_o_9 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_7 & ED1_r32_o_9 & CD1_res_7_0_0_a2_0;
|
| 10088 |
|
|
|
| 10089 |
|
|
--FB1_r32_o_0_9 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_9
|
| 10090 |
|
|
--operation mode is normal
|
| 10091 |
|
|
|
| 10092 |
|
|
FB1_r32_o_0_9 = DFFEAS(FB1_res_7_0_0_9, E1__clk0, VCC, , , , , , );
|
| 10093 |
|
|
|
| 10094 |
|
|
|
| 10095 |
|
|
--FD1_wb_o_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_9
|
| 10096 |
|
|
--operation mode is normal
|
| 10097 |
|
|
|
| 10098 |
|
|
FD1_wb_o_9 = TC1_wb_mux_ctl_o_0 & F1_dout_9 # DB1_r32_o_9 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_9;
|
| 10099 |
|
|
|
| 10100 |
|
|
--FD1_r_data_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_9
|
| 10101 |
|
|
--operation mode is normal
|
| 10102 |
|
|
|
| 10103 |
|
|
FD1_r_data_9 = DFFEAS(FD1_wb_o_9, E1__clk0, VCC, , , , , , );
|
| 10104 |
|
|
|
| 10105 |
|
|
|
| 10106 |
|
|
--VD1_b_o_iv_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_11
|
| 10107 |
|
|
--operation mode is normal
|
| 10108 |
|
|
|
| 10109 |
|
|
VD1_b_o_iv_11 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[11] & !G1_BUS15471_i_m[11] & AB1_r32_o_9 # !QD1_b_o_0_sqmuxa;
|
| 10110 |
|
|
|
| 10111 |
|
|
--VD1_op2_reged[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[11]
|
| 10112 |
|
|
--operation mode is normal
|
| 10113 |
|
|
|
| 10114 |
|
|
VD1_op2_reged[11] = DFFEAS(VD1_b_o_iv_11, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10115 |
|
|
|
| 10116 |
|
|
|
| 10117 |
|
|
--VD1_b_o_iv_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_13
|
| 10118 |
|
|
--operation mode is normal
|
| 10119 |
|
|
|
| 10120 |
|
|
VD1_b_o_iv_13 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[13] & !G1_BUS15471_i_m[13] & AB1_r32_o_11 # !QD1_b_o_0_sqmuxa;
|
| 10121 |
|
|
|
| 10122 |
|
|
--VD1_op2_reged[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[13]
|
| 10123 |
|
|
--operation mode is normal
|
| 10124 |
|
|
|
| 10125 |
|
|
VD1_op2_reged[13] = DFFEAS(VD1_b_o_iv_13, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10126 |
|
|
|
| 10127 |
|
|
|
| 10128 |
|
|
--VD1_b_o_iv_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_12
|
| 10129 |
|
|
--operation mode is normal
|
| 10130 |
|
|
|
| 10131 |
|
|
VD1_b_o_iv_12 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[12] & !G1_BUS15471_i_m[12] & AB1_r32_o_10 # !QD1_b_o_0_sqmuxa;
|
| 10132 |
|
|
|
| 10133 |
|
|
--VD1_op2_reged[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[12]
|
| 10134 |
|
|
--operation mode is normal
|
| 10135 |
|
|
|
| 10136 |
|
|
VD1_op2_reged[12] = DFFEAS(VD1_b_o_iv_12, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10137 |
|
|
|
| 10138 |
|
|
|
| 10139 |
|
|
--VD1_b_o_iv_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_14
|
| 10140 |
|
|
--operation mode is normal
|
| 10141 |
|
|
|
| 10142 |
|
|
VD1_b_o_iv_14 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[14] & !G1_BUS15471_i_m[14] & AB1_r32_o_12 # !QD1_b_o_0_sqmuxa;
|
| 10143 |
|
|
|
| 10144 |
|
|
--VD1_op2_reged[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[14]
|
| 10145 |
|
|
--operation mode is normal
|
| 10146 |
|
|
|
| 10147 |
|
|
VD1_op2_reged[14] = DFFEAS(VD1_b_o_iv_14, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10148 |
|
|
|
| 10149 |
|
|
|
| 10150 |
|
|
--UD1_shift_out_80_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[7]
|
| 10151 |
|
|
--operation mode is normal
|
| 10152 |
|
|
|
| 10153 |
|
|
UD1_shift_out_80_a[7] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_10 # !PD1_a_o_1 & !VD1_b_o_iv_8;
|
| 10154 |
|
|
|
| 10155 |
|
|
|
| 10156 |
|
|
--FB1_res_7_0_0_6 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_6
|
| 10157 |
|
|
--operation mode is normal
|
| 10158 |
|
|
|
| 10159 |
|
|
FB1_res_7_0_0_6 = ED1_r32_o_4 & CD1_res_7_0_0_o3_0 # ED1_r32_o_6 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_4 & ED1_r32_o_6 & CD1_res_7_0_0_a2_0;
|
| 10160 |
|
|
|
| 10161 |
|
|
--FB1_r32_o_0_6 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_6
|
| 10162 |
|
|
--operation mode is normal
|
| 10163 |
|
|
|
| 10164 |
|
|
FB1_r32_o_0_6 = DFFEAS(FB1_res_7_0_0_6, E1__clk0, VCC, , , , , , );
|
| 10165 |
|
|
|
| 10166 |
|
|
|
| 10167 |
|
|
--UD1_shift_out_43_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43_a[31]
|
| 10168 |
|
|
--operation mode is normal
|
| 10169 |
|
|
|
| 10170 |
|
|
UD1_shift_out_43_a[31] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_0 # !PD1_a_o_0 & !VD1_b_o_iv_1 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 10171 |
|
|
|
| 10172 |
|
|
|
| 10173 |
|
|
--ED1_r32_o_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_0
|
| 10174 |
|
|
--operation mode is normal
|
| 10175 |
|
|
|
| 10176 |
|
|
ED1_r32_o_0_lut_out = GE1_q_a[0];
|
| 10177 |
|
|
ED1_r32_o_0 = DFFEAS(ED1_r32_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10178 |
|
|
|
| 10179 |
|
|
|
| 10180 |
|
|
--CD1_res_7_0_0_0_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_0
|
| 10181 |
|
|
--operation mode is normal
|
| 10182 |
|
|
|
| 10183 |
|
|
CD1_res_7_0_0_0_0 = ED1_r32_o_2 & CD1_res_7_0_0_a2_0 # ED1_r32_o_8 & CD1_res_7_0_0_0_a_0 # !ED1_r32_o_2 & ED1_r32_o_8 & CD1_res_7_0_0_0_a_0;
|
| 10184 |
|
|
|
| 10185 |
|
|
|
| 10186 |
|
|
--PD1_a_o_3_d_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[2]
|
| 10187 |
|
|
--operation mode is normal
|
| 10188 |
|
|
|
| 10189 |
|
|
PD1_a_o_3_d_a[2] = PD1_a_o_sn_m2 & !PB1_r32_o_2 # !PD1_a_o_sn_m2 & !AB1_r32_o_0;
|
| 10190 |
|
|
|
| 10191 |
|
|
|
| 10192 |
|
|
--ED1_r32_o_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_7
|
| 10193 |
|
|
--operation mode is normal
|
| 10194 |
|
|
|
| 10195 |
|
|
ED1_r32_o_7_lut_out = GE1_q_a[7];
|
| 10196 |
|
|
ED1_r32_o_7 = DFFEAS(ED1_r32_o_7_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10197 |
|
|
|
| 10198 |
|
|
|
| 10199 |
|
|
--ED1_r32_o_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_1
|
| 10200 |
|
|
--operation mode is normal
|
| 10201 |
|
|
|
| 10202 |
|
|
ED1_r32_o_1_lut_out = GE1_q_a[1];
|
| 10203 |
|
|
ED1_r32_o_1 = DFFEAS(ED1_r32_o_1_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10204 |
|
|
|
| 10205 |
|
|
|
| 10206 |
|
|
--CD1_res_7_0_0_0_a_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_a_0
|
| 10207 |
|
|
--operation mode is normal
|
| 10208 |
|
|
|
| 10209 |
|
|
CD1_res_7_0_0_0_a_0 = !DC1_ext_ctl_o_1 & DC1_ext_ctl_o_2 & DC1_ext_ctl_o_0;
|
| 10210 |
|
|
|
| 10211 |
|
|
|
| 10212 |
|
|
--DD1_pc_next_0_iv_1_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_1
|
| 10213 |
|
|
--operation mode is normal
|
| 10214 |
|
|
|
| 10215 |
|
|
DD1_pc_next_0_iv_1_1 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_1 # !DD1_pc_next_0_iv_1_a[1];
|
| 10216 |
|
|
|
| 10217 |
|
|
|
| 10218 |
|
|
--DD1_un1_pc_add1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add1
|
| 10219 |
|
|
--operation mode is arithmetic
|
| 10220 |
|
|
|
| 10221 |
|
|
DD1_un1_pc_add1_carry_eqn = DD1_un1_pc_carry_0;
|
| 10222 |
|
|
DD1_un1_pc_add1 = KB1_r32_o_1 $ DD1_un1_pc_prectl_1_0_a4[1] $ DD1_un1_pc_add1_carry_eqn;
|
| 10223 |
|
|
|
| 10224 |
|
|
--DD1_un1_pc_carry_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_1
|
| 10225 |
|
|
--operation mode is arithmetic
|
| 10226 |
|
|
|
| 10227 |
|
|
DD1_un1_pc_carry_1 = CARRY(KB1_r32_o_1 & !DD1_un1_pc_prectl_1_0_a4[1] & !DD1_un1_pc_carry_0 # !KB1_r32_o_1 & !DD1_un1_pc_carry_0 # !DD1_un1_pc_prectl_1_0_a4[1]);
|
| 10228 |
|
|
|
| 10229 |
|
|
|
| 10230 |
|
|
--PD1_a_o_3_d_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[1]
|
| 10231 |
|
|
--operation mode is normal
|
| 10232 |
|
|
|
| 10233 |
|
|
PD1_a_o_3_d_a[1] = PD1_a_o_sn_m2 & !PB1_r32_o_1 # !PD1_a_o_sn_m2 & !RB1_byte_addr_o_1;
|
| 10234 |
|
|
|
| 10235 |
|
|
|
| 10236 |
|
|
--ED1_r32_o_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_6
|
| 10237 |
|
|
--operation mode is normal
|
| 10238 |
|
|
|
| 10239 |
|
|
ED1_r32_o_6_lut_out = GE1_q_a[6];
|
| 10240 |
|
|
ED1_r32_o_6 = DFFEAS(ED1_r32_o_6_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10241 |
|
|
|
| 10242 |
|
|
|
| 10243 |
|
|
--DD1_pc_next_0_iv_1_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_0
|
| 10244 |
|
|
--operation mode is normal
|
| 10245 |
|
|
|
| 10246 |
|
|
DD1_pc_next_0_iv_1_0 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_0 # !DD1_pc_next_0_iv_1_a[0];
|
| 10247 |
|
|
|
| 10248 |
|
|
|
| 10249 |
|
|
--DD1_un1_pc_add0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add0
|
| 10250 |
|
|
--operation mode is arithmetic
|
| 10251 |
|
|
|
| 10252 |
|
|
DD1_un1_pc_add0 = KB1_r32_o_0 $ DD1_un1_pc_prectl_1_0_a4[0];
|
| 10253 |
|
|
|
| 10254 |
|
|
--DD1_un1_pc_carry_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_0
|
| 10255 |
|
|
--operation mode is arithmetic
|
| 10256 |
|
|
|
| 10257 |
|
|
DD1_un1_pc_carry_0 = CARRY(KB1_r32_o_0 & DD1_un1_pc_prectl_1_0_a4[0]);
|
| 10258 |
|
|
|
| 10259 |
|
|
|
| 10260 |
|
|
--PD1_a_o_3_d_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[0]
|
| 10261 |
|
|
--operation mode is normal
|
| 10262 |
|
|
|
| 10263 |
|
|
PD1_a_o_3_d_a[0] = PD1_a_o_sn_m2 & !PB1_r32_o_0 # !PD1_a_o_sn_m2 & !RB1_byte_addr_o_0;
|
| 10264 |
|
|
|
| 10265 |
|
|
|
| 10266 |
|
|
--VD1_b_o_iv_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_21
|
| 10267 |
|
|
--operation mode is normal
|
| 10268 |
|
|
|
| 10269 |
|
|
VD1_b_o_iv_21 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[21] & !G1_BUS15471_i_m[21] & AB1_r32_o_19 # !QD1_b_o_0_sqmuxa;
|
| 10270 |
|
|
|
| 10271 |
|
|
--VD1_op2_reged[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[21]
|
| 10272 |
|
|
--operation mode is normal
|
| 10273 |
|
|
|
| 10274 |
|
|
VD1_op2_reged[21] = DFFEAS(VD1_b_o_iv_21, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10275 |
|
|
|
| 10276 |
|
|
|
| 10277 |
|
|
--VD1_b_o_iv_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_22
|
| 10278 |
|
|
--operation mode is normal
|
| 10279 |
|
|
|
| 10280 |
|
|
VD1_b_o_iv_22 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[22] & !G1_BUS15471_i_m[22] & AB1_r32_o_20 # !QD1_b_o_0_sqmuxa;
|
| 10281 |
|
|
|
| 10282 |
|
|
--VD1_op2_reged[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[22]
|
| 10283 |
|
|
--operation mode is normal
|
| 10284 |
|
|
|
| 10285 |
|
|
VD1_op2_reged[22] = DFFEAS(VD1_b_o_iv_22, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10286 |
|
|
|
| 10287 |
|
|
|
| 10288 |
|
|
--UD1_shift_out_79_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[11]
|
| 10289 |
|
|
--operation mode is normal
|
| 10290 |
|
|
|
| 10291 |
|
|
UD1_shift_out_79_a[11] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_20 # !PD1_a_o_0 & !VD1_b_o_iv_19;
|
| 10292 |
|
|
|
| 10293 |
|
|
|
| 10294 |
|
|
--VD1_b_o_iv_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_25
|
| 10295 |
|
|
--operation mode is normal
|
| 10296 |
|
|
|
| 10297 |
|
|
VD1_b_o_iv_25 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[25] & !G1_BUS15471_i_m[25] & AB1_r32_o_23 # !QD1_b_o_0_sqmuxa;
|
| 10298 |
|
|
|
| 10299 |
|
|
--VD1_op2_reged[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[25]
|
| 10300 |
|
|
--operation mode is normal
|
| 10301 |
|
|
|
| 10302 |
|
|
VD1_op2_reged[25] = DFFEAS(VD1_b_o_iv_25, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10303 |
|
|
|
| 10304 |
|
|
|
| 10305 |
|
|
--VD1_b_o_iv_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_26
|
| 10306 |
|
|
--operation mode is normal
|
| 10307 |
|
|
|
| 10308 |
|
|
VD1_b_o_iv_26 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[26] & !G1_BUS15471_i_m[26] & AB1_r32_o_24 # !QD1_b_o_0_sqmuxa;
|
| 10309 |
|
|
|
| 10310 |
|
|
--VD1_op2_reged[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[26]
|
| 10311 |
|
|
--operation mode is normal
|
| 10312 |
|
|
|
| 10313 |
|
|
VD1_op2_reged[26] = DFFEAS(VD1_b_o_iv_26, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10314 |
|
|
|
| 10315 |
|
|
|
| 10316 |
|
|
--UD1_shift_out_79_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[15]
|
| 10317 |
|
|
--operation mode is normal
|
| 10318 |
|
|
|
| 10319 |
|
|
UD1_shift_out_79_a[15] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_24 # !PD1_a_o_0 & !VD1_b_o_iv_23;
|
| 10320 |
|
|
|
| 10321 |
|
|
|
| 10322 |
|
|
--VD1_b_o_iv_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_29
|
| 10323 |
|
|
--operation mode is normal
|
| 10324 |
|
|
|
| 10325 |
|
|
VD1_b_o_iv_29 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[29] & !G1_BUS15471_i_m[29] & AB1_r32_o_27 # !QD1_b_o_0_sqmuxa;
|
| 10326 |
|
|
|
| 10327 |
|
|
--VD1_op2_reged[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[29]
|
| 10328 |
|
|
--operation mode is normal
|
| 10329 |
|
|
|
| 10330 |
|
|
VD1_op2_reged[29] = DFFEAS(VD1_b_o_iv_29, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10331 |
|
|
|
| 10332 |
|
|
|
| 10333 |
|
|
--UD1_shift_out_79_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[19]
|
| 10334 |
|
|
--operation mode is normal
|
| 10335 |
|
|
|
| 10336 |
|
|
UD1_shift_out_79_a[19] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_28 # !PD1_a_o_0 & !VD1_b_o_iv_27;
|
| 10337 |
|
|
|
| 10338 |
|
|
|
| 10339 |
|
|
--VD1_b_o_iv_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_17
|
| 10340 |
|
|
--operation mode is normal
|
| 10341 |
|
|
|
| 10342 |
|
|
VD1_b_o_iv_17 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[17] & !G1_BUS15471_i_m[17] & AB1_r32_o_15 # !QD1_b_o_0_sqmuxa;
|
| 10343 |
|
|
|
| 10344 |
|
|
--VD1_op2_reged[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[17]
|
| 10345 |
|
|
--operation mode is normal
|
| 10346 |
|
|
|
| 10347 |
|
|
VD1_op2_reged[17] = DFFEAS(VD1_b_o_iv_17, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10348 |
|
|
|
| 10349 |
|
|
|
| 10350 |
|
|
--VD1_b_o_iv_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_18
|
| 10351 |
|
|
--operation mode is normal
|
| 10352 |
|
|
|
| 10353 |
|
|
VD1_b_o_iv_18 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[18] & !G1_BUS15471_i_m[18] & AB1_r32_o_16 # !QD1_b_o_0_sqmuxa;
|
| 10354 |
|
|
|
| 10355 |
|
|
--VD1_op2_reged[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[18]
|
| 10356 |
|
|
--operation mode is normal
|
| 10357 |
|
|
|
| 10358 |
|
|
VD1_op2_reged[18] = DFFEAS(VD1_b_o_iv_18, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10359 |
|
|
|
| 10360 |
|
|
|
| 10361 |
|
|
--UD1_shift_out_79_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[7]
|
| 10362 |
|
|
--operation mode is normal
|
| 10363 |
|
|
|
| 10364 |
|
|
UD1_shift_out_79_a[7] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_16 # !PD1_a_o_0 & !VD1_b_o_iv_15;
|
| 10365 |
|
|
|
| 10366 |
|
|
|
| 10367 |
|
|
--UD1_shift_out_39[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_39[19]
|
| 10368 |
|
|
--operation mode is normal
|
| 10369 |
|
|
|
| 10370 |
|
|
UD1_shift_out_39[19] = VD1_b_o_iv_31 & !PD1_a_o_0;
|
| 10371 |
|
|
|
| 10372 |
|
|
|
| 10373 |
|
|
--VD1_hilo_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8
|
| 10374 |
|
|
--operation mode is normal
|
| 10375 |
|
|
|
| 10376 |
|
|
VD1_hilo_8_lut_out = VD1_hilo_37_iv_0[8] # VD1_hilo25 & VD1_hilo_8_Z[8] # !VD1_hilo_37_iv_a[8];
|
| 10377 |
|
|
VD1_hilo_8 = DFFEAS(VD1_hilo_8_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 10378 |
|
|
|
| 10379 |
|
|
|
| 10380 |
|
|
--VD1_hilo_3_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_3_sqmuxa
|
| 10381 |
|
|
--operation mode is normal
|
| 10382 |
|
|
|
| 10383 |
|
|
VD1_hilo_3_sqmuxa = VD1_count[5] & VD1_finish & VD1_addnop2110;
|
| 10384 |
|
|
|
| 10385 |
|
|
|
| 10386 |
|
|
--VD1_hilo_37_iv_0_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[7]
|
| 10387 |
|
|
--operation mode is normal
|
| 10388 |
|
|
|
| 10389 |
|
|
VD1_hilo_37_iv_0_a[7] = VD1_add1 & !VD1_un134_hilo_combout[7] # !VD1_add1 & !VD1_hilo_7;
|
| 10390 |
|
|
|
| 10391 |
|
|
|
| 10392 |
|
|
--VD1_hilo_40 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_40
|
| 10393 |
|
|
--operation mode is normal
|
| 10394 |
|
|
|
| 10395 |
|
|
VD1_hilo_40_lut_out = !VD1_hilo_37_iv_0_a6_3[40] & !VD1_hilo_37_iv_0_5[40] & !VD1_hilo_37_iv_0_a[40] & !VD1_hilo_37_iv_0_a3[57];
|
| 10396 |
|
|
VD1_hilo_40 = DFFEAS(VD1_hilo_40_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 10397 |
|
|
|
| 10398 |
|
|
|
| 10399 |
|
|
--VD1_hilo_37_iv_0_a3_4[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_4[57]
|
| 10400 |
|
|
--operation mode is normal
|
| 10401 |
|
|
|
| 10402 |
|
|
VD1_hilo_37_iv_0_a3_4[57] = VD1_sign & !VD1_sub_or_yn & VD1_hilo[0] & VD1_hilo_1_sqmuxa_1;
|
| 10403 |
|
|
|
| 10404 |
|
|
|
| 10405 |
|
|
--VD1_un50_hilo_add8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add8
|
| 10406 |
|
|
--operation mode is arithmetic
|
| 10407 |
|
|
|
| 10408 |
|
|
VD1_un50_hilo_add8_carry_eqn = VD1_un50_hilo_carry_7;
|
| 10409 |
|
|
VD1_un50_hilo_add8 = VD1_hilo_40 $ VD1_nop2_reged[8] $ !VD1_un50_hilo_add8_carry_eqn;
|
| 10410 |
|
|
|
| 10411 |
|
|
--VD1_un50_hilo_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_8
|
| 10412 |
|
|
--operation mode is arithmetic
|
| 10413 |
|
|
|
| 10414 |
|
|
VD1_un50_hilo_carry_8 = CARRY(VD1_hilo_40 & VD1_nop2_reged[8] # !VD1_un50_hilo_carry_7 # !VD1_hilo_40 & VD1_nop2_reged[8] & !VD1_un50_hilo_carry_7);
|
| 10415 |
|
|
|
| 10416 |
|
|
|
| 10417 |
|
|
--VD1_un59_hilo_add8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add8
|
| 10418 |
|
|
--operation mode is arithmetic
|
| 10419 |
|
|
|
| 10420 |
|
|
VD1_un59_hilo_add8_carry_eqn = VD1_un59_hilo_carry_7;
|
| 10421 |
|
|
VD1_un59_hilo_add8 = VD1_hilo_40 $ VD1_op2_reged[8] $ !VD1_un59_hilo_add8_carry_eqn;
|
| 10422 |
|
|
|
| 10423 |
|
|
--VD1_un59_hilo_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_8
|
| 10424 |
|
|
--operation mode is arithmetic
|
| 10425 |
|
|
|
| 10426 |
|
|
VD1_un59_hilo_carry_8 = CARRY(VD1_hilo_40 & VD1_op2_reged[8] # !VD1_un59_hilo_carry_7 # !VD1_hilo_40 & VD1_op2_reged[8] & !VD1_un59_hilo_carry_7);
|
| 10427 |
|
|
|
| 10428 |
|
|
|
| 10429 |
|
|
--VD1_hilo_37_iv_0_1[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[39]
|
| 10430 |
|
|
--operation mode is normal
|
| 10431 |
|
|
|
| 10432 |
|
|
VD1_hilo_37_iv_0_1[39] = VD1_hilo_37_iv_0_a2_0[38] # VD1_hilo_37_iv_0_a2_1[39] # !VD1_un59_hilo_add7 & VD1_hilo_37_iv_0_a3_2[62];
|
| 10433 |
|
|
|
| 10434 |
|
|
|
| 10435 |
|
|
--VD1_hilo_37_iv_0_4_a[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4_a[39]
|
| 10436 |
|
|
--operation mode is normal
|
| 10437 |
|
|
|
| 10438 |
|
|
VD1_hilo_37_iv_0_4_a[39] = VD1_hilo_39 & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add7 # !VD1_hilo_39 & VD1_hilo_37_iv_0_o3_2[34] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add7;
|
| 10439 |
|
|
|
| 10440 |
|
|
|
| 10441 |
|
|
--VD1_hilo_24_add7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add7
|
| 10442 |
|
|
--operation mode is arithmetic
|
| 10443 |
|
|
|
| 10444 |
|
|
VD1_hilo_24_add7_carry_eqn = VD1_hilo_24_carry_6;
|
| 10445 |
|
|
VD1_hilo_24_add7 = VD1_hilo_38 $ VD1_un1_op2_reged_1_combout[7] $ VD1_hilo_24_add7_carry_eqn;
|
| 10446 |
|
|
|
| 10447 |
|
|
--VD1_hilo_24_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_7
|
| 10448 |
|
|
--operation mode is arithmetic
|
| 10449 |
|
|
|
| 10450 |
|
|
VD1_hilo_24_carry_7 = CARRY(VD1_hilo_38 & !VD1_un1_op2_reged_1_combout[7] & !VD1_hilo_24_carry_6 # !VD1_hilo_38 & !VD1_hilo_24_carry_6 # !VD1_un1_op2_reged_1_combout[7]);
|
| 10451 |
|
|
|
| 10452 |
|
|
|
| 10453 |
|
|
--RD1_r32_o_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_7
|
| 10454 |
|
|
--operation mode is arithmetic
|
| 10455 |
|
|
|
| 10456 |
|
|
RD1_r32_o_7_carry_eqn = RD1_r32_o_cout[5];
|
| 10457 |
|
|
RD1_r32_o_7_lut_out = KB1_r32_o_7 $ (KB1_r32_o_6 & !RD1_r32_o_7_carry_eqn);
|
| 10458 |
|
|
RD1_r32_o_7 = DFFEAS(RD1_r32_o_7_lut_out, E1__clk0, VCC, , , , , , );
|
| 10459 |
|
|
|
| 10460 |
|
|
--RD1_r32_o_cout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[7]
|
| 10461 |
|
|
--operation mode is arithmetic
|
| 10462 |
|
|
|
| 10463 |
|
|
RD1_r32_o_cout[7] = CARRY(KB1_r32_o_6 & KB1_r32_o_7 & !RD1_r32_o_cout[5]);
|
| 10464 |
|
|
|
| 10465 |
|
|
|
| 10466 |
|
|
--FB1_res_7_0_0_7 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_7
|
| 10467 |
|
|
--operation mode is normal
|
| 10468 |
|
|
|
| 10469 |
|
|
FB1_res_7_0_0_7 = ED1_r32_o_5 & CD1_res_7_0_0_o3_0 # ED1_r32_o_7 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_5 & ED1_r32_o_7 & CD1_res_7_0_0_a2_0;
|
| 10470 |
|
|
|
| 10471 |
|
|
--FB1_r32_o_0_7 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_7
|
| 10472 |
|
|
--operation mode is normal
|
| 10473 |
|
|
|
| 10474 |
|
|
FB1_r32_o_0_7 = DFFEAS(FB1_res_7_0_0_7, E1__clk0, VCC, , , , , , );
|
| 10475 |
|
|
|
| 10476 |
|
|
|
| 10477 |
|
|
--SD1_r32_o_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_7
|
| 10478 |
|
|
--operation mode is normal
|
| 10479 |
|
|
|
| 10480 |
|
|
SD1_r32_o_7_lut_out = KB1_r32_o_7;
|
| 10481 |
|
|
SD1_r32_o_7 = DFFEAS(SD1_r32_o_7_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 10482 |
|
|
|
| 10483 |
|
|
|
| 10484 |
|
|
--PD1_a_o_3_d[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[7]
|
| 10485 |
|
|
--operation mode is normal
|
| 10486 |
|
|
|
| 10487 |
|
|
PD1_a_o_3_d[7] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_7 # !PD1_un6_a_o & !PD1_a_o_3_d_a[7] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[7];
|
| 10488 |
|
|
|
| 10489 |
|
|
|
| 10490 |
|
|
--YB1_wb_we_1_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_we_1_0_0_0
|
| 10491 |
|
|
--operation mode is normal
|
| 10492 |
|
|
|
| 10493 |
|
|
YB1_wb_we_1_0_0_0 = WB66L1 & YB1_alu_func_2_0_0_a2_0[1] & YB1_fsm_dly_2_0_0_o2_x[2] # !YB1_wb_we_1_0_0_a[0];
|
| 10494 |
|
|
|
| 10495 |
|
|
|
| 10496 |
|
|
--WB66L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_we_0_|lpm_latch:U1|q[0]~56
|
| 10497 |
|
|
--operation mode is normal
|
| 10498 |
|
|
|
| 10499 |
|
|
WB66L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_wb_we_1_0_0_0 # !YB1_un1_muxa_ctl370_x & WB66L1;
|
| 10500 |
|
|
|
| 10501 |
|
|
|
| 10502 |
|
|
--YB1_alu_we_1_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_0
|
| 10503 |
|
|
--operation mode is normal
|
| 10504 |
|
|
|
| 10505 |
|
|
YB1_alu_we_1_0_0_0 = KE1_q_a[5] # YB1_alu_we_1_0_0_0_Z[0] # YB1_alu_we_1_0_0_a3[0] # YB1_alu_func_2_0_0_a3_1[1];
|
| 10506 |
|
|
|
| 10507 |
|
|
|
| 10508 |
|
|
--WB24L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_we_0_|lpm_latch:U1|q[0]~56
|
| 10509 |
|
|
--operation mode is normal
|
| 10510 |
|
|
|
| 10511 |
|
|
WB24L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_alu_we_1_0_0_0 # !YB1_un1_muxa_ctl370_x & WB24L1;
|
| 10512 |
|
|
|
| 10513 |
|
|
|
| 10514 |
|
|
--SB1_un1_ctl_1_combout is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_ctl_1_combout
|
| 10515 |
|
|
--operation mode is normal
|
| 10516 |
|
|
|
| 10517 |
|
|
SB1_un1_ctl_1_combout = !QC1_dmem_ctl_o_1 & QC1_dmem_ctl_o_2;
|
| 10518 |
|
|
|
| 10519 |
|
|
|
| 10520 |
|
|
--WB3L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1|q[0]~84
|
| 10521 |
|
|
--operation mode is normal
|
| 10522 |
|
|
|
| 10523 |
|
|
WB3L1 = SB1_un1_ctl_1_combout # SB1_un1_addr_i_1_combout & !RB1_c_1 # !SB1_un1_addr_i_1_combout & WB3L2;
|
| 10524 |
|
|
|
| 10525 |
|
|
|
| 10526 |
|
|
--WB3L2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1|q[0]~85
|
| 10527 |
|
|
--operation mode is normal
|
| 10528 |
|
|
|
| 10529 |
|
|
WB3L2 = WB3L1 & !SB1_un1_wr_en46_4_combout;
|
| 10530 |
|
|
|
| 10531 |
|
|
|
| 10532 |
|
|
--TB1_dout21 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout21
|
| 10533 |
|
|
--operation mode is normal
|
| 10534 |
|
|
|
| 10535 |
|
|
TB1_dout21 = !QC1_dmem_ctl_o_3 & !QC1_dmem_ctl_o_1 & QC1_dmem_ctl_o_0 & !QC1_dmem_ctl_o_2;
|
| 10536 |
|
|
|
| 10537 |
|
|
|
| 10538 |
|
|
--TB1_dout22 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout22
|
| 10539 |
|
|
--operation mode is normal
|
| 10540 |
|
|
|
| 10541 |
|
|
TB1_dout22 = !QC1_dmem_ctl_o_3 & QC1_dmem_ctl_o_1 & QC1_dmem_ctl_o_0 & QC1_dmem_ctl_o_2;
|
| 10542 |
|
|
|
| 10543 |
|
|
|
| 10544 |
|
|
--CB1_dout_2_20 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_20
|
| 10545 |
|
|
--operation mode is normal
|
| 10546 |
|
|
|
| 10547 |
|
|
CB1_dout_2_20 = ND1_dout7 & FD1_wb_o_20 # !ND1_dout7 & !ND1_dout_2_a_20;
|
| 10548 |
|
|
|
| 10549 |
|
|
--CB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_20
|
| 10550 |
|
|
--operation mode is normal
|
| 10551 |
|
|
|
| 10552 |
|
|
CB1_r32_o_20 = DFFEAS(CB1_dout_2_20, E1__clk0, VCC, , , , , , );
|
| 10553 |
|
|
|
| 10554 |
|
|
|
| 10555 |
|
|
--AD1_CurrState_Sreg0_ns_0_i_o2[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_i_o2[0]
|
| 10556 |
|
|
--operation mode is normal
|
| 10557 |
|
|
|
| 10558 |
|
|
AD1_CurrState_Sreg0_ns_0_i_o2[0] = AD1_CurrState_Sreg0_i[0] # !AD1_delay_counter_Sreg0[0] & !AD1_delay_counter_Sreg0[5] & AD1_un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0;
|
| 10559 |
|
|
|
| 10560 |
|
|
|
| 10561 |
|
|
--YB1_alu_func_2_0_0_a2_3[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_3[1]
|
| 10562 |
|
|
--operation mode is normal
|
| 10563 |
|
|
|
| 10564 |
|
|
YB1_alu_func_2_0_0_a2_3[1] = YB1_fsm_dly_2_0_0_a2_x[2] & YB1_cmp_ctl_2_0_0_a2_1[0] # YB1_cmp_ctl_2_0_0_a2_0[0] & !KE1_q_a[3];
|
| 10565 |
|
|
|
| 10566 |
|
|
|
| 10567 |
|
|
--YB1_alu_func_2_0_0_3_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_3_Z[1]
|
| 10568 |
|
|
--operation mode is normal
|
| 10569 |
|
|
|
| 10570 |
|
|
YB1_alu_func_2_0_0_3_Z[1] = YB1_alu_func_2_0_0_a2_x[0] & YB1_alu_func_2_0_0_a2_2_x[1] # YB1_alu_func_2_0_0_a2_1[4] # !YB1_alu_func_2_0_0_3_a[1];
|
| 10571 |
|
|
|
| 10572 |
|
|
|
| 10573 |
|
|
--YB1_alu_func_2_0_0_a3_1[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_1[1]
|
| 10574 |
|
|
--operation mode is normal
|
| 10575 |
|
|
|
| 10576 |
|
|
YB1_alu_func_2_0_0_a3_1[1] = YB1_fsm_dly_2_0_0_a2_x[2] & YB1_alu_func_2_0_0_a2_0_x[0] # YB1_alu_func_2_0_0_a2_0[1] & YB1_alu_func_2_0_0_a2_0_x[4];
|
| 10577 |
|
|
|
| 10578 |
|
|
|
| 10579 |
|
|
--YB1_un1_muxa_ctl370_6 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_6
|
| 10580 |
|
|
--operation mode is normal
|
| 10581 |
|
|
|
| 10582 |
|
|
YB1_un1_muxa_ctl370_6 = !KE1_q_a[6] & YB1_un1_muxa_ctl370_6_a_x & KE1_q_a[3] $ KE1_q_a[4];
|
| 10583 |
|
|
|
| 10584 |
|
|
|
| 10585 |
|
|
--YB1_un1_muxa_ctl370_5 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_5
|
| 10586 |
|
|
--operation mode is normal
|
| 10587 |
|
|
|
| 10588 |
|
|
YB1_un1_muxa_ctl370_5 = KE1_q_a[6] & YB1_alu_func_2_0_0_a2_0[1] & !KE1_q_a[2] # !KE1_q_a[6] & YB1_un1_muxa_ctl370_5_a;
|
| 10589 |
|
|
|
| 10590 |
|
|
|
| 10591 |
|
|
--YB1_un1_ins_i_22_1_a is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_22_1_a
|
| 10592 |
|
|
--operation mode is normal
|
| 10593 |
|
|
|
| 10594 |
|
|
YB1_un1_ins_i_22_1_a = KE1_q_a[4] & !KE1_q_a[2] & KE1_q_a[3] # !KE1_q_a[4] & KE1_q_a[5];
|
| 10595 |
|
|
|
| 10596 |
|
|
|
| 10597 |
|
|
--YB1_fsm_dly_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_0
|
| 10598 |
|
|
--operation mode is normal
|
| 10599 |
|
|
|
| 10600 |
|
|
YB1_fsm_dly_2_0_0_0 = YB1_ext_ctl_2_0_0_o3[2] # WB35L1 & YB1_ext_ctl_2_0_0_a3_1_0[2] # !YB1_fsm_dly_2_0_0_a[0];
|
| 10601 |
|
|
|
| 10602 |
|
|
|
| 10603 |
|
|
--WB35L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_|lpm_latch:U1|q[0]~56
|
| 10604 |
|
|
--operation mode is normal
|
| 10605 |
|
|
|
| 10606 |
|
|
WB35L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_fsm_dly_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB35L1;
|
| 10607 |
|
|
|
| 10608 |
|
|
|
| 10609 |
|
|
--YB1_fsm_dly_2_i_m3_0[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_i_m3_0[1]
|
| 10610 |
|
|
--operation mode is normal
|
| 10611 |
|
|
|
| 10612 |
|
|
YB1_fsm_dly_2_i_m3_0[1] = YB1_fsm_dly_2_0_0_a2_x[2] & GE1_q_a[3] & YB1_alu_func_2_0_0_a2_2_x[1] # !YB1_fsm_dly_2_i_m3_0_a[1];
|
| 10613 |
|
|
|
| 10614 |
|
|
|
| 10615 |
|
|
--WB45L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z|lpm_latch:U1|q[0]~56
|
| 10616 |
|
|
--operation mode is normal
|
| 10617 |
|
|
|
| 10618 |
|
|
WB45L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_fsm_dly_2_i_m3_0[1] # !YB1_un1_muxa_ctl370_x & WB45L1;
|
| 10619 |
|
|
|
| 10620 |
|
|
|
| 10621 |
|
|
--YB1_fsm_dly_2_0_0[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0[2]
|
| 10622 |
|
|
--operation mode is normal
|
| 10623 |
|
|
|
| 10624 |
|
|
YB1_fsm_dly_2_0_0[2] = YB1_fsm_dly_2_0_0_a2_x[2] & JE1_q_a[7] & YB1_fsm_dly_2_0_0_a2_0[2] # !YB1_fsm_dly_2_0_0_a[2];
|
| 10625 |
|
|
|
| 10626 |
|
|
|
| 10627 |
|
|
--WB55L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z|lpm_latch:U1|q[0]~56
|
| 10628 |
|
|
--operation mode is normal
|
| 10629 |
|
|
|
| 10630 |
|
|
WB55L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_fsm_dly_2_0_0[2] # !YB1_un1_muxa_ctl370_x & WB55L1;
|
| 10631 |
|
|
|
| 10632 |
|
|
|
| 10633 |
|
|
--AD1_CurrState_Sreg0[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0[8]
|
| 10634 |
|
|
--operation mode is normal
|
| 10635 |
|
|
|
| 10636 |
|
|
AD1_CurrState_Sreg0[8]_lut_out = AD1_CurrState_Sreg0_2 # WB55L1 & AD1_CurrState_Sreg0_ns_0_0_0_a_x[8] & AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
|
| 10637 |
|
|
AD1_CurrState_Sreg0[8] = DFFEAS(AD1_CurrState_Sreg0[8]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 10638 |
|
|
|
| 10639 |
|
|
|
| 10640 |
|
|
--AD1_CurrState_Sreg0[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0[1]
|
| 10641 |
|
|
--operation mode is normal
|
| 10642 |
|
|
|
| 10643 |
|
|
AD1_CurrState_Sreg0[1]_lut_out = AD1_CurrState_Sreg0_ns_0_0_a2_2[1] & !AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & AD1_CurrState_Sreg0_ns_0_i_o2[0] # !AD1_CurrState_Sreg0_ns_0_0_a[1];
|
| 10644 |
|
|
AD1_CurrState_Sreg0[1] = DFFEAS(AD1_CurrState_Sreg0[1]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 10645 |
|
|
|
| 10646 |
|
|
|
| 10647 |
|
|
--YB1_alu_func_2_i_m3_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_0
|
| 10648 |
|
|
--operation mode is normal
|
| 10649 |
|
|
|
| 10650 |
|
|
YB1_alu_func_2_i_m3_0_0 = YB1_alu_func_2_i_m3_0_5[2] # !GE1_q_a[3] & !KE1_q_a[4] & YB1_alu_func_2_i_m3_0_a[2];
|
| 10651 |
|
|
|
| 10652 |
|
|
|
| 10653 |
|
|
--WB93L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1|q[0]~68
|
| 10654 |
|
|
--operation mode is normal
|
| 10655 |
|
|
|
| 10656 |
|
|
WB93L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_alu_func_2_i_m3_0_0 # !YB1_un1_muxa_ctl370_x & WB93L2;
|
| 10657 |
|
|
|
| 10658 |
|
|
|
| 10659 |
|
|
--WB93L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1|q[0]~69
|
| 10660 |
|
|
--operation mode is normal
|
| 10661 |
|
|
|
| 10662 |
|
|
WB93L2 = WB93L1 & !YB1_un1_ins_i_23_2_0;
|
| 10663 |
|
|
|
| 10664 |
|
|
|
| 10665 |
|
|
--YB1_alu_func_2_0_0_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_3
|
| 10666 |
|
|
--operation mode is normal
|
| 10667 |
|
|
|
| 10668 |
|
|
YB1_alu_func_2_0_0_3 = YB1_alu_func_2_0_0_a3_0[3] # YB1_alu_func_2_0_0_a3_1[3] # YB1_alu_func_2_0_0_o3[3] # YB1_alu_func_2_0_0_a[3];
|
| 10669 |
|
|
|
| 10670 |
|
|
|
| 10671 |
|
|
--WB04L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1|q[0]~68
|
| 10672 |
|
|
--operation mode is normal
|
| 10673 |
|
|
|
| 10674 |
|
|
WB04L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_alu_func_2_0_0_3 # !YB1_un1_muxa_ctl370_x & WB04L2;
|
| 10675 |
|
|
|
| 10676 |
|
|
|
| 10677 |
|
|
--WB04L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1|q[0]~69
|
| 10678 |
|
|
--operation mode is normal
|
| 10679 |
|
|
|
| 10680 |
|
|
WB04L2 = WB04L1 & !YB1_un1_ins_i_23_2_0;
|
| 10681 |
|
|
|
| 10682 |
|
|
|
| 10683 |
|
|
--YB1_alu_func_2_0_0_a[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a[4]
|
| 10684 |
|
|
--operation mode is normal
|
| 10685 |
|
|
|
| 10686 |
|
|
YB1_alu_func_2_0_0_a[4] = !YB1_alu_func_2_0_0_a3_1_x[4] & !KE1_q_a[3] & !KE1_q_a[4] # !KE1_q_a[5];
|
| 10687 |
|
|
|
| 10688 |
|
|
|
| 10689 |
|
|
--YB1_alu_func_2_0_0_2[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_2[4]
|
| 10690 |
|
|
--operation mode is normal
|
| 10691 |
|
|
|
| 10692 |
|
|
YB1_alu_func_2_0_0_2[4] = YB1_alu_func_2_0_0_1_Z[4] # !KE1_q_a[4] & !KE1_q_a[7] & YB1_alu_func_2_0_0_a2_0_x[0];
|
| 10693 |
|
|
|
| 10694 |
|
|
|
| 10695 |
|
|
--YB1_alu_func_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a[0]
|
| 10696 |
|
|
--operation mode is normal
|
| 10697 |
|
|
|
| 10698 |
|
|
YB1_alu_func_2_0_0_a[0] = !YB1_cmp_ctl_2_0_0_a2_0[0] & !YB1_cmp_ctl_2_0_0_a2_1[0] # !WB73L1 # !YB1_alu_func_2_0_0_a2_0[1];
|
| 10699 |
|
|
|
| 10700 |
|
|
|
| 10701 |
|
|
--YB1_alu_func_2_0_0_a3[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3[0]
|
| 10702 |
|
|
--operation mode is normal
|
| 10703 |
|
|
|
| 10704 |
|
|
YB1_alu_func_2_0_0_a3[0] = YB1_alu_func_2_0_0_a2_0[1] & !GE1_q_a[3] & GE1_q_a[0] & YB1_alu_func_2_0_0_o2_0[0];
|
| 10705 |
|
|
|
| 10706 |
|
|
|
| 10707 |
|
|
--YB1_alu_func_2_0_0_2_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_2_x[0]
|
| 10708 |
|
|
--operation mode is normal
|
| 10709 |
|
|
|
| 10710 |
|
|
YB1_alu_func_2_0_0_2_x[0] = YB1_alu_func_2_0_0_0_Z[0] # KE1_q_a[5] & !YB1_alu_func_2_0_0_2_a_x[0];
|
| 10711 |
|
|
|
| 10712 |
|
|
|
| 10713 |
|
|
--YB1_alu_func_2_0_0_a3_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_0[0]
|
| 10714 |
|
|
--operation mode is normal
|
| 10715 |
|
|
|
| 10716 |
|
|
YB1_alu_func_2_0_0_a3_0[0] = !GE1_q_a[0] & YB1_alu_func_2_0_0_a2_3_x[0] & YB1_alu_func_2_0_0_a2_2_x[1] # YB1_alu_func_2_0_0_a2_1[4];
|
| 10717 |
|
|
|
| 10718 |
|
|
|
| 10719 |
|
|
--VD1_un134_hilo_combout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[4]
|
| 10720 |
|
|
--operation mode is arithmetic
|
| 10721 |
|
|
|
| 10722 |
|
|
VD1_un134_hilo_combout[4]_carry_eqn = VD1_un134_hilo_cout[2];
|
| 10723 |
|
|
VD1_un134_hilo_combout[4] = VD1_hilo_4 $ (!VD1_un134_hilo_combout[4]_carry_eqn);
|
| 10724 |
|
|
|
| 10725 |
|
|
--VD1_un134_hilo_cout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[4]
|
| 10726 |
|
|
--operation mode is arithmetic
|
| 10727 |
|
|
|
| 10728 |
|
|
VD1_un134_hilo_cout[4] = CARRY(VD1_hilo_4 & VD1_hilo_5 & !VD1_un134_hilo_cout[2]);
|
| 10729 |
|
|
|
| 10730 |
|
|
|
| 10731 |
|
|
--VD1_hilo_37_iv_0_a2_7[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_7[36]
|
| 10732 |
|
|
--operation mode is normal
|
| 10733 |
|
|
|
| 10734 |
|
|
VD1_hilo_37_iv_0_a2_7[36] = !VD1_sub_or_yn & VD1_hilo_37_iv_0_a2_7_2_1[37] & VD1_hilo_1_sqmuxa_1 & !VD1_un50_hilo_add5;
|
| 10735 |
|
|
|
| 10736 |
|
|
|
| 10737 |
|
|
--VD1_hilo_37_iv_0_5[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[36]
|
| 10738 |
|
|
--operation mode is normal
|
| 10739 |
|
|
|
| 10740 |
|
|
VD1_hilo_37_iv_0_5[36] = VD1_hilo_37_iv_0_1[36] # VD1_hilo_37_iv_0_5_a[36] # !VD1_un59_hilo_add5 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 10741 |
|
|
|
| 10742 |
|
|
|
| 10743 |
|
|
--AC1_muxb_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr_cls:U1|muxb_ctl_o_0
|
| 10744 |
|
|
--operation mode is normal
|
| 10745 |
|
|
|
| 10746 |
|
|
AC1_muxb_ctl_o_0_lut_out = WB85L1;
|
| 10747 |
|
|
AC1_muxb_ctl_o_0 = DFFEAS(AC1_muxb_ctl_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10748 |
|
|
|
| 10749 |
|
|
|
| 10750 |
|
|
--AC1_muxb_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr_cls:U1|muxb_ctl_o_1
|
| 10751 |
|
|
--operation mode is normal
|
| 10752 |
|
|
|
| 10753 |
|
|
AC1_muxb_ctl_o_1_lut_out = WB95L2;
|
| 10754 |
|
|
AC1_muxb_ctl_o_1 = DFFEAS(AC1_muxb_ctl_o_1_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10755 |
|
|
|
| 10756 |
|
|
|
| 10757 |
|
|
--XD1_un32_mux_fw is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un32_mux_fw
|
| 10758 |
|
|
--operation mode is normal
|
| 10759 |
|
|
|
| 10760 |
|
|
XD1_un32_mux_fw = !XD1_mux_fw_1 & WD1_un30_mux_fw # XD1_un17_mux_fw_NE # !MC1_wb_we_o_0;
|
| 10761 |
|
|
|
| 10762 |
|
|
|
| 10763 |
|
|
--YB1_muxa_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_0
|
| 10764 |
|
|
--operation mode is normal
|
| 10765 |
|
|
|
| 10766 |
|
|
YB1_muxa_ctl_2_0_0_0 = YB1_alu_func_2_0_0_a2_0[1] & !YB1_alu_func_2_0_0_o2_x[3] & YB1_ext_ctl_2_0_0_a2_2_x[2] # !YB1_muxa_ctl_2_0_0_a[0];
|
| 10767 |
|
|
|
| 10768 |
|
|
|
| 10769 |
|
|
--WB65L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxa_ctl_1_0_|lpm_latch:U1|q[0]~56
|
| 10770 |
|
|
--operation mode is normal
|
| 10771 |
|
|
|
| 10772 |
|
|
WB65L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_muxa_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB65L1;
|
| 10773 |
|
|
|
| 10774 |
|
|
|
| 10775 |
|
|
--ED1_r32_o_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_4
|
| 10776 |
|
|
--operation mode is normal
|
| 10777 |
|
|
|
| 10778 |
|
|
ED1_r32_o_4_lut_out = GE1_q_a[4];
|
| 10779 |
|
|
ED1_r32_o_4 = DFFEAS(ED1_r32_o_4_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10780 |
|
|
|
| 10781 |
|
|
|
| 10782 |
|
|
--ED1_r32_o_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_10
|
| 10783 |
|
|
--operation mode is normal
|
| 10784 |
|
|
|
| 10785 |
|
|
ED1_r32_o_10_lut_out = HE1_q_a[2];
|
| 10786 |
|
|
ED1_r32_o_10 = DFFEAS(ED1_r32_o_10_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10787 |
|
|
|
| 10788 |
|
|
|
| 10789 |
|
|
--DC1_ext_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4|ext_ctl_o_1
|
| 10790 |
|
|
--operation mode is normal
|
| 10791 |
|
|
|
| 10792 |
|
|
DC1_ext_ctl_o_1_lut_out = WB15L1;
|
| 10793 |
|
|
DC1_ext_ctl_o_1 = DFFEAS(DC1_ext_ctl_o_1_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10794 |
|
|
|
| 10795 |
|
|
|
| 10796 |
|
|
--DC1_ext_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4|ext_ctl_o_2
|
| 10797 |
|
|
--operation mode is normal
|
| 10798 |
|
|
|
| 10799 |
|
|
DC1_ext_ctl_o_2_lut_out = WB25L1;
|
| 10800 |
|
|
DC1_ext_ctl_o_2 = DFFEAS(DC1_ext_ctl_o_2_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10801 |
|
|
|
| 10802 |
|
|
|
| 10803 |
|
|
--DC1_ext_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4|ext_ctl_o_0
|
| 10804 |
|
|
--operation mode is normal
|
| 10805 |
|
|
|
| 10806 |
|
|
DC1_ext_ctl_o_0_lut_out = WB05L2;
|
| 10807 |
|
|
DC1_ext_ctl_o_0 = DFFEAS(DC1_ext_ctl_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 10808 |
|
|
|
| 10809 |
|
|
|
| 10810 |
|
|
--CD1_res_7_0_0_a2[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a2[18]
|
| 10811 |
|
|
--operation mode is normal
|
| 10812 |
|
|
|
| 10813 |
|
|
CD1_res_7_0_0_a2[18] = DC1_ext_ctl_o_1 & !DC1_ext_ctl_o_2 & DC1_ext_ctl_o_0;
|
| 10814 |
|
|
|
| 10815 |
|
|
|
| 10816 |
|
|
--WD1_un1_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un1_mux_fw_NE
|
| 10817 |
|
|
--operation mode is normal
|
| 10818 |
|
|
|
| 10819 |
|
|
WD1_un1_mux_fw_NE = WD1_un1_mux_fw_NE_1 # WD1_un1_mux_fw_NE_a # AE1_q_4 $ MB1_r5_o_4;
|
| 10820 |
|
|
|
| 10821 |
|
|
|
| 10822 |
|
|
--PB1_dout_iv_4 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_4
|
| 10823 |
|
|
--operation mode is normal
|
| 10824 |
|
|
|
| 10825 |
|
|
PB1_dout_iv_4 = HD1_dout_iv_1_4 # FD1_wb_o_4 & HD1_dout7_0_a2;
|
| 10826 |
|
|
|
| 10827 |
|
|
--PB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_4
|
| 10828 |
|
|
--operation mode is normal
|
| 10829 |
|
|
|
| 10830 |
|
|
PB1_r32_o_4 = DFFEAS(PB1_dout_iv_4, E1__clk0, VCC, , , , , , );
|
| 10831 |
|
|
|
| 10832 |
|
|
|
| 10833 |
|
|
--PD1_un6_a_o_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|un6_a_o_a
|
| 10834 |
|
|
--operation mode is normal
|
| 10835 |
|
|
|
| 10836 |
|
|
PD1_un6_a_o_a = MC1_wb_we_o_0 & !WD1_un30_mux_fw & !WD1_un17_mux_fw_NE;
|
| 10837 |
|
|
|
| 10838 |
|
|
|
| 10839 |
|
|
--CD1_res_7_0_0_a_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_0
|
| 10840 |
|
|
--operation mode is normal
|
| 10841 |
|
|
|
| 10842 |
|
|
CD1_res_7_0_0_a_0 = ED1_r32_o_3 & !CD1_res_7_0_0_a2_0 & !CD1_res_7_0_0_0_a_0 # !ED1_r32_o_9 # !ED1_r32_o_3 & !CD1_res_7_0_0_0_a_0 # !ED1_r32_o_9;
|
| 10843 |
|
|
|
| 10844 |
|
|
|
| 10845 |
|
|
--PD1_a_o_3_d_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[3]
|
| 10846 |
|
|
--operation mode is normal
|
| 10847 |
|
|
|
| 10848 |
|
|
PD1_a_o_3_d_a[3] = PD1_a_o_sn_m2 & !PB1_r32_o_3 # !PD1_a_o_sn_m2 & !AB1_r32_o_1;
|
| 10849 |
|
|
|
| 10850 |
|
|
|
| 10851 |
|
|
--VD1_b_o_iv_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_10
|
| 10852 |
|
|
--operation mode is normal
|
| 10853 |
|
|
|
| 10854 |
|
|
VD1_b_o_iv_10 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[10] & !G1_BUS15471_i_m[10] & AB1_r32_o_8 # !QD1_b_o_0_sqmuxa;
|
| 10855 |
|
|
|
| 10856 |
|
|
--VD1_op2_reged[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[10]
|
| 10857 |
|
|
--operation mode is normal
|
| 10858 |
|
|
|
| 10859 |
|
|
VD1_op2_reged[10] = DFFEAS(VD1_b_o_iv_10, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10860 |
|
|
|
| 10861 |
|
|
|
| 10862 |
|
|
--UD1_shift_out_80_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[4]
|
| 10863 |
|
|
--operation mode is normal
|
| 10864 |
|
|
|
| 10865 |
|
|
UD1_shift_out_80_a[4] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_7 # !PD1_a_o_1 & !VD1_b_o_iv_5;
|
| 10866 |
|
|
|
| 10867 |
|
|
|
| 10868 |
|
|
--VD1_b_o_iv_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_15
|
| 10869 |
|
|
--operation mode is normal
|
| 10870 |
|
|
|
| 10871 |
|
|
VD1_b_o_iv_15 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[15] & !G1_BUS15471_i_m[15] & AB1_r32_o_13 # !QD1_b_o_0_sqmuxa;
|
| 10872 |
|
|
|
| 10873 |
|
|
--VD1_op2_reged[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[15]
|
| 10874 |
|
|
--operation mode is normal
|
| 10875 |
|
|
|
| 10876 |
|
|
VD1_op2_reged[15] = DFFEAS(VD1_b_o_iv_15, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10877 |
|
|
|
| 10878 |
|
|
|
| 10879 |
|
|
--UD1_shift_out_79_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[4]
|
| 10880 |
|
|
--operation mode is normal
|
| 10881 |
|
|
|
| 10882 |
|
|
UD1_shift_out_79_a[4] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_13 # !PD1_a_o_0 & !VD1_b_o_iv_12;
|
| 10883 |
|
|
|
| 10884 |
|
|
|
| 10885 |
|
|
--VD1_b_o_iv_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_27
|
| 10886 |
|
|
--operation mode is normal
|
| 10887 |
|
|
|
| 10888 |
|
|
VD1_b_o_iv_27 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[27] & !G1_BUS15471_i_m[27] & AB1_r32_o_25 # !QD1_b_o_0_sqmuxa;
|
| 10889 |
|
|
|
| 10890 |
|
|
--VD1_op2_reged[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[27]
|
| 10891 |
|
|
--operation mode is normal
|
| 10892 |
|
|
|
| 10893 |
|
|
VD1_op2_reged[27] = DFFEAS(VD1_b_o_iv_27, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10894 |
|
|
|
| 10895 |
|
|
|
| 10896 |
|
|
--UD1_shift_out_79_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[16]
|
| 10897 |
|
|
--operation mode is normal
|
| 10898 |
|
|
|
| 10899 |
|
|
UD1_shift_out_79_a[16] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_25 # !PD1_a_o_0 & !VD1_b_o_iv_24;
|
| 10900 |
|
|
|
| 10901 |
|
|
|
| 10902 |
|
|
--UD1_shift_out_79_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[20]
|
| 10903 |
|
|
--operation mode is normal
|
| 10904 |
|
|
|
| 10905 |
|
|
UD1_shift_out_79_a[20] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_29 # !PD1_a_o_0 & !VD1_b_o_iv_28;
|
| 10906 |
|
|
|
| 10907 |
|
|
|
| 10908 |
|
|
--VD1_b_o_iv_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_19
|
| 10909 |
|
|
--operation mode is normal
|
| 10910 |
|
|
|
| 10911 |
|
|
VD1_b_o_iv_19 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[19] & !G1_BUS15471_i_m[19] & AB1_r32_o_17 # !QD1_b_o_0_sqmuxa;
|
| 10912 |
|
|
|
| 10913 |
|
|
--VD1_op2_reged[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[19]
|
| 10914 |
|
|
--operation mode is normal
|
| 10915 |
|
|
|
| 10916 |
|
|
VD1_op2_reged[19] = DFFEAS(VD1_b_o_iv_19, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10917 |
|
|
|
| 10918 |
|
|
|
| 10919 |
|
|
--UD1_shift_out_79_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[8]
|
| 10920 |
|
|
--operation mode is normal
|
| 10921 |
|
|
|
| 10922 |
|
|
UD1_shift_out_79_a[8] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_17 # !PD1_a_o_0 & !VD1_b_o_iv_16;
|
| 10923 |
|
|
|
| 10924 |
|
|
|
| 10925 |
|
|
--VD1_b_o_iv_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_20
|
| 10926 |
|
|
--operation mode is normal
|
| 10927 |
|
|
|
| 10928 |
|
|
VD1_b_o_iv_20 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[20] & !G1_BUS15471_i_m[20] & AB1_r32_o_18 # !QD1_b_o_0_sqmuxa;
|
| 10929 |
|
|
|
| 10930 |
|
|
--VD1_op2_reged[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[20]
|
| 10931 |
|
|
--operation mode is normal
|
| 10932 |
|
|
|
| 10933 |
|
|
VD1_op2_reged[20] = DFFEAS(VD1_b_o_iv_20, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 10934 |
|
|
|
| 10935 |
|
|
|
| 10936 |
|
|
--UD1_shift_out_47_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_47_a[0]
|
| 10937 |
|
|
--operation mode is normal
|
| 10938 |
|
|
|
| 10939 |
|
|
UD1_shift_out_47_a[0] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_23 # !PD1_a_o_0 & !VD1_b_o_iv_22 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 10940 |
|
|
|
| 10941 |
|
|
|
| 10942 |
|
|
--VD1_hilo_37_iv_0_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[6]
|
| 10943 |
|
|
--operation mode is normal
|
| 10944 |
|
|
|
| 10945 |
|
|
VD1_hilo_37_iv_0_a[6] = VD1_hilo_5 & !VD1_hilo_2_sqmuxa & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_7 # !VD1_hilo_5 & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_7;
|
| 10946 |
|
|
|
| 10947 |
|
|
|
| 10948 |
|
|
--VD1_hilo_37_iv_0_0[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[6]
|
| 10949 |
|
|
--operation mode is normal
|
| 10950 |
|
|
|
| 10951 |
|
|
VD1_hilo_37_iv_0_0[6] = VD1_hilo_6 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[6] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_6 & VD1_un134_hilo_combout[6] & VD1_hilo_37_iv_0_a3_0[0];
|
| 10952 |
|
|
|
| 10953 |
|
|
|
| 10954 |
|
|
--VD1_count[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[5]
|
| 10955 |
|
|
--operation mode is normal
|
| 10956 |
|
|
|
| 10957 |
|
|
VD1_count[5]_carry_eqn = VD1_count_cout[4];
|
| 10958 |
|
|
VD1_count[5]_lut_out = VD1_count[5] $ (VD1_count[5]_carry_eqn);
|
| 10959 |
|
|
VD1_count[5] = DFFEAS(VD1_count[5]_lut_out, E1__clk0, VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
|
| 10960 |
|
|
|
| 10961 |
|
|
|
| 10962 |
|
|
--VD1_overflow is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|overflow
|
| 10963 |
|
|
--operation mode is normal
|
| 10964 |
|
|
|
| 10965 |
|
|
VD1_overflow_lut_out = VD1_overflow & !VD1_overflow_4_iv_a & VD1_over_i[32] # !VD1_rdy_0_sqmuxa # !VD1_overflow & !VD1_overflow_4_iv_a & VD1_over_i[32];
|
| 10966 |
|
|
VD1_overflow = DFFEAS(VD1_overflow_lut_out, E1__clk0, VCC, , sys_rst, , , , );
|
| 10967 |
|
|
|
| 10968 |
|
|
|
| 10969 |
|
|
--VD1_mul is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|mul
|
| 10970 |
|
|
--operation mode is normal
|
| 10971 |
|
|
|
| 10972 |
|
|
VD1_mul_lut_out = !RC1_alu_func_o_2 & RC1_alu_func_o_3 & !RC1_alu_func_o_1 & !RC1_alu_func_o_4;
|
| 10973 |
|
|
VD1_mul = DFFEAS(VD1_mul_lut_out, E1__clk0, VCC, , VD1_mul_0_sqmuxa_i, , , , );
|
| 10974 |
|
|
|
| 10975 |
|
|
|
| 10976 |
|
|
--VD1_addnop2110 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop2110
|
| 10977 |
|
|
--operation mode is normal
|
| 10978 |
|
|
|
| 10979 |
|
|
VD1_addnop2110 = !VD1_rdy & VD1_start & !VD1_hilo25;
|
| 10980 |
|
|
|
| 10981 |
|
|
|
| 10982 |
|
|
--VD1_rdy is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|rdy
|
| 10983 |
|
|
--operation mode is normal
|
| 10984 |
|
|
|
| 10985 |
|
|
VD1_rdy_lut_out = VD1_rdy_1_i_a2_a & VD1_rdy # !VD1_rdy_1_i_a2_a & !VD1_addnop2109_0_a2 # !sys_rst;
|
| 10986 |
|
|
VD1_rdy = DFFEAS(VD1_rdy_lut_out, E1__clk0, VCC, , , , , , );
|
| 10987 |
|
|
|
| 10988 |
|
|
|
| 10989 |
|
|
--VD1_un134_hilo_combout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[3]
|
| 10990 |
|
|
--operation mode is arithmetic
|
| 10991 |
|
|
|
| 10992 |
|
|
VD1_un134_hilo_combout[3]_carry_eqn = VD1_un134_hilo_cout[1];
|
| 10993 |
|
|
VD1_un134_hilo_combout[3] = VD1_hilo_3 $ (VD1_hilo_2 & VD1_un134_hilo_combout[3]_carry_eqn);
|
| 10994 |
|
|
|
| 10995 |
|
|
--VD1_un134_hilo_cout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[3]
|
| 10996 |
|
|
--operation mode is arithmetic
|
| 10997 |
|
|
|
| 10998 |
|
|
VD1_un134_hilo_cout[3] = CARRY(!VD1_un134_hilo_cout[1] # !VD1_hilo_3 # !VD1_hilo_2);
|
| 10999 |
|
|
|
| 11000 |
|
|
|
| 11001 |
|
|
--VD1_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|add1
|
| 11002 |
|
|
--operation mode is normal
|
| 11003 |
|
|
|
| 11004 |
|
|
VD1_add1_lut_out = VD1_add1_3_sqmuxa_0_x & VD1_op2_sign_reged & !VD1_add1_14_a # !VD1_op2_sign_reged & VD1_add1_14_a & VD1_eqnop2_2_NE;
|
| 11005 |
|
|
VD1_add1 = DFFEAS(VD1_add1_lut_out, E1__clk0, VCC, , VD1_addop2_0_sqmuxa_1_i, , , , );
|
| 11006 |
|
|
|
| 11007 |
|
|
|
| 11008 |
|
|
--VD1_mul_0_sqmuxa_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|mul_0_sqmuxa_i
|
| 11009 |
|
|
--operation mode is normal
|
| 11010 |
|
|
|
| 11011 |
|
|
VD1_mul_0_sqmuxa_i = VD1_addnop2109_0_a2 # !sys_rst;
|
| 11012 |
|
|
|
| 11013 |
|
|
|
| 11014 |
|
|
--VD1_hilo_4_sqmuxa_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_4_sqmuxa_0
|
| 11015 |
|
|
--operation mode is normal
|
| 11016 |
|
|
|
| 11017 |
|
|
VD1_hilo_4_sqmuxa_0 = !VD1_finish & VD1_count[5];
|
| 11018 |
|
|
|
| 11019 |
|
|
|
| 11020 |
|
|
--C1_I_437_a_x is mips_sys:isys|I_437_a_x
|
| 11021 |
|
|
--operation mode is normal
|
| 11022 |
|
|
|
| 11023 |
|
|
C1_I_437_a_x = sys_rst & !VD1_rdy;
|
| 11024 |
|
|
|
| 11025 |
|
|
|
| 11026 |
|
|
--VD1_eqop2_2_32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_32
|
| 11027 |
|
|
--operation mode is normal
|
| 11028 |
|
|
|
| 11029 |
|
|
VD1_eqop2_2_32 = VD1_op2_sign_reged $ VD1_hilo[64];
|
| 11030 |
|
|
|
| 11031 |
|
|
|
| 11032 |
|
|
--VD1_sub_or_yn_0_sqmuxa_1_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sub_or_yn_0_sqmuxa_1_i
|
| 11033 |
|
|
--operation mode is normal
|
| 11034 |
|
|
|
| 11035 |
|
|
VD1_sub_or_yn_0_sqmuxa_1_i = VD1_sub_or_yn_0_sqmuxa_1_a & VD1_un17_mul_0 # !VD1_addnop2109_0_a2 # !sys_rst;
|
| 11036 |
|
|
|
| 11037 |
|
|
|
| 11038 |
|
|
--VD1_sign is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sign
|
| 11039 |
|
|
--operation mode is normal
|
| 11040 |
|
|
|
| 11041 |
|
|
VD1_sign_lut_out = !RC1_alu_func_o_2 & RC1_alu_func_o_3 & !RC1_alu_func_o_4 & RC1_alu_func_o_0;
|
| 11042 |
|
|
VD1_sign = DFFEAS(VD1_sign_lut_out, E1__clk0, VCC, , VD1_mul_0_sqmuxa_i, , , , );
|
| 11043 |
|
|
|
| 11044 |
|
|
|
| 11045 |
|
|
--VD1_nop2_reged[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[6]
|
| 11046 |
|
|
--operation mode is arithmetic
|
| 11047 |
|
|
|
| 11048 |
|
|
VD1_nop2_reged[6]_carry_eqn = VD1_nop2_reged_cout[4];
|
| 11049 |
|
|
VD1_nop2_reged[6] = VD1_op2_reged[6] $ !VD1_nop2_reged[6]_carry_eqn;
|
| 11050 |
|
|
|
| 11051 |
|
|
--VD1_nop2_reged_cout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[6]
|
| 11052 |
|
|
--operation mode is arithmetic
|
| 11053 |
|
|
|
| 11054 |
|
|
VD1_nop2_reged_cout[6] = CARRY(VD1_op2_reged[7] # VD1_op2_reged[6] # !VD1_nop2_reged_cout[4]);
|
| 11055 |
|
|
|
| 11056 |
|
|
|
| 11057 |
|
|
--VD1_un50_hilo_add5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add5
|
| 11058 |
|
|
--operation mode is arithmetic
|
| 11059 |
|
|
|
| 11060 |
|
|
VD1_un50_hilo_add5_carry_eqn = VD1_un50_hilo_carry_4;
|
| 11061 |
|
|
VD1_un50_hilo_add5 = VD1_hilo_37 $ VD1_nop2_reged[5] $ VD1_un50_hilo_add5_carry_eqn;
|
| 11062 |
|
|
|
| 11063 |
|
|
--VD1_un50_hilo_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_5
|
| 11064 |
|
|
--operation mode is arithmetic
|
| 11065 |
|
|
|
| 11066 |
|
|
VD1_un50_hilo_carry_5 = CARRY(VD1_hilo_37 & !VD1_nop2_reged[5] & !VD1_un50_hilo_carry_4 # !VD1_hilo_37 & !VD1_un50_hilo_carry_4 # !VD1_nop2_reged[5]);
|
| 11067 |
|
|
|
| 11068 |
|
|
|
| 11069 |
|
|
--VD1_un59_hilo_add5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add5
|
| 11070 |
|
|
--operation mode is arithmetic
|
| 11071 |
|
|
|
| 11072 |
|
|
VD1_un59_hilo_add5_carry_eqn = VD1_un59_hilo_carry_4;
|
| 11073 |
|
|
VD1_un59_hilo_add5 = VD1_hilo_37 $ VD1_op2_reged[5] $ VD1_un59_hilo_add5_carry_eqn;
|
| 11074 |
|
|
|
| 11075 |
|
|
--VD1_un59_hilo_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_5
|
| 11076 |
|
|
--operation mode is arithmetic
|
| 11077 |
|
|
|
| 11078 |
|
|
VD1_un59_hilo_carry_5 = CARRY(VD1_hilo_37 & !VD1_op2_reged[5] & !VD1_un59_hilo_carry_4 # !VD1_hilo_37 & !VD1_un59_hilo_carry_4 # !VD1_op2_reged[5]);
|
| 11079 |
|
|
|
| 11080 |
|
|
|
| 11081 |
|
|
--VD1_addop2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addop2
|
| 11082 |
|
|
--operation mode is normal
|
| 11083 |
|
|
|
| 11084 |
|
|
VD1_addop2_lut_out = !VD1_mul & VD1_addnop290[0] # VD1_un1_mul_2_a & !VD1_addnop292[0];
|
| 11085 |
|
|
VD1_addop2 = DFFEAS(VD1_addop2_lut_out, E1__clk0, VCC, , VD1_addop2_0_sqmuxa_1_i, , , , );
|
| 11086 |
|
|
|
| 11087 |
|
|
|
| 11088 |
|
|
--VD1_hilo_37_iv_0_a2_7[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_7[34]
|
| 11089 |
|
|
--operation mode is normal
|
| 11090 |
|
|
|
| 11091 |
|
|
VD1_hilo_37_iv_0_a2_7[34] = !VD1_addnop2 & VD1_hilo_3_sqmuxa;
|
| 11092 |
|
|
|
| 11093 |
|
|
|
| 11094 |
|
|
--VD1_hilo_37_iv_0_1_a[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[37]
|
| 11095 |
|
|
--operation mode is normal
|
| 11096 |
|
|
|
| 11097 |
|
|
VD1_hilo_37_iv_0_1_a[37] = VD1_hilo_5 & !VD1_hilo_37 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_hilo_5 & VD1_hilo_0_sqmuxa # !VD1_hilo_37 & VD1_hilo_37_iv_0_o3_2[34];
|
| 11098 |
|
|
|
| 11099 |
|
|
|
| 11100 |
|
|
--VD1_hilo_37_iv_0_a2_6_0[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_6_0[37]
|
| 11101 |
|
|
--operation mode is normal
|
| 11102 |
|
|
|
| 11103 |
|
|
VD1_hilo_37_iv_0_a2_6_0[37] = !VD1_addop2 & VD1_addnop2 & VD1_hilo_3_sqmuxa;
|
| 11104 |
|
|
|
| 11105 |
|
|
|
| 11106 |
|
|
--VD1_hilo_24_add5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add5
|
| 11107 |
|
|
--operation mode is arithmetic
|
| 11108 |
|
|
|
| 11109 |
|
|
VD1_hilo_24_add5_carry_eqn = VD1_hilo_24_carry_4;
|
| 11110 |
|
|
VD1_hilo_24_add5 = VD1_hilo_36 $ VD1_un1_op2_reged_1_combout[5] $ VD1_hilo_24_add5_carry_eqn;
|
| 11111 |
|
|
|
| 11112 |
|
|
--VD1_hilo_24_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_5
|
| 11113 |
|
|
--operation mode is arithmetic
|
| 11114 |
|
|
|
| 11115 |
|
|
VD1_hilo_24_carry_5 = CARRY(VD1_hilo_36 & !VD1_un1_op2_reged_1_combout[5] & !VD1_hilo_24_carry_4 # !VD1_hilo_36 & !VD1_hilo_24_carry_4 # !VD1_un1_op2_reged_1_combout[5]);
|
| 11116 |
|
|
|
| 11117 |
|
|
|
| 11118 |
|
|
--VD1_hilo_37_iv_0_5[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[38]
|
| 11119 |
|
|
--operation mode is normal
|
| 11120 |
|
|
|
| 11121 |
|
|
VD1_hilo_37_iv_0_5[38] = VD1_hilo_39 & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add7 # !VD1_hilo_39 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add7;
|
| 11122 |
|
|
|
| 11123 |
|
|
|
| 11124 |
|
|
--VD1_hilo_37_iv_0_4[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4[38]
|
| 11125 |
|
|
--operation mode is normal
|
| 11126 |
|
|
|
| 11127 |
|
|
VD1_hilo_37_iv_0_4[38] = VD1_hilo_37_iv_0_3[38] # !VD1_un59_hilo_add7 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 11128 |
|
|
|
| 11129 |
|
|
|
| 11130 |
|
|
--VD1_hilo_37_iv_0_a[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[38]
|
| 11131 |
|
|
--operation mode is normal
|
| 11132 |
|
|
|
| 11133 |
|
|
VD1_hilo_37_iv_0_a[38] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_6 # !VD1_hilo_24_add6 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_6;
|
| 11134 |
|
|
|
| 11135 |
|
|
|
| 11136 |
|
|
--VD1_un29_sign_0_o2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un29_sign_0_o2_0
|
| 11137 |
|
|
--operation mode is normal
|
| 11138 |
|
|
|
| 11139 |
|
|
VD1_un29_sign_0_o2_0 = RC1_alu_func_o_2 # RC1_alu_func_o_4;
|
| 11140 |
|
|
|
| 11141 |
|
|
|
| 11142 |
|
|
--PB1_dout_iv_5 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_5
|
| 11143 |
|
|
--operation mode is normal
|
| 11144 |
|
|
|
| 11145 |
|
|
PB1_dout_iv_5 = HD1_dout_iv_1_5 # FD1_wb_o_5 & HD1_dout7_0_a2;
|
| 11146 |
|
|
|
| 11147 |
|
|
--PB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_5
|
| 11148 |
|
|
--operation mode is normal
|
| 11149 |
|
|
|
| 11150 |
|
|
PB1_r32_o_5 = DFFEAS(PB1_dout_iv_5, E1__clk0, VCC, , , , , , );
|
| 11151 |
|
|
|
| 11152 |
|
|
|
| 11153 |
|
|
--UD1_shift_out_80_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[5]
|
| 11154 |
|
|
--operation mode is normal
|
| 11155 |
|
|
|
| 11156 |
|
|
UD1_shift_out_80_a[5] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_8 # !PD1_a_o_1 & !VD1_b_o_iv_6;
|
| 11157 |
|
|
|
| 11158 |
|
|
|
| 11159 |
|
|
--VD1_b_o_iv_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_16
|
| 11160 |
|
|
--operation mode is normal
|
| 11161 |
|
|
|
| 11162 |
|
|
VD1_b_o_iv_16 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[16] & !G1_BUS15471_i_m[16] & AB1_r32_o_14 # !QD1_b_o_0_sqmuxa;
|
| 11163 |
|
|
|
| 11164 |
|
|
--VD1_op2_reged[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[16]
|
| 11165 |
|
|
--operation mode is normal
|
| 11166 |
|
|
|
| 11167 |
|
|
VD1_op2_reged[16] = DFFEAS(VD1_b_o_iv_16, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 11168 |
|
|
|
| 11169 |
|
|
|
| 11170 |
|
|
--UD1_shift_out_79_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[5]
|
| 11171 |
|
|
--operation mode is normal
|
| 11172 |
|
|
|
| 11173 |
|
|
UD1_shift_out_79_a[5] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_14 # !PD1_a_o_0 & !VD1_b_o_iv_13;
|
| 11174 |
|
|
|
| 11175 |
|
|
|
| 11176 |
|
|
--VD1_b_o_iv_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_28
|
| 11177 |
|
|
--operation mode is normal
|
| 11178 |
|
|
|
| 11179 |
|
|
VD1_b_o_iv_28 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[28] & !QD1_b_o_iv_1_27 & FB1_r32_o_28 # !QD1_b_o18;
|
| 11180 |
|
|
|
| 11181 |
|
|
--VD1_op2_reged[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[28]
|
| 11182 |
|
|
--operation mode is normal
|
| 11183 |
|
|
|
| 11184 |
|
|
VD1_op2_reged[28] = DFFEAS(VD1_b_o_iv_28, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 11185 |
|
|
|
| 11186 |
|
|
|
| 11187 |
|
|
--UD1_shift_out_79_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[17]
|
| 11188 |
|
|
--operation mode is normal
|
| 11189 |
|
|
|
| 11190 |
|
|
UD1_shift_out_79_a[17] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_26 # !PD1_a_o_0 & !VD1_b_o_iv_25;
|
| 11191 |
|
|
|
| 11192 |
|
|
|
| 11193 |
|
|
--UD1_shift_out_39[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_39[17]
|
| 11194 |
|
|
--operation mode is normal
|
| 11195 |
|
|
|
| 11196 |
|
|
UD1_shift_out_39[17] = PD1_a_o_0 & VD1_b_o_iv_30 # !PD1_a_o_0 & VD1_b_o_iv_29;
|
| 11197 |
|
|
|
| 11198 |
|
|
|
| 11199 |
|
|
--UD1_shift_out_79_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[9]
|
| 11200 |
|
|
--operation mode is normal
|
| 11201 |
|
|
|
| 11202 |
|
|
UD1_shift_out_79_a[9] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_18 # !PD1_a_o_0 & !VD1_b_o_iv_17;
|
| 11203 |
|
|
|
| 11204 |
|
|
|
| 11205 |
|
|
--VD1_b_o_iv_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_23
|
| 11206 |
|
|
--operation mode is normal
|
| 11207 |
|
|
|
| 11208 |
|
|
VD1_b_o_iv_23 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[23] & !G1_BUS15471_i_m[23] & AB1_r32_o_21 # !QD1_b_o_0_sqmuxa;
|
| 11209 |
|
|
|
| 11210 |
|
|
--VD1_op2_reged[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[23]
|
| 11211 |
|
|
--operation mode is normal
|
| 11212 |
|
|
|
| 11213 |
|
|
VD1_op2_reged[23] = DFFEAS(VD1_b_o_iv_23, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 11214 |
|
|
|
| 11215 |
|
|
|
| 11216 |
|
|
--VD1_b_o_iv_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_24
|
| 11217 |
|
|
--operation mode is normal
|
| 11218 |
|
|
|
| 11219 |
|
|
VD1_b_o_iv_24 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[24] & !G1_BUS15471_i_m[24] & AB1_r32_o_22 # !QD1_b_o_0_sqmuxa;
|
| 11220 |
|
|
|
| 11221 |
|
|
--VD1_op2_reged[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[24]
|
| 11222 |
|
|
--operation mode is normal
|
| 11223 |
|
|
|
| 11224 |
|
|
VD1_op2_reged[24] = DFFEAS(VD1_b_o_iv_24, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 11225 |
|
|
|
| 11226 |
|
|
|
| 11227 |
|
|
--UD1_shift_out_79_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[13]
|
| 11228 |
|
|
--operation mode is normal
|
| 11229 |
|
|
|
| 11230 |
|
|
UD1_shift_out_79_a[13] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_22 # !PD1_a_o_0 & !VD1_b_o_iv_21;
|
| 11231 |
|
|
|
| 11232 |
|
|
|
| 11233 |
|
|
--YB1_un1_ins_i_18_0_0_a2_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_18_0_0_a2_x
|
| 11234 |
|
|
--operation mode is normal
|
| 11235 |
|
|
|
| 11236 |
|
|
YB1_un1_ins_i_18_0_0_a2_x = KE1_q_a[7] & !KE1_q_a[6] & KE1_q_a[5];
|
| 11237 |
|
|
|
| 11238 |
|
|
|
| 11239 |
|
|
--YB1_dmem_ctl_2_0_0_a3[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_a3[2]
|
| 11240 |
|
|
--operation mode is normal
|
| 11241 |
|
|
|
| 11242 |
|
|
YB1_dmem_ctl_2_0_0_a3[2] = YB1_alu_func_2_0_0_a2_0[1] & WB84L2 & YB1_cmp_ctl_2_0_0_a2_0[0] # YB1_cmp_ctl_2_0_0_a2_1[0];
|
| 11243 |
|
|
|
| 11244 |
|
|
|
| 11245 |
|
|
--YB1_dmem_ctl_2_0_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_a[2]
|
| 11246 |
|
|
--operation mode is normal
|
| 11247 |
|
|
|
| 11248 |
|
|
YB1_dmem_ctl_2_0_0_a[2] = KE1_q_a[7] & KE1_q_a[2] & KE1_q_a[3] & !KE1_q_a[4] # !KE1_q_a[2] & !KE1_q_a[3] & KE1_q_a[4];
|
| 11249 |
|
|
|
| 11250 |
|
|
|
| 11251 |
|
|
--YB1_un1_ins_i_18_m_0_0_a3_a_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_18_m_0_0_a3_a_x
|
| 11252 |
|
|
--operation mode is normal
|
| 11253 |
|
|
|
| 11254 |
|
|
YB1_un1_ins_i_18_m_0_0_a3_a_x = KE1_q_a[4] & !KE1_q_a[3] # !KE1_q_a[4] & !KE1_q_a[5];
|
| 11255 |
|
|
|
| 11256 |
|
|
|
| 11257 |
|
|
--UD1_shift_out_79_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[6]
|
| 11258 |
|
|
--operation mode is normal
|
| 11259 |
|
|
|
| 11260 |
|
|
UD1_shift_out_79_a[6] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_15 # !PD1_a_o_0 & !VD1_b_o_iv_14;
|
| 11261 |
|
|
|
| 11262 |
|
|
|
| 11263 |
|
|
--UD1_shift_out_79_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[10]
|
| 11264 |
|
|
--operation mode is normal
|
| 11265 |
|
|
|
| 11266 |
|
|
UD1_shift_out_79_a[10] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_19 # !PD1_a_o_0 & !VD1_b_o_iv_18;
|
| 11267 |
|
|
|
| 11268 |
|
|
|
| 11269 |
|
|
--UD1_shift_out_79_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[18]
|
| 11270 |
|
|
--operation mode is normal
|
| 11271 |
|
|
|
| 11272 |
|
|
UD1_shift_out_79_a[18] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_27 # !PD1_a_o_0 & !VD1_b_o_iv_26;
|
| 11273 |
|
|
|
| 11274 |
|
|
|
| 11275 |
|
|
--UD1_shift_out_79_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[2]
|
| 11276 |
|
|
--operation mode is normal
|
| 11277 |
|
|
|
| 11278 |
|
|
UD1_shift_out_79_a[2] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_11 # !PD1_a_o_0 & !VD1_b_o_iv_10;
|
| 11279 |
|
|
|
| 11280 |
|
|
|
| 11281 |
|
|
--UD1_shift_out_39[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_39[18]
|
| 11282 |
|
|
--operation mode is normal
|
| 11283 |
|
|
|
| 11284 |
|
|
UD1_shift_out_39[18] = PD1_a_o_0 & VD1_b_o_iv_31 # !PD1_a_o_0 & VD1_b_o_iv_30;
|
| 11285 |
|
|
|
| 11286 |
|
|
|
| 11287 |
|
|
--VD1_un134_hilo_combout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[2]
|
| 11288 |
|
|
--operation mode is arithmetic
|
| 11289 |
|
|
|
| 11290 |
|
|
VD1_un134_hilo_combout[2]_carry_eqn = VD1_un134_hilo_cout[0];
|
| 11291 |
|
|
VD1_un134_hilo_combout[2] = VD1_hilo_2 $ (VD1_un134_hilo_combout[2]_carry_eqn);
|
| 11292 |
|
|
|
| 11293 |
|
|
--VD1_un134_hilo_cout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[2]
|
| 11294 |
|
|
--operation mode is arithmetic
|
| 11295 |
|
|
|
| 11296 |
|
|
VD1_un134_hilo_cout[2] = CARRY(!VD1_un134_hilo_cout[0] # !VD1_hilo_3 # !VD1_hilo_2);
|
| 11297 |
|
|
|
| 11298 |
|
|
|
| 11299 |
|
|
--VD1_un50_hilo_add3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add3
|
| 11300 |
|
|
--operation mode is arithmetic
|
| 11301 |
|
|
|
| 11302 |
|
|
VD1_un50_hilo_add3_carry_eqn = VD1_un50_hilo_carry_2;
|
| 11303 |
|
|
VD1_un50_hilo_add3 = VD1_hilo_35 $ VD1_nop2_reged[3] $ VD1_un50_hilo_add3_carry_eqn;
|
| 11304 |
|
|
|
| 11305 |
|
|
--VD1_un50_hilo_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_3
|
| 11306 |
|
|
--operation mode is arithmetic
|
| 11307 |
|
|
|
| 11308 |
|
|
VD1_un50_hilo_carry_3 = CARRY(VD1_hilo_35 & !VD1_nop2_reged[3] & !VD1_un50_hilo_carry_2 # !VD1_hilo_35 & !VD1_un50_hilo_carry_2 # !VD1_nop2_reged[3]);
|
| 11309 |
|
|
|
| 11310 |
|
|
|
| 11311 |
|
|
--VD1_hilo_24_add2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add2
|
| 11312 |
|
|
--operation mode is arithmetic
|
| 11313 |
|
|
|
| 11314 |
|
|
VD1_hilo_24_add2_carry_eqn = VD1_hilo_24_carry_1;
|
| 11315 |
|
|
VD1_hilo_24_add2 = VD1_hilo_33 $ VD1_un1_op2_reged_1_combout[2] $ !VD1_hilo_24_add2_carry_eqn;
|
| 11316 |
|
|
|
| 11317 |
|
|
--VD1_hilo_24_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_2
|
| 11318 |
|
|
--operation mode is arithmetic
|
| 11319 |
|
|
|
| 11320 |
|
|
VD1_hilo_24_carry_2 = CARRY(VD1_hilo_33 & VD1_un1_op2_reged_1_combout[2] # !VD1_hilo_24_carry_1 # !VD1_hilo_33 & VD1_un1_op2_reged_1_combout[2] & !VD1_hilo_24_carry_1);
|
| 11321 |
|
|
|
| 11322 |
|
|
|
| 11323 |
|
|
--VD1_hilo_37_iv_0_2[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[34]
|
| 11324 |
|
|
--operation mode is normal
|
| 11325 |
|
|
|
| 11326 |
|
|
VD1_hilo_37_iv_0_2[34] = VD1_hilo_37_iv_0_a2_0[38] # VD1_hilo_37_iv_0_2_a[34] # !VD1_hilo_34 & VD1_hilo_37_iv_0_o3_2[34];
|
| 11327 |
|
|
|
| 11328 |
|
|
|
| 11329 |
|
|
--VD1_hilo_37_iv_0_o3_1[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1[34]
|
| 11330 |
|
|
--operation mode is normal
|
| 11331 |
|
|
|
| 11332 |
|
|
VD1_hilo_37_iv_0_o3_1[34] = VD1_hilo_37_iv_0_o3_1_a[34] # !VD1_un59_hilo_add3 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 11333 |
|
|
|
| 11334 |
|
|
|
| 11335 |
|
|
--VD1_hilo_37_iv_0[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[3]
|
| 11336 |
|
|
--operation mode is normal
|
| 11337 |
|
|
|
| 11338 |
|
|
VD1_hilo_37_iv_0[3] = VD1_hilo_4 & VD1_hilo_1_sqmuxa_1 # VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[3] # !VD1_hilo_4 & VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[3];
|
| 11339 |
|
|
|
| 11340 |
|
|
|
| 11341 |
|
|
--VD1_hilo_8_Z[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[3]
|
| 11342 |
|
|
--operation mode is normal
|
| 11343 |
|
|
|
| 11344 |
|
|
VD1_hilo_8_Z[3] = RC1_alu_func_o_0 & VD1_hilo_3 # !RC1_alu_func_o_0 & PD1_a_o_3;
|
| 11345 |
|
|
|
| 11346 |
|
|
|
| 11347 |
|
|
--VD1_hilo_37_iv_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[3]
|
| 11348 |
|
|
--operation mode is normal
|
| 11349 |
|
|
|
| 11350 |
|
|
VD1_hilo_37_iv_a[3] = VD1_hilo_2 & !VD1_hilo_2_sqmuxa & !PD1_a_o_3 # !VD1_addnop2109_0_a2 # !VD1_hilo_2 & !PD1_a_o_3 # !VD1_addnop2109_0_a2;
|
| 11351 |
|
|
|
| 11352 |
|
|
|
| 11353 |
|
|
--VD1_hilo_37_iv_2[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[35]
|
| 11354 |
|
|
--operation mode is normal
|
| 11355 |
|
|
|
| 11356 |
|
|
VD1_hilo_37_iv_2[35] = VD1_hilo_33_i_m[35] # VD1_hilo_37_iv_2_a[35] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[35];
|
| 11357 |
|
|
|
| 11358 |
|
|
|
| 11359 |
|
|
--VD1_hilo_37_iv_a[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[35]
|
| 11360 |
|
|
--operation mode is normal
|
| 11361 |
|
|
|
| 11362 |
|
|
VD1_hilo_37_iv_a[35] = RC1_alu_func_o_0 & !PD1_a_o_3 # !RC1_alu_func_o_0 & !VD1_hilo_35;
|
| 11363 |
|
|
|
| 11364 |
|
|
|
| 11365 |
|
|
--UD1_shift_out_80_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[3]
|
| 11366 |
|
|
--operation mode is normal
|
| 11367 |
|
|
|
| 11368 |
|
|
UD1_shift_out_80_a[3] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_6 # !PD1_a_o_1 & !VD1_b_o_iv_4;
|
| 11369 |
|
|
|
| 11370 |
|
|
|
| 11371 |
|
|
--UD1_shift_out_79[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[3]
|
| 11372 |
|
|
--operation mode is normal
|
| 11373 |
|
|
|
| 11374 |
|
|
UD1_shift_out_79[3] = PD1_a_o_1 & UD1_shift_out_79_a[3] & VD1_b_o_iv_13 # !UD1_shift_out_79_a[3] & VD1_b_o_iv_14 # !PD1_a_o_1 & !UD1_shift_out_79_a[3];
|
| 11375 |
|
|
|
| 11376 |
|
|
|
| 11377 |
|
|
--UD1_shift_out_76_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[3]
|
| 11378 |
|
|
--operation mode is normal
|
| 11379 |
|
|
|
| 11380 |
|
|
UD1_shift_out_76_a[3] = PD1_a_o_3 & !PD1_a_o_1 & UD1_shift_out_39[19] # !PD1_a_o_3 & UD1_shift_out_79[15];
|
| 11381 |
|
|
|
| 11382 |
|
|
|
| 11383 |
|
|
--UD1_shift_out_74_c[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_c[3]
|
| 11384 |
|
|
--operation mode is normal
|
| 11385 |
|
|
|
| 11386 |
|
|
UD1_shift_out_74_c[3] = PD1_a_o_2 & PD1_a_o_3 # !PD1_a_o_2 & PD1_a_o_3 & UD1_shift_out_79[19] # !PD1_a_o_3 & UD1_shift_out_79[11];
|
| 11387 |
|
|
|
| 11388 |
|
|
|
| 11389 |
|
|
--YB1_alu_func_2_0_0_a2_0[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_0[1]
|
| 11390 |
|
|
--operation mode is normal
|
| 11391 |
|
|
|
| 11392 |
|
|
YB1_alu_func_2_0_0_a2_0[1] = !KE1_q_a[4] & !KE1_q_a[5] & !KE1_q_a[7] & !KE1_q_a[3];
|
| 11393 |
|
|
|
| 11394 |
|
|
|
| 11395 |
|
|
--YB1_fsm_dly_2_0_0_o2_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_o2_x[2]
|
| 11396 |
|
|
--operation mode is normal
|
| 11397 |
|
|
|
| 11398 |
|
|
YB1_fsm_dly_2_0_0_o2_x[2] = YB1_cmp_ctl_2_0_0_a2_1[0] # YB1_cmp_ctl_2_0_0_a2_0[0];
|
| 11399 |
|
|
|
| 11400 |
|
|
|
| 11401 |
|
|
--YB1_alu_func_2_0_0_a3_1_x[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_1_x[4]
|
| 11402 |
|
|
--operation mode is normal
|
| 11403 |
|
|
|
| 11404 |
|
|
YB1_alu_func_2_0_0_a3_1_x[4] = !JE1_q_a[7] & YB1_alu_func_2_0_0_a2_0[1] & YB1_fsm_dly_2_0_0_a2_0[2];
|
| 11405 |
|
|
|
| 11406 |
|
|
|
| 11407 |
|
|
--YB1_un1_ins_i_23_2_0_a_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_23_2_0_a_x
|
| 11408 |
|
|
--operation mode is normal
|
| 11409 |
|
|
|
| 11410 |
|
|
YB1_un1_ins_i_23_2_0_a_x = !KE1_q_a[6] & KE1_q_a[7] & !KE1_q_a[2];
|
| 11411 |
|
|
|
| 11412 |
|
|
|
| 11413 |
|
|
--YB1_muxa_ctl373_a_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl373_a_x
|
| 11414 |
|
|
--operation mode is normal
|
| 11415 |
|
|
|
| 11416 |
|
|
YB1_muxa_ctl373_a_x = !KE1_q_a[7] # !KE1_q_a[5] # !KE1_q_a[2];
|
| 11417 |
|
|
|
| 11418 |
|
|
|
| 11419 |
|
|
--YB1_dmem_ctl_2_0_0_a_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_a_x[1]
|
| 11420 |
|
|
--operation mode is normal
|
| 11421 |
|
|
|
| 11422 |
|
|
YB1_dmem_ctl_2_0_0_a_x[1] = !YB1_cmp_ctl_2_0_0_a2_0[0] & !YB1_cmp_ctl_2_0_0_a2_1[0];
|
| 11423 |
|
|
|
| 11424 |
|
|
|
| 11425 |
|
|
--YB1_dmem_ctl_2_0_0_1_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_1_Z[1]
|
| 11426 |
|
|
--operation mode is normal
|
| 11427 |
|
|
|
| 11428 |
|
|
YB1_dmem_ctl_2_0_0_1_Z[1] = YB1_alu_func_2_0_0_a3_1_x[4] # !KE1_q_a[5] & !KE1_q_a[6] & YB1_dmem_ctl_2_0_0_1_a[1];
|
| 11429 |
|
|
|
| 11430 |
|
|
|
| 11431 |
|
|
--UD1_shift_out_87_d[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[16]
|
| 11432 |
|
|
--operation mode is normal
|
| 11433 |
|
|
|
| 11434 |
|
|
UD1_shift_out_87_d[16] = PD1_a_o_0 & UD1_shift_out_80[16] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[16];
|
| 11435 |
|
|
|
| 11436 |
|
|
|
| 11437 |
|
|
--UD1_shift_out_85_d[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[16]
|
| 11438 |
|
|
--operation mode is normal
|
| 11439 |
|
|
|
| 11440 |
|
|
UD1_shift_out_85_d[16] = PD1_a_o_2 & UD1_shift_out_52[28] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[16];
|
| 11441 |
|
|
|
| 11442 |
|
|
|
| 11443 |
|
|
--UD1_shift_out_86_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[16]
|
| 11444 |
|
|
--operation mode is normal
|
| 11445 |
|
|
|
| 11446 |
|
|
UD1_shift_out_86_a[16] = UD1_shift_out587 & !PD1_a_o_2;
|
| 11447 |
|
|
|
| 11448 |
|
|
|
| 11449 |
|
|
--UD1_shift_out_92_d_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[16]
|
| 11450 |
|
|
--operation mode is normal
|
| 11451 |
|
|
|
| 11452 |
|
|
UD1_shift_out_92_d_a[16] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_16 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[16];
|
| 11453 |
|
|
|
| 11454 |
|
|
|
| 11455 |
|
|
--UD1_shift_out_84[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[16]
|
| 11456 |
|
|
--operation mode is normal
|
| 11457 |
|
|
|
| 11458 |
|
|
UD1_shift_out_84[16] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_92_d_a[8] # !PD1_a_o_4 & UD1_shift_out_77[16];
|
| 11459 |
|
|
|
| 11460 |
|
|
|
| 11461 |
|
|
--VD1_hilo_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_16
|
| 11462 |
|
|
--operation mode is normal
|
| 11463 |
|
|
|
| 11464 |
|
|
VD1_hilo_16_lut_out = VD1_hilo_37_iv_0_0[16] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_16 # !VD1_hilo_37_iv_0_a[16];
|
| 11465 |
|
|
VD1_hilo_16 = DFFEAS(VD1_hilo_16_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11466 |
|
|
|
| 11467 |
|
|
|
| 11468 |
|
|
--VD1_hilo_48 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_48
|
| 11469 |
|
|
--operation mode is normal
|
| 11470 |
|
|
|
| 11471 |
|
|
VD1_hilo_48_lut_out = !VD1_hilo_37_iv_2[48] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[48] # !VD1_hilo25;
|
| 11472 |
|
|
VD1_hilo_48 = DFFEAS(VD1_hilo_48_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11473 |
|
|
|
| 11474 |
|
|
|
| 11475 |
|
|
--PD1_a_o_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_16
|
| 11476 |
|
|
--operation mode is normal
|
| 11477 |
|
|
|
| 11478 |
|
|
PD1_a_o_16 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[16] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[16];
|
| 11479 |
|
|
|
| 11480 |
|
|
|
| 11481 |
|
|
--TD1_m36_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m36_a
|
| 11482 |
|
|
--operation mode is normal
|
| 11483 |
|
|
|
| 11484 |
|
|
TD1_m36_a = VD1_b_o_iv_16 & !TD1_m9 & PD1_a_o_16 # !VD1_b_o_iv_16 & !TD1_m5 # !PD1_a_o_16;
|
| 11485 |
|
|
|
| 11486 |
|
|
|
| 11487 |
|
|
--TD1_un1_a_add16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add16
|
| 11488 |
|
|
--operation mode is arithmetic
|
| 11489 |
|
|
|
| 11490 |
|
|
TD1_un1_a_add16_carry_eqn = TD1_un1_a_carry_15;
|
| 11491 |
|
|
TD1_un1_a_add16 = PD1_a_o_16 $ TD1_un1_b_1_combout[16] $ !TD1_un1_a_add16_carry_eqn;
|
| 11492 |
|
|
|
| 11493 |
|
|
--TD1_un1_a_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_16
|
| 11494 |
|
|
--operation mode is arithmetic
|
| 11495 |
|
|
|
| 11496 |
|
|
TD1_un1_a_carry_16 = CARRY(PD1_a_o_16 & TD1_un1_b_1_combout[16] # !TD1_un1_a_carry_15 # !PD1_a_o_16 & TD1_un1_b_1_combout[16] & !TD1_un1_a_carry_15);
|
| 11497 |
|
|
|
| 11498 |
|
|
|
| 11499 |
|
|
--UD1_shift_out_87_d[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[17]
|
| 11500 |
|
|
--operation mode is normal
|
| 11501 |
|
|
|
| 11502 |
|
|
UD1_shift_out_87_d[17] = PD1_a_o_0 & UD1_shift_out_80[17] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[17];
|
| 11503 |
|
|
|
| 11504 |
|
|
|
| 11505 |
|
|
--UD1_shift_out_85_d[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[17]
|
| 11506 |
|
|
--operation mode is normal
|
| 11507 |
|
|
|
| 11508 |
|
|
UD1_shift_out_85_d[17] = PD1_a_o_2 & UD1_shift_out_52[29] # !PD1_a_o_2 & !UD1_shift_out_77_a[23];
|
| 11509 |
|
|
|
| 11510 |
|
|
|
| 11511 |
|
|
--UD1_shift_out_83[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[17]
|
| 11512 |
|
|
--operation mode is normal
|
| 11513 |
|
|
|
| 11514 |
|
|
UD1_shift_out_83[17] = PD1_a_o_1 & VD1_b_o_iv_31 & UD1_shift_out_83_a[17] # !PD1_a_o_1 & UD1_shift_out_39[17] & !UD1_shift_out_83_a[17];
|
| 11515 |
|
|
|
| 11516 |
|
|
|
| 11517 |
|
|
--UD1_shift_out_92_d_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[17]
|
| 11518 |
|
|
--operation mode is normal
|
| 11519 |
|
|
|
| 11520 |
|
|
UD1_shift_out_92_d_a[17] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_17 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[17];
|
| 11521 |
|
|
|
| 11522 |
|
|
|
| 11523 |
|
|
--UD1_shift_out_84[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[17]
|
| 11524 |
|
|
--operation mode is normal
|
| 11525 |
|
|
|
| 11526 |
|
|
UD1_shift_out_84[17] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_63[17] # !PD1_a_o_4 & UD1_shift_out_63[25];
|
| 11527 |
|
|
|
| 11528 |
|
|
|
| 11529 |
|
|
--VD1_hilo_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_17
|
| 11530 |
|
|
--operation mode is normal
|
| 11531 |
|
|
|
| 11532 |
|
|
VD1_hilo_17_lut_out = VD1_hilo_37_iv_0_0[17] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_17 # !VD1_hilo_37_iv_0_a[17];
|
| 11533 |
|
|
VD1_hilo_17 = DFFEAS(VD1_hilo_17_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11534 |
|
|
|
| 11535 |
|
|
|
| 11536 |
|
|
--VD1_hilo_49 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_49
|
| 11537 |
|
|
--operation mode is normal
|
| 11538 |
|
|
|
| 11539 |
|
|
VD1_hilo_49_lut_out = !VD1_hilo_37_iv_2[49] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[49] # !VD1_hilo25;
|
| 11540 |
|
|
VD1_hilo_49 = DFFEAS(VD1_hilo_49_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11541 |
|
|
|
| 11542 |
|
|
|
| 11543 |
|
|
--PD1_a_o_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_17
|
| 11544 |
|
|
--operation mode is normal
|
| 11545 |
|
|
|
| 11546 |
|
|
PD1_a_o_17 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[17] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[17];
|
| 11547 |
|
|
|
| 11548 |
|
|
|
| 11549 |
|
|
--TD1_m41_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m41_a
|
| 11550 |
|
|
--operation mode is normal
|
| 11551 |
|
|
|
| 11552 |
|
|
TD1_m41_a = VD1_b_o_iv_17 & !TD1_m9 & PD1_a_o_17 # !VD1_b_o_iv_17 & !TD1_m5 # !PD1_a_o_17;
|
| 11553 |
|
|
|
| 11554 |
|
|
|
| 11555 |
|
|
--TD1_un1_a_add17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add17
|
| 11556 |
|
|
--operation mode is arithmetic
|
| 11557 |
|
|
|
| 11558 |
|
|
TD1_un1_a_add17_carry_eqn = TD1_un1_a_carry_16;
|
| 11559 |
|
|
TD1_un1_a_add17 = PD1_a_o_17 $ TD1_un1_b_1_combout[17] $ TD1_un1_a_add17_carry_eqn;
|
| 11560 |
|
|
|
| 11561 |
|
|
--TD1_un1_a_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_17
|
| 11562 |
|
|
--operation mode is arithmetic
|
| 11563 |
|
|
|
| 11564 |
|
|
TD1_un1_a_carry_17 = CARRY(PD1_a_o_17 & !TD1_un1_b_1_combout[17] & !TD1_un1_a_carry_16 # !PD1_a_o_17 & !TD1_un1_a_carry_16 # !TD1_un1_b_1_combout[17]);
|
| 11565 |
|
|
|
| 11566 |
|
|
|
| 11567 |
|
|
--UD1_shift_out_87_d[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[14]
|
| 11568 |
|
|
--operation mode is normal
|
| 11569 |
|
|
|
| 11570 |
|
|
UD1_shift_out_87_d[14] = PD1_a_o_0 & UD1_shift_out_80[14] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[14];
|
| 11571 |
|
|
|
| 11572 |
|
|
|
| 11573 |
|
|
--UD1_shift_out_85_d[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[14]
|
| 11574 |
|
|
--operation mode is normal
|
| 11575 |
|
|
|
| 11576 |
|
|
UD1_shift_out_85_d[14] = PD1_a_o_2 & UD1_shift_out_48[30] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[14];
|
| 11577 |
|
|
|
| 11578 |
|
|
|
| 11579 |
|
|
--UD1_shift_out_74[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[14]
|
| 11580 |
|
|
--operation mode is normal
|
| 11581 |
|
|
|
| 11582 |
|
|
UD1_shift_out_74[14] = VD1_b_o_iv_31 $ (!PD1_a_o_1 & !PD1_a_o_0 & UD1_shift_out_74_a[14]);
|
| 11583 |
|
|
|
| 11584 |
|
|
|
| 11585 |
|
|
--UD1_shift_out_83[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[14]
|
| 11586 |
|
|
--operation mode is normal
|
| 11587 |
|
|
|
| 11588 |
|
|
UD1_shift_out_83[14] = UD1_shift_out587 & PD1_a_o_2 & UD1_shift_out_79[18] # !PD1_a_o_2 & UD1_shift_out_83_a[14] # !UD1_shift_out587 & UD1_shift_out_79[18];
|
| 11589 |
|
|
|
| 11590 |
|
|
|
| 11591 |
|
|
--UD1_shift_out_63[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[22]
|
| 11592 |
|
|
--operation mode is normal
|
| 11593 |
|
|
|
| 11594 |
|
|
UD1_shift_out_63[22] = PD1_a_o_2 & UD1_shift_out_43[30] # !PD1_a_o_2 & UD1_shift_out_45[30];
|
| 11595 |
|
|
|
| 11596 |
|
|
|
| 11597 |
|
|
--UD1_shift_out_92_d_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[14]
|
| 11598 |
|
|
--operation mode is normal
|
| 11599 |
|
|
|
| 11600 |
|
|
UD1_shift_out_92_d_a[14] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_14 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[14] # !UD1_shift_out_sn_m17_0;
|
| 11601 |
|
|
|
| 11602 |
|
|
|
| 11603 |
|
|
--VD1_hilo_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_14
|
| 11604 |
|
|
--operation mode is normal
|
| 11605 |
|
|
|
| 11606 |
|
|
VD1_hilo_14_lut_out = VD1_hilo_37_iv_0_0[14] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_14 # !VD1_hilo_37_iv_0_a[14];
|
| 11607 |
|
|
VD1_hilo_14 = DFFEAS(VD1_hilo_14_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11608 |
|
|
|
| 11609 |
|
|
|
| 11610 |
|
|
--VD1_hilo_46 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_46
|
| 11611 |
|
|
--operation mode is normal
|
| 11612 |
|
|
|
| 11613 |
|
|
VD1_hilo_46_lut_out = !VD1_hilo_37_iv_2[46] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[46] # !VD1_hilo25;
|
| 11614 |
|
|
VD1_hilo_46 = DFFEAS(VD1_hilo_46_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11615 |
|
|
|
| 11616 |
|
|
|
| 11617 |
|
|
--PD1_a_o_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_14
|
| 11618 |
|
|
--operation mode is normal
|
| 11619 |
|
|
|
| 11620 |
|
|
PD1_a_o_14 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[14] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[14];
|
| 11621 |
|
|
|
| 11622 |
|
|
|
| 11623 |
|
|
--TD1_m26_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m26_a
|
| 11624 |
|
|
--operation mode is normal
|
| 11625 |
|
|
|
| 11626 |
|
|
TD1_m26_a = VD1_b_o_iv_14 & !TD1_m9 & PD1_a_o_14 # !VD1_b_o_iv_14 & !TD1_m5 # !PD1_a_o_14;
|
| 11627 |
|
|
|
| 11628 |
|
|
|
| 11629 |
|
|
--TD1_un1_a_add14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add14
|
| 11630 |
|
|
--operation mode is arithmetic
|
| 11631 |
|
|
|
| 11632 |
|
|
TD1_un1_a_add14_carry_eqn = TD1_un1_a_carry_13;
|
| 11633 |
|
|
TD1_un1_a_add14 = PD1_a_o_14 $ TD1_un1_b_1_combout[14] $ !TD1_un1_a_add14_carry_eqn;
|
| 11634 |
|
|
|
| 11635 |
|
|
--TD1_un1_a_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_14
|
| 11636 |
|
|
--operation mode is arithmetic
|
| 11637 |
|
|
|
| 11638 |
|
|
TD1_un1_a_carry_14 = CARRY(PD1_a_o_14 & TD1_un1_b_1_combout[14] # !TD1_un1_a_carry_13 # !PD1_a_o_14 & TD1_un1_b_1_combout[14] & !TD1_un1_a_carry_13);
|
| 11639 |
|
|
|
| 11640 |
|
|
|
| 11641 |
|
|
--UD1_shift_out_87_d[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[15]
|
| 11642 |
|
|
--operation mode is normal
|
| 11643 |
|
|
|
| 11644 |
|
|
UD1_shift_out_87_d[15] = PD1_a_o_0 & UD1_shift_out_80[15] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[15];
|
| 11645 |
|
|
|
| 11646 |
|
|
|
| 11647 |
|
|
--UD1_shift_out_85_d[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[15]
|
| 11648 |
|
|
--operation mode is normal
|
| 11649 |
|
|
|
| 11650 |
|
|
UD1_shift_out_85_d[15] = PD1_a_o_2 & UD1_shift_out_48[31] # !PD1_a_o_2 & !UD1_shift_out_77_a[21];
|
| 11651 |
|
|
|
| 11652 |
|
|
|
| 11653 |
|
|
--UD1_shift_out_83[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[15]
|
| 11654 |
|
|
--operation mode is normal
|
| 11655 |
|
|
|
| 11656 |
|
|
UD1_shift_out_83[15] = UD1_shift_out587 & PD1_a_o_2 & UD1_shift_out_79[19] # !PD1_a_o_2 & UD1_shift_out_83_a[15] # !UD1_shift_out587 & UD1_shift_out_79[19];
|
| 11657 |
|
|
|
| 11658 |
|
|
|
| 11659 |
|
|
--UD1_shift_out_63[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[23]
|
| 11660 |
|
|
--operation mode is normal
|
| 11661 |
|
|
|
| 11662 |
|
|
UD1_shift_out_63[23] = PD1_a_o_2 & UD1_shift_out_43[31] # !PD1_a_o_2 & UD1_shift_out_45[31];
|
| 11663 |
|
|
|
| 11664 |
|
|
|
| 11665 |
|
|
--UD1_shift_out_92_d_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[15]
|
| 11666 |
|
|
--operation mode is normal
|
| 11667 |
|
|
|
| 11668 |
|
|
UD1_shift_out_92_d_a[15] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_15 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[15] # !UD1_shift_out_sn_m17_0;
|
| 11669 |
|
|
|
| 11670 |
|
|
|
| 11671 |
|
|
--VD1_hilo_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15
|
| 11672 |
|
|
--operation mode is normal
|
| 11673 |
|
|
|
| 11674 |
|
|
VD1_hilo_15_lut_out = VD1_hilo_37_iv_0_0[15] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_15 # !VD1_hilo_37_iv_0_a[15];
|
| 11675 |
|
|
VD1_hilo_15 = DFFEAS(VD1_hilo_15_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11676 |
|
|
|
| 11677 |
|
|
|
| 11678 |
|
|
--VD1_hilo_47 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_47
|
| 11679 |
|
|
--operation mode is normal
|
| 11680 |
|
|
|
| 11681 |
|
|
VD1_hilo_47_lut_out = !VD1_hilo_37_iv_2[47] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[47] # !VD1_hilo25;
|
| 11682 |
|
|
VD1_hilo_47 = DFFEAS(VD1_hilo_47_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11683 |
|
|
|
| 11684 |
|
|
|
| 11685 |
|
|
--PD1_a_o_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_15
|
| 11686 |
|
|
--operation mode is normal
|
| 11687 |
|
|
|
| 11688 |
|
|
PD1_a_o_15 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[15] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[15];
|
| 11689 |
|
|
|
| 11690 |
|
|
|
| 11691 |
|
|
--TD1_m31_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m31_a
|
| 11692 |
|
|
--operation mode is normal
|
| 11693 |
|
|
|
| 11694 |
|
|
TD1_m31_a = VD1_b_o_iv_15 & !TD1_m9 & PD1_a_o_15 # !VD1_b_o_iv_15 & !TD1_m5 # !PD1_a_o_15;
|
| 11695 |
|
|
|
| 11696 |
|
|
|
| 11697 |
|
|
--TD1_un1_a_add15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add15
|
| 11698 |
|
|
--operation mode is arithmetic
|
| 11699 |
|
|
|
| 11700 |
|
|
TD1_un1_a_add15_carry_eqn = TD1_un1_a_carry_14;
|
| 11701 |
|
|
TD1_un1_a_add15 = PD1_a_o_15 $ TD1_un1_b_1_combout[15] $ TD1_un1_a_add15_carry_eqn;
|
| 11702 |
|
|
|
| 11703 |
|
|
--TD1_un1_a_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_15
|
| 11704 |
|
|
--operation mode is arithmetic
|
| 11705 |
|
|
|
| 11706 |
|
|
TD1_un1_a_carry_15 = CARRY(PD1_a_o_15 & !TD1_un1_b_1_combout[15] & !TD1_un1_a_carry_14 # !PD1_a_o_15 & !TD1_un1_a_carry_14 # !TD1_un1_b_1_combout[15]);
|
| 11707 |
|
|
|
| 11708 |
|
|
|
| 11709 |
|
|
--UD1_shift_out_68[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[27]
|
| 11710 |
|
|
--operation mode is normal
|
| 11711 |
|
|
|
| 11712 |
|
|
UD1_shift_out_68[27] = PD1_a_o_0 & VD1_b_o_iv_24 # !PD1_a_o_0 & VD1_b_o_iv_25;
|
| 11713 |
|
|
|
| 11714 |
|
|
|
| 11715 |
|
|
--UD1_shift_out_68[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[29]
|
| 11716 |
|
|
--operation mode is normal
|
| 11717 |
|
|
|
| 11718 |
|
|
UD1_shift_out_68[29] = PD1_a_o_0 & VD1_b_o_iv_26 # !PD1_a_o_0 & VD1_b_o_iv_27;
|
| 11719 |
|
|
|
| 11720 |
|
|
|
| 11721 |
|
|
--UD1_shift_out_85_c[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_c[31]
|
| 11722 |
|
|
--operation mode is normal
|
| 11723 |
|
|
|
| 11724 |
|
|
UD1_shift_out_85_c[31] = PD1_a_o_2 & PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_68[31] # !PD1_a_o_1 & VD1_b_o_iv_30;
|
| 11725 |
|
|
|
| 11726 |
|
|
|
| 11727 |
|
|
--UD1_shift_out_92_d_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[31]
|
| 11728 |
|
|
--operation mode is normal
|
| 11729 |
|
|
|
| 11730 |
|
|
UD1_shift_out_92_d_a[31] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_31 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
|
| 11731 |
|
|
|
| 11732 |
|
|
|
| 11733 |
|
|
--UD1_shift_out_84[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[31]
|
| 11734 |
|
|
--operation mode is normal
|
| 11735 |
|
|
|
| 11736 |
|
|
UD1_shift_out_84[31] = PD1_a_o_4 & UD1_shift_out_75[31] # !PD1_a_o_4 & UD1_shift_out_77[31];
|
| 11737 |
|
|
|
| 11738 |
|
|
|
| 11739 |
|
|
--VD1_hilo_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_31
|
| 11740 |
|
|
--operation mode is normal
|
| 11741 |
|
|
|
| 11742 |
|
|
VD1_hilo_31_lut_out = PD1_a_o_31 & VD1_addnop2109_0_a2 # VD1_hilo_37_iv_0_a3_1[62] # !VD1_hilo_37_iv_0_a[31];
|
| 11743 |
|
|
VD1_hilo_31 = DFFEAS(VD1_hilo_31_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11744 |
|
|
|
| 11745 |
|
|
|
| 11746 |
|
|
--VD1_hilo_63 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_63
|
| 11747 |
|
|
--operation mode is normal
|
| 11748 |
|
|
|
| 11749 |
|
|
VD1_hilo_63_lut_out = !VD1_hilo_37_iv_2[63] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[63] # !VD1_hilo25;
|
| 11750 |
|
|
VD1_hilo_63 = DFFEAS(VD1_hilo_63_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11751 |
|
|
|
| 11752 |
|
|
|
| 11753 |
|
|
--TD1_m101_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m101_a
|
| 11754 |
|
|
--operation mode is normal
|
| 11755 |
|
|
|
| 11756 |
|
|
TD1_m101_a = VD1_b_o_iv_31 & !PD1_a_o_31 # !VD1_b_o_iv_31 & PD1_a_o_31 & !TD1_m5 # !PD1_a_o_31 & !TD1_m4;
|
| 11757 |
|
|
|
| 11758 |
|
|
|
| 11759 |
|
|
--TD1_un1_a_add31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add31
|
| 11760 |
|
|
--operation mode is normal
|
| 11761 |
|
|
|
| 11762 |
|
|
TD1_un1_a_add31_carry_eqn = TD1_un1_a_carry_30;
|
| 11763 |
|
|
TD1_un1_a_add31 = PD1_a_o_31 $ TD1_un1_b_1_combout[31] $ TD1_un1_a_add31_carry_eqn;
|
| 11764 |
|
|
|
| 11765 |
|
|
|
| 11766 |
|
|
--UD1_shift_out_87[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[8]
|
| 11767 |
|
|
--operation mode is normal
|
| 11768 |
|
|
|
| 11769 |
|
|
UD1_shift_out_87[8] = PD1_a_o_2 & UD1_shift_out_87_d[8] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[8] # !PD1_a_o_0 & VD1_b_o_iv_10;
|
| 11770 |
|
|
|
| 11771 |
|
|
|
| 11772 |
|
|
--UD1_shift_out_89_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[8]
|
| 11773 |
|
|
--operation mode is normal
|
| 11774 |
|
|
|
| 11775 |
|
|
UD1_shift_out_89_a[8] = PD1_a_o_2 & !UD1_shift_out_85_d[8] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[8] # !PD1_a_o_1 & !VD1_b_o_iv_7;
|
| 11776 |
|
|
|
| 11777 |
|
|
|
| 11778 |
|
|
--UD1_shift_out_86_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_8
|
| 11779 |
|
|
--operation mode is normal
|
| 11780 |
|
|
|
| 11781 |
|
|
UD1_shift_out_86_8 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[8] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[8];
|
| 11782 |
|
|
|
| 11783 |
|
|
|
| 11784 |
|
|
--UD1_shift_out_92_d_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_0
|
| 11785 |
|
|
--operation mode is normal
|
| 11786 |
|
|
|
| 11787 |
|
|
UD1_shift_out_92_d_0 = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[8] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_92_d_a[8];
|
| 11788 |
|
|
|
| 11789 |
|
|
|
| 11790 |
|
|
--MD1_c_0_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[8]
|
| 11791 |
|
|
--operation mode is normal
|
| 11792 |
|
|
|
| 11793 |
|
|
MD1_c_0_a[8] = VD1_un24_res & !VD1_hilo_40 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_8;
|
| 11794 |
|
|
|
| 11795 |
|
|
|
| 11796 |
|
|
--TD1_m16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m16
|
| 11797 |
|
|
--operation mode is normal
|
| 11798 |
|
|
|
| 11799 |
|
|
TD1_m16 = PD1_a_o_8 & TD1_m16_a # !PD1_a_o_8 & TD1_m16_a & !TD1_m4 # !TD1_m16_a & TD1_m7;
|
| 11800 |
|
|
|
| 11801 |
|
|
|
| 11802 |
|
|
--TD1_m13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m13
|
| 11803 |
|
|
--operation mode is normal
|
| 11804 |
|
|
|
| 11805 |
|
|
TD1_m13 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add8;
|
| 11806 |
|
|
|
| 11807 |
|
|
|
| 11808 |
|
|
--UD1_shift_out_87[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[9]
|
| 11809 |
|
|
--operation mode is normal
|
| 11810 |
|
|
|
| 11811 |
|
|
UD1_shift_out_87[9] = PD1_a_o_2 & UD1_shift_out_87_d[9] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[9] # !PD1_a_o_0 & VD1_b_o_iv_11;
|
| 11812 |
|
|
|
| 11813 |
|
|
|
| 11814 |
|
|
--UD1_shift_out_89_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[9]
|
| 11815 |
|
|
--operation mode is normal
|
| 11816 |
|
|
|
| 11817 |
|
|
UD1_shift_out_89_a[9] = PD1_a_o_2 & !UD1_shift_out_85_d[9] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[9] # !PD1_a_o_1 & !VD1_b_o_iv_8;
|
| 11818 |
|
|
|
| 11819 |
|
|
|
| 11820 |
|
|
--UD1_shift_out_86_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_9
|
| 11821 |
|
|
--operation mode is normal
|
| 11822 |
|
|
|
| 11823 |
|
|
UD1_shift_out_86_9 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[9] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[9];
|
| 11824 |
|
|
|
| 11825 |
|
|
|
| 11826 |
|
|
--UD1_shift_out_92_d_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_1
|
| 11827 |
|
|
--operation mode is normal
|
| 11828 |
|
|
|
| 11829 |
|
|
UD1_shift_out_92_d_1 = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[9] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d_a[9] & UD1_shift_out_63_a[17];
|
| 11830 |
|
|
|
| 11831 |
|
|
|
| 11832 |
|
|
--MD1_c_0_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[9]
|
| 11833 |
|
|
--operation mode is normal
|
| 11834 |
|
|
|
| 11835 |
|
|
MD1_c_0_a[9] = VD1_un24_res & !VD1_hilo_41 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_9;
|
| 11836 |
|
|
|
| 11837 |
|
|
|
| 11838 |
|
|
--TD1_m117 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m117
|
| 11839 |
|
|
--operation mode is normal
|
| 11840 |
|
|
|
| 11841 |
|
|
TD1_m117 = PD1_a_o_9 & TD1_m117_a # !PD1_a_o_9 & TD1_m117_a & !TD1_m4 # !TD1_m117_a & TD1_m7;
|
| 11842 |
|
|
|
| 11843 |
|
|
|
| 11844 |
|
|
--TD1_m114 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m114
|
| 11845 |
|
|
--operation mode is normal
|
| 11846 |
|
|
|
| 11847 |
|
|
TD1_m114 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add9;
|
| 11848 |
|
|
|
| 11849 |
|
|
|
| 11850 |
|
|
--MD1_c_1_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_a[10]
|
| 11851 |
|
|
--operation mode is normal
|
| 11852 |
|
|
|
| 11853 |
|
|
MD1_c_1_a[10] = VD1_un24_res & !VD1_hilo_42 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_10;
|
| 11854 |
|
|
|
| 11855 |
|
|
|
| 11856 |
|
|
--TD1_alu_out_0_a2_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_4
|
| 11857 |
|
|
--operation mode is normal
|
| 11858 |
|
|
|
| 11859 |
|
|
TD1_alu_out_0_a2_4 = TD1_alu_out_sn_m14_0_0 & PD1_a_o_10 & !TD1_alu_out_0_a2_a[10] # !PD1_a_o_10 & TD1_alu_out_7_0_0_m4_0[10];
|
| 11860 |
|
|
|
| 11861 |
|
|
|
| 11862 |
|
|
--PD1_a_o_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_10
|
| 11863 |
|
|
--operation mode is normal
|
| 11864 |
|
|
|
| 11865 |
|
|
PD1_a_o_10 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[10] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[10];
|
| 11866 |
|
|
|
| 11867 |
|
|
|
| 11868 |
|
|
--TD1_un1_b_1_combout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[10]
|
| 11869 |
|
|
--operation mode is normal
|
| 11870 |
|
|
|
| 11871 |
|
|
TD1_un1_b_1_combout[10] = TD1_sum13_0_a2 $ !VD1_b_o_iv_10;
|
| 11872 |
|
|
|
| 11873 |
|
|
|
| 11874 |
|
|
--TD1_un1_a_add9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add9
|
| 11875 |
|
|
--operation mode is arithmetic
|
| 11876 |
|
|
|
| 11877 |
|
|
TD1_un1_a_add9_carry_eqn = TD1_un1_a_carry_8;
|
| 11878 |
|
|
TD1_un1_a_add9 = PD1_a_o_9 $ TD1_un1_b_1_combout[9] $ TD1_un1_a_add9_carry_eqn;
|
| 11879 |
|
|
|
| 11880 |
|
|
--TD1_un1_a_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_9
|
| 11881 |
|
|
--operation mode is arithmetic
|
| 11882 |
|
|
|
| 11883 |
|
|
TD1_un1_a_carry_9 = CARRY(PD1_a_o_9 & !TD1_un1_b_1_combout[9] & !TD1_un1_a_carry_8 # !PD1_a_o_9 & !TD1_un1_a_carry_8 # !TD1_un1_b_1_combout[9]);
|
| 11884 |
|
|
|
| 11885 |
|
|
|
| 11886 |
|
|
--UD1_shift_out_89[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[10]
|
| 11887 |
|
|
--operation mode is normal
|
| 11888 |
|
|
|
| 11889 |
|
|
UD1_shift_out_89[10] = UD1_shift_out586 & !UD1_shift_out_89_a[10] # !UD1_shift_out586 & UD1_shift_out_87[10];
|
| 11890 |
|
|
|
| 11891 |
|
|
|
| 11892 |
|
|
--UD1_shift_out_92[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92[10]
|
| 11893 |
|
|
--operation mode is normal
|
| 11894 |
|
|
|
| 11895 |
|
|
UD1_shift_out_92[10] = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[10] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_92_a[10];
|
| 11896 |
|
|
|
| 11897 |
|
|
|
| 11898 |
|
|
--UD1_shift_out_87[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[11]
|
| 11899 |
|
|
--operation mode is normal
|
| 11900 |
|
|
|
| 11901 |
|
|
UD1_shift_out_87[11] = PD1_a_o_2 & UD1_shift_out_87_d[11] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[11] # !PD1_a_o_0 & VD1_b_o_iv_13;
|
| 11902 |
|
|
|
| 11903 |
|
|
|
| 11904 |
|
|
--UD1_shift_out_89_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[11]
|
| 11905 |
|
|
--operation mode is normal
|
| 11906 |
|
|
|
| 11907 |
|
|
UD1_shift_out_89_a[11] = PD1_a_o_2 & !UD1_shift_out_85_d[11] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[11] # !PD1_a_o_1 & !VD1_b_o_iv_10;
|
| 11908 |
|
|
|
| 11909 |
|
|
|
| 11910 |
|
|
--UD1_shift_out_86_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_11
|
| 11911 |
|
|
--operation mode is normal
|
| 11912 |
|
|
|
| 11913 |
|
|
UD1_shift_out_86_11 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[11] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[11];
|
| 11914 |
|
|
|
| 11915 |
|
|
|
| 11916 |
|
|
--UD1_shift_out_92_d_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_3
|
| 11917 |
|
|
--operation mode is normal
|
| 11918 |
|
|
|
| 11919 |
|
|
UD1_shift_out_92_d_3 = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[11] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_77[11];
|
| 11920 |
|
|
|
| 11921 |
|
|
|
| 11922 |
|
|
--MD1_c_0_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[11]
|
| 11923 |
|
|
--operation mode is normal
|
| 11924 |
|
|
|
| 11925 |
|
|
MD1_c_0_a[11] = VD1_un24_res & !VD1_hilo_43 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_11;
|
| 11926 |
|
|
|
| 11927 |
|
|
|
| 11928 |
|
|
--TD1_m21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m21
|
| 11929 |
|
|
--operation mode is normal
|
| 11930 |
|
|
|
| 11931 |
|
|
TD1_m21 = PD1_a_o_11 & TD1_m21_a # !PD1_a_o_11 & TD1_m21_a & !TD1_m4 # !TD1_m21_a & TD1_m7;
|
| 11932 |
|
|
|
| 11933 |
|
|
|
| 11934 |
|
|
--TD1_m18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m18
|
| 11935 |
|
|
--operation mode is normal
|
| 11936 |
|
|
|
| 11937 |
|
|
TD1_m18 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add11;
|
| 11938 |
|
|
|
| 11939 |
|
|
|
| 11940 |
|
|
--UD1_shift_out_87_d[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[21]
|
| 11941 |
|
|
--operation mode is normal
|
| 11942 |
|
|
|
| 11943 |
|
|
UD1_shift_out_87_d[21] = PD1_a_o_0 & UD1_shift_out_80[21] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[21];
|
| 11944 |
|
|
|
| 11945 |
|
|
|
| 11946 |
|
|
--UD1_shift_out_85_d[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[21]
|
| 11947 |
|
|
--operation mode is normal
|
| 11948 |
|
|
|
| 11949 |
|
|
UD1_shift_out_85_d[21] = PD1_a_o_2 & UD1_shift_out_54[29] # !PD1_a_o_2 & !UD1_shift_out_77_a[27];
|
| 11950 |
|
|
|
| 11951 |
|
|
|
| 11952 |
|
|
--UD1_shift_out_92_d_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[21]
|
| 11953 |
|
|
--operation mode is normal
|
| 11954 |
|
|
|
| 11955 |
|
|
UD1_shift_out_92_d_a[21] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_21 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[21];
|
| 11956 |
|
|
|
| 11957 |
|
|
|
| 11958 |
|
|
--UD1_shift_out_84[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[21]
|
| 11959 |
|
|
--operation mode is normal
|
| 11960 |
|
|
|
| 11961 |
|
|
UD1_shift_out_84[21] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_63[21] # !PD1_a_o_4 & UD1_shift_out_77[21];
|
| 11962 |
|
|
|
| 11963 |
|
|
|
| 11964 |
|
|
--VD1_hilo_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_21
|
| 11965 |
|
|
--operation mode is normal
|
| 11966 |
|
|
|
| 11967 |
|
|
VD1_hilo_21_lut_out = VD1_hilo_37_iv_0_0[21] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_21 # !VD1_hilo_37_iv_0_a[21];
|
| 11968 |
|
|
VD1_hilo_21 = DFFEAS(VD1_hilo_21_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11969 |
|
|
|
| 11970 |
|
|
|
| 11971 |
|
|
--VD1_hilo_53 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_53
|
| 11972 |
|
|
--operation mode is normal
|
| 11973 |
|
|
|
| 11974 |
|
|
VD1_hilo_53_lut_out = !VD1_hilo_37_iv_2[53] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[53] # !VD1_hilo25;
|
| 11975 |
|
|
VD1_hilo_53 = DFFEAS(VD1_hilo_53_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 11976 |
|
|
|
| 11977 |
|
|
|
| 11978 |
|
|
--PD1_a_o_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_21
|
| 11979 |
|
|
--operation mode is normal
|
| 11980 |
|
|
|
| 11981 |
|
|
PD1_a_o_21 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[21] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[21];
|
| 11982 |
|
|
|
| 11983 |
|
|
|
| 11984 |
|
|
--TD1_m132_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m132_a
|
| 11985 |
|
|
--operation mode is normal
|
| 11986 |
|
|
|
| 11987 |
|
|
TD1_m132_a = VD1_b_o_iv_21 & !TD1_m9 & PD1_a_o_21 # !VD1_b_o_iv_21 & !TD1_m5 # !PD1_a_o_21;
|
| 11988 |
|
|
|
| 11989 |
|
|
|
| 11990 |
|
|
--TD1_un1_a_add21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add21
|
| 11991 |
|
|
--operation mode is arithmetic
|
| 11992 |
|
|
|
| 11993 |
|
|
TD1_un1_a_add21_carry_eqn = TD1_un1_a_carry_20;
|
| 11994 |
|
|
TD1_un1_a_add21 = PD1_a_o_21 $ TD1_un1_b_1_combout[21] $ TD1_un1_a_add21_carry_eqn;
|
| 11995 |
|
|
|
| 11996 |
|
|
--TD1_un1_a_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_21
|
| 11997 |
|
|
--operation mode is arithmetic
|
| 11998 |
|
|
|
| 11999 |
|
|
TD1_un1_a_carry_21 = CARRY(PD1_a_o_21 & !TD1_un1_b_1_combout[21] & !TD1_un1_a_carry_20 # !PD1_a_o_21 & !TD1_un1_a_carry_20 # !TD1_un1_b_1_combout[21]);
|
| 12000 |
|
|
|
| 12001 |
|
|
|
| 12002 |
|
|
--UD1_shift_out_87_d[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[20]
|
| 12003 |
|
|
--operation mode is normal
|
| 12004 |
|
|
|
| 12005 |
|
|
UD1_shift_out_87_d[20] = PD1_a_o_0 & UD1_shift_out_80[20] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[20];
|
| 12006 |
|
|
|
| 12007 |
|
|
|
| 12008 |
|
|
--UD1_shift_out_85_d[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[20]
|
| 12009 |
|
|
--operation mode is normal
|
| 12010 |
|
|
|
| 12011 |
|
|
UD1_shift_out_85_d[20] = PD1_a_o_2 & UD1_shift_out_54[28] # !PD1_a_o_2 & !UD1_shift_out_77_a[26];
|
| 12012 |
|
|
|
| 12013 |
|
|
|
| 12014 |
|
|
--VD1_hilo_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_20
|
| 12015 |
|
|
--operation mode is normal
|
| 12016 |
|
|
|
| 12017 |
|
|
VD1_hilo_20_lut_out = VD1_hilo_37_iv_0_0[20] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_20 # !VD1_hilo_37_iv_0_a[20];
|
| 12018 |
|
|
VD1_hilo_20 = DFFEAS(VD1_hilo_20_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 12019 |
|
|
|
| 12020 |
|
|
|
| 12021 |
|
|
--VD1_hilo_52 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_52
|
| 12022 |
|
|
--operation mode is normal
|
| 12023 |
|
|
|
| 12024 |
|
|
VD1_hilo_52_lut_out = VD1_hilo_37_iv_0_a[52] & !VD1_hilo_37_iv_0_a3[57] & PD1_a_o_20 # !VD1_hilo_37_iv_0_a3_1[0];
|
| 12025 |
|
|
VD1_hilo_52 = DFFEAS(VD1_hilo_52_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 12026 |
|
|
|
| 12027 |
|
|
|
| 12028 |
|
|
--PD1_a_o_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_20
|
| 12029 |
|
|
--operation mode is normal
|
| 12030 |
|
|
|
| 12031 |
|
|
PD1_a_o_20 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[20] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[20];
|
| 12032 |
|
|
|
| 12033 |
|
|
|
| 12034 |
|
|
--TD1_m56_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m56_a
|
| 12035 |
|
|
--operation mode is normal
|
| 12036 |
|
|
|
| 12037 |
|
|
TD1_m56_a = VD1_b_o_iv_20 & !TD1_m9 & PD1_a_o_20 # !VD1_b_o_iv_20 & !TD1_m5 # !PD1_a_o_20;
|
| 12038 |
|
|
|
| 12039 |
|
|
|
| 12040 |
|
|
--TD1_un1_a_add20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add20
|
| 12041 |
|
|
--operation mode is arithmetic
|
| 12042 |
|
|
|
| 12043 |
|
|
TD1_un1_a_add20_carry_eqn = TD1_un1_a_carry_19;
|
| 12044 |
|
|
TD1_un1_a_add20 = PD1_a_o_20 $ TD1_un1_b_1_combout[20] $ !TD1_un1_a_add20_carry_eqn;
|
| 12045 |
|
|
|
| 12046 |
|
|
--TD1_un1_a_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_20
|
| 12047 |
|
|
--operation mode is arithmetic
|
| 12048 |
|
|
|
| 12049 |
|
|
TD1_un1_a_carry_20 = CARRY(PD1_a_o_20 & TD1_un1_b_1_combout[20] # !TD1_un1_a_carry_19 # !PD1_a_o_20 & TD1_un1_b_1_combout[20] & !TD1_un1_a_carry_19);
|
| 12050 |
|
|
|
| 12051 |
|
|
|
| 12052 |
|
|
--UD1_shift_out_92_d_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[20]
|
| 12053 |
|
|
--operation mode is normal
|
| 12054 |
|
|
|
| 12055 |
|
|
UD1_shift_out_92_d_a[20] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_20 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[20];
|
| 12056 |
|
|
|
| 12057 |
|
|
|
| 12058 |
|
|
--UD1_shift_out_84[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[20]
|
| 12059 |
|
|
--operation mode is normal
|
| 12060 |
|
|
|
| 12061 |
|
|
UD1_shift_out_84[20] = PD1_a_o_4 & !PD1_a_o_3 & !UD1_shift_out_84_a[20] # !PD1_a_o_4 & UD1_shift_out_63[28];
|
| 12062 |
|
|
|
| 12063 |
|
|
|
| 12064 |
|
|
--UD1_shift_out_87[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[19]
|
| 12065 |
|
|
--operation mode is normal
|
| 12066 |
|
|
|
| 12067 |
|
|
UD1_shift_out_87[19] = PD1_a_o_2 & UD1_shift_out_87_d[19] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[19] # !PD1_a_o_0 & VD1_b_o_iv_21;
|
| 12068 |
|
|
|
| 12069 |
|
|
|
| 12070 |
|
|
--UD1_shift_out_89_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[19]
|
| 12071 |
|
|
--operation mode is normal
|
| 12072 |
|
|
|
| 12073 |
|
|
UD1_shift_out_89_a[19] = PD1_a_o_2 & !UD1_shift_out_85_d[19] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[19] # !PD1_a_o_1 & !VD1_b_o_iv_18;
|
| 12074 |
|
|
|
| 12075 |
|
|
|
| 12076 |
|
|
--MD1_c_0_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[19]
|
| 12077 |
|
|
--operation mode is normal
|
| 12078 |
|
|
|
| 12079 |
|
|
MD1_c_0_a[19] = VD1_un24_res & !VD1_hilo_51 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_19;
|
| 12080 |
|
|
|
| 12081 |
|
|
|
| 12082 |
|
|
--TD1_m51 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m51
|
| 12083 |
|
|
--operation mode is normal
|
| 12084 |
|
|
|
| 12085 |
|
|
TD1_m51 = PD1_a_o_19 & TD1_m51_a # !PD1_a_o_19 & TD1_m51_a & !TD1_m4 # !TD1_m51_a & TD1_m7;
|
| 12086 |
|
|
|
| 12087 |
|
|
|
| 12088 |
|
|
--TD1_m48 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m48
|
| 12089 |
|
|
--operation mode is normal
|
| 12090 |
|
|
|
| 12091 |
|
|
TD1_m48 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add19;
|
| 12092 |
|
|
|
| 12093 |
|
|
|
| 12094 |
|
|
--UD1_shift_out_92_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_a[19]
|
| 12095 |
|
|
--operation mode is normal
|
| 12096 |
|
|
|
| 12097 |
|
|
UD1_shift_out_92_a[19] = PD1_a_o_2 & !PD1_a_o_1 & !PD1_a_o_0 # !UD1_shift_out587;
|
| 12098 |
|
|
|
| 12099 |
|
|
|
| 12100 |
|
|
--UD1_shift_out_92_d[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[19]
|
| 12101 |
|
|
--operation mode is normal
|
| 12102 |
|
|
|
| 12103 |
|
|
UD1_shift_out_92_d[19] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[19] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[19];
|
| 12104 |
|
|
|
| 12105 |
|
|
|
| 12106 |
|
|
--UD1_shift_out_87[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[18]
|
| 12107 |
|
|
--operation mode is normal
|
| 12108 |
|
|
|
| 12109 |
|
|
UD1_shift_out_87[18] = PD1_a_o_2 & UD1_shift_out_87_d[18] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[18] # !PD1_a_o_0 & VD1_b_o_iv_20;
|
| 12110 |
|
|
|
| 12111 |
|
|
|
| 12112 |
|
|
--UD1_shift_out_89_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[18]
|
| 12113 |
|
|
--operation mode is normal
|
| 12114 |
|
|
|
| 12115 |
|
|
UD1_shift_out_89_a[18] = PD1_a_o_2 & !UD1_shift_out_85_d[18] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[18] # !PD1_a_o_1 & !VD1_b_o_iv_17;
|
| 12116 |
|
|
|
| 12117 |
|
|
|
| 12118 |
|
|
--UD1_shift_out_92_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_a[18]
|
| 12119 |
|
|
--operation mode is normal
|
| 12120 |
|
|
|
| 12121 |
|
|
UD1_shift_out_92_a[18] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_83[18] # !UD1_shift_out_sn_b9_0 & !VD1_b_o_iv_31;
|
| 12122 |
|
|
|
| 12123 |
|
|
|
| 12124 |
|
|
--UD1_shift_out_92_d[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[18]
|
| 12125 |
|
|
--operation mode is normal
|
| 12126 |
|
|
|
| 12127 |
|
|
UD1_shift_out_92_d[18] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[18] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[18];
|
| 12128 |
|
|
|
| 12129 |
|
|
|
| 12130 |
|
|
--MD1_c_0_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[18]
|
| 12131 |
|
|
--operation mode is normal
|
| 12132 |
|
|
|
| 12133 |
|
|
MD1_c_0_a[18] = VD1_un24_res & !VD1_hilo_50 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_18;
|
| 12134 |
|
|
|
| 12135 |
|
|
|
| 12136 |
|
|
--TD1_m46 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m46
|
| 12137 |
|
|
--operation mode is normal
|
| 12138 |
|
|
|
| 12139 |
|
|
TD1_m46 = PD1_a_o_18 & TD1_m46_a # !PD1_a_o_18 & TD1_m46_a & !TD1_m4 # !TD1_m46_a & TD1_m7;
|
| 12140 |
|
|
|
| 12141 |
|
|
|
| 12142 |
|
|
--TD1_m43 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m43
|
| 12143 |
|
|
--operation mode is normal
|
| 12144 |
|
|
|
| 12145 |
|
|
TD1_m43 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add18;
|
| 12146 |
|
|
|
| 12147 |
|
|
|
| 12148 |
|
|
--UD1_shift_out_89_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[26]
|
| 12149 |
|
|
--operation mode is normal
|
| 12150 |
|
|
|
| 12151 |
|
|
UD1_shift_out_89_a[26] = PD1_a_o_2 & !UD1_shift_out_87_d[26] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_d[26] # !PD1_a_o_0 & !VD1_b_o_iv_28;
|
| 12152 |
|
|
|
| 12153 |
|
|
|
| 12154 |
|
|
--UD1_shift_out_85[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[26]
|
| 12155 |
|
|
--operation mode is normal
|
| 12156 |
|
|
|
| 12157 |
|
|
UD1_shift_out_85[26] = PD1_a_o_2 & UD1_shift_out_85_a[26] & UD1_shift_out_68[24] # !UD1_shift_out_85_a[26] & UD1_shift_out_68[22] # !PD1_a_o_2 & !UD1_shift_out_85_a[26];
|
| 12158 |
|
|
|
| 12159 |
|
|
|
| 12160 |
|
|
--UD1_shift_out_92_d_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_18
|
| 12161 |
|
|
--operation mode is normal
|
| 12162 |
|
|
|
| 12163 |
|
|
UD1_shift_out_92_d_18 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[26] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[26];
|
| 12164 |
|
|
|
| 12165 |
|
|
|
| 12166 |
|
|
--MD1_c_0_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[26]
|
| 12167 |
|
|
--operation mode is normal
|
| 12168 |
|
|
|
| 12169 |
|
|
MD1_c_0_a[26] = VD1_un24_res & !VD1_hilo_58 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_26;
|
| 12170 |
|
|
|
| 12171 |
|
|
|
| 12172 |
|
|
--TD1_m81 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m81
|
| 12173 |
|
|
--operation mode is normal
|
| 12174 |
|
|
|
| 12175 |
|
|
TD1_m81 = PD1_a_o_26 & TD1_m81_a # !PD1_a_o_26 & TD1_m81_a & !TD1_m4 # !TD1_m81_a & TD1_m7;
|
| 12176 |
|
|
|
| 12177 |
|
|
|
| 12178 |
|
|
--TD1_m78 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m78
|
| 12179 |
|
|
--operation mode is normal
|
| 12180 |
|
|
|
| 12181 |
|
|
TD1_m78 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add26;
|
| 12182 |
|
|
|
| 12183 |
|
|
|
| 12184 |
|
|
--UD1_shift_out_85[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[27]
|
| 12185 |
|
|
--operation mode is normal
|
| 12186 |
|
|
|
| 12187 |
|
|
UD1_shift_out_85[27] = PD1_a_o_2 & UD1_shift_out_85_a[27] & UD1_shift_out_68[25] # !UD1_shift_out_85_a[27] & UD1_shift_out_68[23] # !PD1_a_o_2 & !UD1_shift_out_85_a[27];
|
| 12188 |
|
|
|
| 12189 |
|
|
|
| 12190 |
|
|
--UD1_shift_out_89_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[27]
|
| 12191 |
|
|
--operation mode is normal
|
| 12192 |
|
|
|
| 12193 |
|
|
UD1_shift_out_89_a[27] = PD1_a_o_2 & !UD1_shift_out_87_d[27] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_d[27] # !PD1_a_o_0 & !VD1_b_o_iv_29;
|
| 12194 |
|
|
|
| 12195 |
|
|
|
| 12196 |
|
|
--UD1_shift_out_92_d_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_19
|
| 12197 |
|
|
--operation mode is normal
|
| 12198 |
|
|
|
| 12199 |
|
|
UD1_shift_out_92_d_19 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[27] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[27];
|
| 12200 |
|
|
|
| 12201 |
|
|
|
| 12202 |
|
|
--MD1_c_0_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[27]
|
| 12203 |
|
|
--operation mode is normal
|
| 12204 |
|
|
|
| 12205 |
|
|
MD1_c_0_a[27] = VD1_un24_res & !VD1_hilo_59 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_27;
|
| 12206 |
|
|
|
| 12207 |
|
|
|
| 12208 |
|
|
--TD1_m86 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m86
|
| 12209 |
|
|
--operation mode is normal
|
| 12210 |
|
|
|
| 12211 |
|
|
TD1_m86 = PD1_a_o_27 & TD1_m86_a # !PD1_a_o_27 & TD1_m86_a & !TD1_m4 # !TD1_m86_a & TD1_m7;
|
| 12212 |
|
|
|
| 12213 |
|
|
|
| 12214 |
|
|
--TD1_m83 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m83
|
| 12215 |
|
|
--operation mode is normal
|
| 12216 |
|
|
|
| 12217 |
|
|
TD1_m83 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add27;
|
| 12218 |
|
|
|
| 12219 |
|
|
|
| 12220 |
|
|
--UD1_shift_out_87[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[28]
|
| 12221 |
|
|
--operation mode is normal
|
| 12222 |
|
|
|
| 12223 |
|
|
UD1_shift_out_87[28] = PD1_a_o_1 & PD1_a_o_0 & !UD1_shift_out_87_a[28] # !PD1_a_o_0 & UD1_shift_out_87_d[28] # !PD1_a_o_1 & UD1_shift_out_87_d[28];
|
| 12224 |
|
|
|
| 12225 |
|
|
|
| 12226 |
|
|
--UD1_shift_out_85[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[28]
|
| 12227 |
|
|
--operation mode is normal
|
| 12228 |
|
|
|
| 12229 |
|
|
UD1_shift_out_85[28] = PD1_a_o_2 & UD1_shift_out_85_a[28] & UD1_shift_out_68[26] # !UD1_shift_out_85_a[28] & UD1_shift_out_68[24] # !PD1_a_o_2 & !UD1_shift_out_85_a[28];
|
| 12230 |
|
|
|
| 12231 |
|
|
|
| 12232 |
|
|
--TD1_alu_out_0_a2_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_22
|
| 12233 |
|
|
--operation mode is normal
|
| 12234 |
|
|
|
| 12235 |
|
|
TD1_alu_out_0_a2_22 = TD1_alu_out_0_a2_a[28] & !PD1_a_o_28 & RC1_alu_func_o_0 $ VD1_b_o_iv_28;
|
| 12236 |
|
|
|
| 12237 |
|
|
|
| 12238 |
|
|
--MD1_c_2[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2[28]
|
| 12239 |
|
|
--operation mode is normal
|
| 12240 |
|
|
|
| 12241 |
|
|
MD1_c_2[28] = MD1_c_0_Z[28] # TD1_alu_out_0_a2_3_0 # MD1_c_2_a[28] & PD1_a_o_28;
|
| 12242 |
|
|
|
| 12243 |
|
|
|
| 12244 |
|
|
--TD1_un1_a_add28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add28
|
| 12245 |
|
|
--operation mode is arithmetic
|
| 12246 |
|
|
|
| 12247 |
|
|
TD1_un1_a_add28_carry_eqn = TD1_un1_a_carry_27;
|
| 12248 |
|
|
TD1_un1_a_add28 = PD1_a_o_28 $ TD1_un1_b_1_combout[28] $ !TD1_un1_a_add28_carry_eqn;
|
| 12249 |
|
|
|
| 12250 |
|
|
--TD1_un1_a_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_28
|
| 12251 |
|
|
--operation mode is arithmetic
|
| 12252 |
|
|
|
| 12253 |
|
|
TD1_un1_a_carry_28 = CARRY(PD1_a_o_28 & TD1_un1_b_1_combout[28] # !TD1_un1_a_carry_27 # !PD1_a_o_28 & TD1_un1_b_1_combout[28] & !TD1_un1_a_carry_27);
|
| 12254 |
|
|
|
| 12255 |
|
|
|
| 12256 |
|
|
--UD1_shift_out_92_d_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_20
|
| 12257 |
|
|
--operation mode is normal
|
| 12258 |
|
|
|
| 12259 |
|
|
UD1_shift_out_92_d_20 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[28] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[28];
|
| 12260 |
|
|
|
| 12261 |
|
|
|
| 12262 |
|
|
--UD1_shift_out_87[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[29]
|
| 12263 |
|
|
--operation mode is normal
|
| 12264 |
|
|
|
| 12265 |
|
|
UD1_shift_out_87[29] = PD1_a_o_2 & !UD1_shift_out_87_a[29] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_a[29] # !PD1_a_o_0 & VD1_b_o_iv_31;
|
| 12266 |
|
|
|
| 12267 |
|
|
|
| 12268 |
|
|
--UD1_shift_out_85[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[29]
|
| 12269 |
|
|
--operation mode is normal
|
| 12270 |
|
|
|
| 12271 |
|
|
UD1_shift_out_85[29] = PD1_a_o_2 & UD1_shift_out_85_c[29] & UD1_shift_out_68[25] # !UD1_shift_out_85_c[29] & UD1_shift_out_68[27] # !PD1_a_o_2 & UD1_shift_out_85_c[29];
|
| 12272 |
|
|
|
| 12273 |
|
|
|
| 12274 |
|
|
--UD1_shift_out_92_d_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_21
|
| 12275 |
|
|
--operation mode is normal
|
| 12276 |
|
|
|
| 12277 |
|
|
UD1_shift_out_92_d_21 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[29] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[29];
|
| 12278 |
|
|
|
| 12279 |
|
|
|
| 12280 |
|
|
--MD1_c_0_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[29]
|
| 12281 |
|
|
--operation mode is normal
|
| 12282 |
|
|
|
| 12283 |
|
|
MD1_c_0_a[29] = VD1_un24_res & !VD1_hilo_61 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_29;
|
| 12284 |
|
|
|
| 12285 |
|
|
|
| 12286 |
|
|
--TD1_m91 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m91
|
| 12287 |
|
|
--operation mode is normal
|
| 12288 |
|
|
|
| 12289 |
|
|
TD1_m91 = PD1_a_o_29 & TD1_m91_a # !PD1_a_o_29 & TD1_m91_a & !TD1_m4 # !TD1_m91_a & TD1_m7;
|
| 12290 |
|
|
|
| 12291 |
|
|
|
| 12292 |
|
|
--TD1_m88 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m88
|
| 12293 |
|
|
--operation mode is normal
|
| 12294 |
|
|
|
| 12295 |
|
|
TD1_m88 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add29;
|
| 12296 |
|
|
|
| 12297 |
|
|
|
| 12298 |
|
|
--UD1_shift_out_87_d[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[13]
|
| 12299 |
|
|
--operation mode is normal
|
| 12300 |
|
|
|
| 12301 |
|
|
UD1_shift_out_87_d[13] = PD1_a_o_0 & UD1_shift_out_80[13] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[13];
|
| 12302 |
|
|
|
| 12303 |
|
|
|
| 12304 |
|
|
--UD1_shift_out_85_d[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[13]
|
| 12305 |
|
|
--operation mode is normal
|
| 12306 |
|
|
|
| 12307 |
|
|
UD1_shift_out_85_d[13] = PD1_a_o_2 & UD1_shift_out_48[29] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[13];
|
| 12308 |
|
|
|
| 12309 |
|
|
|
| 12310 |
|
|
--UD1_shift_out_86_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[13]
|
| 12311 |
|
|
--operation mode is normal
|
| 12312 |
|
|
|
| 12313 |
|
|
UD1_shift_out_86_a[13] = UD1_shift_out_sn_b9_0 & UD1_shift_out587 & !PD1_a_o_2 # !UD1_shift_out_sn_b9_0 & !UD1_shift_out_74[13];
|
| 12314 |
|
|
|
| 12315 |
|
|
|
| 12316 |
|
|
--UD1_shift_out_63[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[21]
|
| 12317 |
|
|
--operation mode is normal
|
| 12318 |
|
|
|
| 12319 |
|
|
UD1_shift_out_63[21] = PD1_a_o_2 & !PD1_a_o_1 & !UD1_shift_out_85_d_a[5] # !PD1_a_o_2 & UD1_shift_out_45[29];
|
| 12320 |
|
|
|
| 12321 |
|
|
|
| 12322 |
|
|
--UD1_shift_out_92_d_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[13]
|
| 12323 |
|
|
--operation mode is normal
|
| 12324 |
|
|
|
| 12325 |
|
|
UD1_shift_out_92_d_a[13] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_13 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[13] # !UD1_shift_out_sn_m17_0;
|
| 12326 |
|
|
|
| 12327 |
|
|
|
| 12328 |
|
|
--VD1_hilo_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_13
|
| 12329 |
|
|
--operation mode is normal
|
| 12330 |
|
|
|
| 12331 |
|
|
VD1_hilo_13_lut_out = VD1_hilo_37_iv_0_0[13] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_13 # !VD1_hilo_37_iv_0_a[13];
|
| 12332 |
|
|
VD1_hilo_13 = DFFEAS(VD1_hilo_13_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 12333 |
|
|
|
| 12334 |
|
|
|
| 12335 |
|
|
--VD1_hilo_45 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_45
|
| 12336 |
|
|
--operation mode is normal
|
| 12337 |
|
|
|
| 12338 |
|
|
VD1_hilo_45_lut_out = !VD1_hilo_37_iv_2[45] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[45] # !VD1_hilo25;
|
| 12339 |
|
|
VD1_hilo_45 = DFFEAS(VD1_hilo_45_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 12340 |
|
|
|
| 12341 |
|
|
|
| 12342 |
|
|
--PD1_a_o_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_13
|
| 12343 |
|
|
--operation mode is normal
|
| 12344 |
|
|
|
| 12345 |
|
|
PD1_a_o_13 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[13] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[13];
|
| 12346 |
|
|
|
| 12347 |
|
|
|
| 12348 |
|
|
--TD1_m127_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m127_a
|
| 12349 |
|
|
--operation mode is normal
|
| 12350 |
|
|
|
| 12351 |
|
|
TD1_m127_a = VD1_b_o_iv_13 & !TD1_m9 & PD1_a_o_13 # !VD1_b_o_iv_13 & !TD1_m5 # !PD1_a_o_13;
|
| 12352 |
|
|
|
| 12353 |
|
|
|
| 12354 |
|
|
--TD1_un1_a_add13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add13
|
| 12355 |
|
|
--operation mode is arithmetic
|
| 12356 |
|
|
|
| 12357 |
|
|
TD1_un1_a_add13_carry_eqn = TD1_un1_a_carry_12;
|
| 12358 |
|
|
TD1_un1_a_add13 = PD1_a_o_13 $ TD1_un1_b_1_combout[13] $ TD1_un1_a_add13_carry_eqn;
|
| 12359 |
|
|
|
| 12360 |
|
|
--TD1_un1_a_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_13
|
| 12361 |
|
|
--operation mode is arithmetic
|
| 12362 |
|
|
|
| 12363 |
|
|
TD1_un1_a_carry_13 = CARRY(PD1_a_o_13 & !TD1_un1_b_1_combout[13] & !TD1_un1_a_carry_12 # !PD1_a_o_13 & !TD1_un1_a_carry_12 # !TD1_un1_b_1_combout[13]);
|
| 12364 |
|
|
|
| 12365 |
|
|
|
| 12366 |
|
|
--VD1_hilo_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_29
|
| 12367 |
|
|
--operation mode is normal
|
| 12368 |
|
|
|
| 12369 |
|
|
VD1_hilo_29_lut_out = VD1_hilo_37_iv_0_0[29] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_29 # !VD1_hilo_37_iv_0_a[29];
|
| 12370 |
|
|
VD1_hilo_29 = DFFEAS(VD1_hilo_29_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 12371 |
|
|
|
| 12372 |
|
|
|
| 12373 |
|
|
--VD1_un134_hilo_combout[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[30]
|
| 12374 |
|
|
--operation mode is normal
|
| 12375 |
|
|
|
| 12376 |
|
|
VD1_un134_hilo_combout[30]_carry_eqn = VD1_un134_hilo_cout[28];
|
| 12377 |
|
|
VD1_un134_hilo_combout[30] = VD1_hilo_30 $ (VD1_un134_hilo_combout[30]_carry_eqn);
|
| 12378 |
|
|
|
| 12379 |
|
|
|
| 12380 |
|
|
--PD1_a_o_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[30]
|
| 12381 |
|
|
--operation mode is normal
|
| 12382 |
|
|
|
| 12383 |
|
|
PD1_a_o_a[30] = SC1_muxa_ctl_o_1 & !FB1_r32_o_30 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_30;
|
| 12384 |
|
|
|
| 12385 |
|
|
|
| 12386 |
|
|
--PD1_a_o_3_Z[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[30]
|
| 12387 |
|
|
--operation mode is normal
|
| 12388 |
|
|
|
| 12389 |
|
|
PD1_a_o_3_Z[30] = PD1_a_o_3_s[0] & SD1_r32_o_30 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[30];
|
| 12390 |
|
|
|
| 12391 |
|
|
|
| 12392 |
|
|
--VD1_hilo_37_iv_0_a3_4[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_4[62]
|
| 12393 |
|
|
--operation mode is normal
|
| 12394 |
|
|
|
| 12395 |
|
|
VD1_hilo_37_iv_0_a3_4[62] = !VD1_hilo_33_1[64] & VD1_hilo_3_sqmuxa;
|
| 12396 |
|
|
|
| 12397 |
|
|
|
| 12398 |
|
|
--VD1_hilo_37_iv_0_a[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[62]
|
| 12399 |
|
|
--operation mode is normal
|
| 12400 |
|
|
|
| 12401 |
|
|
VD1_hilo_37_iv_0_a[62] = !VD1_hilo_37_iv_0_2[62] & !VD1_hilo_37_iv_0_o5[62] & VD1_hilo_24_add30 # !VD1_hilo_2_sqmuxa;
|
| 12402 |
|
|
|
| 12403 |
|
|
|
| 12404 |
|
|
--VD1_hilo_37_iv_0_o5_0[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5_0[62]
|
| 12405 |
|
|
--operation mode is normal
|
| 12406 |
|
|
|
| 12407 |
|
|
VD1_hilo_37_iv_0_o5_0[62] = VD1_hilo_37_iv_0_o5_0_a[62] # VD1_hilo_37_iv_0_a3[57] # !VD1_un59_hilo_add31 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 12408 |
|
|
|
| 12409 |
|
|
|
| 12410 |
|
|
--UD1_shift_out_92_d[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[30]
|
| 12411 |
|
|
--operation mode is normal
|
| 12412 |
|
|
|
| 12413 |
|
|
UD1_shift_out_92_d[30] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[30] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[30];
|
| 12414 |
|
|
|
| 12415 |
|
|
|
| 12416 |
|
|
--UD1_shift_out_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[30]
|
| 12417 |
|
|
--operation mode is normal
|
| 12418 |
|
|
|
| 12419 |
|
|
UD1_shift_out_a[30] = UD1_shift_out_sn_m31_i & !UD1_shift_out586 & !UD1_shift_out_sn_m25_0 # !UD1_shift_out_sn_m31_i & !UD1_shift_out_89[30];
|
| 12420 |
|
|
|
| 12421 |
|
|
|
| 12422 |
|
|
--TD1_m96_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m96_a
|
| 12423 |
|
|
--operation mode is normal
|
| 12424 |
|
|
|
| 12425 |
|
|
TD1_m96_a = VD1_b_o_iv_30 & !TD1_m9 & PD1_a_o_30 # !VD1_b_o_iv_30 & !TD1_m5 # !PD1_a_o_30;
|
| 12426 |
|
|
|
| 12427 |
|
|
|
| 12428 |
|
|
--TD1_un1_b_1_combout[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[30]
|
| 12429 |
|
|
--operation mode is normal
|
| 12430 |
|
|
|
| 12431 |
|
|
TD1_un1_b_1_combout[30] = TD1_sum13_0_a2 $ !VD1_b_o_iv_30;
|
| 12432 |
|
|
|
| 12433 |
|
|
|
| 12434 |
|
|
--TD1_un1_a_add29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add29
|
| 12435 |
|
|
--operation mode is arithmetic
|
| 12436 |
|
|
|
| 12437 |
|
|
TD1_un1_a_add29_carry_eqn = TD1_un1_a_carry_28;
|
| 12438 |
|
|
TD1_un1_a_add29 = PD1_a_o_29 $ TD1_un1_b_1_combout[29] $ TD1_un1_a_add29_carry_eqn;
|
| 12439 |
|
|
|
| 12440 |
|
|
--TD1_un1_a_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_29
|
| 12441 |
|
|
--operation mode is arithmetic
|
| 12442 |
|
|
|
| 12443 |
|
|
TD1_un1_a_carry_29 = CARRY(PD1_a_o_29 & !TD1_un1_b_1_combout[29] & !TD1_un1_a_carry_28 # !PD1_a_o_29 & !TD1_un1_a_carry_28 # !TD1_un1_b_1_combout[29]);
|
| 12444 |
|
|
|
| 12445 |
|
|
|
| 12446 |
|
|
--UD1_shift_out_87[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[12]
|
| 12447 |
|
|
--operation mode is normal
|
| 12448 |
|
|
|
| 12449 |
|
|
UD1_shift_out_87[12] = PD1_a_o_2 & UD1_shift_out_87_d[12] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[12] # !PD1_a_o_0 & VD1_b_o_iv_14;
|
| 12450 |
|
|
|
| 12451 |
|
|
|
| 12452 |
|
|
--UD1_shift_out_89_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[12]
|
| 12453 |
|
|
--operation mode is normal
|
| 12454 |
|
|
|
| 12455 |
|
|
UD1_shift_out_89_a[12] = PD1_a_o_2 & !UD1_shift_out_85_d[12] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[12] # !PD1_a_o_1 & !VD1_b_o_iv_11;
|
| 12456 |
|
|
|
| 12457 |
|
|
|
| 12458 |
|
|
--UD1_shift_out_86_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_12
|
| 12459 |
|
|
--operation mode is normal
|
| 12460 |
|
|
|
| 12461 |
|
|
UD1_shift_out_86_12 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[12] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[12];
|
| 12462 |
|
|
|
| 12463 |
|
|
|
| 12464 |
|
|
--UD1_shift_out_92_d_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_4
|
| 12465 |
|
|
--operation mode is normal
|
| 12466 |
|
|
|
| 12467 |
|
|
UD1_shift_out_92_d_4 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[12] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_63[20];
|
| 12468 |
|
|
|
| 12469 |
|
|
|
| 12470 |
|
|
--MD1_c_0_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[12]
|
| 12471 |
|
|
--operation mode is normal
|
| 12472 |
|
|
|
| 12473 |
|
|
MD1_c_0_a[12] = VD1_un24_res & !VD1_hilo_44 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_12;
|
| 12474 |
|
|
|
| 12475 |
|
|
|
| 12476 |
|
|
--TD1_m122 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m122
|
| 12477 |
|
|
--operation mode is normal
|
| 12478 |
|
|
|
| 12479 |
|
|
TD1_m122 = PD1_a_o_12 & TD1_m122_a # !PD1_a_o_12 & TD1_m122_a & !TD1_m4 # !TD1_m122_a & TD1_m7;
|
| 12480 |
|
|
|
| 12481 |
|
|
|
| 12482 |
|
|
--TD1_m119 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m119
|
| 12483 |
|
|
--operation mode is normal
|
| 12484 |
|
|
|
| 12485 |
|
|
TD1_m119 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add12;
|
| 12486 |
|
|
|
| 12487 |
|
|
|
| 12488 |
|
|
--UD1_shift_out_89_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[24]
|
| 12489 |
|
|
--operation mode is normal
|
| 12490 |
|
|
|
| 12491 |
|
|
UD1_shift_out_89_a[24] = PD1_a_o_2 & !UD1_shift_out_87_d[24] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_d[24] # !PD1_a_o_0 & !VD1_b_o_iv_26;
|
| 12492 |
|
|
|
| 12493 |
|
|
|
| 12494 |
|
|
--UD1_shift_out_85[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[24]
|
| 12495 |
|
|
--operation mode is normal
|
| 12496 |
|
|
|
| 12497 |
|
|
UD1_shift_out_85[24] = PD1_a_o_2 & UD1_shift_out_85_a[24] & UD1_shift_out_68[22] # !UD1_shift_out_85_a[24] & UD1_shift_out_68[20] # !PD1_a_o_2 & !UD1_shift_out_85_a[24];
|
| 12498 |
|
|
|
| 12499 |
|
|
|
| 12500 |
|
|
--UD1_shift_out_92_d_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_16
|
| 12501 |
|
|
--operation mode is normal
|
| 12502 |
|
|
|
| 12503 |
|
|
UD1_shift_out_92_d_16 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[24] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[24];
|
| 12504 |
|
|
|
| 12505 |
|
|
|
| 12506 |
|
|
--MD1_c_0_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[24]
|
| 12507 |
|
|
--operation mode is normal
|
| 12508 |
|
|
|
| 12509 |
|
|
MD1_c_0_a[24] = VD1_un24_res & !VD1_hilo_56 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_24;
|
| 12510 |
|
|
|
| 12511 |
|
|
|
| 12512 |
|
|
--TD1_m71 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m71
|
| 12513 |
|
|
--operation mode is normal
|
| 12514 |
|
|
|
| 12515 |
|
|
TD1_m71 = PD1_a_o_24 & TD1_m71_a # !PD1_a_o_24 & TD1_m71_a & !TD1_m4 # !TD1_m71_a & TD1_m7;
|
| 12516 |
|
|
|
| 12517 |
|
|
|
| 12518 |
|
|
--TD1_m68 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m68
|
| 12519 |
|
|
--operation mode is normal
|
| 12520 |
|
|
|
| 12521 |
|
|
TD1_m68 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add24;
|
| 12522 |
|
|
|
| 12523 |
|
|
|
| 12524 |
|
|
--UD1_shift_out_89_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[25]
|
| 12525 |
|
|
--operation mode is normal
|
| 12526 |
|
|
|
| 12527 |
|
|
UD1_shift_out_89_a[25] = PD1_a_o_2 & !UD1_shift_out_87_d[25] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_d[25] # !PD1_a_o_0 & !VD1_b_o_iv_27;
|
| 12528 |
|
|
|
| 12529 |
|
|
|
| 12530 |
|
|
--UD1_shift_out_85[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[25]
|
| 12531 |
|
|
--operation mode is normal
|
| 12532 |
|
|
|
| 12533 |
|
|
UD1_shift_out_85[25] = PD1_a_o_2 & UD1_shift_out_85_a[25] & UD1_shift_out_68[23] # !UD1_shift_out_85_a[25] & UD1_shift_out_68[21] # !PD1_a_o_2 & !UD1_shift_out_85_a[25];
|
| 12534 |
|
|
|
| 12535 |
|
|
|
| 12536 |
|
|
--UD1_shift_out_92_d_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_17
|
| 12537 |
|
|
--operation mode is normal
|
| 12538 |
|
|
|
| 12539 |
|
|
UD1_shift_out_92_d_17 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[25] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[25];
|
| 12540 |
|
|
|
| 12541 |
|
|
|
| 12542 |
|
|
--MD1_c_0_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[25]
|
| 12543 |
|
|
--operation mode is normal
|
| 12544 |
|
|
|
| 12545 |
|
|
MD1_c_0_a[25] = VD1_un24_res & !VD1_hilo_57 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_25;
|
| 12546 |
|
|
|
| 12547 |
|
|
|
| 12548 |
|
|
--TD1_m76 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m76
|
| 12549 |
|
|
--operation mode is normal
|
| 12550 |
|
|
|
| 12551 |
|
|
TD1_m76 = PD1_a_o_25 & TD1_m76_a # !PD1_a_o_25 & TD1_m76_a & !TD1_m4 # !TD1_m76_a & TD1_m7;
|
| 12552 |
|
|
|
| 12553 |
|
|
|
| 12554 |
|
|
--TD1_m73 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m73
|
| 12555 |
|
|
--operation mode is normal
|
| 12556 |
|
|
|
| 12557 |
|
|
TD1_m73 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add25;
|
| 12558 |
|
|
|
| 12559 |
|
|
|
| 12560 |
|
|
--UD1_shift_out_87[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[22]
|
| 12561 |
|
|
--operation mode is normal
|
| 12562 |
|
|
|
| 12563 |
|
|
UD1_shift_out_87[22] = PD1_a_o_2 & UD1_shift_out_87_d[22] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[22] # !PD1_a_o_0 & VD1_b_o_iv_24;
|
| 12564 |
|
|
|
| 12565 |
|
|
|
| 12566 |
|
|
--UD1_shift_out_85[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[22]
|
| 12567 |
|
|
--operation mode is normal
|
| 12568 |
|
|
|
| 12569 |
|
|
UD1_shift_out_85[22] = PD1_a_o_2 & UD1_shift_out_85_d[22] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[22] # !PD1_a_o_1 & VD1_b_o_iv_21;
|
| 12570 |
|
|
|
| 12571 |
|
|
|
| 12572 |
|
|
--UD1_shift_out_92_d_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_14
|
| 12573 |
|
|
--operation mode is normal
|
| 12574 |
|
|
|
| 12575 |
|
|
UD1_shift_out_92_d_14 = UD1_shift_out_sn_m25_0 & UD1_shift_out_88[22] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d_a[22];
|
| 12576 |
|
|
|
| 12577 |
|
|
|
| 12578 |
|
|
--MD1_c_0_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[22]
|
| 12579 |
|
|
--operation mode is normal
|
| 12580 |
|
|
|
| 12581 |
|
|
MD1_c_0_a[22] = VD1_un24_res & !VD1_hilo_54 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_22;
|
| 12582 |
|
|
|
| 12583 |
|
|
|
| 12584 |
|
|
--TD1_m61 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m61
|
| 12585 |
|
|
--operation mode is normal
|
| 12586 |
|
|
|
| 12587 |
|
|
TD1_m61 = PD1_a_o_22 & TD1_m61_a # !PD1_a_o_22 & TD1_m61_a & !TD1_m4 # !TD1_m61_a & TD1_m7;
|
| 12588 |
|
|
|
| 12589 |
|
|
|
| 12590 |
|
|
--TD1_m58 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m58
|
| 12591 |
|
|
--operation mode is normal
|
| 12592 |
|
|
|
| 12593 |
|
|
TD1_m58 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add22;
|
| 12594 |
|
|
|
| 12595 |
|
|
|
| 12596 |
|
|
--UD1_shift_out_89_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[23]
|
| 12597 |
|
|
--operation mode is normal
|
| 12598 |
|
|
|
| 12599 |
|
|
UD1_shift_out_89_a[23] = PD1_a_o_2 & !UD1_shift_out_87_d[23] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_d[23] # !PD1_a_o_0 & !VD1_b_o_iv_25;
|
| 12600 |
|
|
|
| 12601 |
|
|
|
| 12602 |
|
|
--UD1_shift_out_85[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[23]
|
| 12603 |
|
|
--operation mode is normal
|
| 12604 |
|
|
|
| 12605 |
|
|
UD1_shift_out_85[23] = PD1_a_o_2 & !UD1_shift_out_85_a[23] # !PD1_a_o_2 & UD1_shift_out_85_a[23] & VD1_b_o_iv_22 # !UD1_shift_out_85_a[23] & UD1_shift_out_68[23];
|
| 12606 |
|
|
|
| 12607 |
|
|
|
| 12608 |
|
|
--UD1_shift_out_92_d_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_15
|
| 12609 |
|
|
--operation mode is normal
|
| 12610 |
|
|
|
| 12611 |
|
|
UD1_shift_out_92_d_15 = UD1_shift_out_sn_m25_0 & UD1_shift_out_88[23] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d_a[23];
|
| 12612 |
|
|
|
| 12613 |
|
|
|
| 12614 |
|
|
--MD1_c_0_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[23]
|
| 12615 |
|
|
--operation mode is normal
|
| 12616 |
|
|
|
| 12617 |
|
|
MD1_c_0_a[23] = VD1_un24_res & !VD1_hilo_55 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_23;
|
| 12618 |
|
|
|
| 12619 |
|
|
|
| 12620 |
|
|
--TD1_m66 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m66
|
| 12621 |
|
|
--operation mode is normal
|
| 12622 |
|
|
|
| 12623 |
|
|
TD1_m66 = PD1_a_o_23 & TD1_m66_a # !PD1_a_o_23 & TD1_m66_a & !TD1_m4 # !TD1_m66_a & TD1_m7;
|
| 12624 |
|
|
|
| 12625 |
|
|
|
| 12626 |
|
|
--TD1_m63 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m63
|
| 12627 |
|
|
--operation mode is normal
|
| 12628 |
|
|
|
| 12629 |
|
|
TD1_m63 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add23;
|
| 12630 |
|
|
|
| 12631 |
|
|
|
| 12632 |
|
|
--CB1_dout_2_22 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_22
|
| 12633 |
|
|
--operation mode is normal
|
| 12634 |
|
|
|
| 12635 |
|
|
CB1_dout_2_22 = ND1_dout7 & FD1_wb_o_22 # !ND1_dout7 & !ND1_dout_2_a_22;
|
| 12636 |
|
|
|
| 12637 |
|
|
--CB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_22
|
| 12638 |
|
|
--operation mode is normal
|
| 12639 |
|
|
|
| 12640 |
|
|
CB1_r32_o_22 = DFFEAS(CB1_dout_2_22, E1__clk0, VCC, , , , , , );
|
| 12641 |
|
|
|
| 12642 |
|
|
|
| 12643 |
|
|
--UB1_dout_2_i_o2_0_a[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_o2_0_a[3]
|
| 12644 |
|
|
--operation mode is normal
|
| 12645 |
|
|
|
| 12646 |
|
|
UB1_dout_2_i_o2_0_a[3] = RB1_ctl_o_2 & !RB1_ctl_o_1 # !RB1_ctl_o_2 & RB1_ctl_o_1 & !RB1_ctl_o_3 # !RB1_byte_addr_o_1;
|
| 12647 |
|
|
|
| 12648 |
|
|
|
| 12649 |
|
|
--TB1_dout_1_x_6 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_6
|
| 12650 |
|
|
--operation mode is normal
|
| 12651 |
|
|
|
| 12652 |
|
|
TB1_dout_1_x_6 = TB1_dout21 & CB1_dout_2_6 # !TB1_dout21 & CB1_dout_2_14;
|
| 12653 |
|
|
|
| 12654 |
|
|
|
| 12655 |
|
|
--TB1_dout_1_2_6 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_6
|
| 12656 |
|
|
--operation mode is normal
|
| 12657 |
|
|
|
| 12658 |
|
|
TB1_dout_1_2_6 = TB1_dout22 & !TB1_dout_1_2_a_x[30] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_6 # !TB1_dout21 & !TB1_dout_1_2_a_x[30];
|
| 12659 |
|
|
|
| 12660 |
|
|
|
| 12661 |
|
|
--UB1_dout_2_i_i_o3[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_o3[7]
|
| 12662 |
|
|
--operation mode is normal
|
| 12663 |
|
|
|
| 12664 |
|
|
UB1_dout_2_i_i_o3[7] = RB1_ctl_o_1 & !RB1_ctl_o_3 & !RB1_ctl_o_2 # !RB1_ctl_o_1 & RB1_ctl_o_2;
|
| 12665 |
|
|
|
| 12666 |
|
|
|
| 12667 |
|
|
--QB1_dout_iv_8 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_8
|
| 12668 |
|
|
--operation mode is normal
|
| 12669 |
|
|
|
| 12670 |
|
|
QB1_dout_iv_8 = GD1_dout_iv_1_8 # FD1_wb_o_8 & GD1_dout7_0_a2;
|
| 12671 |
|
|
|
| 12672 |
|
|
--QB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_8
|
| 12673 |
|
|
--operation mode is normal
|
| 12674 |
|
|
|
| 12675 |
|
|
QB1_r32_o_8 = DFFEAS(QB1_dout_iv_8, E1__clk0, VCC, , , , , , );
|
| 12676 |
|
|
|
| 12677 |
|
|
|
| 12678 |
|
|
--FB1_res_7_0_0_8 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_8
|
| 12679 |
|
|
--operation mode is normal
|
| 12680 |
|
|
|
| 12681 |
|
|
FB1_res_7_0_0_8 = ED1_r32_o_6 & CD1_res_7_0_0_o3_0 # ED1_r32_o_8 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_6 & ED1_r32_o_8 & CD1_res_7_0_0_a2_0;
|
| 12682 |
|
|
|
| 12683 |
|
|
--FB1_r32_o_0_8 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_8
|
| 12684 |
|
|
--operation mode is normal
|
| 12685 |
|
|
|
| 12686 |
|
|
FB1_r32_o_0_8 = DFFEAS(FB1_res_7_0_0_8, E1__clk0, VCC, , , , , , );
|
| 12687 |
|
|
|
| 12688 |
|
|
|
| 12689 |
|
|
--UD1_shift_out_80_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[6]
|
| 12690 |
|
|
--operation mode is normal
|
| 12691 |
|
|
|
| 12692 |
|
|
UD1_shift_out_80_a[6] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_9 # !PD1_a_o_1 & !VD1_b_o_iv_7;
|
| 12693 |
|
|
|
| 12694 |
|
|
|
| 12695 |
|
|
--UD1_shift_out_43_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43_a[30]
|
| 12696 |
|
|
--operation mode is normal
|
| 12697 |
|
|
|
| 12698 |
|
|
UD1_shift_out_43_a[30] = PD1_a_o_1 & !VD1_b_o_iv_0 # !PD1_a_o_1 & !VD1_b_o_iv_2;
|
| 12699 |
|
|
|
| 12700 |
|
|
|
| 12701 |
|
|
--RD1_r32_o_0_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_6
|
| 12702 |
|
|
--operation mode is arithmetic
|
| 12703 |
|
|
|
| 12704 |
|
|
RD1_r32_o_0_6_carry_eqn = RD1_r32_o_cout[4];
|
| 12705 |
|
|
RD1_r32_o_0_6_lut_out = KB1_r32_o_6 $ (!RD1_r32_o_0_6_carry_eqn);
|
| 12706 |
|
|
RD1_r32_o_0_6 = DFFEAS(RD1_r32_o_0_6_lut_out, E1__clk0, VCC, , , , , , );
|
| 12707 |
|
|
|
| 12708 |
|
|
--RD1_r32_o_cout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[6]
|
| 12709 |
|
|
--operation mode is arithmetic
|
| 12710 |
|
|
|
| 12711 |
|
|
RD1_r32_o_cout[6] = CARRY(KB1_r32_o_6 & KB1_r32_o_7 & !RD1_r32_o_cout[4]);
|
| 12712 |
|
|
|
| 12713 |
|
|
|
| 12714 |
|
|
--SD1_r32_o_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_6
|
| 12715 |
|
|
--operation mode is normal
|
| 12716 |
|
|
|
| 12717 |
|
|
SD1_r32_o_6_lut_out = KB1_r32_o_6;
|
| 12718 |
|
|
SD1_r32_o_6 = DFFEAS(SD1_r32_o_6_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 12719 |
|
|
|
| 12720 |
|
|
|
| 12721 |
|
|
--PD1_a_o_3_d[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[6]
|
| 12722 |
|
|
--operation mode is normal
|
| 12723 |
|
|
|
| 12724 |
|
|
PD1_a_o_3_d[6] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_6 # !PD1_un6_a_o & !PD1_a_o_3_d_a[6] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[6];
|
| 12725 |
|
|
|
| 12726 |
|
|
|
| 12727 |
|
|
--UD1_shift_out_47_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_47_a[2]
|
| 12728 |
|
|
--operation mode is normal
|
| 12729 |
|
|
|
| 12730 |
|
|
UD1_shift_out_47_a[2] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_25 # !PD1_a_o_0 & !VD1_b_o_iv_24 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 12731 |
|
|
|
| 12732 |
|
|
|
| 12733 |
|
|
--UD1_shift_out_63_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63_a[17]
|
| 12734 |
|
|
--operation mode is normal
|
| 12735 |
|
|
|
| 12736 |
|
|
UD1_shift_out_63_a[17] = !PD1_a_o_2 & !PD1_a_o_1;
|
| 12737 |
|
|
|
| 12738 |
|
|
|
| 12739 |
|
|
--CB1_dout_2_21 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_21
|
| 12740 |
|
|
--operation mode is normal
|
| 12741 |
|
|
|
| 12742 |
|
|
CB1_dout_2_21 = ND1_dout7 & FD1_wb_o_21 # !ND1_dout7 & !ND1_dout_2_a_21;
|
| 12743 |
|
|
|
| 12744 |
|
|
--CB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_21
|
| 12745 |
|
|
--operation mode is normal
|
| 12746 |
|
|
|
| 12747 |
|
|
CB1_r32_o_21 = DFFEAS(CB1_dout_2_21, E1__clk0, VCC, , , , , , );
|
| 12748 |
|
|
|
| 12749 |
|
|
|
| 12750 |
|
|
--TB1_dout_1_x_5 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_5
|
| 12751 |
|
|
--operation mode is normal
|
| 12752 |
|
|
|
| 12753 |
|
|
TB1_dout_1_x_5 = TB1_dout21 & CB1_dout_2_5 # !TB1_dout21 & CB1_dout_2_13;
|
| 12754 |
|
|
|
| 12755 |
|
|
|
| 12756 |
|
|
--TB1_dout_1_2_5 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_5
|
| 12757 |
|
|
--operation mode is normal
|
| 12758 |
|
|
|
| 12759 |
|
|
TB1_dout_1_2_5 = TB1_dout22 & !TB1_dout_1_2_a_x[29] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_5 # !TB1_dout21 & !TB1_dout_1_2_a_x[29];
|
| 12760 |
|
|
|
| 12761 |
|
|
|
| 12762 |
|
|
--TB1_dout_1_2_4 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_4
|
| 12763 |
|
|
--operation mode is normal
|
| 12764 |
|
|
|
| 12765 |
|
|
TB1_dout_1_2_4 = TB1_dout22 & !TB1_dout_1_2_a_x[28] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_4 # !TB1_dout21 & !TB1_dout_1_2_a_x[28];
|
| 12766 |
|
|
|
| 12767 |
|
|
|
| 12768 |
|
|
--TB1_dout_1_x_4 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_4
|
| 12769 |
|
|
--operation mode is normal
|
| 12770 |
|
|
|
| 12771 |
|
|
TB1_dout_1_x_4 = TB1_dout21 & CB1_dout_2_4 # !TB1_dout21 & CB1_dout_2_12;
|
| 12772 |
|
|
|
| 12773 |
|
|
|
| 12774 |
|
|
--M1_ua_state[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state[2]
|
| 12775 |
|
|
--operation mode is normal
|
| 12776 |
|
|
|
| 12777 |
|
|
M1_ua_state[2]_lut_out = M1_clk_ctr_equ15_0_a2 & M1_ua_state[1] # M1_ua_state[2] & M1_ua_state_ns_0_a[2] # !M1_clk_ctr_equ15_0_a2 & M1_ua_state[2];
|
| 12778 |
|
|
M1_ua_state[2] = DFFEAS(M1_ua_state[2]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 12779 |
|
|
|
| 12780 |
|
|
|
| 12781 |
|
|
--M1_ua_state_ns_0_a[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state_ns_0_a[2]
|
| 12782 |
|
|
--operation mode is normal
|
| 12783 |
|
|
|
| 12784 |
|
|
M1_ua_state_ns_0_a[2] = !M1_bit_ctr[0] # !M1_bit_ctr[2] # !M1_bit_ctr[1];
|
| 12785 |
|
|
|
| 12786 |
|
|
|
| 12787 |
|
|
--M1_clk_ctr_equ15_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_equ15_0_a2_a
|
| 12788 |
|
|
--operation mode is normal
|
| 12789 |
|
|
|
| 12790 |
|
|
M1_clk_ctr_equ15_0_a2_a = M1_clk_ctr_2 & !M1_clk_ctr_3;
|
| 12791 |
|
|
|
| 12792 |
|
|
|
| 12793 |
|
|
--CB1_dout_2_19 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_19
|
| 12794 |
|
|
--operation mode is normal
|
| 12795 |
|
|
|
| 12796 |
|
|
CB1_dout_2_19 = ND1_dout7 & FD1_wb_o_19 # !ND1_dout7 & !ND1_dout_2_a_19;
|
| 12797 |
|
|
|
| 12798 |
|
|
--CB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_19
|
| 12799 |
|
|
--operation mode is normal
|
| 12800 |
|
|
|
| 12801 |
|
|
CB1_r32_o_19 = DFFEAS(CB1_dout_2_19, E1__clk0, VCC, , , , , , );
|
| 12802 |
|
|
|
| 12803 |
|
|
|
| 12804 |
|
|
--TB1_dout_1_x_3 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_3
|
| 12805 |
|
|
--operation mode is normal
|
| 12806 |
|
|
|
| 12807 |
|
|
TB1_dout_1_x_3 = TB1_dout21 & CB1_dout_2_3 # !TB1_dout21 & CB1_dout_2_11;
|
| 12808 |
|
|
|
| 12809 |
|
|
|
| 12810 |
|
|
--TB1_dout_1_2_3 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_3
|
| 12811 |
|
|
--operation mode is normal
|
| 12812 |
|
|
|
| 12813 |
|
|
TB1_dout_1_2_3 = TB1_dout22 & !TB1_dout_1_2_a_x[27] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_3 # !TB1_dout21 & !TB1_dout_1_2_a_x[27];
|
| 12814 |
|
|
|
| 12815 |
|
|
|
| 12816 |
|
|
--CB1_dout_2_18 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_18
|
| 12817 |
|
|
--operation mode is normal
|
| 12818 |
|
|
|
| 12819 |
|
|
CB1_dout_2_18 = ND1_dout7 & FD1_wb_o_18 # !ND1_dout7 & !ND1_dout_2_a_18;
|
| 12820 |
|
|
|
| 12821 |
|
|
--CB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_18
|
| 12822 |
|
|
--operation mode is normal
|
| 12823 |
|
|
|
| 12824 |
|
|
CB1_r32_o_18 = DFFEAS(CB1_dout_2_18, E1__clk0, VCC, , , , , , );
|
| 12825 |
|
|
|
| 12826 |
|
|
|
| 12827 |
|
|
--TB1_dout_1_2_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_2
|
| 12828 |
|
|
--operation mode is normal
|
| 12829 |
|
|
|
| 12830 |
|
|
TB1_dout_1_2_2 = TB1_dout22 & !TB1_dout_1_2_a_x[26] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_2 # !TB1_dout21 & !TB1_dout_1_2_a_x[26];
|
| 12831 |
|
|
|
| 12832 |
|
|
|
| 12833 |
|
|
--TB1_dout_1_x_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_2
|
| 12834 |
|
|
--operation mode is normal
|
| 12835 |
|
|
|
| 12836 |
|
|
TB1_dout_1_x_2 = TB1_dout21 & CB1_dout_2_2 # !TB1_dout21 & CB1_dout_2_10;
|
| 12837 |
|
|
|
| 12838 |
|
|
|
| 12839 |
|
|
--CB1_dout_2_17 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_17
|
| 12840 |
|
|
--operation mode is normal
|
| 12841 |
|
|
|
| 12842 |
|
|
CB1_dout_2_17 = ND1_dout7 & FD1_wb_o_17 # !ND1_dout7 & !ND1_dout_2_a_17;
|
| 12843 |
|
|
|
| 12844 |
|
|
--CB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_17
|
| 12845 |
|
|
--operation mode is normal
|
| 12846 |
|
|
|
| 12847 |
|
|
CB1_r32_o_17 = DFFEAS(CB1_dout_2_17, E1__clk0, VCC, , , , , , );
|
| 12848 |
|
|
|
| 12849 |
|
|
|
| 12850 |
|
|
--TB1_dout_1_2_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_1
|
| 12851 |
|
|
--operation mode is normal
|
| 12852 |
|
|
|
| 12853 |
|
|
TB1_dout_1_2_1 = TB1_dout22 & !TB1_dout_1_2_a_x[25] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_1 # !TB1_dout21 & !TB1_dout_1_2_a_x[25];
|
| 12854 |
|
|
|
| 12855 |
|
|
|
| 12856 |
|
|
--TB1_dout_1_x_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_1
|
| 12857 |
|
|
--operation mode is normal
|
| 12858 |
|
|
|
| 12859 |
|
|
TB1_dout_1_x_1 = TB1_dout21 & CB1_dout_2_1 # !TB1_dout21 & CB1_dout_2_9;
|
| 12860 |
|
|
|
| 12861 |
|
|
|
| 12862 |
|
|
--UD1_shift_out_79_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[1]
|
| 12863 |
|
|
--operation mode is normal
|
| 12864 |
|
|
|
| 12865 |
|
|
UD1_shift_out_79_a[1] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_10 # !PD1_a_o_0 & !VD1_b_o_iv_9;
|
| 12866 |
|
|
|
| 12867 |
|
|
|
| 12868 |
|
|
--UD1_shift_out_59[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_59[1]
|
| 12869 |
|
|
--operation mode is normal
|
| 12870 |
|
|
|
| 12871 |
|
|
UD1_shift_out_59[1] = UD1_shift_out587 & PD1_a_o_1 & UD1_shift_out_39[19] # !PD1_a_o_1 & UD1_shift_out_39[17];
|
| 12872 |
|
|
|
| 12873 |
|
|
|
| 12874 |
|
|
--VD1_un134_hilo_combout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[1]
|
| 12875 |
|
|
--operation mode is arithmetic
|
| 12876 |
|
|
|
| 12877 |
|
|
VD1_un134_hilo_combout[1] = VD1_hilo[0] $ VD1_hilo_1;
|
| 12878 |
|
|
|
| 12879 |
|
|
--VD1_un134_hilo_cout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[1]
|
| 12880 |
|
|
--operation mode is arithmetic
|
| 12881 |
|
|
|
| 12882 |
|
|
VD1_un134_hilo_cout[1] = CARRY(VD1_hilo[0] & VD1_hilo_1);
|
| 12883 |
|
|
|
| 12884 |
|
|
|
| 12885 |
|
|
--VD1_hilo_33_i_m[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[33]
|
| 12886 |
|
|
--operation mode is normal
|
| 12887 |
|
|
|
| 12888 |
|
|
VD1_hilo_33_i_m[33] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[33] # !VD1_hilo_33_1[64] & !VD1_hilo_33;
|
| 12889 |
|
|
|
| 12890 |
|
|
|
| 12891 |
|
|
--VD1_hilo_37_iv_2_a[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[33]
|
| 12892 |
|
|
--operation mode is normal
|
| 12893 |
|
|
|
| 12894 |
|
|
VD1_hilo_37_iv_2_a[33] = VD1_hilo_1 & !VD1_hilo_24_add1 & VD1_hilo_2_sqmuxa # !VD1_hilo_1 & VD1_hilo_0_sqmuxa # !VD1_hilo_24_add1 & VD1_hilo_2_sqmuxa;
|
| 12895 |
|
|
|
| 12896 |
|
|
|
| 12897 |
|
|
--VD1_hilo_22_Z[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[33]
|
| 12898 |
|
|
--operation mode is normal
|
| 12899 |
|
|
|
| 12900 |
|
|
VD1_hilo_22_Z[33] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[33] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[33] # !VD1_sign & !VD1_hilo_22_a[33];
|
| 12901 |
|
|
|
| 12902 |
|
|
|
| 12903 |
|
|
--CB1_dout_2_16 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_16
|
| 12904 |
|
|
--operation mode is normal
|
| 12905 |
|
|
|
| 12906 |
|
|
CB1_dout_2_16 = ND1_dout7 & FD1_wb_o_16 # !ND1_dout7 & !ND1_dout_2_a_16;
|
| 12907 |
|
|
|
| 12908 |
|
|
--CB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_16
|
| 12909 |
|
|
--operation mode is normal
|
| 12910 |
|
|
|
| 12911 |
|
|
CB1_r32_o_16 = DFFEAS(CB1_dout_2_16, E1__clk0, VCC, , , , , , );
|
| 12912 |
|
|
|
| 12913 |
|
|
|
| 12914 |
|
|
--TB1_dout_1_x_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_0
|
| 12915 |
|
|
--operation mode is normal
|
| 12916 |
|
|
|
| 12917 |
|
|
TB1_dout_1_x_0 = TB1_dout21 & CB1_dout_2_0 # !TB1_dout21 & CB1_dout_2_8;
|
| 12918 |
|
|
|
| 12919 |
|
|
|
| 12920 |
|
|
--TB1_dout_1_2_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_0
|
| 12921 |
|
|
--operation mode is normal
|
| 12922 |
|
|
|
| 12923 |
|
|
TB1_dout_1_2_0 = TB1_dout22 & !TB1_dout_1_2_a_x[24] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_0 # !TB1_dout21 & !TB1_dout_1_2_a_x[24];
|
| 12924 |
|
|
|
| 12925 |
|
|
|
| 12926 |
|
|
--VD1_hilo_37_iv_2[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[32]
|
| 12927 |
|
|
--operation mode is normal
|
| 12928 |
|
|
|
| 12929 |
|
|
VD1_hilo_37_iv_2[32] = VD1_hilo_33_i_m[32] # VD1_hilo_37_iv_2_a[32] # !VD1_hilo_24_add0 & VD1_hilo_2_sqmuxa;
|
| 12930 |
|
|
|
| 12931 |
|
|
|
| 12932 |
|
|
--VD1_hilo_37_iv_a[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[32]
|
| 12933 |
|
|
--operation mode is normal
|
| 12934 |
|
|
|
| 12935 |
|
|
VD1_hilo_37_iv_a[32] = RC1_alu_func_o_0 & !PD1_a_o_0 # !RC1_alu_func_o_0 & !VD1_hilo[32];
|
| 12936 |
|
|
|
| 12937 |
|
|
|
| 12938 |
|
|
--VD1_hilo_37_iv_0_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[0]
|
| 12939 |
|
|
--operation mode is normal
|
| 12940 |
|
|
|
| 12941 |
|
|
VD1_hilo_37_iv_0_a[0] = !VD1_hilo_37_iv_0_1[0] & VD1_op2_sign_reged $ VD1_hilo_24_add32 # !VD1_hilo_2_sqmuxa;
|
| 12942 |
|
|
|
| 12943 |
|
|
|
| 12944 |
|
|
--UD1_shift_out_79_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[0]
|
| 12945 |
|
|
--operation mode is normal
|
| 12946 |
|
|
|
| 12947 |
|
|
UD1_shift_out_79_a[0] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_9 # !PD1_a_o_0 & !VD1_b_o_iv_8;
|
| 12948 |
|
|
|
| 12949 |
|
|
|
| 12950 |
|
|
--UD1_shift_out_80_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[0]
|
| 12951 |
|
|
--operation mode is normal
|
| 12952 |
|
|
|
| 12953 |
|
|
UD1_shift_out_80_a[0] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_3 # !PD1_a_o_1 & !VD1_b_o_iv_1;
|
| 12954 |
|
|
|
| 12955 |
|
|
|
| 12956 |
|
|
--UD1_shift_out_82_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82_a[0]
|
| 12957 |
|
|
--operation mode is normal
|
| 12958 |
|
|
|
| 12959 |
|
|
UD1_shift_out_82_a[0] = PD1_a_o_2 & !VD1_b_o_iv_4 # !PD1_a_o_2 & !VD1_b_o_iv_2;
|
| 12960 |
|
|
|
| 12961 |
|
|
|
| 12962 |
|
|
--UD1_shift_out_74_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[0]
|
| 12963 |
|
|
--operation mode is normal
|
| 12964 |
|
|
|
| 12965 |
|
|
UD1_shift_out_74_a[0] = PD1_a_o_3 & !PD1_a_o_2 # !PD1_a_o_3 & PD1_a_o_2 & !UD1_shift_out_47[0] # !PD1_a_o_2 & !UD1_shift_out_79[8];
|
| 12966 |
|
|
|
| 12967 |
|
|
|
| 12968 |
|
|
--RD1_r32_o_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_31
|
| 12969 |
|
|
--operation mode is normal
|
| 12970 |
|
|
|
| 12971 |
|
|
RD1_r32_o_31_carry_eqn = RD1_r32_o_cout[29];
|
| 12972 |
|
|
RD1_r32_o_31_lut_out = KB1_r32_o_31 $ (KB1_r32_o_30 & !RD1_r32_o_31_carry_eqn);
|
| 12973 |
|
|
RD1_r32_o_31 = DFFEAS(RD1_r32_o_31_lut_out, E1__clk0, VCC, , , , , , );
|
| 12974 |
|
|
|
| 12975 |
|
|
|
| 12976 |
|
|
--FB1_res_7_0_0_31 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_31
|
| 12977 |
|
|
--operation mode is normal
|
| 12978 |
|
|
|
| 12979 |
|
|
FB1_res_7_0_0_31 = ED1_r32_o_15 & DC1_ext_ctl_o_2 & !DC1_ext_ctl_o_0 # !DC1_ext_ctl_o_2 & !DC1_ext_ctl_o_1 & DC1_ext_ctl_o_0;
|
| 12980 |
|
|
|
| 12981 |
|
|
--FB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_31
|
| 12982 |
|
|
--operation mode is normal
|
| 12983 |
|
|
|
| 12984 |
|
|
FB1_r32_o_31 = DFFEAS(FB1_res_7_0_0_31, E1__clk0, VCC, , , , , , );
|
| 12985 |
|
|
|
| 12986 |
|
|
|
| 12987 |
|
|
--SD1_r32_o_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_31
|
| 12988 |
|
|
--operation mode is normal
|
| 12989 |
|
|
|
| 12990 |
|
|
SD1_r32_o_31_lut_out = KB1_r32_o_31;
|
| 12991 |
|
|
SD1_r32_o_31 = DFFEAS(SD1_r32_o_31_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 12992 |
|
|
|
| 12993 |
|
|
|
| 12994 |
|
|
--PD1_a_o_3_d[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[31]
|
| 12995 |
|
|
--operation mode is normal
|
| 12996 |
|
|
|
| 12997 |
|
|
PD1_a_o_3_d[31] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_31 # !PD1_un6_a_o & !PD1_a_o_3_d_a[31] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[31];
|
| 12998 |
|
|
|
| 12999 |
|
|
|
| 13000 |
|
|
--QB1_dout_iv_31 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_31
|
| 13001 |
|
|
--operation mode is normal
|
| 13002 |
|
|
|
| 13003 |
|
|
QB1_dout_iv_31 = GD1_dout_iv_1_31 # FD1_wb_o_31 & GD1_dout7_0_a2;
|
| 13004 |
|
|
|
| 13005 |
|
|
--QB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_31
|
| 13006 |
|
|
--operation mode is normal
|
| 13007 |
|
|
|
| 13008 |
|
|
QB1_r32_o_31 = DFFEAS(QB1_dout_iv_31, E1__clk0, VCC, , , , , , );
|
| 13009 |
|
|
|
| 13010 |
|
|
|
| 13011 |
|
|
--FD1_wb_o_31 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_31
|
| 13012 |
|
|
--operation mode is normal
|
| 13013 |
|
|
|
| 13014 |
|
|
FD1_wb_o_31 = TC1_wb_mux_ctl_o_0 & F1_dout_31 # DB1_r32_o_31 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_31;
|
| 13015 |
|
|
|
| 13016 |
|
|
--FD1_r_data_31 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_31
|
| 13017 |
|
|
--operation mode is normal
|
| 13018 |
|
|
|
| 13019 |
|
|
FD1_r_data_31 = DFFEAS(FD1_wb_o_31, E1__clk0, VCC, , , , , , );
|
| 13020 |
|
|
|
| 13021 |
|
|
|
| 13022 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[30] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[30]
|
| 13023 |
|
|
--operation mode is normal
|
| 13024 |
|
|
|
| 13025 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[30] = QB1_r32_o_30 & !FB1_r32_o_30 & QD1_b_o18 # !QB1_r32_o_30 & QD1_un1_b_o18_2 # !FB1_r32_o_30 & QD1_b_o18;
|
| 13026 |
|
|
|
| 13027 |
|
|
|
| 13028 |
|
|
--G1_BUS15471_i_m[30] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[30]
|
| 13029 |
|
|
--operation mode is normal
|
| 13030 |
|
|
|
| 13031 |
|
|
G1_BUS15471_i_m[30] = !FD1_wb_o_30 & QD1_b_o_1_sqmuxa;
|
| 13032 |
|
|
|
| 13033 |
|
|
|
| 13034 |
|
|
--PD1_a_o_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_29
|
| 13035 |
|
|
--operation mode is normal
|
| 13036 |
|
|
|
| 13037 |
|
|
PD1_a_o_29 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[29] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[29];
|
| 13038 |
|
|
|
| 13039 |
|
|
|
| 13040 |
|
|
--TD1_lt_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_28
|
| 13041 |
|
|
--operation mode is arithmetic
|
| 13042 |
|
|
|
| 13043 |
|
|
TD1_lt_28 = CARRY(PD1_a_o_28 & VD1_b_o_iv_28 & !TD1_lt_27 # !PD1_a_o_28 & VD1_b_o_iv_28 # !TD1_lt_27);
|
| 13044 |
|
|
|
| 13045 |
|
|
|
| 13046 |
|
|
--TD1_sum_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_29
|
| 13047 |
|
|
--operation mode is arithmetic
|
| 13048 |
|
|
|
| 13049 |
|
|
TD1_sum_carry_29 = CARRY(VD1_b_o_iv_29 & !TD1_sum_carry_28 # !PD1_a_o_29 # !VD1_b_o_iv_29 & !PD1_a_o_29 & !TD1_sum_carry_28);
|
| 13050 |
|
|
|
| 13051 |
|
|
|
| 13052 |
|
|
--Y1_q_b[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[6]
|
| 13053 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 13054 |
|
|
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
|
| 13055 |
|
|
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
|
| 13056 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 13057 |
|
|
Y1_q_b[6]_PORT_A_data_in = CB1_r32_o_6;
|
| 13058 |
|
|
Y1_q_b[6]_PORT_A_data_in_reg = DFFE(Y1_q_b[6]_PORT_A_data_in, Y1_q_b[6]_clock_0, , , );
|
| 13059 |
|
|
Y1_q_b[6]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
|
| 13060 |
|
|
Y1_q_b[6]_PORT_A_address_reg = DFFE(Y1_q_b[6]_PORT_A_address, Y1_q_b[6]_clock_0, , , );
|
| 13061 |
|
|
Y1_q_b[6]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
|
| 13062 |
|
|
Y1_q_b[6]_PORT_B_address_reg = DFFE(Y1_q_b[6]_PORT_B_address, Y1_q_b[6]_clock_1, , , Y1_q_b[6]_clock_enable_1);
|
| 13063 |
|
|
Y1_q_b[6]_PORT_A_write_enable = T1_valid_wreq;
|
| 13064 |
|
|
Y1_q_b[6]_PORT_A_write_enable_reg = DFFE(Y1_q_b[6]_PORT_A_write_enable, Y1_q_b[6]_clock_0, , , );
|
| 13065 |
|
|
Y1_q_b[6]_PORT_B_read_enable = VCC;
|
| 13066 |
|
|
Y1_q_b[6]_PORT_B_read_enable_reg = DFFE(Y1_q_b[6]_PORT_B_read_enable, Y1_q_b[6]_clock_1, , , Y1_q_b[6]_clock_enable_1);
|
| 13067 |
|
|
Y1_q_b[6]_clock_0 = E1__clk0;
|
| 13068 |
|
|
Y1_q_b[6]_clock_1 = E1__clk0;
|
| 13069 |
|
|
Y1_q_b[6]_clock_enable_1 = T1_valid_rreq;
|
| 13070 |
|
|
Y1_q_b[6]_PORT_B_data_out = MEMORY(Y1_q_b[6]_PORT_A_data_in_reg, , Y1_q_b[6]_PORT_A_address_reg, Y1_q_b[6]_PORT_B_address_reg, Y1_q_b[6]_PORT_A_write_enable_reg, Y1_q_b[6]_PORT_B_read_enable_reg, , , Y1_q_b[6]_clock_0, Y1_q_b[6]_clock_1, , Y1_q_b[6]_clock_enable_1, , );
|
| 13071 |
|
|
Y1_q_b[6] = Y1_q_b[6]_PORT_B_data_out[0];
|
| 13072 |
|
|
|
| 13073 |
|
|
|
| 13074 |
|
|
--N1_tx_sr[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[7]
|
| 13075 |
|
|
--operation mode is normal
|
| 13076 |
|
|
|
| 13077 |
|
|
N1_tx_sr[7]_lut_out = Y1_q_b[7] & N1_read_request_ff;
|
| 13078 |
|
|
N1_tx_sr[7] = DFFEAS(N1_tx_sr[7]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );
|
| 13079 |
|
|
|
| 13080 |
|
|
|
| 13081 |
|
|
--CB1_dout_2_30 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_30
|
| 13082 |
|
|
--operation mode is normal
|
| 13083 |
|
|
|
| 13084 |
|
|
CB1_dout_2_30 = ND1_dout7 & FD1_wb_o_30 # !ND1_dout7 & !ND1_dout_2_a_30;
|
| 13085 |
|
|
|
| 13086 |
|
|
--CB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_30
|
| 13087 |
|
|
--operation mode is normal
|
| 13088 |
|
|
|
| 13089 |
|
|
CB1_r32_o_30 = DFFEAS(CB1_dout_2_30, E1__clk0, VCC, , , , , , );
|
| 13090 |
|
|
|
| 13091 |
|
|
|
| 13092 |
|
|
--CB1_dout_2_31 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_31
|
| 13093 |
|
|
--operation mode is normal
|
| 13094 |
|
|
|
| 13095 |
|
|
CB1_dout_2_31 = ND1_dout7 & FD1_wb_o_31 # !ND1_dout7 & !ND1_dout_2_a_31;
|
| 13096 |
|
|
|
| 13097 |
|
|
--CB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_31
|
| 13098 |
|
|
--operation mode is normal
|
| 13099 |
|
|
|
| 13100 |
|
|
CB1_r32_o_31 = DFFEAS(CB1_dout_2_31, E1__clk0, VCC, , , , , , );
|
| 13101 |
|
|
|
| 13102 |
|
|
|
| 13103 |
|
|
--CB1_dout_2_28 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_28
|
| 13104 |
|
|
--operation mode is normal
|
| 13105 |
|
|
|
| 13106 |
|
|
CB1_dout_2_28 = ND1_dout7 & FD1_wb_o_28 # !ND1_dout7 & !ND1_dout_2_a_28;
|
| 13107 |
|
|
|
| 13108 |
|
|
--CB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_28
|
| 13109 |
|
|
--operation mode is normal
|
| 13110 |
|
|
|
| 13111 |
|
|
CB1_r32_o_28 = DFFEAS(CB1_dout_2_28, E1__clk0, VCC, , , , , , );
|
| 13112 |
|
|
|
| 13113 |
|
|
|
| 13114 |
|
|
--K1_cntr_5_0[27] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[27]
|
| 13115 |
|
|
--operation mode is normal
|
| 13116 |
|
|
|
| 13117 |
|
|
K1_s_cntr_27__Z_qfbk = K1_s_cntr_27__Z;
|
| 13118 |
|
|
K1_cntr_5_0[27] = F1_wr_tmr_data_0_a2 & CB1_r32_o_27 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_27__Z_qfbk;
|
| 13119 |
|
|
|
| 13120 |
|
|
--K1_s_cntr_27__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_27__Z
|
| 13121 |
|
|
--operation mode is normal
|
| 13122 |
|
|
|
| 13123 |
|
|
K1_s_cntr_27__Z = DFFEAS(K1_cntr_5_0[27], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_27, , , VCC);
|
| 13124 |
|
|
|
| 13125 |
|
|
|
| 13126 |
|
|
--CB1_dout_2_29 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_29
|
| 13127 |
|
|
--operation mode is normal
|
| 13128 |
|
|
|
| 13129 |
|
|
CB1_dout_2_29 = ND1_dout7 & FD1_wb_o_29 # !ND1_dout7 & !ND1_dout_2_a_29;
|
| 13130 |
|
|
|
| 13131 |
|
|
--CB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_29
|
| 13132 |
|
|
--operation mode is normal
|
| 13133 |
|
|
|
| 13134 |
|
|
CB1_r32_o_29 = DFFEAS(CB1_dout_2_29, E1__clk0, VCC, , , , , , );
|
| 13135 |
|
|
|
| 13136 |
|
|
|
| 13137 |
|
|
--K1_cntr_5_0[18] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[18]
|
| 13138 |
|
|
--operation mode is normal
|
| 13139 |
|
|
|
| 13140 |
|
|
K1_s_cntr_18__Z_qfbk = K1_s_cntr_18__Z;
|
| 13141 |
|
|
K1_cntr_5_0[18] = F1_wr_tmr_data_0_a2 & CB1_r32_o_18 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_18__Z_qfbk;
|
| 13142 |
|
|
|
| 13143 |
|
|
--K1_s_cntr_18__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_18__Z
|
| 13144 |
|
|
--operation mode is normal
|
| 13145 |
|
|
|
| 13146 |
|
|
K1_s_cntr_18__Z = DFFEAS(K1_cntr_5_0[18], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_18, , , VCC);
|
| 13147 |
|
|
|
| 13148 |
|
|
|
| 13149 |
|
|
--K1_cntr_5_0[19] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[19]
|
| 13150 |
|
|
--operation mode is normal
|
| 13151 |
|
|
|
| 13152 |
|
|
K1_s_cntr_19__Z_qfbk = K1_s_cntr_19__Z;
|
| 13153 |
|
|
K1_cntr_5_0[19] = F1_wr_tmr_data_0_a2 & CB1_r32_o_19 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_19__Z_qfbk;
|
| 13154 |
|
|
|
| 13155 |
|
|
--K1_s_cntr_19__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_19__Z
|
| 13156 |
|
|
--operation mode is normal
|
| 13157 |
|
|
|
| 13158 |
|
|
K1_s_cntr_19__Z = DFFEAS(K1_cntr_5_0[19], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_19, , , VCC);
|
| 13159 |
|
|
|
| 13160 |
|
|
|
| 13161 |
|
|
--K1_cntr_5_0[16] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[16]
|
| 13162 |
|
|
--operation mode is normal
|
| 13163 |
|
|
|
| 13164 |
|
|
K1_s_cntr_16__Z_qfbk = K1_s_cntr_16__Z;
|
| 13165 |
|
|
K1_cntr_5_0[16] = F1_wr_tmr_data_0_a2 & CB1_r32_o_16 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_16__Z_qfbk;
|
| 13166 |
|
|
|
| 13167 |
|
|
--K1_s_cntr_16__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_16__Z
|
| 13168 |
|
|
--operation mode is normal
|
| 13169 |
|
|
|
| 13170 |
|
|
K1_s_cntr_16__Z = DFFEAS(K1_cntr_5_0[16], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_16, , , VCC);
|
| 13171 |
|
|
|
| 13172 |
|
|
|
| 13173 |
|
|
--K1_cntr_5_0[17] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[17]
|
| 13174 |
|
|
--operation mode is normal
|
| 13175 |
|
|
|
| 13176 |
|
|
K1_s_cntr_17__Z_qfbk = K1_s_cntr_17__Z;
|
| 13177 |
|
|
K1_cntr_5_0[17] = F1_wr_tmr_data_0_a2 & CB1_r32_o_17 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_17__Z_qfbk;
|
| 13178 |
|
|
|
| 13179 |
|
|
--K1_s_cntr_17__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_17__Z
|
| 13180 |
|
|
--operation mode is normal
|
| 13181 |
|
|
|
| 13182 |
|
|
K1_s_cntr_17__Z = DFFEAS(K1_cntr_5_0[17], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_17, , , VCC);
|
| 13183 |
|
|
|
| 13184 |
|
|
|
| 13185 |
|
|
--K1_cntr_5_0[22] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[22]
|
| 13186 |
|
|
--operation mode is normal
|
| 13187 |
|
|
|
| 13188 |
|
|
K1_s_cntr_22__Z_qfbk = K1_s_cntr_22__Z;
|
| 13189 |
|
|
K1_cntr_5_0[22] = F1_wr_tmr_data_0_a2 & CB1_r32_o_22 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_22__Z_qfbk;
|
| 13190 |
|
|
|
| 13191 |
|
|
--K1_s_cntr_22__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_22__Z
|
| 13192 |
|
|
--operation mode is normal
|
| 13193 |
|
|
|
| 13194 |
|
|
K1_s_cntr_22__Z = DFFEAS(K1_cntr_5_0[22], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_22, , , VCC);
|
| 13195 |
|
|
|
| 13196 |
|
|
|
| 13197 |
|
|
--K1_cntr_5_0[23] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[23]
|
| 13198 |
|
|
--operation mode is normal
|
| 13199 |
|
|
|
| 13200 |
|
|
K1_s_cntr_23__Z_qfbk = K1_s_cntr_23__Z;
|
| 13201 |
|
|
K1_cntr_5_0[23] = F1_wr_tmr_data_0_a2 & CB1_r32_o_23 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_23__Z_qfbk;
|
| 13202 |
|
|
|
| 13203 |
|
|
--K1_s_cntr_23__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_23__Z
|
| 13204 |
|
|
--operation mode is normal
|
| 13205 |
|
|
|
| 13206 |
|
|
K1_s_cntr_23__Z = DFFEAS(K1_cntr_5_0[23], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_23, , , VCC);
|
| 13207 |
|
|
|
| 13208 |
|
|
|
| 13209 |
|
|
--K1_cntr_5_0[20] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[20]
|
| 13210 |
|
|
--operation mode is normal
|
| 13211 |
|
|
|
| 13212 |
|
|
K1_s_cntr_20__Z_qfbk = K1_s_cntr_20__Z;
|
| 13213 |
|
|
K1_cntr_5_0[20] = F1_wr_tmr_data_0_a2 & CB1_r32_o_20 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_20__Z_qfbk;
|
| 13214 |
|
|
|
| 13215 |
|
|
--K1_s_cntr_20__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_20__Z
|
| 13216 |
|
|
--operation mode is normal
|
| 13217 |
|
|
|
| 13218 |
|
|
K1_s_cntr_20__Z = DFFEAS(K1_cntr_5_0[20], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_20, , , VCC);
|
| 13219 |
|
|
|
| 13220 |
|
|
|
| 13221 |
|
|
--K1_cntr_5_0[21] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[21]
|
| 13222 |
|
|
--operation mode is normal
|
| 13223 |
|
|
|
| 13224 |
|
|
K1_s_cntr_21__Z_qfbk = K1_s_cntr_21__Z;
|
| 13225 |
|
|
K1_cntr_5_0[21] = F1_wr_tmr_data_0_a2 & CB1_r32_o_21 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_21__Z_qfbk;
|
| 13226 |
|
|
|
| 13227 |
|
|
--K1_s_cntr_21__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_21__Z
|
| 13228 |
|
|
--operation mode is normal
|
| 13229 |
|
|
|
| 13230 |
|
|
K1_s_cntr_21__Z = DFFEAS(K1_cntr_5_0[21], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_21, , , VCC);
|
| 13231 |
|
|
|
| 13232 |
|
|
|
| 13233 |
|
|
--K1_cntr_5_0[26] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[26]
|
| 13234 |
|
|
--operation mode is normal
|
| 13235 |
|
|
|
| 13236 |
|
|
K1_s_cntr_26__Z_qfbk = K1_s_cntr_26__Z;
|
| 13237 |
|
|
K1_cntr_5_0[26] = F1_wr_tmr_data_0_a2 & CB1_r32_o_26 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_26__Z_qfbk;
|
| 13238 |
|
|
|
| 13239 |
|
|
--K1_s_cntr_26__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_26__Z
|
| 13240 |
|
|
--operation mode is normal
|
| 13241 |
|
|
|
| 13242 |
|
|
K1_s_cntr_26__Z = DFFEAS(K1_cntr_5_0[26], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_26, , , VCC);
|
| 13243 |
|
|
|
| 13244 |
|
|
|
| 13245 |
|
|
--K1_cntr_5_0[24] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[24]
|
| 13246 |
|
|
--operation mode is normal
|
| 13247 |
|
|
|
| 13248 |
|
|
K1_s_cntr_24__Z_qfbk = K1_s_cntr_24__Z;
|
| 13249 |
|
|
K1_cntr_5_0[24] = F1_wr_tmr_data_0_a2 & CB1_r32_o_24 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_24__Z_qfbk;
|
| 13250 |
|
|
|
| 13251 |
|
|
--K1_s_cntr_24__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_24__Z
|
| 13252 |
|
|
--operation mode is normal
|
| 13253 |
|
|
|
| 13254 |
|
|
K1_s_cntr_24__Z = DFFEAS(K1_cntr_5_0[24], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_24, , , VCC);
|
| 13255 |
|
|
|
| 13256 |
|
|
|
| 13257 |
|
|
--K1_cntr_5_0[25] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[25]
|
| 13258 |
|
|
--operation mode is normal
|
| 13259 |
|
|
|
| 13260 |
|
|
K1_s_cntr_25__Z_qfbk = K1_s_cntr_25__Z;
|
| 13261 |
|
|
K1_cntr_5_0[25] = F1_wr_tmr_data_0_a2 & CB1_r32_o_25 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_25__Z_qfbk;
|
| 13262 |
|
|
|
| 13263 |
|
|
--K1_s_cntr_25__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_25__Z
|
| 13264 |
|
|
--operation mode is normal
|
| 13265 |
|
|
|
| 13266 |
|
|
K1_s_cntr_25__Z = DFFEAS(K1_cntr_5_0[25], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_25, , , VCC);
|
| 13267 |
|
|
|
| 13268 |
|
|
|
| 13269 |
|
|
--K1_cntr_5_0[10] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[10]
|
| 13270 |
|
|
--operation mode is normal
|
| 13271 |
|
|
|
| 13272 |
|
|
K1_s_cntr_10__Z_qfbk = K1_s_cntr_10__Z;
|
| 13273 |
|
|
K1_cntr_5_0[10] = F1_wr_tmr_data_0_a2 & CB1_r32_o_10 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_10__Z_qfbk;
|
| 13274 |
|
|
|
| 13275 |
|
|
--K1_s_cntr_10__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_10__Z
|
| 13276 |
|
|
--operation mode is normal
|
| 13277 |
|
|
|
| 13278 |
|
|
K1_s_cntr_10__Z = DFFEAS(K1_cntr_5_0[10], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_10, , , VCC);
|
| 13279 |
|
|
|
| 13280 |
|
|
|
| 13281 |
|
|
--K1_cntr_5_0[11] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[11]
|
| 13282 |
|
|
--operation mode is normal
|
| 13283 |
|
|
|
| 13284 |
|
|
K1_s_cntr_11__Z_qfbk = K1_s_cntr_11__Z;
|
| 13285 |
|
|
K1_cntr_5_0[11] = F1_wr_tmr_data_0_a2 & CB1_r32_o_11 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_11__Z_qfbk;
|
| 13286 |
|
|
|
| 13287 |
|
|
--K1_s_cntr_11__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_11__Z
|
| 13288 |
|
|
--operation mode is normal
|
| 13289 |
|
|
|
| 13290 |
|
|
K1_s_cntr_11__Z = DFFEAS(K1_cntr_5_0[11], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_11, , , VCC);
|
| 13291 |
|
|
|
| 13292 |
|
|
|
| 13293 |
|
|
--K1_cntr_5_0[8] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[8]
|
| 13294 |
|
|
--operation mode is normal
|
| 13295 |
|
|
|
| 13296 |
|
|
K1_s_cntr_8__Z_qfbk = K1_s_cntr_8__Z;
|
| 13297 |
|
|
K1_cntr_5_0[8] = F1_wr_tmr_data_0_a2 & CB1_r32_o_8 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_8__Z_qfbk;
|
| 13298 |
|
|
|
| 13299 |
|
|
--K1_s_cntr_8__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_8__Z
|
| 13300 |
|
|
--operation mode is normal
|
| 13301 |
|
|
|
| 13302 |
|
|
K1_s_cntr_8__Z = DFFEAS(K1_cntr_5_0[8], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_8, , , VCC);
|
| 13303 |
|
|
|
| 13304 |
|
|
|
| 13305 |
|
|
--K1_cntr_5_0[9] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[9]
|
| 13306 |
|
|
--operation mode is normal
|
| 13307 |
|
|
|
| 13308 |
|
|
K1_s_cntr_9__Z_qfbk = K1_s_cntr_9__Z;
|
| 13309 |
|
|
K1_cntr_5_0[9] = F1_wr_tmr_data_0_a2 & CB1_r32_o_9 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_9__Z_qfbk;
|
| 13310 |
|
|
|
| 13311 |
|
|
--K1_s_cntr_9__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_9__Z
|
| 13312 |
|
|
--operation mode is normal
|
| 13313 |
|
|
|
| 13314 |
|
|
K1_s_cntr_9__Z = DFFEAS(K1_cntr_5_0[9], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_9, , , VCC);
|
| 13315 |
|
|
|
| 13316 |
|
|
|
| 13317 |
|
|
--K1_cntr_5_0[14] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[14]
|
| 13318 |
|
|
--operation mode is normal
|
| 13319 |
|
|
|
| 13320 |
|
|
K1_s_cntr_14__Z_qfbk = K1_s_cntr_14__Z;
|
| 13321 |
|
|
K1_cntr_5_0[14] = F1_wr_tmr_data_0_a2 & CB1_r32_o_14 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_14__Z_qfbk;
|
| 13322 |
|
|
|
| 13323 |
|
|
--K1_s_cntr_14__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_14__Z
|
| 13324 |
|
|
--operation mode is normal
|
| 13325 |
|
|
|
| 13326 |
|
|
K1_s_cntr_14__Z = DFFEAS(K1_cntr_5_0[14], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_14, , , VCC);
|
| 13327 |
|
|
|
| 13328 |
|
|
|
| 13329 |
|
|
--K1_cntr_5_0[15] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[15]
|
| 13330 |
|
|
--operation mode is normal
|
| 13331 |
|
|
|
| 13332 |
|
|
K1_s_cntr_15__Z_qfbk = K1_s_cntr_15__Z;
|
| 13333 |
|
|
K1_cntr_5_0[15] = F1_wr_tmr_data_0_a2 & CB1_r32_o_15 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_15__Z_qfbk;
|
| 13334 |
|
|
|
| 13335 |
|
|
--K1_s_cntr_15__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_15__Z
|
| 13336 |
|
|
--operation mode is normal
|
| 13337 |
|
|
|
| 13338 |
|
|
K1_s_cntr_15__Z = DFFEAS(K1_cntr_5_0[15], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_15, , , VCC);
|
| 13339 |
|
|
|
| 13340 |
|
|
|
| 13341 |
|
|
--K1_cntr_5_0[12] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[12]
|
| 13342 |
|
|
--operation mode is normal
|
| 13343 |
|
|
|
| 13344 |
|
|
K1_s_cntr_12__Z_qfbk = K1_s_cntr_12__Z;
|
| 13345 |
|
|
K1_cntr_5_0[12] = F1_wr_tmr_data_0_a2 & CB1_r32_o_12 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_12__Z_qfbk;
|
| 13346 |
|
|
|
| 13347 |
|
|
--K1_s_cntr_12__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_12__Z
|
| 13348 |
|
|
--operation mode is normal
|
| 13349 |
|
|
|
| 13350 |
|
|
K1_s_cntr_12__Z = DFFEAS(K1_cntr_5_0[12], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_12, , , VCC);
|
| 13351 |
|
|
|
| 13352 |
|
|
|
| 13353 |
|
|
--K1_cntr_5_0[13] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[13]
|
| 13354 |
|
|
--operation mode is normal
|
| 13355 |
|
|
|
| 13356 |
|
|
K1_s_cntr_13__Z_qfbk = K1_s_cntr_13__Z;
|
| 13357 |
|
|
K1_cntr_5_0[13] = F1_wr_tmr_data_0_a2 & CB1_r32_o_13 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_13__Z_qfbk;
|
| 13358 |
|
|
|
| 13359 |
|
|
--K1_s_cntr_13__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_13__Z
|
| 13360 |
|
|
--operation mode is normal
|
| 13361 |
|
|
|
| 13362 |
|
|
K1_s_cntr_13__Z = DFFEAS(K1_cntr_5_0[13], E1__clk0, VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_13, , , VCC);
|
| 13363 |
|
|
|
| 13364 |
|
|
|
| 13365 |
|
|
--F1_dout_8 is mips_sys:isys|mips_dvc:imips_dvc|dout_8
|
| 13366 |
|
|
--operation mode is normal
|
| 13367 |
|
|
|
| 13368 |
|
|
F1_dout_8_lut_out = F1_cmd[8] & F1_dout_0_0_a3_3[0] # K1_cntr_8 & F1_dout_0_0_a3_4[0] # !F1_cmd[8] & K1_cntr_8 & F1_dout_0_0_a3_4[0];
|
| 13369 |
|
|
F1_dout_8 = DFFEAS(F1_dout_8_lut_out, E1__clk0, VCC, , , , , , );
|
| 13370 |
|
|
|
| 13371 |
|
|
|
| 13372 |
|
|
--DB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_8
|
| 13373 |
|
|
--operation mode is normal
|
| 13374 |
|
|
|
| 13375 |
|
|
DB1_r32_o_8_lut_out = WB31L1;
|
| 13376 |
|
|
DB1_r32_o_8 = DFFEAS(DB1_r32_o_8_lut_out, E1__clk0, VCC, , , , , , );
|
| 13377 |
|
|
|
| 13378 |
|
|
|
| 13379 |
|
|
--BB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_8
|
| 13380 |
|
|
--operation mode is normal
|
| 13381 |
|
|
|
| 13382 |
|
|
BB1_r32_o_8_lut_out = AB1_r32_o_6;
|
| 13383 |
|
|
BB1_r32_o_8 = DFFEAS(BB1_r32_o_8_lut_out, E1__clk0, VCC, , , , , , );
|
| 13384 |
|
|
|
| 13385 |
|
|
|
| 13386 |
|
|
--M1_clk_ctr27_i_i is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_i
|
| 13387 |
|
|
--operation mode is normal
|
| 13388 |
|
|
|
| 13389 |
|
|
M1_clk_ctr27_i_i = sys_rst & M1_ua_state_i[0] & !M1_ua_state[4] & M1_clk_ctr27_i_0_a;
|
| 13390 |
|
|
|
| 13391 |
|
|
|
| 13392 |
|
|
--M1_clk_ctr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[1]
|
| 13393 |
|
|
--operation mode is arithmetic
|
| 13394 |
|
|
|
| 13395 |
|
|
M1_clk_ctr[1]_carry_eqn = M1_clk_ctr_cout[0];
|
| 13396 |
|
|
M1_clk_ctr[1]_lut_out = M1_clk_ctr[1] $ (M1_clk_ctr[1]_carry_eqn);
|
| 13397 |
|
|
M1_clk_ctr[1] = DFFEAS(M1_clk_ctr[1]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 13398 |
|
|
|
| 13399 |
|
|
--M1_clk_ctr_cout[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[1]
|
| 13400 |
|
|
--operation mode is arithmetic
|
| 13401 |
|
|
|
| 13402 |
|
|
M1_clk_ctr_cout[1] = CARRY(!M1_clk_ctr_cout[0] # !M1_clk_ctr[1]);
|
| 13403 |
|
|
|
| 13404 |
|
|
|
| 13405 |
|
|
--M1_clk_ctr[12] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[12]
|
| 13406 |
|
|
--operation mode is arithmetic
|
| 13407 |
|
|
|
| 13408 |
|
|
M1_clk_ctr[12]_carry_eqn = M1_clk_ctr_cout[11];
|
| 13409 |
|
|
M1_clk_ctr[12]_lut_out = M1_clk_ctr[12] $ (!M1_clk_ctr[12]_carry_eqn);
|
| 13410 |
|
|
M1_clk_ctr[12] = DFFEAS(M1_clk_ctr[12]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 13411 |
|
|
|
| 13412 |
|
|
--M1_clk_ctr_cout[12] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[12]
|
| 13413 |
|
|
--operation mode is arithmetic
|
| 13414 |
|
|
|
| 13415 |
|
|
M1_clk_ctr_cout[12] = CARRY(M1_clk_ctr[12] & !M1_clk_ctr_cout[11]);
|
| 13416 |
|
|
|
| 13417 |
|
|
|
| 13418 |
|
|
--M1_clk_ctr[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[6]
|
| 13419 |
|
|
--operation mode is arithmetic
|
| 13420 |
|
|
|
| 13421 |
|
|
M1_clk_ctr[6]_carry_eqn = M1_clk_ctr_cout[5];
|
| 13422 |
|
|
M1_clk_ctr[6]_lut_out = M1_clk_ctr[6] $ (!M1_clk_ctr[6]_carry_eqn);
|
| 13423 |
|
|
M1_clk_ctr[6] = DFFEAS(M1_clk_ctr[6]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 13424 |
|
|
|
| 13425 |
|
|
--M1_clk_ctr_cout[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[6]
|
| 13426 |
|
|
--operation mode is arithmetic
|
| 13427 |
|
|
|
| 13428 |
|
|
M1_clk_ctr_cout[6] = CARRY(M1_clk_ctr[6] & !M1_clk_ctr_cout[5]);
|
| 13429 |
|
|
|
| 13430 |
|
|
|
| 13431 |
|
|
--M1_clk_ctr[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[7]
|
| 13432 |
|
|
--operation mode is arithmetic
|
| 13433 |
|
|
|
| 13434 |
|
|
M1_clk_ctr[7]_carry_eqn = M1_clk_ctr_cout[6];
|
| 13435 |
|
|
M1_clk_ctr[7]_lut_out = M1_clk_ctr[7] $ (M1_clk_ctr[7]_carry_eqn);
|
| 13436 |
|
|
M1_clk_ctr[7] = DFFEAS(M1_clk_ctr[7]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 13437 |
|
|
|
| 13438 |
|
|
--M1_clk_ctr_cout[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[7]
|
| 13439 |
|
|
--operation mode is arithmetic
|
| 13440 |
|
|
|
| 13441 |
|
|
M1_clk_ctr_cout[7] = CARRY(!M1_clk_ctr_cout[6] # !M1_clk_ctr[7]);
|
| 13442 |
|
|
|
| 13443 |
|
|
|
| 13444 |
|
|
--M1_clk_ctr[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[4]
|
| 13445 |
|
|
--operation mode is arithmetic
|
| 13446 |
|
|
|
| 13447 |
|
|
M1_clk_ctr[4]_carry_eqn = M1_clk_ctr_cout[3];
|
| 13448 |
|
|
M1_clk_ctr[4]_lut_out = M1_clk_ctr[4] $ (!M1_clk_ctr[4]_carry_eqn);
|
| 13449 |
|
|
M1_clk_ctr[4] = DFFEAS(M1_clk_ctr[4]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 13450 |
|
|
|
| 13451 |
|
|
--M1_clk_ctr_cout[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[4]
|
| 13452 |
|
|
--operation mode is arithmetic
|
| 13453 |
|
|
|
| 13454 |
|
|
M1_clk_ctr_cout[4] = CARRY(M1_clk_ctr[4] & !M1_clk_ctr_cout[3]);
|
| 13455 |
|
|
|
| 13456 |
|
|
|
| 13457 |
|
|
--M1_clk_ctr[9] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[9]
|
| 13458 |
|
|
--operation mode is arithmetic
|
| 13459 |
|
|
|
| 13460 |
|
|
M1_clk_ctr[9]_carry_eqn = M1_clk_ctr_cout[8];
|
| 13461 |
|
|
M1_clk_ctr[9]_lut_out = M1_clk_ctr[9] $ (M1_clk_ctr[9]_carry_eqn);
|
| 13462 |
|
|
M1_clk_ctr[9] = DFFEAS(M1_clk_ctr[9]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 13463 |
|
|
|
| 13464 |
|
|
--M1_clk_ctr_cout[9] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[9]
|
| 13465 |
|
|
--operation mode is arithmetic
|
| 13466 |
|
|
|
| 13467 |
|
|
M1_clk_ctr_cout[9] = CARRY(!M1_clk_ctr_cout[8] # !M1_clk_ctr[9]);
|
| 13468 |
|
|
|
| 13469 |
|
|
|
| 13470 |
|
|
--M1_clk_ctr[11] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[11]
|
| 13471 |
|
|
--operation mode is arithmetic
|
| 13472 |
|
|
|
| 13473 |
|
|
M1_clk_ctr[11]_carry_eqn = M1_clk_ctr_cout[10];
|
| 13474 |
|
|
M1_clk_ctr[11]_lut_out = M1_clk_ctr[11] $ (M1_clk_ctr[11]_carry_eqn);
|
| 13475 |
|
|
M1_clk_ctr[11] = DFFEAS(M1_clk_ctr[11]_lut_out, E1__clk0, VCC, , , , , !M1_clk_ctr27_i_i, );
|
| 13476 |
|
|
|
| 13477 |
|
|
--M1_clk_ctr_cout[11] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[11]
|
| 13478 |
|
|
--operation mode is arithmetic
|
| 13479 |
|
|
|
| 13480 |
|
|
M1_clk_ctr_cout[11] = CARRY(!M1_clk_ctr_cout[10] # !M1_clk_ctr[11]);
|
| 13481 |
|
|
|
| 13482 |
|
|
|
| 13483 |
|
|
--SB1_wr_en46_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|wr_en46_0
|
| 13484 |
|
|
--operation mode is normal
|
| 13485 |
|
|
|
| 13486 |
|
|
SB1_wr_en46_0 = QC1_dmem_ctl_o_0 & QC1_dmem_ctl_o_2;
|
| 13487 |
|
|
|
| 13488 |
|
|
|
| 13489 |
|
|
--DD1_un1_pc_next46_0_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_next46_0_a
|
| 13490 |
|
|
--operation mode is normal
|
| 13491 |
|
|
|
| 13492 |
|
|
DD1_un1_pc_next46_0_a = HC1_pc_gen_ctl_o_0 & !HC1_pc_gen_ctl_o_2 & !HC1_pc_gen_ctl_o_1 # !HC1_pc_gen_ctl_o_0 & HC1_pc_gen_ctl_o_1;
|
| 13493 |
|
|
|
| 13494 |
|
|
|
| 13495 |
|
|
--AD1_pc_prectl_1_0_i_a2_0_a2_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|pc_prectl_1_0_i_a2_0_a2_0
|
| 13496 |
|
|
--operation mode is normal
|
| 13497 |
|
|
|
| 13498 |
|
|
AD1_pc_prectl_1_0_i_a2_0_a2_0 = !AD1_CurrState_Sreg0_3 & !AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
|
| 13499 |
|
|
|
| 13500 |
|
|
|
| 13501 |
|
|
--AD1_pc_prectl_1_0_i_a2_0_a2_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|pc_prectl_1_0_i_a2_0_a2_1
|
| 13502 |
|
|
--operation mode is normal
|
| 13503 |
|
|
|
| 13504 |
|
|
AD1_pc_prectl_1_0_i_a2_0_a2_1 = AD1_CurrState_Sreg0_i[0] & !AD1_CurrState_Sreg0[7] & !AD1_CurrState_Sreg0[2] & !AD1_CurrState_Sreg0_2;
|
| 13505 |
|
|
|
| 13506 |
|
|
|
| 13507 |
|
|
--DD1_pc_next_2_sqmuxa_0_a4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_2_sqmuxa_0_a4
|
| 13508 |
|
|
--operation mode is normal
|
| 13509 |
|
|
|
| 13510 |
|
|
DD1_pc_next_2_sqmuxa_0_a4 = HC1_pc_gen_ctl_o_1 & !HC1_pc_gen_ctl_o_2 & !HC1_pc_gen_ctl_o_0 & DD1_pc_next_2_sqmuxa_1_i_a2;
|
| 13511 |
|
|
|
| 13512 |
|
|
|
| 13513 |
|
|
--DD1_pc_next_0_iv_1_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[2]
|
| 13514 |
|
|
--operation mode is normal
|
| 13515 |
|
|
|
| 13516 |
|
|
DD1_pc_next_0_iv_1_a[2] = SD1_r32_o_2 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_2 # !SD1_r32_o_2 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_2;
|
| 13517 |
|
|
|
| 13518 |
|
|
|
| 13519 |
|
|
--PB1_dout_iv_2 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_2
|
| 13520 |
|
|
--operation mode is normal
|
| 13521 |
|
|
|
| 13522 |
|
|
PB1_dout_iv_2 = HD1_dout_iv_1_2 # FD1_wb_o_2 & HD1_dout7_0_a2;
|
| 13523 |
|
|
|
| 13524 |
|
|
--PB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_2
|
| 13525 |
|
|
--operation mode is normal
|
| 13526 |
|
|
|
| 13527 |
|
|
PB1_r32_o_2 = DFFEAS(PB1_dout_iv_2, E1__clk0, VCC, , , , , , );
|
| 13528 |
|
|
|
| 13529 |
|
|
|
| 13530 |
|
|
--DD1_un1_pc_prectl_1_i[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_i[2]
|
| 13531 |
|
|
--operation mode is normal
|
| 13532 |
|
|
|
| 13533 |
|
|
DD1_un1_pc_prectl_1_i[2] = AD1_pc_prectl_1_0_i_a2_0_a2_0 # DD1_un1_pc_prectl_1_i_a[2] & !FB1_res_7_0_0_2 & BD1_res_7_0;
|
| 13534 |
|
|
|
| 13535 |
|
|
|
| 13536 |
|
|
--DD1_pc_next_0_iv_1_a[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[3]
|
| 13537 |
|
|
--operation mode is normal
|
| 13538 |
|
|
|
| 13539 |
|
|
DD1_pc_next_0_iv_1_a[3] = SD1_r32_o_3 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_3 # !SD1_r32_o_3 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_3;
|
| 13540 |
|
|
|
| 13541 |
|
|
|
| 13542 |
|
|
--PB1_dout_iv_3 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_3
|
| 13543 |
|
|
--operation mode is normal
|
| 13544 |
|
|
|
| 13545 |
|
|
PB1_dout_iv_3 = HD1_dout_iv_1_3 # FD1_wb_o_3 & HD1_dout7_0_a2;
|
| 13546 |
|
|
|
| 13547 |
|
|
--PB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_3
|
| 13548 |
|
|
--operation mode is normal
|
| 13549 |
|
|
|
| 13550 |
|
|
PB1_r32_o_3 = DFFEAS(PB1_dout_iv_3, E1__clk0, VCC, , , , , , );
|
| 13551 |
|
|
|
| 13552 |
|
|
|
| 13553 |
|
|
--DD1_un1_pc_prectl_1_0_a4[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[3]
|
| 13554 |
|
|
--operation mode is normal
|
| 13555 |
|
|
|
| 13556 |
|
|
DD1_un1_pc_prectl_1_0_a4[3] = FB1_res_7_0_0_3 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13557 |
|
|
|
| 13558 |
|
|
|
| 13559 |
|
|
--DD1_pc_next_0_iv_1_a[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[4]
|
| 13560 |
|
|
--operation mode is normal
|
| 13561 |
|
|
|
| 13562 |
|
|
DD1_pc_next_0_iv_1_a[4] = SD1_r32_o_4 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_4 # !SD1_r32_o_4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_4;
|
| 13563 |
|
|
|
| 13564 |
|
|
|
| 13565 |
|
|
--DD1_un1_pc_prectl_1_0_a4[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[4]
|
| 13566 |
|
|
--operation mode is normal
|
| 13567 |
|
|
|
| 13568 |
|
|
DD1_un1_pc_prectl_1_0_a4[4] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_0_2 # ED1_r32_o_2 & CD1_res_7_0_0_o3_0;
|
| 13569 |
|
|
|
| 13570 |
|
|
|
| 13571 |
|
|
--DD1_pc_next_0_iv_1_a[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[5]
|
| 13572 |
|
|
--operation mode is normal
|
| 13573 |
|
|
|
| 13574 |
|
|
DD1_pc_next_0_iv_1_a[5] = SD1_r32_o_5 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_5 # !SD1_r32_o_5 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_5;
|
| 13575 |
|
|
|
| 13576 |
|
|
|
| 13577 |
|
|
--DD1_un1_pc_prectl_1_0_a4[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[5]
|
| 13578 |
|
|
--operation mode is normal
|
| 13579 |
|
|
|
| 13580 |
|
|
DD1_un1_pc_prectl_1_0_a4[5] = FB1_res_7_0_0_5 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13581 |
|
|
|
| 13582 |
|
|
|
| 13583 |
|
|
--DD1_pc_next_0_iv_1_a[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[6]
|
| 13584 |
|
|
--operation mode is normal
|
| 13585 |
|
|
|
| 13586 |
|
|
DD1_pc_next_0_iv_1_a[6] = SD1_r32_o_6 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_6 # !SD1_r32_o_6 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_6;
|
| 13587 |
|
|
|
| 13588 |
|
|
|
| 13589 |
|
|
--PB1_dout_iv_6 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_6
|
| 13590 |
|
|
--operation mode is normal
|
| 13591 |
|
|
|
| 13592 |
|
|
PB1_dout_iv_6 = HD1_dout_iv_1_6 # FD1_wb_o_6 & HD1_dout7_0_a2;
|
| 13593 |
|
|
|
| 13594 |
|
|
--PB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_6
|
| 13595 |
|
|
--operation mode is normal
|
| 13596 |
|
|
|
| 13597 |
|
|
PB1_r32_o_6 = DFFEAS(PB1_dout_iv_6, E1__clk0, VCC, , , , , , );
|
| 13598 |
|
|
|
| 13599 |
|
|
|
| 13600 |
|
|
--DD1_un1_pc_prectl_1_0_a4[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[6]
|
| 13601 |
|
|
--operation mode is normal
|
| 13602 |
|
|
|
| 13603 |
|
|
DD1_un1_pc_prectl_1_0_a4[6] = FB1_res_7_0_0_6 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13604 |
|
|
|
| 13605 |
|
|
|
| 13606 |
|
|
--DD1_pc_next_0_iv_1_a[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[7]
|
| 13607 |
|
|
--operation mode is normal
|
| 13608 |
|
|
|
| 13609 |
|
|
DD1_pc_next_0_iv_1_a[7] = SD1_r32_o_7 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_7 # !SD1_r32_o_7 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_7;
|
| 13610 |
|
|
|
| 13611 |
|
|
|
| 13612 |
|
|
--PB1_dout_iv_7 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_7
|
| 13613 |
|
|
--operation mode is normal
|
| 13614 |
|
|
|
| 13615 |
|
|
PB1_dout_iv_7 = HD1_dout_iv_1_7 # FD1_wb_o_7 & HD1_dout7_0_a2;
|
| 13616 |
|
|
|
| 13617 |
|
|
--PB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_7
|
| 13618 |
|
|
--operation mode is normal
|
| 13619 |
|
|
|
| 13620 |
|
|
PB1_r32_o_7 = DFFEAS(PB1_dout_iv_7, E1__clk0, VCC, , , , , , );
|
| 13621 |
|
|
|
| 13622 |
|
|
|
| 13623 |
|
|
--DD1_un1_pc_prectl_1_0_a4[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[7]
|
| 13624 |
|
|
--operation mode is normal
|
| 13625 |
|
|
|
| 13626 |
|
|
DD1_un1_pc_prectl_1_0_a4[7] = FB1_res_7_0_0_7 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13627 |
|
|
|
| 13628 |
|
|
|
| 13629 |
|
|
--DD1_pc_next_0_iv_1_a[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[8]
|
| 13630 |
|
|
--operation mode is normal
|
| 13631 |
|
|
|
| 13632 |
|
|
DD1_pc_next_0_iv_1_a[8] = SD1_r32_o_8 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_8 # !SD1_r32_o_8 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_8;
|
| 13633 |
|
|
|
| 13634 |
|
|
|
| 13635 |
|
|
--PB1_dout_iv_8 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_8
|
| 13636 |
|
|
--operation mode is normal
|
| 13637 |
|
|
|
| 13638 |
|
|
PB1_dout_iv_8 = HD1_dout_iv_1_8 # FD1_wb_o_8 & HD1_dout7_0_a2;
|
| 13639 |
|
|
|
| 13640 |
|
|
--PB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_8
|
| 13641 |
|
|
--operation mode is normal
|
| 13642 |
|
|
|
| 13643 |
|
|
PB1_r32_o_8 = DFFEAS(PB1_dout_iv_8, E1__clk0, VCC, , , , , , );
|
| 13644 |
|
|
|
| 13645 |
|
|
|
| 13646 |
|
|
--DD1_un1_pc_prectl_1_0_a4[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[8]
|
| 13647 |
|
|
--operation mode is normal
|
| 13648 |
|
|
|
| 13649 |
|
|
DD1_un1_pc_prectl_1_0_a4[8] = FB1_res_7_0_0_8 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13650 |
|
|
|
| 13651 |
|
|
|
| 13652 |
|
|
--DD1_pc_next_0_iv_1_a[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[9]
|
| 13653 |
|
|
--operation mode is normal
|
| 13654 |
|
|
|
| 13655 |
|
|
DD1_pc_next_0_iv_1_a[9] = SD1_r32_o_9 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_9 # !SD1_r32_o_9 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_9;
|
| 13656 |
|
|
|
| 13657 |
|
|
|
| 13658 |
|
|
--PB1_dout_iv_9 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_9
|
| 13659 |
|
|
--operation mode is normal
|
| 13660 |
|
|
|
| 13661 |
|
|
PB1_dout_iv_9 = HD1_dout_iv_1_9 # FD1_wb_o_9 & HD1_dout7_0_a2;
|
| 13662 |
|
|
|
| 13663 |
|
|
--PB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_9
|
| 13664 |
|
|
--operation mode is normal
|
| 13665 |
|
|
|
| 13666 |
|
|
PB1_r32_o_9 = DFFEAS(PB1_dout_iv_9, E1__clk0, VCC, , , , , , );
|
| 13667 |
|
|
|
| 13668 |
|
|
|
| 13669 |
|
|
--DD1_un1_pc_prectl_1_0_a4[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[9]
|
| 13670 |
|
|
--operation mode is normal
|
| 13671 |
|
|
|
| 13672 |
|
|
DD1_un1_pc_prectl_1_0_a4[9] = FB1_res_7_0_0_9 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13673 |
|
|
|
| 13674 |
|
|
|
| 13675 |
|
|
--DD1_pc_next_0_iv_1_a[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[10]
|
| 13676 |
|
|
--operation mode is normal
|
| 13677 |
|
|
|
| 13678 |
|
|
DD1_pc_next_0_iv_1_a[10] = SD1_r32_o_10 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_10 # !SD1_r32_o_10 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_10;
|
| 13679 |
|
|
|
| 13680 |
|
|
|
| 13681 |
|
|
--PB1_dout_iv_10 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_10
|
| 13682 |
|
|
--operation mode is normal
|
| 13683 |
|
|
|
| 13684 |
|
|
PB1_dout_iv_10 = HD1_dout_iv_1_10 # FD1_wb_o_10 & HD1_dout7_0_a2;
|
| 13685 |
|
|
|
| 13686 |
|
|
--PB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_10
|
| 13687 |
|
|
--operation mode is normal
|
| 13688 |
|
|
|
| 13689 |
|
|
PB1_r32_o_10 = DFFEAS(PB1_dout_iv_10, E1__clk0, VCC, , , , , , );
|
| 13690 |
|
|
|
| 13691 |
|
|
|
| 13692 |
|
|
--DD1_un1_pc_prectl_1_0_a4[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[10]
|
| 13693 |
|
|
--operation mode is normal
|
| 13694 |
|
|
|
| 13695 |
|
|
DD1_un1_pc_prectl_1_0_a4[10] = FB1_res_7_0_0_10 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13696 |
|
|
|
| 13697 |
|
|
|
| 13698 |
|
|
--DD1_pc_next_0_iv_1_a[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[11]
|
| 13699 |
|
|
--operation mode is normal
|
| 13700 |
|
|
|
| 13701 |
|
|
DD1_pc_next_0_iv_1_a[11] = SD1_r32_o_11 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_11 # !SD1_r32_o_11 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_11;
|
| 13702 |
|
|
|
| 13703 |
|
|
|
| 13704 |
|
|
--PB1_dout_iv_11 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_11
|
| 13705 |
|
|
--operation mode is normal
|
| 13706 |
|
|
|
| 13707 |
|
|
PB1_dout_iv_11 = HD1_dout_iv_1_11 # FD1_wb_o_11 & HD1_dout7_0_a2;
|
| 13708 |
|
|
|
| 13709 |
|
|
--PB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_11
|
| 13710 |
|
|
--operation mode is normal
|
| 13711 |
|
|
|
| 13712 |
|
|
PB1_r32_o_11 = DFFEAS(PB1_dout_iv_11, E1__clk0, VCC, , , , , , );
|
| 13713 |
|
|
|
| 13714 |
|
|
|
| 13715 |
|
|
--DD1_un1_pc_prectl_1_0_a4[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[11]
|
| 13716 |
|
|
--operation mode is normal
|
| 13717 |
|
|
|
| 13718 |
|
|
DD1_un1_pc_prectl_1_0_a4[11] = FB1_res_7_0_0_11 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13719 |
|
|
|
| 13720 |
|
|
|
| 13721 |
|
|
--DD1_pc_next_0_iv_1_a[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[12]
|
| 13722 |
|
|
--operation mode is normal
|
| 13723 |
|
|
|
| 13724 |
|
|
DD1_pc_next_0_iv_1_a[12] = SD1_r32_o_12 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_12 # !SD1_r32_o_12 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_12;
|
| 13725 |
|
|
|
| 13726 |
|
|
|
| 13727 |
|
|
--PB1_dout_iv_12 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_12
|
| 13728 |
|
|
--operation mode is normal
|
| 13729 |
|
|
|
| 13730 |
|
|
PB1_dout_iv_12 = HD1_dout_iv_1_12 # FD1_wb_o_12 & HD1_dout7_0_a2;
|
| 13731 |
|
|
|
| 13732 |
|
|
--PB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_12
|
| 13733 |
|
|
--operation mode is normal
|
| 13734 |
|
|
|
| 13735 |
|
|
PB1_r32_o_12 = DFFEAS(PB1_dout_iv_12, E1__clk0, VCC, , , , , , );
|
| 13736 |
|
|
|
| 13737 |
|
|
|
| 13738 |
|
|
--DD1_un1_pc_prectl_1_0_a4[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[12]
|
| 13739 |
|
|
--operation mode is normal
|
| 13740 |
|
|
|
| 13741 |
|
|
DD1_un1_pc_prectl_1_0_a4[12] = FB1_res_7_0_0_12 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13742 |
|
|
|
| 13743 |
|
|
|
| 13744 |
|
|
--CB1_dout_2_23 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_23
|
| 13745 |
|
|
--operation mode is normal
|
| 13746 |
|
|
|
| 13747 |
|
|
CB1_dout_2_23 = ND1_dout7 & FD1_wb_o_23 # !ND1_dout7 & !ND1_dout_2_a_23;
|
| 13748 |
|
|
|
| 13749 |
|
|
--CB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_23
|
| 13750 |
|
|
--operation mode is normal
|
| 13751 |
|
|
|
| 13752 |
|
|
CB1_r32_o_23 = DFFEAS(CB1_dout_2_23, E1__clk0, VCC, , , , , , );
|
| 13753 |
|
|
|
| 13754 |
|
|
|
| 13755 |
|
|
--TB1_dout_1_x_7 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_7
|
| 13756 |
|
|
--operation mode is normal
|
| 13757 |
|
|
|
| 13758 |
|
|
TB1_dout_1_x_7 = TB1_dout21 & CB1_dout_2_7 # !TB1_dout21 & CB1_dout_2_15;
|
| 13759 |
|
|
|
| 13760 |
|
|
|
| 13761 |
|
|
--TB1_dout_1_2_7 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_7
|
| 13762 |
|
|
--operation mode is normal
|
| 13763 |
|
|
|
| 13764 |
|
|
TB1_dout_1_2_7 = TB1_dout22 & !TB1_dout_1_2_a_x[31] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_7 # !TB1_dout21 & !TB1_dout_1_2_a_x[31];
|
| 13765 |
|
|
|
| 13766 |
|
|
|
| 13767 |
|
|
--YB1_wb_mux_1_0_0_a3[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_mux_1_0_0_a3[0]
|
| 13768 |
|
|
--operation mode is normal
|
| 13769 |
|
|
|
| 13770 |
|
|
YB1_wb_mux_1_0_0_a3[0] = !KE1_q_a[5] & !KE1_q_a[6] & KE1_q_a[7] & YB1_wb_mux_1_0_0_a3_a_x[0];
|
| 13771 |
|
|
|
| 13772 |
|
|
|
| 13773 |
|
|
--GD1_dout_iv_1_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_9
|
| 13774 |
|
|
--operation mode is normal
|
| 13775 |
|
|
|
| 13776 |
|
|
GD1_dout_iv_1_9 = FD1_N_20_i_0_s3 & LD1_q_b[9] # !GD1_dout_iv_1_a[9];
|
| 13777 |
|
|
|
| 13778 |
|
|
|
| 13779 |
|
|
--ED1_r32_o_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_9
|
| 13780 |
|
|
--operation mode is normal
|
| 13781 |
|
|
|
| 13782 |
|
|
ED1_r32_o_9_lut_out = HE1_q_a[1];
|
| 13783 |
|
|
ED1_r32_o_9 = DFFEAS(ED1_r32_o_9_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 13784 |
|
|
|
| 13785 |
|
|
|
| 13786 |
|
|
--F1_dout_9 is mips_sys:isys|mips_dvc:imips_dvc|dout_9
|
| 13787 |
|
|
--operation mode is normal
|
| 13788 |
|
|
|
| 13789 |
|
|
F1_dout_9_lut_out = K1_cntr_9 & F1_dout_0_0_a3_4[0] # F1_cmd[9] & F1_dout_0_0_a3_3[0] # !K1_cntr_9 & F1_cmd[9] & F1_dout_0_0_a3_3[0];
|
| 13790 |
|
|
F1_dout_9 = DFFEAS(F1_dout_9_lut_out, E1__clk0, VCC, , , , , , );
|
| 13791 |
|
|
|
| 13792 |
|
|
|
| 13793 |
|
|
--DB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_9
|
| 13794 |
|
|
--operation mode is normal
|
| 13795 |
|
|
|
| 13796 |
|
|
DB1_r32_o_9_lut_out = WB41L1;
|
| 13797 |
|
|
DB1_r32_o_9 = DFFEAS(DB1_r32_o_9_lut_out, E1__clk0, VCC, , , , , , );
|
| 13798 |
|
|
|
| 13799 |
|
|
|
| 13800 |
|
|
--BB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_9
|
| 13801 |
|
|
--operation mode is normal
|
| 13802 |
|
|
|
| 13803 |
|
|
BB1_r32_o_9_lut_out = AB1_r32_o_7;
|
| 13804 |
|
|
BB1_r32_o_9 = DFFEAS(BB1_r32_o_9_lut_out, E1__clk0, VCC, , , , , , );
|
| 13805 |
|
|
|
| 13806 |
|
|
|
| 13807 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[11] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[11]
|
| 13808 |
|
|
--operation mode is normal
|
| 13809 |
|
|
|
| 13810 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[11] = QB1_r32_o_11 & !FB1_r32_o_0_11 & QD1_b_o18 # !QB1_r32_o_11 & QD1_un1_b_o18_2 # !FB1_r32_o_0_11 & QD1_b_o18;
|
| 13811 |
|
|
|
| 13812 |
|
|
|
| 13813 |
|
|
--G1_BUS15471_i_m[11] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[11]
|
| 13814 |
|
|
--operation mode is normal
|
| 13815 |
|
|
|
| 13816 |
|
|
G1_BUS15471_i_m[11] = !FD1_wb_o_11 & QD1_b_o_1_sqmuxa;
|
| 13817 |
|
|
|
| 13818 |
|
|
|
| 13819 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[13] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[13]
|
| 13820 |
|
|
--operation mode is normal
|
| 13821 |
|
|
|
| 13822 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[13] = QB1_r32_o_13 & !FB1_r32_o_0_13 & QD1_b_o18 # !QB1_r32_o_13 & QD1_un1_b_o18_2 # !FB1_r32_o_0_13 & QD1_b_o18;
|
| 13823 |
|
|
|
| 13824 |
|
|
|
| 13825 |
|
|
--G1_BUS15471_i_m[13] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[13]
|
| 13826 |
|
|
--operation mode is normal
|
| 13827 |
|
|
|
| 13828 |
|
|
G1_BUS15471_i_m[13] = !FD1_wb_o_13 & QD1_b_o_1_sqmuxa;
|
| 13829 |
|
|
|
| 13830 |
|
|
|
| 13831 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[12] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[12]
|
| 13832 |
|
|
--operation mode is normal
|
| 13833 |
|
|
|
| 13834 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[12] = QB1_r32_o_12 & !FB1_r32_o_0_12 & QD1_b_o18 # !QB1_r32_o_12 & QD1_un1_b_o18_2 # !FB1_r32_o_0_12 & QD1_b_o18;
|
| 13835 |
|
|
|
| 13836 |
|
|
|
| 13837 |
|
|
--G1_BUS15471_i_m[12] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[12]
|
| 13838 |
|
|
--operation mode is normal
|
| 13839 |
|
|
|
| 13840 |
|
|
G1_BUS15471_i_m[12] = !FD1_wb_o_12 & QD1_b_o_1_sqmuxa;
|
| 13841 |
|
|
|
| 13842 |
|
|
|
| 13843 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[14] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[14]
|
| 13844 |
|
|
--operation mode is normal
|
| 13845 |
|
|
|
| 13846 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[14] = QB1_r32_o_14 & !FB1_r32_o_0_14 & QD1_b_o18 # !QB1_r32_o_14 & QD1_un1_b_o18_2 # !FB1_r32_o_0_14 & QD1_b_o18;
|
| 13847 |
|
|
|
| 13848 |
|
|
|
| 13849 |
|
|
--G1_BUS15471_i_m[14] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[14]
|
| 13850 |
|
|
--operation mode is normal
|
| 13851 |
|
|
|
| 13852 |
|
|
G1_BUS15471_i_m[14] = !FD1_wb_o_14 & QD1_b_o_1_sqmuxa;
|
| 13853 |
|
|
|
| 13854 |
|
|
|
| 13855 |
|
|
--ED1_r32_o_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_8
|
| 13856 |
|
|
--operation mode is normal
|
| 13857 |
|
|
|
| 13858 |
|
|
ED1_r32_o_8_lut_out = HE1_q_a[0];
|
| 13859 |
|
|
ED1_r32_o_8 = DFFEAS(ED1_r32_o_8_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 13860 |
|
|
|
| 13861 |
|
|
|
| 13862 |
|
|
--DD1_pc_next_0_iv_1_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[1]
|
| 13863 |
|
|
--operation mode is normal
|
| 13864 |
|
|
|
| 13865 |
|
|
DD1_pc_next_0_iv_1_a[1] = SD1_r32_o_1 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_1 # !SD1_r32_o_1 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_1;
|
| 13866 |
|
|
|
| 13867 |
|
|
|
| 13868 |
|
|
--PB1_dout_iv_1 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_1
|
| 13869 |
|
|
--operation mode is normal
|
| 13870 |
|
|
|
| 13871 |
|
|
PB1_dout_iv_1 = HD1_dout_iv_1_1 # FD1_wb_o_1 & HD1_dout7_0_a2;
|
| 13872 |
|
|
|
| 13873 |
|
|
--PB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_1
|
| 13874 |
|
|
--operation mode is normal
|
| 13875 |
|
|
|
| 13876 |
|
|
PB1_r32_o_1 = DFFEAS(PB1_dout_iv_1, E1__clk0, VCC, , , , , , );
|
| 13877 |
|
|
|
| 13878 |
|
|
|
| 13879 |
|
|
--DD1_un1_pc_prectl_1_0_a4[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[1]
|
| 13880 |
|
|
--operation mode is normal
|
| 13881 |
|
|
|
| 13882 |
|
|
DD1_un1_pc_prectl_1_0_a4[1] = FB1_res_7_0_0_1 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13883 |
|
|
|
| 13884 |
|
|
|
| 13885 |
|
|
--DD1_pc_next_0_iv_1_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[0]
|
| 13886 |
|
|
--operation mode is normal
|
| 13887 |
|
|
|
| 13888 |
|
|
DD1_pc_next_0_iv_1_a[0] = SD1_r32_o_0 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_0_d0 # !SD1_r32_o_0 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_0_d0;
|
| 13889 |
|
|
|
| 13890 |
|
|
|
| 13891 |
|
|
--PB1_dout_iv_0 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_0
|
| 13892 |
|
|
--operation mode is normal
|
| 13893 |
|
|
|
| 13894 |
|
|
PB1_dout_iv_0 = HD1_dout_iv_1_0 # FD1_wb_o_0 & HD1_dout7_0_a2;
|
| 13895 |
|
|
|
| 13896 |
|
|
--PB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_0
|
| 13897 |
|
|
--operation mode is normal
|
| 13898 |
|
|
|
| 13899 |
|
|
PB1_r32_o_0 = DFFEAS(PB1_dout_iv_0, E1__clk0, VCC, , , , , , );
|
| 13900 |
|
|
|
| 13901 |
|
|
|
| 13902 |
|
|
--DD1_un1_pc_prectl_1_0_a4[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[0]
|
| 13903 |
|
|
--operation mode is normal
|
| 13904 |
|
|
|
| 13905 |
|
|
DD1_un1_pc_prectl_1_0_a4[0] = FB1_res_7_0_0_0_d0 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 13906 |
|
|
|
| 13907 |
|
|
|
| 13908 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[21] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[21]
|
| 13909 |
|
|
--operation mode is normal
|
| 13910 |
|
|
|
| 13911 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[21] = QB1_r32_o_21 & !FB1_r32_o_21 & QD1_b_o18 # !QB1_r32_o_21 & QD1_un1_b_o18_2 # !FB1_r32_o_21 & QD1_b_o18;
|
| 13912 |
|
|
|
| 13913 |
|
|
|
| 13914 |
|
|
--G1_BUS15471_i_m[21] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[21]
|
| 13915 |
|
|
--operation mode is normal
|
| 13916 |
|
|
|
| 13917 |
|
|
G1_BUS15471_i_m[21] = !FD1_wb_o_21 & QD1_b_o_1_sqmuxa;
|
| 13918 |
|
|
|
| 13919 |
|
|
|
| 13920 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[22] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[22]
|
| 13921 |
|
|
--operation mode is normal
|
| 13922 |
|
|
|
| 13923 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[22] = QB1_r32_o_22 & !FB1_r32_o_22 & QD1_b_o18 # !QB1_r32_o_22 & QD1_un1_b_o18_2 # !FB1_r32_o_22 & QD1_b_o18;
|
| 13924 |
|
|
|
| 13925 |
|
|
|
| 13926 |
|
|
--G1_BUS15471_i_m[22] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[22]
|
| 13927 |
|
|
--operation mode is normal
|
| 13928 |
|
|
|
| 13929 |
|
|
G1_BUS15471_i_m[22] = !FD1_wb_o_22 & QD1_b_o_1_sqmuxa;
|
| 13930 |
|
|
|
| 13931 |
|
|
|
| 13932 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[25] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[25]
|
| 13933 |
|
|
--operation mode is normal
|
| 13934 |
|
|
|
| 13935 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[25] = QB1_r32_o_25 & !FB1_r32_o_25 & QD1_b_o18 # !QB1_r32_o_25 & QD1_un1_b_o18_2 # !FB1_r32_o_25 & QD1_b_o18;
|
| 13936 |
|
|
|
| 13937 |
|
|
|
| 13938 |
|
|
--G1_BUS15471_i_m[25] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[25]
|
| 13939 |
|
|
--operation mode is normal
|
| 13940 |
|
|
|
| 13941 |
|
|
G1_BUS15471_i_m[25] = !FD1_wb_o_25 & QD1_b_o_1_sqmuxa;
|
| 13942 |
|
|
|
| 13943 |
|
|
|
| 13944 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[26] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[26]
|
| 13945 |
|
|
--operation mode is normal
|
| 13946 |
|
|
|
| 13947 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[26] = QB1_r32_o_26 & !FB1_r32_o_26 & QD1_b_o18 # !QB1_r32_o_26 & QD1_un1_b_o18_2 # !FB1_r32_o_26 & QD1_b_o18;
|
| 13948 |
|
|
|
| 13949 |
|
|
|
| 13950 |
|
|
--G1_BUS15471_i_m[26] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[26]
|
| 13951 |
|
|
--operation mode is normal
|
| 13952 |
|
|
|
| 13953 |
|
|
G1_BUS15471_i_m[26] = !FD1_wb_o_26 & QD1_b_o_1_sqmuxa;
|
| 13954 |
|
|
|
| 13955 |
|
|
|
| 13956 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[29] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[29]
|
| 13957 |
|
|
--operation mode is normal
|
| 13958 |
|
|
|
| 13959 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[29] = QB1_r32_o_29 & !FB1_r32_o_29 & QD1_b_o18 # !QB1_r32_o_29 & QD1_un1_b_o18_2 # !FB1_r32_o_29 & QD1_b_o18;
|
| 13960 |
|
|
|
| 13961 |
|
|
|
| 13962 |
|
|
--G1_BUS15471_i_m[29] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[29]
|
| 13963 |
|
|
--operation mode is normal
|
| 13964 |
|
|
|
| 13965 |
|
|
G1_BUS15471_i_m[29] = !FD1_wb_o_29 & QD1_b_o_1_sqmuxa;
|
| 13966 |
|
|
|
| 13967 |
|
|
|
| 13968 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[17] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[17]
|
| 13969 |
|
|
--operation mode is normal
|
| 13970 |
|
|
|
| 13971 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[17] = QB1_r32_o_17 & !FB1_r32_o_17 & QD1_b_o18 # !QB1_r32_o_17 & QD1_un1_b_o18_2 # !FB1_r32_o_17 & QD1_b_o18;
|
| 13972 |
|
|
|
| 13973 |
|
|
|
| 13974 |
|
|
--G1_BUS15471_i_m[17] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[17]
|
| 13975 |
|
|
--operation mode is normal
|
| 13976 |
|
|
|
| 13977 |
|
|
G1_BUS15471_i_m[17] = !FD1_wb_o_17 & QD1_b_o_1_sqmuxa;
|
| 13978 |
|
|
|
| 13979 |
|
|
|
| 13980 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[18] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[18]
|
| 13981 |
|
|
--operation mode is normal
|
| 13982 |
|
|
|
| 13983 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[18] = QB1_r32_o_18 & !FB1_r32_o_18 & QD1_b_o18 # !QB1_r32_o_18 & QD1_un1_b_o18_2 # !FB1_r32_o_18 & QD1_b_o18;
|
| 13984 |
|
|
|
| 13985 |
|
|
|
| 13986 |
|
|
--G1_BUS15471_i_m[18] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[18]
|
| 13987 |
|
|
--operation mode is normal
|
| 13988 |
|
|
|
| 13989 |
|
|
G1_BUS15471_i_m[18] = !FD1_wb_o_18 & QD1_b_o_1_sqmuxa;
|
| 13990 |
|
|
|
| 13991 |
|
|
|
| 13992 |
|
|
--VD1_hilo_37_iv_0[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[8]
|
| 13993 |
|
|
--operation mode is normal
|
| 13994 |
|
|
|
| 13995 |
|
|
VD1_hilo_37_iv_0[8] = VD1_hilo_9 & VD1_hilo_1_sqmuxa_1 # VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[8] # !VD1_hilo_9 & VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[8];
|
| 13996 |
|
|
|
| 13997 |
|
|
|
| 13998 |
|
|
--VD1_hilo_8_Z[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[8]
|
| 13999 |
|
|
--operation mode is normal
|
| 14000 |
|
|
|
| 14001 |
|
|
VD1_hilo_8_Z[8] = RC1_alu_func_o_0 & VD1_hilo_8 # !RC1_alu_func_o_0 & PD1_a_o_8;
|
| 14002 |
|
|
|
| 14003 |
|
|
|
| 14004 |
|
|
--VD1_hilo_37_iv_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[8]
|
| 14005 |
|
|
--operation mode is normal
|
| 14006 |
|
|
|
| 14007 |
|
|
VD1_hilo_37_iv_a[8] = VD1_hilo_7 & !VD1_hilo_2_sqmuxa & !PD1_a_o_8 # !VD1_addnop2109_0_a2 # !VD1_hilo_7 & !PD1_a_o_8 # !VD1_addnop2109_0_a2;
|
| 14008 |
|
|
|
| 14009 |
|
|
|
| 14010 |
|
|
--VD1_finish is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|finish
|
| 14011 |
|
|
--operation mode is normal
|
| 14012 |
|
|
|
| 14013 |
|
|
VD1_finish_lut_out = !VD1_rdy;
|
| 14014 |
|
|
VD1_finish = DFFEAS(VD1_finish_lut_out, E1__clk0, VCC, , VD1_finish_0_sqmuxa_i, , , !sys_rst, );
|
| 14015 |
|
|
|
| 14016 |
|
|
|
| 14017 |
|
|
--VD1_un134_hilo_combout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[7]
|
| 14018 |
|
|
--operation mode is arithmetic
|
| 14019 |
|
|
|
| 14020 |
|
|
VD1_un134_hilo_combout[7]_carry_eqn = VD1_un134_hilo_cout[5];
|
| 14021 |
|
|
VD1_un134_hilo_combout[7] = VD1_hilo_7 $ (VD1_hilo_6 & VD1_un134_hilo_combout[7]_carry_eqn);
|
| 14022 |
|
|
|
| 14023 |
|
|
--VD1_un134_hilo_cout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[7]
|
| 14024 |
|
|
--operation mode is arithmetic
|
| 14025 |
|
|
|
| 14026 |
|
|
VD1_un134_hilo_cout[7] = CARRY(!VD1_un134_hilo_cout[5] # !VD1_hilo_7 # !VD1_hilo_6);
|
| 14027 |
|
|
|
| 14028 |
|
|
|
| 14029 |
|
|
--VD1_hilo_37_iv_0_a6_3[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a6_3[40]
|
| 14030 |
|
|
--operation mode is normal
|
| 14031 |
|
|
|
| 14032 |
|
|
VD1_hilo_37_iv_0_a6_3[40] = !VD1_sub_or_yn & VD1_hilo_37_iv_0_a2_7_2_1[37] & VD1_hilo_1_sqmuxa_1 & !VD1_un50_hilo_add9;
|
| 14033 |
|
|
|
| 14034 |
|
|
|
| 14035 |
|
|
--VD1_hilo_37_iv_0_5[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[40]
|
| 14036 |
|
|
--operation mode is normal
|
| 14037 |
|
|
|
| 14038 |
|
|
VD1_hilo_37_iv_0_5[40] = VD1_hilo_37_iv_0_1[40] # VD1_hilo_37_iv_0_5_a[40] # !VD1_un59_hilo_add9 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 14039 |
|
|
|
| 14040 |
|
|
|
| 14041 |
|
|
--VD1_hilo_37_iv_0_a[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[40]
|
| 14042 |
|
|
--operation mode is normal
|
| 14043 |
|
|
|
| 14044 |
|
|
VD1_hilo_37_iv_0_a[40] = VD1_hilo_41 & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_8 # !VD1_hilo_41 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_8;
|
| 14045 |
|
|
|
| 14046 |
|
|
|
| 14047 |
|
|
--VD1_nop2_reged[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[8]
|
| 14048 |
|
|
--operation mode is arithmetic
|
| 14049 |
|
|
|
| 14050 |
|
|
VD1_nop2_reged[8]_carry_eqn = VD1_nop2_reged_cout[6];
|
| 14051 |
|
|
VD1_nop2_reged[8] = VD1_op2_reged[8] $ VD1_nop2_reged[8]_carry_eqn;
|
| 14052 |
|
|
|
| 14053 |
|
|
--VD1_nop2_reged_cout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[8]
|
| 14054 |
|
|
--operation mode is arithmetic
|
| 14055 |
|
|
|
| 14056 |
|
|
VD1_nop2_reged_cout[8] = CARRY(!VD1_op2_reged[9] & !VD1_op2_reged[8] & !VD1_nop2_reged_cout[6]);
|
| 14057 |
|
|
|
| 14058 |
|
|
|
| 14059 |
|
|
--VD1_un50_hilo_add7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add7
|
| 14060 |
|
|
--operation mode is arithmetic
|
| 14061 |
|
|
|
| 14062 |
|
|
VD1_un50_hilo_add7_carry_eqn = VD1_un50_hilo_carry_6;
|
| 14063 |
|
|
VD1_un50_hilo_add7 = VD1_hilo_39 $ VD1_nop2_reged[7] $ VD1_un50_hilo_add7_carry_eqn;
|
| 14064 |
|
|
|
| 14065 |
|
|
--VD1_un50_hilo_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_7
|
| 14066 |
|
|
--operation mode is arithmetic
|
| 14067 |
|
|
|
| 14068 |
|
|
VD1_un50_hilo_carry_7 = CARRY(VD1_hilo_39 & !VD1_nop2_reged[7] & !VD1_un50_hilo_carry_6 # !VD1_hilo_39 & !VD1_un50_hilo_carry_6 # !VD1_nop2_reged[7]);
|
| 14069 |
|
|
|
| 14070 |
|
|
|
| 14071 |
|
|
--VD1_un59_hilo_add7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add7
|
| 14072 |
|
|
--operation mode is arithmetic
|
| 14073 |
|
|
|
| 14074 |
|
|
VD1_un59_hilo_add7_carry_eqn = VD1_un59_hilo_carry_6;
|
| 14075 |
|
|
VD1_un59_hilo_add7 = VD1_hilo_39 $ VD1_op2_reged[7] $ VD1_un59_hilo_add7_carry_eqn;
|
| 14076 |
|
|
|
| 14077 |
|
|
--VD1_un59_hilo_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_7
|
| 14078 |
|
|
--operation mode is arithmetic
|
| 14079 |
|
|
|
| 14080 |
|
|
VD1_un59_hilo_carry_7 = CARRY(VD1_hilo_39 & !VD1_op2_reged[7] & !VD1_un59_hilo_carry_6 # !VD1_hilo_39 & !VD1_un59_hilo_carry_6 # !VD1_op2_reged[7]);
|
| 14081 |
|
|
|
| 14082 |
|
|
|
| 14083 |
|
|
--VD1_hilo_37_iv_0_a2_0[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_0[38]
|
| 14084 |
|
|
--operation mode is normal
|
| 14085 |
|
|
|
| 14086 |
|
|
VD1_hilo_37_iv_0_a2_0[38] = !RC1_alu_func_o_0 & VD1_addnop2109_0_a2;
|
| 14087 |
|
|
|
| 14088 |
|
|
|
| 14089 |
|
|
--VD1_hilo_37_iv_0_a2_1[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_1[39]
|
| 14090 |
|
|
--operation mode is normal
|
| 14091 |
|
|
|
| 14092 |
|
|
VD1_hilo_37_iv_0_a2_1[39] = !VD1_hilo_7 & VD1_hilo_0_sqmuxa;
|
| 14093 |
|
|
|
| 14094 |
|
|
|
| 14095 |
|
|
--VD1_hilo_37_iv_0_a3_2[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_2[62]
|
| 14096 |
|
|
--operation mode is normal
|
| 14097 |
|
|
|
| 14098 |
|
|
VD1_hilo_37_iv_0_a3_2[62] = VD1_addop2 & !VD1_addnop2 & VD1_hilo_3_sqmuxa;
|
| 14099 |
|
|
|
| 14100 |
|
|
|
| 14101 |
|
|
--VD1_hilo_37_iv_0_o3_2[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_2[34]
|
| 14102 |
|
|
--operation mode is normal
|
| 14103 |
|
|
|
| 14104 |
|
|
VD1_hilo_37_iv_0_o3_2[34] = VD1_hilo_37_iv_0_a3_1[62] # !VD1_hilo_33_1[64] & VD1_hilo_3_sqmuxa;
|
| 14105 |
|
|
|
| 14106 |
|
|
|
| 14107 |
|
|
--VD1_un1_op2_reged_1_combout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[7]
|
| 14108 |
|
|
--operation mode is normal
|
| 14109 |
|
|
|
| 14110 |
|
|
VD1_un1_op2_reged_1_combout[7] = VD1_eqop2_2_32 & VD1_op2_reged[7] # !VD1_eqop2_2_32 & VD1_nop2_reged[7];
|
| 14111 |
|
|
|
| 14112 |
|
|
|
| 14113 |
|
|
--VD1_hilo_24_add6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add6
|
| 14114 |
|
|
--operation mode is arithmetic
|
| 14115 |
|
|
|
| 14116 |
|
|
VD1_hilo_24_add6_carry_eqn = VD1_hilo_24_carry_5;
|
| 14117 |
|
|
VD1_hilo_24_add6 = VD1_hilo_37 $ VD1_un1_op2_reged_1_combout[6] $ !VD1_hilo_24_add6_carry_eqn;
|
| 14118 |
|
|
|
| 14119 |
|
|
--VD1_hilo_24_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_6
|
| 14120 |
|
|
--operation mode is arithmetic
|
| 14121 |
|
|
|
| 14122 |
|
|
VD1_hilo_24_carry_6 = CARRY(VD1_hilo_37 & VD1_un1_op2_reged_1_combout[6] # !VD1_hilo_24_carry_5 # !VD1_hilo_37 & VD1_un1_op2_reged_1_combout[6] & !VD1_hilo_24_carry_5);
|
| 14123 |
|
|
|
| 14124 |
|
|
|
| 14125 |
|
|
--PD1_a_o_3_d_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[7]
|
| 14126 |
|
|
--operation mode is normal
|
| 14127 |
|
|
|
| 14128 |
|
|
PD1_a_o_3_d_a[7] = PD1_a_o_sn_m2 & !PB1_r32_o_7 # !PD1_a_o_sn_m2 & !AB1_r32_o_5;
|
| 14129 |
|
|
|
| 14130 |
|
|
|
| 14131 |
|
|
--YB1_rd_sel_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_0
|
| 14132 |
|
|
--operation mode is normal
|
| 14133 |
|
|
|
| 14134 |
|
|
YB1_rd_sel_2_0_0_0 = YB1_alu_func_2_0_0_a3_1[1] # WB36L1 & YB1_alu_func_2_0_0_a2_3[1] # !YB1_rd_sel_2_0_0_a[0];
|
| 14135 |
|
|
|
| 14136 |
|
|
|
| 14137 |
|
|
--WB36L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:rd_sel_1_0_|lpm_latch:U1|q[0]~56
|
| 14138 |
|
|
--operation mode is normal
|
| 14139 |
|
|
|
| 14140 |
|
|
WB36L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_rd_sel_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB36L1;
|
| 14141 |
|
|
|
| 14142 |
|
|
|
| 14143 |
|
|
--YB1_rd_sel_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_1
|
| 14144 |
|
|
--operation mode is normal
|
| 14145 |
|
|
|
| 14146 |
|
|
YB1_rd_sel_2_0_0_1 = YB1_rd_sel_2_0_0_0_Z[1] # WB46L2 & !KE1_q_a[7] & YB1_rd_sel_2_0_0_a[1];
|
| 14147 |
|
|
|
| 14148 |
|
|
|
| 14149 |
|
|
--WB46L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1|q[0]~68
|
| 14150 |
|
|
--operation mode is normal
|
| 14151 |
|
|
|
| 14152 |
|
|
WB46L1 = YB1_muxa_ctl373 # YB1_un1_muxa_ctl370_x & YB1_rd_sel_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB46L2;
|
| 14153 |
|
|
|
| 14154 |
|
|
|
| 14155 |
|
|
--WB46L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1|q[0]~69
|
| 14156 |
|
|
--operation mode is normal
|
| 14157 |
|
|
|
| 14158 |
|
|
WB46L2 = WB46L1 & !YB1_un1_ins_i_22_u_x;
|
| 14159 |
|
|
|
| 14160 |
|
|
|
| 14161 |
|
|
--YB1_wb_we_1_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_we_1_0_0_a[0]
|
| 14162 |
|
|
--operation mode is normal
|
| 14163 |
|
|
|
| 14164 |
|
|
YB1_wb_we_1_0_0_a[0] = !YB1_wb_mux_1_0_0_a3[0] & YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x # !KE1_q_a[5] # !KE1_q_a[4];
|
| 14165 |
|
|
|
| 14166 |
|
|
|
| 14167 |
|
|
--YB1_alu_we_1_0_0_0_Z[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_0_Z[0]
|
| 14168 |
|
|
--operation mode is normal
|
| 14169 |
|
|
|
| 14170 |
|
|
YB1_alu_we_1_0_0_0_Z[0] = YB1_alu_we_1_0_0_a3_1[0] # WB24L1 & !KE1_q_a[7] & YB1_rd_sel_2_0_0_a[1];
|
| 14171 |
|
|
|
| 14172 |
|
|
|
| 14173 |
|
|
--YB1_alu_we_1_0_0_a3[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3[0]
|
| 14174 |
|
|
--operation mode is normal
|
| 14175 |
|
|
|
| 14176 |
|
|
YB1_alu_we_1_0_0_a3[0] = !GE1_q_a[3] & YB1_alu_we_1_0_0_a3_a_x[0] & YB1_alu_func_2_i_m3_0_a2_0_x[2] # YB1_alu_func_2_0_0_a2_2_x[0];
|
| 14177 |
|
|
|
| 14178 |
|
|
|
| 14179 |
|
|
--FD1_wb_o_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_20
|
| 14180 |
|
|
--operation mode is normal
|
| 14181 |
|
|
|
| 14182 |
|
|
FD1_wb_o_20 = TC1_wb_mux_ctl_o_0 & F1_dout_20 # DB1_r32_o_20 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_20;
|
| 14183 |
|
|
|
| 14184 |
|
|
--FD1_r_data_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_20
|
| 14185 |
|
|
--operation mode is normal
|
| 14186 |
|
|
|
| 14187 |
|
|
FD1_r_data_20 = DFFEAS(FD1_wb_o_20, E1__clk0, VCC, , , , , , );
|
| 14188 |
|
|
|
| 14189 |
|
|
|
| 14190 |
|
|
--ND1_dout_2_a_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_20
|
| 14191 |
|
|
--operation mode is normal
|
| 14192 |
|
|
|
| 14193 |
|
|
ND1_dout_2_a_20 = XD1_mux_fw_1 & !AB1_r32_o_18 # !XD1_mux_fw_1 & !QB1_r32_o_20;
|
| 14194 |
|
|
|
| 14195 |
|
|
|
| 14196 |
|
|
--AD1_delay_counter_Sreg0[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[0]
|
| 14197 |
|
|
--operation mode is normal
|
| 14198 |
|
|
|
| 14199 |
|
|
AD1_delay_counter_Sreg0[0]_lut_out = WB76L1;
|
| 14200 |
|
|
AD1_delay_counter_Sreg0[0] = DFFEAS(AD1_delay_counter_Sreg0[0]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 14201 |
|
|
|
| 14202 |
|
|
|
| 14203 |
|
|
--AD1_delay_counter_Sreg0[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[5]
|
| 14204 |
|
|
--operation mode is normal
|
| 14205 |
|
|
|
| 14206 |
|
|
AD1_delay_counter_Sreg0[5]_lut_out = WB27L1 # !sys_rst;
|
| 14207 |
|
|
AD1_delay_counter_Sreg0[5] = DFFEAS(AD1_delay_counter_Sreg0[5]_lut_out, E1__clk0, VCC, , , , , , );
|
| 14208 |
|
|
|
| 14209 |
|
|
|
| 14210 |
|
|
--AD1_un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0
|
| 14211 |
|
|
--operation mode is normal
|
| 14212 |
|
|
|
| 14213 |
|
|
AD1_un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0 = !AD1_delay_counter_Sreg0[1] & !AD1_delay_counter_Sreg0[2] & !AD1_delay_counter_Sreg0[3] & !AD1_delay_counter_Sreg0[4];
|
| 14214 |
|
|
|
| 14215 |
|
|
|
| 14216 |
|
|
--YB1_cmp_ctl_2_0_0_a2_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a2_0[0]
|
| 14217 |
|
|
--operation mode is normal
|
| 14218 |
|
|
|
| 14219 |
|
|
YB1_cmp_ctl_2_0_0_a2_0[0] = !KE1_q_a[2] & KE1_q_a[6] & KE1_q_a[1] # !YB1_fsm_dly_2_0_0_a2_0_a_x[2];
|
| 14220 |
|
|
|
| 14221 |
|
|
|
| 14222 |
|
|
--YB1_cmp_ctl_2_0_0_a2_1[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a2_1[0]
|
| 14223 |
|
|
--operation mode is normal
|
| 14224 |
|
|
|
| 14225 |
|
|
YB1_cmp_ctl_2_0_0_a2_1[0] = KE1_q_a[2] & YB1_alu_we_1s_1_o2_0_x[0] # JE1_q_a[0] & JE1_q_a[4];
|
| 14226 |
|
|
|
| 14227 |
|
|
|
| 14228 |
|
|
--YB1_fsm_dly_2_0_0_a2_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a2_x[2]
|
| 14229 |
|
|
--operation mode is normal
|
| 14230 |
|
|
|
| 14231 |
|
|
YB1_fsm_dly_2_0_0_a2_x[2] = !KE1_q_a[4] & !KE1_q_a[5] & !KE1_q_a[7];
|
| 14232 |
|
|
|
| 14233 |
|
|
|
| 14234 |
|
|
--YB1_alu_func_2_0_0_a2_2_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_2_x[1]
|
| 14235 |
|
|
--operation mode is normal
|
| 14236 |
|
|
|
| 14237 |
|
|
YB1_alu_func_2_0_0_a2_2_x[1] = !GE1_q_a[5] & GE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[3];
|
| 14238 |
|
|
|
| 14239 |
|
|
|
| 14240 |
|
|
--YB1_alu_func_2_0_0_a2_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_x[0]
|
| 14241 |
|
|
--operation mode is normal
|
| 14242 |
|
|
|
| 14243 |
|
|
YB1_alu_func_2_0_0_a2_x[0] = !GE1_q_a[3] & YB1_alu_func_2_0_0_a2_0[1];
|
| 14244 |
|
|
|
| 14245 |
|
|
|
| 14246 |
|
|
--YB1_alu_func_2_0_0_a2_1[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_1[4]
|
| 14247 |
|
|
--operation mode is normal
|
| 14248 |
|
|
|
| 14249 |
|
|
YB1_alu_func_2_0_0_a2_1[4] = GE1_q_a[1] & GE1_q_a[5] & !GE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[3];
|
| 14250 |
|
|
|
| 14251 |
|
|
|
| 14252 |
|
|
--YB1_alu_func_2_0_0_3_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_3_a[1]
|
| 14253 |
|
|
--operation mode is normal
|
| 14254 |
|
|
|
| 14255 |
|
|
YB1_alu_func_2_0_0_3_a[1] = !YB1_alu_func_2_0_0_1_Z[1] & !YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x # !KE1_q_a[5] # !KE1_q_a[4];
|
| 14256 |
|
|
|
| 14257 |
|
|
|
| 14258 |
|
|
--YB1_alu_func_2_0_0_a2_0_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_0_x[0]
|
| 14259 |
|
|
--operation mode is normal
|
| 14260 |
|
|
|
| 14261 |
|
|
YB1_alu_func_2_0_0_a2_0_x[0] = KE1_q_a[3] & KE1_q_a[2];
|
| 14262 |
|
|
|
| 14263 |
|
|
|
| 14264 |
|
|
--YB1_alu_func_2_0_0_a2_0_x[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_0_x[4]
|
| 14265 |
|
|
--operation mode is normal
|
| 14266 |
|
|
|
| 14267 |
|
|
YB1_alu_func_2_0_0_a2_0_x[4] = !JE1_q_a[7] & YB1_fsm_dly_2_0_0_a2_0[2];
|
| 14268 |
|
|
|
| 14269 |
|
|
|
| 14270 |
|
|
--YB1_un1_muxa_ctl370_6_a_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_6_a_x
|
| 14271 |
|
|
--operation mode is normal
|
| 14272 |
|
|
|
| 14273 |
|
|
YB1_un1_muxa_ctl370_6_a_x = !KE1_q_a[5] & KE1_q_a[7];
|
| 14274 |
|
|
|
| 14275 |
|
|
|
| 14276 |
|
|
--YB1_un1_muxa_ctl370_5_a is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_5_a
|
| 14277 |
|
|
--operation mode is normal
|
| 14278 |
|
|
|
| 14279 |
|
|
YB1_un1_muxa_ctl370_5_a = !KE1_q_a[3] & !KE1_q_a[4] & !KE1_q_a[5] # !KE1_q_a[7];
|
| 14280 |
|
|
|
| 14281 |
|
|
|
| 14282 |
|
|
--YB1_ext_ctl_2_0_0_a3_1_0[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a3_1_0[2]
|
| 14283 |
|
|
--operation mode is normal
|
| 14284 |
|
|
|
| 14285 |
|
|
YB1_ext_ctl_2_0_0_a3_1_0[2] = !KE1_q_a[3] & !KE1_q_a[5] & !KE1_q_a[7] & YB1_ext_ctl_2_0_0_o2[2];
|
| 14286 |
|
|
|
| 14287 |
|
|
|
| 14288 |
|
|
--YB1_ext_ctl_2_0_0_o3[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_o3[2]
|
| 14289 |
|
|
--operation mode is normal
|
| 14290 |
|
|
|
| 14291 |
|
|
YB1_ext_ctl_2_0_0_o3[2] = YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0] & YB1_cmp_ctl_2_0_0_a2_x[0] # YB1_ext_ctl_2_0_0_a2_0_x[2] & YB1_cmp_ctl_2_0_0_a2_x[2] # !YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0] & YB1_ext_ctl_2_0_0_a2_0_x[2] & YB1_cmp_ctl_2_0_0_a2_x[2];
|
| 14292 |
|
|
|
| 14293 |
|
|
|
| 14294 |
|
|
--YB1_fsm_dly_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a[0]
|
| 14295 |
|
|
--operation mode is normal
|
| 14296 |
|
|
|
| 14297 |
|
|
YB1_fsm_dly_2_0_0_a[0] = !YB1_alu_func_2_0_0_a2_2_x[0] # !YB1_ext_ctl_2_0_0_a2_0_x[2] # !YB1_pc_gen_ctl_2_0_0_a2_x[1] # !GE1_q_a[3];
|
| 14298 |
|
|
|
| 14299 |
|
|
|
| 14300 |
|
|
--YB1_fsm_dly_2_i_m3_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_i_m3_0_a[1]
|
| 14301 |
|
|
--operation mode is normal
|
| 14302 |
|
|
|
| 14303 |
|
|
YB1_fsm_dly_2_i_m3_0_a[1] = !KE1_q_a[3] & !YB1_cmp_ctl_2_0_0_a2_0[0] & !YB1_cmp_ctl_2_0_0_a2_1[0] # !WB45L1;
|
| 14304 |
|
|
|
| 14305 |
|
|
|
| 14306 |
|
|
--YB1_fsm_dly_2_0_0_a2_0[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a2_0[2]
|
| 14307 |
|
|
--operation mode is normal
|
| 14308 |
|
|
|
| 14309 |
|
|
YB1_fsm_dly_2_0_0_a2_0[2] = !KE1_q_a[2] & KE1_q_a[6] & !KE1_q_a[1] & YB1_fsm_dly_2_0_0_a2_0_a_x[2];
|
| 14310 |
|
|
|
| 14311 |
|
|
|
| 14312 |
|
|
--YB1_fsm_dly_2_0_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a[2]
|
| 14313 |
|
|
--operation mode is normal
|
| 14314 |
|
|
|
| 14315 |
|
|
YB1_fsm_dly_2_0_0_a[2] = !KE1_q_a[3] & !YB1_cmp_ctl_2_0_0_a2_0[0] & !YB1_cmp_ctl_2_0_0_a2_1[0] # !WB55L1;
|
| 14316 |
|
|
|
| 14317 |
|
|
|
| 14318 |
|
|
--AD1_CurrState_Sreg0_ns_0_0_0_a_x[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_0_0_a_x[8]
|
| 14319 |
|
|
--operation mode is normal
|
| 14320 |
|
|
|
| 14321 |
|
|
AD1_CurrState_Sreg0_ns_0_0_0_a_x[8] = !WB35L1 & WB45L1;
|
| 14322 |
|
|
|
| 14323 |
|
|
|
| 14324 |
|
|
--AD1_CurrState_Sreg0_ns_0_0_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_0_a[1]
|
| 14325 |
|
|
--operation mode is normal
|
| 14326 |
|
|
|
| 14327 |
|
|
AD1_CurrState_Sreg0_ns_0_0_a[1] = WB35L1 & !WB45L1 # !WB35L1 & WB45L1 # WB55L1 # !AD1_CurrState_Sreg0_i[0];
|
| 14328 |
|
|
|
| 14329 |
|
|
|
| 14330 |
|
|
--AD1_CurrState_Sreg0_ns_0_0_a2_2[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_0_a2_2[1]
|
| 14331 |
|
|
--operation mode is normal
|
| 14332 |
|
|
|
| 14333 |
|
|
AD1_CurrState_Sreg0_ns_0_0_a2_2[1] = !AD1_CurrState_Sreg0[2] & !AD1_CurrState_Sreg0_2;
|
| 14334 |
|
|
|
| 14335 |
|
|
|
| 14336 |
|
|
--YB1_alu_func_2_i_m3_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a[2]
|
| 14337 |
|
|
--operation mode is normal
|
| 14338 |
|
|
|
| 14339 |
|
|
YB1_alu_func_2_i_m3_0_a[2] = !KE1_q_a[3] & YB1_alu_func_2_0_0_o2_0[0] # YB1_alu_func_2_0_0_a2_1_x[3] & YB1_alu_func_2_0_0_a2_0_x[3];
|
| 14340 |
|
|
|
| 14341 |
|
|
|
| 14342 |
|
|
--YB1_alu_func_2_i_m3_0_5[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_5[2]
|
| 14343 |
|
|
--operation mode is normal
|
| 14344 |
|
|
|
| 14345 |
|
|
YB1_alu_func_2_i_m3_0_5[2] = YB1_alu_func_2_i_m3_0_a3_5[2] # YB1_alu_func_2_i_m3_0_2[2] # !KE1_q_a[4] & YB1_alu_func_2_i_m3_0_5_a[2];
|
| 14346 |
|
|
|
| 14347 |
|
|
|
| 14348 |
|
|
--YB1_alu_func_2_0_0_a3_0[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_0[3]
|
| 14349 |
|
|
--operation mode is normal
|
| 14350 |
|
|
|
| 14351 |
|
|
YB1_alu_func_2_0_0_a3_0[3] = WB04L2 & !KE1_q_a[7] & !KE1_q_a[4] & YB1_alu_func_2_0_0_a3_0_a_x[3];
|
| 14352 |
|
|
|
| 14353 |
|
|
|
| 14354 |
|
|
--YB1_alu_func_2_0_0_a3_1[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_1[3]
|
| 14355 |
|
|
--operation mode is normal
|
| 14356 |
|
|
|
| 14357 |
|
|
YB1_alu_func_2_0_0_a3_1[3] = !GE1_q_a[3] & !KE1_q_a[4] & YB1_alu_func_2_0_0_a3_1_a[3] & YB1_alu_func_2_0_0_a2_1_x[3];
|
| 14358 |
|
|
|
| 14359 |
|
|
|
| 14360 |
|
|
--YB1_alu_func_2_0_0_o3[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_o3[3]
|
| 14361 |
|
|
--operation mode is normal
|
| 14362 |
|
|
|
| 14363 |
|
|
YB1_alu_func_2_0_0_o3[3] = YB1_wb_mux_1_0_0_a3[0] # !KE1_q_a[3] & !KE1_q_a[4] & KE1_q_a[5];
|
| 14364 |
|
|
|
| 14365 |
|
|
|
| 14366 |
|
|
--YB1_alu_func_2_0_0_a[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a[3]
|
| 14367 |
|
|
--operation mode is normal
|
| 14368 |
|
|
|
| 14369 |
|
|
YB1_alu_func_2_0_0_a[3] = !KE1_q_a[3] & !KE1_q_a[4] & YB1_alu_func_2_0_0_a2_2_x[1] & YB1_alu_func_2_0_0_o2_x[3];
|
| 14370 |
|
|
|
| 14371 |
|
|
|
| 14372 |
|
|
--YB1_alu_func_2_0_0_1_Z[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1_Z[4]
|
| 14373 |
|
|
--operation mode is normal
|
| 14374 |
|
|
|
| 14375 |
|
|
YB1_alu_func_2_0_0_1_Z[4] = YB1_alu_func_2_0_0_a2_3_x[0] & YB1_alu_func_2_0_0_a2_1[4] # YB1_alu_func_2_0_0_a2_x[0] & !YB1_alu_func_2_0_0_1_a[4] # !YB1_alu_func_2_0_0_a2_3_x[0] & YB1_alu_func_2_0_0_a2_x[0] & !YB1_alu_func_2_0_0_1_a[4];
|
| 14376 |
|
|
|
| 14377 |
|
|
|
| 14378 |
|
|
--YB1_alu_func_2_0_0_o2_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_o2_0[0]
|
| 14379 |
|
|
--operation mode is normal
|
| 14380 |
|
|
|
| 14381 |
|
|
YB1_alu_func_2_0_0_o2_0[0] = YB1_alu_func_2_0_0_a2_2_x[1] # GE1_q_a[1] & !GE1_q_a[4] & YB1_alu_func_2_0_0_o2_0_a_x[0];
|
| 14382 |
|
|
|
| 14383 |
|
|
|
| 14384 |
|
|
--YB1_alu_func_2_0_0_0_Z[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_0_Z[0]
|
| 14385 |
|
|
--operation mode is normal
|
| 14386 |
|
|
|
| 14387 |
|
|
YB1_alu_func_2_0_0_0_Z[0] = !GE1_q_a[0] & !GE1_q_a[3] & YB1_alu_func_2_0_0_a2_0[1] & YB1_alu_func_2_0_0_0_a[0];
|
| 14388 |
|
|
|
| 14389 |
|
|
|
| 14390 |
|
|
--YB1_alu_func_2_0_0_2_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_2_a_x[0]
|
| 14391 |
|
|
--operation mode is normal
|
| 14392 |
|
|
|
| 14393 |
|
|
YB1_alu_func_2_0_0_2_a_x[0] = KE1_q_a[3] & KE1_q_a[4] $ KE1_q_a[2] # !KE1_q_a[3] & KE1_q_a[2] # !KE1_q_a[4];
|
| 14394 |
|
|
|
| 14395 |
|
|
|
| 14396 |
|
|
--YB1_alu_func_2_0_0_a2_3_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_3_x[0]
|
| 14397 |
|
|
--operation mode is normal
|
| 14398 |
|
|
|
| 14399 |
|
|
YB1_alu_func_2_0_0_a2_3_x[0] = GE1_q_a[3] & YB1_alu_func_2_0_0_a2_0[1];
|
| 14400 |
|
|
|
| 14401 |
|
|
|
| 14402 |
|
|
--VD1_hilo_37_iv_0_1[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[36]
|
| 14403 |
|
|
--operation mode is normal
|
| 14404 |
|
|
|
| 14405 |
|
|
VD1_hilo_37_iv_0_1[36] = VD1_hilo_37_iv_0_1_a[36] # VD1_addop2 & !VD1_un59_hilo_add4 & VD1_hilo_37_iv_0_a2_7[34];
|
| 14406 |
|
|
|
| 14407 |
|
|
|
| 14408 |
|
|
--VD1_hilo_37_iv_0_5_a[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[36]
|
| 14409 |
|
|
--operation mode is normal
|
| 14410 |
|
|
|
| 14411 |
|
|
VD1_hilo_37_iv_0_5_a[36] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add4 # !VD1_hilo_24_add4 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add4;
|
| 14412 |
|
|
|
| 14413 |
|
|
|
| 14414 |
|
|
--YB1_alu_func_2_0_0_o2_x[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_o2_x[3]
|
| 14415 |
|
|
--operation mode is normal
|
| 14416 |
|
|
|
| 14417 |
|
|
YB1_alu_func_2_0_0_o2_x[3] = GE1_q_a[3] # !GE1_q_a[1] & GE1_q_a[0];
|
| 14418 |
|
|
|
| 14419 |
|
|
|
| 14420 |
|
|
--YB1_ext_ctl_2_0_0_a2_2_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a2_2_x[2]
|
| 14421 |
|
|
--operation mode is normal
|
| 14422 |
|
|
|
| 14423 |
|
|
YB1_ext_ctl_2_0_0_a2_2_x[2] = !GE1_q_a[5] & !GE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[3];
|
| 14424 |
|
|
|
| 14425 |
|
|
|
| 14426 |
|
|
--YB1_muxa_ctl_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a[0]
|
| 14427 |
|
|
--operation mode is normal
|
| 14428 |
|
|
|
| 14429 |
|
|
YB1_muxa_ctl_2_0_0_a[0] = WB65L1 & !YB1_alu_func_2_0_0_a2_3[1] & !YB1_fsm_dly_2_0_0_a2_x[2] # !YB1_alu_func_2_0_0_a2_0_x[0] # !WB65L1 & !YB1_fsm_dly_2_0_0_a2_x[2] # !YB1_alu_func_2_0_0_a2_0_x[0];
|
| 14430 |
|
|
|
| 14431 |
|
|
|
| 14432 |
|
|
--YB1_muxa_ctl_2_0_0_x_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_x_0
|
| 14433 |
|
|
--operation mode is normal
|
| 14434 |
|
|
|
| 14435 |
|
|
YB1_muxa_ctl_2_0_0_x_0 = KE1_q_a[5] # YB1_muxa_ctl_2_0_0_2[1];
|
| 14436 |
|
|
|
| 14437 |
|
|
|
| 14438 |
|
|
--WB75L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1|q[0]~68
|
| 14439 |
|
|
--operation mode is normal
|
| 14440 |
|
|
|
| 14441 |
|
|
WB75L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_muxa_ctl_2_0_0_x_0 # !YB1_un1_muxa_ctl370_x & WB75L2;
|
| 14442 |
|
|
|
| 14443 |
|
|
|
| 14444 |
|
|
--WB75L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1|q[0]~69
|
| 14445 |
|
|
--operation mode is normal
|
| 14446 |
|
|
|
| 14447 |
|
|
WB75L2 = WB75L1 & !YB1_un1_ins_i_23_2_0;
|
| 14448 |
|
|
|
| 14449 |
|
|
|
| 14450 |
|
|
--AE1_q_4 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_4
|
| 14451 |
|
|
--operation mode is normal
|
| 14452 |
|
|
|
| 14453 |
|
|
AE1_q_4_lut_out = ED1_r32_o_25;
|
| 14454 |
|
|
AE1_q_4 = DFFEAS(AE1_q_4_lut_out, E1__clk0, VCC, , , , , , );
|
| 14455 |
|
|
|
| 14456 |
|
|
|
| 14457 |
|
|
--WD1_un1_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un1_mux_fw_NE_1
|
| 14458 |
|
|
--operation mode is normal
|
| 14459 |
|
|
|
| 14460 |
|
|
WD1_un1_mux_fw_NE_1 = MB1_r5_o_1 & MB1_r5_o_0 $ AE1_q_0 # !AE1_q_1 # !MB1_r5_o_1 & AE1_q_1 # MB1_r5_o_0 $ AE1_q_0;
|
| 14461 |
|
|
|
| 14462 |
|
|
|
| 14463 |
|
|
--WD1_un1_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un1_mux_fw_NE_a
|
| 14464 |
|
|
--operation mode is normal
|
| 14465 |
|
|
|
| 14466 |
|
|
WD1_un1_mux_fw_NE_a = MB1_r5_o_2 & MB1_r5_o_3 $ AE1_q_3 # !AE1_q_2 # !MB1_r5_o_2 & AE1_q_2 # MB1_r5_o_3 $ AE1_q_3;
|
| 14467 |
|
|
|
| 14468 |
|
|
|
| 14469 |
|
|
--HD1_dout_iv_1_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_4
|
| 14470 |
|
|
--operation mode is normal
|
| 14471 |
|
|
|
| 14472 |
|
|
HD1_dout_iv_1_4 = FD1_N_18_i_0_s3 & LD2_q_b[4] # !HD1_dout_iv_1_a[4];
|
| 14473 |
|
|
|
| 14474 |
|
|
|
| 14475 |
|
|
--HD1_dout7_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout7_0_a2
|
| 14476 |
|
|
--operation mode is normal
|
| 14477 |
|
|
|
| 14478 |
|
|
HD1_dout7_0_a2 = MC1_wb_we_o_0 & !WD1_un30_mux_fw & !YD1_un17_mux_fw_NE & !YD1_mux_fw_1;
|
| 14479 |
|
|
|
| 14480 |
|
|
|
| 14481 |
|
|
--WD1_un17_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un17_mux_fw_NE
|
| 14482 |
|
|
--operation mode is normal
|
| 14483 |
|
|
|
| 14484 |
|
|
WD1_un17_mux_fw_NE = WD1_un17_mux_fw_NE_1 # WD1_un17_mux_fw_NE_a # AE1_q_4 $ NB1_r5_o_4;
|
| 14485 |
|
|
|
| 14486 |
|
|
|
| 14487 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[10] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[10]
|
| 14488 |
|
|
--operation mode is normal
|
| 14489 |
|
|
|
| 14490 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[10] = QB1_r32_o_10 & !FB1_r32_o_0_10 & QD1_b_o18 # !QB1_r32_o_10 & QD1_un1_b_o18_2 # !FB1_r32_o_0_10 & QD1_b_o18;
|
| 14491 |
|
|
|
| 14492 |
|
|
|
| 14493 |
|
|
--G1_BUS15471_i_m[10] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[10]
|
| 14494 |
|
|
--operation mode is normal
|
| 14495 |
|
|
|
| 14496 |
|
|
G1_BUS15471_i_m[10] = !FD1_wb_o_10 & QD1_b_o_1_sqmuxa;
|
| 14497 |
|
|
|
| 14498 |
|
|
|
| 14499 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[15] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[15]
|
| 14500 |
|
|
--operation mode is normal
|
| 14501 |
|
|
|
| 14502 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[15] = QB1_r32_o_15 & !FB1_r32_o_0_15 & QD1_b_o18 # !QB1_r32_o_15 & QD1_un1_b_o18_2 # !FB1_r32_o_0_15 & QD1_b_o18;
|
| 14503 |
|
|
|
| 14504 |
|
|
|
| 14505 |
|
|
--G1_BUS15471_i_m[15] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[15]
|
| 14506 |
|
|
--operation mode is normal
|
| 14507 |
|
|
|
| 14508 |
|
|
G1_BUS15471_i_m[15] = !FD1_wb_o_15 & QD1_b_o_1_sqmuxa;
|
| 14509 |
|
|
|
| 14510 |
|
|
|
| 14511 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[27] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[27]
|
| 14512 |
|
|
--operation mode is normal
|
| 14513 |
|
|
|
| 14514 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[27] = QB1_r32_o_27 & !FB1_r32_o_27 & QD1_b_o18 # !QB1_r32_o_27 & QD1_un1_b_o18_2 # !FB1_r32_o_27 & QD1_b_o18;
|
| 14515 |
|
|
|
| 14516 |
|
|
|
| 14517 |
|
|
--G1_BUS15471_i_m[27] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[27]
|
| 14518 |
|
|
--operation mode is normal
|
| 14519 |
|
|
|
| 14520 |
|
|
G1_BUS15471_i_m[27] = !FD1_wb_o_27 & QD1_b_o_1_sqmuxa;
|
| 14521 |
|
|
|
| 14522 |
|
|
|
| 14523 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[19] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[19]
|
| 14524 |
|
|
--operation mode is normal
|
| 14525 |
|
|
|
| 14526 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[19] = QB1_r32_o_19 & !FB1_r32_o_19 & QD1_b_o18 # !QB1_r32_o_19 & QD1_un1_b_o18_2 # !FB1_r32_o_19 & QD1_b_o18;
|
| 14527 |
|
|
|
| 14528 |
|
|
|
| 14529 |
|
|
--G1_BUS15471_i_m[19] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[19]
|
| 14530 |
|
|
--operation mode is normal
|
| 14531 |
|
|
|
| 14532 |
|
|
G1_BUS15471_i_m[19] = !FD1_wb_o_19 & QD1_b_o_1_sqmuxa;
|
| 14533 |
|
|
|
| 14534 |
|
|
|
| 14535 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[20] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[20]
|
| 14536 |
|
|
--operation mode is normal
|
| 14537 |
|
|
|
| 14538 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[20] = QB1_r32_o_20 & !FB1_r32_o_20 & QD1_b_o18 # !QB1_r32_o_20 & QD1_un1_b_o18_2 # !FB1_r32_o_20 & QD1_b_o18;
|
| 14539 |
|
|
|
| 14540 |
|
|
|
| 14541 |
|
|
--G1_BUS15471_i_m[20] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[20]
|
| 14542 |
|
|
--operation mode is normal
|
| 14543 |
|
|
|
| 14544 |
|
|
G1_BUS15471_i_m[20] = !FD1_wb_o_20 & QD1_b_o_1_sqmuxa;
|
| 14545 |
|
|
|
| 14546 |
|
|
|
| 14547 |
|
|
--VD1_un134_hilo_combout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[6]
|
| 14548 |
|
|
--operation mode is arithmetic
|
| 14549 |
|
|
|
| 14550 |
|
|
VD1_un134_hilo_combout[6]_carry_eqn = VD1_un134_hilo_cout[4];
|
| 14551 |
|
|
VD1_un134_hilo_combout[6] = VD1_hilo_6 $ (VD1_un134_hilo_combout[6]_carry_eqn);
|
| 14552 |
|
|
|
| 14553 |
|
|
--VD1_un134_hilo_cout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[6]
|
| 14554 |
|
|
--operation mode is arithmetic
|
| 14555 |
|
|
|
| 14556 |
|
|
VD1_un134_hilo_cout[6] = CARRY(!VD1_un134_hilo_cout[4] # !VD1_hilo_7 # !VD1_hilo_6);
|
| 14557 |
|
|
|
| 14558 |
|
|
|
| 14559 |
|
|
--VD1_hilo_1_sqmuxa_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1_sqmuxa_i
|
| 14560 |
|
|
--operation mode is normal
|
| 14561 |
|
|
|
| 14562 |
|
|
VD1_hilo_1_sqmuxa_i = !VD1_rdy_0_sqmuxa # !sys_rst;
|
| 14563 |
|
|
|
| 14564 |
|
|
|
| 14565 |
|
|
--VD1_count[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[4]
|
| 14566 |
|
|
--operation mode is arithmetic
|
| 14567 |
|
|
|
| 14568 |
|
|
VD1_count[4]_carry_eqn = VD1_count_cout[3];
|
| 14569 |
|
|
VD1_count[4]_lut_out = VD1_count[4] $ (!VD1_count[4]_carry_eqn);
|
| 14570 |
|
|
VD1_count[4] = DFFEAS(VD1_count[4]_lut_out, E1__clk0, VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
|
| 14571 |
|
|
|
| 14572 |
|
|
--VD1_count_cout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[4]
|
| 14573 |
|
|
--operation mode is arithmetic
|
| 14574 |
|
|
|
| 14575 |
|
|
VD1_count_cout[4] = CARRY(VD1_count[4] & !VD1_count_cout[3]);
|
| 14576 |
|
|
|
| 14577 |
|
|
|
| 14578 |
|
|
--VD1_overflow_4_iv_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|overflow_4_iv_a
|
| 14579 |
|
|
--operation mode is normal
|
| 14580 |
|
|
|
| 14581 |
|
|
VD1_overflow_4_iv_a = !VD1_op2_reged_3[32] # !PD1_a_o_31 # !VD1_addnop2109_0_a2 # !VD1_un3_overflow_m_0;
|
| 14582 |
|
|
|
| 14583 |
|
|
|
| 14584 |
|
|
--VD1_over_i[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_i[32]
|
| 14585 |
|
|
--operation mode is normal
|
| 14586 |
|
|
|
| 14587 |
|
|
VD1_over_i[32]_carry_eqn = VD1_over_add31_cout;
|
| 14588 |
|
|
VD1_over_i[32] = !VD1_over_i[32]_carry_eqn;
|
| 14589 |
|
|
|
| 14590 |
|
|
|
| 14591 |
|
|
--VD1_rdy_1_i_a2_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|rdy_1_i_a2_a
|
| 14592 |
|
|
--operation mode is normal
|
| 14593 |
|
|
|
| 14594 |
|
|
VD1_rdy_1_i_a2_a = !VD1_hilo25 & !VD1_rdy_0_sqmuxa & !VD1_addnop2110 # !VD1_un1_overflow_1;
|
| 14595 |
|
|
|
| 14596 |
|
|
|
| 14597 |
|
|
--VD1_op2_reged_3[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged_3[32]
|
| 14598 |
|
|
--operation mode is normal
|
| 14599 |
|
|
|
| 14600 |
|
|
VD1_op2_reged_3[32] = RC1_alu_func_o_0 & VD1_b_o_iv_31;
|
| 14601 |
|
|
|
| 14602 |
|
|
--VD1_op2_sign_reged is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_sign_reged
|
| 14603 |
|
|
--operation mode is normal
|
| 14604 |
|
|
|
| 14605 |
|
|
VD1_op2_sign_reged = DFFEAS(VD1_op2_reged_3[32], E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 14606 |
|
|
|
| 14607 |
|
|
|
| 14608 |
|
|
--VD1_add1_3_sqmuxa_0_x is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|add1_3_sqmuxa_0_x
|
| 14609 |
|
|
--operation mode is normal
|
| 14610 |
|
|
|
| 14611 |
|
|
VD1_add1_3_sqmuxa_0_x = sys_rst & !VD1_mul;
|
| 14612 |
|
|
|
| 14613 |
|
|
|
| 14614 |
|
|
--VD1_add1_14_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|add1_14_a
|
| 14615 |
|
|
--operation mode is normal
|
| 14616 |
|
|
|
| 14617 |
|
|
VD1_add1_14_a = VD1_op1_sign_reged & !VD1_eqz_2 & VD1_eqop2_2_NE # !VD1_op2_sign_reged;
|
| 14618 |
|
|
|
| 14619 |
|
|
|
| 14620 |
|
|
--VD1_eqnop2_2_NE is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE
|
| 14621 |
|
|
--operation mode is normal
|
| 14622 |
|
|
|
| 14623 |
|
|
VD1_eqnop2_2_NE = VD1_eqnop2_2_NE_7 # VD1_eqnop2_2_NE_9 # VD1_eqnop2_2_NE_10 # !VD1_eqnop2_2_NE_a;
|
| 14624 |
|
|
|
| 14625 |
|
|
|
| 14626 |
|
|
--VD1_addop2_0_sqmuxa_1_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addop2_0_sqmuxa_1_i
|
| 14627 |
|
|
--operation mode is normal
|
| 14628 |
|
|
|
| 14629 |
|
|
VD1_addop2_0_sqmuxa_1_i = VD1_count[5] & !VD1_finish & VD1_addnop2110 # !sys_rst;
|
| 14630 |
|
|
|
| 14631 |
|
|
|
| 14632 |
|
|
--VD1_hilo[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo[64]
|
| 14633 |
|
|
--operation mode is normal
|
| 14634 |
|
|
|
| 14635 |
|
|
VD1_hilo[64]_lut_out = !VD1_hilo_33_i_m[64] & VD1_hilo_37_iv_a[64] & !VD1_hilo_37_iv_1[64] & !VD1_hilo_37_iv_0_a3[57];
|
| 14636 |
|
|
VD1_hilo[64] = DFFEAS(VD1_hilo[64]_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 14637 |
|
|
|
| 14638 |
|
|
|
| 14639 |
|
|
--VD1_sub_or_yn_0_sqmuxa_1_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sub_or_yn_0_sqmuxa_1_a
|
| 14640 |
|
|
--operation mode is normal
|
| 14641 |
|
|
|
| 14642 |
|
|
VD1_sub_or_yn_0_sqmuxa_1_a = !VD1_hilo25 & VD1_rdy # VD1_start & !VD1_un1_addnop2104_1;
|
| 14643 |
|
|
|
| 14644 |
|
|
|
| 14645 |
|
|
--VD1_nop2_reged[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[4]
|
| 14646 |
|
|
--operation mode is arithmetic
|
| 14647 |
|
|
|
| 14648 |
|
|
VD1_nop2_reged[4]_carry_eqn = VD1_nop2_reged_cout[2];
|
| 14649 |
|
|
VD1_nop2_reged[4] = VD1_op2_reged[4] $ VD1_nop2_reged[4]_carry_eqn;
|
| 14650 |
|
|
|
| 14651 |
|
|
--VD1_nop2_reged_cout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[4]
|
| 14652 |
|
|
--operation mode is arithmetic
|
| 14653 |
|
|
|
| 14654 |
|
|
VD1_nop2_reged_cout[4] = CARRY(!VD1_op2_reged[5] & !VD1_op2_reged[4] & !VD1_nop2_reged_cout[2]);
|
| 14655 |
|
|
|
| 14656 |
|
|
|
| 14657 |
|
|
--VD1_nop2_reged[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[5]
|
| 14658 |
|
|
--operation mode is arithmetic
|
| 14659 |
|
|
|
| 14660 |
|
|
VD1_nop2_reged[5]_carry_eqn = VD1_nop2_reged_cout[3];
|
| 14661 |
|
|
VD1_nop2_reged[5] = VD1_op2_reged[5] $ (VD1_op2_reged[4] # VD1_nop2_reged[5]_carry_eqn);
|
| 14662 |
|
|
|
| 14663 |
|
|
--VD1_nop2_reged_cout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[5]
|
| 14664 |
|
|
--operation mode is arithmetic
|
| 14665 |
|
|
|
| 14666 |
|
|
VD1_nop2_reged_cout[5] = CARRY(!VD1_op2_reged[5] & !VD1_op2_reged[4] & !VD1_nop2_reged_cout[3]);
|
| 14667 |
|
|
|
| 14668 |
|
|
|
| 14669 |
|
|
--VD1_un50_hilo_add4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add4
|
| 14670 |
|
|
--operation mode is arithmetic
|
| 14671 |
|
|
|
| 14672 |
|
|
VD1_un50_hilo_add4_carry_eqn = VD1_un50_hilo_carry_3;
|
| 14673 |
|
|
VD1_un50_hilo_add4 = VD1_hilo_36 $ VD1_nop2_reged[4] $ !VD1_un50_hilo_add4_carry_eqn;
|
| 14674 |
|
|
|
| 14675 |
|
|
--VD1_un50_hilo_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_4
|
| 14676 |
|
|
--operation mode is arithmetic
|
| 14677 |
|
|
|
| 14678 |
|
|
VD1_un50_hilo_carry_4 = CARRY(VD1_hilo_36 & VD1_nop2_reged[4] # !VD1_un50_hilo_carry_3 # !VD1_hilo_36 & VD1_nop2_reged[4] & !VD1_un50_hilo_carry_3);
|
| 14679 |
|
|
|
| 14680 |
|
|
|
| 14681 |
|
|
--VD1_un59_hilo_add4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add4
|
| 14682 |
|
|
--operation mode is arithmetic
|
| 14683 |
|
|
|
| 14684 |
|
|
VD1_un59_hilo_add4_carry_eqn = VD1_un59_hilo_carry_3;
|
| 14685 |
|
|
VD1_un59_hilo_add4 = VD1_hilo_36 $ VD1_op2_reged[4] $ !VD1_un59_hilo_add4_carry_eqn;
|
| 14686 |
|
|
|
| 14687 |
|
|
--VD1_un59_hilo_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_4
|
| 14688 |
|
|
--operation mode is arithmetic
|
| 14689 |
|
|
|
| 14690 |
|
|
VD1_un59_hilo_carry_4 = CARRY(VD1_hilo_36 & VD1_op2_reged[4] # !VD1_un59_hilo_carry_3 # !VD1_hilo_36 & VD1_op2_reged[4] & !VD1_un59_hilo_carry_3);
|
| 14691 |
|
|
|
| 14692 |
|
|
|
| 14693 |
|
|
--VD1_un1_mul_2_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_mul_2_a
|
| 14694 |
|
|
--operation mode is normal
|
| 14695 |
|
|
|
| 14696 |
|
|
VD1_un1_mul_2_a = VD1_op1_sign_reged & VD1_op2_sign_reged & !VD1_hilo[64] & !VD1_eqz_2 # !VD1_op1_sign_reged & !VD1_op2_sign_reged & VD1_hilo[64];
|
| 14697 |
|
|
|
| 14698 |
|
|
|
| 14699 |
|
|
--VD1_addnop292[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop292[0]
|
| 14700 |
|
|
--operation mode is normal
|
| 14701 |
|
|
|
| 14702 |
|
|
VD1_addnop292[0] = VD1_op1_sign_reged & VD1_op2_sign_reged & !VD1_eqz_2 & !VD1_eqop2_2_NE;
|
| 14703 |
|
|
|
| 14704 |
|
|
|
| 14705 |
|
|
--VD1_addnop290[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop290[0]
|
| 14706 |
|
|
--operation mode is normal
|
| 14707 |
|
|
|
| 14708 |
|
|
VD1_addnop290[0] = VD1_op1_sign_reged & !VD1_op2_sign_reged & !VD1_eqz_2 & !VD1_eqnop2_2_NE;
|
| 14709 |
|
|
|
| 14710 |
|
|
|
| 14711 |
|
|
--VD1_addnop2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop2
|
| 14712 |
|
|
--operation mode is normal
|
| 14713 |
|
|
|
| 14714 |
|
|
VD1_addnop2_lut_out = !VD1_mul & VD1_addnop292[0] # VD1_un1_mul_3_a & !VD1_addnop290[0];
|
| 14715 |
|
|
VD1_addnop2 = DFFEAS(VD1_addnop2_lut_out, E1__clk0, VCC, , VD1_addop2_0_sqmuxa_1_i, , , , );
|
| 14716 |
|
|
|
| 14717 |
|
|
|
| 14718 |
|
|
--VD1_hilo_0_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_0_sqmuxa
|
| 14719 |
|
|
--operation mode is normal
|
| 14720 |
|
|
|
| 14721 |
|
|
VD1_hilo_0_sqmuxa = !VD1_rdy & VD1_start & VD1_overflow & !VD1_hilo25;
|
| 14722 |
|
|
|
| 14723 |
|
|
|
| 14724 |
|
|
--VD1_un1_op2_reged_1_combout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[5]
|
| 14725 |
|
|
--operation mode is normal
|
| 14726 |
|
|
|
| 14727 |
|
|
VD1_un1_op2_reged_1_combout[5] = VD1_eqop2_2_32 & VD1_op2_reged[5] # !VD1_eqop2_2_32 & VD1_nop2_reged[5];
|
| 14728 |
|
|
|
| 14729 |
|
|
|
| 14730 |
|
|
--VD1_hilo_24_add4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add4
|
| 14731 |
|
|
--operation mode is arithmetic
|
| 14732 |
|
|
|
| 14733 |
|
|
VD1_hilo_24_add4_carry_eqn = VD1_hilo_24_carry_3;
|
| 14734 |
|
|
VD1_hilo_24_add4 = VD1_hilo_35 $ VD1_un1_op2_reged_1_combout[4] $ !VD1_hilo_24_add4_carry_eqn;
|
| 14735 |
|
|
|
| 14736 |
|
|
--VD1_hilo_24_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_4
|
| 14737 |
|
|
--operation mode is arithmetic
|
| 14738 |
|
|
|
| 14739 |
|
|
VD1_hilo_24_carry_4 = CARRY(VD1_hilo_35 & VD1_un1_op2_reged_1_combout[4] # !VD1_hilo_24_carry_3 # !VD1_hilo_35 & VD1_un1_op2_reged_1_combout[4] & !VD1_hilo_24_carry_3);
|
| 14740 |
|
|
|
| 14741 |
|
|
|
| 14742 |
|
|
--VD1_hilo_37_iv_0_3[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[38]
|
| 14743 |
|
|
--operation mode is normal
|
| 14744 |
|
|
|
| 14745 |
|
|
VD1_hilo_37_iv_0_3[38] = VD1_hilo_37_iv_0_a2_0[38] # !VD1_hilo_38 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_hilo_37_iv_0_3_a[38];
|
| 14746 |
|
|
|
| 14747 |
|
|
|
| 14748 |
|
|
--HD1_dout_iv_1_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_5
|
| 14749 |
|
|
--operation mode is normal
|
| 14750 |
|
|
|
| 14751 |
|
|
HD1_dout_iv_1_5 = FD1_N_18_i_0_s3 & LD2_q_b[5] # !HD1_dout_iv_1_a[5];
|
| 14752 |
|
|
|
| 14753 |
|
|
|
| 14754 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[16] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[16]
|
| 14755 |
|
|
--operation mode is normal
|
| 14756 |
|
|
|
| 14757 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[16] = QB1_r32_o_16 & !FB1_r32_o_16 & QD1_b_o18 # !QB1_r32_o_16 & QD1_un1_b_o18_2 # !FB1_r32_o_16 & QD1_b_o18;
|
| 14758 |
|
|
|
| 14759 |
|
|
|
| 14760 |
|
|
--G1_BUS15471_i_m[16] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[16]
|
| 14761 |
|
|
--operation mode is normal
|
| 14762 |
|
|
|
| 14763 |
|
|
G1_BUS15471_i_m[16] = !FD1_wb_o_16 & QD1_b_o_1_sqmuxa;
|
| 14764 |
|
|
|
| 14765 |
|
|
|
| 14766 |
|
|
--FB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_28
|
| 14767 |
|
|
--operation mode is normal
|
| 14768 |
|
|
|
| 14769 |
|
|
FB1_r32_o_28_lut_out = CD1_res_7_0_0_a3_0 # ED1_r32_o_12 & CD1_res_7_0_0_a2_16;
|
| 14770 |
|
|
FB1_r32_o_28 = DFFEAS(FB1_r32_o_28_lut_out, E1__clk0, VCC, , , , , , );
|
| 14771 |
|
|
|
| 14772 |
|
|
|
| 14773 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[28] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[28]
|
| 14774 |
|
|
--operation mode is normal
|
| 14775 |
|
|
|
| 14776 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[28] = !QB1_r32_o_28 & QD1_un1_b_o18_2;
|
| 14777 |
|
|
|
| 14778 |
|
|
|
| 14779 |
|
|
--QD1_b_o_iv_1_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_iv_1_27
|
| 14780 |
|
|
--operation mode is normal
|
| 14781 |
|
|
|
| 14782 |
|
|
QD1_b_o_iv_1_27 = AB1_r32_o_26 & !FD1_wb_o_28 & QD1_b_o_1_sqmuxa # !AB1_r32_o_26 & QD1_b_o_0_sqmuxa # !FD1_wb_o_28 & QD1_b_o_1_sqmuxa;
|
| 14783 |
|
|
|
| 14784 |
|
|
|
| 14785 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[23] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[23]
|
| 14786 |
|
|
--operation mode is normal
|
| 14787 |
|
|
|
| 14788 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[23] = QB1_r32_o_23 & !FB1_r32_o_23 & QD1_b_o18 # !QB1_r32_o_23 & QD1_un1_b_o18_2 # !FB1_r32_o_23 & QD1_b_o18;
|
| 14789 |
|
|
|
| 14790 |
|
|
|
| 14791 |
|
|
--G1_BUS15471_i_m[23] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[23]
|
| 14792 |
|
|
--operation mode is normal
|
| 14793 |
|
|
|
| 14794 |
|
|
G1_BUS15471_i_m[23] = !FD1_wb_o_23 & QD1_b_o_1_sqmuxa;
|
| 14795 |
|
|
|
| 14796 |
|
|
|
| 14797 |
|
|
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[24] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[24]
|
| 14798 |
|
|
--operation mode is normal
|
| 14799 |
|
|
|
| 14800 |
|
|
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[24] = QB1_r32_o_24 & !FB1_r32_o_24 & QD1_b_o18 # !QB1_r32_o_24 & QD1_un1_b_o18_2 # !FB1_r32_o_24 & QD1_b_o18;
|
| 14801 |
|
|
|
| 14802 |
|
|
|
| 14803 |
|
|
--G1_BUS15471_i_m[24] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[24]
|
| 14804 |
|
|
--operation mode is normal
|
| 14805 |
|
|
|
| 14806 |
|
|
G1_BUS15471_i_m[24] = !FD1_wb_o_24 & QD1_b_o_1_sqmuxa;
|
| 14807 |
|
|
|
| 14808 |
|
|
|
| 14809 |
|
|
--VD1_un134_hilo_cout[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[0]
|
| 14810 |
|
|
--operation mode is arithmetic
|
| 14811 |
|
|
|
| 14812 |
|
|
VD1_un134_hilo_cout[0] = CARRY(VD1_hilo[0] & VD1_hilo_1);
|
| 14813 |
|
|
|
| 14814 |
|
|
|
| 14815 |
|
|
--VD1_nop2_reged[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[3]
|
| 14816 |
|
|
--operation mode is arithmetic
|
| 14817 |
|
|
|
| 14818 |
|
|
VD1_nop2_reged[3]_carry_eqn = VD1_nop2_reged_cout[1];
|
| 14819 |
|
|
VD1_nop2_reged[3] = VD1_op2_reged[3] $ (VD1_op2_reged[2] # !VD1_nop2_reged[3]_carry_eqn);
|
| 14820 |
|
|
|
| 14821 |
|
|
--VD1_nop2_reged_cout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[3]
|
| 14822 |
|
|
--operation mode is arithmetic
|
| 14823 |
|
|
|
| 14824 |
|
|
VD1_nop2_reged_cout[3] = CARRY(VD1_op2_reged[3] # VD1_op2_reged[2] # !VD1_nop2_reged_cout[1]);
|
| 14825 |
|
|
|
| 14826 |
|
|
|
| 14827 |
|
|
--VD1_un50_hilo_add2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add2
|
| 14828 |
|
|
--operation mode is arithmetic
|
| 14829 |
|
|
|
| 14830 |
|
|
VD1_un50_hilo_add2_carry_eqn = VD1_un50_hilo_carry_1;
|
| 14831 |
|
|
VD1_un50_hilo_add2 = VD1_hilo_34 $ VD1_nop2_reged[2] $ !VD1_un50_hilo_add2_carry_eqn;
|
| 14832 |
|
|
|
| 14833 |
|
|
--VD1_un50_hilo_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_2
|
| 14834 |
|
|
--operation mode is arithmetic
|
| 14835 |
|
|
|
| 14836 |
|
|
VD1_un50_hilo_carry_2 = CARRY(VD1_hilo_34 & VD1_nop2_reged[2] # !VD1_un50_hilo_carry_1 # !VD1_hilo_34 & VD1_nop2_reged[2] & !VD1_un50_hilo_carry_1);
|
| 14837 |
|
|
|
| 14838 |
|
|
|
| 14839 |
|
|
--VD1_un1_op2_reged_1_combout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[2]
|
| 14840 |
|
|
--operation mode is normal
|
| 14841 |
|
|
|
| 14842 |
|
|
VD1_un1_op2_reged_1_combout[2] = VD1_eqop2_2_32 & VD1_op2_reged[2] # !VD1_eqop2_2_32 & VD1_nop2_reged[2];
|
| 14843 |
|
|
|
| 14844 |
|
|
|
| 14845 |
|
|
--VD1_hilo_24_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add1
|
| 14846 |
|
|
--operation mode is arithmetic
|
| 14847 |
|
|
|
| 14848 |
|
|
VD1_hilo_24_add1_carry_eqn = VD1_hilo_24_carry_0;
|
| 14849 |
|
|
VD1_hilo_24_add1 = VD1_hilo[32] $ VD1_un1_op2_reged_1_combout[1] $ VD1_hilo_24_add1_carry_eqn;
|
| 14850 |
|
|
|
| 14851 |
|
|
--VD1_hilo_24_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_1
|
| 14852 |
|
|
--operation mode is arithmetic
|
| 14853 |
|
|
|
| 14854 |
|
|
VD1_hilo_24_carry_1 = CARRY(VD1_hilo[32] & !VD1_un1_op2_reged_1_combout[1] & !VD1_hilo_24_carry_0 # !VD1_hilo[32] & !VD1_hilo_24_carry_0 # !VD1_un1_op2_reged_1_combout[1]);
|
| 14855 |
|
|
|
| 14856 |
|
|
|
| 14857 |
|
|
--VD1_hilo_37_iv_0_2_a[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2_a[34]
|
| 14858 |
|
|
--operation mode is normal
|
| 14859 |
|
|
|
| 14860 |
|
|
VD1_hilo_37_iv_0_2_a[34] = VD1_un59_hilo_add2 & !VD1_un50_hilo_add2 & VD1_hilo_37_iv_0_a2_6_0[37] # !VD1_un59_hilo_add2 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_un50_hilo_add2 & VD1_hilo_37_iv_0_a2_6_0[37];
|
| 14861 |
|
|
|
| 14862 |
|
|
|
| 14863 |
|
|
--VD1_un59_hilo_add3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add3
|
| 14864 |
|
|
--operation mode is arithmetic
|
| 14865 |
|
|
|
| 14866 |
|
|
VD1_un59_hilo_add3_carry_eqn = VD1_un59_hilo_carry_2;
|
| 14867 |
|
|
VD1_un59_hilo_add3 = VD1_hilo_35 $ VD1_op2_reged[3] $ VD1_un59_hilo_add3_carry_eqn;
|
| 14868 |
|
|
|
| 14869 |
|
|
--VD1_un59_hilo_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_3
|
| 14870 |
|
|
--operation mode is arithmetic
|
| 14871 |
|
|
|
| 14872 |
|
|
VD1_un59_hilo_carry_3 = CARRY(VD1_hilo_35 & !VD1_op2_reged[3] & !VD1_un59_hilo_carry_2 # !VD1_hilo_35 & !VD1_un59_hilo_carry_2 # !VD1_op2_reged[3]);
|
| 14873 |
|
|
|
| 14874 |
|
|
|
| 14875 |
|
|
--VD1_hilo_37_iv_0_o3_1_a[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1_a[34]
|
| 14876 |
|
|
--operation mode is normal
|
| 14877 |
|
|
|
| 14878 |
|
|
VD1_hilo_37_iv_0_o3_1_a[34] = VD1_hilo_2 & !VD1_hilo_35 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_hilo_2 & VD1_hilo_0_sqmuxa # !VD1_hilo_35 & VD1_hilo_37_iv_0_a6_0_1[40];
|
| 14879 |
|
|
|
| 14880 |
|
|
|
| 14881 |
|
|
--VD1_hilo_37_iv_0_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[3]
|
| 14882 |
|
|
--operation mode is normal
|
| 14883 |
|
|
|
| 14884 |
|
|
VD1_hilo_37_iv_0_a[3] = VD1_add1 & !VD1_un134_hilo_combout[3] # !VD1_add1 & !VD1_hilo_3;
|
| 14885 |
|
|
|
| 14886 |
|
|
|
| 14887 |
|
|
--VD1_hilo_33_i_m[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[35]
|
| 14888 |
|
|
--operation mode is normal
|
| 14889 |
|
|
|
| 14890 |
|
|
VD1_hilo_33_i_m[35] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[35] # !VD1_hilo_33_1[64] & !VD1_hilo_35;
|
| 14891 |
|
|
|
| 14892 |
|
|
|
| 14893 |
|
|
--VD1_hilo_37_iv_2_a[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[35]
|
| 14894 |
|
|
--operation mode is normal
|
| 14895 |
|
|
|
| 14896 |
|
|
VD1_hilo_37_iv_2_a[35] = VD1_hilo_3 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add3 # !VD1_hilo_3 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add3;
|
| 14897 |
|
|
|
| 14898 |
|
|
|
| 14899 |
|
|
--VD1_hilo_22_Z[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[35]
|
| 14900 |
|
|
--operation mode is normal
|
| 14901 |
|
|
|
| 14902 |
|
|
VD1_hilo_22_Z[35] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[35] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[35] # !VD1_sign & !VD1_hilo_22_a[35];
|
| 14903 |
|
|
|
| 14904 |
|
|
|
| 14905 |
|
|
--UD1_shift_out_79_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[3]
|
| 14906 |
|
|
--operation mode is normal
|
| 14907 |
|
|
|
| 14908 |
|
|
UD1_shift_out_79_a[3] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_12 # !PD1_a_o_0 & !VD1_b_o_iv_11;
|
| 14909 |
|
|
|
| 14910 |
|
|
|
| 14911 |
|
|
--YB1_dmem_ctl_2_0_0_1_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_1_a[1]
|
| 14912 |
|
|
--operation mode is normal
|
| 14913 |
|
|
|
| 14914 |
|
|
YB1_dmem_ctl_2_0_0_1_a[1] = KE1_q_a[7] & KE1_q_a[3] & !KE1_q_a[4] & KE1_q_a[2] # !KE1_q_a[3] & KE1_q_a[4] $ !KE1_q_a[2];
|
| 14915 |
|
|
|
| 14916 |
|
|
|
| 14917 |
|
|
--UD1_shift_out_87_d_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[16]
|
| 14918 |
|
|
--operation mode is normal
|
| 14919 |
|
|
|
| 14920 |
|
|
UD1_shift_out_87_d_a[16] = PD1_a_o_1 & !VD1_b_o_iv_22 # !PD1_a_o_1 & !VD1_b_o_iv_20;
|
| 14921 |
|
|
|
| 14922 |
|
|
|
| 14923 |
|
|
--UD1_shift_out_80[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[16]
|
| 14924 |
|
|
--operation mode is normal
|
| 14925 |
|
|
|
| 14926 |
|
|
UD1_shift_out_80[16] = PD1_a_o_2 & UD1_shift_out_80_a[16] & VD1_b_o_iv_21 # !UD1_shift_out_80_a[16] & VD1_b_o_iv_23 # !PD1_a_o_2 & !UD1_shift_out_80_a[16];
|
| 14927 |
|
|
|
| 14928 |
|
|
|
| 14929 |
|
|
--UD1_shift_out_85_d_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[16]
|
| 14930 |
|
|
--operation mode is normal
|
| 14931 |
|
|
|
| 14932 |
|
|
UD1_shift_out_85_d_a[16] = PD1_a_o_0 & !VD1_b_o_iv_13 # !PD1_a_o_0 & !VD1_b_o_iv_14;
|
| 14933 |
|
|
|
| 14934 |
|
|
|
| 14935 |
|
|
--UD1_shift_out_52[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52[28]
|
| 14936 |
|
|
--operation mode is normal
|
| 14937 |
|
|
|
| 14938 |
|
|
UD1_shift_out_52[28] = PD1_a_o_1 & !UD1_shift_out_52_a[28] # !PD1_a_o_1 & UD1_shift_out_52_a[28] & VD1_b_o_iv_12 # !UD1_shift_out_52_a[28] & VD1_b_o_iv_11;
|
| 14939 |
|
|
|
| 14940 |
|
|
|
| 14941 |
|
|
--UD1_shift_out_92_d_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[8]
|
| 14942 |
|
|
--operation mode is normal
|
| 14943 |
|
|
|
| 14944 |
|
|
UD1_shift_out_92_d_a[8] = VD1_b_o_iv_0 & !PD1_a_o_2 & !PD1_a_o_1 & !PD1_a_o_0;
|
| 14945 |
|
|
|
| 14946 |
|
|
|
| 14947 |
|
|
--UD1_shift_out_77[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[16]
|
| 14948 |
|
|
--operation mode is normal
|
| 14949 |
|
|
|
| 14950 |
|
|
UD1_shift_out_77[16] = PD1_a_o_2 & UD1_shift_out_85_d[8] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[8] # !PD1_a_o_1 & !UD1_shift_out_77_a[16];
|
| 14951 |
|
|
|
| 14952 |
|
|
|
| 14953 |
|
|
--VD1_hilo_37_iv_0_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[16]
|
| 14954 |
|
|
--operation mode is normal
|
| 14955 |
|
|
|
| 14956 |
|
|
VD1_hilo_37_iv_0_a[16] = VD1_hilo_17 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_15 # !VD1_hilo_17 & !VD1_hilo_2_sqmuxa # !VD1_hilo_15;
|
| 14957 |
|
|
|
| 14958 |
|
|
|
| 14959 |
|
|
--VD1_hilo_37_iv_0_0[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[16]
|
| 14960 |
|
|
--operation mode is normal
|
| 14961 |
|
|
|
| 14962 |
|
|
VD1_hilo_37_iv_0_0[16] = VD1_hilo_16 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[16] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_16 & VD1_un134_hilo_combout[16] & VD1_hilo_37_iv_0_a3_0[0];
|
| 14963 |
|
|
|
| 14964 |
|
|
|
| 14965 |
|
|
--VD1_hilo_37_iv_2[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[48]
|
| 14966 |
|
|
--operation mode is normal
|
| 14967 |
|
|
|
| 14968 |
|
|
VD1_hilo_37_iv_2[48] = VD1_hilo_33_i_m[48] # VD1_hilo_37_iv_2_a[48] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[48];
|
| 14969 |
|
|
|
| 14970 |
|
|
|
| 14971 |
|
|
--VD1_hilo_37_iv_a[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[48]
|
| 14972 |
|
|
--operation mode is normal
|
| 14973 |
|
|
|
| 14974 |
|
|
VD1_hilo_37_iv_a[48] = RC1_alu_func_o_0 & !PD1_a_o_16 # !RC1_alu_func_o_0 & !VD1_hilo_48;
|
| 14975 |
|
|
|
| 14976 |
|
|
|
| 14977 |
|
|
--PD1_a_o_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[16]
|
| 14978 |
|
|
--operation mode is normal
|
| 14979 |
|
|
|
| 14980 |
|
|
PD1_a_o_a[16] = SC1_muxa_ctl_o_1 & !FB1_r32_o_16 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_16;
|
| 14981 |
|
|
|
| 14982 |
|
|
|
| 14983 |
|
|
--PD1_a_o_3_Z[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[16]
|
| 14984 |
|
|
--operation mode is normal
|
| 14985 |
|
|
|
| 14986 |
|
|
PD1_a_o_3_Z[16] = PD1_a_o_3_s[0] & SD1_r32_o_16 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[16];
|
| 14987 |
|
|
|
| 14988 |
|
|
|
| 14989 |
|
|
--TD1_un1_b_1_combout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[16]
|
| 14990 |
|
|
--operation mode is normal
|
| 14991 |
|
|
|
| 14992 |
|
|
TD1_un1_b_1_combout[16] = TD1_sum13_0_a2 $ !VD1_b_o_iv_16;
|
| 14993 |
|
|
|
| 14994 |
|
|
|
| 14995 |
|
|
--UD1_shift_out_87_d_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[17]
|
| 14996 |
|
|
--operation mode is normal
|
| 14997 |
|
|
|
| 14998 |
|
|
UD1_shift_out_87_d_a[17] = PD1_a_o_1 & !VD1_b_o_iv_23 # !PD1_a_o_1 & !VD1_b_o_iv_21;
|
| 14999 |
|
|
|
| 15000 |
|
|
|
| 15001 |
|
|
--UD1_shift_out_80[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[17]
|
| 15002 |
|
|
--operation mode is normal
|
| 15003 |
|
|
|
| 15004 |
|
|
UD1_shift_out_80[17] = PD1_a_o_2 & UD1_shift_out_80_a[17] & VD1_b_o_iv_22 # !UD1_shift_out_80_a[17] & VD1_b_o_iv_24 # !PD1_a_o_2 & !UD1_shift_out_80_a[17];
|
| 15005 |
|
|
|
| 15006 |
|
|
|
| 15007 |
|
|
--UD1_shift_out_77_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[23]
|
| 15008 |
|
|
--operation mode is normal
|
| 15009 |
|
|
|
| 15010 |
|
|
UD1_shift_out_77_a[23] = PD1_a_o_0 & !VD1_b_o_iv_14 # !PD1_a_o_0 & !VD1_b_o_iv_15;
|
| 15011 |
|
|
|
| 15012 |
|
|
|
| 15013 |
|
|
--UD1_shift_out_52[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52[29]
|
| 15014 |
|
|
--operation mode is normal
|
| 15015 |
|
|
|
| 15016 |
|
|
UD1_shift_out_52[29] = PD1_a_o_1 & !UD1_shift_out_52_a[29] # !PD1_a_o_1 & UD1_shift_out_52_a[29] & VD1_b_o_iv_13 # !UD1_shift_out_52_a[29] & VD1_b_o_iv_12;
|
| 15017 |
|
|
|
| 15018 |
|
|
|
| 15019 |
|
|
--UD1_shift_out_83_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83_a[17]
|
| 15020 |
|
|
--operation mode is normal
|
| 15021 |
|
|
|
| 15022 |
|
|
UD1_shift_out_83_a[17] = UD1_shift_out587 & PD1_a_o_2 & PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_2 & !PD1_a_o_1 # !UD1_shift_out587 & PD1_a_o_1;
|
| 15023 |
|
|
|
| 15024 |
|
|
|
| 15025 |
|
|
--UD1_shift_out_63[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[17]
|
| 15026 |
|
|
--operation mode is normal
|
| 15027 |
|
|
|
| 15028 |
|
|
UD1_shift_out_63[17] = UD1_shift_out_63_a[17] & PD1_a_o_0 & VD1_b_o_iv_0 # !PD1_a_o_0 & VD1_b_o_iv_1;
|
| 15029 |
|
|
|
| 15030 |
|
|
|
| 15031 |
|
|
--UD1_shift_out_63[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[25]
|
| 15032 |
|
|
--operation mode is normal
|
| 15033 |
|
|
|
| 15034 |
|
|
UD1_shift_out_63[25] = PD1_a_o_2 & UD1_shift_out_45[29] # !PD1_a_o_2 & UD1_shift_out_48[29];
|
| 15035 |
|
|
|
| 15036 |
|
|
|
| 15037 |
|
|
--VD1_hilo_37_iv_0_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[17]
|
| 15038 |
|
|
--operation mode is normal
|
| 15039 |
|
|
|
| 15040 |
|
|
VD1_hilo_37_iv_0_a[17] = VD1_hilo_16 & !VD1_hilo_2_sqmuxa & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_18 # !VD1_hilo_16 & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_18;
|
| 15041 |
|
|
|
| 15042 |
|
|
|
| 15043 |
|
|
--VD1_hilo_37_iv_0_0[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[17]
|
| 15044 |
|
|
--operation mode is normal
|
| 15045 |
|
|
|
| 15046 |
|
|
VD1_hilo_37_iv_0_0[17] = VD1_hilo_17 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[17] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_17 & VD1_un134_hilo_combout[17] & VD1_hilo_37_iv_0_a3_0[0];
|
| 15047 |
|
|
|
| 15048 |
|
|
|
| 15049 |
|
|
--VD1_hilo_37_iv_2[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[49]
|
| 15050 |
|
|
--operation mode is normal
|
| 15051 |
|
|
|
| 15052 |
|
|
VD1_hilo_37_iv_2[49] = VD1_hilo_33_i_m[49] # VD1_hilo_37_iv_2_a[49] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[49];
|
| 15053 |
|
|
|
| 15054 |
|
|
|
| 15055 |
|
|
--VD1_hilo_37_iv_a[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[49]
|
| 15056 |
|
|
--operation mode is normal
|
| 15057 |
|
|
|
| 15058 |
|
|
VD1_hilo_37_iv_a[49] = RC1_alu_func_o_0 & !PD1_a_o_17 # !RC1_alu_func_o_0 & !VD1_hilo_49;
|
| 15059 |
|
|
|
| 15060 |
|
|
|
| 15061 |
|
|
--PD1_a_o_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[17]
|
| 15062 |
|
|
--operation mode is normal
|
| 15063 |
|
|
|
| 15064 |
|
|
PD1_a_o_a[17] = SC1_muxa_ctl_o_1 & !FB1_r32_o_17 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_17;
|
| 15065 |
|
|
|
| 15066 |
|
|
|
| 15067 |
|
|
--PD1_a_o_3_Z[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[17]
|
| 15068 |
|
|
--operation mode is normal
|
| 15069 |
|
|
|
| 15070 |
|
|
PD1_a_o_3_Z[17] = PD1_a_o_3_s[0] & SD1_r32_o_17 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[17];
|
| 15071 |
|
|
|
| 15072 |
|
|
|
| 15073 |
|
|
--TD1_un1_b_1_combout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[17]
|
| 15074 |
|
|
--operation mode is normal
|
| 15075 |
|
|
|
| 15076 |
|
|
TD1_un1_b_1_combout[17] = TD1_sum13_0_a2 $ !VD1_b_o_iv_17;
|
| 15077 |
|
|
|
| 15078 |
|
|
|
| 15079 |
|
|
--UD1_shift_out_87_d_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[14]
|
| 15080 |
|
|
--operation mode is normal
|
| 15081 |
|
|
|
| 15082 |
|
|
UD1_shift_out_87_d_a[14] = PD1_a_o_1 & !VD1_b_o_iv_20 # !PD1_a_o_1 & !VD1_b_o_iv_18;
|
| 15083 |
|
|
|
| 15084 |
|
|
|
| 15085 |
|
|
--UD1_shift_out_80[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[14]
|
| 15086 |
|
|
--operation mode is normal
|
| 15087 |
|
|
|
| 15088 |
|
|
UD1_shift_out_80[14] = PD1_a_o_2 & UD1_shift_out_80_a[14] & VD1_b_o_iv_19 # !UD1_shift_out_80_a[14] & VD1_b_o_iv_21 # !PD1_a_o_2 & !UD1_shift_out_80_a[14];
|
| 15089 |
|
|
|
| 15090 |
|
|
|
| 15091 |
|
|
--UD1_shift_out_85_d_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[14]
|
| 15092 |
|
|
--operation mode is normal
|
| 15093 |
|
|
|
| 15094 |
|
|
UD1_shift_out_85_d_a[14] = PD1_a_o_0 & !VD1_b_o_iv_11 # !PD1_a_o_0 & !VD1_b_o_iv_12;
|
| 15095 |
|
|
|
| 15096 |
|
|
|
| 15097 |
|
|
--UD1_shift_out_48[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48[30]
|
| 15098 |
|
|
--operation mode is normal
|
| 15099 |
|
|
|
| 15100 |
|
|
UD1_shift_out_48[30] = PD1_a_o_1 & !UD1_shift_out_48_a[30] # !PD1_a_o_1 & UD1_shift_out_48_a[30] & VD1_b_o_iv_10 # !UD1_shift_out_48_a[30] & VD1_b_o_iv_9;
|
| 15101 |
|
|
|
| 15102 |
|
|
|
| 15103 |
|
|
--UD1_shift_out_74_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[14]
|
| 15104 |
|
|
--operation mode is normal
|
| 15105 |
|
|
|
| 15106 |
|
|
UD1_shift_out_74_a[14] = !PD1_a_o_3 & !PD1_a_o_2 & VD1_b_o_iv_30 $ VD1_b_o_iv_31;
|
| 15107 |
|
|
|
| 15108 |
|
|
|
| 15109 |
|
|
--UD1_shift_out_83_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83_a[14]
|
| 15110 |
|
|
--operation mode is normal
|
| 15111 |
|
|
|
| 15112 |
|
|
UD1_shift_out_83_a[14] = !PD1_a_o_1 & PD1_a_o_0 & VD1_b_o_iv_31 # !PD1_a_o_0 & VD1_b_o_iv_30;
|
| 15113 |
|
|
|
| 15114 |
|
|
|
| 15115 |
|
|
--UD1_shift_out_45[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45[30]
|
| 15116 |
|
|
--operation mode is normal
|
| 15117 |
|
|
|
| 15118 |
|
|
UD1_shift_out_45[30] = PD1_a_o_1 & !UD1_shift_out_45_a[30] # !PD1_a_o_1 & UD1_shift_out_45_a[30] & VD1_b_o_iv_6 # !UD1_shift_out_45_a[30] & VD1_b_o_iv_5;
|
| 15119 |
|
|
|
| 15120 |
|
|
|
| 15121 |
|
|
--UD1_shift_out_79[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[14]
|
| 15122 |
|
|
--operation mode is normal
|
| 15123 |
|
|
|
| 15124 |
|
|
UD1_shift_out_79[14] = PD1_a_o_1 & UD1_shift_out_79_a[14] & VD1_b_o_iv_24 # !UD1_shift_out_79_a[14] & VD1_b_o_iv_25 # !PD1_a_o_1 & !UD1_shift_out_79_a[14];
|
| 15125 |
|
|
|
| 15126 |
|
|
|
| 15127 |
|
|
--VD1_hilo_37_iv_0_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[14]
|
| 15128 |
|
|
--operation mode is normal
|
| 15129 |
|
|
|
| 15130 |
|
|
VD1_hilo_37_iv_0_a[14] = VD1_hilo_15 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_13 # !VD1_hilo_15 & !VD1_hilo_2_sqmuxa # !VD1_hilo_13;
|
| 15131 |
|
|
|
| 15132 |
|
|
|
| 15133 |
|
|
--VD1_hilo_37_iv_0_0[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[14]
|
| 15134 |
|
|
--operation mode is normal
|
| 15135 |
|
|
|
| 15136 |
|
|
VD1_hilo_37_iv_0_0[14] = VD1_hilo_14 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[14] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_14 & VD1_un134_hilo_combout[14] & VD1_hilo_37_iv_0_a3_0[0];
|
| 15137 |
|
|
|
| 15138 |
|
|
|
| 15139 |
|
|
--VD1_hilo_37_iv_2[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[46]
|
| 15140 |
|
|
--operation mode is normal
|
| 15141 |
|
|
|
| 15142 |
|
|
VD1_hilo_37_iv_2[46] = VD1_hilo_33_i_m[46] # VD1_hilo_37_iv_2_a[46] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[46];
|
| 15143 |
|
|
|
| 15144 |
|
|
|
| 15145 |
|
|
--VD1_hilo_37_iv_a[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[46]
|
| 15146 |
|
|
--operation mode is normal
|
| 15147 |
|
|
|
| 15148 |
|
|
VD1_hilo_37_iv_a[46] = RC1_alu_func_o_0 & !PD1_a_o_14 # !RC1_alu_func_o_0 & !VD1_hilo_46;
|
| 15149 |
|
|
|
| 15150 |
|
|
|
| 15151 |
|
|
--PD1_a_o_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[14]
|
| 15152 |
|
|
--operation mode is normal
|
| 15153 |
|
|
|
| 15154 |
|
|
PD1_a_o_a[14] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_14 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_14;
|
| 15155 |
|
|
|
| 15156 |
|
|
|
| 15157 |
|
|
--PD1_a_o_3_Z[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[14]
|
| 15158 |
|
|
--operation mode is normal
|
| 15159 |
|
|
|
| 15160 |
|
|
PD1_a_o_3_Z[14] = PD1_a_o_3_s[0] & SD1_r32_o_14 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[14];
|
| 15161 |
|
|
|
| 15162 |
|
|
|
| 15163 |
|
|
--TD1_un1_b_1_combout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[14]
|
| 15164 |
|
|
--operation mode is normal
|
| 15165 |
|
|
|
| 15166 |
|
|
TD1_un1_b_1_combout[14] = TD1_sum13_0_a2 $ !VD1_b_o_iv_14;
|
| 15167 |
|
|
|
| 15168 |
|
|
|
| 15169 |
|
|
--UD1_shift_out_87_d_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[15]
|
| 15170 |
|
|
--operation mode is normal
|
| 15171 |
|
|
|
| 15172 |
|
|
UD1_shift_out_87_d_a[15] = PD1_a_o_1 & !VD1_b_o_iv_21 # !PD1_a_o_1 & !VD1_b_o_iv_19;
|
| 15173 |
|
|
|
| 15174 |
|
|
|
| 15175 |
|
|
--UD1_shift_out_80[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[15]
|
| 15176 |
|
|
--operation mode is normal
|
| 15177 |
|
|
|
| 15178 |
|
|
UD1_shift_out_80[15] = PD1_a_o_2 & UD1_shift_out_80_a[15] & VD1_b_o_iv_20 # !UD1_shift_out_80_a[15] & VD1_b_o_iv_22 # !PD1_a_o_2 & !UD1_shift_out_80_a[15];
|
| 15179 |
|
|
|
| 15180 |
|
|
|
| 15181 |
|
|
--UD1_shift_out_77_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[21]
|
| 15182 |
|
|
--operation mode is normal
|
| 15183 |
|
|
|
| 15184 |
|
|
UD1_shift_out_77_a[21] = PD1_a_o_0 & !VD1_b_o_iv_12 # !PD1_a_o_0 & !VD1_b_o_iv_13;
|
| 15185 |
|
|
|
| 15186 |
|
|
|
| 15187 |
|
|
--UD1_shift_out_48[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48[31]
|
| 15188 |
|
|
--operation mode is normal
|
| 15189 |
|
|
|
| 15190 |
|
|
UD1_shift_out_48[31] = PD1_a_o_1 & !UD1_shift_out_48_a[31] # !PD1_a_o_1 & UD1_shift_out_48_a[31] & VD1_b_o_iv_11 # !UD1_shift_out_48_a[31] & VD1_b_o_iv_10;
|
| 15191 |
|
|
|
| 15192 |
|
|
|
| 15193 |
|
|
--UD1_shift_out_83_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83_a[15]
|
| 15194 |
|
|
--operation mode is normal
|
| 15195 |
|
|
|
| 15196 |
|
|
UD1_shift_out_83_a[15] = VD1_b_o_iv_31 & !PD1_a_o_1 & !PD1_a_o_0;
|
| 15197 |
|
|
|
| 15198 |
|
|
|
| 15199 |
|
|
--UD1_shift_out_45[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45[31]
|
| 15200 |
|
|
--operation mode is normal
|
| 15201 |
|
|
|
| 15202 |
|
|
UD1_shift_out_45[31] = PD1_a_o_1 & !UD1_shift_out_45_a[31] # !PD1_a_o_1 & UD1_shift_out_45_a[31] & VD1_b_o_iv_7 # !UD1_shift_out_45_a[31] & VD1_b_o_iv_6;
|
| 15203 |
|
|
|
| 15204 |
|
|
|
| 15205 |
|
|
--VD1_hilo_37_iv_0_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[15]
|
| 15206 |
|
|
--operation mode is normal
|
| 15207 |
|
|
|
| 15208 |
|
|
VD1_hilo_37_iv_0_a[15] = VD1_hilo_16 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_14 # !VD1_hilo_16 & !VD1_hilo_2_sqmuxa # !VD1_hilo_14;
|
| 15209 |
|
|
|
| 15210 |
|
|
|
| 15211 |
|
|
--VD1_hilo_37_iv_0_0[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[15]
|
| 15212 |
|
|
--operation mode is normal
|
| 15213 |
|
|
|
| 15214 |
|
|
VD1_hilo_37_iv_0_0[15] = VD1_hilo_15 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[15] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_15 & VD1_un134_hilo_combout[15] & VD1_hilo_37_iv_0_a3_0[0];
|
| 15215 |
|
|
|
| 15216 |
|
|
|
| 15217 |
|
|
--VD1_hilo_37_iv_2[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[47]
|
| 15218 |
|
|
--operation mode is normal
|
| 15219 |
|
|
|
| 15220 |
|
|
VD1_hilo_37_iv_2[47] = VD1_hilo_33_i_m[47] # VD1_hilo_37_iv_2_a[47] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[47];
|
| 15221 |
|
|
|
| 15222 |
|
|
|
| 15223 |
|
|
--VD1_hilo_37_iv_a[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[47]
|
| 15224 |
|
|
--operation mode is normal
|
| 15225 |
|
|
|
| 15226 |
|
|
VD1_hilo_37_iv_a[47] = RC1_alu_func_o_0 & !PD1_a_o_15 # !RC1_alu_func_o_0 & !VD1_hilo_47;
|
| 15227 |
|
|
|
| 15228 |
|
|
|
| 15229 |
|
|
--PD1_a_o_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[15]
|
| 15230 |
|
|
--operation mode is normal
|
| 15231 |
|
|
|
| 15232 |
|
|
PD1_a_o_a[15] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_15 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_15;
|
| 15233 |
|
|
|
| 15234 |
|
|
|
| 15235 |
|
|
--PD1_a_o_3_Z[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[15]
|
| 15236 |
|
|
--operation mode is normal
|
| 15237 |
|
|
|
| 15238 |
|
|
PD1_a_o_3_Z[15] = PD1_a_o_3_s[0] & SD1_r32_o_15 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[15];
|
| 15239 |
|
|
|
| 15240 |
|
|
|
| 15241 |
|
|
--TD1_un1_b_1_combout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[15]
|
| 15242 |
|
|
--operation mode is normal
|
| 15243 |
|
|
|
| 15244 |
|
|
TD1_un1_b_1_combout[15] = TD1_sum13_0_a2 $ !VD1_b_o_iv_15;
|
| 15245 |
|
|
|
| 15246 |
|
|
|
| 15247 |
|
|
--UD1_shift_out_68[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[31]
|
| 15248 |
|
|
--operation mode is normal
|
| 15249 |
|
|
|
| 15250 |
|
|
UD1_shift_out_68[31] = PD1_a_o_0 & VD1_b_o_iv_28 # !PD1_a_o_0 & VD1_b_o_iv_29;
|
| 15251 |
|
|
|
| 15252 |
|
|
|
| 15253 |
|
|
--UD1_shift_out_75[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[31]
|
| 15254 |
|
|
--operation mode is normal
|
| 15255 |
|
|
|
| 15256 |
|
|
UD1_shift_out_75[31] = PD1_a_o_3 & !UD1_shift_out_75_a[31] # !PD1_a_o_3 & UD1_shift_out_75_a[31] & UD1_shift_out_52[31] # !UD1_shift_out_75_a[31] & UD1_shift_out_48[31];
|
| 15257 |
|
|
|
| 15258 |
|
|
|
| 15259 |
|
|
--UD1_shift_out_77[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[31]
|
| 15260 |
|
|
--operation mode is normal
|
| 15261 |
|
|
|
| 15262 |
|
|
UD1_shift_out_77[31] = PD1_a_o_2 & !UD1_shift_out_85_a[23] # !PD1_a_o_2 & UD1_shift_out_85_a[23] & UD1_shift_out_68[25] # !UD1_shift_out_85_a[23] & UD1_shift_out_68[23];
|
| 15263 |
|
|
|
| 15264 |
|
|
|
| 15265 |
|
|
--VD1_hilo_37_iv_0_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[31]
|
| 15266 |
|
|
--operation mode is normal
|
| 15267 |
|
|
|
| 15268 |
|
|
VD1_hilo_37_iv_0_a[31] = !VD1_hilo_37_iv_0_2[31] & !VD1_hilo_37_iv_0_1[31] & !VD1_hilo_2_sqmuxa # !VD1_hilo_30;
|
| 15269 |
|
|
|
| 15270 |
|
|
|
| 15271 |
|
|
--VD1_hilo_37_iv_2[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[63]
|
| 15272 |
|
|
--operation mode is normal
|
| 15273 |
|
|
|
| 15274 |
|
|
VD1_hilo_37_iv_2[63] = VD1_hilo_22_i_m[63] # VD1_hilo_37_iv_2_a[63] # VD1_hilo_3_sqmuxa & !VD1_hilo_33_3[63];
|
| 15275 |
|
|
|
| 15276 |
|
|
|
| 15277 |
|
|
--VD1_hilo_37_iv_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[63]
|
| 15278 |
|
|
--operation mode is normal
|
| 15279 |
|
|
|
| 15280 |
|
|
VD1_hilo_37_iv_a[63] = RC1_alu_func_o_0 & !PD1_a_o_31 # !RC1_alu_func_o_0 & !VD1_hilo_63;
|
| 15281 |
|
|
|
| 15282 |
|
|
|
| 15283 |
|
|
--TD1_un1_b_1_combout[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[31]
|
| 15284 |
|
|
--operation mode is normal
|
| 15285 |
|
|
|
| 15286 |
|
|
TD1_un1_b_1_combout[31] = TD1_sum13_0_a2 $ !VD1_b_o_iv_31;
|
| 15287 |
|
|
|
| 15288 |
|
|
|
| 15289 |
|
|
--UD1_shift_out_87_d[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[8]
|
| 15290 |
|
|
--operation mode is normal
|
| 15291 |
|
|
|
| 15292 |
|
|
UD1_shift_out_87_d[8] = PD1_a_o_0 & UD1_shift_out_80[8] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[8];
|
| 15293 |
|
|
|
| 15294 |
|
|
|
| 15295 |
|
|
--UD1_shift_out_85_d[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[8]
|
| 15296 |
|
|
--operation mode is normal
|
| 15297 |
|
|
|
| 15298 |
|
|
UD1_shift_out_85_d[8] = PD1_a_o_2 & UD1_shift_out_45[28] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[8];
|
| 15299 |
|
|
|
| 15300 |
|
|
|
| 15301 |
|
|
--UD1_shift_out_86_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[8]
|
| 15302 |
|
|
--operation mode is normal
|
| 15303 |
|
|
|
| 15304 |
|
|
UD1_shift_out_86_a[8] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_47[0] # !PD1_a_o_2 & !UD1_shift_out_79[16] # !UD1_shift_out587 & !UD1_shift_out_47[0];
|
| 15305 |
|
|
|
| 15306 |
|
|
|
| 15307 |
|
|
--UD1_shift_out_74[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[8]
|
| 15308 |
|
|
--operation mode is normal
|
| 15309 |
|
|
|
| 15310 |
|
|
UD1_shift_out_74[8] = PD1_a_o_3 & !UD1_shift_out_74_a[7] # !PD1_a_o_3 & UD1_shift_out_74_a[7] & UD1_shift_out_79[16] # !UD1_shift_out_74_a[7] & UD1_shift_out_79[20];
|
| 15311 |
|
|
|
| 15312 |
|
|
|
| 15313 |
|
|
--UD1_shift_out_91[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[8]
|
| 15314 |
|
|
--operation mode is normal
|
| 15315 |
|
|
|
| 15316 |
|
|
UD1_shift_out_91[8] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[8] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[8];
|
| 15317 |
|
|
|
| 15318 |
|
|
|
| 15319 |
|
|
--PD1_a_o_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_8
|
| 15320 |
|
|
--operation mode is normal
|
| 15321 |
|
|
|
| 15322 |
|
|
PD1_a_o_8 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[8] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[8];
|
| 15323 |
|
|
|
| 15324 |
|
|
|
| 15325 |
|
|
--TD1_m16_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m16_a
|
| 15326 |
|
|
--operation mode is normal
|
| 15327 |
|
|
|
| 15328 |
|
|
TD1_m16_a = VD1_b_o_iv_8 & !TD1_m9 & PD1_a_o_8 # !VD1_b_o_iv_8 & !PD1_a_o_8 # !TD1_m5;
|
| 15329 |
|
|
|
| 15330 |
|
|
|
| 15331 |
|
|
--TD1_un1_a_add8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add8
|
| 15332 |
|
|
--operation mode is arithmetic
|
| 15333 |
|
|
|
| 15334 |
|
|
TD1_un1_a_add8_carry_eqn = TD1_un1_a_carry_7;
|
| 15335 |
|
|
TD1_un1_a_add8 = PD1_a_o_8 $ TD1_un1_b_1_combout[8] $ !TD1_un1_a_add8_carry_eqn;
|
| 15336 |
|
|
|
| 15337 |
|
|
--TD1_un1_a_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_8
|
| 15338 |
|
|
--operation mode is arithmetic
|
| 15339 |
|
|
|
| 15340 |
|
|
TD1_un1_a_carry_8 = CARRY(PD1_a_o_8 & TD1_un1_b_1_combout[8] # !TD1_un1_a_carry_7 # !PD1_a_o_8 & TD1_un1_b_1_combout[8] & !TD1_un1_a_carry_7);
|
| 15341 |
|
|
|
| 15342 |
|
|
|
| 15343 |
|
|
--UD1_shift_out_87_d[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[9]
|
| 15344 |
|
|
--operation mode is normal
|
| 15345 |
|
|
|
| 15346 |
|
|
UD1_shift_out_87_d[9] = PD1_a_o_0 & UD1_shift_out_80[9] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[9];
|
| 15347 |
|
|
|
| 15348 |
|
|
|
| 15349 |
|
|
--UD1_shift_out_85_d[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[9]
|
| 15350 |
|
|
--operation mode is normal
|
| 15351 |
|
|
|
| 15352 |
|
|
UD1_shift_out_85_d[9] = PD1_a_o_2 & UD1_shift_out_45[29] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[9];
|
| 15353 |
|
|
|
| 15354 |
|
|
|
| 15355 |
|
|
--UD1_shift_out_74[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[9]
|
| 15356 |
|
|
--operation mode is normal
|
| 15357 |
|
|
|
| 15358 |
|
|
UD1_shift_out_74[9] = PD1_a_o_3 & !UD1_shift_out_74_a[9] # !PD1_a_o_3 & PD1_a_o_2 & !UD1_shift_out_74_a[9] # !PD1_a_o_2 & UD1_shift_out_79[17];
|
| 15359 |
|
|
|
| 15360 |
|
|
|
| 15361 |
|
|
--UD1_shift_out_86_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[9]
|
| 15362 |
|
|
--operation mode is normal
|
| 15363 |
|
|
|
| 15364 |
|
|
UD1_shift_out_86_a[9] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[13] # !PD1_a_o_2 & !UD1_shift_out_79[17] # !UD1_shift_out587 & !UD1_shift_out_79[13];
|
| 15365 |
|
|
|
| 15366 |
|
|
|
| 15367 |
|
|
--UD1_shift_out_92_d_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[9]
|
| 15368 |
|
|
--operation mode is normal
|
| 15369 |
|
|
|
| 15370 |
|
|
UD1_shift_out_92_d_a[9] = !PD1_a_o_4 & PD1_a_o_0 & VD1_b_o_iv_0 # !PD1_a_o_0 & VD1_b_o_iv_1;
|
| 15371 |
|
|
|
| 15372 |
|
|
|
| 15373 |
|
|
--UD1_shift_out_91[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[9]
|
| 15374 |
|
|
--operation mode is normal
|
| 15375 |
|
|
|
| 15376 |
|
|
UD1_shift_out_91[9] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[9] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[9];
|
| 15377 |
|
|
|
| 15378 |
|
|
|
| 15379 |
|
|
--VD1_hilo_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_9
|
| 15380 |
|
|
--operation mode is normal
|
| 15381 |
|
|
|
| 15382 |
|
|
VD1_hilo_9_lut_out = VD1_hilo_37_iv_0_0[9] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_9 # !VD1_hilo_37_iv_0_a[9];
|
| 15383 |
|
|
VD1_hilo_9 = DFFEAS(VD1_hilo_9_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15384 |
|
|
|
| 15385 |
|
|
|
| 15386 |
|
|
--VD1_hilo_41 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_41
|
| 15387 |
|
|
--operation mode is normal
|
| 15388 |
|
|
|
| 15389 |
|
|
VD1_hilo_41_lut_out = !VD1_hilo_37_iv_2[41] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[41] # !VD1_hilo25;
|
| 15390 |
|
|
VD1_hilo_41 = DFFEAS(VD1_hilo_41_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15391 |
|
|
|
| 15392 |
|
|
|
| 15393 |
|
|
--PD1_a_o_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_9
|
| 15394 |
|
|
--operation mode is normal
|
| 15395 |
|
|
|
| 15396 |
|
|
PD1_a_o_9 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[9] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[9];
|
| 15397 |
|
|
|
| 15398 |
|
|
|
| 15399 |
|
|
--TD1_m117_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m117_a
|
| 15400 |
|
|
--operation mode is normal
|
| 15401 |
|
|
|
| 15402 |
|
|
TD1_m117_a = VD1_b_o_iv_9 & !TD1_m9 & PD1_a_o_9 # !VD1_b_o_iv_9 & !TD1_m5 # !PD1_a_o_9;
|
| 15403 |
|
|
|
| 15404 |
|
|
|
| 15405 |
|
|
--VD1_hilo_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_10
|
| 15406 |
|
|
--operation mode is normal
|
| 15407 |
|
|
|
| 15408 |
|
|
VD1_hilo_10_lut_out = VD1_hilo_37_iv_0_0[10] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_10 # !VD1_hilo_37_iv_0_a[10];
|
| 15409 |
|
|
VD1_hilo_10 = DFFEAS(VD1_hilo_10_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15410 |
|
|
|
| 15411 |
|
|
|
| 15412 |
|
|
--VD1_hilo_42 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_42
|
| 15413 |
|
|
--operation mode is normal
|
| 15414 |
|
|
|
| 15415 |
|
|
VD1_hilo_42_lut_out = !VD1_hilo_37_iv_2[42] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[42] # !VD1_hilo25;
|
| 15416 |
|
|
VD1_hilo_42 = DFFEAS(VD1_hilo_42_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15417 |
|
|
|
| 15418 |
|
|
|
| 15419 |
|
|
--TD1_alu_out_7_0_0_m4_0[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[10]
|
| 15420 |
|
|
--operation mode is normal
|
| 15421 |
|
|
|
| 15422 |
|
|
TD1_alu_out_7_0_0_m4_0[10] = VD1_b_o_iv_10 & TD1_alu_out_7_0_0_o3_0 & TD1_alu_out_0_a3[28] # !VD1_b_o_iv_10 & TD1_alu_out_7_0_0_m4_0_a[3];
|
| 15423 |
|
|
|
| 15424 |
|
|
|
| 15425 |
|
|
--TD1_alu_out_0_a2_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_a[10]
|
| 15426 |
|
|
--operation mode is normal
|
| 15427 |
|
|
|
| 15428 |
|
|
TD1_alu_out_0_a2_a[10] = VD1_b_o_iv_10 & !TD1_m107 # !VD1_b_o_iv_10 & !TD1_alu_out_0_a3[28];
|
| 15429 |
|
|
|
| 15430 |
|
|
|
| 15431 |
|
|
--PD1_a_o_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[10]
|
| 15432 |
|
|
--operation mode is normal
|
| 15433 |
|
|
|
| 15434 |
|
|
PD1_a_o_a[10] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_10 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_10;
|
| 15435 |
|
|
|
| 15436 |
|
|
|
| 15437 |
|
|
--PD1_a_o_3_Z[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[10]
|
| 15438 |
|
|
--operation mode is normal
|
| 15439 |
|
|
|
| 15440 |
|
|
PD1_a_o_3_Z[10] = PD1_a_o_3_s[0] & SD1_r32_o_10 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[10];
|
| 15441 |
|
|
|
| 15442 |
|
|
|
| 15443 |
|
|
--TD1_un1_b_1_combout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[9]
|
| 15444 |
|
|
--operation mode is normal
|
| 15445 |
|
|
|
| 15446 |
|
|
TD1_un1_b_1_combout[9] = TD1_sum13_0_a2 $ !VD1_b_o_iv_9;
|
| 15447 |
|
|
|
| 15448 |
|
|
|
| 15449 |
|
|
--UD1_shift_out_87[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[10]
|
| 15450 |
|
|
--operation mode is normal
|
| 15451 |
|
|
|
| 15452 |
|
|
UD1_shift_out_87[10] = PD1_a_o_2 & UD1_shift_out_87_d[10] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[10] # !PD1_a_o_0 & VD1_b_o_iv_12;
|
| 15453 |
|
|
|
| 15454 |
|
|
|
| 15455 |
|
|
--UD1_shift_out_89_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[10]
|
| 15456 |
|
|
--operation mode is normal
|
| 15457 |
|
|
|
| 15458 |
|
|
UD1_shift_out_89_a[10] = PD1_a_o_2 & !UD1_shift_out_85_d[10] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[10] # !PD1_a_o_1 & !VD1_b_o_iv_9;
|
| 15459 |
|
|
|
| 15460 |
|
|
|
| 15461 |
|
|
--UD1_shift_out_91[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[10]
|
| 15462 |
|
|
--operation mode is normal
|
| 15463 |
|
|
|
| 15464 |
|
|
UD1_shift_out_91[10] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[10] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[10];
|
| 15465 |
|
|
|
| 15466 |
|
|
|
| 15467 |
|
|
--UD1_shift_out_92_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_a[10]
|
| 15468 |
|
|
--operation mode is normal
|
| 15469 |
|
|
|
| 15470 |
|
|
UD1_shift_out_92_a[10] = UD1_shift_out586 & !PD1_a_o_4 & UD1_shift_out_77[10] # !UD1_shift_out586 & UD1_shift_out_86[10];
|
| 15471 |
|
|
|
| 15472 |
|
|
|
| 15473 |
|
|
--UD1_shift_out_87_d[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[11]
|
| 15474 |
|
|
--operation mode is normal
|
| 15475 |
|
|
|
| 15476 |
|
|
UD1_shift_out_87_d[11] = PD1_a_o_0 & UD1_shift_out_80[11] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[11];
|
| 15477 |
|
|
|
| 15478 |
|
|
|
| 15479 |
|
|
--UD1_shift_out_85_d[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[11]
|
| 15480 |
|
|
--operation mode is normal
|
| 15481 |
|
|
|
| 15482 |
|
|
UD1_shift_out_85_d[11] = PD1_a_o_2 & UD1_shift_out_45[31] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[11];
|
| 15483 |
|
|
|
| 15484 |
|
|
|
| 15485 |
|
|
--UD1_shift_out_74[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[11]
|
| 15486 |
|
|
--operation mode is normal
|
| 15487 |
|
|
|
| 15488 |
|
|
UD1_shift_out_74[11] = PD1_a_o_3 & VD1_b_o_iv_31 # !PD1_a_o_3 & PD1_a_o_2 & VD1_b_o_iv_31 # !PD1_a_o_2 & UD1_shift_out_79[19];
|
| 15489 |
|
|
|
| 15490 |
|
|
|
| 15491 |
|
|
--UD1_shift_out_86_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[11]
|
| 15492 |
|
|
--operation mode is normal
|
| 15493 |
|
|
|
| 15494 |
|
|
UD1_shift_out_86_a[11] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[15] # !PD1_a_o_2 & !UD1_shift_out_79[19] # !UD1_shift_out587 & !UD1_shift_out_79[15];
|
| 15495 |
|
|
|
| 15496 |
|
|
|
| 15497 |
|
|
--UD1_shift_out_77[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[11]
|
| 15498 |
|
|
--operation mode is normal
|
| 15499 |
|
|
|
| 15500 |
|
|
UD1_shift_out_77[11] = !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d_a[5] # !PD1_a_o_1 & UD1_shift_out_68[5];
|
| 15501 |
|
|
|
| 15502 |
|
|
|
| 15503 |
|
|
--UD1_shift_out_91[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[11]
|
| 15504 |
|
|
--operation mode is normal
|
| 15505 |
|
|
|
| 15506 |
|
|
UD1_shift_out_91[11] = UD1_shift_out_sn_m17_0 & UD1_shift_out_88[11] # !UD1_shift_out_sn_m17_0 & UD1_shift_out587 & UD1_shift_out_91_a[11];
|
| 15507 |
|
|
|
| 15508 |
|
|
|
| 15509 |
|
|
--VD1_hilo_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_11
|
| 15510 |
|
|
--operation mode is normal
|
| 15511 |
|
|
|
| 15512 |
|
|
VD1_hilo_11_lut_out = VD1_hilo_37_iv_0_0[11] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_11 # !VD1_hilo_37_iv_0_a[11];
|
| 15513 |
|
|
VD1_hilo_11 = DFFEAS(VD1_hilo_11_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15514 |
|
|
|
| 15515 |
|
|
|
| 15516 |
|
|
--VD1_hilo_43 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_43
|
| 15517 |
|
|
--operation mode is normal
|
| 15518 |
|
|
|
| 15519 |
|
|
VD1_hilo_43_lut_out = !VD1_hilo_37_iv_2[43] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[43] # !VD1_hilo25;
|
| 15520 |
|
|
VD1_hilo_43 = DFFEAS(VD1_hilo_43_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15521 |
|
|
|
| 15522 |
|
|
|
| 15523 |
|
|
--PD1_a_o_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_11
|
| 15524 |
|
|
--operation mode is normal
|
| 15525 |
|
|
|
| 15526 |
|
|
PD1_a_o_11 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[11] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[11];
|
| 15527 |
|
|
|
| 15528 |
|
|
|
| 15529 |
|
|
--TD1_m21_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m21_a
|
| 15530 |
|
|
--operation mode is normal
|
| 15531 |
|
|
|
| 15532 |
|
|
TD1_m21_a = VD1_b_o_iv_11 & !TD1_m9 & PD1_a_o_11 # !VD1_b_o_iv_11 & !TD1_m5 # !PD1_a_o_11;
|
| 15533 |
|
|
|
| 15534 |
|
|
|
| 15535 |
|
|
--TD1_un1_a_add11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add11
|
| 15536 |
|
|
--operation mode is arithmetic
|
| 15537 |
|
|
|
| 15538 |
|
|
TD1_un1_a_add11_carry_eqn = TD1_un1_a_carry_10;
|
| 15539 |
|
|
TD1_un1_a_add11 = PD1_a_o_11 $ TD1_un1_b_1_combout[11] $ TD1_un1_a_add11_carry_eqn;
|
| 15540 |
|
|
|
| 15541 |
|
|
--TD1_un1_a_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_11
|
| 15542 |
|
|
--operation mode is arithmetic
|
| 15543 |
|
|
|
| 15544 |
|
|
TD1_un1_a_carry_11 = CARRY(PD1_a_o_11 & !TD1_un1_b_1_combout[11] & !TD1_un1_a_carry_10 # !PD1_a_o_11 & !TD1_un1_a_carry_10 # !TD1_un1_b_1_combout[11]);
|
| 15545 |
|
|
|
| 15546 |
|
|
|
| 15547 |
|
|
--UD1_shift_out_87_d_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[21]
|
| 15548 |
|
|
--operation mode is normal
|
| 15549 |
|
|
|
| 15550 |
|
|
UD1_shift_out_87_d_a[21] = PD1_a_o_1 & !VD1_b_o_iv_27 # !PD1_a_o_1 & !VD1_b_o_iv_25;
|
| 15551 |
|
|
|
| 15552 |
|
|
|
| 15553 |
|
|
--UD1_shift_out_80[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[21]
|
| 15554 |
|
|
--operation mode is normal
|
| 15555 |
|
|
|
| 15556 |
|
|
UD1_shift_out_80[21] = PD1_a_o_2 & UD1_shift_out_80_a[21] & VD1_b_o_iv_26 # !UD1_shift_out_80_a[21] & VD1_b_o_iv_28 # !PD1_a_o_2 & !UD1_shift_out_80_a[21];
|
| 15557 |
|
|
|
| 15558 |
|
|
|
| 15559 |
|
|
--UD1_shift_out_77_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[27]
|
| 15560 |
|
|
--operation mode is normal
|
| 15561 |
|
|
|
| 15562 |
|
|
UD1_shift_out_77_a[27] = PD1_a_o_0 & !VD1_b_o_iv_18 # !PD1_a_o_0 & !VD1_b_o_iv_19;
|
| 15563 |
|
|
|
| 15564 |
|
|
|
| 15565 |
|
|
--UD1_shift_out_54[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54[29]
|
| 15566 |
|
|
--operation mode is normal
|
| 15567 |
|
|
|
| 15568 |
|
|
UD1_shift_out_54[29] = PD1_a_o_1 & !UD1_shift_out_54_a[29] # !PD1_a_o_1 & UD1_shift_out_54_a[29] & VD1_b_o_iv_17 # !UD1_shift_out_54_a[29] & VD1_b_o_iv_16;
|
| 15569 |
|
|
|
| 15570 |
|
|
|
| 15571 |
|
|
--UD1_shift_out_79[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[21]
|
| 15572 |
|
|
--operation mode is normal
|
| 15573 |
|
|
|
| 15574 |
|
|
UD1_shift_out_79[21] = PD1_a_o_1 & UD1_shift_out_79_a[21] & VD1_b_o_iv_31 # !UD1_shift_out_79_a[21] & UD1_shift_out_36_0 # !PD1_a_o_1 & !UD1_shift_out_79_a[21];
|
| 15575 |
|
|
|
| 15576 |
|
|
|
| 15577 |
|
|
--UD1_shift_out_77[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[21]
|
| 15578 |
|
|
--operation mode is normal
|
| 15579 |
|
|
|
| 15580 |
|
|
UD1_shift_out_77[21] = PD1_a_o_2 & UD1_shift_out_85_d[13] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[13] # !PD1_a_o_1 & !UD1_shift_out_77_a[21];
|
| 15581 |
|
|
|
| 15582 |
|
|
|
| 15583 |
|
|
--VD1_hilo_37_iv_0_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[21]
|
| 15584 |
|
|
--operation mode is normal
|
| 15585 |
|
|
|
| 15586 |
|
|
VD1_hilo_37_iv_0_a[21] = VD1_hilo_22 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_20 # !VD1_hilo_22 & !VD1_hilo_2_sqmuxa # !VD1_hilo_20;
|
| 15587 |
|
|
|
| 15588 |
|
|
|
| 15589 |
|
|
--VD1_hilo_37_iv_0_0[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[21]
|
| 15590 |
|
|
--operation mode is normal
|
| 15591 |
|
|
|
| 15592 |
|
|
VD1_hilo_37_iv_0_0[21] = VD1_hilo_21 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[21] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_21 & VD1_un134_hilo_combout[21] & VD1_hilo_37_iv_0_a3_0[0];
|
| 15593 |
|
|
|
| 15594 |
|
|
|
| 15595 |
|
|
--VD1_hilo_37_iv_2[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[53]
|
| 15596 |
|
|
--operation mode is normal
|
| 15597 |
|
|
|
| 15598 |
|
|
VD1_hilo_37_iv_2[53] = VD1_hilo_33_i_m[53] # VD1_hilo_37_iv_2_a[53] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[53];
|
| 15599 |
|
|
|
| 15600 |
|
|
|
| 15601 |
|
|
--VD1_hilo_37_iv_a[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[53]
|
| 15602 |
|
|
--operation mode is normal
|
| 15603 |
|
|
|
| 15604 |
|
|
VD1_hilo_37_iv_a[53] = RC1_alu_func_o_0 & !PD1_a_o_21 # !RC1_alu_func_o_0 & !VD1_hilo_53;
|
| 15605 |
|
|
|
| 15606 |
|
|
|
| 15607 |
|
|
--PD1_a_o_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[21]
|
| 15608 |
|
|
--operation mode is normal
|
| 15609 |
|
|
|
| 15610 |
|
|
PD1_a_o_a[21] = SC1_muxa_ctl_o_1 & !FB1_r32_o_21 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_21;
|
| 15611 |
|
|
|
| 15612 |
|
|
|
| 15613 |
|
|
--PD1_a_o_3_Z[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[21]
|
| 15614 |
|
|
--operation mode is normal
|
| 15615 |
|
|
|
| 15616 |
|
|
PD1_a_o_3_Z[21] = PD1_a_o_3_s[0] & SD1_r32_o_21 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[21];
|
| 15617 |
|
|
|
| 15618 |
|
|
|
| 15619 |
|
|
--TD1_un1_b_1_combout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[21]
|
| 15620 |
|
|
--operation mode is normal
|
| 15621 |
|
|
|
| 15622 |
|
|
TD1_un1_b_1_combout[21] = TD1_sum13_0_a2 $ !VD1_b_o_iv_21;
|
| 15623 |
|
|
|
| 15624 |
|
|
|
| 15625 |
|
|
--UD1_shift_out_87_d_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[20]
|
| 15626 |
|
|
--operation mode is normal
|
| 15627 |
|
|
|
| 15628 |
|
|
UD1_shift_out_87_d_a[20] = PD1_a_o_1 & !VD1_b_o_iv_26 # !PD1_a_o_1 & !VD1_b_o_iv_24;
|
| 15629 |
|
|
|
| 15630 |
|
|
|
| 15631 |
|
|
--UD1_shift_out_80[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[20]
|
| 15632 |
|
|
--operation mode is normal
|
| 15633 |
|
|
|
| 15634 |
|
|
UD1_shift_out_80[20] = PD1_a_o_2 & UD1_shift_out_80_a[20] & VD1_b_o_iv_25 # !UD1_shift_out_80_a[20] & VD1_b_o_iv_27 # !PD1_a_o_2 & !UD1_shift_out_80_a[20];
|
| 15635 |
|
|
|
| 15636 |
|
|
|
| 15637 |
|
|
--UD1_shift_out_77_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[26]
|
| 15638 |
|
|
--operation mode is normal
|
| 15639 |
|
|
|
| 15640 |
|
|
UD1_shift_out_77_a[26] = PD1_a_o_0 & !VD1_b_o_iv_17 # !PD1_a_o_0 & !VD1_b_o_iv_18;
|
| 15641 |
|
|
|
| 15642 |
|
|
|
| 15643 |
|
|
--UD1_shift_out_54[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54[28]
|
| 15644 |
|
|
--operation mode is normal
|
| 15645 |
|
|
|
| 15646 |
|
|
UD1_shift_out_54[28] = PD1_a_o_1 & !UD1_shift_out_54_a[28] # !PD1_a_o_1 & UD1_shift_out_54_a[28] & VD1_b_o_iv_16 # !UD1_shift_out_54_a[28] & VD1_b_o_iv_15;
|
| 15647 |
|
|
|
| 15648 |
|
|
|
| 15649 |
|
|
--VD1_hilo_37_iv_0_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[20]
|
| 15650 |
|
|
--operation mode is normal
|
| 15651 |
|
|
|
| 15652 |
|
|
VD1_hilo_37_iv_0_a[20] = VD1_hilo_21 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_19 # !VD1_hilo_21 & !VD1_hilo_2_sqmuxa # !VD1_hilo_19;
|
| 15653 |
|
|
|
| 15654 |
|
|
|
| 15655 |
|
|
--VD1_hilo_37_iv_0_0[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[20]
|
| 15656 |
|
|
--operation mode is normal
|
| 15657 |
|
|
|
| 15658 |
|
|
VD1_hilo_37_iv_0_0[20] = VD1_hilo_20 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[20] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_20 & VD1_un134_hilo_combout[20] & VD1_hilo_37_iv_0_a3_0[0];
|
| 15659 |
|
|
|
| 15660 |
|
|
|
| 15661 |
|
|
--VD1_hilo_37_iv_0_a[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[52]
|
| 15662 |
|
|
--operation mode is normal
|
| 15663 |
|
|
|
| 15664 |
|
|
VD1_hilo_37_iv_0_a[52] = !VD1_hilo_37_iv_0_3[52] & !VD1_hilo_37_iv_0_4[52] & VD1_hilo_24_add20 # !VD1_hilo_2_sqmuxa;
|
| 15665 |
|
|
|
| 15666 |
|
|
|
| 15667 |
|
|
--PD1_a_o_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[20]
|
| 15668 |
|
|
--operation mode is normal
|
| 15669 |
|
|
|
| 15670 |
|
|
PD1_a_o_a[20] = SC1_muxa_ctl_o_1 & !FB1_r32_o_20 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_20;
|
| 15671 |
|
|
|
| 15672 |
|
|
|
| 15673 |
|
|
--PD1_a_o_3_Z[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[20]
|
| 15674 |
|
|
--operation mode is normal
|
| 15675 |
|
|
|
| 15676 |
|
|
PD1_a_o_3_Z[20] = PD1_a_o_3_s[0] & SD1_r32_o_20 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[20];
|
| 15677 |
|
|
|
| 15678 |
|
|
|
| 15679 |
|
|
--TD1_un1_b_1_combout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[20]
|
| 15680 |
|
|
--operation mode is normal
|
| 15681 |
|
|
|
| 15682 |
|
|
TD1_un1_b_1_combout[20] = TD1_sum13_0_a2 $ !VD1_b_o_iv_20;
|
| 15683 |
|
|
|
| 15684 |
|
|
|
| 15685 |
|
|
--TD1_un1_a_add19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add19
|
| 15686 |
|
|
--operation mode is arithmetic
|
| 15687 |
|
|
|
| 15688 |
|
|
TD1_un1_a_add19_carry_eqn = TD1_un1_a_carry_18;
|
| 15689 |
|
|
TD1_un1_a_add19 = PD1_a_o_19 $ TD1_un1_b_1_combout[19] $ TD1_un1_a_add19_carry_eqn;
|
| 15690 |
|
|
|
| 15691 |
|
|
--TD1_un1_a_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_19
|
| 15692 |
|
|
--operation mode is arithmetic
|
| 15693 |
|
|
|
| 15694 |
|
|
TD1_un1_a_carry_19 = CARRY(PD1_a_o_19 & !TD1_un1_b_1_combout[19] & !TD1_un1_a_carry_18 # !PD1_a_o_19 & !TD1_un1_a_carry_18 # !TD1_un1_b_1_combout[19]);
|
| 15695 |
|
|
|
| 15696 |
|
|
|
| 15697 |
|
|
--UD1_shift_out_84_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[20]
|
| 15698 |
|
|
--operation mode is normal
|
| 15699 |
|
|
|
| 15700 |
|
|
UD1_shift_out_84_a[20] = PD1_a_o_2 & !UD1_shift_out_43[28] # !PD1_a_o_2 & !UD1_shift_out_45[28];
|
| 15701 |
|
|
|
| 15702 |
|
|
|
| 15703 |
|
|
--UD1_shift_out_63[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[28]
|
| 15704 |
|
|
--operation mode is normal
|
| 15705 |
|
|
|
| 15706 |
|
|
UD1_shift_out_63[28] = PD1_a_o_2 & UD1_shift_out_48[28] # !PD1_a_o_2 & UD1_shift_out_52[28];
|
| 15707 |
|
|
|
| 15708 |
|
|
|
| 15709 |
|
|
--UD1_shift_out_87_d[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[19]
|
| 15710 |
|
|
--operation mode is normal
|
| 15711 |
|
|
|
| 15712 |
|
|
UD1_shift_out_87_d[19] = PD1_a_o_0 & UD1_shift_out_80[19] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[19];
|
| 15713 |
|
|
|
| 15714 |
|
|
|
| 15715 |
|
|
--UD1_shift_out_85_d[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[19]
|
| 15716 |
|
|
--operation mode is normal
|
| 15717 |
|
|
|
| 15718 |
|
|
UD1_shift_out_85_d[19] = PD1_a_o_2 & UD1_shift_out_52[31] # !PD1_a_o_2 & !UD1_shift_out_77_a[25];
|
| 15719 |
|
|
|
| 15720 |
|
|
|
| 15721 |
|
|
--VD1_hilo_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_19
|
| 15722 |
|
|
--operation mode is normal
|
| 15723 |
|
|
|
| 15724 |
|
|
VD1_hilo_19_lut_out = VD1_hilo_37_iv_0_0[19] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_19 # !VD1_hilo_37_iv_0_a[19];
|
| 15725 |
|
|
VD1_hilo_19 = DFFEAS(VD1_hilo_19_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15726 |
|
|
|
| 15727 |
|
|
|
| 15728 |
|
|
--VD1_hilo_51 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_51
|
| 15729 |
|
|
--operation mode is normal
|
| 15730 |
|
|
|
| 15731 |
|
|
VD1_hilo_51_lut_out = !VD1_hilo_37_iv_0_8[51] & !VD1_hilo_37_iv_0_a3[57];
|
| 15732 |
|
|
VD1_hilo_51 = DFFEAS(VD1_hilo_51_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15733 |
|
|
|
| 15734 |
|
|
|
| 15735 |
|
|
--PD1_a_o_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_19
|
| 15736 |
|
|
--operation mode is normal
|
| 15737 |
|
|
|
| 15738 |
|
|
PD1_a_o_19 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[19] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[19];
|
| 15739 |
|
|
|
| 15740 |
|
|
|
| 15741 |
|
|
--TD1_m51_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m51_a
|
| 15742 |
|
|
--operation mode is normal
|
| 15743 |
|
|
|
| 15744 |
|
|
TD1_m51_a = VD1_b_o_iv_19 & !TD1_m9 & PD1_a_o_19 # !VD1_b_o_iv_19 & !TD1_m5 # !PD1_a_o_19;
|
| 15745 |
|
|
|
| 15746 |
|
|
|
| 15747 |
|
|
--UD1_shift_out_92_d_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[19]
|
| 15748 |
|
|
--operation mode is normal
|
| 15749 |
|
|
|
| 15750 |
|
|
UD1_shift_out_92_d_a[19] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_19 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[19];
|
| 15751 |
|
|
|
| 15752 |
|
|
|
| 15753 |
|
|
--UD1_shift_out_84[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[19]
|
| 15754 |
|
|
--operation mode is normal
|
| 15755 |
|
|
|
| 15756 |
|
|
UD1_shift_out_84[19] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_77[11] # !PD1_a_o_4 & !UD1_shift_out_84_a[19];
|
| 15757 |
|
|
|
| 15758 |
|
|
|
| 15759 |
|
|
--UD1_shift_out_87_d[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[18]
|
| 15760 |
|
|
--operation mode is normal
|
| 15761 |
|
|
|
| 15762 |
|
|
UD1_shift_out_87_d[18] = PD1_a_o_0 & UD1_shift_out_80[18] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[18];
|
| 15763 |
|
|
|
| 15764 |
|
|
|
| 15765 |
|
|
--UD1_shift_out_85_d[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[18]
|
| 15766 |
|
|
--operation mode is normal
|
| 15767 |
|
|
|
| 15768 |
|
|
UD1_shift_out_85_d[18] = PD1_a_o_2 & UD1_shift_out_52[30] # !PD1_a_o_2 & !UD1_shift_out_77_a[24];
|
| 15769 |
|
|
|
| 15770 |
|
|
|
| 15771 |
|
|
--UD1_shift_out_83[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[18]
|
| 15772 |
|
|
--operation mode is normal
|
| 15773 |
|
|
|
| 15774 |
|
|
UD1_shift_out_83[18] = !UD1_shift_out_83_a[18] & PD1_a_o_2 & !PD1_a_o_1 # !UD1_shift_out587;
|
| 15775 |
|
|
|
| 15776 |
|
|
|
| 15777 |
|
|
--UD1_shift_out_92_d_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[18]
|
| 15778 |
|
|
--operation mode is normal
|
| 15779 |
|
|
|
| 15780 |
|
|
UD1_shift_out_92_d_a[18] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_18 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[18];
|
| 15781 |
|
|
|
| 15782 |
|
|
|
| 15783 |
|
|
--UD1_shift_out_84[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[18]
|
| 15784 |
|
|
--operation mode is normal
|
| 15785 |
|
|
|
| 15786 |
|
|
UD1_shift_out_84[18] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_77[10] # !PD1_a_o_4 & UD1_shift_out_77[18];
|
| 15787 |
|
|
|
| 15788 |
|
|
|
| 15789 |
|
|
--VD1_hilo_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_18
|
| 15790 |
|
|
--operation mode is normal
|
| 15791 |
|
|
|
| 15792 |
|
|
VD1_hilo_18_lut_out = VD1_hilo_37_iv_1[18] # VD1_addnop2109_0_a2 & PD1_a_o_18 # !VD1_hilo_37_iv_a[18];
|
| 15793 |
|
|
VD1_hilo_18 = DFFEAS(VD1_hilo_18_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15794 |
|
|
|
| 15795 |
|
|
|
| 15796 |
|
|
--VD1_hilo_50 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_50
|
| 15797 |
|
|
--operation mode is normal
|
| 15798 |
|
|
|
| 15799 |
|
|
VD1_hilo_50_lut_out = !VD1_hilo_37_iv_0_4[50] & !VD1_hilo_37_iv_0_5[50] & !VD1_hilo_37_iv_0_a[50] & !VD1_hilo_37_iv_0_a3[57];
|
| 15800 |
|
|
VD1_hilo_50 = DFFEAS(VD1_hilo_50_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15801 |
|
|
|
| 15802 |
|
|
|
| 15803 |
|
|
--PD1_a_o_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_18
|
| 15804 |
|
|
--operation mode is normal
|
| 15805 |
|
|
|
| 15806 |
|
|
PD1_a_o_18 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[18] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[18];
|
| 15807 |
|
|
|
| 15808 |
|
|
|
| 15809 |
|
|
--TD1_m46_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m46_a
|
| 15810 |
|
|
--operation mode is normal
|
| 15811 |
|
|
|
| 15812 |
|
|
TD1_m46_a = VD1_b_o_iv_18 & !TD1_m9 & PD1_a_o_18 # !VD1_b_o_iv_18 & !PD1_a_o_18 # !TD1_m5;
|
| 15813 |
|
|
|
| 15814 |
|
|
|
| 15815 |
|
|
--TD1_un1_a_add18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add18
|
| 15816 |
|
|
--operation mode is arithmetic
|
| 15817 |
|
|
|
| 15818 |
|
|
TD1_un1_a_add18_carry_eqn = TD1_un1_a_carry_17;
|
| 15819 |
|
|
TD1_un1_a_add18 = PD1_a_o_18 $ TD1_un1_b_1_combout[18] $ !TD1_un1_a_add18_carry_eqn;
|
| 15820 |
|
|
|
| 15821 |
|
|
--TD1_un1_a_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_18
|
| 15822 |
|
|
--operation mode is arithmetic
|
| 15823 |
|
|
|
| 15824 |
|
|
TD1_un1_a_carry_18 = CARRY(PD1_a_o_18 & TD1_un1_b_1_combout[18] # !TD1_un1_a_carry_17 # !PD1_a_o_18 & TD1_un1_b_1_combout[18] & !TD1_un1_a_carry_17);
|
| 15825 |
|
|
|
| 15826 |
|
|
|
| 15827 |
|
|
--UD1_shift_out_87_d[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[26]
|
| 15828 |
|
|
--operation mode is normal
|
| 15829 |
|
|
|
| 15830 |
|
|
UD1_shift_out_87_d[26] = PD1_a_o_0 & UD1_shift_out_80[26] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[26];
|
| 15831 |
|
|
|
| 15832 |
|
|
|
| 15833 |
|
|
--UD1_shift_out_68[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[22]
|
| 15834 |
|
|
--operation mode is normal
|
| 15835 |
|
|
|
| 15836 |
|
|
UD1_shift_out_68[22] = PD1_a_o_0 & VD1_b_o_iv_19 # !PD1_a_o_0 & VD1_b_o_iv_20;
|
| 15837 |
|
|
|
| 15838 |
|
|
|
| 15839 |
|
|
--UD1_shift_out_68[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[24]
|
| 15840 |
|
|
--operation mode is normal
|
| 15841 |
|
|
|
| 15842 |
|
|
UD1_shift_out_68[24] = PD1_a_o_0 & VD1_b_o_iv_21 # !PD1_a_o_0 & VD1_b_o_iv_22;
|
| 15843 |
|
|
|
| 15844 |
|
|
|
| 15845 |
|
|
--UD1_shift_out_85_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[26]
|
| 15846 |
|
|
--operation mode is normal
|
| 15847 |
|
|
|
| 15848 |
|
|
UD1_shift_out_85_a[26] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_68[26] # !PD1_a_o_1 & !VD1_b_o_iv_25;
|
| 15849 |
|
|
|
| 15850 |
|
|
|
| 15851 |
|
|
--UD1_shift_out_92_d_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[26]
|
| 15852 |
|
|
--operation mode is normal
|
| 15853 |
|
|
|
| 15854 |
|
|
UD1_shift_out_92_d_a[26] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_26 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
|
| 15855 |
|
|
|
| 15856 |
|
|
|
| 15857 |
|
|
--UD1_shift_out_84[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[26]
|
| 15858 |
|
|
--operation mode is normal
|
| 15859 |
|
|
|
| 15860 |
|
|
UD1_shift_out_84[26] = PD1_a_o_4 & PD1_a_o_3 & !UD1_shift_out_84_a[26] # !PD1_a_o_3 & UD1_shift_out_77[18] # !PD1_a_o_4 & !UD1_shift_out_84_a[26];
|
| 15861 |
|
|
|
| 15862 |
|
|
|
| 15863 |
|
|
--VD1_hilo_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_26
|
| 15864 |
|
|
--operation mode is normal
|
| 15865 |
|
|
|
| 15866 |
|
|
VD1_hilo_26_lut_out = VD1_hilo_37_iv_0_0[26] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_26 # !VD1_hilo_37_iv_0_a[26];
|
| 15867 |
|
|
VD1_hilo_26 = DFFEAS(VD1_hilo_26_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15868 |
|
|
|
| 15869 |
|
|
|
| 15870 |
|
|
--VD1_hilo_58 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_58
|
| 15871 |
|
|
--operation mode is normal
|
| 15872 |
|
|
|
| 15873 |
|
|
VD1_hilo_58_lut_out = !VD1_hilo_37_iv_0_1[58] & !VD1_hilo_37_iv_0_o3_1_0_1[58] & !VD1_hilo_37_iv_0_o3[58] # !VD1_hilo_3_sqmuxa;
|
| 15874 |
|
|
VD1_hilo_58 = DFFEAS(VD1_hilo_58_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15875 |
|
|
|
| 15876 |
|
|
|
| 15877 |
|
|
--PD1_a_o_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_26
|
| 15878 |
|
|
--operation mode is normal
|
| 15879 |
|
|
|
| 15880 |
|
|
PD1_a_o_26 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[26] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[26];
|
| 15881 |
|
|
|
| 15882 |
|
|
|
| 15883 |
|
|
--TD1_m81_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m81_a
|
| 15884 |
|
|
--operation mode is normal
|
| 15885 |
|
|
|
| 15886 |
|
|
TD1_m81_a = VD1_b_o_iv_26 & !TD1_m9 & PD1_a_o_26 # !VD1_b_o_iv_26 & !TD1_m5 # !PD1_a_o_26;
|
| 15887 |
|
|
|
| 15888 |
|
|
|
| 15889 |
|
|
--TD1_un1_a_add26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add26
|
| 15890 |
|
|
--operation mode is arithmetic
|
| 15891 |
|
|
|
| 15892 |
|
|
TD1_un1_a_add26_carry_eqn = TD1_un1_a_carry_25;
|
| 15893 |
|
|
TD1_un1_a_add26 = PD1_a_o_26 $ TD1_un1_b_1_combout[26] $ !TD1_un1_a_add26_carry_eqn;
|
| 15894 |
|
|
|
| 15895 |
|
|
--TD1_un1_a_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_26
|
| 15896 |
|
|
--operation mode is arithmetic
|
| 15897 |
|
|
|
| 15898 |
|
|
TD1_un1_a_carry_26 = CARRY(PD1_a_o_26 & TD1_un1_b_1_combout[26] # !TD1_un1_a_carry_25 # !PD1_a_o_26 & TD1_un1_b_1_combout[26] & !TD1_un1_a_carry_25);
|
| 15899 |
|
|
|
| 15900 |
|
|
|
| 15901 |
|
|
--UD1_shift_out_68[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[25]
|
| 15902 |
|
|
--operation mode is normal
|
| 15903 |
|
|
|
| 15904 |
|
|
UD1_shift_out_68[25] = PD1_a_o_0 & VD1_b_o_iv_22 # !PD1_a_o_0 & VD1_b_o_iv_23;
|
| 15905 |
|
|
|
| 15906 |
|
|
|
| 15907 |
|
|
--UD1_shift_out_68[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[23]
|
| 15908 |
|
|
--operation mode is normal
|
| 15909 |
|
|
|
| 15910 |
|
|
UD1_shift_out_68[23] = PD1_a_o_0 & VD1_b_o_iv_20 # !PD1_a_o_0 & VD1_b_o_iv_21;
|
| 15911 |
|
|
|
| 15912 |
|
|
|
| 15913 |
|
|
--UD1_shift_out_85_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[27]
|
| 15914 |
|
|
--operation mode is normal
|
| 15915 |
|
|
|
| 15916 |
|
|
UD1_shift_out_85_a[27] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_68[27] # !PD1_a_o_1 & !VD1_b_o_iv_26;
|
| 15917 |
|
|
|
| 15918 |
|
|
|
| 15919 |
|
|
--UD1_shift_out_87_d[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[27]
|
| 15920 |
|
|
--operation mode is normal
|
| 15921 |
|
|
|
| 15922 |
|
|
UD1_shift_out_87_d[27] = PD1_a_o_0 & UD1_shift_out_80[27] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[27];
|
| 15923 |
|
|
|
| 15924 |
|
|
|
| 15925 |
|
|
--UD1_shift_out_92_d_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[27]
|
| 15926 |
|
|
--operation mode is normal
|
| 15927 |
|
|
|
| 15928 |
|
|
UD1_shift_out_92_d_a[27] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_27 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
|
| 15929 |
|
|
|
| 15930 |
|
|
|
| 15931 |
|
|
--UD1_shift_out_84[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[27]
|
| 15932 |
|
|
--operation mode is normal
|
| 15933 |
|
|
|
| 15934 |
|
|
UD1_shift_out_84[27] = PD1_a_o_4 & UD1_shift_out_75[27] # !PD1_a_o_4 & UD1_shift_out_77[27];
|
| 15935 |
|
|
|
| 15936 |
|
|
|
| 15937 |
|
|
--VD1_hilo_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_27
|
| 15938 |
|
|
--operation mode is normal
|
| 15939 |
|
|
|
| 15940 |
|
|
VD1_hilo_27_lut_out = VD1_hilo_37_iv_0[27] # VD1_hilo25 & VD1_hilo_8_Z[27] # !VD1_hilo_37_iv_a[27];
|
| 15941 |
|
|
VD1_hilo_27 = DFFEAS(VD1_hilo_27_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15942 |
|
|
|
| 15943 |
|
|
|
| 15944 |
|
|
--VD1_hilo_59 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_59
|
| 15945 |
|
|
--operation mode is normal
|
| 15946 |
|
|
|
| 15947 |
|
|
VD1_hilo_59_lut_out = VD1_hilo_37_iv_0_a[59] & !VD1_hilo_37_iv_0_a3[57] & PD1_a_o_27 # !VD1_hilo_37_iv_0_a3_1[0];
|
| 15948 |
|
|
VD1_hilo_59 = DFFEAS(VD1_hilo_59_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 15949 |
|
|
|
| 15950 |
|
|
|
| 15951 |
|
|
--PD1_a_o_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_27
|
| 15952 |
|
|
--operation mode is normal
|
| 15953 |
|
|
|
| 15954 |
|
|
PD1_a_o_27 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[27] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[27];
|
| 15955 |
|
|
|
| 15956 |
|
|
|
| 15957 |
|
|
--TD1_m86_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m86_a
|
| 15958 |
|
|
--operation mode is normal
|
| 15959 |
|
|
|
| 15960 |
|
|
TD1_m86_a = VD1_b_o_iv_27 & !TD1_m9 & PD1_a_o_27 # !VD1_b_o_iv_27 & !PD1_a_o_27 # !TD1_m5;
|
| 15961 |
|
|
|
| 15962 |
|
|
|
| 15963 |
|
|
--TD1_un1_a_add27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add27
|
| 15964 |
|
|
--operation mode is arithmetic
|
| 15965 |
|
|
|
| 15966 |
|
|
TD1_un1_a_add27_carry_eqn = TD1_un1_a_carry_26;
|
| 15967 |
|
|
TD1_un1_a_add27 = PD1_a_o_27 $ TD1_un1_b_1_combout[27] $ TD1_un1_a_add27_carry_eqn;
|
| 15968 |
|
|
|
| 15969 |
|
|
--TD1_un1_a_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_27
|
| 15970 |
|
|
--operation mode is arithmetic
|
| 15971 |
|
|
|
| 15972 |
|
|
TD1_un1_a_carry_27 = CARRY(PD1_a_o_27 & !TD1_un1_b_1_combout[27] & !TD1_un1_a_carry_26 # !PD1_a_o_27 & !TD1_un1_a_carry_26 # !TD1_un1_b_1_combout[27]);
|
| 15973 |
|
|
|
| 15974 |
|
|
|
| 15975 |
|
|
--UD1_shift_out_87_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_a[28]
|
| 15976 |
|
|
--operation mode is normal
|
| 15977 |
|
|
|
| 15978 |
|
|
UD1_shift_out_87_a[28] = PD1_a_o_2 & !UD1_shift_out_36_0 # !PD1_a_o_2 & !VD1_b_o_iv_31;
|
| 15979 |
|
|
|
| 15980 |
|
|
|
| 15981 |
|
|
--UD1_shift_out_87_d[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[28]
|
| 15982 |
|
|
--operation mode is normal
|
| 15983 |
|
|
|
| 15984 |
|
|
UD1_shift_out_87_d[28] = PD1_a_o_2 & !UD1_shift_out_87_d_a[28] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_d_a[28] # !PD1_a_o_0 & VD1_b_o_iv_30;
|
| 15985 |
|
|
|
| 15986 |
|
|
|
| 15987 |
|
|
--UD1_shift_out_68[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[26]
|
| 15988 |
|
|
--operation mode is normal
|
| 15989 |
|
|
|
| 15990 |
|
|
UD1_shift_out_68[26] = PD1_a_o_0 & VD1_b_o_iv_23 # !PD1_a_o_0 & VD1_b_o_iv_24;
|
| 15991 |
|
|
|
| 15992 |
|
|
|
| 15993 |
|
|
--UD1_shift_out_85_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[28]
|
| 15994 |
|
|
--operation mode is normal
|
| 15995 |
|
|
|
| 15996 |
|
|
UD1_shift_out_85_a[28] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_68[28] # !PD1_a_o_1 & !VD1_b_o_iv_27;
|
| 15997 |
|
|
|
| 15998 |
|
|
|
| 15999 |
|
|
--TD1_alu_out_0_a2_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_a[28]
|
| 16000 |
|
|
--operation mode is normal
|
| 16001 |
|
|
|
| 16002 |
|
|
TD1_alu_out_0_a2_a[28] = RC1_alu_func_o_2 & !RC1_alu_func_o_3 & !RC1_alu_func_o_1 & RC1_alu_func_o_4;
|
| 16003 |
|
|
|
| 16004 |
|
|
|
| 16005 |
|
|
--PD1_a_o_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_28
|
| 16006 |
|
|
--operation mode is normal
|
| 16007 |
|
|
|
| 16008 |
|
|
PD1_a_o_28 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[28] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[28];
|
| 16009 |
|
|
|
| 16010 |
|
|
|
| 16011 |
|
|
--MD1_c_0_Z[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_Z[28]
|
| 16012 |
|
|
--operation mode is normal
|
| 16013 |
|
|
|
| 16014 |
|
|
MD1_c_0_Z[28] = TD1_alu_out_9_a2_1_1_0 & VD1_b_o_iv_28 # !MD1_c_0_a[28];
|
| 16015 |
|
|
|
| 16016 |
|
|
|
| 16017 |
|
|
--MD1_c_2_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_a[28]
|
| 16018 |
|
|
--operation mode is normal
|
| 16019 |
|
|
|
| 16020 |
|
|
MD1_c_2_a[28] = !RC1_alu_func_o_3 & TD1_m107 & VD1_b_o_iv_28 # !RC1_alu_func_o_0;
|
| 16021 |
|
|
|
| 16022 |
|
|
|
| 16023 |
|
|
--TD1_alu_out_0_a2_3_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_3_0
|
| 16024 |
|
|
--operation mode is normal
|
| 16025 |
|
|
|
| 16026 |
|
|
TD1_alu_out_0_a2_3_0 = UD1_shift_out588_0 & TD1_alu_out_0_a3[28] & !VD1_b_o_iv_28 & PD1_a_o_28;
|
| 16027 |
|
|
|
| 16028 |
|
|
|
| 16029 |
|
|
--TD1_un1_b_1_combout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[28]
|
| 16030 |
|
|
--operation mode is normal
|
| 16031 |
|
|
|
| 16032 |
|
|
TD1_un1_b_1_combout[28] = TD1_sum13_0_a2 $ !VD1_b_o_iv_28;
|
| 16033 |
|
|
|
| 16034 |
|
|
|
| 16035 |
|
|
--UD1_shift_out_92_d_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[28]
|
| 16036 |
|
|
--operation mode is normal
|
| 16037 |
|
|
|
| 16038 |
|
|
UD1_shift_out_92_d_a[28] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_28 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
|
| 16039 |
|
|
|
| 16040 |
|
|
|
| 16041 |
|
|
--UD1_shift_out_84[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[28]
|
| 16042 |
|
|
--operation mode is normal
|
| 16043 |
|
|
|
| 16044 |
|
|
UD1_shift_out_84[28] = PD1_a_o_4 & UD1_shift_out_75[28] # !PD1_a_o_4 & UD1_shift_out_77[28];
|
| 16045 |
|
|
|
| 16046 |
|
|
|
| 16047 |
|
|
--UD1_shift_out_87_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_a[29]
|
| 16048 |
|
|
--operation mode is normal
|
| 16049 |
|
|
|
| 16050 |
|
|
UD1_shift_out_87_a[29] = PD1_a_o_2 & !UD1_shift_out_36_0 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_36_0 # !PD1_a_o_1 & !VD1_b_o_iv_30;
|
| 16051 |
|
|
|
| 16052 |
|
|
|
| 16053 |
|
|
--UD1_shift_out_85_c[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_c[29]
|
| 16054 |
|
|
--operation mode is normal
|
| 16055 |
|
|
|
| 16056 |
|
|
UD1_shift_out_85_c[29] = PD1_a_o_2 & PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_68[29] # !PD1_a_o_1 & VD1_b_o_iv_28;
|
| 16057 |
|
|
|
| 16058 |
|
|
|
| 16059 |
|
|
--UD1_shift_out_92_d_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[29]
|
| 16060 |
|
|
--operation mode is normal
|
| 16061 |
|
|
|
| 16062 |
|
|
UD1_shift_out_92_d_a[29] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_29 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
|
| 16063 |
|
|
|
| 16064 |
|
|
|
| 16065 |
|
|
--UD1_shift_out_84[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[29]
|
| 16066 |
|
|
--operation mode is normal
|
| 16067 |
|
|
|
| 16068 |
|
|
UD1_shift_out_84[29] = PD1_a_o_4 & UD1_shift_out_75[29] # !PD1_a_o_4 & !UD1_shift_out_84_a[29];
|
| 16069 |
|
|
|
| 16070 |
|
|
|
| 16071 |
|
|
--VD1_hilo_61 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_61
|
| 16072 |
|
|
--operation mode is normal
|
| 16073 |
|
|
|
| 16074 |
|
|
VD1_hilo_61_lut_out = VD1_hilo_37_iv_0_a[61] & !VD1_hilo_37_iv_0_a3[57] & PD1_a_o_29 # !VD1_hilo_37_iv_0_a3_1[0];
|
| 16075 |
|
|
VD1_hilo_61 = DFFEAS(VD1_hilo_61_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16076 |
|
|
|
| 16077 |
|
|
|
| 16078 |
|
|
--TD1_m91_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m91_a
|
| 16079 |
|
|
--operation mode is normal
|
| 16080 |
|
|
|
| 16081 |
|
|
TD1_m91_a = VD1_b_o_iv_29 & !TD1_m9 & PD1_a_o_29 # !VD1_b_o_iv_29 & !TD1_m5 # !PD1_a_o_29;
|
| 16082 |
|
|
|
| 16083 |
|
|
|
| 16084 |
|
|
--UD1_shift_out_87_d_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[13]
|
| 16085 |
|
|
--operation mode is normal
|
| 16086 |
|
|
|
| 16087 |
|
|
UD1_shift_out_87_d_a[13] = PD1_a_o_1 & !VD1_b_o_iv_19 # !PD1_a_o_1 & !VD1_b_o_iv_17;
|
| 16088 |
|
|
|
| 16089 |
|
|
|
| 16090 |
|
|
--UD1_shift_out_80[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[13]
|
| 16091 |
|
|
--operation mode is normal
|
| 16092 |
|
|
|
| 16093 |
|
|
UD1_shift_out_80[13] = PD1_a_o_2 & UD1_shift_out_80_a[13] & VD1_b_o_iv_18 # !UD1_shift_out_80_a[13] & VD1_b_o_iv_20 # !PD1_a_o_2 & !UD1_shift_out_80_a[13];
|
| 16094 |
|
|
|
| 16095 |
|
|
|
| 16096 |
|
|
--UD1_shift_out_85_d_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[13]
|
| 16097 |
|
|
--operation mode is normal
|
| 16098 |
|
|
|
| 16099 |
|
|
UD1_shift_out_85_d_a[13] = PD1_a_o_0 & !VD1_b_o_iv_10 # !PD1_a_o_0 & !VD1_b_o_iv_11;
|
| 16100 |
|
|
|
| 16101 |
|
|
|
| 16102 |
|
|
--UD1_shift_out_48[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48[29]
|
| 16103 |
|
|
--operation mode is normal
|
| 16104 |
|
|
|
| 16105 |
|
|
UD1_shift_out_48[29] = PD1_a_o_1 & !UD1_shift_out_48_a[29] # !PD1_a_o_1 & UD1_shift_out_48_a[29] & VD1_b_o_iv_9 # !UD1_shift_out_48_a[29] & VD1_b_o_iv_8;
|
| 16106 |
|
|
|
| 16107 |
|
|
|
| 16108 |
|
|
--UD1_shift_out_74[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[13]
|
| 16109 |
|
|
--operation mode is normal
|
| 16110 |
|
|
|
| 16111 |
|
|
UD1_shift_out_74[13] = PD1_a_o_1 & VD1_b_o_iv_31 # !PD1_a_o_1 & UD1_shift_out_sn_m25_0_o2 & VD1_b_o_iv_31 # !UD1_shift_out_sn_m25_0_o2 & UD1_shift_out_39[17];
|
| 16112 |
|
|
|
| 16113 |
|
|
|
| 16114 |
|
|
--UD1_shift_out_45[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45[29]
|
| 16115 |
|
|
--operation mode is normal
|
| 16116 |
|
|
|
| 16117 |
|
|
UD1_shift_out_45[29] = PD1_a_o_1 & !UD1_shift_out_45_a[29] # !PD1_a_o_1 & UD1_shift_out_45_a[29] & VD1_b_o_iv_5 # !UD1_shift_out_45_a[29] & VD1_b_o_iv_4;
|
| 16118 |
|
|
|
| 16119 |
|
|
|
| 16120 |
|
|
--VD1_hilo_37_iv_0_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[13]
|
| 16121 |
|
|
--operation mode is normal
|
| 16122 |
|
|
|
| 16123 |
|
|
VD1_hilo_37_iv_0_a[13] = VD1_hilo_14 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_12 # !VD1_hilo_14 & !VD1_hilo_2_sqmuxa # !VD1_hilo_12;
|
| 16124 |
|
|
|
| 16125 |
|
|
|
| 16126 |
|
|
--VD1_hilo_37_iv_0_0[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[13]
|
| 16127 |
|
|
--operation mode is normal
|
| 16128 |
|
|
|
| 16129 |
|
|
VD1_hilo_37_iv_0_0[13] = VD1_hilo_13 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[13] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_13 & VD1_un134_hilo_combout[13] & VD1_hilo_37_iv_0_a3_0[0];
|
| 16130 |
|
|
|
| 16131 |
|
|
|
| 16132 |
|
|
--VD1_hilo_37_iv_2[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[45]
|
| 16133 |
|
|
--operation mode is normal
|
| 16134 |
|
|
|
| 16135 |
|
|
VD1_hilo_37_iv_2[45] = VD1_hilo_33_i_m[45] # VD1_hilo_37_iv_2_a[45] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[45];
|
| 16136 |
|
|
|
| 16137 |
|
|
|
| 16138 |
|
|
--VD1_hilo_37_iv_a[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[45]
|
| 16139 |
|
|
--operation mode is normal
|
| 16140 |
|
|
|
| 16141 |
|
|
VD1_hilo_37_iv_a[45] = RC1_alu_func_o_0 & !PD1_a_o_13 # !RC1_alu_func_o_0 & !VD1_hilo_45;
|
| 16142 |
|
|
|
| 16143 |
|
|
|
| 16144 |
|
|
--PD1_a_o_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[13]
|
| 16145 |
|
|
--operation mode is normal
|
| 16146 |
|
|
|
| 16147 |
|
|
PD1_a_o_a[13] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_13 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_13;
|
| 16148 |
|
|
|
| 16149 |
|
|
|
| 16150 |
|
|
--PD1_a_o_3_Z[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[13]
|
| 16151 |
|
|
--operation mode is normal
|
| 16152 |
|
|
|
| 16153 |
|
|
PD1_a_o_3_Z[13] = PD1_a_o_3_s[0] & SD1_r32_o_13 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[13];
|
| 16154 |
|
|
|
| 16155 |
|
|
|
| 16156 |
|
|
--TD1_un1_b_1_combout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[13]
|
| 16157 |
|
|
--operation mode is normal
|
| 16158 |
|
|
|
| 16159 |
|
|
TD1_un1_b_1_combout[13] = TD1_sum13_0_a2 $ !VD1_b_o_iv_13;
|
| 16160 |
|
|
|
| 16161 |
|
|
|
| 16162 |
|
|
--TD1_un1_a_add12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add12
|
| 16163 |
|
|
--operation mode is arithmetic
|
| 16164 |
|
|
|
| 16165 |
|
|
TD1_un1_a_add12_carry_eqn = TD1_un1_a_carry_11;
|
| 16166 |
|
|
TD1_un1_a_add12 = PD1_a_o_12 $ TD1_un1_b_1_combout[12] $ !TD1_un1_a_add12_carry_eqn;
|
| 16167 |
|
|
|
| 16168 |
|
|
--TD1_un1_a_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_12
|
| 16169 |
|
|
--operation mode is arithmetic
|
| 16170 |
|
|
|
| 16171 |
|
|
TD1_un1_a_carry_12 = CARRY(PD1_a_o_12 & TD1_un1_b_1_combout[12] # !TD1_un1_a_carry_11 # !PD1_a_o_12 & TD1_un1_b_1_combout[12] & !TD1_un1_a_carry_11);
|
| 16172 |
|
|
|
| 16173 |
|
|
|
| 16174 |
|
|
--VD1_hilo_37_iv_0_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[29]
|
| 16175 |
|
|
--operation mode is normal
|
| 16176 |
|
|
|
| 16177 |
|
|
VD1_hilo_37_iv_0_a[29] = VD1_hilo_30 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_28 # !VD1_hilo_30 & !VD1_hilo_2_sqmuxa # !VD1_hilo_28;
|
| 16178 |
|
|
|
| 16179 |
|
|
|
| 16180 |
|
|
--VD1_hilo_37_iv_0_0[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[29]
|
| 16181 |
|
|
--operation mode is normal
|
| 16182 |
|
|
|
| 16183 |
|
|
VD1_hilo_37_iv_0_0[29] = VD1_hilo_29 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[29] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_29 & VD1_un134_hilo_combout[29] & VD1_hilo_37_iv_0_a3_0[0];
|
| 16184 |
|
|
|
| 16185 |
|
|
|
| 16186 |
|
|
--VD1_un134_hilo_combout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[28]
|
| 16187 |
|
|
--operation mode is arithmetic
|
| 16188 |
|
|
|
| 16189 |
|
|
VD1_un134_hilo_combout[28]_carry_eqn = VD1_un134_hilo_cout[26];
|
| 16190 |
|
|
VD1_un134_hilo_combout[28] = VD1_hilo_28 $ (!VD1_un134_hilo_combout[28]_carry_eqn);
|
| 16191 |
|
|
|
| 16192 |
|
|
--VD1_un134_hilo_cout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[28]
|
| 16193 |
|
|
--operation mode is arithmetic
|
| 16194 |
|
|
|
| 16195 |
|
|
VD1_un134_hilo_cout[28] = CARRY(VD1_hilo_28 & VD1_hilo_29 & !VD1_un134_hilo_cout[26]);
|
| 16196 |
|
|
|
| 16197 |
|
|
|
| 16198 |
|
|
--RD1_r32_o_0_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_30
|
| 16199 |
|
|
--operation mode is normal
|
| 16200 |
|
|
|
| 16201 |
|
|
RD1_r32_o_0_30_carry_eqn = RD1_r32_o_cout[28];
|
| 16202 |
|
|
RD1_r32_o_0_30_lut_out = KB1_r32_o_30 $ (!RD1_r32_o_0_30_carry_eqn);
|
| 16203 |
|
|
RD1_r32_o_0_30 = DFFEAS(RD1_r32_o_0_30_lut_out, E1__clk0, VCC, , , , , , );
|
| 16204 |
|
|
|
| 16205 |
|
|
|
| 16206 |
|
|
--FB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_30
|
| 16207 |
|
|
--operation mode is normal
|
| 16208 |
|
|
|
| 16209 |
|
|
FB1_r32_o_30_lut_out = CD1_res_7_0_0_a3_0 # ED1_r32_o_14 & CD1_res_7_0_0_a2_16;
|
| 16210 |
|
|
FB1_r32_o_30 = DFFEAS(FB1_r32_o_30_lut_out, E1__clk0, VCC, , , , , , );
|
| 16211 |
|
|
|
| 16212 |
|
|
|
| 16213 |
|
|
--SD1_r32_o_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_30
|
| 16214 |
|
|
--operation mode is normal
|
| 16215 |
|
|
|
| 16216 |
|
|
SD1_r32_o_30_lut_out = KB1_r32_o_30;
|
| 16217 |
|
|
SD1_r32_o_30 = DFFEAS(SD1_r32_o_30_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 16218 |
|
|
|
| 16219 |
|
|
|
| 16220 |
|
|
--PD1_a_o_3_d[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[30]
|
| 16221 |
|
|
--operation mode is normal
|
| 16222 |
|
|
|
| 16223 |
|
|
PD1_a_o_3_d[30] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_30 # !PD1_un6_a_o & !PD1_a_o_3_d_a[30] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[30];
|
| 16224 |
|
|
|
| 16225 |
|
|
|
| 16226 |
|
|
--VD1_hilo_33_1[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_1[64]
|
| 16227 |
|
|
--operation mode is normal
|
| 16228 |
|
|
|
| 16229 |
|
|
VD1_hilo_33_1[64] = VD1_addop2 $ VD1_addnop2;
|
| 16230 |
|
|
|
| 16231 |
|
|
|
| 16232 |
|
|
--VD1_hilo_24_add30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add30
|
| 16233 |
|
|
--operation mode is arithmetic
|
| 16234 |
|
|
|
| 16235 |
|
|
VD1_hilo_24_add30_carry_eqn = VD1_hilo_24_carry_29;
|
| 16236 |
|
|
VD1_hilo_24_add30 = VD1_hilo_61 $ VD1_un1_op2_reged_1_combout[30] $ !VD1_hilo_24_add30_carry_eqn;
|
| 16237 |
|
|
|
| 16238 |
|
|
--VD1_hilo_24_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_30
|
| 16239 |
|
|
--operation mode is arithmetic
|
| 16240 |
|
|
|
| 16241 |
|
|
VD1_hilo_24_carry_30 = CARRY(VD1_hilo_61 & VD1_un1_op2_reged_1_combout[30] # !VD1_hilo_24_carry_29 # !VD1_hilo_61 & VD1_un1_op2_reged_1_combout[30] & !VD1_hilo_24_carry_29);
|
| 16242 |
|
|
|
| 16243 |
|
|
|
| 16244 |
|
|
--VD1_hilo_37_iv_0_2[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[62]
|
| 16245 |
|
|
--operation mode is normal
|
| 16246 |
|
|
|
| 16247 |
|
|
VD1_hilo_37_iv_0_2[62] = VD1_hilo_37_iv_0_a5_0[62] # VD1_hilo_37_iv_0_0[62] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add30;
|
| 16248 |
|
|
|
| 16249 |
|
|
|
| 16250 |
|
|
--VD1_hilo_37_iv_0_o5[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5[62]
|
| 16251 |
|
|
--operation mode is normal
|
| 16252 |
|
|
|
| 16253 |
|
|
VD1_hilo_37_iv_0_o5[62] = VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_30 # !VD1_un50_hilo_add31 # !VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_30;
|
| 16254 |
|
|
|
| 16255 |
|
|
|
| 16256 |
|
|
--VD1_un59_hilo_add31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add31
|
| 16257 |
|
|
--operation mode is arithmetic
|
| 16258 |
|
|
|
| 16259 |
|
|
VD1_un59_hilo_add31_carry_eqn = VD1_un59_hilo_carry_30;
|
| 16260 |
|
|
VD1_un59_hilo_add31 = VD1_hilo_63 $ VD1_op2_reged[31] $ VD1_un59_hilo_add31_carry_eqn;
|
| 16261 |
|
|
|
| 16262 |
|
|
--VD1_un59_hilo_carry_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_31
|
| 16263 |
|
|
--operation mode is arithmetic
|
| 16264 |
|
|
|
| 16265 |
|
|
VD1_un59_hilo_carry_31 = CARRY(VD1_hilo_63 & !VD1_op2_reged[31] & !VD1_un59_hilo_carry_30 # !VD1_hilo_63 & !VD1_un59_hilo_carry_30 # !VD1_op2_reged[31]);
|
| 16266 |
|
|
|
| 16267 |
|
|
|
| 16268 |
|
|
--VD1_hilo_37_iv_0_o5_0_a[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5_0_a[62]
|
| 16269 |
|
|
--operation mode is normal
|
| 16270 |
|
|
|
| 16271 |
|
|
VD1_hilo_37_iv_0_o5_0_a[62] = !VD1_hilo_63 & VD1_hilo_37_iv_0_a6_0_1[40];
|
| 16272 |
|
|
|
| 16273 |
|
|
|
| 16274 |
|
|
--UD1_shift_out_92_d_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[30]
|
| 16275 |
|
|
--operation mode is normal
|
| 16276 |
|
|
|
| 16277 |
|
|
UD1_shift_out_92_d_a[30] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_30 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
|
| 16278 |
|
|
|
| 16279 |
|
|
|
| 16280 |
|
|
--UD1_shift_out_84[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[30]
|
| 16281 |
|
|
--operation mode is normal
|
| 16282 |
|
|
|
| 16283 |
|
|
UD1_shift_out_84[30] = PD1_a_o_4 & !UD1_shift_out_84_a[30] # !PD1_a_o_4 & UD1_shift_out_77[30];
|
| 16284 |
|
|
|
| 16285 |
|
|
|
| 16286 |
|
|
--UD1_shift_out_89[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[30]
|
| 16287 |
|
|
--operation mode is normal
|
| 16288 |
|
|
|
| 16289 |
|
|
UD1_shift_out_89[30] = UD1_shift_out586 & UD1_shift_out_85[30] # !UD1_shift_out586 & !UD1_shift_out_89_a[30];
|
| 16290 |
|
|
|
| 16291 |
|
|
|
| 16292 |
|
|
--TD1_un1_b_1_combout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[29]
|
| 16293 |
|
|
--operation mode is normal
|
| 16294 |
|
|
|
| 16295 |
|
|
TD1_un1_b_1_combout[29] = TD1_sum13_0_a2 $ !VD1_b_o_iv_29;
|
| 16296 |
|
|
|
| 16297 |
|
|
|
| 16298 |
|
|
--UD1_shift_out_87_d[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[12]
|
| 16299 |
|
|
--operation mode is normal
|
| 16300 |
|
|
|
| 16301 |
|
|
UD1_shift_out_87_d[12] = PD1_a_o_0 & UD1_shift_out_80[12] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[12];
|
| 16302 |
|
|
|
| 16303 |
|
|
|
| 16304 |
|
|
--UD1_shift_out_85_d[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[12]
|
| 16305 |
|
|
--operation mode is normal
|
| 16306 |
|
|
|
| 16307 |
|
|
UD1_shift_out_85_d[12] = PD1_a_o_2 & UD1_shift_out_48[28] # !PD1_a_o_2 & !UD1_shift_out_77_a[18];
|
| 16308 |
|
|
|
| 16309 |
|
|
|
| 16310 |
|
|
--UD1_shift_out_74[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[12]
|
| 16311 |
|
|
--operation mode is normal
|
| 16312 |
|
|
|
| 16313 |
|
|
UD1_shift_out_74[12] = PD1_a_o_3 & VD1_b_o_iv_31 # !PD1_a_o_3 & PD1_a_o_2 & VD1_b_o_iv_31 # !PD1_a_o_2 & UD1_shift_out_79[20];
|
| 16314 |
|
|
|
| 16315 |
|
|
|
| 16316 |
|
|
--UD1_shift_out_86_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[12]
|
| 16317 |
|
|
--operation mode is normal
|
| 16318 |
|
|
|
| 16319 |
|
|
UD1_shift_out_86_a[12] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[16] # !PD1_a_o_2 & !UD1_shift_out_79[20] # !UD1_shift_out587 & !UD1_shift_out_79[16];
|
| 16320 |
|
|
|
| 16321 |
|
|
|
| 16322 |
|
|
--UD1_shift_out_63[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[20]
|
| 16323 |
|
|
--operation mode is normal
|
| 16324 |
|
|
|
| 16325 |
|
|
UD1_shift_out_63[20] = PD1_a_o_2 & UD1_shift_out_43[28] # !PD1_a_o_2 & UD1_shift_out_45[28];
|
| 16326 |
|
|
|
| 16327 |
|
|
|
| 16328 |
|
|
--UD1_shift_out_92_d_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[12]
|
| 16329 |
|
|
--operation mode is normal
|
| 16330 |
|
|
|
| 16331 |
|
|
UD1_shift_out_92_d_a[12] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_12 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[12] # !UD1_shift_out_sn_m17_0;
|
| 16332 |
|
|
|
| 16333 |
|
|
|
| 16334 |
|
|
--VD1_hilo_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_12
|
| 16335 |
|
|
--operation mode is normal
|
| 16336 |
|
|
|
| 16337 |
|
|
VD1_hilo_12_lut_out = VD1_hilo_37_iv_0_0[12] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_12 # !VD1_hilo_37_iv_0_a[12];
|
| 16338 |
|
|
VD1_hilo_12 = DFFEAS(VD1_hilo_12_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16339 |
|
|
|
| 16340 |
|
|
|
| 16341 |
|
|
--VD1_hilo_44 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_44
|
| 16342 |
|
|
--operation mode is normal
|
| 16343 |
|
|
|
| 16344 |
|
|
VD1_hilo_44_lut_out = !VD1_hilo_37_iv_0_o3[44] & VD1_hilo_37_iv_0_a[44] & !VD1_hilo_37_iv_0_o3[34] # !VD1_hilo_37_iv_0_o2_3_0[44];
|
| 16345 |
|
|
VD1_hilo_44 = DFFEAS(VD1_hilo_44_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16346 |
|
|
|
| 16347 |
|
|
|
| 16348 |
|
|
--PD1_a_o_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_12
|
| 16349 |
|
|
--operation mode is normal
|
| 16350 |
|
|
|
| 16351 |
|
|
PD1_a_o_12 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[12] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[12];
|
| 16352 |
|
|
|
| 16353 |
|
|
|
| 16354 |
|
|
--TD1_m122_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m122_a
|
| 16355 |
|
|
--operation mode is normal
|
| 16356 |
|
|
|
| 16357 |
|
|
TD1_m122_a = VD1_b_o_iv_12 & !TD1_m9 & PD1_a_o_12 # !VD1_b_o_iv_12 & !TD1_m5 # !PD1_a_o_12;
|
| 16358 |
|
|
|
| 16359 |
|
|
|
| 16360 |
|
|
--YB1_dmem_ctl_2_0_0_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_3
|
| 16361 |
|
|
--operation mode is normal
|
| 16362 |
|
|
|
| 16363 |
|
|
YB1_dmem_ctl_2_0_0_3 = YB1_dmem_ctl_2_0_0_a[3] # WB94L1 & YB1_alu_func_2_0_0_a2_0[1] & YB1_fsm_dly_2_0_0_o2_x[2];
|
| 16364 |
|
|
|
| 16365 |
|
|
|
| 16366 |
|
|
--WB94L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:dmem_ctl_1_3_|lpm_latch:U1|q[0]~56
|
| 16367 |
|
|
--operation mode is normal
|
| 16368 |
|
|
|
| 16369 |
|
|
WB94L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_dmem_ctl_2_0_0_3 # !YB1_un1_muxa_ctl370_x & WB94L1;
|
| 16370 |
|
|
|
| 16371 |
|
|
|
| 16372 |
|
|
--UD1_shift_out_87_d[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[24]
|
| 16373 |
|
|
--operation mode is normal
|
| 16374 |
|
|
|
| 16375 |
|
|
UD1_shift_out_87_d[24] = PD1_a_o_0 & UD1_shift_out_80[24] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[24];
|
| 16376 |
|
|
|
| 16377 |
|
|
|
| 16378 |
|
|
--UD1_shift_out_68[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[20]
|
| 16379 |
|
|
--operation mode is normal
|
| 16380 |
|
|
|
| 16381 |
|
|
UD1_shift_out_68[20] = PD1_a_o_0 & VD1_b_o_iv_17 # !PD1_a_o_0 & VD1_b_o_iv_18;
|
| 16382 |
|
|
|
| 16383 |
|
|
|
| 16384 |
|
|
--UD1_shift_out_85_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[24]
|
| 16385 |
|
|
--operation mode is normal
|
| 16386 |
|
|
|
| 16387 |
|
|
UD1_shift_out_85_a[24] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_68[24] # !PD1_a_o_1 & !VD1_b_o_iv_23;
|
| 16388 |
|
|
|
| 16389 |
|
|
|
| 16390 |
|
|
--UD1_shift_out_92_d_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[24]
|
| 16391 |
|
|
--operation mode is normal
|
| 16392 |
|
|
|
| 16393 |
|
|
UD1_shift_out_92_d_a[24] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_24 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
|
| 16394 |
|
|
|
| 16395 |
|
|
|
| 16396 |
|
|
--UD1_shift_out_84[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[24]
|
| 16397 |
|
|
--operation mode is normal
|
| 16398 |
|
|
|
| 16399 |
|
|
UD1_shift_out_84[24] = PD1_a_o_4 & PD1_a_o_3 & UD1_shift_out_84_a[24] # !PD1_a_o_3 & UD1_shift_out_77[16] # !PD1_a_o_4 & !UD1_shift_out_84_a[24];
|
| 16400 |
|
|
|
| 16401 |
|
|
|
| 16402 |
|
|
--VD1_hilo_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24
|
| 16403 |
|
|
--operation mode is normal
|
| 16404 |
|
|
|
| 16405 |
|
|
VD1_hilo_24_lut_out = VD1_hilo_37_iv_1[24] # VD1_addnop2109_0_a2 & PD1_a_o_24 # !VD1_hilo_37_iv_a[24];
|
| 16406 |
|
|
VD1_hilo_24 = DFFEAS(VD1_hilo_24_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16407 |
|
|
|
| 16408 |
|
|
|
| 16409 |
|
|
--VD1_hilo_56 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_56
|
| 16410 |
|
|
--operation mode is normal
|
| 16411 |
|
|
|
| 16412 |
|
|
VD1_hilo_56_lut_out = !VD1_hilo_37_iv_2[56] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[56] # !VD1_hilo25;
|
| 16413 |
|
|
VD1_hilo_56 = DFFEAS(VD1_hilo_56_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16414 |
|
|
|
| 16415 |
|
|
|
| 16416 |
|
|
--PD1_a_o_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_24
|
| 16417 |
|
|
--operation mode is normal
|
| 16418 |
|
|
|
| 16419 |
|
|
PD1_a_o_24 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[24] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[24];
|
| 16420 |
|
|
|
| 16421 |
|
|
|
| 16422 |
|
|
--TD1_m71_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m71_a
|
| 16423 |
|
|
--operation mode is normal
|
| 16424 |
|
|
|
| 16425 |
|
|
TD1_m71_a = VD1_b_o_iv_24 & !TD1_m9 & PD1_a_o_24 # !VD1_b_o_iv_24 & !PD1_a_o_24 # !TD1_m5;
|
| 16426 |
|
|
|
| 16427 |
|
|
|
| 16428 |
|
|
--TD1_un1_a_add24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add24
|
| 16429 |
|
|
--operation mode is arithmetic
|
| 16430 |
|
|
|
| 16431 |
|
|
TD1_un1_a_add24_carry_eqn = TD1_un1_a_carry_23;
|
| 16432 |
|
|
TD1_un1_a_add24 = PD1_a_o_24 $ TD1_un1_b_1_combout[24] $ !TD1_un1_a_add24_carry_eqn;
|
| 16433 |
|
|
|
| 16434 |
|
|
--TD1_un1_a_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_24
|
| 16435 |
|
|
--operation mode is arithmetic
|
| 16436 |
|
|
|
| 16437 |
|
|
TD1_un1_a_carry_24 = CARRY(PD1_a_o_24 & TD1_un1_b_1_combout[24] # !TD1_un1_a_carry_23 # !PD1_a_o_24 & TD1_un1_b_1_combout[24] & !TD1_un1_a_carry_23);
|
| 16438 |
|
|
|
| 16439 |
|
|
|
| 16440 |
|
|
--UD1_shift_out_87_d[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[25]
|
| 16441 |
|
|
--operation mode is normal
|
| 16442 |
|
|
|
| 16443 |
|
|
UD1_shift_out_87_d[25] = PD1_a_o_0 & UD1_shift_out_80[25] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[25];
|
| 16444 |
|
|
|
| 16445 |
|
|
|
| 16446 |
|
|
--UD1_shift_out_68[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[21]
|
| 16447 |
|
|
--operation mode is normal
|
| 16448 |
|
|
|
| 16449 |
|
|
UD1_shift_out_68[21] = PD1_a_o_0 & VD1_b_o_iv_18 # !PD1_a_o_0 & VD1_b_o_iv_19;
|
| 16450 |
|
|
|
| 16451 |
|
|
|
| 16452 |
|
|
--UD1_shift_out_85_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[25]
|
| 16453 |
|
|
--operation mode is normal
|
| 16454 |
|
|
|
| 16455 |
|
|
UD1_shift_out_85_a[25] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_68[25] # !PD1_a_o_1 & !VD1_b_o_iv_24;
|
| 16456 |
|
|
|
| 16457 |
|
|
|
| 16458 |
|
|
--UD1_shift_out_92_d_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[25]
|
| 16459 |
|
|
--operation mode is normal
|
| 16460 |
|
|
|
| 16461 |
|
|
UD1_shift_out_92_d_a[25] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_25 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
|
| 16462 |
|
|
|
| 16463 |
|
|
|
| 16464 |
|
|
--UD1_shift_out_84[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[25]
|
| 16465 |
|
|
--operation mode is normal
|
| 16466 |
|
|
|
| 16467 |
|
|
UD1_shift_out_84[25] = PD1_a_o_4 & UD1_shift_out_75[25] # !PD1_a_o_4 & UD1_shift_out_77[25];
|
| 16468 |
|
|
|
| 16469 |
|
|
|
| 16470 |
|
|
--VD1_hilo_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_25
|
| 16471 |
|
|
--operation mode is normal
|
| 16472 |
|
|
|
| 16473 |
|
|
VD1_hilo_25_lut_out = VD1_hilo_37_iv_0_0[25] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_25 # !VD1_hilo_37_iv_0_a[25];
|
| 16474 |
|
|
VD1_hilo_25 = DFFEAS(VD1_hilo_25_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16475 |
|
|
|
| 16476 |
|
|
|
| 16477 |
|
|
--VD1_hilo_57 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_57
|
| 16478 |
|
|
--operation mode is normal
|
| 16479 |
|
|
|
| 16480 |
|
|
VD1_hilo_57_lut_out = !VD1_hilo_37_iv_0_8[57] & !VD1_hilo_37_iv_0_a3[57];
|
| 16481 |
|
|
VD1_hilo_57 = DFFEAS(VD1_hilo_57_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16482 |
|
|
|
| 16483 |
|
|
|
| 16484 |
|
|
--PD1_a_o_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_25
|
| 16485 |
|
|
--operation mode is normal
|
| 16486 |
|
|
|
| 16487 |
|
|
PD1_a_o_25 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[25] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[25];
|
| 16488 |
|
|
|
| 16489 |
|
|
|
| 16490 |
|
|
--TD1_m76_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m76_a
|
| 16491 |
|
|
--operation mode is normal
|
| 16492 |
|
|
|
| 16493 |
|
|
TD1_m76_a = VD1_b_o_iv_25 & !TD1_m9 & PD1_a_o_25 # !VD1_b_o_iv_25 & !TD1_m5 # !PD1_a_o_25;
|
| 16494 |
|
|
|
| 16495 |
|
|
|
| 16496 |
|
|
--TD1_un1_a_add25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add25
|
| 16497 |
|
|
--operation mode is arithmetic
|
| 16498 |
|
|
|
| 16499 |
|
|
TD1_un1_a_add25_carry_eqn = TD1_un1_a_carry_24;
|
| 16500 |
|
|
TD1_un1_a_add25 = PD1_a_o_25 $ TD1_un1_b_1_combout[25] $ TD1_un1_a_add25_carry_eqn;
|
| 16501 |
|
|
|
| 16502 |
|
|
--TD1_un1_a_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_25
|
| 16503 |
|
|
--operation mode is arithmetic
|
| 16504 |
|
|
|
| 16505 |
|
|
TD1_un1_a_carry_25 = CARRY(PD1_a_o_25 & !TD1_un1_b_1_combout[25] & !TD1_un1_a_carry_24 # !PD1_a_o_25 & !TD1_un1_a_carry_24 # !TD1_un1_b_1_combout[25]);
|
| 16506 |
|
|
|
| 16507 |
|
|
|
| 16508 |
|
|
--UD1_shift_out_87_d[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[22]
|
| 16509 |
|
|
--operation mode is normal
|
| 16510 |
|
|
|
| 16511 |
|
|
UD1_shift_out_87_d[22] = PD1_a_o_0 & UD1_shift_out_80[22] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[22];
|
| 16512 |
|
|
|
| 16513 |
|
|
|
| 16514 |
|
|
--UD1_shift_out_85_d[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[22]
|
| 16515 |
|
|
--operation mode is normal
|
| 16516 |
|
|
|
| 16517 |
|
|
UD1_shift_out_85_d[22] = PD1_a_o_2 & UD1_shift_out_54[30] # !PD1_a_o_2 & UD1_shift_out_68[22];
|
| 16518 |
|
|
|
| 16519 |
|
|
|
| 16520 |
|
|
--UD1_shift_out_88[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[22]
|
| 16521 |
|
|
--operation mode is normal
|
| 16522 |
|
|
|
| 16523 |
|
|
UD1_shift_out_88[22] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_22 # !UD1_shift_out_sn_b10_0 & UD1_shift_out_79[22];
|
| 16524 |
|
|
|
| 16525 |
|
|
|
| 16526 |
|
|
--UD1_shift_out_92_d_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[22]
|
| 16527 |
|
|
--operation mode is normal
|
| 16528 |
|
|
|
| 16529 |
|
|
UD1_shift_out_92_d_a[22] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_63[22] # !PD1_a_o_4 & UD1_shift_out_63[30];
|
| 16530 |
|
|
|
| 16531 |
|
|
|
| 16532 |
|
|
--VD1_hilo_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22
|
| 16533 |
|
|
--operation mode is normal
|
| 16534 |
|
|
|
| 16535 |
|
|
VD1_hilo_22_lut_out = VD1_hilo_37_iv_0_0[22] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_22 # !VD1_hilo_37_iv_0_a[22];
|
| 16536 |
|
|
VD1_hilo_22 = DFFEAS(VD1_hilo_22_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16537 |
|
|
|
| 16538 |
|
|
|
| 16539 |
|
|
--VD1_hilo_54 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_54
|
| 16540 |
|
|
--operation mode is normal
|
| 16541 |
|
|
|
| 16542 |
|
|
VD1_hilo_54_lut_out = VD1_hilo_37_iv_0_a[54] & !VD1_hilo_37_iv_0_3[54] & !VD1_hilo_37_iv_0_o5[54] & !VD1_hilo_37_iv_0_a3[57];
|
| 16543 |
|
|
VD1_hilo_54 = DFFEAS(VD1_hilo_54_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16544 |
|
|
|
| 16545 |
|
|
|
| 16546 |
|
|
--PD1_a_o_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_22
|
| 16547 |
|
|
--operation mode is normal
|
| 16548 |
|
|
|
| 16549 |
|
|
PD1_a_o_22 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[22] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[22];
|
| 16550 |
|
|
|
| 16551 |
|
|
|
| 16552 |
|
|
--TD1_m61_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m61_a
|
| 16553 |
|
|
--operation mode is normal
|
| 16554 |
|
|
|
| 16555 |
|
|
TD1_m61_a = VD1_b_o_iv_22 & !TD1_m9 & PD1_a_o_22 # !VD1_b_o_iv_22 & !TD1_m5 # !PD1_a_o_22;
|
| 16556 |
|
|
|
| 16557 |
|
|
|
| 16558 |
|
|
--TD1_un1_a_add22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add22
|
| 16559 |
|
|
--operation mode is arithmetic
|
| 16560 |
|
|
|
| 16561 |
|
|
TD1_un1_a_add22_carry_eqn = TD1_un1_a_carry_21;
|
| 16562 |
|
|
TD1_un1_a_add22 = PD1_a_o_22 $ TD1_un1_b_1_combout[22] $ !TD1_un1_a_add22_carry_eqn;
|
| 16563 |
|
|
|
| 16564 |
|
|
--TD1_un1_a_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_22
|
| 16565 |
|
|
--operation mode is arithmetic
|
| 16566 |
|
|
|
| 16567 |
|
|
TD1_un1_a_carry_22 = CARRY(PD1_a_o_22 & TD1_un1_b_1_combout[22] # !TD1_un1_a_carry_21 # !PD1_a_o_22 & TD1_un1_b_1_combout[22] & !TD1_un1_a_carry_21);
|
| 16568 |
|
|
|
| 16569 |
|
|
|
| 16570 |
|
|
--UD1_shift_out_87_d[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[23]
|
| 16571 |
|
|
--operation mode is normal
|
| 16572 |
|
|
|
| 16573 |
|
|
UD1_shift_out_87_d[23] = PD1_a_o_0 & UD1_shift_out_80[23] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[23];
|
| 16574 |
|
|
|
| 16575 |
|
|
|
| 16576 |
|
|
--UD1_shift_out_85_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[23]
|
| 16577 |
|
|
--operation mode is normal
|
| 16578 |
|
|
|
| 16579 |
|
|
UD1_shift_out_85_a[23] = PD1_a_o_2 & !UD1_shift_out_54[31] # !PD1_a_o_2 & !PD1_a_o_1;
|
| 16580 |
|
|
|
| 16581 |
|
|
|
| 16582 |
|
|
--UD1_shift_out_88[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[23]
|
| 16583 |
|
|
--operation mode is normal
|
| 16584 |
|
|
|
| 16585 |
|
|
UD1_shift_out_88[23] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_23 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_88_a[23];
|
| 16586 |
|
|
|
| 16587 |
|
|
|
| 16588 |
|
|
--UD1_shift_out_92_d_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[23]
|
| 16589 |
|
|
--operation mode is normal
|
| 16590 |
|
|
|
| 16591 |
|
|
UD1_shift_out_92_d_a[23] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_63[23] # !PD1_a_o_4 & UD1_shift_out_77[23];
|
| 16592 |
|
|
|
| 16593 |
|
|
|
| 16594 |
|
|
--VD1_hilo_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_23
|
| 16595 |
|
|
--operation mode is normal
|
| 16596 |
|
|
|
| 16597 |
|
|
VD1_hilo_23_lut_out = VD1_hilo_37_iv_0[23] # VD1_hilo25 & VD1_hilo_8_Z[23] # !VD1_hilo_37_iv_a[23];
|
| 16598 |
|
|
VD1_hilo_23 = DFFEAS(VD1_hilo_23_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16599 |
|
|
|
| 16600 |
|
|
|
| 16601 |
|
|
--VD1_hilo_55 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_55
|
| 16602 |
|
|
--operation mode is normal
|
| 16603 |
|
|
|
| 16604 |
|
|
VD1_hilo_55_lut_out = !VD1_hilo_37_iv_2[55] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[55] # !VD1_hilo25;
|
| 16605 |
|
|
VD1_hilo_55 = DFFEAS(VD1_hilo_55_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 16606 |
|
|
|
| 16607 |
|
|
|
| 16608 |
|
|
--PD1_a_o_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_23
|
| 16609 |
|
|
--operation mode is normal
|
| 16610 |
|
|
|
| 16611 |
|
|
PD1_a_o_23 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[23] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[23];
|
| 16612 |
|
|
|
| 16613 |
|
|
|
| 16614 |
|
|
--TD1_m66_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m66_a
|
| 16615 |
|
|
--operation mode is normal
|
| 16616 |
|
|
|
| 16617 |
|
|
TD1_m66_a = VD1_b_o_iv_23 & !TD1_m9 & PD1_a_o_23 # !VD1_b_o_iv_23 & !PD1_a_o_23 # !TD1_m5;
|
| 16618 |
|
|
|
| 16619 |
|
|
|
| 16620 |
|
|
--TD1_un1_a_add23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add23
|
| 16621 |
|
|
--operation mode is arithmetic
|
| 16622 |
|
|
|
| 16623 |
|
|
TD1_un1_a_add23_carry_eqn = TD1_un1_a_carry_22;
|
| 16624 |
|
|
TD1_un1_a_add23 = PD1_a_o_23 $ TD1_un1_b_1_combout[23] $ TD1_un1_a_add23_carry_eqn;
|
| 16625 |
|
|
|
| 16626 |
|
|
--TD1_un1_a_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_23
|
| 16627 |
|
|
--operation mode is arithmetic
|
| 16628 |
|
|
|
| 16629 |
|
|
TD1_un1_a_carry_23 = CARRY(PD1_a_o_23 & !TD1_un1_b_1_combout[23] & !TD1_un1_a_carry_22 # !PD1_a_o_23 & !TD1_un1_a_carry_22 # !TD1_un1_b_1_combout[23]);
|
| 16630 |
|
|
|
| 16631 |
|
|
|
| 16632 |
|
|
--FD1_wb_o_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_22
|
| 16633 |
|
|
--operation mode is normal
|
| 16634 |
|
|
|
| 16635 |
|
|
FD1_wb_o_22 = TC1_wb_mux_ctl_o_0 & F1_dout_22 # DB1_r32_o_22 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_22;
|
| 16636 |
|
|
|
| 16637 |
|
|
--FD1_r_data_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_22
|
| 16638 |
|
|
--operation mode is normal
|
| 16639 |
|
|
|
| 16640 |
|
|
FD1_r_data_22 = DFFEAS(FD1_wb_o_22, E1__clk0, VCC, , , , , , );
|
| 16641 |
|
|
|
| 16642 |
|
|
|
| 16643 |
|
|
--ND1_dout_2_a_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_22
|
| 16644 |
|
|
--operation mode is normal
|
| 16645 |
|
|
|
| 16646 |
|
|
ND1_dout_2_a_22 = XD1_mux_fw_1 & !AB1_r32_o_20 # !XD1_mux_fw_1 & !QB1_r32_o_22;
|
| 16647 |
|
|
|
| 16648 |
|
|
|
| 16649 |
|
|
--SB1_un1_wr_en46_3_combout is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_wr_en46_3_combout
|
| 16650 |
|
|
--operation mode is normal
|
| 16651 |
|
|
|
| 16652 |
|
|
SB1_un1_wr_en46_3_combout = TB1_dout21 & RB1_c_0_d0 & QC1_dmem_ctl_o_3 # !SB1_wr_en46_0 # !TB1_dout21 & QC1_dmem_ctl_o_3 # !SB1_wr_en46_0;
|
| 16653 |
|
|
|
| 16654 |
|
|
|
| 16655 |
|
|
--WB2L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~94
|
| 16656 |
|
|
--operation mode is normal
|
| 16657 |
|
|
|
| 16658 |
|
|
WB2L1 = SB1_un1_wr_en46_3_combout # RB1_c_0_d0 & !WB2L2 # !RB1_c_0_d0 & !RB1_c_1;
|
| 16659 |
|
|
|
| 16660 |
|
|
|
| 16661 |
|
|
--WB2L2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~95
|
| 16662 |
|
|
--operation mode is normal
|
| 16663 |
|
|
|
| 16664 |
|
|
WB2L2 = SB1_wr_en47 # !WB2L1;
|
| 16665 |
|
|
|
| 16666 |
|
|
|
| 16667 |
|
|
--CB1_dout_2_14 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_14
|
| 16668 |
|
|
--operation mode is normal
|
| 16669 |
|
|
|
| 16670 |
|
|
CB1_dout_2_14 = ND1_dout7 & FD1_wb_o_14 # !ND1_dout7 & !ND1_dout_2_a_14;
|
| 16671 |
|
|
|
| 16672 |
|
|
--CB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_14
|
| 16673 |
|
|
--operation mode is normal
|
| 16674 |
|
|
|
| 16675 |
|
|
CB1_r32_o_14 = DFFEAS(CB1_dout_2_14, E1__clk0, VCC, , , , , , );
|
| 16676 |
|
|
|
| 16677 |
|
|
|
| 16678 |
|
|
--WB4L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1|q[0]~84
|
| 16679 |
|
|
--operation mode is normal
|
| 16680 |
|
|
|
| 16681 |
|
|
WB4L1 = SB1_un1_ctl_1_combout # RB1_c_0_d0 & WB4L2 # !RB1_c_0_d0 & !RB1_c_1;
|
| 16682 |
|
|
|
| 16683 |
|
|
|
| 16684 |
|
|
--WB4L2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1|q[0]~85
|
| 16685 |
|
|
--operation mode is normal
|
| 16686 |
|
|
|
| 16687 |
|
|
WB4L2 = WB4L1 & !SB1_un1_wr_en46_3_combout;
|
| 16688 |
|
|
|
| 16689 |
|
|
|
| 16690 |
|
|
--TB1_dout_1_2_a_x[30] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[30]
|
| 16691 |
|
|
--operation mode is normal
|
| 16692 |
|
|
|
| 16693 |
|
|
TB1_dout_1_2_a_x[30] = TB1_dout22 & !CB1_dout_2_14 # !TB1_dout22 & !CB1_dout_2_30;
|
| 16694 |
|
|
|
| 16695 |
|
|
|
| 16696 |
|
|
--GD1_dout_iv_1_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_8
|
| 16697 |
|
|
--operation mode is normal
|
| 16698 |
|
|
|
| 16699 |
|
|
GD1_dout_iv_1_8 = FD1_N_20_i_0_s3 & LD1_q_b[8] # !GD1_dout_iv_1_a[8];
|
| 16700 |
|
|
|
| 16701 |
|
|
|
| 16702 |
|
|
--PD1_a_o_3_d_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[6]
|
| 16703 |
|
|
--operation mode is normal
|
| 16704 |
|
|
|
| 16705 |
|
|
PD1_a_o_3_d_a[6] = PD1_a_o_sn_m2 & !PB1_r32_o_6 # !PD1_a_o_sn_m2 & !AB1_r32_o_4;
|
| 16706 |
|
|
|
| 16707 |
|
|
|
| 16708 |
|
|
--FD1_wb_o_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_21
|
| 16709 |
|
|
--operation mode is normal
|
| 16710 |
|
|
|
| 16711 |
|
|
FD1_wb_o_21 = TC1_wb_mux_ctl_o_0 & F1_dout_21 # DB1_r32_o_21 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_21;
|
| 16712 |
|
|
|
| 16713 |
|
|
--FD1_r_data_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_21
|
| 16714 |
|
|
--operation mode is normal
|
| 16715 |
|
|
|
| 16716 |
|
|
FD1_r_data_21 = DFFEAS(FD1_wb_o_21, E1__clk0, VCC, , , , , , );
|
| 16717 |
|
|
|
| 16718 |
|
|
|
| 16719 |
|
|
--ND1_dout_2_a_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_21
|
| 16720 |
|
|
--operation mode is normal
|
| 16721 |
|
|
|
| 16722 |
|
|
ND1_dout_2_a_21 = XD1_mux_fw_1 & !AB1_r32_o_19 # !XD1_mux_fw_1 & !QB1_r32_o_21;
|
| 16723 |
|
|
|
| 16724 |
|
|
|
| 16725 |
|
|
--CB1_dout_2_13 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_13
|
| 16726 |
|
|
--operation mode is normal
|
| 16727 |
|
|
|
| 16728 |
|
|
CB1_dout_2_13 = ND1_dout7 & FD1_wb_o_13 # !ND1_dout7 & !ND1_dout_2_a_13;
|
| 16729 |
|
|
|
| 16730 |
|
|
--CB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_13
|
| 16731 |
|
|
--operation mode is normal
|
| 16732 |
|
|
|
| 16733 |
|
|
CB1_r32_o_13 = DFFEAS(CB1_dout_2_13, E1__clk0, VCC, , , , , , );
|
| 16734 |
|
|
|
| 16735 |
|
|
|
| 16736 |
|
|
--TB1_dout_1_2_a_x[29] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[29]
|
| 16737 |
|
|
--operation mode is normal
|
| 16738 |
|
|
|
| 16739 |
|
|
TB1_dout_1_2_a_x[29] = TB1_dout22 & !CB1_dout_2_13 # !TB1_dout22 & !CB1_dout_2_29;
|
| 16740 |
|
|
|
| 16741 |
|
|
|
| 16742 |
|
|
--TB1_dout_1_2_a_x[28] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[28]
|
| 16743 |
|
|
--operation mode is normal
|
| 16744 |
|
|
|
| 16745 |
|
|
TB1_dout_1_2_a_x[28] = TB1_dout22 & !CB1_dout_2_12 # !TB1_dout22 & !CB1_dout_2_28;
|
| 16746 |
|
|
|
| 16747 |
|
|
|
| 16748 |
|
|
--CB1_dout_2_12 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_12
|
| 16749 |
|
|
--operation mode is normal
|
| 16750 |
|
|
|
| 16751 |
|
|
CB1_dout_2_12 = ND1_dout7 & FD1_wb_o_12 # !ND1_dout7 & !ND1_dout_2_a_12;
|
| 16752 |
|
|
|
| 16753 |
|
|
--CB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_12
|
| 16754 |
|
|
--operation mode is normal
|
| 16755 |
|
|
|
| 16756 |
|
|
CB1_r32_o_12 = DFFEAS(CB1_dout_2_12, E1__clk0, VCC, , , , , , );
|
| 16757 |
|
|
|
| 16758 |
|
|
|
| 16759 |
|
|
--M1_ua_state[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state[1]
|
| 16760 |
|
|
--operation mode is normal
|
| 16761 |
|
|
|
| 16762 |
|
|
M1_ua_state[1]_lut_out = M1_rxq1 & M1_ua_state[1] & !M1_clk_ctr_equ15_0_a2 # !M1_rxq1 & M1_ua_state[1] & !M1_clk_ctr_equ15_0_a2 # !M1_ua_state_i[0];
|
| 16763 |
|
|
M1_ua_state[1] = DFFEAS(M1_ua_state[1]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 16764 |
|
|
|
| 16765 |
|
|
|
| 16766 |
|
|
--M1_bit_ctr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr[1]
|
| 16767 |
|
|
--operation mode is arithmetic
|
| 16768 |
|
|
|
| 16769 |
|
|
M1_bit_ctr[1]_carry_eqn = M1_bit_ctr_cout[0];
|
| 16770 |
|
|
M1_bit_ctr[1]_lut_out = M1_bit_ctr[1] $ (M1_bit_ctr[1]_carry_eqn);
|
| 16771 |
|
|
M1_bit_ctr[1] = DFFEAS(M1_bit_ctr[1]_lut_out, E1__clk0, VCC, , , , , !M1_bit_ctr23_i_i, );
|
| 16772 |
|
|
|
| 16773 |
|
|
--M1_bit_ctr_cout[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr_cout[1]
|
| 16774 |
|
|
--operation mode is arithmetic
|
| 16775 |
|
|
|
| 16776 |
|
|
M1_bit_ctr_cout[1] = CARRY(!M1_bit_ctr_cout[0] # !M1_bit_ctr[1]);
|
| 16777 |
|
|
|
| 16778 |
|
|
|
| 16779 |
|
|
--M1_bit_ctr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr[2]
|
| 16780 |
|
|
--operation mode is normal
|
| 16781 |
|
|
|
| 16782 |
|
|
M1_bit_ctr[2]_carry_eqn = M1_bit_ctr_cout[1];
|
| 16783 |
|
|
M1_bit_ctr[2]_lut_out = M1_bit_ctr[2] $ (!M1_bit_ctr[2]_carry_eqn);
|
| 16784 |
|
|
M1_bit_ctr[2] = DFFEAS(M1_bit_ctr[2]_lut_out, E1__clk0, VCC, , , , , !M1_bit_ctr23_i_i, );
|
| 16785 |
|
|
|
| 16786 |
|
|
|
| 16787 |
|
|
--M1_bit_ctr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr[0]
|
| 16788 |
|
|
--operation mode is arithmetic
|
| 16789 |
|
|
|
| 16790 |
|
|
M1_bit_ctr[0]_lut_out = M1_bit_ctr[0] $ M1_clk_ctr_equ15_0_a2;
|
| 16791 |
|
|
M1_bit_ctr[0] = DFFEAS(M1_bit_ctr[0]_lut_out, E1__clk0, VCC, , , , , !M1_bit_ctr23_i_i, );
|
| 16792 |
|
|
|
| 16793 |
|
|
--M1_bit_ctr_cout[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr_cout[0]
|
| 16794 |
|
|
--operation mode is arithmetic
|
| 16795 |
|
|
|
| 16796 |
|
|
M1_bit_ctr_cout[0] = CARRY(M1_bit_ctr[0] & M1_clk_ctr_equ15_0_a2);
|
| 16797 |
|
|
|
| 16798 |
|
|
|
| 16799 |
|
|
--FD1_wb_o_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_19
|
| 16800 |
|
|
--operation mode is normal
|
| 16801 |
|
|
|
| 16802 |
|
|
FD1_wb_o_19 = TC1_wb_mux_ctl_o_0 & F1_dout_19 # DB1_r32_o_19 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_19;
|
| 16803 |
|
|
|
| 16804 |
|
|
--FD1_r_data_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_19
|
| 16805 |
|
|
--operation mode is normal
|
| 16806 |
|
|
|
| 16807 |
|
|
FD1_r_data_19 = DFFEAS(FD1_wb_o_19, E1__clk0, VCC, , , , , , );
|
| 16808 |
|
|
|
| 16809 |
|
|
|
| 16810 |
|
|
--ND1_dout_2_a_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_19
|
| 16811 |
|
|
--operation mode is normal
|
| 16812 |
|
|
|
| 16813 |
|
|
ND1_dout_2_a_19 = XD1_mux_fw_1 & !AB1_r32_o_17 # !XD1_mux_fw_1 & !QB1_r32_o_19;
|
| 16814 |
|
|
|
| 16815 |
|
|
|
| 16816 |
|
|
--CB1_dout_2_11 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_11
|
| 16817 |
|
|
--operation mode is normal
|
| 16818 |
|
|
|
| 16819 |
|
|
CB1_dout_2_11 = ND1_dout7 & FD1_wb_o_11 # !ND1_dout7 & !ND1_dout_2_a_11;
|
| 16820 |
|
|
|
| 16821 |
|
|
--CB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_11
|
| 16822 |
|
|
--operation mode is normal
|
| 16823 |
|
|
|
| 16824 |
|
|
CB1_r32_o_11 = DFFEAS(CB1_dout_2_11, E1__clk0, VCC, , , , , , );
|
| 16825 |
|
|
|
| 16826 |
|
|
|
| 16827 |
|
|
--TB1_dout_1_2_a_x[27] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[27]
|
| 16828 |
|
|
--operation mode is normal
|
| 16829 |
|
|
|
| 16830 |
|
|
TB1_dout_1_2_a_x[27] = TB1_dout22 & !CB1_dout_2_11 # !TB1_dout22 & !CB1_dout_2_27;
|
| 16831 |
|
|
|
| 16832 |
|
|
|
| 16833 |
|
|
--FD1_wb_o_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_18
|
| 16834 |
|
|
--operation mode is normal
|
| 16835 |
|
|
|
| 16836 |
|
|
FD1_wb_o_18 = TC1_wb_mux_ctl_o_0 & F1_dout_18 # DB1_r32_o_18 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_18;
|
| 16837 |
|
|
|
| 16838 |
|
|
--FD1_r_data_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_18
|
| 16839 |
|
|
--operation mode is normal
|
| 16840 |
|
|
|
| 16841 |
|
|
FD1_r_data_18 = DFFEAS(FD1_wb_o_18, E1__clk0, VCC, , , , , , );
|
| 16842 |
|
|
|
| 16843 |
|
|
|
| 16844 |
|
|
--ND1_dout_2_a_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_18
|
| 16845 |
|
|
--operation mode is normal
|
| 16846 |
|
|
|
| 16847 |
|
|
ND1_dout_2_a_18 = XD1_mux_fw_1 & !AB1_r32_o_16 # !XD1_mux_fw_1 & !QB1_r32_o_18;
|
| 16848 |
|
|
|
| 16849 |
|
|
|
| 16850 |
|
|
--TB1_dout_1_2_a_x[26] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[26]
|
| 16851 |
|
|
--operation mode is normal
|
| 16852 |
|
|
|
| 16853 |
|
|
TB1_dout_1_2_a_x[26] = TB1_dout22 & !CB1_dout_2_10 # !TB1_dout22 & !CB1_dout_2_26;
|
| 16854 |
|
|
|
| 16855 |
|
|
|
| 16856 |
|
|
--CB1_dout_2_10 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_10
|
| 16857 |
|
|
--operation mode is normal
|
| 16858 |
|
|
|
| 16859 |
|
|
CB1_dout_2_10 = ND1_dout7 & FD1_wb_o_10 # !ND1_dout7 & !ND1_dout_2_a_10;
|
| 16860 |
|
|
|
| 16861 |
|
|
--CB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_10
|
| 16862 |
|
|
--operation mode is normal
|
| 16863 |
|
|
|
| 16864 |
|
|
CB1_r32_o_10 = DFFEAS(CB1_dout_2_10, E1__clk0, VCC, , , , , , );
|
| 16865 |
|
|
|
| 16866 |
|
|
|
| 16867 |
|
|
--FD1_wb_o_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_17
|
| 16868 |
|
|
--operation mode is normal
|
| 16869 |
|
|
|
| 16870 |
|
|
FD1_wb_o_17 = TC1_wb_mux_ctl_o_0 & F1_dout_17 # DB1_r32_o_17 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_17;
|
| 16871 |
|
|
|
| 16872 |
|
|
--FD1_r_data_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_17
|
| 16873 |
|
|
--operation mode is normal
|
| 16874 |
|
|
|
| 16875 |
|
|
FD1_r_data_17 = DFFEAS(FD1_wb_o_17, E1__clk0, VCC, , , , , , );
|
| 16876 |
|
|
|
| 16877 |
|
|
|
| 16878 |
|
|
--ND1_dout_2_a_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_17
|
| 16879 |
|
|
--operation mode is normal
|
| 16880 |
|
|
|
| 16881 |
|
|
ND1_dout_2_a_17 = XD1_mux_fw_1 & !AB1_r32_o_15 # !XD1_mux_fw_1 & !QB1_r32_o_17;
|
| 16882 |
|
|
|
| 16883 |
|
|
|
| 16884 |
|
|
--TB1_dout_1_2_a_x[25] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[25]
|
| 16885 |
|
|
--operation mode is normal
|
| 16886 |
|
|
|
| 16887 |
|
|
TB1_dout_1_2_a_x[25] = TB1_dout22 & !CB1_dout_2_9 # !TB1_dout22 & !CB1_dout_2_25;
|
| 16888 |
|
|
|
| 16889 |
|
|
|
| 16890 |
|
|
--CB1_dout_2_9 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_9
|
| 16891 |
|
|
--operation mode is normal
|
| 16892 |
|
|
|
| 16893 |
|
|
CB1_dout_2_9 = ND1_dout7 & FD1_wb_o_9 # !ND1_dout7 & !ND1_dout_2_a_9;
|
| 16894 |
|
|
|
| 16895 |
|
|
--CB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_9
|
| 16896 |
|
|
--operation mode is normal
|
| 16897 |
|
|
|
| 16898 |
|
|
CB1_r32_o_9 = DFFEAS(CB1_dout_2_9, E1__clk0, VCC, , , , , , );
|
| 16899 |
|
|
|
| 16900 |
|
|
|
| 16901 |
|
|
--VD1_hilo_33_i_m_a[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[33]
|
| 16902 |
|
|
--operation mode is normal
|
| 16903 |
|
|
|
| 16904 |
|
|
VD1_hilo_33_i_m_a[33] = VD1_addnop2 & !VD1_un50_hilo_add1 # !VD1_addnop2 & !VD1_un59_hilo_add1;
|
| 16905 |
|
|
|
| 16906 |
|
|
|
| 16907 |
|
|
--VD1_hilo_15_1[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_1[56]
|
| 16908 |
|
|
--operation mode is normal
|
| 16909 |
|
|
|
| 16910 |
|
|
VD1_hilo_15_1[56] = VD1_sub_or_yn $ VD1_hilo[0];
|
| 16911 |
|
|
|
| 16912 |
|
|
|
| 16913 |
|
|
--VD1_hilo_22_a[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[33]
|
| 16914 |
|
|
--operation mode is normal
|
| 16915 |
|
|
|
| 16916 |
|
|
VD1_hilo_22_a[33] = VD1_sign & !VD1_hilo_34 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add2 # !VD1_hilo[0] & !VD1_hilo_34;
|
| 16917 |
|
|
|
| 16918 |
|
|
|
| 16919 |
|
|
--VD1_hilo_15_2[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[33]
|
| 16920 |
|
|
--operation mode is normal
|
| 16921 |
|
|
|
| 16922 |
|
|
VD1_hilo_15_2[33] = VD1_sub_or_yn & VD1_un59_hilo_add2 # !VD1_sub_or_yn & VD1_un50_hilo_add2;
|
| 16923 |
|
|
|
| 16924 |
|
|
|
| 16925 |
|
|
--FD1_wb_o_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_16
|
| 16926 |
|
|
--operation mode is normal
|
| 16927 |
|
|
|
| 16928 |
|
|
FD1_wb_o_16 = TC1_wb_mux_ctl_o_0 & F1_dout_16 # DB1_r32_o_16 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_16;
|
| 16929 |
|
|
|
| 16930 |
|
|
--FD1_r_data_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_16
|
| 16931 |
|
|
--operation mode is normal
|
| 16932 |
|
|
|
| 16933 |
|
|
FD1_r_data_16 = DFFEAS(FD1_wb_o_16, E1__clk0, VCC, , , , , , );
|
| 16934 |
|
|
|
| 16935 |
|
|
|
| 16936 |
|
|
--ND1_dout_2_a_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_16
|
| 16937 |
|
|
--operation mode is normal
|
| 16938 |
|
|
|
| 16939 |
|
|
ND1_dout_2_a_16 = XD1_mux_fw_1 & !AB1_r32_o_14 # !XD1_mux_fw_1 & !QB1_r32_o_16;
|
| 16940 |
|
|
|
| 16941 |
|
|
|
| 16942 |
|
|
--TB1_dout_1_2_a_x[24] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[24]
|
| 16943 |
|
|
--operation mode is normal
|
| 16944 |
|
|
|
| 16945 |
|
|
TB1_dout_1_2_a_x[24] = TB1_dout22 & !CB1_dout_2_8 # !TB1_dout22 & !CB1_dout_2_24;
|
| 16946 |
|
|
|
| 16947 |
|
|
|
| 16948 |
|
|
--VD1_hilo_24_add0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add0
|
| 16949 |
|
|
--operation mode is arithmetic
|
| 16950 |
|
|
|
| 16951 |
|
|
VD1_hilo_24_add0 = VD1_hilo_31 $ VD1_op2_reged[0];
|
| 16952 |
|
|
|
| 16953 |
|
|
--VD1_hilo_24_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_0
|
| 16954 |
|
|
--operation mode is arithmetic
|
| 16955 |
|
|
|
| 16956 |
|
|
VD1_hilo_24_carry_0 = CARRY(VD1_hilo_31 & VD1_op2_reged[0]);
|
| 16957 |
|
|
|
| 16958 |
|
|
|
| 16959 |
|
|
--VD1_hilo_33_i_m[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[32]
|
| 16960 |
|
|
--operation mode is normal
|
| 16961 |
|
|
|
| 16962 |
|
|
VD1_hilo_33_i_m[32] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[32] # !VD1_hilo_33_1[64] & !VD1_hilo[32];
|
| 16963 |
|
|
|
| 16964 |
|
|
|
| 16965 |
|
|
--VD1_hilo_37_iv_2_a[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[32]
|
| 16966 |
|
|
--operation mode is normal
|
| 16967 |
|
|
|
| 16968 |
|
|
VD1_hilo_37_iv_2_a[32] = VD1_hilo[0] & !VD1_hilo_22_Z[32] & VD1_hilo_1_sqmuxa_1 # !VD1_hilo[0] & VD1_hilo_0_sqmuxa # !VD1_hilo_22_Z[32] & VD1_hilo_1_sqmuxa_1;
|
| 16969 |
|
|
|
| 16970 |
|
|
|
| 16971 |
|
|
--VD1_hilo_37_iv_0_1[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[0]
|
| 16972 |
|
|
--operation mode is normal
|
| 16973 |
|
|
|
| 16974 |
|
|
VD1_hilo_37_iv_0_1[0] = VD1_hilo[0] & VD1_hilo_37_iv_0_o5[0] # !VD1_hilo[0] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_37_iv_0_1_a[0];
|
| 16975 |
|
|
|
| 16976 |
|
|
|
| 16977 |
|
|
--VD1_hilo_24_add32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add32
|
| 16978 |
|
|
--operation mode is normal
|
| 16979 |
|
|
|
| 16980 |
|
|
VD1_hilo_24_add32_carry_eqn = VD1_hilo_24_carry_31;
|
| 16981 |
|
|
VD1_hilo_24_add32 = VD1_hilo_63 $ VD1_un1_op2_reged_1_combout[32] $ !VD1_hilo_24_add32_carry_eqn;
|
| 16982 |
|
|
|
| 16983 |
|
|
|
| 16984 |
|
|
--KB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_30
|
| 16985 |
|
|
--operation mode is normal
|
| 16986 |
|
|
|
| 16987 |
|
|
KB1_r32_o_30_lut_out = DD1_pc_next_0_iv_1_30 # DD1_un1_pc_next46_0 & DD1_un1_pc_add30;
|
| 16988 |
|
|
KB1_r32_o_30 = DFFEAS(KB1_r32_o_30_lut_out, E1__clk0, VCC, , , , , , );
|
| 16989 |
|
|
|
| 16990 |
|
|
|
| 16991 |
|
|
--KB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_31
|
| 16992 |
|
|
--operation mode is normal
|
| 16993 |
|
|
|
| 16994 |
|
|
KB1_r32_o_31_lut_out = G1_BUS24839_m[31] # DD1_un1_pc_next46_0 & DD1_un1_pc_add31 # !DD1_pc_next_0_iv_a_0;
|
| 16995 |
|
|
KB1_r32_o_31 = DFFEAS(KB1_r32_o_31_lut_out, E1__clk0, VCC, , , , , , );
|
| 16996 |
|
|
|
| 16997 |
|
|
|
| 16998 |
|
|
--RD1_r32_o_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_29
|
| 16999 |
|
|
--operation mode is arithmetic
|
| 17000 |
|
|
|
| 17001 |
|
|
RD1_r32_o_29_carry_eqn = RD1_r32_o_cout[27];
|
| 17002 |
|
|
RD1_r32_o_29_lut_out = KB1_r32_o_29 $ (KB1_r32_o_28 & RD1_r32_o_29_carry_eqn);
|
| 17003 |
|
|
RD1_r32_o_29 = DFFEAS(RD1_r32_o_29_lut_out, E1__clk0, VCC, , , , , , );
|
| 17004 |
|
|
|
| 17005 |
|
|
--RD1_r32_o_cout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[29]
|
| 17006 |
|
|
--operation mode is arithmetic
|
| 17007 |
|
|
|
| 17008 |
|
|
RD1_r32_o_cout[29] = CARRY(!RD1_r32_o_cout[27] # !KB1_r32_o_29 # !KB1_r32_o_28);
|
| 17009 |
|
|
|
| 17010 |
|
|
|
| 17011 |
|
|
--PD1_a_o_3_d_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[31]
|
| 17012 |
|
|
--operation mode is normal
|
| 17013 |
|
|
|
| 17014 |
|
|
PD1_a_o_3_d_a[31] = PD1_a_o_sn_m2 & !PB1_r32_o_31 # !PD1_a_o_sn_m2 & !AB1_r32_o_29;
|
| 17015 |
|
|
|
| 17016 |
|
|
|
| 17017 |
|
|
--GD1_dout_iv_1_31 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_31
|
| 17018 |
|
|
--operation mode is normal
|
| 17019 |
|
|
|
| 17020 |
|
|
GD1_dout_iv_1_31 = FD1_N_20_i_0_s3 & LD1_q_b[31] # !GD1_dout_iv_1_a[31];
|
| 17021 |
|
|
|
| 17022 |
|
|
|
| 17023 |
|
|
--F1_dout_31 is mips_sys:isys|mips_dvc:imips_dvc|dout_31
|
| 17024 |
|
|
--operation mode is normal
|
| 17025 |
|
|
|
| 17026 |
|
|
F1_dout_31_lut_out = K1_cntr_31 & F1_dout_0_0_a3_4[0] # F1_cmd[31] & F1_dout_0_0_a3_3[0] # !K1_cntr_31 & F1_cmd[31] & F1_dout_0_0_a3_3[0];
|
| 17027 |
|
|
F1_dout_31 = DFFEAS(F1_dout_31_lut_out, E1__clk0, VCC, , , , , , );
|
| 17028 |
|
|
|
| 17029 |
|
|
|
| 17030 |
|
|
--DB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_31
|
| 17031 |
|
|
--operation mode is normal
|
| 17032 |
|
|
|
| 17033 |
|
|
DB1_r32_o_31_lut_out = WB63L1;
|
| 17034 |
|
|
DB1_r32_o_31 = DFFEAS(DB1_r32_o_31_lut_out, E1__clk0, VCC, , , , , , );
|
| 17035 |
|
|
|
| 17036 |
|
|
|
| 17037 |
|
|
--BB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_31
|
| 17038 |
|
|
--operation mode is normal
|
| 17039 |
|
|
|
| 17040 |
|
|
BB1_r32_o_31_lut_out = AB1_r32_o_29;
|
| 17041 |
|
|
BB1_r32_o_31 = DFFEAS(BB1_r32_o_31_lut_out, E1__clk0, VCC, , , , , , );
|
| 17042 |
|
|
|
| 17043 |
|
|
|
| 17044 |
|
|
--QB1_dout_iv_30 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_30
|
| 17045 |
|
|
--operation mode is normal
|
| 17046 |
|
|
|
| 17047 |
|
|
QB1_dout_iv_30 = GD1_dout_iv_1_30 # FD1_wb_o_30 & GD1_dout7_0_a2;
|
| 17048 |
|
|
|
| 17049 |
|
|
--QB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_30
|
| 17050 |
|
|
--operation mode is normal
|
| 17051 |
|
|
|
| 17052 |
|
|
QB1_r32_o_30 = DFFEAS(QB1_dout_iv_30, E1__clk0, VCC, , , , , , );
|
| 17053 |
|
|
|
| 17054 |
|
|
|
| 17055 |
|
|
--FD1_wb_o_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_30
|
| 17056 |
|
|
--operation mode is normal
|
| 17057 |
|
|
|
| 17058 |
|
|
FD1_wb_o_30 = TC1_wb_mux_ctl_o_0 & F1_dout_30 # DB1_r32_o_30 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_30;
|
| 17059 |
|
|
|
| 17060 |
|
|
--FD1_r_data_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_30
|
| 17061 |
|
|
--operation mode is normal
|
| 17062 |
|
|
|
| 17063 |
|
|
FD1_r_data_30 = DFFEAS(FD1_wb_o_30, E1__clk0, VCC, , , , , , );
|
| 17064 |
|
|
|
| 17065 |
|
|
|
| 17066 |
|
|
--PD1_a_o_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[29]
|
| 17067 |
|
|
--operation mode is normal
|
| 17068 |
|
|
|
| 17069 |
|
|
PD1_a_o_a[29] = SC1_muxa_ctl_o_1 & !FB1_r32_o_29 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_29;
|
| 17070 |
|
|
|
| 17071 |
|
|
|
| 17072 |
|
|
--PD1_a_o_3_Z[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[29]
|
| 17073 |
|
|
--operation mode is normal
|
| 17074 |
|
|
|
| 17075 |
|
|
PD1_a_o_3_Z[29] = PD1_a_o_3_s[0] & SD1_r32_o_29 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[29];
|
| 17076 |
|
|
|
| 17077 |
|
|
|
| 17078 |
|
|
--TD1_lt_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_27
|
| 17079 |
|
|
--operation mode is arithmetic
|
| 17080 |
|
|
|
| 17081 |
|
|
TD1_lt_27 = CARRY(PD1_a_o_27 & !TD1_lt_26 # !VD1_b_o_iv_27 # !PD1_a_o_27 & !VD1_b_o_iv_27 & !TD1_lt_26);
|
| 17082 |
|
|
|
| 17083 |
|
|
|
| 17084 |
|
|
--TD1_sum_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_28
|
| 17085 |
|
|
--operation mode is arithmetic
|
| 17086 |
|
|
|
| 17087 |
|
|
TD1_sum_carry_28 = CARRY(VD1_b_o_iv_28 & PD1_a_o_28 & !TD1_sum_carry_27 # !VD1_b_o_iv_28 & PD1_a_o_28 # !TD1_sum_carry_27);
|
| 17088 |
|
|
|
| 17089 |
|
|
|
| 17090 |
|
|
--Y1_q_b[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[7]
|
| 17091 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 17092 |
|
|
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
|
| 17093 |
|
|
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
|
| 17094 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 17095 |
|
|
Y1_q_b[7]_PORT_A_data_in = CB1_r32_o_7;
|
| 17096 |
|
|
Y1_q_b[7]_PORT_A_data_in_reg = DFFE(Y1_q_b[7]_PORT_A_data_in, Y1_q_b[7]_clock_0, , , );
|
| 17097 |
|
|
Y1_q_b[7]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
|
| 17098 |
|
|
Y1_q_b[7]_PORT_A_address_reg = DFFE(Y1_q_b[7]_PORT_A_address, Y1_q_b[7]_clock_0, , , );
|
| 17099 |
|
|
Y1_q_b[7]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
|
| 17100 |
|
|
Y1_q_b[7]_PORT_B_address_reg = DFFE(Y1_q_b[7]_PORT_B_address, Y1_q_b[7]_clock_1, , , Y1_q_b[7]_clock_enable_1);
|
| 17101 |
|
|
Y1_q_b[7]_PORT_A_write_enable = T1_valid_wreq;
|
| 17102 |
|
|
Y1_q_b[7]_PORT_A_write_enable_reg = DFFE(Y1_q_b[7]_PORT_A_write_enable, Y1_q_b[7]_clock_0, , , );
|
| 17103 |
|
|
Y1_q_b[7]_PORT_B_read_enable = VCC;
|
| 17104 |
|
|
Y1_q_b[7]_PORT_B_read_enable_reg = DFFE(Y1_q_b[7]_PORT_B_read_enable, Y1_q_b[7]_clock_1, , , Y1_q_b[7]_clock_enable_1);
|
| 17105 |
|
|
Y1_q_b[7]_clock_0 = E1__clk0;
|
| 17106 |
|
|
Y1_q_b[7]_clock_1 = E1__clk0;
|
| 17107 |
|
|
Y1_q_b[7]_clock_enable_1 = T1_valid_rreq;
|
| 17108 |
|
|
Y1_q_b[7]_PORT_B_data_out = MEMORY(Y1_q_b[7]_PORT_A_data_in_reg, , Y1_q_b[7]_PORT_A_address_reg, Y1_q_b[7]_PORT_B_address_reg, Y1_q_b[7]_PORT_A_write_enable_reg, Y1_q_b[7]_PORT_B_read_enable_reg, , , Y1_q_b[7]_clock_0, Y1_q_b[7]_clock_1, , Y1_q_b[7]_clock_enable_1, , );
|
| 17109 |
|
|
Y1_q_b[7] = Y1_q_b[7]_PORT_B_data_out[0];
|
| 17110 |
|
|
|
| 17111 |
|
|
|
| 17112 |
|
|
--ND1_dout_2_a_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_30
|
| 17113 |
|
|
--operation mode is normal
|
| 17114 |
|
|
|
| 17115 |
|
|
ND1_dout_2_a_30 = XD1_mux_fw_1 & !AB1_r32_o_28 # !XD1_mux_fw_1 & !QB1_r32_o_30;
|
| 17116 |
|
|
|
| 17117 |
|
|
|
| 17118 |
|
|
--ND1_dout_2_a_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_31
|
| 17119 |
|
|
--operation mode is normal
|
| 17120 |
|
|
|
| 17121 |
|
|
ND1_dout_2_a_31 = XD1_mux_fw_1 & !AB1_r32_o_29 # !XD1_mux_fw_1 & !QB1_r32_o_31;
|
| 17122 |
|
|
|
| 17123 |
|
|
|
| 17124 |
|
|
--FD1_wb_o_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_28
|
| 17125 |
|
|
--operation mode is normal
|
| 17126 |
|
|
|
| 17127 |
|
|
FD1_wb_o_28 = TC1_wb_mux_ctl_o_0 & F1_dout_28 # DB1_r32_o_28 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_28;
|
| 17128 |
|
|
|
| 17129 |
|
|
--FD1_r_data_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_28
|
| 17130 |
|
|
--operation mode is normal
|
| 17131 |
|
|
|
| 17132 |
|
|
FD1_r_data_28 = DFFEAS(FD1_wb_o_28, E1__clk0, VCC, , , , , , );
|
| 17133 |
|
|
|
| 17134 |
|
|
|
| 17135 |
|
|
--ND1_dout_2_a_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_28
|
| 17136 |
|
|
--operation mode is normal
|
| 17137 |
|
|
|
| 17138 |
|
|
ND1_dout_2_a_28 = XD1_mux_fw_1 & !AB1_r32_o_26 # !XD1_mux_fw_1 & !QB1_r32_o_28;
|
| 17139 |
|
|
|
| 17140 |
|
|
|
| 17141 |
|
|
--CB1_dout_2_27 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_27
|
| 17142 |
|
|
--operation mode is normal
|
| 17143 |
|
|
|
| 17144 |
|
|
CB1_dout_2_27 = ND1_dout7 & FD1_wb_o_27 # !ND1_dout7 & !ND1_dout_2_a_27;
|
| 17145 |
|
|
|
| 17146 |
|
|
--CB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_27
|
| 17147 |
|
|
--operation mode is normal
|
| 17148 |
|
|
|
| 17149 |
|
|
CB1_r32_o_27 = DFFEAS(CB1_dout_2_27, E1__clk0, VCC, , , , , , );
|
| 17150 |
|
|
|
| 17151 |
|
|
|
| 17152 |
|
|
--FD1_wb_o_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_29
|
| 17153 |
|
|
--operation mode is normal
|
| 17154 |
|
|
|
| 17155 |
|
|
FD1_wb_o_29 = TC1_wb_mux_ctl_o_0 & F1_dout_29 # DB1_r32_o_29 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_29;
|
| 17156 |
|
|
|
| 17157 |
|
|
--FD1_r_data_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_29
|
| 17158 |
|
|
--operation mode is normal
|
| 17159 |
|
|
|
| 17160 |
|
|
FD1_r_data_29 = DFFEAS(FD1_wb_o_29, E1__clk0, VCC, , , , , , );
|
| 17161 |
|
|
|
| 17162 |
|
|
|
| 17163 |
|
|
--ND1_dout_2_a_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_29
|
| 17164 |
|
|
--operation mode is normal
|
| 17165 |
|
|
|
| 17166 |
|
|
ND1_dout_2_a_29 = XD1_mux_fw_1 & !AB1_r32_o_27 # !XD1_mux_fw_1 & !QB1_r32_o_29;
|
| 17167 |
|
|
|
| 17168 |
|
|
|
| 17169 |
|
|
--CB1_dout_2_26 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_26
|
| 17170 |
|
|
--operation mode is normal
|
| 17171 |
|
|
|
| 17172 |
|
|
CB1_dout_2_26 = ND1_dout7 & FD1_wb_o_26 # !ND1_dout7 & !ND1_dout_2_a_26;
|
| 17173 |
|
|
|
| 17174 |
|
|
--CB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_26
|
| 17175 |
|
|
--operation mode is normal
|
| 17176 |
|
|
|
| 17177 |
|
|
CB1_r32_o_26 = DFFEAS(CB1_dout_2_26, E1__clk0, VCC, , , , , , );
|
| 17178 |
|
|
|
| 17179 |
|
|
|
| 17180 |
|
|
--CB1_dout_2_24 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_24
|
| 17181 |
|
|
--operation mode is normal
|
| 17182 |
|
|
|
| 17183 |
|
|
CB1_dout_2_24 = ND1_dout7 & FD1_wb_o_24 # !ND1_dout7 & !ND1_dout_2_a_24;
|
| 17184 |
|
|
|
| 17185 |
|
|
--CB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_24
|
| 17186 |
|
|
--operation mode is normal
|
| 17187 |
|
|
|
| 17188 |
|
|
CB1_r32_o_24 = DFFEAS(CB1_dout_2_24, E1__clk0, VCC, , , , , , );
|
| 17189 |
|
|
|
| 17190 |
|
|
|
| 17191 |
|
|
--CB1_dout_2_25 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_25
|
| 17192 |
|
|
--operation mode is normal
|
| 17193 |
|
|
|
| 17194 |
|
|
CB1_dout_2_25 = ND1_dout7 & FD1_wb_o_25 # !ND1_dout7 & !ND1_dout_2_a_25;
|
| 17195 |
|
|
|
| 17196 |
|
|
--CB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_25
|
| 17197 |
|
|
--operation mode is normal
|
| 17198 |
|
|
|
| 17199 |
|
|
CB1_r32_o_25 = DFFEAS(CB1_dout_2_25, E1__clk0, VCC, , , , , , );
|
| 17200 |
|
|
|
| 17201 |
|
|
|
| 17202 |
|
|
--CB1_dout_2_15 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_15
|
| 17203 |
|
|
--operation mode is normal
|
| 17204 |
|
|
|
| 17205 |
|
|
CB1_dout_2_15 = ND1_dout7 & FD1_wb_o_15 # !ND1_dout7 & !ND1_dout_2_a_15;
|
| 17206 |
|
|
|
| 17207 |
|
|
--CB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_15
|
| 17208 |
|
|
--operation mode is normal
|
| 17209 |
|
|
|
| 17210 |
|
|
CB1_r32_o_15 = DFFEAS(CB1_dout_2_15, E1__clk0, VCC, , , , , , );
|
| 17211 |
|
|
|
| 17212 |
|
|
|
| 17213 |
|
|
--M1_ua_state_i[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state_i[0]
|
| 17214 |
|
|
--operation mode is normal
|
| 17215 |
|
|
|
| 17216 |
|
|
M1_ua_state_i[0]_lut_out = !M1_ua_state[4] & M1_ua_state_i[0] # !M1_rxq1;
|
| 17217 |
|
|
M1_ua_state_i[0] = DFFEAS(M1_ua_state_i[0]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 17218 |
|
|
|
| 17219 |
|
|
|
| 17220 |
|
|
--M1_clk_ctr27_i_0_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_0_a
|
| 17221 |
|
|
--operation mode is normal
|
| 17222 |
|
|
|
| 17223 |
|
|
M1_clk_ctr27_i_0_a = !M1_un1_clk_ctr_equ0_0_a2 # !M1_clk_ctr27_i_0_a5_5 # !M1_clk_ctr27_i_0_a5_4 # !M1_clk_ctr_0;
|
| 17224 |
|
|
|
| 17225 |
|
|
|
| 17226 |
|
|
--HC1_pc_gen_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8|pc_gen_ctl_o_2
|
| 17227 |
|
|
--operation mode is normal
|
| 17228 |
|
|
|
| 17229 |
|
|
HC1_pc_gen_ctl_o_2_lut_out = WB26L2;
|
| 17230 |
|
|
HC1_pc_gen_ctl_o_2 = DFFEAS(HC1_pc_gen_ctl_o_2_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 17231 |
|
|
|
| 17232 |
|
|
|
| 17233 |
|
|
--HC1_pc_gen_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8|pc_gen_ctl_o_0
|
| 17234 |
|
|
--operation mode is normal
|
| 17235 |
|
|
|
| 17236 |
|
|
HC1_pc_gen_ctl_o_0_lut_out = WB06L2;
|
| 17237 |
|
|
HC1_pc_gen_ctl_o_0 = DFFEAS(HC1_pc_gen_ctl_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 17238 |
|
|
|
| 17239 |
|
|
|
| 17240 |
|
|
--HC1_pc_gen_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8|pc_gen_ctl_o_1
|
| 17241 |
|
|
--operation mode is normal
|
| 17242 |
|
|
|
| 17243 |
|
|
HC1_pc_gen_ctl_o_1_lut_out = WB16L1;
|
| 17244 |
|
|
HC1_pc_gen_ctl_o_1 = DFFEAS(HC1_pc_gen_ctl_o_1_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 17245 |
|
|
|
| 17246 |
|
|
|
| 17247 |
|
|
--AD1_CurrState_Sreg0_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_3
|
| 17248 |
|
|
--operation mode is normal
|
| 17249 |
|
|
|
| 17250 |
|
|
AD1_CurrState_Sreg0_3_lut_out = !WB35L1 & !WB45L1 & WB55L1 & AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
|
| 17251 |
|
|
AD1_CurrState_Sreg0_3 = DFFEAS(AD1_CurrState_Sreg0_3_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 17252 |
|
|
|
| 17253 |
|
|
|
| 17254 |
|
|
--DD1_pc_next_2_sqmuxa_1_i_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_2_sqmuxa_1_i_a2
|
| 17255 |
|
|
--operation mode is normal
|
| 17256 |
|
|
|
| 17257 |
|
|
DD1_pc_next_2_sqmuxa_1_i_a2 = !AD1_CurrState_Sreg0_5 & AD1_pc_prectl_1_0_i_a2_0_a2_1 & AD1_CurrState_Sreg0_3 # AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
|
| 17258 |
|
|
|
| 17259 |
|
|
|
| 17260 |
|
|
--DD1_pc_next_1_sqmuxa_0_a4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_1_sqmuxa_0_a4
|
| 17261 |
|
|
--operation mode is normal
|
| 17262 |
|
|
|
| 17263 |
|
|
DD1_pc_next_1_sqmuxa_0_a4 = !HC1_pc_gen_ctl_o_1 & !HC1_pc_gen_ctl_o_2 & HC1_pc_gen_ctl_o_0 & DD1_pc_next_2_sqmuxa_1_i_a2;
|
| 17264 |
|
|
|
| 17265 |
|
|
|
| 17266 |
|
|
--DD1_pc_next_0_sqmuxa_0_a4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_sqmuxa_0_a4
|
| 17267 |
|
|
--operation mode is normal
|
| 17268 |
|
|
|
| 17269 |
|
|
DD1_pc_next_0_sqmuxa_0_a4 = HC1_pc_gen_ctl_o_2 & !HC1_pc_gen_ctl_o_0 & HC1_pc_gen_ctl_o_1 & DD1_pc_next_2_sqmuxa_1_i_a2;
|
| 17270 |
|
|
|
| 17271 |
|
|
|
| 17272 |
|
|
--HD1_dout_iv_1_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_2
|
| 17273 |
|
|
--operation mode is normal
|
| 17274 |
|
|
|
| 17275 |
|
|
HD1_dout_iv_1_2 = FD1_N_18_i_0_s3 & LD2_q_b[2] # !HD1_dout_iv_1_a[2];
|
| 17276 |
|
|
|
| 17277 |
|
|
|
| 17278 |
|
|
--DD1_un1_pc_prectl_1_i_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_i_a[2]
|
| 17279 |
|
|
--operation mode is normal
|
| 17280 |
|
|
|
| 17281 |
|
|
DD1_un1_pc_prectl_1_i_a[2] = HC1_pc_gen_ctl_o_2 & !HC1_pc_gen_ctl_o_0 & !AD1_CurrState_Sreg0_5 & AD1_pc_prectl_1_0_i_a2_0_a2_1;
|
| 17282 |
|
|
|
| 17283 |
|
|
|
| 17284 |
|
|
--BD1_res_7_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_7_0
|
| 17285 |
|
|
--operation mode is normal
|
| 17286 |
|
|
|
| 17287 |
|
|
BD1_res_7_0 = BC1_cmp_ctl_o_0 & BD1_res_7_0_a # !BC1_cmp_ctl_o_0 & BD1_res_3_0;
|
| 17288 |
|
|
|
| 17289 |
|
|
|
| 17290 |
|
|
--HD1_dout_iv_1_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_3
|
| 17291 |
|
|
--operation mode is normal
|
| 17292 |
|
|
|
| 17293 |
|
|
HD1_dout_iv_1_3 = FD1_N_18_i_0_s3 & LD2_q_b[3] # !HD1_dout_iv_1_a[3];
|
| 17294 |
|
|
|
| 17295 |
|
|
|
| 17296 |
|
|
--DD1_un1_pc_prectl_1_0_a3[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a3[0]
|
| 17297 |
|
|
--operation mode is normal
|
| 17298 |
|
|
|
| 17299 |
|
|
DD1_un1_pc_prectl_1_0_a3[0] = !HC1_pc_gen_ctl_o_0 & DD1_un1_pc_prectl_1_0_a3_a[0] & AD1_pc_prectl_1_0_i_a2_0_a2_1 & BD1_res_7_0;
|
| 17300 |
|
|
|
| 17301 |
|
|
|
| 17302 |
|
|
--HD1_dout_iv_1_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_6
|
| 17303 |
|
|
--operation mode is normal
|
| 17304 |
|
|
|
| 17305 |
|
|
HD1_dout_iv_1_6 = FD1_N_18_i_0_s3 & LD2_q_b[6] # !HD1_dout_iv_1_a[6];
|
| 17306 |
|
|
|
| 17307 |
|
|
|
| 17308 |
|
|
--HD1_dout_iv_1_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_7
|
| 17309 |
|
|
--operation mode is normal
|
| 17310 |
|
|
|
| 17311 |
|
|
HD1_dout_iv_1_7 = FD1_N_18_i_0_s3 & LD2_q_b[7] # !HD1_dout_iv_1_a[7];
|
| 17312 |
|
|
|
| 17313 |
|
|
|
| 17314 |
|
|
--SD1_r32_o_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_8
|
| 17315 |
|
|
--operation mode is normal
|
| 17316 |
|
|
|
| 17317 |
|
|
SD1_r32_o_8_lut_out = KB1_r32_o_8;
|
| 17318 |
|
|
SD1_r32_o_8 = DFFEAS(SD1_r32_o_8_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 17319 |
|
|
|
| 17320 |
|
|
|
| 17321 |
|
|
--HD1_dout_iv_1_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_8
|
| 17322 |
|
|
--operation mode is normal
|
| 17323 |
|
|
|
| 17324 |
|
|
HD1_dout_iv_1_8 = FD1_N_18_i_0_s3 & LD2_q_b[8] # !HD1_dout_iv_1_a[8];
|
| 17325 |
|
|
|
| 17326 |
|
|
|
| 17327 |
|
|
--SD1_r32_o_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_9
|
| 17328 |
|
|
--operation mode is normal
|
| 17329 |
|
|
|
| 17330 |
|
|
SD1_r32_o_9_lut_out = KB1_r32_o_9;
|
| 17331 |
|
|
SD1_r32_o_9 = DFFEAS(SD1_r32_o_9_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 17332 |
|
|
|
| 17333 |
|
|
|
| 17334 |
|
|
--HD1_dout_iv_1_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_9
|
| 17335 |
|
|
--operation mode is normal
|
| 17336 |
|
|
|
| 17337 |
|
|
HD1_dout_iv_1_9 = FD1_N_18_i_0_s3 & LD2_q_b[9] # !HD1_dout_iv_1_a[9];
|
| 17338 |
|
|
|
| 17339 |
|
|
|
| 17340 |
|
|
--SD1_r32_o_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_10
|
| 17341 |
|
|
--operation mode is normal
|
| 17342 |
|
|
|
| 17343 |
|
|
SD1_r32_o_10_lut_out = KB1_r32_o_10;
|
| 17344 |
|
|
SD1_r32_o_10 = DFFEAS(SD1_r32_o_10_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 17345 |
|
|
|
| 17346 |
|
|
|
| 17347 |
|
|
--FB1_res_7_0_0_10 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_10
|
| 17348 |
|
|
--operation mode is normal
|
| 17349 |
|
|
|
| 17350 |
|
|
FB1_res_7_0_0_10 = ED1_r32_o_8 & CD1_res_7_0_0_o3_0 # ED1_r32_o_10 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_8 & ED1_r32_o_10 & CD1_res_7_0_0_a2_0;
|
| 17351 |
|
|
|
| 17352 |
|
|
--FB1_r32_o_0_10 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_10
|
| 17353 |
|
|
--operation mode is normal
|
| 17354 |
|
|
|
| 17355 |
|
|
FB1_r32_o_0_10 = DFFEAS(FB1_res_7_0_0_10, E1__clk0, VCC, , , , , , );
|
| 17356 |
|
|
|
| 17357 |
|
|
|
| 17358 |
|
|
--FD1_wb_o_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_10
|
| 17359 |
|
|
--operation mode is normal
|
| 17360 |
|
|
|
| 17361 |
|
|
FD1_wb_o_10 = TC1_wb_mux_ctl_o_0 & F1_dout_10 # DB1_r32_o_10 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_10;
|
| 17362 |
|
|
|
| 17363 |
|
|
--FD1_r_data_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_10
|
| 17364 |
|
|
--operation mode is normal
|
| 17365 |
|
|
|
| 17366 |
|
|
FD1_r_data_10 = DFFEAS(FD1_wb_o_10, E1__clk0, VCC, , , , , , );
|
| 17367 |
|
|
|
| 17368 |
|
|
|
| 17369 |
|
|
--HD1_dout_iv_1_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_10
|
| 17370 |
|
|
--operation mode is normal
|
| 17371 |
|
|
|
| 17372 |
|
|
HD1_dout_iv_1_10 = FD1_N_18_i_0_s3 & LD2_q_b[10] # !HD1_dout_iv_1_a[10];
|
| 17373 |
|
|
|
| 17374 |
|
|
|
| 17375 |
|
|
--SD1_r32_o_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_11
|
| 17376 |
|
|
--operation mode is normal
|
| 17377 |
|
|
|
| 17378 |
|
|
SD1_r32_o_11_lut_out = KB1_r32_o_11;
|
| 17379 |
|
|
SD1_r32_o_11 = DFFEAS(SD1_r32_o_11_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 17380 |
|
|
|
| 17381 |
|
|
|
| 17382 |
|
|
--FB1_res_7_0_0_11 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_11
|
| 17383 |
|
|
--operation mode is normal
|
| 17384 |
|
|
|
| 17385 |
|
|
FB1_res_7_0_0_11 = ED1_r32_o_9 & CD1_res_7_0_0_o3_0 # ED1_r32_o_11 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_9 & ED1_r32_o_11 & CD1_res_7_0_0_a2_0;
|
| 17386 |
|
|
|
| 17387 |
|
|
--FB1_r32_o_0_11 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_11
|
| 17388 |
|
|
--operation mode is normal
|
| 17389 |
|
|
|
| 17390 |
|
|
FB1_r32_o_0_11 = DFFEAS(FB1_res_7_0_0_11, E1__clk0, VCC, , , , , , );
|
| 17391 |
|
|
|
| 17392 |
|
|
|
| 17393 |
|
|
--FD1_wb_o_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_11
|
| 17394 |
|
|
--operation mode is normal
|
| 17395 |
|
|
|
| 17396 |
|
|
FD1_wb_o_11 = TC1_wb_mux_ctl_o_0 & F1_dout_11 # DB1_r32_o_11 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_11;
|
| 17397 |
|
|
|
| 17398 |
|
|
--FD1_r_data_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_11
|
| 17399 |
|
|
--operation mode is normal
|
| 17400 |
|
|
|
| 17401 |
|
|
FD1_r_data_11 = DFFEAS(FD1_wb_o_11, E1__clk0, VCC, , , , , , );
|
| 17402 |
|
|
|
| 17403 |
|
|
|
| 17404 |
|
|
--HD1_dout_iv_1_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_11
|
| 17405 |
|
|
--operation mode is normal
|
| 17406 |
|
|
|
| 17407 |
|
|
HD1_dout_iv_1_11 = FD1_N_18_i_0_s3 & LD2_q_b[11] # !HD1_dout_iv_1_a[11];
|
| 17408 |
|
|
|
| 17409 |
|
|
|
| 17410 |
|
|
--SD1_r32_o_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_12
|
| 17411 |
|
|
--operation mode is normal
|
| 17412 |
|
|
|
| 17413 |
|
|
SD1_r32_o_12_lut_out = KB1_r32_o_12;
|
| 17414 |
|
|
SD1_r32_o_12 = DFFEAS(SD1_r32_o_12_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 17415 |
|
|
|
| 17416 |
|
|
|
| 17417 |
|
|
--FB1_res_7_0_0_12 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_12
|
| 17418 |
|
|
--operation mode is normal
|
| 17419 |
|
|
|
| 17420 |
|
|
FB1_res_7_0_0_12 = ED1_r32_o_10 & CD1_res_7_0_0_o3_0 # ED1_r32_o_12 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_10 & ED1_r32_o_12 & CD1_res_7_0_0_a2_0;
|
| 17421 |
|
|
|
| 17422 |
|
|
--FB1_r32_o_0_12 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_12
|
| 17423 |
|
|
--operation mode is normal
|
| 17424 |
|
|
|
| 17425 |
|
|
FB1_r32_o_0_12 = DFFEAS(FB1_res_7_0_0_12, E1__clk0, VCC, , , , , , );
|
| 17426 |
|
|
|
| 17427 |
|
|
|
| 17428 |
|
|
--FD1_wb_o_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_12
|
| 17429 |
|
|
--operation mode is normal
|
| 17430 |
|
|
|
| 17431 |
|
|
FD1_wb_o_12 = TC1_wb_mux_ctl_o_0 & F1_dout_12 # DB1_r32_o_12 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_12;
|
| 17432 |
|
|
|
| 17433 |
|
|
--FD1_r_data_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_12
|
| 17434 |
|
|
--operation mode is normal
|
| 17435 |
|
|
|
| 17436 |
|
|
FD1_r_data_12 = DFFEAS(FD1_wb_o_12, E1__clk0, VCC, , , , , , );
|
| 17437 |
|
|
|
| 17438 |
|
|
|
| 17439 |
|
|
--HD1_dout_iv_1_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_12
|
| 17440 |
|
|
--operation mode is normal
|
| 17441 |
|
|
|
| 17442 |
|
|
HD1_dout_iv_1_12 = FD1_N_18_i_0_s3 & LD2_q_b[12] # !HD1_dout_iv_1_a[12];
|
| 17443 |
|
|
|
| 17444 |
|
|
|
| 17445 |
|
|
--FD1_wb_o_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_23
|
| 17446 |
|
|
--operation mode is normal
|
| 17447 |
|
|
|
| 17448 |
|
|
FD1_wb_o_23 = TC1_wb_mux_ctl_o_0 & F1_dout_23 # DB1_r32_o_23 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_23;
|
| 17449 |
|
|
|
| 17450 |
|
|
--FD1_r_data_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_23
|
| 17451 |
|
|
--operation mode is normal
|
| 17452 |
|
|
|
| 17453 |
|
|
FD1_r_data_23 = DFFEAS(FD1_wb_o_23, E1__clk0, VCC, , , , , , );
|
| 17454 |
|
|
|
| 17455 |
|
|
|
| 17456 |
|
|
--ND1_dout_2_a_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_23
|
| 17457 |
|
|
--operation mode is normal
|
| 17458 |
|
|
|
| 17459 |
|
|
ND1_dout_2_a_23 = XD1_mux_fw_1 & !AB1_r32_o_21 # !XD1_mux_fw_1 & !QB1_r32_o_23;
|
| 17460 |
|
|
|
| 17461 |
|
|
|
| 17462 |
|
|
--TB1_dout_1_2_a_x[31] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[31]
|
| 17463 |
|
|
--operation mode is normal
|
| 17464 |
|
|
|
| 17465 |
|
|
TB1_dout_1_2_a_x[31] = TB1_dout22 & !CB1_dout_2_15 # !TB1_dout22 & !CB1_dout_2_31;
|
| 17466 |
|
|
|
| 17467 |
|
|
|
| 17468 |
|
|
--YB1_wb_mux_1_0_0_a3_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_mux_1_0_0_a3_a_x[0]
|
| 17469 |
|
|
--operation mode is normal
|
| 17470 |
|
|
|
| 17471 |
|
|
YB1_wb_mux_1_0_0_a3_a_x[0] = KE1_q_a[2] & !KE1_q_a[4] # !KE1_q_a[3];
|
| 17472 |
|
|
|
| 17473 |
|
|
|
| 17474 |
|
|
--GD1_dout_iv_1_a[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[9]
|
| 17475 |
|
|
--operation mode is normal
|
| 17476 |
|
|
|
| 17477 |
|
|
GD1_dout_iv_1_a[9] = FD1_r_data_9 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_7 # !FD1_r_data_9 & !ZD1_mux_fw_1 # !AB1_r32_o_7;
|
| 17478 |
|
|
|
| 17479 |
|
|
|
| 17480 |
|
|
--LD1_q_b[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[9]
|
| 17481 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 17482 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 17483 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 17484 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 17485 |
|
|
LD1_q_b[9]_PORT_A_data_in = FD1_wb_o_9;
|
| 17486 |
|
|
LD1_q_b[9]_PORT_A_data_in_reg = DFFE(LD1_q_b[9]_PORT_A_data_in, LD1_q_b[9]_clock_0, , , );
|
| 17487 |
|
|
LD1_q_b[9]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 17488 |
|
|
LD1_q_b[9]_PORT_A_address_reg = DFFE(LD1_q_b[9]_PORT_A_address, LD1_q_b[9]_clock_0, , , );
|
| 17489 |
|
|
LD1_q_b[9]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 17490 |
|
|
LD1_q_b[9]_PORT_B_address_reg = DFFE(LD1_q_b[9]_PORT_B_address, LD1_q_b[9]_clock_1, , , );
|
| 17491 |
|
|
LD1_q_b[9]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 17492 |
|
|
LD1_q_b[9]_PORT_A_write_enable_reg = DFFE(LD1_q_b[9]_PORT_A_write_enable, LD1_q_b[9]_clock_0, , , );
|
| 17493 |
|
|
LD1_q_b[9]_PORT_B_read_enable = VCC;
|
| 17494 |
|
|
LD1_q_b[9]_PORT_B_read_enable_reg = DFFE(LD1_q_b[9]_PORT_B_read_enable, LD1_q_b[9]_clock_1, , , );
|
| 17495 |
|
|
LD1_q_b[9]_clock_0 = E1__clk0;
|
| 17496 |
|
|
LD1_q_b[9]_clock_1 = E1__clk0;
|
| 17497 |
|
|
LD1_q_b[9]_PORT_B_data_out = MEMORY(LD1_q_b[9]_PORT_A_data_in_reg, , LD1_q_b[9]_PORT_A_address_reg, LD1_q_b[9]_PORT_B_address_reg, LD1_q_b[9]_PORT_A_write_enable_reg, LD1_q_b[9]_PORT_B_read_enable_reg, , , LD1_q_b[9]_clock_0, LD1_q_b[9]_clock_1, , , , );
|
| 17498 |
|
|
LD1_q_b[9] = LD1_q_b[9]_PORT_B_data_out[0];
|
| 17499 |
|
|
|
| 17500 |
|
|
|
| 17501 |
|
|
--F1_cmd[9] is mips_sys:isys|mips_dvc:imips_dvc|cmd[9]
|
| 17502 |
|
|
--operation mode is normal
|
| 17503 |
|
|
|
| 17504 |
|
|
F1_cmd[9]_lut_out = CB1_r32_o_9;
|
| 17505 |
|
|
F1_cmd[9] = DFFEAS(F1_cmd[9]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 17506 |
|
|
|
| 17507 |
|
|
|
| 17508 |
|
|
--QB1_dout_iv_11 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_11
|
| 17509 |
|
|
--operation mode is normal
|
| 17510 |
|
|
|
| 17511 |
|
|
QB1_dout_iv_11 = GD1_dout_iv_1_11 # FD1_wb_o_11 & GD1_dout7_0_a2;
|
| 17512 |
|
|
|
| 17513 |
|
|
--QB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_11
|
| 17514 |
|
|
--operation mode is normal
|
| 17515 |
|
|
|
| 17516 |
|
|
QB1_r32_o_11 = DFFEAS(QB1_dout_iv_11, E1__clk0, VCC, , , , , , );
|
| 17517 |
|
|
|
| 17518 |
|
|
|
| 17519 |
|
|
--QB1_dout_iv_13 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_13
|
| 17520 |
|
|
--operation mode is normal
|
| 17521 |
|
|
|
| 17522 |
|
|
QB1_dout_iv_13 = GD1_dout_iv_1_13 # FD1_wb_o_13 & GD1_dout7_0_a2;
|
| 17523 |
|
|
|
| 17524 |
|
|
--QB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_13
|
| 17525 |
|
|
--operation mode is normal
|
| 17526 |
|
|
|
| 17527 |
|
|
QB1_r32_o_13 = DFFEAS(QB1_dout_iv_13, E1__clk0, VCC, , , , , , );
|
| 17528 |
|
|
|
| 17529 |
|
|
|
| 17530 |
|
|
--FB1_res_7_0_0_13 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_13
|
| 17531 |
|
|
--operation mode is normal
|
| 17532 |
|
|
|
| 17533 |
|
|
FB1_res_7_0_0_13 = ED1_r32_o_11 & CD1_res_7_0_0_o3_0 # ED1_r32_o_13 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_11 & ED1_r32_o_13 & CD1_res_7_0_0_a2_0;
|
| 17534 |
|
|
|
| 17535 |
|
|
--FB1_r32_o_0_13 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_13
|
| 17536 |
|
|
--operation mode is normal
|
| 17537 |
|
|
|
| 17538 |
|
|
FB1_r32_o_0_13 = DFFEAS(FB1_res_7_0_0_13, E1__clk0, VCC, , , , , , );
|
| 17539 |
|
|
|
| 17540 |
|
|
|
| 17541 |
|
|
--FD1_wb_o_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_13
|
| 17542 |
|
|
--operation mode is normal
|
| 17543 |
|
|
|
| 17544 |
|
|
FD1_wb_o_13 = TC1_wb_mux_ctl_o_0 & F1_dout_13 # DB1_r32_o_13 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_13;
|
| 17545 |
|
|
|
| 17546 |
|
|
--FD1_r_data_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_13
|
| 17547 |
|
|
--operation mode is normal
|
| 17548 |
|
|
|
| 17549 |
|
|
FD1_r_data_13 = DFFEAS(FD1_wb_o_13, E1__clk0, VCC, , , , , , );
|
| 17550 |
|
|
|
| 17551 |
|
|
|
| 17552 |
|
|
--QB1_dout_iv_12 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_12
|
| 17553 |
|
|
--operation mode is normal
|
| 17554 |
|
|
|
| 17555 |
|
|
QB1_dout_iv_12 = GD1_dout_iv_1_12 # FD1_wb_o_12 & GD1_dout7_0_a2;
|
| 17556 |
|
|
|
| 17557 |
|
|
--QB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_12
|
| 17558 |
|
|
--operation mode is normal
|
| 17559 |
|
|
|
| 17560 |
|
|
QB1_r32_o_12 = DFFEAS(QB1_dout_iv_12, E1__clk0, VCC, , , , , , );
|
| 17561 |
|
|
|
| 17562 |
|
|
|
| 17563 |
|
|
--QB1_dout_iv_14 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_14
|
| 17564 |
|
|
--operation mode is normal
|
| 17565 |
|
|
|
| 17566 |
|
|
QB1_dout_iv_14 = GD1_dout_iv_1_14 # FD1_wb_o_14 & GD1_dout7_0_a2;
|
| 17567 |
|
|
|
| 17568 |
|
|
--QB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_14
|
| 17569 |
|
|
--operation mode is normal
|
| 17570 |
|
|
|
| 17571 |
|
|
QB1_r32_o_14 = DFFEAS(QB1_dout_iv_14, E1__clk0, VCC, , , , , , );
|
| 17572 |
|
|
|
| 17573 |
|
|
|
| 17574 |
|
|
--FB1_res_7_0_0_14 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_14
|
| 17575 |
|
|
--operation mode is normal
|
| 17576 |
|
|
|
| 17577 |
|
|
FB1_res_7_0_0_14 = ED1_r32_o_12 & CD1_res_7_0_0_o3_0 # ED1_r32_o_14 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_12 & ED1_r32_o_14 & CD1_res_7_0_0_a2_0;
|
| 17578 |
|
|
|
| 17579 |
|
|
--FB1_r32_o_0_14 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_14
|
| 17580 |
|
|
--operation mode is normal
|
| 17581 |
|
|
|
| 17582 |
|
|
FB1_r32_o_0_14 = DFFEAS(FB1_res_7_0_0_14, E1__clk0, VCC, , , , , , );
|
| 17583 |
|
|
|
| 17584 |
|
|
|
| 17585 |
|
|
--FD1_wb_o_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_14
|
| 17586 |
|
|
--operation mode is normal
|
| 17587 |
|
|
|
| 17588 |
|
|
FD1_wb_o_14 = TC1_wb_mux_ctl_o_0 & F1_dout_14 # DB1_r32_o_14 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_14;
|
| 17589 |
|
|
|
| 17590 |
|
|
--FD1_r_data_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_14
|
| 17591 |
|
|
--operation mode is normal
|
| 17592 |
|
|
|
| 17593 |
|
|
FD1_r_data_14 = DFFEAS(FD1_wb_o_14, E1__clk0, VCC, , , , , , );
|
| 17594 |
|
|
|
| 17595 |
|
|
|
| 17596 |
|
|
--HD1_dout_iv_1_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_1
|
| 17597 |
|
|
--operation mode is normal
|
| 17598 |
|
|
|
| 17599 |
|
|
HD1_dout_iv_1_1 = FD1_N_18_i_0_s3 & LD2_q_b[1] # !HD1_dout_iv_1_a[1];
|
| 17600 |
|
|
|
| 17601 |
|
|
|
| 17602 |
|
|
--HD1_dout_iv_1_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_0
|
| 17603 |
|
|
--operation mode is normal
|
| 17604 |
|
|
|
| 17605 |
|
|
HD1_dout_iv_1_0 = FD1_N_18_i_0_s3 & LD2_q_b[0] # !HD1_dout_iv_1_a[0];
|
| 17606 |
|
|
|
| 17607 |
|
|
|
| 17608 |
|
|
--QB1_dout_iv_21 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_21
|
| 17609 |
|
|
--operation mode is normal
|
| 17610 |
|
|
|
| 17611 |
|
|
QB1_dout_iv_21 = GD1_dout_iv_1_21 # FD1_wb_o_21 & GD1_dout7_0_a2;
|
| 17612 |
|
|
|
| 17613 |
|
|
--QB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_21
|
| 17614 |
|
|
--operation mode is normal
|
| 17615 |
|
|
|
| 17616 |
|
|
QB1_r32_o_21 = DFFEAS(QB1_dout_iv_21, E1__clk0, VCC, , , , , , );
|
| 17617 |
|
|
|
| 17618 |
|
|
|
| 17619 |
|
|
--FB1_res_7_0_0_21 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_21
|
| 17620 |
|
|
--operation mode is normal
|
| 17621 |
|
|
|
| 17622 |
|
|
FB1_res_7_0_0_21 = CD1_res_7_0_0_a3_0 # ED1_r32_o_5 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_18;
|
| 17623 |
|
|
|
| 17624 |
|
|
--FB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_21
|
| 17625 |
|
|
--operation mode is normal
|
| 17626 |
|
|
|
| 17627 |
|
|
FB1_r32_o_21 = DFFEAS(FB1_res_7_0_0_21, E1__clk0, VCC, , , , , , );
|
| 17628 |
|
|
|
| 17629 |
|
|
|
| 17630 |
|
|
--QB1_dout_iv_22 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_22
|
| 17631 |
|
|
--operation mode is normal
|
| 17632 |
|
|
|
| 17633 |
|
|
QB1_dout_iv_22 = GD1_dout_iv_1_22 # FD1_wb_o_22 & GD1_dout7_0_a2;
|
| 17634 |
|
|
|
| 17635 |
|
|
--QB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_22
|
| 17636 |
|
|
--operation mode is normal
|
| 17637 |
|
|
|
| 17638 |
|
|
QB1_r32_o_22 = DFFEAS(QB1_dout_iv_22, E1__clk0, VCC, , , , , , );
|
| 17639 |
|
|
|
| 17640 |
|
|
|
| 17641 |
|
|
--FB1_res_7_0_0_22 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_22
|
| 17642 |
|
|
--operation mode is normal
|
| 17643 |
|
|
|
| 17644 |
|
|
FB1_res_7_0_0_22 = CD1_res_7_0_0_a3_0 # ED1_r32_o_6 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_19;
|
| 17645 |
|
|
|
| 17646 |
|
|
--FB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_22
|
| 17647 |
|
|
--operation mode is normal
|
| 17648 |
|
|
|
| 17649 |
|
|
FB1_r32_o_22 = DFFEAS(FB1_res_7_0_0_22, E1__clk0, VCC, , , , , , );
|
| 17650 |
|
|
|
| 17651 |
|
|
|
| 17652 |
|
|
--QB1_dout_iv_25 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_25
|
| 17653 |
|
|
--operation mode is normal
|
| 17654 |
|
|
|
| 17655 |
|
|
QB1_dout_iv_25 = GD1_dout_iv_1_25 # FD1_wb_o_25 & GD1_dout7_0_a2;
|
| 17656 |
|
|
|
| 17657 |
|
|
--QB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_25
|
| 17658 |
|
|
--operation mode is normal
|
| 17659 |
|
|
|
| 17660 |
|
|
QB1_r32_o_25 = DFFEAS(QB1_dout_iv_25, E1__clk0, VCC, , , , , , );
|
| 17661 |
|
|
|
| 17662 |
|
|
|
| 17663 |
|
|
--FB1_res_7_0_0_25 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_25
|
| 17664 |
|
|
--operation mode is normal
|
| 17665 |
|
|
|
| 17666 |
|
|
FB1_res_7_0_0_25 = CD1_res_7_0_0_a3_0 # ED1_r32_o_9 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_22;
|
| 17667 |
|
|
|
| 17668 |
|
|
--FB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_25
|
| 17669 |
|
|
--operation mode is normal
|
| 17670 |
|
|
|
| 17671 |
|
|
FB1_r32_o_25 = DFFEAS(FB1_res_7_0_0_25, E1__clk0, VCC, , , , , , );
|
| 17672 |
|
|
|
| 17673 |
|
|
|
| 17674 |
|
|
--FD1_wb_o_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_25
|
| 17675 |
|
|
--operation mode is normal
|
| 17676 |
|
|
|
| 17677 |
|
|
FD1_wb_o_25 = TC1_wb_mux_ctl_o_0 & F1_dout_25 # DB1_r32_o_25 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_25;
|
| 17678 |
|
|
|
| 17679 |
|
|
--FD1_r_data_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_25
|
| 17680 |
|
|
--operation mode is normal
|
| 17681 |
|
|
|
| 17682 |
|
|
FD1_r_data_25 = DFFEAS(FD1_wb_o_25, E1__clk0, VCC, , , , , , );
|
| 17683 |
|
|
|
| 17684 |
|
|
|
| 17685 |
|
|
--QB1_dout_iv_26 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_26
|
| 17686 |
|
|
--operation mode is normal
|
| 17687 |
|
|
|
| 17688 |
|
|
QB1_dout_iv_26 = GD1_dout_iv_1_26 # FD1_wb_o_26 & GD1_dout7_0_a2;
|
| 17689 |
|
|
|
| 17690 |
|
|
--QB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_26
|
| 17691 |
|
|
--operation mode is normal
|
| 17692 |
|
|
|
| 17693 |
|
|
QB1_r32_o_26 = DFFEAS(QB1_dout_iv_26, E1__clk0, VCC, , , , , , );
|
| 17694 |
|
|
|
| 17695 |
|
|
|
| 17696 |
|
|
--FB1_res_7_0_0_26 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_26
|
| 17697 |
|
|
--operation mode is normal
|
| 17698 |
|
|
|
| 17699 |
|
|
FB1_res_7_0_0_26 = CD1_res_7_0_0_a3_0 # ED1_r32_o_10 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_23;
|
| 17700 |
|
|
|
| 17701 |
|
|
--FB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_26
|
| 17702 |
|
|
--operation mode is normal
|
| 17703 |
|
|
|
| 17704 |
|
|
FB1_r32_o_26 = DFFEAS(FB1_res_7_0_0_26, E1__clk0, VCC, , , , , , );
|
| 17705 |
|
|
|
| 17706 |
|
|
|
| 17707 |
|
|
--FD1_wb_o_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_26
|
| 17708 |
|
|
--operation mode is normal
|
| 17709 |
|
|
|
| 17710 |
|
|
FD1_wb_o_26 = TC1_wb_mux_ctl_o_0 & F1_dout_26 # DB1_r32_o_26 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_26;
|
| 17711 |
|
|
|
| 17712 |
|
|
--FD1_r_data_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_26
|
| 17713 |
|
|
--operation mode is normal
|
| 17714 |
|
|
|
| 17715 |
|
|
FD1_r_data_26 = DFFEAS(FD1_wb_o_26, E1__clk0, VCC, , , , , , );
|
| 17716 |
|
|
|
| 17717 |
|
|
|
| 17718 |
|
|
--QB1_dout_iv_29 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_29
|
| 17719 |
|
|
--operation mode is normal
|
| 17720 |
|
|
|
| 17721 |
|
|
QB1_dout_iv_29 = GD1_dout_iv_1_29 # FD1_wb_o_29 & GD1_dout7_0_a2;
|
| 17722 |
|
|
|
| 17723 |
|
|
--QB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_29
|
| 17724 |
|
|
--operation mode is normal
|
| 17725 |
|
|
|
| 17726 |
|
|
QB1_r32_o_29 = DFFEAS(QB1_dout_iv_29, E1__clk0, VCC, , , , , , );
|
| 17727 |
|
|
|
| 17728 |
|
|
|
| 17729 |
|
|
--FB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_29
|
| 17730 |
|
|
--operation mode is normal
|
| 17731 |
|
|
|
| 17732 |
|
|
FB1_r32_o_29_lut_out = CD1_res_7_0_0_a3_0 # ED1_r32_o_13 & CD1_res_7_0_0_a2_16;
|
| 17733 |
|
|
FB1_r32_o_29 = DFFEAS(FB1_r32_o_29_lut_out, E1__clk0, VCC, , , , , , );
|
| 17734 |
|
|
|
| 17735 |
|
|
|
| 17736 |
|
|
--QB1_dout_iv_17 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_17
|
| 17737 |
|
|
--operation mode is normal
|
| 17738 |
|
|
|
| 17739 |
|
|
QB1_dout_iv_17 = GD1_dout_iv_1_17 # FD1_wb_o_17 & GD1_dout7_0_a2;
|
| 17740 |
|
|
|
| 17741 |
|
|
--QB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_17
|
| 17742 |
|
|
--operation mode is normal
|
| 17743 |
|
|
|
| 17744 |
|
|
QB1_r32_o_17 = DFFEAS(QB1_dout_iv_17, E1__clk0, VCC, , , , , , );
|
| 17745 |
|
|
|
| 17746 |
|
|
|
| 17747 |
|
|
--FB1_res_7_0_0_17 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_17
|
| 17748 |
|
|
--operation mode is normal
|
| 17749 |
|
|
|
| 17750 |
|
|
FB1_res_7_0_0_17 = ED1_r32_o_1 & CD1_res_7_0_0_a2_16 # ED1_r32_o_15 & CD1_res_7_0_0_a_14 # !ED1_r32_o_1 & ED1_r32_o_15 & CD1_res_7_0_0_a_14;
|
| 17751 |
|
|
|
| 17752 |
|
|
--FB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_17
|
| 17753 |
|
|
--operation mode is normal
|
| 17754 |
|
|
|
| 17755 |
|
|
FB1_r32_o_17 = DFFEAS(FB1_res_7_0_0_17, E1__clk0, VCC, , , , , , );
|
| 17756 |
|
|
|
| 17757 |
|
|
|
| 17758 |
|
|
--QB1_dout_iv_18 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_18
|
| 17759 |
|
|
--operation mode is normal
|
| 17760 |
|
|
|
| 17761 |
|
|
QB1_dout_iv_18 = GD1_dout_iv_1_18 # FD1_wb_o_18 & GD1_dout7_0_a2;
|
| 17762 |
|
|
|
| 17763 |
|
|
--QB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_18
|
| 17764 |
|
|
--operation mode is normal
|
| 17765 |
|
|
|
| 17766 |
|
|
QB1_r32_o_18 = DFFEAS(QB1_dout_iv_18, E1__clk0, VCC, , , , , , );
|
| 17767 |
|
|
|
| 17768 |
|
|
|
| 17769 |
|
|
--FB1_res_7_0_0_18 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_18
|
| 17770 |
|
|
--operation mode is normal
|
| 17771 |
|
|
|
| 17772 |
|
|
FB1_res_7_0_0_18 = CD1_res_7_0_0_a3_0 # ED1_r32_o_2 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_15;
|
| 17773 |
|
|
|
| 17774 |
|
|
--FB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_18
|
| 17775 |
|
|
--operation mode is normal
|
| 17776 |
|
|
|
| 17777 |
|
|
FB1_r32_o_18 = DFFEAS(FB1_res_7_0_0_18, E1__clk0, VCC, , , , , , );
|
| 17778 |
|
|
|
| 17779 |
|
|
|
| 17780 |
|
|
--VD1_hilo_37_iv_0_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[8]
|
| 17781 |
|
|
--operation mode is normal
|
| 17782 |
|
|
|
| 17783 |
|
|
VD1_hilo_37_iv_0_a[8] = VD1_add1 & !VD1_un134_hilo_combout[8] # !VD1_add1 & !VD1_hilo_8;
|
| 17784 |
|
|
|
| 17785 |
|
|
|
| 17786 |
|
|
--VD1_finish_0_sqmuxa_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|finish_0_sqmuxa_i
|
| 17787 |
|
|
--operation mode is normal
|
| 17788 |
|
|
|
| 17789 |
|
|
VD1_finish_0_sqmuxa_i = VD1_rdy_0_sqmuxa # VD1_hilo_4_sqmuxa_0 & VD1_addnop2110 # !sys_rst;
|
| 17790 |
|
|
|
| 17791 |
|
|
|
| 17792 |
|
|
--VD1_un50_hilo_add9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add9
|
| 17793 |
|
|
--operation mode is arithmetic
|
| 17794 |
|
|
|
| 17795 |
|
|
VD1_un50_hilo_add9_carry_eqn = VD1_un50_hilo_carry_8;
|
| 17796 |
|
|
VD1_un50_hilo_add9 = VD1_hilo_41 $ VD1_nop2_reged[9] $ VD1_un50_hilo_add9_carry_eqn;
|
| 17797 |
|
|
|
| 17798 |
|
|
--VD1_un50_hilo_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_9
|
| 17799 |
|
|
--operation mode is arithmetic
|
| 17800 |
|
|
|
| 17801 |
|
|
VD1_un50_hilo_carry_9 = CARRY(VD1_hilo_41 & !VD1_nop2_reged[9] & !VD1_un50_hilo_carry_8 # !VD1_hilo_41 & !VD1_un50_hilo_carry_8 # !VD1_nop2_reged[9]);
|
| 17802 |
|
|
|
| 17803 |
|
|
|
| 17804 |
|
|
--VD1_un59_hilo_add9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add9
|
| 17805 |
|
|
--operation mode is arithmetic
|
| 17806 |
|
|
|
| 17807 |
|
|
VD1_un59_hilo_add9_carry_eqn = VD1_un59_hilo_carry_8;
|
| 17808 |
|
|
VD1_un59_hilo_add9 = VD1_hilo_41 $ VD1_op2_reged[9] $ VD1_un59_hilo_add9_carry_eqn;
|
| 17809 |
|
|
|
| 17810 |
|
|
--VD1_un59_hilo_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_9
|
| 17811 |
|
|
--operation mode is arithmetic
|
| 17812 |
|
|
|
| 17813 |
|
|
VD1_un59_hilo_carry_9 = CARRY(VD1_hilo_41 & !VD1_op2_reged[9] & !VD1_un59_hilo_carry_8 # !VD1_hilo_41 & !VD1_un59_hilo_carry_8 # !VD1_op2_reged[9]);
|
| 17814 |
|
|
|
| 17815 |
|
|
|
| 17816 |
|
|
--VD1_hilo_37_iv_0_1[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[40]
|
| 17817 |
|
|
--operation mode is normal
|
| 17818 |
|
|
|
| 17819 |
|
|
VD1_hilo_37_iv_0_1[40] = VD1_hilo_37_iv_0_1_a[40] # VD1_addop2 & !VD1_un59_hilo_add8 & VD1_hilo_37_iv_0_a2_7[34];
|
| 17820 |
|
|
|
| 17821 |
|
|
|
| 17822 |
|
|
--VD1_hilo_37_iv_0_5_a[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[40]
|
| 17823 |
|
|
--operation mode is normal
|
| 17824 |
|
|
|
| 17825 |
|
|
VD1_hilo_37_iv_0_5_a[40] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add8 # !VD1_hilo_24_add8 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add8;
|
| 17826 |
|
|
|
| 17827 |
|
|
|
| 17828 |
|
|
--VD1_nop2_reged[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[7]
|
| 17829 |
|
|
--operation mode is arithmetic
|
| 17830 |
|
|
|
| 17831 |
|
|
VD1_nop2_reged[7]_carry_eqn = VD1_nop2_reged_cout[5];
|
| 17832 |
|
|
VD1_nop2_reged[7] = VD1_op2_reged[7] $ (VD1_op2_reged[6] # !VD1_nop2_reged[7]_carry_eqn);
|
| 17833 |
|
|
|
| 17834 |
|
|
--VD1_nop2_reged_cout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[7]
|
| 17835 |
|
|
--operation mode is arithmetic
|
| 17836 |
|
|
|
| 17837 |
|
|
VD1_nop2_reged_cout[7] = CARRY(VD1_op2_reged[7] # VD1_op2_reged[6] # !VD1_nop2_reged_cout[5]);
|
| 17838 |
|
|
|
| 17839 |
|
|
|
| 17840 |
|
|
--VD1_un1_op2_reged_1_combout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[6]
|
| 17841 |
|
|
--operation mode is normal
|
| 17842 |
|
|
|
| 17843 |
|
|
VD1_un1_op2_reged_1_combout[6] = VD1_eqop2_2_32 & VD1_op2_reged[6] # !VD1_eqop2_2_32 & VD1_nop2_reged[6];
|
| 17844 |
|
|
|
| 17845 |
|
|
|
| 17846 |
|
|
--YB1_rd_sel_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_a[0]
|
| 17847 |
|
|
--operation mode is normal
|
| 17848 |
|
|
|
| 17849 |
|
|
YB1_rd_sel_2_0_0_a[0] = !YB1_rd_sel_2_0_0_a3_0[0] & !YB1_alu_func_2_i_m3_0_a2_0_x[2] & !YB1_alu_func_2_0_0_a2_2_x[0] # !YB1_alu_func_2_0_0_a2_x[0];
|
| 17850 |
|
|
|
| 17851 |
|
|
|
| 17852 |
|
|
--YB1_rd_sel_2_0_0_0_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_0_Z[1]
|
| 17853 |
|
|
--operation mode is normal
|
| 17854 |
|
|
|
| 17855 |
|
|
YB1_rd_sel_2_0_0_0_Z[1] = KE1_q_a[5] # YB1_rd_sel_2_0_0_0_a[1] & !KE1_q_a[6] # !KE1_q_a[7];
|
| 17856 |
|
|
|
| 17857 |
|
|
|
| 17858 |
|
|
--YB1_rd_sel_2_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_a[1]
|
| 17859 |
|
|
--operation mode is normal
|
| 17860 |
|
|
|
| 17861 |
|
|
YB1_rd_sel_2_0_0_a[1] = !KE1_q_a[4] & YB1_cmp_ctl_2_0_0_a2_1[0] # YB1_cmp_ctl_2_0_0_a2_0[0] & !KE1_q_a[3];
|
| 17862 |
|
|
|
| 17863 |
|
|
|
| 17864 |
|
|
--YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl350_1_0_a2_0_a3_0_o2_x
|
| 17865 |
|
|
--operation mode is normal
|
| 17866 |
|
|
|
| 17867 |
|
|
YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x = KE1_q_a[2] # !KE1_q_a[3];
|
| 17868 |
|
|
|
| 17869 |
|
|
|
| 17870 |
|
|
--YB1_alu_we_1_0_0_a3_1[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3_1[0]
|
| 17871 |
|
|
--operation mode is normal
|
| 17872 |
|
|
|
| 17873 |
|
|
YB1_alu_we_1_0_0_a3_1[0] = !KE1_q_a[3] & !KE1_q_a[4] & !KE1_q_a[7] & YB1_alu_we_1_0_0_a3_1_0[0];
|
| 17874 |
|
|
|
| 17875 |
|
|
|
| 17876 |
|
|
--YB1_alu_we_1_0_0_a3_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3_a_x[0]
|
| 17877 |
|
|
--operation mode is normal
|
| 17878 |
|
|
|
| 17879 |
|
|
YB1_alu_we_1_0_0_a3_a_x[0] = !KE1_q_a[3] & !KE1_q_a[4] & !KE1_q_a[7];
|
| 17880 |
|
|
|
| 17881 |
|
|
|
| 17882 |
|
|
--YB1_alu_func_2_i_m3_0_a2_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a2_0_x[2]
|
| 17883 |
|
|
--operation mode is normal
|
| 17884 |
|
|
|
| 17885 |
|
|
YB1_alu_func_2_i_m3_0_a2_0_x[2] = GE1_q_a[1] & !GE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[3];
|
| 17886 |
|
|
|
| 17887 |
|
|
|
| 17888 |
|
|
--YB1_alu_func_2_0_0_a2_2_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_2_x[0]
|
| 17889 |
|
|
--operation mode is normal
|
| 17890 |
|
|
|
| 17891 |
|
|
YB1_alu_func_2_0_0_a2_2_x[0] = !GE1_q_a[5] & !GE1_q_a[0] & YB1_alu_func_2_0_0_a2_0_x[3];
|
| 17892 |
|
|
|
| 17893 |
|
|
|
| 17894 |
|
|
--F1_dout_20 is mips_sys:isys|mips_dvc:imips_dvc|dout_20
|
| 17895 |
|
|
--operation mode is normal
|
| 17896 |
|
|
|
| 17897 |
|
|
F1_dout_20_lut_out = K1_cntr_20 & F1_dout_0_0_a3_4[0] # F1_cmd[20] & F1_dout_0_0_a3_3[0] # !K1_cntr_20 & F1_cmd[20] & F1_dout_0_0_a3_3[0];
|
| 17898 |
|
|
F1_dout_20 = DFFEAS(F1_dout_20_lut_out, E1__clk0, VCC, , , , , , );
|
| 17899 |
|
|
|
| 17900 |
|
|
|
| 17901 |
|
|
--DB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_20
|
| 17902 |
|
|
--operation mode is normal
|
| 17903 |
|
|
|
| 17904 |
|
|
DB1_r32_o_20_lut_out = WB52L1;
|
| 17905 |
|
|
DB1_r32_o_20 = DFFEAS(DB1_r32_o_20_lut_out, E1__clk0, VCC, , , , , , );
|
| 17906 |
|
|
|
| 17907 |
|
|
|
| 17908 |
|
|
--BB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_20
|
| 17909 |
|
|
--operation mode is normal
|
| 17910 |
|
|
|
| 17911 |
|
|
BB1_r32_o_20_lut_out = AB1_r32_o_18;
|
| 17912 |
|
|
BB1_r32_o_20 = DFFEAS(BB1_r32_o_20_lut_out, E1__clk0, VCC, , , , , , );
|
| 17913 |
|
|
|
| 17914 |
|
|
|
| 17915 |
|
|
--QB1_dout_iv_20 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_20
|
| 17916 |
|
|
--operation mode is normal
|
| 17917 |
|
|
|
| 17918 |
|
|
QB1_dout_iv_20 = GD1_dout_iv_1_20 # FD1_wb_o_20 & GD1_dout7_0_a2;
|
| 17919 |
|
|
|
| 17920 |
|
|
--QB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_20
|
| 17921 |
|
|
--operation mode is normal
|
| 17922 |
|
|
|
| 17923 |
|
|
QB1_r32_o_20 = DFFEAS(QB1_dout_iv_20, E1__clk0, VCC, , , , , , );
|
| 17924 |
|
|
|
| 17925 |
|
|
|
| 17926 |
|
|
--AD1_delay_counter_Sreg0[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[1]
|
| 17927 |
|
|
--operation mode is normal
|
| 17928 |
|
|
|
| 17929 |
|
|
AD1_delay_counter_Sreg0[1]_lut_out = WB86L1;
|
| 17930 |
|
|
AD1_delay_counter_Sreg0[1] = DFFEAS(AD1_delay_counter_Sreg0[1]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 17931 |
|
|
|
| 17932 |
|
|
|
| 17933 |
|
|
--AD1_delay_counter_Sreg0[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[2]
|
| 17934 |
|
|
--operation mode is normal
|
| 17935 |
|
|
|
| 17936 |
|
|
AD1_delay_counter_Sreg0[2]_lut_out = WB96L1;
|
| 17937 |
|
|
AD1_delay_counter_Sreg0[2] = DFFEAS(AD1_delay_counter_Sreg0[2]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 17938 |
|
|
|
| 17939 |
|
|
|
| 17940 |
|
|
--AD1_delay_counter_Sreg0[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[3]
|
| 17941 |
|
|
--operation mode is normal
|
| 17942 |
|
|
|
| 17943 |
|
|
AD1_delay_counter_Sreg0[3]_lut_out = WB07L1 # !sys_rst;
|
| 17944 |
|
|
AD1_delay_counter_Sreg0[3] = DFFEAS(AD1_delay_counter_Sreg0[3]_lut_out, E1__clk0, VCC, , , , , , );
|
| 17945 |
|
|
|
| 17946 |
|
|
|
| 17947 |
|
|
--AD1_delay_counter_Sreg0[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[4]
|
| 17948 |
|
|
--operation mode is normal
|
| 17949 |
|
|
|
| 17950 |
|
|
AD1_delay_counter_Sreg0[4]_lut_out = WB17L1;
|
| 17951 |
|
|
AD1_delay_counter_Sreg0[4] = DFFEAS(AD1_delay_counter_Sreg0[4]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );
|
| 17952 |
|
|
|
| 17953 |
|
|
|
| 17954 |
|
|
--YB1_fsm_dly_2_0_0_a2_0_a_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a2_0_a_x[2]
|
| 17955 |
|
|
--operation mode is normal
|
| 17956 |
|
|
|
| 17957 |
|
|
YB1_fsm_dly_2_0_0_a2_0_a_x[2] = !JE1_q_a[5] & !JE1_q_a[6] & !KE1_q_a[0];
|
| 17958 |
|
|
|
| 17959 |
|
|
|
| 17960 |
|
|
--YB1_alu_we_1s_1_o2_0_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1s_1_o2_0_x[0]
|
| 17961 |
|
|
--operation mode is normal
|
| 17962 |
|
|
|
| 17963 |
|
|
YB1_alu_we_1s_1_o2_0_x[0] = JE1_q_a[2] # JE1_q_a[3] # JE1_q_a[1];
|
| 17964 |
|
|
|
| 17965 |
|
|
|
| 17966 |
|
|
--YB1_alu_func_2_0_0_a2_0_x[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_0_x[3]
|
| 17967 |
|
|
--operation mode is normal
|
| 17968 |
|
|
|
| 17969 |
|
|
YB1_alu_func_2_0_0_a2_0_x[3] = !KE1_q_a[2] & !KE1_q_a[6] & !GE1_q_a[2];
|
| 17970 |
|
|
|
| 17971 |
|
|
|
| 17972 |
|
|
--YB1_alu_func_2_0_0_1_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1_Z[1]
|
| 17973 |
|
|
--operation mode is normal
|
| 17974 |
|
|
|
| 17975 |
|
|
YB1_alu_func_2_0_0_1_Z[1] = !YB1_alu_func_2_0_0_1_a[1] & GE1_q_a[1] # YB1_alu_func_2_0_0_a2_2[4] # YB1_alu_func_2_0_0_a2_2_x[0];
|
| 17976 |
|
|
|
| 17977 |
|
|
|
| 17978 |
|
|
--YB1_ext_ctl_2_0_0_o2[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_o2[2]
|
| 17979 |
|
|
--operation mode is normal
|
| 17980 |
|
|
|
| 17981 |
|
|
YB1_ext_ctl_2_0_0_o2[2] = YB1_cmp_ctl_2_0_0_a2_0[0] # KE1_q_a[2] & JE1_q_a[0] # YB1_alu_we_1s_1_o2_0_x[0];
|
| 17982 |
|
|
|
| 17983 |
|
|
|
| 17984 |
|
|
--YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_o2_0_x[0]
|
| 17985 |
|
|
--operation mode is normal
|
| 17986 |
|
|
|
| 17987 |
|
|
YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0] = KE1_q_a[3] # !KE1_q_a[7];
|
| 17988 |
|
|
|
| 17989 |
|
|
|
| 17990 |
|
|
--YB1_ext_ctl_2_0_0_a2_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a2_0_x[2]
|
| 17991 |
|
|
--operation mode is normal
|
| 17992 |
|
|
|
| 17993 |
|
|
YB1_ext_ctl_2_0_0_a2_0_x[2] = !KE1_q_a[3] & !KE1_q_a[5] & !KE1_q_a[7];
|
| 17994 |
|
|
|
| 17995 |
|
|
|
| 17996 |
|
|
--YB1_cmp_ctl_2_0_0_a2_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a2_x[0]
|
| 17997 |
|
|
--operation mode is normal
|
| 17998 |
|
|
|
| 17999 |
|
|
YB1_cmp_ctl_2_0_0_a2_x[0] = !KE1_q_a[5] & KE1_q_a[4];
|
| 18000 |
|
|
|
| 18001 |
|
|
|
| 18002 |
|
|
--YB1_cmp_ctl_2_0_0_a2_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a2_x[2]
|
| 18003 |
|
|
--operation mode is normal
|
| 18004 |
|
|
|
| 18005 |
|
|
YB1_cmp_ctl_2_0_0_a2_x[2] = KE1_q_a[2] & !JE1_q_a[4] & !YB1_alu_we_1s_1_o2_0_x[0];
|
| 18006 |
|
|
|
| 18007 |
|
|
|
| 18008 |
|
|
--YB1_pc_gen_ctl_2_0_0_a2_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_0_0_a2_x[1]
|
| 18009 |
|
|
--operation mode is normal
|
| 18010 |
|
|
|
| 18011 |
|
|
YB1_pc_gen_ctl_2_0_0_a2_x[1] = !GE1_q_a[4] & !GE1_q_a[1];
|
| 18012 |
|
|
|
| 18013 |
|
|
|
| 18014 |
|
|
--YB1_alu_func_2_0_0_a2_1_x[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_1_x[3]
|
| 18015 |
|
|
--operation mode is normal
|
| 18016 |
|
|
|
| 18017 |
|
|
YB1_alu_func_2_0_0_a2_1_x[3] = !GE1_q_a[4] & GE1_q_a[5];
|
| 18018 |
|
|
|
| 18019 |
|
|
|
| 18020 |
|
|
--YB1_alu_func_2_i_m3_0_a3_5[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a3_5[2]
|
| 18021 |
|
|
--operation mode is normal
|
| 18022 |
|
|
|
| 18023 |
|
|
YB1_alu_func_2_i_m3_0_a3_5[2] = GE1_q_a[0] & !GE1_q_a[3] & YB1_alu_func_2_i_m3_0_a3_5_a[2] & YB1_alu_func_2_0_0_a2_0_x[3];
|
| 18024 |
|
|
|
| 18025 |
|
|
|
| 18026 |
|
|
--YB1_alu_func_2_i_m3_0_2[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_2[2]
|
| 18027 |
|
|
--operation mode is normal
|
| 18028 |
|
|
|
| 18029 |
|
|
YB1_alu_func_2_i_m3_0_2[2] = YB1_alu_func_2_i_m3_0_a3_0_x[2] # !KE1_q_a[5] & YB1_alu_func_2_i_m3_0_2_a[2] # !YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0];
|
| 18030 |
|
|
|
| 18031 |
|
|
|
| 18032 |
|
|
--YB1_alu_func_2_i_m3_0_5_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_5_a[2]
|
| 18033 |
|
|
--operation mode is normal
|
| 18034 |
|
|
|
| 18035 |
|
|
YB1_alu_func_2_i_m3_0_5_a[2] = !KE1_q_a[3] & YB1_alu_func_2_0_0_a2_0_x[4] # YB1_cmp_ctl_2_0_0_a2_0[0] & WB93L2;
|
| 18036 |
|
|
|
| 18037 |
|
|
|
| 18038 |
|
|
--YB1_alu_func_2_0_0_a3_0_a_x[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_0_a_x[3]
|
| 18039 |
|
|
--operation mode is normal
|
| 18040 |
|
|
|
| 18041 |
|
|
YB1_alu_func_2_0_0_a3_0_a_x[3] = !KE1_q_a[3] & YB1_cmp_ctl_2_0_0_a2_0[0] # YB1_cmp_ctl_2_0_0_a2_1[0];
|
| 18042 |
|
|
|
| 18043 |
|
|
|
| 18044 |
|
|
--YB1_alu_func_2_0_0_a3_1_a[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_1_a[3]
|
| 18045 |
|
|
--operation mode is normal
|
| 18046 |
|
|
|
| 18047 |
|
|
YB1_alu_func_2_0_0_a3_1_a[3] = !KE1_q_a[2] & !KE1_q_a[6] & !GE1_q_a[2] & !KE1_q_a[3];
|
| 18048 |
|
|
|
| 18049 |
|
|
|
| 18050 |
|
|
--YB1_alu_func_2_0_0_1_a[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1_a[4]
|
| 18051 |
|
|
--operation mode is normal
|
| 18052 |
|
|
|
| 18053 |
|
|
YB1_alu_func_2_0_0_1_a[4] = !YB1_alu_func_2_0_0_a2_2[4] & GE1_q_a[1] # !YB1_alu_func_2_0_0_a2_2_x[1] # !GE1_q_a[0];
|
| 18054 |
|
|
|
| 18055 |
|
|
|
| 18056 |
|
|
--YB1_alu_func_2_0_0_o2_0_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_o2_0_a_x[0]
|
| 18057 |
|
|
--operation mode is normal
|
| 18058 |
|
|
|
| 18059 |
|
|
YB1_alu_func_2_0_0_o2_0_a_x[0] = !KE1_q_a[2] & !KE1_q_a[6] & GE1_q_a[5];
|
| 18060 |
|
|
|
| 18061 |
|
|
|
| 18062 |
|
|
--YB1_alu_func_2_0_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_0_a[0]
|
| 18063 |
|
|
--operation mode is normal
|
| 18064 |
|
|
|
| 18065 |
|
|
YB1_alu_func_2_0_0_0_a[0] = GE1_q_a[1] & !GE1_q_a[5] & YB1_alu_func_2_0_0_a2_0_x[3] # !GE1_q_a[1] & YB1_alu_func_2_0_0_a2_2[4];
|
| 18066 |
|
|
|
| 18067 |
|
|
|
| 18068 |
|
|
--VD1_hilo_37_iv_0_1_a[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[36]
|
| 18069 |
|
|
--operation mode is normal
|
| 18070 |
|
|
|
| 18071 |
|
|
VD1_hilo_37_iv_0_1_a[36] = VD1_hilo_4 & !VD1_hilo_36 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_hilo_4 & VD1_hilo_0_sqmuxa # !VD1_hilo_36 & VD1_hilo_37_iv_0_o3_2[34];
|
| 18072 |
|
|
|
| 18073 |
|
|
|
| 18074 |
|
|
--YB1_muxb_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_0
|
| 18075 |
|
|
--operation mode is normal
|
| 18076 |
|
|
|
| 18077 |
|
|
YB1_muxb_ctl_2_0_0_0 = YB1_muxa_ctl_2_0_0_a3_1[0] # !GE1_q_a[4] & YB1_muxb_ctl_2_0_0_a3_0_0_x[0] # !YB1_muxb_ctl_2_0_0_a[0];
|
| 18078 |
|
|
|
| 18079 |
|
|
|
| 18080 |
|
|
--WB85L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxb_ctl_1_0_|lpm_latch:U1|q[0]~56
|
| 18081 |
|
|
--operation mode is normal
|
| 18082 |
|
|
|
| 18083 |
|
|
WB85L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_muxb_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB85L1;
|
| 18084 |
|
|
|
| 18085 |
|
|
|
| 18086 |
|
|
--YB1_muxb_ctl_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_1
|
| 18087 |
|
|
--operation mode is normal
|
| 18088 |
|
|
|
| 18089 |
|
|
YB1_muxb_ctl_2_0_0_1 = KE1_q_a[5] # YB1_muxb_ctl_2_0_0_0_Z[1] # !KE1_q_a[6] & YB1_muxb_ctl_2_0_0_a[1];
|
| 18090 |
|
|
|
| 18091 |
|
|
|
| 18092 |
|
|
--WB95L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1|q[0]~68
|
| 18093 |
|
|
--operation mode is normal
|
| 18094 |
|
|
|
| 18095 |
|
|
WB95L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_muxb_ctl_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB95L2;
|
| 18096 |
|
|
|
| 18097 |
|
|
|
| 18098 |
|
|
--WB95L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1|q[0]~69
|
| 18099 |
|
|
--operation mode is normal
|
| 18100 |
|
|
|
| 18101 |
|
|
WB95L2 = WB95L1 & !YB1_un1_ins_i_23_2_0;
|
| 18102 |
|
|
|
| 18103 |
|
|
|
| 18104 |
|
|
--YB1_ext_ctl_2_i_m3_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_1
|
| 18105 |
|
|
--operation mode is normal
|
| 18106 |
|
|
|
| 18107 |
|
|
YB1_ext_ctl_2_i_m3_0_1 = KE1_q_a[5] & KE1_q_a[4] # YB1_alu_func_2_0_0_a2_0_x[0] # !KE1_q_a[5] & !KE1_q_a[4] & YB1_ext_ctl_2_i_m3_0_a[1];
|
| 18108 |
|
|
|
| 18109 |
|
|
|
| 18110 |
|
|
--WB15L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_1_|lpm_latch:U1|q[0]~56
|
| 18111 |
|
|
--operation mode is normal
|
| 18112 |
|
|
|
| 18113 |
|
|
WB15L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_ext_ctl_2_i_m3_0_1 # !YB1_un1_muxa_ctl370_x & WB15L1;
|
| 18114 |
|
|
|
| 18115 |
|
|
|
| 18116 |
|
|
--YB1_ext_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_0
|
| 18117 |
|
|
--operation mode is normal
|
| 18118 |
|
|
|
| 18119 |
|
|
YB1_ext_ctl_2_0_0_0 = YB1_ext_ctl_2_0_0_o3[2] # WB25L1 & YB1_ext_ctl_2_0_0_a3_1_0[2] # !YB1_ext_ctl_2_0_0_a[2];
|
| 18120 |
|
|
|
| 18121 |
|
|
|
| 18122 |
|
|
--WB25L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_2_|lpm_latch:U1|q[0]~56
|
| 18123 |
|
|
--operation mode is normal
|
| 18124 |
|
|
|
| 18125 |
|
|
WB25L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_ext_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB25L1;
|
| 18126 |
|
|
|
| 18127 |
|
|
|
| 18128 |
|
|
--YB1_ext_ctl_2_i_m3_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_0
|
| 18129 |
|
|
--operation mode is normal
|
| 18130 |
|
|
|
| 18131 |
|
|
YB1_ext_ctl_2_i_m3_0_0 = YB1_alu_func_2_0_0_o3[3] # YB1_ext_ctl_2_i_m3_0_2[0] # !YB1_ext_ctl_2_i_m3_0_a_x[0] & YB1_fsm_dly_2_0_0_a2_x[2];
|
| 18132 |
|
|
|
| 18133 |
|
|
|
| 18134 |
|
|
--WB05L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1|q[0]~68
|
| 18135 |
|
|
--operation mode is normal
|
| 18136 |
|
|
|
| 18137 |
|
|
WB05L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_ext_ctl_2_i_m3_0_0 # !YB1_un1_muxa_ctl370_x & WB05L2;
|
| 18138 |
|
|
|
| 18139 |
|
|
|
| 18140 |
|
|
--WB05L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1|q[0]~69
|
| 18141 |
|
|
--operation mode is normal
|
| 18142 |
|
|
|
| 18143 |
|
|
WB05L2 = WB05L1 & !YB1_un1_ins_i_23_2_0;
|
| 18144 |
|
|
|
| 18145 |
|
|
|
| 18146 |
|
|
--YB1_muxa_ctl_2_0_0_2[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_2[1]
|
| 18147 |
|
|
--operation mode is normal
|
| 18148 |
|
|
|
| 18149 |
|
|
YB1_muxa_ctl_2_0_0_2[1] = YB1_muxa_ctl_2_0_0_0_Z[1] # !KE1_q_a[4] & !KE1_q_a[3] & !YB1_muxa_ctl_2_0_0_2_a[1];
|
| 18150 |
|
|
|
| 18151 |
|
|
|
| 18152 |
|
|
--ED1_r32_o_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_25
|
| 18153 |
|
|
--operation mode is normal
|
| 18154 |
|
|
|
| 18155 |
|
|
ED1_r32_o_25_lut_out = KE1_q_a[1];
|
| 18156 |
|
|
ED1_r32_o_25 = DFFEAS(ED1_r32_o_25_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 18157 |
|
|
|
| 18158 |
|
|
|
| 18159 |
|
|
--AE1_q_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_1
|
| 18160 |
|
|
--operation mode is normal
|
| 18161 |
|
|
|
| 18162 |
|
|
AE1_q_1_lut_out = ED1_r32_o_22;
|
| 18163 |
|
|
AE1_q_1 = DFFEAS(AE1_q_1_lut_out, E1__clk0, VCC, , , , , , );
|
| 18164 |
|
|
|
| 18165 |
|
|
|
| 18166 |
|
|
--AE1_q_0 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_0
|
| 18167 |
|
|
--operation mode is normal
|
| 18168 |
|
|
|
| 18169 |
|
|
AE1_q_0_lut_out = ED1_r32_o_21;
|
| 18170 |
|
|
AE1_q_0 = DFFEAS(AE1_q_0_lut_out, E1__clk0, VCC, , , , , , );
|
| 18171 |
|
|
|
| 18172 |
|
|
|
| 18173 |
|
|
--AE1_q_2 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_2
|
| 18174 |
|
|
--operation mode is normal
|
| 18175 |
|
|
|
| 18176 |
|
|
AE1_q_2_lut_out = ED1_r32_o_23;
|
| 18177 |
|
|
AE1_q_2 = DFFEAS(AE1_q_2_lut_out, E1__clk0, VCC, , , , , , );
|
| 18178 |
|
|
|
| 18179 |
|
|
|
| 18180 |
|
|
--AE1_q_3 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_3
|
| 18181 |
|
|
--operation mode is normal
|
| 18182 |
|
|
|
| 18183 |
|
|
AE1_q_3_lut_out = ED1_r32_o_24;
|
| 18184 |
|
|
AE1_q_3 = DFFEAS(AE1_q_3_lut_out, E1__clk0, VCC, , , , , , );
|
| 18185 |
|
|
|
| 18186 |
|
|
|
| 18187 |
|
|
--FD1_N_18_i_0_s3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_18_i_0_s3
|
| 18188 |
|
|
--operation mode is normal
|
| 18189 |
|
|
|
| 18190 |
|
|
FD1_N_18_i_0_s3 = FD1_N_18_i_0_s3_a & !YD1_mux_fw_1 & FD1_un14_qa_NE # !FD1_r_wren;
|
| 18191 |
|
|
|
| 18192 |
|
|
|
| 18193 |
|
|
--HD1_dout_iv_1_a[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[4]
|
| 18194 |
|
|
--operation mode is normal
|
| 18195 |
|
|
|
| 18196 |
|
|
HD1_dout_iv_1_a[4] = FD1_r_data_4 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_2 # !FD1_r_data_4 & !YD1_mux_fw_1 # !AB1_r32_o_2;
|
| 18197 |
|
|
|
| 18198 |
|
|
|
| 18199 |
|
|
--LD2_q_b[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[4]
|
| 18200 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 18201 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 18202 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 18203 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 18204 |
|
|
LD2_q_b[4]_PORT_A_data_in = FD1_wb_o_4;
|
| 18205 |
|
|
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
|
| 18206 |
|
|
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 18207 |
|
|
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
|
| 18208 |
|
|
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 18209 |
|
|
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
|
| 18210 |
|
|
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 18211 |
|
|
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
|
| 18212 |
|
|
LD2_q_b[4]_PORT_B_read_enable = VCC;
|
| 18213 |
|
|
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
|
| 18214 |
|
|
LD2_q_b[4]_clock_0 = E1__clk0;
|
| 18215 |
|
|
LD2_q_b[4]_clock_1 = E1__clk0;
|
| 18216 |
|
|
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
|
| 18217 |
|
|
LD2_q_b[4] = LD2_q_b[4]_PORT_B_data_out[0];
|
| 18218 |
|
|
|
| 18219 |
|
|
|
| 18220 |
|
|
--YD1_un17_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un17_mux_fw_NE
|
| 18221 |
|
|
--operation mode is normal
|
| 18222 |
|
|
|
| 18223 |
|
|
YD1_un17_mux_fw_NE = YD1_un17_mux_fw_NE_1 # YD1_un17_mux_fw_NE_a # ED1_r32_o_25 $ NB1_r5_o_4;
|
| 18224 |
|
|
|
| 18225 |
|
|
|
| 18226 |
|
|
--YD1_mux_fw_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|mux_fw_1
|
| 18227 |
|
|
--operation mode is normal
|
| 18228 |
|
|
|
| 18229 |
|
|
YD1_mux_fw_1 = XC1_wb_we_o_0 & !WD1_un14_mux_fw & !YD1_un1_mux_fw_NE;
|
| 18230 |
|
|
|
| 18231 |
|
|
|
| 18232 |
|
|
--WD1_un17_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un17_mux_fw_NE_1
|
| 18233 |
|
|
--operation mode is normal
|
| 18234 |
|
|
|
| 18235 |
|
|
WD1_un17_mux_fw_NE_1 = AE1_q_1 & AE1_q_0 $ NB1_r5_o_0 # !NB1_r5_o_1 # !AE1_q_1 & NB1_r5_o_1 # AE1_q_0 $ NB1_r5_o_0;
|
| 18236 |
|
|
|
| 18237 |
|
|
|
| 18238 |
|
|
--WD1_un17_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un17_mux_fw_NE_a
|
| 18239 |
|
|
--operation mode is normal
|
| 18240 |
|
|
|
| 18241 |
|
|
WD1_un17_mux_fw_NE_a = AE1_q_2 & AE1_q_3 $ NB1_r5_o_3 # !NB1_r5_o_2 # !AE1_q_2 & NB1_r5_o_2 # AE1_q_3 $ NB1_r5_o_3;
|
| 18242 |
|
|
|
| 18243 |
|
|
|
| 18244 |
|
|
--QB1_dout_iv_10 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_10
|
| 18245 |
|
|
--operation mode is normal
|
| 18246 |
|
|
|
| 18247 |
|
|
QB1_dout_iv_10 = GD1_dout_iv_1_10 # FD1_wb_o_10 & GD1_dout7_0_a2;
|
| 18248 |
|
|
|
| 18249 |
|
|
--QB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_10
|
| 18250 |
|
|
--operation mode is normal
|
| 18251 |
|
|
|
| 18252 |
|
|
QB1_r32_o_10 = DFFEAS(QB1_dout_iv_10, E1__clk0, VCC, , , , , , );
|
| 18253 |
|
|
|
| 18254 |
|
|
|
| 18255 |
|
|
--QB1_dout_iv_15 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_15
|
| 18256 |
|
|
--operation mode is normal
|
| 18257 |
|
|
|
| 18258 |
|
|
QB1_dout_iv_15 = GD1_dout_iv_1_15 # FD1_wb_o_15 & GD1_dout7_0_a2;
|
| 18259 |
|
|
|
| 18260 |
|
|
--QB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_15
|
| 18261 |
|
|
--operation mode is normal
|
| 18262 |
|
|
|
| 18263 |
|
|
QB1_r32_o_15 = DFFEAS(QB1_dout_iv_15, E1__clk0, VCC, , , , , , );
|
| 18264 |
|
|
|
| 18265 |
|
|
|
| 18266 |
|
|
--FB1_res_7_0_0_15 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_15
|
| 18267 |
|
|
--operation mode is normal
|
| 18268 |
|
|
|
| 18269 |
|
|
FB1_res_7_0_0_15 = ED1_r32_o_13 & CD1_res_7_0_0_o3_0 # ED1_r32_o_15 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_13 & ED1_r32_o_15 & CD1_res_7_0_0_a2_0;
|
| 18270 |
|
|
|
| 18271 |
|
|
--FB1_r32_o_0_15 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_15
|
| 18272 |
|
|
--operation mode is normal
|
| 18273 |
|
|
|
| 18274 |
|
|
FB1_r32_o_0_15 = DFFEAS(FB1_res_7_0_0_15, E1__clk0, VCC, , , , , , );
|
| 18275 |
|
|
|
| 18276 |
|
|
|
| 18277 |
|
|
--FD1_wb_o_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_15
|
| 18278 |
|
|
--operation mode is normal
|
| 18279 |
|
|
|
| 18280 |
|
|
FD1_wb_o_15 = TC1_wb_mux_ctl_o_0 & F1_dout_15 # DB1_r32_o_15 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_15;
|
| 18281 |
|
|
|
| 18282 |
|
|
--FD1_r_data_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_15
|
| 18283 |
|
|
--operation mode is normal
|
| 18284 |
|
|
|
| 18285 |
|
|
FD1_r_data_15 = DFFEAS(FD1_wb_o_15, E1__clk0, VCC, , , , , , );
|
| 18286 |
|
|
|
| 18287 |
|
|
|
| 18288 |
|
|
--QB1_dout_iv_27 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_27
|
| 18289 |
|
|
--operation mode is normal
|
| 18290 |
|
|
|
| 18291 |
|
|
QB1_dout_iv_27 = GD1_dout_iv_1_27 # FD1_wb_o_27 & GD1_dout7_0_a2;
|
| 18292 |
|
|
|
| 18293 |
|
|
--QB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_27
|
| 18294 |
|
|
--operation mode is normal
|
| 18295 |
|
|
|
| 18296 |
|
|
QB1_r32_o_27 = DFFEAS(QB1_dout_iv_27, E1__clk0, VCC, , , , , , );
|
| 18297 |
|
|
|
| 18298 |
|
|
|
| 18299 |
|
|
--FB1_res_7_0_0_27 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_27
|
| 18300 |
|
|
--operation mode is normal
|
| 18301 |
|
|
|
| 18302 |
|
|
FB1_res_7_0_0_27 = CD1_res_7_0_0_a3_0 # ED1_r32_o_11 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_24;
|
| 18303 |
|
|
|
| 18304 |
|
|
--FB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_27
|
| 18305 |
|
|
--operation mode is normal
|
| 18306 |
|
|
|
| 18307 |
|
|
FB1_r32_o_27 = DFFEAS(FB1_res_7_0_0_27, E1__clk0, VCC, , , , , , );
|
| 18308 |
|
|
|
| 18309 |
|
|
|
| 18310 |
|
|
--FD1_wb_o_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_27
|
| 18311 |
|
|
--operation mode is normal
|
| 18312 |
|
|
|
| 18313 |
|
|
FD1_wb_o_27 = TC1_wb_mux_ctl_o_0 & F1_dout_27 # DB1_r32_o_27 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_27;
|
| 18314 |
|
|
|
| 18315 |
|
|
--FD1_r_data_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_27
|
| 18316 |
|
|
--operation mode is normal
|
| 18317 |
|
|
|
| 18318 |
|
|
FD1_r_data_27 = DFFEAS(FD1_wb_o_27, E1__clk0, VCC, , , , , , );
|
| 18319 |
|
|
|
| 18320 |
|
|
|
| 18321 |
|
|
--QB1_dout_iv_19 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_19
|
| 18322 |
|
|
--operation mode is normal
|
| 18323 |
|
|
|
| 18324 |
|
|
QB1_dout_iv_19 = GD1_dout_iv_1_19 # FD1_wb_o_19 & GD1_dout7_0_a2;
|
| 18325 |
|
|
|
| 18326 |
|
|
--QB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_19
|
| 18327 |
|
|
--operation mode is normal
|
| 18328 |
|
|
|
| 18329 |
|
|
QB1_r32_o_19 = DFFEAS(QB1_dout_iv_19, E1__clk0, VCC, , , , , , );
|
| 18330 |
|
|
|
| 18331 |
|
|
|
| 18332 |
|
|
--FB1_res_7_0_0_19 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_19
|
| 18333 |
|
|
--operation mode is normal
|
| 18334 |
|
|
|
| 18335 |
|
|
FB1_res_7_0_0_19 = CD1_res_7_0_0_a3_0 # ED1_r32_o_3 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_16;
|
| 18336 |
|
|
|
| 18337 |
|
|
--FB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_19
|
| 18338 |
|
|
--operation mode is normal
|
| 18339 |
|
|
|
| 18340 |
|
|
FB1_r32_o_19 = DFFEAS(FB1_res_7_0_0_19, E1__clk0, VCC, , , , , , );
|
| 18341 |
|
|
|
| 18342 |
|
|
|
| 18343 |
|
|
--FB1_res_7_0_0_20 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_20
|
| 18344 |
|
|
--operation mode is normal
|
| 18345 |
|
|
|
| 18346 |
|
|
FB1_res_7_0_0_20 = CD1_res_7_0_0_a3_0 # ED1_r32_o_4 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_17;
|
| 18347 |
|
|
|
| 18348 |
|
|
--FB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_20
|
| 18349 |
|
|
--operation mode is normal
|
| 18350 |
|
|
|
| 18351 |
|
|
FB1_r32_o_20 = DFFEAS(FB1_res_7_0_0_20, E1__clk0, VCC, , , , , , );
|
| 18352 |
|
|
|
| 18353 |
|
|
|
| 18354 |
|
|
--VD1_count[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[3]
|
| 18355 |
|
|
--operation mode is arithmetic
|
| 18356 |
|
|
|
| 18357 |
|
|
VD1_count[3]_carry_eqn = VD1_count_cout[2];
|
| 18358 |
|
|
VD1_count[3]_lut_out = VD1_count[3] $ (VD1_count[3]_carry_eqn);
|
| 18359 |
|
|
VD1_count[3] = DFFEAS(VD1_count[3]_lut_out, E1__clk0, VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
|
| 18360 |
|
|
|
| 18361 |
|
|
--VD1_count_cout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[3]
|
| 18362 |
|
|
--operation mode is arithmetic
|
| 18363 |
|
|
|
| 18364 |
|
|
VD1_count_cout[3] = CARRY(!VD1_count_cout[2] # !VD1_count[3]);
|
| 18365 |
|
|
|
| 18366 |
|
|
|
| 18367 |
|
|
--VD1_un3_overflow_m_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un3_overflow_m_0
|
| 18368 |
|
|
--operation mode is normal
|
| 18369 |
|
|
|
| 18370 |
|
|
VD1_un3_overflow_m_0 = RC1_alu_func_o_3 & RC1_alu_func_o_1 & RC1_alu_func_o_0 & !VD1_un29_sign_0_o2_0;
|
| 18371 |
|
|
|
| 18372 |
|
|
|
| 18373 |
|
|
--VD1_over_add31_cout is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_add31_cout
|
| 18374 |
|
|
--operation mode is arithmetic
|
| 18375 |
|
|
|
| 18376 |
|
|
VD1_over_add31_cout = CARRY(VD1_b_o_iv_31 & !VD1_over_carry_30 # !PD1_a_o_31 # !VD1_b_o_iv_31 & !PD1_a_o_31 & !VD1_over_carry_30);
|
| 18377 |
|
|
|
| 18378 |
|
|
|
| 18379 |
|
|
--VD1_un1_overflow_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_overflow_1
|
| 18380 |
|
|
--operation mode is normal
|
| 18381 |
|
|
|
| 18382 |
|
|
VD1_un1_overflow_1 = VD1_overflow # VD1_count[5] & VD1_finish;
|
| 18383 |
|
|
|
| 18384 |
|
|
|
| 18385 |
|
|
--VD1_op1_sign_reged is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op1_sign_reged
|
| 18386 |
|
|
--operation mode is normal
|
| 18387 |
|
|
|
| 18388 |
|
|
VD1_op1_sign_reged_lut_out = RC1_alu_func_o_0 & PD1_a_o_31;
|
| 18389 |
|
|
VD1_op1_sign_reged = DFFEAS(VD1_op1_sign_reged_lut_out, E1__clk0, VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
|
| 18390 |
|
|
|
| 18391 |
|
|
|
| 18392 |
|
|
--VD1_eqz_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2
|
| 18393 |
|
|
--operation mode is normal
|
| 18394 |
|
|
|
| 18395 |
|
|
VD1_eqz_2 = VD1_eqz_2_17 & VD1_eqz_2_21 & VD1_eqz_2_27 & VD1_eqz_2_30;
|
| 18396 |
|
|
|
| 18397 |
|
|
|
| 18398 |
|
|
--VD1_eqop2_2_NE is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE
|
| 18399 |
|
|
--operation mode is normal
|
| 18400 |
|
|
|
| 18401 |
|
|
VD1_eqop2_2_NE = VD1_eqop2_2_NE_11 # VD1_eqop2_2_NE_9 # VD1_eqop2_2_NE_10 # VD1_eqop2_2_NE_12;
|
| 18402 |
|
|
|
| 18403 |
|
|
|
| 18404 |
|
|
--VD1_eqnop2_2_NE_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_7
|
| 18405 |
|
|
--operation mode is normal
|
| 18406 |
|
|
|
| 18407 |
|
|
VD1_eqnop2_2_NE_7 = VD1_eqnop2_2_NE_7_a # VD1_eqnop2_2_NE_143 # VD1_hilo[64] $ VD1_nop2_reged[32];
|
| 18408 |
|
|
|
| 18409 |
|
|
|
| 18410 |
|
|
--VD1_eqnop2_2_NE_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_9
|
| 18411 |
|
|
--operation mode is normal
|
| 18412 |
|
|
|
| 18413 |
|
|
VD1_eqnop2_2_NE_9 = VD1_eqnop2_2_NE_129 # VD1_eqnop2_2_NE_131 # VD1_eqnop2_2_NE_130 # VD1_eqnop2_2_NE_132_0;
|
| 18414 |
|
|
|
| 18415 |
|
|
|
| 18416 |
|
|
--VD1_eqnop2_2_NE_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_10
|
| 18417 |
|
|
--operation mode is normal
|
| 18418 |
|
|
|
| 18419 |
|
|
VD1_eqnop2_2_NE_10 = VD1_eqnop2_2_NE_133 # VD1_eqnop2_2_NE_134 # VD1_eqnop2_2_NE_135 # VD1_eqnop2_2_NE_10_a;
|
| 18420 |
|
|
|
| 18421 |
|
|
|
| 18422 |
|
|
--VD1_eqnop2_2_NE_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_a
|
| 18423 |
|
|
--operation mode is normal
|
| 18424 |
|
|
|
| 18425 |
|
|
VD1_eqnop2_2_NE_a = !VD1_eqnop2_2_NE_141 & !VD1_eqnop2_2_NE_142 & !VD1_eqnop2_2_NE_5 & !VD1_eqnop2_2_NE_8;
|
| 18426 |
|
|
|
| 18427 |
|
|
|
| 18428 |
|
|
--VD1_hilo_33_i_m[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[64]
|
| 18429 |
|
|
--operation mode is normal
|
| 18430 |
|
|
|
| 18431 |
|
|
VD1_hilo_33_i_m[64] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[64] # !VD1_hilo_33_1[64] & !VD1_hilo[64];
|
| 18432 |
|
|
|
| 18433 |
|
|
|
| 18434 |
|
|
--VD1_hilo_37_iv_a[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[64]
|
| 18435 |
|
|
--operation mode is normal
|
| 18436 |
|
|
|
| 18437 |
|
|
VD1_hilo_37_iv_a[64] = VD1_sign & !VD1_hilo_15_3_i[63] # !VD1_hilo_1_sqmuxa_1;
|
| 18438 |
|
|
|
| 18439 |
|
|
|
| 18440 |
|
|
--VD1_hilo_37_iv_1[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1[64]
|
| 18441 |
|
|
--operation mode is normal
|
| 18442 |
|
|
|
| 18443 |
|
|
VD1_hilo_37_iv_1[64] = VD1_hilo_2_sqmuxa & !VD1_hilo_24_add32 # !VD1_hilo_37_iv_1_a[64];
|
| 18444 |
|
|
|
| 18445 |
|
|
|
| 18446 |
|
|
--VD1_un1_addnop2104_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_addnop2104_1
|
| 18447 |
|
|
--operation mode is normal
|
| 18448 |
|
|
|
| 18449 |
|
|
VD1_un1_addnop2104_1 = VD1_count[5] # VD1_overflow # VD1_mul & !VD1_sign;
|
| 18450 |
|
|
|
| 18451 |
|
|
|
| 18452 |
|
|
--VD1_nop2_reged[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[2]
|
| 18453 |
|
|
--operation mode is arithmetic
|
| 18454 |
|
|
|
| 18455 |
|
|
VD1_nop2_reged[2]_carry_eqn = VD1_nop2_reged_cout[0];
|
| 18456 |
|
|
VD1_nop2_reged[2] = VD1_op2_reged[2] $ !VD1_nop2_reged[2]_carry_eqn;
|
| 18457 |
|
|
|
| 18458 |
|
|
--VD1_nop2_reged_cout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[2]
|
| 18459 |
|
|
--operation mode is arithmetic
|
| 18460 |
|
|
|
| 18461 |
|
|
VD1_nop2_reged_cout[2] = CARRY(VD1_op2_reged[3] # VD1_op2_reged[2] # !VD1_nop2_reged_cout[0]);
|
| 18462 |
|
|
|
| 18463 |
|
|
|
| 18464 |
|
|
--VD1_un1_mul_3_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_mul_3_a
|
| 18465 |
|
|
--operation mode is normal
|
| 18466 |
|
|
|
| 18467 |
|
|
VD1_un1_mul_3_a = VD1_op1_sign_reged & !VD1_op2_sign_reged & !VD1_hilo[64] & !VD1_eqz_2 # !VD1_op1_sign_reged & VD1_op2_sign_reged & VD1_hilo[64];
|
| 18468 |
|
|
|
| 18469 |
|
|
|
| 18470 |
|
|
--VD1_un1_op2_reged_1_combout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[4]
|
| 18471 |
|
|
--operation mode is normal
|
| 18472 |
|
|
|
| 18473 |
|
|
VD1_un1_op2_reged_1_combout[4] = VD1_eqop2_2_32 & VD1_op2_reged[4] # !VD1_eqop2_2_32 & VD1_nop2_reged[4];
|
| 18474 |
|
|
|
| 18475 |
|
|
|
| 18476 |
|
|
--VD1_hilo_24_add3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add3
|
| 18477 |
|
|
--operation mode is arithmetic
|
| 18478 |
|
|
|
| 18479 |
|
|
VD1_hilo_24_add3_carry_eqn = VD1_hilo_24_carry_2;
|
| 18480 |
|
|
VD1_hilo_24_add3 = VD1_hilo_34 $ VD1_un1_op2_reged_1_combout[3] $ VD1_hilo_24_add3_carry_eqn;
|
| 18481 |
|
|
|
| 18482 |
|
|
--VD1_hilo_24_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_3
|
| 18483 |
|
|
--operation mode is arithmetic
|
| 18484 |
|
|
|
| 18485 |
|
|
VD1_hilo_24_carry_3 = CARRY(VD1_hilo_34 & !VD1_un1_op2_reged_1_combout[3] & !VD1_hilo_24_carry_2 # !VD1_hilo_34 & !VD1_hilo_24_carry_2 # !VD1_un1_op2_reged_1_combout[3]);
|
| 18486 |
|
|
|
| 18487 |
|
|
|
| 18488 |
|
|
--VD1_hilo_37_iv_0_3_a[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3_a[38]
|
| 18489 |
|
|
--operation mode is normal
|
| 18490 |
|
|
|
| 18491 |
|
|
VD1_hilo_37_iv_0_3_a[38] = !VD1_hilo_37_iv_0_a3_2[38] & !VD1_hilo_37_iv_0_a3_6[38] & VD1_un50_hilo_add6 # !VD1_hilo_37_iv_0_a2_6_0[37];
|
| 18492 |
|
|
|
| 18493 |
|
|
|
| 18494 |
|
|
--HD1_dout_iv_1_a[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[5]
|
| 18495 |
|
|
--operation mode is normal
|
| 18496 |
|
|
|
| 18497 |
|
|
HD1_dout_iv_1_a[5] = FD1_r_data_5 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_3 # !FD1_r_data_5 & !YD1_mux_fw_1 # !AB1_r32_o_3;
|
| 18498 |
|
|
|
| 18499 |
|
|
|
| 18500 |
|
|
--LD2_q_b[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[5]
|
| 18501 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 18502 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 18503 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 18504 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 18505 |
|
|
LD2_q_b[5]_PORT_A_data_in = FD1_wb_o_5;
|
| 18506 |
|
|
LD2_q_b[5]_PORT_A_data_in_reg = DFFE(LD2_q_b[5]_PORT_A_data_in, LD2_q_b[5]_clock_0, , , );
|
| 18507 |
|
|
LD2_q_b[5]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 18508 |
|
|
LD2_q_b[5]_PORT_A_address_reg = DFFE(LD2_q_b[5]_PORT_A_address, LD2_q_b[5]_clock_0, , , );
|
| 18509 |
|
|
LD2_q_b[5]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 18510 |
|
|
LD2_q_b[5]_PORT_B_address_reg = DFFE(LD2_q_b[5]_PORT_B_address, LD2_q_b[5]_clock_1, , , );
|
| 18511 |
|
|
LD2_q_b[5]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 18512 |
|
|
LD2_q_b[5]_PORT_A_write_enable_reg = DFFE(LD2_q_b[5]_PORT_A_write_enable, LD2_q_b[5]_clock_0, , , );
|
| 18513 |
|
|
LD2_q_b[5]_PORT_B_read_enable = VCC;
|
| 18514 |
|
|
LD2_q_b[5]_PORT_B_read_enable_reg = DFFE(LD2_q_b[5]_PORT_B_read_enable, LD2_q_b[5]_clock_1, , , );
|
| 18515 |
|
|
LD2_q_b[5]_clock_0 = E1__clk0;
|
| 18516 |
|
|
LD2_q_b[5]_clock_1 = E1__clk0;
|
| 18517 |
|
|
LD2_q_b[5]_PORT_B_data_out = MEMORY(LD2_q_b[5]_PORT_A_data_in_reg, , LD2_q_b[5]_PORT_A_address_reg, LD2_q_b[5]_PORT_B_address_reg, LD2_q_b[5]_PORT_A_write_enable_reg, LD2_q_b[5]_PORT_B_read_enable_reg, , , LD2_q_b[5]_clock_0, LD2_q_b[5]_clock_1, , , , );
|
| 18518 |
|
|
LD2_q_b[5] = LD2_q_b[5]_PORT_B_data_out[0];
|
| 18519 |
|
|
|
| 18520 |
|
|
|
| 18521 |
|
|
--QB1_dout_iv_16 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_16
|
| 18522 |
|
|
--operation mode is normal
|
| 18523 |
|
|
|
| 18524 |
|
|
QB1_dout_iv_16 = GD1_dout_iv_1_16 # FD1_wb_o_16 & GD1_dout7_0_a2;
|
| 18525 |
|
|
|
| 18526 |
|
|
--QB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_16
|
| 18527 |
|
|
--operation mode is normal
|
| 18528 |
|
|
|
| 18529 |
|
|
QB1_r32_o_16 = DFFEAS(QB1_dout_iv_16, E1__clk0, VCC, , , , , , );
|
| 18530 |
|
|
|
| 18531 |
|
|
|
| 18532 |
|
|
--FB1_res_7_0_0_16 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_16
|
| 18533 |
|
|
--operation mode is normal
|
| 18534 |
|
|
|
| 18535 |
|
|
FB1_res_7_0_0_16 = CD1_res_7_0_0_0_14 # ED1_r32_o_14 & CD1_res_7_0_0_o3_0;
|
| 18536 |
|
|
|
| 18537 |
|
|
--FB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_16
|
| 18538 |
|
|
--operation mode is normal
|
| 18539 |
|
|
|
| 18540 |
|
|
FB1_r32_o_16 = DFFEAS(FB1_res_7_0_0_16, E1__clk0, VCC, , , , , , );
|
| 18541 |
|
|
|
| 18542 |
|
|
|
| 18543 |
|
|
--CD1_res_7_0_0_a2_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a2_16
|
| 18544 |
|
|
--operation mode is normal
|
| 18545 |
|
|
|
| 18546 |
|
|
CD1_res_7_0_0_a2_16 = DC1_ext_ctl_o_1 & DC1_ext_ctl_o_2 & !DC1_ext_ctl_o_0;
|
| 18547 |
|
|
|
| 18548 |
|
|
|
| 18549 |
|
|
--CD1_res_7_0_0_a3_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a3_0
|
| 18550 |
|
|
--operation mode is normal
|
| 18551 |
|
|
|
| 18552 |
|
|
CD1_res_7_0_0_a3_0 = !DC1_ext_ctl_o_1 & ED1_r32_o_15 & DC1_ext_ctl_o_2 $ DC1_ext_ctl_o_0;
|
| 18553 |
|
|
|
| 18554 |
|
|
|
| 18555 |
|
|
--QB1_dout_iv_28 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_28
|
| 18556 |
|
|
--operation mode is normal
|
| 18557 |
|
|
|
| 18558 |
|
|
QB1_dout_iv_28 = GD1_dout_iv_1_28 # FD1_wb_o_28 & GD1_dout7_0_a2;
|
| 18559 |
|
|
|
| 18560 |
|
|
--QB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_28
|
| 18561 |
|
|
--operation mode is normal
|
| 18562 |
|
|
|
| 18563 |
|
|
QB1_r32_o_28 = DFFEAS(QB1_dout_iv_28, E1__clk0, VCC, , , , , , );
|
| 18564 |
|
|
|
| 18565 |
|
|
|
| 18566 |
|
|
--QB1_dout_iv_23 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_23
|
| 18567 |
|
|
--operation mode is normal
|
| 18568 |
|
|
|
| 18569 |
|
|
QB1_dout_iv_23 = GD1_dout_iv_1_23 # FD1_wb_o_23 & GD1_dout7_0_a2;
|
| 18570 |
|
|
|
| 18571 |
|
|
--QB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_23
|
| 18572 |
|
|
--operation mode is normal
|
| 18573 |
|
|
|
| 18574 |
|
|
QB1_r32_o_23 = DFFEAS(QB1_dout_iv_23, E1__clk0, VCC, , , , , , );
|
| 18575 |
|
|
|
| 18576 |
|
|
|
| 18577 |
|
|
--FB1_res_7_0_0_23 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_23
|
| 18578 |
|
|
--operation mode is normal
|
| 18579 |
|
|
|
| 18580 |
|
|
FB1_res_7_0_0_23 = CD1_res_7_0_0_a3_0 # ED1_r32_o_7 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_20;
|
| 18581 |
|
|
|
| 18582 |
|
|
--FB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_23
|
| 18583 |
|
|
--operation mode is normal
|
| 18584 |
|
|
|
| 18585 |
|
|
FB1_r32_o_23 = DFFEAS(FB1_res_7_0_0_23, E1__clk0, VCC, , , , , , );
|
| 18586 |
|
|
|
| 18587 |
|
|
|
| 18588 |
|
|
--QB1_dout_iv_24 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_24
|
| 18589 |
|
|
--operation mode is normal
|
| 18590 |
|
|
|
| 18591 |
|
|
QB1_dout_iv_24 = GD1_dout_iv_1_24 # FD1_wb_o_24 & GD1_dout7_0_a2;
|
| 18592 |
|
|
|
| 18593 |
|
|
--QB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_24
|
| 18594 |
|
|
--operation mode is normal
|
| 18595 |
|
|
|
| 18596 |
|
|
QB1_r32_o_24 = DFFEAS(QB1_dout_iv_24, E1__clk0, VCC, , , , , , );
|
| 18597 |
|
|
|
| 18598 |
|
|
|
| 18599 |
|
|
--FB1_res_7_0_0_24 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_24
|
| 18600 |
|
|
--operation mode is normal
|
| 18601 |
|
|
|
| 18602 |
|
|
FB1_res_7_0_0_24 = CD1_res_7_0_0_a3_0 # ED1_r32_o_8 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_21;
|
| 18603 |
|
|
|
| 18604 |
|
|
--FB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_24
|
| 18605 |
|
|
--operation mode is normal
|
| 18606 |
|
|
|
| 18607 |
|
|
FB1_r32_o_24 = DFFEAS(FB1_res_7_0_0_24, E1__clk0, VCC, , , , , , );
|
| 18608 |
|
|
|
| 18609 |
|
|
|
| 18610 |
|
|
--FD1_wb_o_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_24
|
| 18611 |
|
|
--operation mode is normal
|
| 18612 |
|
|
|
| 18613 |
|
|
FD1_wb_o_24 = TC1_wb_mux_ctl_o_0 & F1_dout_24 # DB1_r32_o_24 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_24;
|
| 18614 |
|
|
|
| 18615 |
|
|
--FD1_r_data_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_24
|
| 18616 |
|
|
--operation mode is normal
|
| 18617 |
|
|
|
| 18618 |
|
|
FD1_r_data_24 = DFFEAS(FD1_wb_o_24, E1__clk0, VCC, , , , , , );
|
| 18619 |
|
|
|
| 18620 |
|
|
|
| 18621 |
|
|
--VD1_nop2_reged[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[1]
|
| 18622 |
|
|
--operation mode is arithmetic
|
| 18623 |
|
|
|
| 18624 |
|
|
VD1_nop2_reged[1] = VD1_op2_reged[1] $ VD1_op2_reged[0];
|
| 18625 |
|
|
|
| 18626 |
|
|
--VD1_nop2_reged_cout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[1]
|
| 18627 |
|
|
--operation mode is arithmetic
|
| 18628 |
|
|
|
| 18629 |
|
|
VD1_nop2_reged_cout[1] = CARRY(!VD1_op2_reged[1] & !VD1_op2_reged[0]);
|
| 18630 |
|
|
|
| 18631 |
|
|
|
| 18632 |
|
|
--VD1_un50_hilo_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add1
|
| 18633 |
|
|
--operation mode is arithmetic
|
| 18634 |
|
|
|
| 18635 |
|
|
VD1_un50_hilo_add1_carry_eqn = VD1_un50_hilo_carry_0;
|
| 18636 |
|
|
VD1_un50_hilo_add1 = VD1_hilo_33 $ VD1_nop2_reged[1] $ VD1_un50_hilo_add1_carry_eqn;
|
| 18637 |
|
|
|
| 18638 |
|
|
--VD1_un50_hilo_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_1
|
| 18639 |
|
|
--operation mode is arithmetic
|
| 18640 |
|
|
|
| 18641 |
|
|
VD1_un50_hilo_carry_1 = CARRY(VD1_hilo_33 & !VD1_nop2_reged[1] & !VD1_un50_hilo_carry_0 # !VD1_hilo_33 & !VD1_un50_hilo_carry_0 # !VD1_nop2_reged[1]);
|
| 18642 |
|
|
|
| 18643 |
|
|
|
| 18644 |
|
|
--VD1_un1_op2_reged_1_combout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[1]
|
| 18645 |
|
|
--operation mode is normal
|
| 18646 |
|
|
|
| 18647 |
|
|
VD1_un1_op2_reged_1_combout[1] = VD1_eqop2_2_32 & VD1_op2_reged[1] # !VD1_eqop2_2_32 & VD1_nop2_reged[1];
|
| 18648 |
|
|
|
| 18649 |
|
|
|
| 18650 |
|
|
--VD1_un59_hilo_add2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add2
|
| 18651 |
|
|
--operation mode is arithmetic
|
| 18652 |
|
|
|
| 18653 |
|
|
VD1_un59_hilo_add2_carry_eqn = VD1_un59_hilo_carry_1;
|
| 18654 |
|
|
VD1_un59_hilo_add2 = VD1_hilo_34 $ VD1_op2_reged[2] $ !VD1_un59_hilo_add2_carry_eqn;
|
| 18655 |
|
|
|
| 18656 |
|
|
--VD1_un59_hilo_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_2
|
| 18657 |
|
|
--operation mode is arithmetic
|
| 18658 |
|
|
|
| 18659 |
|
|
VD1_un59_hilo_carry_2 = CARRY(VD1_hilo_34 & VD1_op2_reged[2] # !VD1_un59_hilo_carry_1 # !VD1_hilo_34 & VD1_op2_reged[2] & !VD1_un59_hilo_carry_1);
|
| 18660 |
|
|
|
| 18661 |
|
|
|
| 18662 |
|
|
--VD1_hilo_33_i_m_a[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[35]
|
| 18663 |
|
|
--operation mode is normal
|
| 18664 |
|
|
|
| 18665 |
|
|
VD1_hilo_33_i_m_a[35] = VD1_addnop2 & !VD1_un50_hilo_add3 # !VD1_addnop2 & !VD1_un59_hilo_add3;
|
| 18666 |
|
|
|
| 18667 |
|
|
|
| 18668 |
|
|
--VD1_hilo_22_a[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[35]
|
| 18669 |
|
|
--operation mode is normal
|
| 18670 |
|
|
|
| 18671 |
|
|
VD1_hilo_22_a[35] = VD1_sign & !VD1_hilo_36 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add4 # !VD1_hilo[0] & !VD1_hilo_36;
|
| 18672 |
|
|
|
| 18673 |
|
|
|
| 18674 |
|
|
--VD1_hilo_15_2[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[35]
|
| 18675 |
|
|
--operation mode is normal
|
| 18676 |
|
|
|
| 18677 |
|
|
VD1_hilo_15_2[35] = VD1_sub_or_yn & VD1_un59_hilo_add4 # !VD1_sub_or_yn & VD1_un50_hilo_add4;
|
| 18678 |
|
|
|
| 18679 |
|
|
|
| 18680 |
|
|
--UD1_shift_out_80_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[16]
|
| 18681 |
|
|
--operation mode is normal
|
| 18682 |
|
|
|
| 18683 |
|
|
UD1_shift_out_80_a[16] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_19 # !PD1_a_o_1 & !VD1_b_o_iv_17;
|
| 18684 |
|
|
|
| 18685 |
|
|
|
| 18686 |
|
|
--UD1_shift_out_52_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52_a[28]
|
| 18687 |
|
|
--operation mode is normal
|
| 18688 |
|
|
|
| 18689 |
|
|
UD1_shift_out_52_a[28] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_9 # !PD1_a_o_0 & !VD1_b_o_iv_10 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 18690 |
|
|
|
| 18691 |
|
|
|
| 18692 |
|
|
--UD1_shift_out_77_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[16]
|
| 18693 |
|
|
--operation mode is normal
|
| 18694 |
|
|
|
| 18695 |
|
|
UD1_shift_out_77_a[16] = PD1_a_o_0 & !VD1_b_o_iv_7 # !PD1_a_o_0 & !VD1_b_o_iv_8;
|
| 18696 |
|
|
|
| 18697 |
|
|
|
| 18698 |
|
|
--VD1_un134_hilo_combout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[16]
|
| 18699 |
|
|
--operation mode is arithmetic
|
| 18700 |
|
|
|
| 18701 |
|
|
VD1_un134_hilo_combout[16]_carry_eqn = VD1_un134_hilo_cout[14];
|
| 18702 |
|
|
VD1_un134_hilo_combout[16] = VD1_hilo_16 $ (!VD1_un134_hilo_combout[16]_carry_eqn);
|
| 18703 |
|
|
|
| 18704 |
|
|
--VD1_un134_hilo_cout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[16]
|
| 18705 |
|
|
--operation mode is arithmetic
|
| 18706 |
|
|
|
| 18707 |
|
|
VD1_un134_hilo_cout[16] = CARRY(VD1_hilo_16 & VD1_hilo_17 & !VD1_un134_hilo_cout[14]);
|
| 18708 |
|
|
|
| 18709 |
|
|
|
| 18710 |
|
|
--VD1_hilo_33_i_m[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[48]
|
| 18711 |
|
|
--operation mode is normal
|
| 18712 |
|
|
|
| 18713 |
|
|
VD1_hilo_33_i_m[48] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[48] # !VD1_hilo_33_1[64] & !VD1_hilo_48;
|
| 18714 |
|
|
|
| 18715 |
|
|
|
| 18716 |
|
|
--VD1_hilo_37_iv_2_a[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[48]
|
| 18717 |
|
|
--operation mode is normal
|
| 18718 |
|
|
|
| 18719 |
|
|
VD1_hilo_37_iv_2_a[48] = VD1_hilo_16 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add16 # !VD1_hilo_16 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add16;
|
| 18720 |
|
|
|
| 18721 |
|
|
|
| 18722 |
|
|
--VD1_hilo_22_Z[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[48]
|
| 18723 |
|
|
--operation mode is normal
|
| 18724 |
|
|
|
| 18725 |
|
|
VD1_hilo_22_Z[48] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[48] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[48] # !VD1_sign & !VD1_hilo_22_a[48];
|
| 18726 |
|
|
|
| 18727 |
|
|
|
| 18728 |
|
|
--RD1_r32_o_0_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_16
|
| 18729 |
|
|
--operation mode is arithmetic
|
| 18730 |
|
|
|
| 18731 |
|
|
RD1_r32_o_0_16_carry_eqn = RD1_r32_o_cout[14];
|
| 18732 |
|
|
RD1_r32_o_0_16_lut_out = KB1_r32_o_16 $ (RD1_r32_o_0_16_carry_eqn);
|
| 18733 |
|
|
RD1_r32_o_0_16 = DFFEAS(RD1_r32_o_0_16_lut_out, E1__clk0, VCC, , , , , , );
|
| 18734 |
|
|
|
| 18735 |
|
|
--RD1_r32_o_cout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[16]
|
| 18736 |
|
|
--operation mode is arithmetic
|
| 18737 |
|
|
|
| 18738 |
|
|
RD1_r32_o_cout[16] = CARRY(!RD1_r32_o_cout[14] # !KB1_r32_o_17 # !KB1_r32_o_16);
|
| 18739 |
|
|
|
| 18740 |
|
|
|
| 18741 |
|
|
--SD1_r32_o_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_16
|
| 18742 |
|
|
--operation mode is normal
|
| 18743 |
|
|
|
| 18744 |
|
|
SD1_r32_o_16_lut_out = KB1_r32_o_16;
|
| 18745 |
|
|
SD1_r32_o_16 = DFFEAS(SD1_r32_o_16_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 18746 |
|
|
|
| 18747 |
|
|
|
| 18748 |
|
|
--PD1_a_o_3_d[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[16]
|
| 18749 |
|
|
--operation mode is normal
|
| 18750 |
|
|
|
| 18751 |
|
|
PD1_a_o_3_d[16] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_16 # !PD1_un6_a_o & !PD1_a_o_3_d_a[16] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[16];
|
| 18752 |
|
|
|
| 18753 |
|
|
|
| 18754 |
|
|
--UD1_shift_out_80_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[17]
|
| 18755 |
|
|
--operation mode is normal
|
| 18756 |
|
|
|
| 18757 |
|
|
UD1_shift_out_80_a[17] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_20 # !PD1_a_o_1 & !VD1_b_o_iv_18;
|
| 18758 |
|
|
|
| 18759 |
|
|
|
| 18760 |
|
|
--UD1_shift_out_52_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52_a[29]
|
| 18761 |
|
|
--operation mode is normal
|
| 18762 |
|
|
|
| 18763 |
|
|
UD1_shift_out_52_a[29] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_10 # !PD1_a_o_0 & !VD1_b_o_iv_11 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 18764 |
|
|
|
| 18765 |
|
|
|
| 18766 |
|
|
--VD1_un134_hilo_combout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[17]
|
| 18767 |
|
|
--operation mode is arithmetic
|
| 18768 |
|
|
|
| 18769 |
|
|
VD1_un134_hilo_combout[17]_carry_eqn = VD1_un134_hilo_cout[15];
|
| 18770 |
|
|
VD1_un134_hilo_combout[17] = VD1_hilo_17 $ (VD1_hilo_16 & !VD1_un134_hilo_combout[17]_carry_eqn);
|
| 18771 |
|
|
|
| 18772 |
|
|
--VD1_un134_hilo_cout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[17]
|
| 18773 |
|
|
--operation mode is arithmetic
|
| 18774 |
|
|
|
| 18775 |
|
|
VD1_un134_hilo_cout[17] = CARRY(VD1_hilo_16 & VD1_hilo_17 & !VD1_un134_hilo_cout[15]);
|
| 18776 |
|
|
|
| 18777 |
|
|
|
| 18778 |
|
|
--VD1_hilo_33_i_m[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[49]
|
| 18779 |
|
|
--operation mode is normal
|
| 18780 |
|
|
|
| 18781 |
|
|
VD1_hilo_33_i_m[49] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[49] # !VD1_hilo_33_1[64] & !VD1_hilo_49;
|
| 18782 |
|
|
|
| 18783 |
|
|
|
| 18784 |
|
|
--VD1_hilo_37_iv_2_a[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[49]
|
| 18785 |
|
|
--operation mode is normal
|
| 18786 |
|
|
|
| 18787 |
|
|
VD1_hilo_37_iv_2_a[49] = VD1_hilo_17 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add17 # !VD1_hilo_17 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add17;
|
| 18788 |
|
|
|
| 18789 |
|
|
|
| 18790 |
|
|
--VD1_hilo_22_Z[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[49]
|
| 18791 |
|
|
--operation mode is normal
|
| 18792 |
|
|
|
| 18793 |
|
|
VD1_hilo_22_Z[49] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[49] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[49] # !VD1_sign & !VD1_hilo_22_a[49];
|
| 18794 |
|
|
|
| 18795 |
|
|
|
| 18796 |
|
|
--RD1_r32_o_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_17
|
| 18797 |
|
|
--operation mode is arithmetic
|
| 18798 |
|
|
|
| 18799 |
|
|
RD1_r32_o_17_carry_eqn = RD1_r32_o_cout[15];
|
| 18800 |
|
|
RD1_r32_o_17_lut_out = KB1_r32_o_17 $ (KB1_r32_o_16 & RD1_r32_o_17_carry_eqn);
|
| 18801 |
|
|
RD1_r32_o_17 = DFFEAS(RD1_r32_o_17_lut_out, E1__clk0, VCC, , , , , , );
|
| 18802 |
|
|
|
| 18803 |
|
|
--RD1_r32_o_cout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[17]
|
| 18804 |
|
|
--operation mode is arithmetic
|
| 18805 |
|
|
|
| 18806 |
|
|
RD1_r32_o_cout[17] = CARRY(!RD1_r32_o_cout[15] # !KB1_r32_o_17 # !KB1_r32_o_16);
|
| 18807 |
|
|
|
| 18808 |
|
|
|
| 18809 |
|
|
--SD1_r32_o_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_17
|
| 18810 |
|
|
--operation mode is normal
|
| 18811 |
|
|
|
| 18812 |
|
|
SD1_r32_o_17_lut_out = KB1_r32_o_17;
|
| 18813 |
|
|
SD1_r32_o_17 = DFFEAS(SD1_r32_o_17_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 18814 |
|
|
|
| 18815 |
|
|
|
| 18816 |
|
|
--PD1_a_o_3_d[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[17]
|
| 18817 |
|
|
--operation mode is normal
|
| 18818 |
|
|
|
| 18819 |
|
|
PD1_a_o_3_d[17] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_17 # !PD1_un6_a_o & !PD1_a_o_3_d_a[17] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[17];
|
| 18820 |
|
|
|
| 18821 |
|
|
|
| 18822 |
|
|
--UD1_shift_out_80_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[14]
|
| 18823 |
|
|
--operation mode is normal
|
| 18824 |
|
|
|
| 18825 |
|
|
UD1_shift_out_80_a[14] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_17 # !PD1_a_o_1 & !VD1_b_o_iv_15;
|
| 18826 |
|
|
|
| 18827 |
|
|
|
| 18828 |
|
|
--UD1_shift_out_48_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48_a[30]
|
| 18829 |
|
|
--operation mode is normal
|
| 18830 |
|
|
|
| 18831 |
|
|
UD1_shift_out_48_a[30] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_7 # !PD1_a_o_0 & !VD1_b_o_iv_8 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 18832 |
|
|
|
| 18833 |
|
|
|
| 18834 |
|
|
--UD1_shift_out_45_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45_a[30]
|
| 18835 |
|
|
--operation mode is normal
|
| 18836 |
|
|
|
| 18837 |
|
|
UD1_shift_out_45_a[30] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_3 # !PD1_a_o_0 & !VD1_b_o_iv_4 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 18838 |
|
|
|
| 18839 |
|
|
|
| 18840 |
|
|
--UD1_shift_out_79_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[14]
|
| 18841 |
|
|
--operation mode is normal
|
| 18842 |
|
|
|
| 18843 |
|
|
UD1_shift_out_79_a[14] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_23 # !PD1_a_o_0 & !VD1_b_o_iv_22;
|
| 18844 |
|
|
|
| 18845 |
|
|
|
| 18846 |
|
|
--VD1_un134_hilo_combout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[14]
|
| 18847 |
|
|
--operation mode is arithmetic
|
| 18848 |
|
|
|
| 18849 |
|
|
VD1_un134_hilo_combout[14]_carry_eqn = VD1_un134_hilo_cout[12];
|
| 18850 |
|
|
VD1_un134_hilo_combout[14] = VD1_hilo_14 $ (VD1_un134_hilo_combout[14]_carry_eqn);
|
| 18851 |
|
|
|
| 18852 |
|
|
--VD1_un134_hilo_cout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[14]
|
| 18853 |
|
|
--operation mode is arithmetic
|
| 18854 |
|
|
|
| 18855 |
|
|
VD1_un134_hilo_cout[14] = CARRY(!VD1_un134_hilo_cout[12] # !VD1_hilo_15 # !VD1_hilo_14);
|
| 18856 |
|
|
|
| 18857 |
|
|
|
| 18858 |
|
|
--VD1_hilo_33_i_m[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[46]
|
| 18859 |
|
|
--operation mode is normal
|
| 18860 |
|
|
|
| 18861 |
|
|
VD1_hilo_33_i_m[46] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[46] # !VD1_hilo_33_1[64] & !VD1_hilo_46;
|
| 18862 |
|
|
|
| 18863 |
|
|
|
| 18864 |
|
|
--VD1_hilo_37_iv_2_a[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[46]
|
| 18865 |
|
|
--operation mode is normal
|
| 18866 |
|
|
|
| 18867 |
|
|
VD1_hilo_37_iv_2_a[46] = VD1_hilo_14 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add14 # !VD1_hilo_14 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add14;
|
| 18868 |
|
|
|
| 18869 |
|
|
|
| 18870 |
|
|
--VD1_hilo_22_Z[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[46]
|
| 18871 |
|
|
--operation mode is normal
|
| 18872 |
|
|
|
| 18873 |
|
|
VD1_hilo_22_Z[46] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[46] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[46] # !VD1_sign & !VD1_hilo_22_a[46];
|
| 18874 |
|
|
|
| 18875 |
|
|
|
| 18876 |
|
|
--RD1_r32_o_0_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_14
|
| 18877 |
|
|
--operation mode is arithmetic
|
| 18878 |
|
|
|
| 18879 |
|
|
RD1_r32_o_0_14_carry_eqn = RD1_r32_o_cout[12];
|
| 18880 |
|
|
RD1_r32_o_0_14_lut_out = KB1_r32_o_14 $ (!RD1_r32_o_0_14_carry_eqn);
|
| 18881 |
|
|
RD1_r32_o_0_14 = DFFEAS(RD1_r32_o_0_14_lut_out, E1__clk0, VCC, , , , , , );
|
| 18882 |
|
|
|
| 18883 |
|
|
--RD1_r32_o_cout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[14]
|
| 18884 |
|
|
--operation mode is arithmetic
|
| 18885 |
|
|
|
| 18886 |
|
|
RD1_r32_o_cout[14] = CARRY(KB1_r32_o_14 & KB1_r32_o_15 & !RD1_r32_o_cout[12]);
|
| 18887 |
|
|
|
| 18888 |
|
|
|
| 18889 |
|
|
--SD1_r32_o_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_14
|
| 18890 |
|
|
--operation mode is normal
|
| 18891 |
|
|
|
| 18892 |
|
|
SD1_r32_o_14_lut_out = KB1_r32_o_14;
|
| 18893 |
|
|
SD1_r32_o_14 = DFFEAS(SD1_r32_o_14_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 18894 |
|
|
|
| 18895 |
|
|
|
| 18896 |
|
|
--PD1_a_o_3_d[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[14]
|
| 18897 |
|
|
--operation mode is normal
|
| 18898 |
|
|
|
| 18899 |
|
|
PD1_a_o_3_d[14] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_14 # !PD1_un6_a_o & !PD1_a_o_3_d_a[14] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[14];
|
| 18900 |
|
|
|
| 18901 |
|
|
|
| 18902 |
|
|
--UD1_shift_out_80_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[15]
|
| 18903 |
|
|
--operation mode is normal
|
| 18904 |
|
|
|
| 18905 |
|
|
UD1_shift_out_80_a[15] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_18 # !PD1_a_o_1 & !VD1_b_o_iv_16;
|
| 18906 |
|
|
|
| 18907 |
|
|
|
| 18908 |
|
|
--UD1_shift_out_48_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48_a[31]
|
| 18909 |
|
|
--operation mode is normal
|
| 18910 |
|
|
|
| 18911 |
|
|
UD1_shift_out_48_a[31] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_8 # !PD1_a_o_0 & !VD1_b_o_iv_9 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 18912 |
|
|
|
| 18913 |
|
|
|
| 18914 |
|
|
--UD1_shift_out_45_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45_a[31]
|
| 18915 |
|
|
--operation mode is normal
|
| 18916 |
|
|
|
| 18917 |
|
|
UD1_shift_out_45_a[31] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_4 # !PD1_a_o_0 & !VD1_b_o_iv_5 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 18918 |
|
|
|
| 18919 |
|
|
|
| 18920 |
|
|
--VD1_un134_hilo_combout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[15]
|
| 18921 |
|
|
--operation mode is arithmetic
|
| 18922 |
|
|
|
| 18923 |
|
|
VD1_un134_hilo_combout[15]_carry_eqn = VD1_un134_hilo_cout[13];
|
| 18924 |
|
|
VD1_un134_hilo_combout[15] = VD1_hilo_15 $ (VD1_hilo_14 & VD1_un134_hilo_combout[15]_carry_eqn);
|
| 18925 |
|
|
|
| 18926 |
|
|
--VD1_un134_hilo_cout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[15]
|
| 18927 |
|
|
--operation mode is arithmetic
|
| 18928 |
|
|
|
| 18929 |
|
|
VD1_un134_hilo_cout[15] = CARRY(!VD1_un134_hilo_cout[13] # !VD1_hilo_15 # !VD1_hilo_14);
|
| 18930 |
|
|
|
| 18931 |
|
|
|
| 18932 |
|
|
--VD1_hilo_33_i_m[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[47]
|
| 18933 |
|
|
--operation mode is normal
|
| 18934 |
|
|
|
| 18935 |
|
|
VD1_hilo_33_i_m[47] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[47] # !VD1_hilo_33_1[64] & !VD1_hilo_47;
|
| 18936 |
|
|
|
| 18937 |
|
|
|
| 18938 |
|
|
--VD1_hilo_37_iv_2_a[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[47]
|
| 18939 |
|
|
--operation mode is normal
|
| 18940 |
|
|
|
| 18941 |
|
|
VD1_hilo_37_iv_2_a[47] = VD1_hilo_15 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add15 # !VD1_hilo_15 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add15;
|
| 18942 |
|
|
|
| 18943 |
|
|
|
| 18944 |
|
|
--VD1_hilo_22_Z[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[47]
|
| 18945 |
|
|
--operation mode is normal
|
| 18946 |
|
|
|
| 18947 |
|
|
VD1_hilo_22_Z[47] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[47] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[47] # !VD1_sign & !VD1_hilo_22_a[47];
|
| 18948 |
|
|
|
| 18949 |
|
|
|
| 18950 |
|
|
--RD1_r32_o_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_15
|
| 18951 |
|
|
--operation mode is arithmetic
|
| 18952 |
|
|
|
| 18953 |
|
|
RD1_r32_o_15_carry_eqn = RD1_r32_o_cout[13];
|
| 18954 |
|
|
RD1_r32_o_15_lut_out = KB1_r32_o_15 $ (KB1_r32_o_14 & !RD1_r32_o_15_carry_eqn);
|
| 18955 |
|
|
RD1_r32_o_15 = DFFEAS(RD1_r32_o_15_lut_out, E1__clk0, VCC, , , , , , );
|
| 18956 |
|
|
|
| 18957 |
|
|
--RD1_r32_o_cout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[15]
|
| 18958 |
|
|
--operation mode is arithmetic
|
| 18959 |
|
|
|
| 18960 |
|
|
RD1_r32_o_cout[15] = CARRY(KB1_r32_o_14 & KB1_r32_o_15 & !RD1_r32_o_cout[13]);
|
| 18961 |
|
|
|
| 18962 |
|
|
|
| 18963 |
|
|
--SD1_r32_o_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_15
|
| 18964 |
|
|
--operation mode is normal
|
| 18965 |
|
|
|
| 18966 |
|
|
SD1_r32_o_15_lut_out = KB1_r32_o_15;
|
| 18967 |
|
|
SD1_r32_o_15 = DFFEAS(SD1_r32_o_15_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 18968 |
|
|
|
| 18969 |
|
|
|
| 18970 |
|
|
--PD1_a_o_3_d[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[15]
|
| 18971 |
|
|
--operation mode is normal
|
| 18972 |
|
|
|
| 18973 |
|
|
PD1_a_o_3_d[15] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_15 # !PD1_un6_a_o & !PD1_a_o_3_d_a[15] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[15];
|
| 18974 |
|
|
|
| 18975 |
|
|
|
| 18976 |
|
|
--UD1_shift_out_52[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52[31]
|
| 18977 |
|
|
--operation mode is normal
|
| 18978 |
|
|
|
| 18979 |
|
|
UD1_shift_out_52[31] = PD1_a_o_1 & !UD1_shift_out_52_a[31] # !PD1_a_o_1 & UD1_shift_out_52_a[31] & VD1_b_o_iv_15 # !UD1_shift_out_52_a[31] & VD1_b_o_iv_14;
|
| 18980 |
|
|
|
| 18981 |
|
|
|
| 18982 |
|
|
--UD1_shift_out_75_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75_a[31]
|
| 18983 |
|
|
--operation mode is normal
|
| 18984 |
|
|
|
| 18985 |
|
|
UD1_shift_out_75_a[31] = PD1_a_o_3 & PD1_a_o_2 & !UD1_shift_out_43[31] # !PD1_a_o_2 & !UD1_shift_out_45[31] # !PD1_a_o_3 & !PD1_a_o_2;
|
| 18986 |
|
|
|
| 18987 |
|
|
|
| 18988 |
|
|
--VD1_hilo_37_iv_0_2[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[31]
|
| 18989 |
|
|
--operation mode is normal
|
| 18990 |
|
|
|
| 18991 |
|
|
VD1_hilo_37_iv_0_2[31] = VD1_un50_hilo_add0 & VD1_hilo_37_iv_0_a3_4[57] # VD1_un59_hilo_add0 & VD1_hilo_37_iv_0_a6_1_0[40] # !VD1_un50_hilo_add0 & VD1_un59_hilo_add0 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 18992 |
|
|
|
| 18993 |
|
|
|
| 18994 |
|
|
--VD1_hilo_37_iv_0_1[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[31]
|
| 18995 |
|
|
--operation mode is normal
|
| 18996 |
|
|
|
| 18997 |
|
|
VD1_hilo_37_iv_0_1[31] = VD1_hilo_31 & VD1_hilo_37_iv_0_o5[0] # !VD1_hilo_37_iv_0_1_a[31];
|
| 18998 |
|
|
|
| 18999 |
|
|
|
| 19000 |
|
|
--VD1_hilo_22_i_m[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_i_m[63]
|
| 19001 |
|
|
--operation mode is normal
|
| 19002 |
|
|
|
| 19003 |
|
|
VD1_hilo_22_i_m[63] = VD1_hilo_1_sqmuxa_1 & VD1_sign & VD1_hilo_15_3_i[63] # !VD1_sign & VD1_hilo_22_i_m_a[63];
|
| 19004 |
|
|
|
| 19005 |
|
|
|
| 19006 |
|
|
--VD1_hilo_33_3[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_3[63]
|
| 19007 |
|
|
--operation mode is normal
|
| 19008 |
|
|
|
| 19009 |
|
|
VD1_hilo_33_3[63] = VD1_addnop2 & VD1_hilo_33_1[64] & VD1_un50_hilo_add31 # !VD1_hilo_33_1[64] & !VD1_hilo_33_3_a[63] # !VD1_addnop2 & !VD1_hilo_33_3_a[63];
|
| 19010 |
|
|
|
| 19011 |
|
|
|
| 19012 |
|
|
--VD1_hilo_37_iv_2_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[63]
|
| 19013 |
|
|
--operation mode is normal
|
| 19014 |
|
|
|
| 19015 |
|
|
VD1_hilo_37_iv_2_a[63] = VD1_hilo_31 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add31 # !VD1_hilo_31 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add31;
|
| 19016 |
|
|
|
| 19017 |
|
|
|
| 19018 |
|
|
--UD1_shift_out_87_d_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[8]
|
| 19019 |
|
|
--operation mode is normal
|
| 19020 |
|
|
|
| 19021 |
|
|
UD1_shift_out_87_d_a[8] = PD1_a_o_1 & !VD1_b_o_iv_14 # !PD1_a_o_1 & !VD1_b_o_iv_12;
|
| 19022 |
|
|
|
| 19023 |
|
|
|
| 19024 |
|
|
--UD1_shift_out_80[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[8]
|
| 19025 |
|
|
--operation mode is normal
|
| 19026 |
|
|
|
| 19027 |
|
|
UD1_shift_out_80[8] = PD1_a_o_2 & UD1_shift_out_80_a[8] & VD1_b_o_iv_13 # !UD1_shift_out_80_a[8] & VD1_b_o_iv_15 # !PD1_a_o_2 & !UD1_shift_out_80_a[8];
|
| 19028 |
|
|
|
| 19029 |
|
|
|
| 19030 |
|
|
--UD1_shift_out_85_d_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[8]
|
| 19031 |
|
|
--operation mode is normal
|
| 19032 |
|
|
|
| 19033 |
|
|
UD1_shift_out_85_d_a[8] = PD1_a_o_0 & !VD1_b_o_iv_5 # !PD1_a_o_0 & !VD1_b_o_iv_6;
|
| 19034 |
|
|
|
| 19035 |
|
|
|
| 19036 |
|
|
--UD1_shift_out_45[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45[28]
|
| 19037 |
|
|
--operation mode is normal
|
| 19038 |
|
|
|
| 19039 |
|
|
UD1_shift_out_45[28] = PD1_a_o_1 & !UD1_shift_out_45_a[28] # !PD1_a_o_1 & UD1_shift_out_45_a[28] & VD1_b_o_iv_4 # !UD1_shift_out_45_a[28] & VD1_b_o_iv_3;
|
| 19040 |
|
|
|
| 19041 |
|
|
|
| 19042 |
|
|
--UD1_shift_out_91_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[8]
|
| 19043 |
|
|
--operation mode is normal
|
| 19044 |
|
|
|
| 19045 |
|
|
UD1_shift_out_91_a[8] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_8 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[8];
|
| 19046 |
|
|
|
| 19047 |
|
|
|
| 19048 |
|
|
--UD1_shift_out_76[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[8]
|
| 19049 |
|
|
--operation mode is normal
|
| 19050 |
|
|
|
| 19051 |
|
|
UD1_shift_out_76[8] = UD1_shift_out587 & !PD1_a_o_3 & PD1_a_o_2 & UD1_shift_out_79[20];
|
| 19052 |
|
|
|
| 19053 |
|
|
|
| 19054 |
|
|
--PD1_a_o_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[8]
|
| 19055 |
|
|
--operation mode is normal
|
| 19056 |
|
|
|
| 19057 |
|
|
PD1_a_o_a[8] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_8 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_8;
|
| 19058 |
|
|
|
| 19059 |
|
|
|
| 19060 |
|
|
--PD1_a_o_3_Z[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[8]
|
| 19061 |
|
|
--operation mode is normal
|
| 19062 |
|
|
|
| 19063 |
|
|
PD1_a_o_3_Z[8] = PD1_a_o_3_s[0] & SD1_r32_o_8 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[8];
|
| 19064 |
|
|
|
| 19065 |
|
|
|
| 19066 |
|
|
--TD1_un1_b_1_combout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[8]
|
| 19067 |
|
|
--operation mode is normal
|
| 19068 |
|
|
|
| 19069 |
|
|
TD1_un1_b_1_combout[8] = TD1_sum13_0_a2 $ !VD1_b_o_iv_8;
|
| 19070 |
|
|
|
| 19071 |
|
|
|
| 19072 |
|
|
--UD1_shift_out_87_d_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[9]
|
| 19073 |
|
|
--operation mode is normal
|
| 19074 |
|
|
|
| 19075 |
|
|
UD1_shift_out_87_d_a[9] = PD1_a_o_1 & !VD1_b_o_iv_15 # !PD1_a_o_1 & !VD1_b_o_iv_13;
|
| 19076 |
|
|
|
| 19077 |
|
|
|
| 19078 |
|
|
--UD1_shift_out_80[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[9]
|
| 19079 |
|
|
--operation mode is normal
|
| 19080 |
|
|
|
| 19081 |
|
|
UD1_shift_out_80[9] = PD1_a_o_2 & UD1_shift_out_80_a[9] & VD1_b_o_iv_14 # !UD1_shift_out_80_a[9] & VD1_b_o_iv_16 # !PD1_a_o_2 & !UD1_shift_out_80_a[9];
|
| 19082 |
|
|
|
| 19083 |
|
|
|
| 19084 |
|
|
--UD1_shift_out_85_d_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[9]
|
| 19085 |
|
|
--operation mode is normal
|
| 19086 |
|
|
|
| 19087 |
|
|
UD1_shift_out_85_d_a[9] = PD1_a_o_0 & !VD1_b_o_iv_6 # !PD1_a_o_0 & !VD1_b_o_iv_7;
|
| 19088 |
|
|
|
| 19089 |
|
|
|
| 19090 |
|
|
--UD1_shift_out_74_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[9]
|
| 19091 |
|
|
--operation mode is normal
|
| 19092 |
|
|
|
| 19093 |
|
|
UD1_shift_out_74_a[9] = PD1_a_o_3 & !VD1_b_o_iv_31 # !PD1_a_o_3 & PD1_a_o_1 & !VD1_b_o_iv_31 # !PD1_a_o_1 & !UD1_shift_out_39[17];
|
| 19094 |
|
|
|
| 19095 |
|
|
|
| 19096 |
|
|
--UD1_shift_out_91_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[9]
|
| 19097 |
|
|
--operation mode is normal
|
| 19098 |
|
|
|
| 19099 |
|
|
UD1_shift_out_91_a[9] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_9 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[9];
|
| 19100 |
|
|
|
| 19101 |
|
|
|
| 19102 |
|
|
--UD1_shift_out_76[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[9]
|
| 19103 |
|
|
--operation mode is normal
|
| 19104 |
|
|
|
| 19105 |
|
|
UD1_shift_out_76[9] = UD1_shift_out587 & !PD1_a_o_3 & PD1_a_o_2 & UD1_shift_out_42[1];
|
| 19106 |
|
|
|
| 19107 |
|
|
|
| 19108 |
|
|
--VD1_hilo_37_iv_0_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[9]
|
| 19109 |
|
|
--operation mode is normal
|
| 19110 |
|
|
|
| 19111 |
|
|
VD1_hilo_37_iv_0_a[9] = VD1_hilo_10 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_8 # !VD1_hilo_10 & !VD1_hilo_2_sqmuxa # !VD1_hilo_8;
|
| 19112 |
|
|
|
| 19113 |
|
|
|
| 19114 |
|
|
--VD1_hilo_37_iv_0_0[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[9]
|
| 19115 |
|
|
--operation mode is normal
|
| 19116 |
|
|
|
| 19117 |
|
|
VD1_hilo_37_iv_0_0[9] = VD1_hilo_9 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[9] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_9 & VD1_un134_hilo_combout[9] & VD1_hilo_37_iv_0_a3_0[0];
|
| 19118 |
|
|
|
| 19119 |
|
|
|
| 19120 |
|
|
--VD1_hilo_37_iv_2[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[41]
|
| 19121 |
|
|
--operation mode is normal
|
| 19122 |
|
|
|
| 19123 |
|
|
VD1_hilo_37_iv_2[41] = VD1_hilo_33_i_m[41] # VD1_hilo_37_iv_2_a[41] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[41];
|
| 19124 |
|
|
|
| 19125 |
|
|
|
| 19126 |
|
|
--VD1_hilo_37_iv_a[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[41]
|
| 19127 |
|
|
--operation mode is normal
|
| 19128 |
|
|
|
| 19129 |
|
|
VD1_hilo_37_iv_a[41] = RC1_alu_func_o_0 & !PD1_a_o_9 # !RC1_alu_func_o_0 & !VD1_hilo_41;
|
| 19130 |
|
|
|
| 19131 |
|
|
|
| 19132 |
|
|
--PD1_a_o_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[9]
|
| 19133 |
|
|
--operation mode is normal
|
| 19134 |
|
|
|
| 19135 |
|
|
PD1_a_o_a[9] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_9 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_9;
|
| 19136 |
|
|
|
| 19137 |
|
|
|
| 19138 |
|
|
--PD1_a_o_3_Z[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[9]
|
| 19139 |
|
|
--operation mode is normal
|
| 19140 |
|
|
|
| 19141 |
|
|
PD1_a_o_3_Z[9] = PD1_a_o_3_s[0] & SD1_r32_o_9 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[9];
|
| 19142 |
|
|
|
| 19143 |
|
|
|
| 19144 |
|
|
--VD1_hilo_37_iv_0_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[10]
|
| 19145 |
|
|
--operation mode is normal
|
| 19146 |
|
|
|
| 19147 |
|
|
VD1_hilo_37_iv_0_a[10] = VD1_hilo_11 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_9 # !VD1_hilo_11 & !VD1_hilo_2_sqmuxa # !VD1_hilo_9;
|
| 19148 |
|
|
|
| 19149 |
|
|
|
| 19150 |
|
|
--VD1_hilo_37_iv_0_0[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[10]
|
| 19151 |
|
|
--operation mode is normal
|
| 19152 |
|
|
|
| 19153 |
|
|
VD1_hilo_37_iv_0_0[10] = VD1_hilo_10 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[10] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_10 & VD1_un134_hilo_combout[10] & VD1_hilo_37_iv_0_a3_0[0];
|
| 19154 |
|
|
|
| 19155 |
|
|
|
| 19156 |
|
|
--VD1_hilo_37_iv_2[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[42]
|
| 19157 |
|
|
--operation mode is normal
|
| 19158 |
|
|
|
| 19159 |
|
|
VD1_hilo_37_iv_2[42] = VD1_hilo_33_i_m[42] # VD1_hilo_37_iv_2_a[42] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[42];
|
| 19160 |
|
|
|
| 19161 |
|
|
|
| 19162 |
|
|
--VD1_hilo_37_iv_a[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[42]
|
| 19163 |
|
|
--operation mode is normal
|
| 19164 |
|
|
|
| 19165 |
|
|
VD1_hilo_37_iv_a[42] = RC1_alu_func_o_0 & !PD1_a_o_10 # !RC1_alu_func_o_0 & !VD1_hilo_42;
|
| 19166 |
|
|
|
| 19167 |
|
|
|
| 19168 |
|
|
--RD1_r32_o_0_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_10
|
| 19169 |
|
|
--operation mode is arithmetic
|
| 19170 |
|
|
|
| 19171 |
|
|
RD1_r32_o_0_10_carry_eqn = RD1_r32_o_cout[8];
|
| 19172 |
|
|
RD1_r32_o_0_10_lut_out = KB1_r32_o_10 $ (!RD1_r32_o_0_10_carry_eqn);
|
| 19173 |
|
|
RD1_r32_o_0_10 = DFFEAS(RD1_r32_o_0_10_lut_out, E1__clk0, VCC, , , , , , );
|
| 19174 |
|
|
|
| 19175 |
|
|
--RD1_r32_o_cout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[10]
|
| 19176 |
|
|
--operation mode is arithmetic
|
| 19177 |
|
|
|
| 19178 |
|
|
RD1_r32_o_cout[10] = CARRY(KB1_r32_o_10 & KB1_r32_o_11 & !RD1_r32_o_cout[8]);
|
| 19179 |
|
|
|
| 19180 |
|
|
|
| 19181 |
|
|
--PD1_a_o_3_d[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[10]
|
| 19182 |
|
|
--operation mode is normal
|
| 19183 |
|
|
|
| 19184 |
|
|
PD1_a_o_3_d[10] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_10 # !PD1_un6_a_o & !PD1_a_o_3_d_a[10] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[10];
|
| 19185 |
|
|
|
| 19186 |
|
|
|
| 19187 |
|
|
--UD1_shift_out_87_d[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[10]
|
| 19188 |
|
|
--operation mode is normal
|
| 19189 |
|
|
|
| 19190 |
|
|
UD1_shift_out_87_d[10] = PD1_a_o_0 & UD1_shift_out_80[10] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[10];
|
| 19191 |
|
|
|
| 19192 |
|
|
|
| 19193 |
|
|
--UD1_shift_out_85_d[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[10]
|
| 19194 |
|
|
--operation mode is normal
|
| 19195 |
|
|
|
| 19196 |
|
|
UD1_shift_out_85_d[10] = PD1_a_o_2 & UD1_shift_out_45[30] # !PD1_a_o_2 & !UD1_shift_out_77_a[16];
|
| 19197 |
|
|
|
| 19198 |
|
|
|
| 19199 |
|
|
--UD1_shift_out_76[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[10]
|
| 19200 |
|
|
--operation mode is normal
|
| 19201 |
|
|
|
| 19202 |
|
|
UD1_shift_out_76[10] = UD1_shift_out_76_a[10] & PD1_a_o_0 & VD1_b_o_iv_31 # !PD1_a_o_0 & VD1_b_o_iv_30;
|
| 19203 |
|
|
|
| 19204 |
|
|
|
| 19205 |
|
|
--UD1_shift_out_91_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[10]
|
| 19206 |
|
|
--operation mode is normal
|
| 19207 |
|
|
|
| 19208 |
|
|
UD1_shift_out_91_a[10] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_10 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[10];
|
| 19209 |
|
|
|
| 19210 |
|
|
|
| 19211 |
|
|
--UD1_shift_out_77[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[10]
|
| 19212 |
|
|
--operation mode is normal
|
| 19213 |
|
|
|
| 19214 |
|
|
UD1_shift_out_77[10] = !PD1_a_o_2 & PD1_a_o_1 & VD1_b_o_iv_0 & UD1_shift_out_77_a[10] # !PD1_a_o_1 & !UD1_shift_out_77_a[10];
|
| 19215 |
|
|
|
| 19216 |
|
|
|
| 19217 |
|
|
--UD1_shift_out_86[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[10]
|
| 19218 |
|
|
--operation mode is normal
|
| 19219 |
|
|
|
| 19220 |
|
|
UD1_shift_out_86[10] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[10] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[10];
|
| 19221 |
|
|
|
| 19222 |
|
|
|
| 19223 |
|
|
--UD1_shift_out_87_d_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[11]
|
| 19224 |
|
|
--operation mode is normal
|
| 19225 |
|
|
|
| 19226 |
|
|
UD1_shift_out_87_d_a[11] = PD1_a_o_1 & !VD1_b_o_iv_17 # !PD1_a_o_1 & !VD1_b_o_iv_15;
|
| 19227 |
|
|
|
| 19228 |
|
|
|
| 19229 |
|
|
--UD1_shift_out_80[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[11]
|
| 19230 |
|
|
--operation mode is normal
|
| 19231 |
|
|
|
| 19232 |
|
|
UD1_shift_out_80[11] = PD1_a_o_2 & UD1_shift_out_80_a[11] & VD1_b_o_iv_16 # !UD1_shift_out_80_a[11] & VD1_b_o_iv_18 # !PD1_a_o_2 & !UD1_shift_out_80_a[11];
|
| 19233 |
|
|
|
| 19234 |
|
|
|
| 19235 |
|
|
--UD1_shift_out_85_d_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[11]
|
| 19236 |
|
|
--operation mode is normal
|
| 19237 |
|
|
|
| 19238 |
|
|
UD1_shift_out_85_d_a[11] = PD1_a_o_0 & !VD1_b_o_iv_8 # !PD1_a_o_0 & !VD1_b_o_iv_9;
|
| 19239 |
|
|
|
| 19240 |
|
|
|
| 19241 |
|
|
--UD1_shift_out_91_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[11]
|
| 19242 |
|
|
--operation mode is normal
|
| 19243 |
|
|
|
| 19244 |
|
|
UD1_shift_out_91_a[11] = !PD1_a_o_3 & PD1_a_o_2 & !PD1_a_o_1 & UD1_shift_out_39[19];
|
| 19245 |
|
|
|
| 19246 |
|
|
|
| 19247 |
|
|
--UD1_shift_out_88[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[11]
|
| 19248 |
|
|
--operation mode is normal
|
| 19249 |
|
|
|
| 19250 |
|
|
UD1_shift_out_88[11] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_11 # !UD1_shift_out_sn_b10_0 & UD1_shift_out_79[11];
|
| 19251 |
|
|
|
| 19252 |
|
|
|
| 19253 |
|
|
--VD1_hilo_37_iv_0_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[11]
|
| 19254 |
|
|
--operation mode is normal
|
| 19255 |
|
|
|
| 19256 |
|
|
VD1_hilo_37_iv_0_a[11] = VD1_hilo_12 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_10 # !VD1_hilo_12 & !VD1_hilo_2_sqmuxa # !VD1_hilo_10;
|
| 19257 |
|
|
|
| 19258 |
|
|
|
| 19259 |
|
|
--VD1_hilo_37_iv_0_0[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[11]
|
| 19260 |
|
|
--operation mode is normal
|
| 19261 |
|
|
|
| 19262 |
|
|
VD1_hilo_37_iv_0_0[11] = VD1_hilo_11 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[11] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_11 & VD1_un134_hilo_combout[11] & VD1_hilo_37_iv_0_a3_0[0];
|
| 19263 |
|
|
|
| 19264 |
|
|
|
| 19265 |
|
|
--VD1_hilo_37_iv_2[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[43]
|
| 19266 |
|
|
--operation mode is normal
|
| 19267 |
|
|
|
| 19268 |
|
|
VD1_hilo_37_iv_2[43] = VD1_hilo_33_i_m[43] # VD1_hilo_37_iv_2_a[43] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[43];
|
| 19269 |
|
|
|
| 19270 |
|
|
|
| 19271 |
|
|
--VD1_hilo_37_iv_a[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[43]
|
| 19272 |
|
|
--operation mode is normal
|
| 19273 |
|
|
|
| 19274 |
|
|
VD1_hilo_37_iv_a[43] = RC1_alu_func_o_0 & !PD1_a_o_11 # !RC1_alu_func_o_0 & !VD1_hilo_43;
|
| 19275 |
|
|
|
| 19276 |
|
|
|
| 19277 |
|
|
--PD1_a_o_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[11]
|
| 19278 |
|
|
--operation mode is normal
|
| 19279 |
|
|
|
| 19280 |
|
|
PD1_a_o_a[11] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_11 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_11;
|
| 19281 |
|
|
|
| 19282 |
|
|
|
| 19283 |
|
|
--PD1_a_o_3_Z[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[11]
|
| 19284 |
|
|
--operation mode is normal
|
| 19285 |
|
|
|
| 19286 |
|
|
PD1_a_o_3_Z[11] = PD1_a_o_3_s[0] & SD1_r32_o_11 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[11];
|
| 19287 |
|
|
|
| 19288 |
|
|
|
| 19289 |
|
|
--TD1_un1_b_1_combout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[11]
|
| 19290 |
|
|
--operation mode is normal
|
| 19291 |
|
|
|
| 19292 |
|
|
TD1_un1_b_1_combout[11] = TD1_sum13_0_a2 $ !VD1_b_o_iv_11;
|
| 19293 |
|
|
|
| 19294 |
|
|
|
| 19295 |
|
|
--UD1_shift_out_80_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[21]
|
| 19296 |
|
|
--operation mode is normal
|
| 19297 |
|
|
|
| 19298 |
|
|
UD1_shift_out_80_a[21] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_24 # !PD1_a_o_1 & !VD1_b_o_iv_22;
|
| 19299 |
|
|
|
| 19300 |
|
|
|
| 19301 |
|
|
--UD1_shift_out_54_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54_a[29]
|
| 19302 |
|
|
--operation mode is normal
|
| 19303 |
|
|
|
| 19304 |
|
|
UD1_shift_out_54_a[29] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_14 # !PD1_a_o_0 & !VD1_b_o_iv_15 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 19305 |
|
|
|
| 19306 |
|
|
|
| 19307 |
|
|
--UD1_shift_out_79_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[21]
|
| 19308 |
|
|
--operation mode is normal
|
| 19309 |
|
|
|
| 19310 |
|
|
UD1_shift_out_79_a[21] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_30 # !PD1_a_o_0 & !VD1_b_o_iv_29;
|
| 19311 |
|
|
|
| 19312 |
|
|
|
| 19313 |
|
|
--VD1_un134_hilo_combout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[21]
|
| 19314 |
|
|
--operation mode is arithmetic
|
| 19315 |
|
|
|
| 19316 |
|
|
VD1_un134_hilo_combout[21]_carry_eqn = VD1_un134_hilo_cout[19];
|
| 19317 |
|
|
VD1_un134_hilo_combout[21] = VD1_hilo_21 $ (VD1_hilo_20 & !VD1_un134_hilo_combout[21]_carry_eqn);
|
| 19318 |
|
|
|
| 19319 |
|
|
--VD1_un134_hilo_cout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[21]
|
| 19320 |
|
|
--operation mode is arithmetic
|
| 19321 |
|
|
|
| 19322 |
|
|
VD1_un134_hilo_cout[21] = CARRY(VD1_hilo_20 & VD1_hilo_21 & !VD1_un134_hilo_cout[19]);
|
| 19323 |
|
|
|
| 19324 |
|
|
|
| 19325 |
|
|
--VD1_hilo_33_i_m[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[53]
|
| 19326 |
|
|
--operation mode is normal
|
| 19327 |
|
|
|
| 19328 |
|
|
VD1_hilo_33_i_m[53] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[53] # !VD1_hilo_33_1[64] & !VD1_hilo_53;
|
| 19329 |
|
|
|
| 19330 |
|
|
|
| 19331 |
|
|
--VD1_hilo_37_iv_2_a[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[53]
|
| 19332 |
|
|
--operation mode is normal
|
| 19333 |
|
|
|
| 19334 |
|
|
VD1_hilo_37_iv_2_a[53] = VD1_hilo_21 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add21 # !VD1_hilo_21 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add21;
|
| 19335 |
|
|
|
| 19336 |
|
|
|
| 19337 |
|
|
--VD1_hilo_22_Z[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[53]
|
| 19338 |
|
|
--operation mode is normal
|
| 19339 |
|
|
|
| 19340 |
|
|
VD1_hilo_22_Z[53] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[53] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[53] # !VD1_sign & !VD1_hilo_22_a[53];
|
| 19341 |
|
|
|
| 19342 |
|
|
|
| 19343 |
|
|
--RD1_r32_o_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_21
|
| 19344 |
|
|
--operation mode is arithmetic
|
| 19345 |
|
|
|
| 19346 |
|
|
RD1_r32_o_21_carry_eqn = RD1_r32_o_cout[19];
|
| 19347 |
|
|
RD1_r32_o_21_lut_out = KB1_r32_o_21 $ (KB1_r32_o_20 & RD1_r32_o_21_carry_eqn);
|
| 19348 |
|
|
RD1_r32_o_21 = DFFEAS(RD1_r32_o_21_lut_out, E1__clk0, VCC, , , , , , );
|
| 19349 |
|
|
|
| 19350 |
|
|
--RD1_r32_o_cout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[21]
|
| 19351 |
|
|
--operation mode is arithmetic
|
| 19352 |
|
|
|
| 19353 |
|
|
RD1_r32_o_cout[21] = CARRY(!RD1_r32_o_cout[19] # !KB1_r32_o_21 # !KB1_r32_o_20);
|
| 19354 |
|
|
|
| 19355 |
|
|
|
| 19356 |
|
|
--SD1_r32_o_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_21
|
| 19357 |
|
|
--operation mode is normal
|
| 19358 |
|
|
|
| 19359 |
|
|
SD1_r32_o_21_lut_out = KB1_r32_o_21;
|
| 19360 |
|
|
SD1_r32_o_21 = DFFEAS(SD1_r32_o_21_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 19361 |
|
|
|
| 19362 |
|
|
|
| 19363 |
|
|
--PD1_a_o_3_d[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[21]
|
| 19364 |
|
|
--operation mode is normal
|
| 19365 |
|
|
|
| 19366 |
|
|
PD1_a_o_3_d[21] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_21 # !PD1_un6_a_o & !PD1_a_o_3_d_a[21] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[21];
|
| 19367 |
|
|
|
| 19368 |
|
|
|
| 19369 |
|
|
--UD1_shift_out_80_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[20]
|
| 19370 |
|
|
--operation mode is normal
|
| 19371 |
|
|
|
| 19372 |
|
|
UD1_shift_out_80_a[20] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_23 # !PD1_a_o_1 & !VD1_b_o_iv_21;
|
| 19373 |
|
|
|
| 19374 |
|
|
|
| 19375 |
|
|
--UD1_shift_out_54_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54_a[28]
|
| 19376 |
|
|
--operation mode is normal
|
| 19377 |
|
|
|
| 19378 |
|
|
UD1_shift_out_54_a[28] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_13 # !PD1_a_o_0 & !VD1_b_o_iv_14 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 19379 |
|
|
|
| 19380 |
|
|
|
| 19381 |
|
|
--VD1_un134_hilo_combout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[20]
|
| 19382 |
|
|
--operation mode is arithmetic
|
| 19383 |
|
|
|
| 19384 |
|
|
VD1_un134_hilo_combout[20]_carry_eqn = VD1_un134_hilo_cout[18];
|
| 19385 |
|
|
VD1_un134_hilo_combout[20] = VD1_hilo_20 $ (!VD1_un134_hilo_combout[20]_carry_eqn);
|
| 19386 |
|
|
|
| 19387 |
|
|
--VD1_un134_hilo_cout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[20]
|
| 19388 |
|
|
--operation mode is arithmetic
|
| 19389 |
|
|
|
| 19390 |
|
|
VD1_un134_hilo_cout[20] = CARRY(VD1_hilo_20 & VD1_hilo_21 & !VD1_un134_hilo_cout[18]);
|
| 19391 |
|
|
|
| 19392 |
|
|
|
| 19393 |
|
|
--VD1_hilo_24_add20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add20
|
| 19394 |
|
|
--operation mode is arithmetic
|
| 19395 |
|
|
|
| 19396 |
|
|
VD1_hilo_24_add20_carry_eqn = VD1_hilo_24_carry_19;
|
| 19397 |
|
|
VD1_hilo_24_add20 = VD1_hilo_51 $ VD1_un1_op2_reged_1_i_m6[20] $ !VD1_hilo_24_add20_carry_eqn;
|
| 19398 |
|
|
|
| 19399 |
|
|
--VD1_hilo_24_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_20
|
| 19400 |
|
|
--operation mode is arithmetic
|
| 19401 |
|
|
|
| 19402 |
|
|
VD1_hilo_24_carry_20 = CARRY(VD1_hilo_51 & VD1_un1_op2_reged_1_i_m6[20] # !VD1_hilo_24_carry_19 # !VD1_hilo_51 & VD1_un1_op2_reged_1_i_m6[20] & !VD1_hilo_24_carry_19);
|
| 19403 |
|
|
|
| 19404 |
|
|
|
| 19405 |
|
|
--VD1_hilo_37_iv_0_3[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[52]
|
| 19406 |
|
|
--operation mode is normal
|
| 19407 |
|
|
|
| 19408 |
|
|
VD1_hilo_37_iv_0_3[52] = VD1_hilo_53 & !VD1_un59_hilo_add21 & VD1_hilo_37_iv_0_a6_1_0[40] # !VD1_hilo_53 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_un59_hilo_add21 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 19409 |
|
|
|
| 19410 |
|
|
|
| 19411 |
|
|
--VD1_hilo_37_iv_0_4[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4[52]
|
| 19412 |
|
|
--operation mode is normal
|
| 19413 |
|
|
|
| 19414 |
|
|
VD1_hilo_37_iv_0_4[52] = VD1_hilo_37_iv_0_1[52] # VD1_hilo_37_iv_0_4_a[52] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add20;
|
| 19415 |
|
|
|
| 19416 |
|
|
|
| 19417 |
|
|
--RD1_r32_o_0_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_20
|
| 19418 |
|
|
--operation mode is arithmetic
|
| 19419 |
|
|
|
| 19420 |
|
|
RD1_r32_o_0_20_carry_eqn = RD1_r32_o_cout[18];
|
| 19421 |
|
|
RD1_r32_o_0_20_lut_out = KB1_r32_o_20 $ (RD1_r32_o_0_20_carry_eqn);
|
| 19422 |
|
|
RD1_r32_o_0_20 = DFFEAS(RD1_r32_o_0_20_lut_out, E1__clk0, VCC, , , , , , );
|
| 19423 |
|
|
|
| 19424 |
|
|
--RD1_r32_o_cout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[20]
|
| 19425 |
|
|
--operation mode is arithmetic
|
| 19426 |
|
|
|
| 19427 |
|
|
RD1_r32_o_cout[20] = CARRY(!RD1_r32_o_cout[18] # !KB1_r32_o_21 # !KB1_r32_o_20);
|
| 19428 |
|
|
|
| 19429 |
|
|
|
| 19430 |
|
|
--SD1_r32_o_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_20
|
| 19431 |
|
|
--operation mode is normal
|
| 19432 |
|
|
|
| 19433 |
|
|
SD1_r32_o_20_lut_out = KB1_r32_o_20;
|
| 19434 |
|
|
SD1_r32_o_20 = DFFEAS(SD1_r32_o_20_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 19435 |
|
|
|
| 19436 |
|
|
|
| 19437 |
|
|
--PD1_a_o_3_d[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[20]
|
| 19438 |
|
|
--operation mode is normal
|
| 19439 |
|
|
|
| 19440 |
|
|
PD1_a_o_3_d[20] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_20 # !PD1_un6_a_o & !PD1_a_o_3_d_a[20] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[20];
|
| 19441 |
|
|
|
| 19442 |
|
|
|
| 19443 |
|
|
--TD1_un1_b_1_combout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[19]
|
| 19444 |
|
|
--operation mode is normal
|
| 19445 |
|
|
|
| 19446 |
|
|
TD1_un1_b_1_combout[19] = TD1_sum13_0_a2 $ !VD1_b_o_iv_19;
|
| 19447 |
|
|
|
| 19448 |
|
|
|
| 19449 |
|
|
--UD1_shift_out_43[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43[28]
|
| 19450 |
|
|
--operation mode is normal
|
| 19451 |
|
|
|
| 19452 |
|
|
UD1_shift_out_43[28] = VD1_b_o_iv_0 & !PD1_a_o_1 & !PD1_a_o_0;
|
| 19453 |
|
|
|
| 19454 |
|
|
|
| 19455 |
|
|
--UD1_shift_out_48[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48[28]
|
| 19456 |
|
|
--operation mode is normal
|
| 19457 |
|
|
|
| 19458 |
|
|
UD1_shift_out_48[28] = PD1_a_o_1 & !UD1_shift_out_48_a[28] # !PD1_a_o_1 & UD1_shift_out_48_a[28] & VD1_b_o_iv_8 # !UD1_shift_out_48_a[28] & VD1_b_o_iv_7;
|
| 19459 |
|
|
|
| 19460 |
|
|
|
| 19461 |
|
|
--UD1_shift_out_87_d_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[19]
|
| 19462 |
|
|
--operation mode is normal
|
| 19463 |
|
|
|
| 19464 |
|
|
UD1_shift_out_87_d_a[19] = PD1_a_o_1 & !VD1_b_o_iv_25 # !PD1_a_o_1 & !VD1_b_o_iv_23;
|
| 19465 |
|
|
|
| 19466 |
|
|
|
| 19467 |
|
|
--UD1_shift_out_80[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[19]
|
| 19468 |
|
|
--operation mode is normal
|
| 19469 |
|
|
|
| 19470 |
|
|
UD1_shift_out_80[19] = PD1_a_o_2 & UD1_shift_out_80_a[19] & VD1_b_o_iv_24 # !UD1_shift_out_80_a[19] & VD1_b_o_iv_26 # !PD1_a_o_2 & !UD1_shift_out_80_a[19];
|
| 19471 |
|
|
|
| 19472 |
|
|
|
| 19473 |
|
|
--UD1_shift_out_77_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[25]
|
| 19474 |
|
|
--operation mode is normal
|
| 19475 |
|
|
|
| 19476 |
|
|
UD1_shift_out_77_a[25] = PD1_a_o_0 & !VD1_b_o_iv_16 # !PD1_a_o_0 & !VD1_b_o_iv_17;
|
| 19477 |
|
|
|
| 19478 |
|
|
|
| 19479 |
|
|
--VD1_hilo_37_iv_0_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[19]
|
| 19480 |
|
|
--operation mode is normal
|
| 19481 |
|
|
|
| 19482 |
|
|
VD1_hilo_37_iv_0_a[19] = VD1_hilo_20 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_18 # !VD1_hilo_20 & !VD1_hilo_2_sqmuxa # !VD1_hilo_18;
|
| 19483 |
|
|
|
| 19484 |
|
|
|
| 19485 |
|
|
--VD1_hilo_37_iv_0_0[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[19]
|
| 19486 |
|
|
--operation mode is normal
|
| 19487 |
|
|
|
| 19488 |
|
|
VD1_hilo_37_iv_0_0[19] = VD1_hilo_19 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[19] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_19 & VD1_un134_hilo_combout[19] & VD1_hilo_37_iv_0_a3_0[0];
|
| 19489 |
|
|
|
| 19490 |
|
|
|
| 19491 |
|
|
--VD1_hilo_37_iv_0_8[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_8[51]
|
| 19492 |
|
|
--operation mode is normal
|
| 19493 |
|
|
|
| 19494 |
|
|
VD1_hilo_37_iv_0_8[51] = VD1_hilo_37_iv_0_8_a[51] # VD1_hilo_37_iv_0_6[51] # VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_19;
|
| 19495 |
|
|
|
| 19496 |
|
|
|
| 19497 |
|
|
--PD1_a_o_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[19]
|
| 19498 |
|
|
--operation mode is normal
|
| 19499 |
|
|
|
| 19500 |
|
|
PD1_a_o_a[19] = SC1_muxa_ctl_o_1 & !FB1_r32_o_19 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_19;
|
| 19501 |
|
|
|
| 19502 |
|
|
|
| 19503 |
|
|
--PD1_a_o_3_Z[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[19]
|
| 19504 |
|
|
--operation mode is normal
|
| 19505 |
|
|
|
| 19506 |
|
|
PD1_a_o_3_Z[19] = PD1_a_o_3_s[0] & SD1_r32_o_19 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[19];
|
| 19507 |
|
|
|
| 19508 |
|
|
|
| 19509 |
|
|
--UD1_shift_out_84_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[19]
|
| 19510 |
|
|
--operation mode is normal
|
| 19511 |
|
|
|
| 19512 |
|
|
UD1_shift_out_84_a[19] = PD1_a_o_2 & !UD1_shift_out_45[31] # !PD1_a_o_2 & !UD1_shift_out_48[31];
|
| 19513 |
|
|
|
| 19514 |
|
|
|
| 19515 |
|
|
--UD1_shift_out_87_d_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[18]
|
| 19516 |
|
|
--operation mode is normal
|
| 19517 |
|
|
|
| 19518 |
|
|
UD1_shift_out_87_d_a[18] = PD1_a_o_1 & !VD1_b_o_iv_24 # !PD1_a_o_1 & !VD1_b_o_iv_22;
|
| 19519 |
|
|
|
| 19520 |
|
|
|
| 19521 |
|
|
--UD1_shift_out_80[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[18]
|
| 19522 |
|
|
--operation mode is normal
|
| 19523 |
|
|
|
| 19524 |
|
|
UD1_shift_out_80[18] = PD1_a_o_2 & UD1_shift_out_80_a[18] & VD1_b_o_iv_23 # !UD1_shift_out_80_a[18] & VD1_b_o_iv_25 # !PD1_a_o_2 & !UD1_shift_out_80_a[18];
|
| 19525 |
|
|
|
| 19526 |
|
|
|
| 19527 |
|
|
--UD1_shift_out_77_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[24]
|
| 19528 |
|
|
--operation mode is normal
|
| 19529 |
|
|
|
| 19530 |
|
|
UD1_shift_out_77_a[24] = PD1_a_o_0 & !VD1_b_o_iv_15 # !PD1_a_o_0 & !VD1_b_o_iv_16;
|
| 19531 |
|
|
|
| 19532 |
|
|
|
| 19533 |
|
|
--UD1_shift_out_52[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52[30]
|
| 19534 |
|
|
--operation mode is normal
|
| 19535 |
|
|
|
| 19536 |
|
|
UD1_shift_out_52[30] = PD1_a_o_1 & !UD1_shift_out_52_a[30] # !PD1_a_o_1 & UD1_shift_out_52_a[30] & VD1_b_o_iv_14 # !UD1_shift_out_52_a[30] & VD1_b_o_iv_13;
|
| 19537 |
|
|
|
| 19538 |
|
|
|
| 19539 |
|
|
--UD1_shift_out_83_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83_a[18]
|
| 19540 |
|
|
--operation mode is normal
|
| 19541 |
|
|
|
| 19542 |
|
|
UD1_shift_out_83_a[18] = PD1_a_o_1 & !VD1_b_o_iv_31 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_31 # !PD1_a_o_0 & !VD1_b_o_iv_30;
|
| 19543 |
|
|
|
| 19544 |
|
|
|
| 19545 |
|
|
--UD1_shift_out_77[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[18]
|
| 19546 |
|
|
--operation mode is normal
|
| 19547 |
|
|
|
| 19548 |
|
|
UD1_shift_out_77[18] = PD1_a_o_2 & UD1_shift_out_85_d[10] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[10] # !PD1_a_o_1 & !UD1_shift_out_77_a[18];
|
| 19549 |
|
|
|
| 19550 |
|
|
|
| 19551 |
|
|
--VD1_hilo_37_iv_1[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1[18]
|
| 19552 |
|
|
--operation mode is normal
|
| 19553 |
|
|
|
| 19554 |
|
|
VD1_hilo_37_iv_1[18] = VD1_hilo_17 & VD1_hilo_2_sqmuxa # !VD1_hilo_37_iv_1_a[18];
|
| 19555 |
|
|
|
| 19556 |
|
|
|
| 19557 |
|
|
--VD1_hilo_37_iv_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[18]
|
| 19558 |
|
|
--operation mode is normal
|
| 19559 |
|
|
|
| 19560 |
|
|
VD1_hilo_37_iv_a[18] = RC1_alu_func_o_0 & !VD1_hilo_18 # !RC1_alu_func_o_0 & !PD1_a_o_18 # !VD1_hilo25;
|
| 19561 |
|
|
|
| 19562 |
|
|
|
| 19563 |
|
|
--VD1_hilo_37_iv_0_4[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4[50]
|
| 19564 |
|
|
--operation mode is normal
|
| 19565 |
|
|
|
| 19566 |
|
|
VD1_hilo_37_iv_0_4[50] = VD1_un59_hilo_add19 & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add18 # !VD1_un59_hilo_add19 & VD1_hilo_37_iv_0_a6_1_0[40] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add18;
|
| 19567 |
|
|
|
| 19568 |
|
|
|
| 19569 |
|
|
--VD1_hilo_37_iv_0_5[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[50]
|
| 19570 |
|
|
--operation mode is normal
|
| 19571 |
|
|
|
| 19572 |
|
|
VD1_hilo_37_iv_0_5[50] = VD1_hilo_37_iv_0_1[50] # VD1_hilo_37_iv_0_5_a[50] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add19;
|
| 19573 |
|
|
|
| 19574 |
|
|
|
| 19575 |
|
|
--VD1_hilo_37_iv_0_a[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[50]
|
| 19576 |
|
|
--operation mode is normal
|
| 19577 |
|
|
|
| 19578 |
|
|
VD1_hilo_37_iv_0_a[50] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_18 # !VD1_hilo_24_add18 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_18;
|
| 19579 |
|
|
|
| 19580 |
|
|
|
| 19581 |
|
|
--PD1_a_o_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[18]
|
| 19582 |
|
|
--operation mode is normal
|
| 19583 |
|
|
|
| 19584 |
|
|
PD1_a_o_a[18] = SC1_muxa_ctl_o_1 & !FB1_r32_o_18 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_18;
|
| 19585 |
|
|
|
| 19586 |
|
|
|
| 19587 |
|
|
--PD1_a_o_3_Z[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[18]
|
| 19588 |
|
|
--operation mode is normal
|
| 19589 |
|
|
|
| 19590 |
|
|
PD1_a_o_3_Z[18] = PD1_a_o_3_s[0] & SD1_r32_o_18 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[18];
|
| 19591 |
|
|
|
| 19592 |
|
|
|
| 19593 |
|
|
--TD1_un1_b_1_combout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[18]
|
| 19594 |
|
|
--operation mode is normal
|
| 19595 |
|
|
|
| 19596 |
|
|
TD1_un1_b_1_combout[18] = TD1_sum13_0_a2 $ !VD1_b_o_iv_18;
|
| 19597 |
|
|
|
| 19598 |
|
|
|
| 19599 |
|
|
--UD1_shift_out_87_d_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[26]
|
| 19600 |
|
|
--operation mode is normal
|
| 19601 |
|
|
|
| 19602 |
|
|
UD1_shift_out_87_d_a[26] = PD1_a_o_1 & !UD1_shift_out_36_0 # !PD1_a_o_1 & !VD1_b_o_iv_30;
|
| 19603 |
|
|
|
| 19604 |
|
|
|
| 19605 |
|
|
--UD1_shift_out_80[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[26]
|
| 19606 |
|
|
--operation mode is normal
|
| 19607 |
|
|
|
| 19608 |
|
|
UD1_shift_out_80[26] = PD1_a_o_2 & UD1_shift_out_80_a[26] & VD1_b_o_iv_31 # !UD1_shift_out_80_a[26] & UD1_shift_out_36_0 # !PD1_a_o_2 & !UD1_shift_out_80_a[26];
|
| 19609 |
|
|
|
| 19610 |
|
|
|
| 19611 |
|
|
--UD1_shift_out_84_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[26]
|
| 19612 |
|
|
--operation mode is normal
|
| 19613 |
|
|
|
| 19614 |
|
|
UD1_shift_out_84_a[26] = PD1_a_o_4 & !UD1_shift_out_77[10] # !PD1_a_o_4 & !UD1_shift_out_77[26];
|
| 19615 |
|
|
|
| 19616 |
|
|
|
| 19617 |
|
|
--VD1_hilo_37_iv_0_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[26]
|
| 19618 |
|
|
--operation mode is normal
|
| 19619 |
|
|
|
| 19620 |
|
|
VD1_hilo_37_iv_0_a[26] = VD1_hilo_25 & !VD1_hilo_2_sqmuxa & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_27 # !VD1_hilo_25 & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_27;
|
| 19621 |
|
|
|
| 19622 |
|
|
|
| 19623 |
|
|
--VD1_hilo_37_iv_0_0[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[26]
|
| 19624 |
|
|
--operation mode is normal
|
| 19625 |
|
|
|
| 19626 |
|
|
VD1_hilo_37_iv_0_0[26] = VD1_hilo_26 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[26] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_26 & VD1_un134_hilo_combout[26] & VD1_hilo_37_iv_0_a3_0[0];
|
| 19627 |
|
|
|
| 19628 |
|
|
|
| 19629 |
|
|
--VD1_hilo_37_iv_0_1[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[58]
|
| 19630 |
|
|
--operation mode is normal
|
| 19631 |
|
|
|
| 19632 |
|
|
VD1_hilo_37_iv_0_1[58] = VD1_hilo_37_iv_0_1_a[58] # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add26;
|
| 19633 |
|
|
|
| 19634 |
|
|
|
| 19635 |
|
|
--VD1_hilo_37_iv_0_o3_1_0_1[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1_0_1[58]
|
| 19636 |
|
|
--operation mode is normal
|
| 19637 |
|
|
|
| 19638 |
|
|
VD1_hilo_37_iv_0_o3_1_0_1[58] = VD1_hilo_37_iv_0_o3_1_0_1_1[58] # VD1_hilo_37_iv_0_a3[57] # VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_26;
|
| 19639 |
|
|
|
| 19640 |
|
|
|
| 19641 |
|
|
--VD1_hilo_37_iv_0_o3[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3[58]
|
| 19642 |
|
|
--operation mode is normal
|
| 19643 |
|
|
|
| 19644 |
|
|
VD1_hilo_37_iv_0_o3[58] = VD1_hilo_37_iv_0_o3_a[58] # !VD1_hilo_33_1[64] & VD1_hilo_37_iv_0_o3_1_0_1[58] # !VD1_hilo_58;
|
| 19645 |
|
|
|
| 19646 |
|
|
|
| 19647 |
|
|
--PD1_a_o_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[26]
|
| 19648 |
|
|
--operation mode is normal
|
| 19649 |
|
|
|
| 19650 |
|
|
PD1_a_o_a[26] = SC1_muxa_ctl_o_1 & !FB1_r32_o_26 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_26;
|
| 19651 |
|
|
|
| 19652 |
|
|
|
| 19653 |
|
|
--PD1_a_o_3_Z[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[26]
|
| 19654 |
|
|
--operation mode is normal
|
| 19655 |
|
|
|
| 19656 |
|
|
PD1_a_o_3_Z[26] = PD1_a_o_3_s[0] & SD1_r32_o_26 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[26];
|
| 19657 |
|
|
|
| 19658 |
|
|
|
| 19659 |
|
|
--TD1_un1_b_1_combout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[26]
|
| 19660 |
|
|
--operation mode is normal
|
| 19661 |
|
|
|
| 19662 |
|
|
TD1_un1_b_1_combout[26] = TD1_sum13_0_a2 $ !VD1_b_o_iv_26;
|
| 19663 |
|
|
|
| 19664 |
|
|
|
| 19665 |
|
|
--UD1_shift_out_87_d_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[27]
|
| 19666 |
|
|
--operation mode is normal
|
| 19667 |
|
|
|
| 19668 |
|
|
UD1_shift_out_87_d_a[27] = PD1_a_o_1 & !UD1_shift_out_36_0 # !PD1_a_o_1 & !VD1_b_o_iv_31;
|
| 19669 |
|
|
|
| 19670 |
|
|
|
| 19671 |
|
|
--UD1_shift_out_80[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[27]
|
| 19672 |
|
|
--operation mode is normal
|
| 19673 |
|
|
|
| 19674 |
|
|
UD1_shift_out_80[27] = PD1_a_o_2 & !UD1_shift_out_80_a[27] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_80_a[27] # !PD1_a_o_1 & VD1_b_o_iv_28;
|
| 19675 |
|
|
|
| 19676 |
|
|
|
| 19677 |
|
|
--UD1_shift_out_77[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[27]
|
| 19678 |
|
|
--operation mode is normal
|
| 19679 |
|
|
|
| 19680 |
|
|
UD1_shift_out_77[27] = PD1_a_o_2 & UD1_shift_out_85_d[19] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[19] # !PD1_a_o_1 & !UD1_shift_out_77_a[27];
|
| 19681 |
|
|
|
| 19682 |
|
|
|
| 19683 |
|
|
--UD1_shift_out_75[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[27]
|
| 19684 |
|
|
--operation mode is normal
|
| 19685 |
|
|
|
| 19686 |
|
|
UD1_shift_out_75[27] = PD1_a_o_3 & UD1_shift_out_77[11] # !PD1_a_o_3 & !UD1_shift_out_84_a[19];
|
| 19687 |
|
|
|
| 19688 |
|
|
|
| 19689 |
|
|
--VD1_hilo_37_iv_0[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[27]
|
| 19690 |
|
|
--operation mode is normal
|
| 19691 |
|
|
|
| 19692 |
|
|
VD1_hilo_37_iv_0[27] = VD1_hilo_28 & VD1_hilo_1_sqmuxa_1 # VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[27] # !VD1_hilo_28 & VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[27];
|
| 19693 |
|
|
|
| 19694 |
|
|
|
| 19695 |
|
|
--VD1_hilo_8_Z[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[27]
|
| 19696 |
|
|
--operation mode is normal
|
| 19697 |
|
|
|
| 19698 |
|
|
VD1_hilo_8_Z[27] = RC1_alu_func_o_0 & VD1_hilo_27 # !RC1_alu_func_o_0 & PD1_a_o_27;
|
| 19699 |
|
|
|
| 19700 |
|
|
|
| 19701 |
|
|
--VD1_hilo_37_iv_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[27]
|
| 19702 |
|
|
--operation mode is normal
|
| 19703 |
|
|
|
| 19704 |
|
|
VD1_hilo_37_iv_a[27] = VD1_hilo_26 & !VD1_hilo_2_sqmuxa & !PD1_a_o_27 # !VD1_addnop2109_0_a2 # !VD1_hilo_26 & !PD1_a_o_27 # !VD1_addnop2109_0_a2;
|
| 19705 |
|
|
|
| 19706 |
|
|
|
| 19707 |
|
|
--VD1_hilo_37_iv_0_a[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[59]
|
| 19708 |
|
|
--operation mode is normal
|
| 19709 |
|
|
|
| 19710 |
|
|
VD1_hilo_37_iv_0_a[59] = !VD1_hilo_37_iv_0_6[59] & VD1_hilo_24_add27 # !VD1_hilo_2_sqmuxa;
|
| 19711 |
|
|
|
| 19712 |
|
|
|
| 19713 |
|
|
--PD1_a_o_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[27]
|
| 19714 |
|
|
--operation mode is normal
|
| 19715 |
|
|
|
| 19716 |
|
|
PD1_a_o_a[27] = SC1_muxa_ctl_o_1 & !FB1_r32_o_27 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_27;
|
| 19717 |
|
|
|
| 19718 |
|
|
|
| 19719 |
|
|
--PD1_a_o_3_Z[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[27]
|
| 19720 |
|
|
--operation mode is normal
|
| 19721 |
|
|
|
| 19722 |
|
|
PD1_a_o_3_Z[27] = PD1_a_o_3_s[0] & SD1_r32_o_27 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[27];
|
| 19723 |
|
|
|
| 19724 |
|
|
|
| 19725 |
|
|
--TD1_un1_b_1_combout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[27]
|
| 19726 |
|
|
--operation mode is normal
|
| 19727 |
|
|
|
| 19728 |
|
|
TD1_un1_b_1_combout[27] = TD1_sum13_0_a2 $ !VD1_b_o_iv_27;
|
| 19729 |
|
|
|
| 19730 |
|
|
|
| 19731 |
|
|
--UD1_shift_out_87_d_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[28]
|
| 19732 |
|
|
--operation mode is normal
|
| 19733 |
|
|
|
| 19734 |
|
|
UD1_shift_out_87_d_a[28] = PD1_a_o_2 & !UD1_shift_out_36_0 # !PD1_a_o_2 & !VD1_b_o_iv_29;
|
| 19735 |
|
|
|
| 19736 |
|
|
|
| 19737 |
|
|
--UD1_shift_out_68[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[28]
|
| 19738 |
|
|
--operation mode is normal
|
| 19739 |
|
|
|
| 19740 |
|
|
UD1_shift_out_68[28] = PD1_a_o_0 & VD1_b_o_iv_25 # !PD1_a_o_0 & VD1_b_o_iv_26;
|
| 19741 |
|
|
|
| 19742 |
|
|
|
| 19743 |
|
|
--PD1_a_o_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[28]
|
| 19744 |
|
|
--operation mode is normal
|
| 19745 |
|
|
|
| 19746 |
|
|
PD1_a_o_a[28] = SC1_muxa_ctl_o_1 & !FB1_r32_o_28 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_28;
|
| 19747 |
|
|
|
| 19748 |
|
|
|
| 19749 |
|
|
--PD1_a_o_3_Z[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[28]
|
| 19750 |
|
|
--operation mode is normal
|
| 19751 |
|
|
|
| 19752 |
|
|
PD1_a_o_3_Z[28] = PD1_a_o_3_s[0] & SD1_r32_o_28 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[28];
|
| 19753 |
|
|
|
| 19754 |
|
|
|
| 19755 |
|
|
--TD1_alu_out_9_a2_1_1_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_9_a2_1_1_0
|
| 19756 |
|
|
--operation mode is normal
|
| 19757 |
|
|
|
| 19758 |
|
|
TD1_alu_out_9_a2_1_1_0 = !RC1_alu_func_o_3 & TD1_m107 & RC1_alu_func_o_2 $ !RC1_alu_func_o_0;
|
| 19759 |
|
|
|
| 19760 |
|
|
|
| 19761 |
|
|
--MD1_c_0_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[28]
|
| 19762 |
|
|
--operation mode is normal
|
| 19763 |
|
|
|
| 19764 |
|
|
MD1_c_0_a[28] = VD1_un24_res & !VD1_hilo_60 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_28;
|
| 19765 |
|
|
|
| 19766 |
|
|
|
| 19767 |
|
|
--UD1_shift_out_75[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[28]
|
| 19768 |
|
|
--operation mode is normal
|
| 19769 |
|
|
|
| 19770 |
|
|
UD1_shift_out_75[28] = PD1_a_o_3 & UD1_shift_out_75_a[28] & UD1_shift_out_45[28] # !UD1_shift_out_75_a[28] & UD1_shift_out_43[28] # !PD1_a_o_3 & !UD1_shift_out_75_a[28];
|
| 19771 |
|
|
|
| 19772 |
|
|
|
| 19773 |
|
|
--UD1_shift_out_77[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[28]
|
| 19774 |
|
|
--operation mode is normal
|
| 19775 |
|
|
|
| 19776 |
|
|
UD1_shift_out_77[28] = PD1_a_o_2 & !UD1_shift_out_77_a[28] # !PD1_a_o_2 & UD1_shift_out_77_a[28] & UD1_shift_out_68[22] # !UD1_shift_out_77_a[28] & UD1_shift_out_68[20];
|
| 19777 |
|
|
|
| 19778 |
|
|
|
| 19779 |
|
|
--UD1_shift_out_84_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[29]
|
| 19780 |
|
|
--operation mode is normal
|
| 19781 |
|
|
|
| 19782 |
|
|
UD1_shift_out_84_a[29] = PD1_a_o_2 & !UD1_shift_out_85_d[21] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[21] # !PD1_a_o_1 & !UD1_shift_out_68[23];
|
| 19783 |
|
|
|
| 19784 |
|
|
|
| 19785 |
|
|
--UD1_shift_out_75[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[29]
|
| 19786 |
|
|
--operation mode is normal
|
| 19787 |
|
|
|
| 19788 |
|
|
UD1_shift_out_75[29] = PD1_a_o_3 & UD1_shift_out_63[21] # !PD1_a_o_3 & UD1_shift_out_77[21];
|
| 19789 |
|
|
|
| 19790 |
|
|
|
| 19791 |
|
|
--VD1_hilo_37_iv_0_a[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[61]
|
| 19792 |
|
|
--operation mode is normal
|
| 19793 |
|
|
|
| 19794 |
|
|
VD1_hilo_37_iv_0_a[61] = !VD1_hilo_37_iv_0_6[61] & VD1_hilo_24_add29 # !VD1_hilo_2_sqmuxa;
|
| 19795 |
|
|
|
| 19796 |
|
|
|
| 19797 |
|
|
--UD1_shift_out_80_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[13]
|
| 19798 |
|
|
--operation mode is normal
|
| 19799 |
|
|
|
| 19800 |
|
|
UD1_shift_out_80_a[13] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_16 # !PD1_a_o_1 & !VD1_b_o_iv_14;
|
| 19801 |
|
|
|
| 19802 |
|
|
|
| 19803 |
|
|
--UD1_shift_out_48_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48_a[29]
|
| 19804 |
|
|
--operation mode is normal
|
| 19805 |
|
|
|
| 19806 |
|
|
UD1_shift_out_48_a[29] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_6 # !PD1_a_o_0 & !VD1_b_o_iv_7 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 19807 |
|
|
|
| 19808 |
|
|
|
| 19809 |
|
|
--UD1_shift_out_45_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45_a[29]
|
| 19810 |
|
|
--operation mode is normal
|
| 19811 |
|
|
|
| 19812 |
|
|
UD1_shift_out_45_a[29] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_2 # !PD1_a_o_0 & !VD1_b_o_iv_3 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 19813 |
|
|
|
| 19814 |
|
|
|
| 19815 |
|
|
--VD1_un134_hilo_combout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[13]
|
| 19816 |
|
|
--operation mode is arithmetic
|
| 19817 |
|
|
|
| 19818 |
|
|
VD1_un134_hilo_combout[13]_carry_eqn = VD1_un134_hilo_cout[11];
|
| 19819 |
|
|
VD1_un134_hilo_combout[13] = VD1_hilo_13 $ (VD1_hilo_12 & !VD1_un134_hilo_combout[13]_carry_eqn);
|
| 19820 |
|
|
|
| 19821 |
|
|
--VD1_un134_hilo_cout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[13]
|
| 19822 |
|
|
--operation mode is arithmetic
|
| 19823 |
|
|
|
| 19824 |
|
|
VD1_un134_hilo_cout[13] = CARRY(VD1_hilo_12 & VD1_hilo_13 & !VD1_un134_hilo_cout[11]);
|
| 19825 |
|
|
|
| 19826 |
|
|
|
| 19827 |
|
|
--VD1_hilo_33_i_m[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[45]
|
| 19828 |
|
|
--operation mode is normal
|
| 19829 |
|
|
|
| 19830 |
|
|
VD1_hilo_33_i_m[45] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[45] # !VD1_hilo_33_1[64] & !VD1_hilo_45;
|
| 19831 |
|
|
|
| 19832 |
|
|
|
| 19833 |
|
|
--VD1_hilo_37_iv_2_a[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[45]
|
| 19834 |
|
|
--operation mode is normal
|
| 19835 |
|
|
|
| 19836 |
|
|
VD1_hilo_37_iv_2_a[45] = VD1_hilo_13 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add13 # !VD1_hilo_13 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add13;
|
| 19837 |
|
|
|
| 19838 |
|
|
|
| 19839 |
|
|
--VD1_hilo_22_Z[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[45]
|
| 19840 |
|
|
--operation mode is normal
|
| 19841 |
|
|
|
| 19842 |
|
|
VD1_hilo_22_Z[45] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[45] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[45] # !VD1_sign & !VD1_hilo_22_a[45];
|
| 19843 |
|
|
|
| 19844 |
|
|
|
| 19845 |
|
|
--RD1_r32_o_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_13
|
| 19846 |
|
|
--operation mode is arithmetic
|
| 19847 |
|
|
|
| 19848 |
|
|
RD1_r32_o_13_carry_eqn = RD1_r32_o_cout[11];
|
| 19849 |
|
|
RD1_r32_o_13_lut_out = KB1_r32_o_13 $ (KB1_r32_o_12 & RD1_r32_o_13_carry_eqn);
|
| 19850 |
|
|
RD1_r32_o_13 = DFFEAS(RD1_r32_o_13_lut_out, E1__clk0, VCC, , , , , , );
|
| 19851 |
|
|
|
| 19852 |
|
|
--RD1_r32_o_cout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[13]
|
| 19853 |
|
|
--operation mode is arithmetic
|
| 19854 |
|
|
|
| 19855 |
|
|
RD1_r32_o_cout[13] = CARRY(!RD1_r32_o_cout[11] # !KB1_r32_o_13 # !KB1_r32_o_12);
|
| 19856 |
|
|
|
| 19857 |
|
|
|
| 19858 |
|
|
--SD1_r32_o_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_13
|
| 19859 |
|
|
--operation mode is normal
|
| 19860 |
|
|
|
| 19861 |
|
|
SD1_r32_o_13_lut_out = KB1_r32_o_13;
|
| 19862 |
|
|
SD1_r32_o_13 = DFFEAS(SD1_r32_o_13_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 19863 |
|
|
|
| 19864 |
|
|
|
| 19865 |
|
|
--PD1_a_o_3_d[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[13]
|
| 19866 |
|
|
--operation mode is normal
|
| 19867 |
|
|
|
| 19868 |
|
|
PD1_a_o_3_d[13] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_13 # !PD1_un6_a_o & !PD1_a_o_3_d_a[13] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[13];
|
| 19869 |
|
|
|
| 19870 |
|
|
|
| 19871 |
|
|
--TD1_un1_b_1_combout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[12]
|
| 19872 |
|
|
--operation mode is normal
|
| 19873 |
|
|
|
| 19874 |
|
|
TD1_un1_b_1_combout[12] = TD1_sum13_0_a2 $ !VD1_b_o_iv_12;
|
| 19875 |
|
|
|
| 19876 |
|
|
|
| 19877 |
|
|
--VD1_hilo_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_28
|
| 19878 |
|
|
--operation mode is normal
|
| 19879 |
|
|
|
| 19880 |
|
|
VD1_hilo_28_lut_out = VD1_hilo_37_iv_0_0[28] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_28 # !VD1_hilo_37_iv_0_a[28];
|
| 19881 |
|
|
VD1_hilo_28 = DFFEAS(VD1_hilo_28_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 19882 |
|
|
|
| 19883 |
|
|
|
| 19884 |
|
|
--VD1_un134_hilo_combout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[29]
|
| 19885 |
|
|
--operation mode is arithmetic
|
| 19886 |
|
|
|
| 19887 |
|
|
VD1_un134_hilo_combout[29]_carry_eqn = VD1_un134_hilo_cout[27];
|
| 19888 |
|
|
VD1_un134_hilo_combout[29] = VD1_hilo_29 $ (VD1_hilo_28 & !VD1_un134_hilo_combout[29]_carry_eqn);
|
| 19889 |
|
|
|
| 19890 |
|
|
--VD1_un134_hilo_cout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[29]
|
| 19891 |
|
|
--operation mode is arithmetic
|
| 19892 |
|
|
|
| 19893 |
|
|
VD1_un134_hilo_cout[29] = CARRY(VD1_hilo_28 & VD1_hilo_29 & !VD1_un134_hilo_cout[27]);
|
| 19894 |
|
|
|
| 19895 |
|
|
|
| 19896 |
|
|
--VD1_un134_hilo_combout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[26]
|
| 19897 |
|
|
--operation mode is arithmetic
|
| 19898 |
|
|
|
| 19899 |
|
|
VD1_un134_hilo_combout[26]_carry_eqn = VD1_un134_hilo_cout[24];
|
| 19900 |
|
|
VD1_un134_hilo_combout[26] = VD1_hilo_26 $ (VD1_un134_hilo_combout[26]_carry_eqn);
|
| 19901 |
|
|
|
| 19902 |
|
|
--VD1_un134_hilo_cout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[26]
|
| 19903 |
|
|
--operation mode is arithmetic
|
| 19904 |
|
|
|
| 19905 |
|
|
VD1_un134_hilo_cout[26] = CARRY(!VD1_un134_hilo_cout[24] # !VD1_hilo_27 # !VD1_hilo_26);
|
| 19906 |
|
|
|
| 19907 |
|
|
|
| 19908 |
|
|
--RD1_r32_o_0_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_28
|
| 19909 |
|
|
--operation mode is arithmetic
|
| 19910 |
|
|
|
| 19911 |
|
|
RD1_r32_o_0_28_carry_eqn = RD1_r32_o_cout[26];
|
| 19912 |
|
|
RD1_r32_o_0_28_lut_out = KB1_r32_o_28 $ (RD1_r32_o_0_28_carry_eqn);
|
| 19913 |
|
|
RD1_r32_o_0_28 = DFFEAS(RD1_r32_o_0_28_lut_out, E1__clk0, VCC, , , , , , );
|
| 19914 |
|
|
|
| 19915 |
|
|
--RD1_r32_o_cout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[28]
|
| 19916 |
|
|
--operation mode is arithmetic
|
| 19917 |
|
|
|
| 19918 |
|
|
RD1_r32_o_cout[28] = CARRY(!RD1_r32_o_cout[26] # !KB1_r32_o_29 # !KB1_r32_o_28);
|
| 19919 |
|
|
|
| 19920 |
|
|
|
| 19921 |
|
|
--PD1_a_o_3_d_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[30]
|
| 19922 |
|
|
--operation mode is normal
|
| 19923 |
|
|
|
| 19924 |
|
|
PD1_a_o_3_d_a[30] = PD1_a_o_sn_m2 & !PB1_r32_o_30 # !PD1_a_o_sn_m2 & !AB1_r32_o_28;
|
| 19925 |
|
|
|
| 19926 |
|
|
|
| 19927 |
|
|
--VD1_un1_op2_reged_1_combout[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[30]
|
| 19928 |
|
|
--operation mode is normal
|
| 19929 |
|
|
|
| 19930 |
|
|
VD1_un1_op2_reged_1_combout[30] = VD1_eqop2_2_32 & VD1_op2_reged[30] # !VD1_eqop2_2_32 & VD1_nop2_reged[30];
|
| 19931 |
|
|
|
| 19932 |
|
|
|
| 19933 |
|
|
--VD1_hilo_24_add29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add29
|
| 19934 |
|
|
--operation mode is arithmetic
|
| 19935 |
|
|
|
| 19936 |
|
|
VD1_hilo_24_add29_carry_eqn = VD1_hilo_24_carry_28;
|
| 19937 |
|
|
VD1_hilo_24_add29 = VD1_hilo_60 $ VD1_un1_op2_reged_1_combout[29] $ VD1_hilo_24_add29_carry_eqn;
|
| 19938 |
|
|
|
| 19939 |
|
|
--VD1_hilo_24_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_29
|
| 19940 |
|
|
--operation mode is arithmetic
|
| 19941 |
|
|
|
| 19942 |
|
|
VD1_hilo_24_carry_29 = CARRY(VD1_hilo_60 & !VD1_un1_op2_reged_1_combout[29] & !VD1_hilo_24_carry_28 # !VD1_hilo_60 & !VD1_hilo_24_carry_28 # !VD1_un1_op2_reged_1_combout[29]);
|
| 19943 |
|
|
|
| 19944 |
|
|
|
| 19945 |
|
|
--VD1_hilo_37_iv_0_a5_0[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a5_0[62]
|
| 19946 |
|
|
--operation mode is normal
|
| 19947 |
|
|
|
| 19948 |
|
|
VD1_hilo_37_iv_0_a5_0[62] = !VD1_hilo_62 & VD1_hilo_37_iv_0_a3_1[62];
|
| 19949 |
|
|
|
| 19950 |
|
|
|
| 19951 |
|
|
--VD1_hilo_37_iv_0_0[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[62]
|
| 19952 |
|
|
--operation mode is normal
|
| 19953 |
|
|
|
| 19954 |
|
|
VD1_hilo_37_iv_0_0[62] = VD1_hilo_30 & !VD1_un59_hilo_add30 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_hilo_30 & VD1_hilo_0_sqmuxa # !VD1_un59_hilo_add30 & VD1_hilo_37_iv_0_a3_2[62];
|
| 19955 |
|
|
|
| 19956 |
|
|
|
| 19957 |
|
|
--VD1_un50_hilo_add30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add30
|
| 19958 |
|
|
--operation mode is arithmetic
|
| 19959 |
|
|
|
| 19960 |
|
|
VD1_un50_hilo_add30_carry_eqn = VD1_un50_hilo_carry_29;
|
| 19961 |
|
|
VD1_un50_hilo_add30 = VD1_hilo_62 $ VD1_nop2_reged[30] $ !VD1_un50_hilo_add30_carry_eqn;
|
| 19962 |
|
|
|
| 19963 |
|
|
--VD1_un50_hilo_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_30
|
| 19964 |
|
|
--operation mode is arithmetic
|
| 19965 |
|
|
|
| 19966 |
|
|
VD1_un50_hilo_carry_30 = CARRY(VD1_hilo_62 & VD1_nop2_reged[30] # !VD1_un50_hilo_carry_29 # !VD1_hilo_62 & VD1_nop2_reged[30] & !VD1_un50_hilo_carry_29);
|
| 19967 |
|
|
|
| 19968 |
|
|
|
| 19969 |
|
|
--VD1_un50_hilo_add31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add31
|
| 19970 |
|
|
--operation mode is arithmetic
|
| 19971 |
|
|
|
| 19972 |
|
|
VD1_un50_hilo_add31_carry_eqn = VD1_un50_hilo_carry_30;
|
| 19973 |
|
|
VD1_un50_hilo_add31 = VD1_hilo_63 $ VD1_nop2_reged[31] $ VD1_un50_hilo_add31_carry_eqn;
|
| 19974 |
|
|
|
| 19975 |
|
|
--VD1_un50_hilo_carry_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_31
|
| 19976 |
|
|
--operation mode is arithmetic
|
| 19977 |
|
|
|
| 19978 |
|
|
VD1_un50_hilo_carry_31 = CARRY(VD1_hilo_63 & !VD1_nop2_reged[31] & !VD1_un50_hilo_carry_30 # !VD1_hilo_63 & !VD1_un50_hilo_carry_30 # !VD1_nop2_reged[31]);
|
| 19979 |
|
|
|
| 19980 |
|
|
|
| 19981 |
|
|
--VD1_un59_hilo_add30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add30
|
| 19982 |
|
|
--operation mode is arithmetic
|
| 19983 |
|
|
|
| 19984 |
|
|
VD1_un59_hilo_add30_carry_eqn = VD1_un59_hilo_carry_29;
|
| 19985 |
|
|
VD1_un59_hilo_add30 = VD1_hilo_62 $ VD1_op2_reged[30] $ !VD1_un59_hilo_add30_carry_eqn;
|
| 19986 |
|
|
|
| 19987 |
|
|
--VD1_un59_hilo_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_30
|
| 19988 |
|
|
--operation mode is arithmetic
|
| 19989 |
|
|
|
| 19990 |
|
|
VD1_un59_hilo_carry_30 = CARRY(VD1_hilo_62 & VD1_op2_reged[30] # !VD1_un59_hilo_carry_29 # !VD1_hilo_62 & VD1_op2_reged[30] & !VD1_un59_hilo_carry_29);
|
| 19991 |
|
|
|
| 19992 |
|
|
|
| 19993 |
|
|
--UD1_shift_out_77[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[30]
|
| 19994 |
|
|
--operation mode is normal
|
| 19995 |
|
|
|
| 19996 |
|
|
UD1_shift_out_77[30] = PD1_a_o_2 & UD1_shift_out_85_d[22] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[22] # !PD1_a_o_1 & UD1_shift_out_68[24];
|
| 19997 |
|
|
|
| 19998 |
|
|
|
| 19999 |
|
|
--UD1_shift_out_84_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[30]
|
| 20000 |
|
|
--operation mode is normal
|
| 20001 |
|
|
|
| 20002 |
|
|
UD1_shift_out_84_a[30] = PD1_a_o_3 & !UD1_shift_out_63[22] # !PD1_a_o_3 & !UD1_shift_out_63[30];
|
| 20003 |
|
|
|
| 20004 |
|
|
|
| 20005 |
|
|
--UD1_shift_out_89_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[30]
|
| 20006 |
|
|
--operation mode is normal
|
| 20007 |
|
|
|
| 20008 |
|
|
UD1_shift_out_89_a[30] = PD1_a_o_0 & UD1_shift_out_63_a[17] & !VD1_b_o_iv_31 # !UD1_shift_out_63_a[17] & !UD1_shift_out_36_0 # !PD1_a_o_0 & !UD1_shift_out_36_0;
|
| 20009 |
|
|
|
| 20010 |
|
|
|
| 20011 |
|
|
--UD1_shift_out_85[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[30]
|
| 20012 |
|
|
--operation mode is normal
|
| 20013 |
|
|
|
| 20014 |
|
|
UD1_shift_out_85[30] = PD1_a_o_2 & UD1_shift_out_85_c[30] & UD1_shift_out_68[26] # !UD1_shift_out_85_c[30] & UD1_shift_out_68[28] # !PD1_a_o_2 & UD1_shift_out_85_c[30];
|
| 20015 |
|
|
|
| 20016 |
|
|
|
| 20017 |
|
|
--UD1_shift_out_87_d_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[12]
|
| 20018 |
|
|
--operation mode is normal
|
| 20019 |
|
|
|
| 20020 |
|
|
UD1_shift_out_87_d_a[12] = PD1_a_o_1 & !VD1_b_o_iv_18 # !PD1_a_o_1 & !VD1_b_o_iv_16;
|
| 20021 |
|
|
|
| 20022 |
|
|
|
| 20023 |
|
|
--UD1_shift_out_80[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[12]
|
| 20024 |
|
|
--operation mode is normal
|
| 20025 |
|
|
|
| 20026 |
|
|
UD1_shift_out_80[12] = PD1_a_o_2 & UD1_shift_out_80_a[12] & VD1_b_o_iv_17 # !UD1_shift_out_80_a[12] & VD1_b_o_iv_19 # !PD1_a_o_2 & !UD1_shift_out_80_a[12];
|
| 20027 |
|
|
|
| 20028 |
|
|
|
| 20029 |
|
|
--UD1_shift_out_77_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[18]
|
| 20030 |
|
|
--operation mode is normal
|
| 20031 |
|
|
|
| 20032 |
|
|
UD1_shift_out_77_a[18] = PD1_a_o_0 & !VD1_b_o_iv_9 # !PD1_a_o_0 & !VD1_b_o_iv_10;
|
| 20033 |
|
|
|
| 20034 |
|
|
|
| 20035 |
|
|
--UD1_shift_out_79[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[12]
|
| 20036 |
|
|
--operation mode is normal
|
| 20037 |
|
|
|
| 20038 |
|
|
UD1_shift_out_79[12] = PD1_a_o_1 & UD1_shift_out_79_a[12] & VD1_b_o_iv_22 # !UD1_shift_out_79_a[12] & VD1_b_o_iv_23 # !PD1_a_o_1 & !UD1_shift_out_79_a[12];
|
| 20039 |
|
|
|
| 20040 |
|
|
|
| 20041 |
|
|
--VD1_hilo_37_iv_0_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[12]
|
| 20042 |
|
|
--operation mode is normal
|
| 20043 |
|
|
|
| 20044 |
|
|
VD1_hilo_37_iv_0_a[12] = VD1_hilo_13 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_11 # !VD1_hilo_13 & !VD1_hilo_2_sqmuxa # !VD1_hilo_11;
|
| 20045 |
|
|
|
| 20046 |
|
|
|
| 20047 |
|
|
--VD1_hilo_37_iv_0_0[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[12]
|
| 20048 |
|
|
--operation mode is normal
|
| 20049 |
|
|
|
| 20050 |
|
|
VD1_hilo_37_iv_0_0[12] = VD1_hilo_12 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[12] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_12 & VD1_un134_hilo_combout[12] & VD1_hilo_37_iv_0_a3_0[0];
|
| 20051 |
|
|
|
| 20052 |
|
|
|
| 20053 |
|
|
--VD1_hilo_37_iv_0_o3[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3[44]
|
| 20054 |
|
|
--operation mode is normal
|
| 20055 |
|
|
|
| 20056 |
|
|
VD1_hilo_37_iv_0_o3[44] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add13 # !VD1_hilo_24_add12 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add13;
|
| 20057 |
|
|
|
| 20058 |
|
|
|
| 20059 |
|
|
--VD1_hilo_37_iv_0_o2_3_0[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o2_3_0[44]
|
| 20060 |
|
|
--operation mode is normal
|
| 20061 |
|
|
|
| 20062 |
|
|
VD1_hilo_37_iv_0_o2_3_0[44] = VD1_addnop2109_0_a2 # VD1_hilo_37_iv_0_o3_0[44];
|
| 20063 |
|
|
|
| 20064 |
|
|
|
| 20065 |
|
|
--VD1_hilo_37_iv_0_a[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[44]
|
| 20066 |
|
|
--operation mode is normal
|
| 20067 |
|
|
|
| 20068 |
|
|
VD1_hilo_37_iv_0_a[44] = !VD1_hilo_37_iv_0_2[44] & !VD1_hilo_37_iv_0_o3_0[44] & PD1_a_o_12 # !VD1_hilo_37_iv_0_a3_1[0];
|
| 20069 |
|
|
|
| 20070 |
|
|
|
| 20071 |
|
|
--PD1_a_o_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[12]
|
| 20072 |
|
|
--operation mode is normal
|
| 20073 |
|
|
|
| 20074 |
|
|
PD1_a_o_a[12] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_12 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_12;
|
| 20075 |
|
|
|
| 20076 |
|
|
|
| 20077 |
|
|
--PD1_a_o_3_Z[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[12]
|
| 20078 |
|
|
--operation mode is normal
|
| 20079 |
|
|
|
| 20080 |
|
|
PD1_a_o_3_Z[12] = PD1_a_o_3_s[0] & SD1_r32_o_12 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[12];
|
| 20081 |
|
|
|
| 20082 |
|
|
|
| 20083 |
|
|
--YB1_dmem_ctl_2_0_0_a[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_a[3]
|
| 20084 |
|
|
--operation mode is normal
|
| 20085 |
|
|
|
| 20086 |
|
|
YB1_dmem_ctl_2_0_0_a[3] = KE1_q_a[2] & !KE1_q_a[5] & !KE1_q_a[6] & !YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0];
|
| 20087 |
|
|
|
| 20088 |
|
|
|
| 20089 |
|
|
--UD1_shift_out_87_d_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[24]
|
| 20090 |
|
|
--operation mode is normal
|
| 20091 |
|
|
|
| 20092 |
|
|
UD1_shift_out_87_d_a[24] = PD1_a_o_1 & !VD1_b_o_iv_30 # !PD1_a_o_1 & !VD1_b_o_iv_28;
|
| 20093 |
|
|
|
| 20094 |
|
|
|
| 20095 |
|
|
--UD1_shift_out_80[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[24]
|
| 20096 |
|
|
--operation mode is normal
|
| 20097 |
|
|
|
| 20098 |
|
|
UD1_shift_out_80[24] = PD1_a_o_2 & UD1_shift_out_80_a[24] & VD1_b_o_iv_29 # !UD1_shift_out_80_a[24] & VD1_b_o_iv_31 # !PD1_a_o_2 & !UD1_shift_out_80_a[24];
|
| 20099 |
|
|
|
| 20100 |
|
|
|
| 20101 |
|
|
--UD1_shift_out_84_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[24]
|
| 20102 |
|
|
--operation mode is normal
|
| 20103 |
|
|
|
| 20104 |
|
|
UD1_shift_out_84_a[24] = PD1_a_o_4 & !PD1_a_o_2 & UD1_shift_out_43[28] # !PD1_a_o_4 & !UD1_shift_out_77[24];
|
| 20105 |
|
|
|
| 20106 |
|
|
|
| 20107 |
|
|
--VD1_hilo_37_iv_1[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1[24]
|
| 20108 |
|
|
--operation mode is normal
|
| 20109 |
|
|
|
| 20110 |
|
|
VD1_hilo_37_iv_1[24] = VD1_hilo_37_iv_0[24] # VD1_hilo_23 & VD1_hilo_2_sqmuxa;
|
| 20111 |
|
|
|
| 20112 |
|
|
|
| 20113 |
|
|
--VD1_hilo_37_iv_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[24]
|
| 20114 |
|
|
--operation mode is normal
|
| 20115 |
|
|
|
| 20116 |
|
|
VD1_hilo_37_iv_a[24] = RC1_alu_func_o_0 & !VD1_hilo_24 # !RC1_alu_func_o_0 & !PD1_a_o_24 # !VD1_hilo25;
|
| 20117 |
|
|
|
| 20118 |
|
|
|
| 20119 |
|
|
--VD1_hilo_37_iv_2[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[56]
|
| 20120 |
|
|
--operation mode is normal
|
| 20121 |
|
|
|
| 20122 |
|
|
VD1_hilo_37_iv_2[56] = VD1_hilo_33_i_m[56] # VD1_hilo_37_iv_2_a[56] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[56];
|
| 20123 |
|
|
|
| 20124 |
|
|
|
| 20125 |
|
|
--VD1_hilo_37_iv_a[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[56]
|
| 20126 |
|
|
--operation mode is normal
|
| 20127 |
|
|
|
| 20128 |
|
|
VD1_hilo_37_iv_a[56] = RC1_alu_func_o_0 & !PD1_a_o_24 # !RC1_alu_func_o_0 & !VD1_hilo_56;
|
| 20129 |
|
|
|
| 20130 |
|
|
|
| 20131 |
|
|
--PD1_a_o_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[24]
|
| 20132 |
|
|
--operation mode is normal
|
| 20133 |
|
|
|
| 20134 |
|
|
PD1_a_o_a[24] = SC1_muxa_ctl_o_1 & !FB1_r32_o_24 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_24;
|
| 20135 |
|
|
|
| 20136 |
|
|
|
| 20137 |
|
|
--PD1_a_o_3_Z[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[24]
|
| 20138 |
|
|
--operation mode is normal
|
| 20139 |
|
|
|
| 20140 |
|
|
PD1_a_o_3_Z[24] = PD1_a_o_3_s[0] & SD1_r32_o_24 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[24];
|
| 20141 |
|
|
|
| 20142 |
|
|
|
| 20143 |
|
|
--TD1_un1_b_1_combout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[24]
|
| 20144 |
|
|
--operation mode is normal
|
| 20145 |
|
|
|
| 20146 |
|
|
TD1_un1_b_1_combout[24] = TD1_sum13_0_a2 $ !VD1_b_o_iv_24;
|
| 20147 |
|
|
|
| 20148 |
|
|
|
| 20149 |
|
|
--UD1_shift_out_87_d_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[25]
|
| 20150 |
|
|
--operation mode is normal
|
| 20151 |
|
|
|
| 20152 |
|
|
UD1_shift_out_87_d_a[25] = PD1_a_o_1 & !VD1_b_o_iv_31 # !PD1_a_o_1 & !VD1_b_o_iv_29;
|
| 20153 |
|
|
|
| 20154 |
|
|
|
| 20155 |
|
|
--UD1_shift_out_80[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[25]
|
| 20156 |
|
|
--operation mode is normal
|
| 20157 |
|
|
|
| 20158 |
|
|
UD1_shift_out_80[25] = PD1_a_o_2 & UD1_shift_out_80_a[25] & VD1_b_o_iv_30 # !UD1_shift_out_80_a[25] & UD1_shift_out_36_0 # !PD1_a_o_2 & !UD1_shift_out_80_a[25];
|
| 20159 |
|
|
|
| 20160 |
|
|
|
| 20161 |
|
|
--UD1_shift_out_75[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[25]
|
| 20162 |
|
|
--operation mode is normal
|
| 20163 |
|
|
|
| 20164 |
|
|
UD1_shift_out_75[25] = PD1_a_o_3 & !UD1_shift_out_75_a[25] # !PD1_a_o_3 & PD1_a_o_2 & UD1_shift_out_45[29] # !PD1_a_o_2 & !UD1_shift_out_75_a[25];
|
| 20165 |
|
|
|
| 20166 |
|
|
|
| 20167 |
|
|
--UD1_shift_out_77[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[25]
|
| 20168 |
|
|
--operation mode is normal
|
| 20169 |
|
|
|
| 20170 |
|
|
UD1_shift_out_77[25] = PD1_a_o_2 & UD1_shift_out_85_d[17] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[17] # !PD1_a_o_1 & !UD1_shift_out_77_a[25];
|
| 20171 |
|
|
|
| 20172 |
|
|
|
| 20173 |
|
|
--VD1_hilo_37_iv_0_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[25]
|
| 20174 |
|
|
--operation mode is normal
|
| 20175 |
|
|
|
| 20176 |
|
|
VD1_hilo_37_iv_0_a[25] = VD1_hilo_26 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_24 # !VD1_hilo_26 & !VD1_hilo_2_sqmuxa # !VD1_hilo_24;
|
| 20177 |
|
|
|
| 20178 |
|
|
|
| 20179 |
|
|
--VD1_hilo_37_iv_0_0[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[25]
|
| 20180 |
|
|
--operation mode is normal
|
| 20181 |
|
|
|
| 20182 |
|
|
VD1_hilo_37_iv_0_0[25] = VD1_hilo_25 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[25] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_25 & VD1_un134_hilo_combout[25] & VD1_hilo_37_iv_0_a3_0[0];
|
| 20183 |
|
|
|
| 20184 |
|
|
|
| 20185 |
|
|
--VD1_hilo_37_iv_0_8[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_8[57]
|
| 20186 |
|
|
--operation mode is normal
|
| 20187 |
|
|
|
| 20188 |
|
|
VD1_hilo_37_iv_0_8[57] = VD1_hilo_37_iv_0_5[57] # VD1_hilo_37_iv_0_8_a[57] # VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_25;
|
| 20189 |
|
|
|
| 20190 |
|
|
|
| 20191 |
|
|
--PD1_a_o_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[25]
|
| 20192 |
|
|
--operation mode is normal
|
| 20193 |
|
|
|
| 20194 |
|
|
PD1_a_o_a[25] = SC1_muxa_ctl_o_1 & !FB1_r32_o_25 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_25;
|
| 20195 |
|
|
|
| 20196 |
|
|
|
| 20197 |
|
|
--PD1_a_o_3_Z[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[25]
|
| 20198 |
|
|
--operation mode is normal
|
| 20199 |
|
|
|
| 20200 |
|
|
PD1_a_o_3_Z[25] = PD1_a_o_3_s[0] & SD1_r32_o_25 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[25];
|
| 20201 |
|
|
|
| 20202 |
|
|
|
| 20203 |
|
|
--TD1_un1_b_1_combout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[25]
|
| 20204 |
|
|
--operation mode is normal
|
| 20205 |
|
|
|
| 20206 |
|
|
TD1_un1_b_1_combout[25] = TD1_sum13_0_a2 $ !VD1_b_o_iv_25;
|
| 20207 |
|
|
|
| 20208 |
|
|
|
| 20209 |
|
|
--UD1_shift_out_87_d_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[22]
|
| 20210 |
|
|
--operation mode is normal
|
| 20211 |
|
|
|
| 20212 |
|
|
UD1_shift_out_87_d_a[22] = PD1_a_o_1 & !VD1_b_o_iv_28 # !PD1_a_o_1 & !VD1_b_o_iv_26;
|
| 20213 |
|
|
|
| 20214 |
|
|
|
| 20215 |
|
|
--UD1_shift_out_80[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[22]
|
| 20216 |
|
|
--operation mode is normal
|
| 20217 |
|
|
|
| 20218 |
|
|
UD1_shift_out_80[22] = PD1_a_o_2 & UD1_shift_out_80_a[22] & VD1_b_o_iv_27 # !UD1_shift_out_80_a[22] & VD1_b_o_iv_29 # !PD1_a_o_2 & !UD1_shift_out_80_a[22];
|
| 20219 |
|
|
|
| 20220 |
|
|
|
| 20221 |
|
|
--UD1_shift_out_54[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54[30]
|
| 20222 |
|
|
--operation mode is normal
|
| 20223 |
|
|
|
| 20224 |
|
|
UD1_shift_out_54[30] = PD1_a_o_1 & !UD1_shift_out_54_a[30] # !PD1_a_o_1 & UD1_shift_out_54_a[30] & VD1_b_o_iv_18 # !UD1_shift_out_54_a[30] & VD1_b_o_iv_17;
|
| 20225 |
|
|
|
| 20226 |
|
|
|
| 20227 |
|
|
--UD1_shift_out_79[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[22]
|
| 20228 |
|
|
--operation mode is normal
|
| 20229 |
|
|
|
| 20230 |
|
|
UD1_shift_out_79[22] = PD1_a_o_1 & UD1_shift_out_36_0 # !PD1_a_o_1 & !UD1_shift_out_79_a[22];
|
| 20231 |
|
|
|
| 20232 |
|
|
|
| 20233 |
|
|
--UD1_shift_out_63[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[30]
|
| 20234 |
|
|
--operation mode is normal
|
| 20235 |
|
|
|
| 20236 |
|
|
UD1_shift_out_63[30] = PD1_a_o_2 & UD1_shift_out_48[30] # !PD1_a_o_2 & UD1_shift_out_52[30];
|
| 20237 |
|
|
|
| 20238 |
|
|
|
| 20239 |
|
|
--VD1_hilo_37_iv_0_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[22]
|
| 20240 |
|
|
--operation mode is normal
|
| 20241 |
|
|
|
| 20242 |
|
|
VD1_hilo_37_iv_0_a[22] = VD1_hilo_21 & !VD1_hilo_2_sqmuxa & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_23 # !VD1_hilo_21 & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_23;
|
| 20243 |
|
|
|
| 20244 |
|
|
|
| 20245 |
|
|
--VD1_hilo_37_iv_0_0[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[22]
|
| 20246 |
|
|
--operation mode is normal
|
| 20247 |
|
|
|
| 20248 |
|
|
VD1_hilo_37_iv_0_0[22] = VD1_hilo_22 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[22] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_22 & VD1_un134_hilo_combout[22] & VD1_hilo_37_iv_0_a3_0[0];
|
| 20249 |
|
|
|
| 20250 |
|
|
|
| 20251 |
|
|
--VD1_hilo_37_iv_0_a[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[54]
|
| 20252 |
|
|
--operation mode is normal
|
| 20253 |
|
|
|
| 20254 |
|
|
VD1_hilo_37_iv_0_a[54] = !VD1_hilo_37_iv_0_o5_0_0[54] & VD1_hilo_54 # VD1_hilo_33_1[64] # !VD1_hilo_3_sqmuxa;
|
| 20255 |
|
|
|
| 20256 |
|
|
|
| 20257 |
|
|
--VD1_hilo_37_iv_0_3[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[54]
|
| 20258 |
|
|
--operation mode is normal
|
| 20259 |
|
|
|
| 20260 |
|
|
VD1_hilo_37_iv_0_3[54] = VD1_hilo_37_iv_0_0[54] # VD1_hilo_37_iv_0_3_a[54] # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add22;
|
| 20261 |
|
|
|
| 20262 |
|
|
|
| 20263 |
|
|
--VD1_hilo_37_iv_0_o5[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5[54]
|
| 20264 |
|
|
--operation mode is normal
|
| 20265 |
|
|
|
| 20266 |
|
|
VD1_hilo_37_iv_0_o5[54] = VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_22 # !VD1_un50_hilo_add23 # !VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_22;
|
| 20267 |
|
|
|
| 20268 |
|
|
|
| 20269 |
|
|
--PD1_a_o_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[22]
|
| 20270 |
|
|
--operation mode is normal
|
| 20271 |
|
|
|
| 20272 |
|
|
PD1_a_o_a[22] = SC1_muxa_ctl_o_1 & !FB1_r32_o_22 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_22;
|
| 20273 |
|
|
|
| 20274 |
|
|
|
| 20275 |
|
|
--PD1_a_o_3_Z[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[22]
|
| 20276 |
|
|
--operation mode is normal
|
| 20277 |
|
|
|
| 20278 |
|
|
PD1_a_o_3_Z[22] = PD1_a_o_3_s[0] & SD1_r32_o_22 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[22];
|
| 20279 |
|
|
|
| 20280 |
|
|
|
| 20281 |
|
|
--TD1_un1_b_1_combout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[22]
|
| 20282 |
|
|
--operation mode is normal
|
| 20283 |
|
|
|
| 20284 |
|
|
TD1_un1_b_1_combout[22] = TD1_sum13_0_a2 $ !VD1_b_o_iv_22;
|
| 20285 |
|
|
|
| 20286 |
|
|
|
| 20287 |
|
|
--UD1_shift_out_87_d_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[23]
|
| 20288 |
|
|
--operation mode is normal
|
| 20289 |
|
|
|
| 20290 |
|
|
UD1_shift_out_87_d_a[23] = PD1_a_o_1 & !VD1_b_o_iv_29 # !PD1_a_o_1 & !VD1_b_o_iv_27;
|
| 20291 |
|
|
|
| 20292 |
|
|
|
| 20293 |
|
|
--UD1_shift_out_80[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[23]
|
| 20294 |
|
|
--operation mode is normal
|
| 20295 |
|
|
|
| 20296 |
|
|
UD1_shift_out_80[23] = PD1_a_o_2 & UD1_shift_out_80_a[23] & VD1_b_o_iv_28 # !UD1_shift_out_80_a[23] & VD1_b_o_iv_30 # !PD1_a_o_2 & !UD1_shift_out_80_a[23];
|
| 20297 |
|
|
|
| 20298 |
|
|
|
| 20299 |
|
|
--UD1_shift_out_54[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54[31]
|
| 20300 |
|
|
--operation mode is normal
|
| 20301 |
|
|
|
| 20302 |
|
|
UD1_shift_out_54[31] = PD1_a_o_1 & !UD1_shift_out_54_a[31] # !PD1_a_o_1 & UD1_shift_out_54_a[31] & VD1_b_o_iv_19 # !UD1_shift_out_54_a[31] & VD1_b_o_iv_18;
|
| 20303 |
|
|
|
| 20304 |
|
|
|
| 20305 |
|
|
--UD1_shift_out_88_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88_a[23]
|
| 20306 |
|
|
--operation mode is normal
|
| 20307 |
|
|
|
| 20308 |
|
|
UD1_shift_out_88_a[23] = PD1_a_o_1 & !UD1_shift_out_36_0 # !PD1_a_o_1 & PD1_a_o_0 & !UD1_shift_out_36_0 # !PD1_a_o_0 & !VD1_b_o_iv_31;
|
| 20309 |
|
|
|
| 20310 |
|
|
|
| 20311 |
|
|
--UD1_shift_out_77[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[23]
|
| 20312 |
|
|
--operation mode is normal
|
| 20313 |
|
|
|
| 20314 |
|
|
UD1_shift_out_77[23] = PD1_a_o_2 & UD1_shift_out_85_d[15] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[15] # !PD1_a_o_1 & !UD1_shift_out_77_a[23];
|
| 20315 |
|
|
|
| 20316 |
|
|
|
| 20317 |
|
|
--VD1_hilo_37_iv_0[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[23]
|
| 20318 |
|
|
--operation mode is normal
|
| 20319 |
|
|
|
| 20320 |
|
|
VD1_hilo_37_iv_0[23] = VD1_hilo_24 & VD1_hilo_1_sqmuxa_1 # VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[23] # !VD1_hilo_24 & VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[23];
|
| 20321 |
|
|
|
| 20322 |
|
|
|
| 20323 |
|
|
--VD1_hilo_8_Z[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[23]
|
| 20324 |
|
|
--operation mode is normal
|
| 20325 |
|
|
|
| 20326 |
|
|
VD1_hilo_8_Z[23] = RC1_alu_func_o_0 & VD1_hilo_23 # !RC1_alu_func_o_0 & PD1_a_o_23;
|
| 20327 |
|
|
|
| 20328 |
|
|
|
| 20329 |
|
|
--VD1_hilo_37_iv_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[23]
|
| 20330 |
|
|
--operation mode is normal
|
| 20331 |
|
|
|
| 20332 |
|
|
VD1_hilo_37_iv_a[23] = VD1_hilo_22 & !VD1_hilo_2_sqmuxa & !PD1_a_o_23 # !VD1_addnop2109_0_a2 # !VD1_hilo_22 & !PD1_a_o_23 # !VD1_addnop2109_0_a2;
|
| 20333 |
|
|
|
| 20334 |
|
|
|
| 20335 |
|
|
--VD1_hilo_37_iv_2[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[55]
|
| 20336 |
|
|
--operation mode is normal
|
| 20337 |
|
|
|
| 20338 |
|
|
VD1_hilo_37_iv_2[55] = VD1_hilo_33_i_m[55] # VD1_hilo_37_iv_2_a[55] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[55];
|
| 20339 |
|
|
|
| 20340 |
|
|
|
| 20341 |
|
|
--VD1_hilo_37_iv_a[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[55]
|
| 20342 |
|
|
--operation mode is normal
|
| 20343 |
|
|
|
| 20344 |
|
|
VD1_hilo_37_iv_a[55] = RC1_alu_func_o_0 & !PD1_a_o_23 # !RC1_alu_func_o_0 & !VD1_hilo_55;
|
| 20345 |
|
|
|
| 20346 |
|
|
|
| 20347 |
|
|
--PD1_a_o_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[23]
|
| 20348 |
|
|
--operation mode is normal
|
| 20349 |
|
|
|
| 20350 |
|
|
PD1_a_o_a[23] = SC1_muxa_ctl_o_1 & !FB1_r32_o_23 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_23;
|
| 20351 |
|
|
|
| 20352 |
|
|
|
| 20353 |
|
|
--PD1_a_o_3_Z[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[23]
|
| 20354 |
|
|
--operation mode is normal
|
| 20355 |
|
|
|
| 20356 |
|
|
PD1_a_o_3_Z[23] = PD1_a_o_3_s[0] & SD1_r32_o_23 # !PD1_a_o_3_s[0] & PD1_a_o_3_d[23];
|
| 20357 |
|
|
|
| 20358 |
|
|
|
| 20359 |
|
|
--TD1_un1_b_1_combout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[23]
|
| 20360 |
|
|
--operation mode is normal
|
| 20361 |
|
|
|
| 20362 |
|
|
TD1_un1_b_1_combout[23] = TD1_sum13_0_a2 $ !VD1_b_o_iv_23;
|
| 20363 |
|
|
|
| 20364 |
|
|
|
| 20365 |
|
|
--F1_dout_22 is mips_sys:isys|mips_dvc:imips_dvc|dout_22
|
| 20366 |
|
|
--operation mode is normal
|
| 20367 |
|
|
|
| 20368 |
|
|
F1_dout_22_lut_out = K1_cntr_22 & F1_dout_0_0_a3_4[0] # F1_cmd[22] & F1_dout_0_0_a3_3[0] # !K1_cntr_22 & F1_cmd[22] & F1_dout_0_0_a3_3[0];
|
| 20369 |
|
|
F1_dout_22 = DFFEAS(F1_dout_22_lut_out, E1__clk0, VCC, , , , , , );
|
| 20370 |
|
|
|
| 20371 |
|
|
|
| 20372 |
|
|
--DB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_22
|
| 20373 |
|
|
--operation mode is normal
|
| 20374 |
|
|
|
| 20375 |
|
|
DB1_r32_o_22_lut_out = WB72L1;
|
| 20376 |
|
|
DB1_r32_o_22 = DFFEAS(DB1_r32_o_22_lut_out, E1__clk0, VCC, , , , , , );
|
| 20377 |
|
|
|
| 20378 |
|
|
|
| 20379 |
|
|
--BB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_22
|
| 20380 |
|
|
--operation mode is normal
|
| 20381 |
|
|
|
| 20382 |
|
|
BB1_r32_o_22_lut_out = AB1_r32_o_20;
|
| 20383 |
|
|
BB1_r32_o_22 = DFFEAS(BB1_r32_o_22_lut_out, E1__clk0, VCC, , , , , , );
|
| 20384 |
|
|
|
| 20385 |
|
|
|
| 20386 |
|
|
--ND1_dout_2_a_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_14
|
| 20387 |
|
|
--operation mode is normal
|
| 20388 |
|
|
|
| 20389 |
|
|
ND1_dout_2_a_14 = XD1_mux_fw_1 & !AB1_r32_o_12 # !XD1_mux_fw_1 & !QB1_r32_o_14;
|
| 20390 |
|
|
|
| 20391 |
|
|
|
| 20392 |
|
|
--GD1_dout_iv_1_a[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[8]
|
| 20393 |
|
|
--operation mode is normal
|
| 20394 |
|
|
|
| 20395 |
|
|
GD1_dout_iv_1_a[8] = FD1_r_data_8 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_6 # !FD1_r_data_8 & !ZD1_mux_fw_1 # !AB1_r32_o_6;
|
| 20396 |
|
|
|
| 20397 |
|
|
|
| 20398 |
|
|
--LD1_q_b[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[8]
|
| 20399 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 20400 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 20401 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 20402 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 20403 |
|
|
LD1_q_b[8]_PORT_A_data_in = FD1_wb_o_8;
|
| 20404 |
|
|
LD1_q_b[8]_PORT_A_data_in_reg = DFFE(LD1_q_b[8]_PORT_A_data_in, LD1_q_b[8]_clock_0, , , );
|
| 20405 |
|
|
LD1_q_b[8]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 20406 |
|
|
LD1_q_b[8]_PORT_A_address_reg = DFFE(LD1_q_b[8]_PORT_A_address, LD1_q_b[8]_clock_0, , , );
|
| 20407 |
|
|
LD1_q_b[8]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 20408 |
|
|
LD1_q_b[8]_PORT_B_address_reg = DFFE(LD1_q_b[8]_PORT_B_address, LD1_q_b[8]_clock_1, , , );
|
| 20409 |
|
|
LD1_q_b[8]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 20410 |
|
|
LD1_q_b[8]_PORT_A_write_enable_reg = DFFE(LD1_q_b[8]_PORT_A_write_enable, LD1_q_b[8]_clock_0, , , );
|
| 20411 |
|
|
LD1_q_b[8]_PORT_B_read_enable = VCC;
|
| 20412 |
|
|
LD1_q_b[8]_PORT_B_read_enable_reg = DFFE(LD1_q_b[8]_PORT_B_read_enable, LD1_q_b[8]_clock_1, , , );
|
| 20413 |
|
|
LD1_q_b[8]_clock_0 = E1__clk0;
|
| 20414 |
|
|
LD1_q_b[8]_clock_1 = E1__clk0;
|
| 20415 |
|
|
LD1_q_b[8]_PORT_B_data_out = MEMORY(LD1_q_b[8]_PORT_A_data_in_reg, , LD1_q_b[8]_PORT_A_address_reg, LD1_q_b[8]_PORT_B_address_reg, LD1_q_b[8]_PORT_A_write_enable_reg, LD1_q_b[8]_PORT_B_read_enable_reg, , , LD1_q_b[8]_clock_0, LD1_q_b[8]_clock_1, , , , );
|
| 20416 |
|
|
LD1_q_b[8] = LD1_q_b[8]_PORT_B_data_out[0];
|
| 20417 |
|
|
|
| 20418 |
|
|
|
| 20419 |
|
|
--F1_dout_21 is mips_sys:isys|mips_dvc:imips_dvc|dout_21
|
| 20420 |
|
|
--operation mode is normal
|
| 20421 |
|
|
|
| 20422 |
|
|
F1_dout_21_lut_out = K1_cntr_21 & F1_dout_0_0_a3_4[0] # F1_cmd[21] & F1_dout_0_0_a3_3[0] # !K1_cntr_21 & F1_cmd[21] & F1_dout_0_0_a3_3[0];
|
| 20423 |
|
|
F1_dout_21 = DFFEAS(F1_dout_21_lut_out, E1__clk0, VCC, , , , , , );
|
| 20424 |
|
|
|
| 20425 |
|
|
|
| 20426 |
|
|
--DB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_21
|
| 20427 |
|
|
--operation mode is normal
|
| 20428 |
|
|
|
| 20429 |
|
|
DB1_r32_o_21_lut_out = WB62L1;
|
| 20430 |
|
|
DB1_r32_o_21 = DFFEAS(DB1_r32_o_21_lut_out, E1__clk0, VCC, , , , , , );
|
| 20431 |
|
|
|
| 20432 |
|
|
|
| 20433 |
|
|
--BB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_21
|
| 20434 |
|
|
--operation mode is normal
|
| 20435 |
|
|
|
| 20436 |
|
|
BB1_r32_o_21_lut_out = AB1_r32_o_19;
|
| 20437 |
|
|
BB1_r32_o_21 = DFFEAS(BB1_r32_o_21_lut_out, E1__clk0, VCC, , , , , , );
|
| 20438 |
|
|
|
| 20439 |
|
|
|
| 20440 |
|
|
--ND1_dout_2_a_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_13
|
| 20441 |
|
|
--operation mode is normal
|
| 20442 |
|
|
|
| 20443 |
|
|
ND1_dout_2_a_13 = XD1_mux_fw_1 & !AB1_r32_o_11 # !XD1_mux_fw_1 & !QB1_r32_o_13;
|
| 20444 |
|
|
|
| 20445 |
|
|
|
| 20446 |
|
|
--ND1_dout_2_a_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_12
|
| 20447 |
|
|
--operation mode is normal
|
| 20448 |
|
|
|
| 20449 |
|
|
ND1_dout_2_a_12 = XD1_mux_fw_1 & !AB1_r32_o_10 # !XD1_mux_fw_1 & !QB1_r32_o_12;
|
| 20450 |
|
|
|
| 20451 |
|
|
|
| 20452 |
|
|
--M1_bit_ctr23_i_i is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr23_i_i
|
| 20453 |
|
|
--operation mode is normal
|
| 20454 |
|
|
|
| 20455 |
|
|
M1_bit_ctr23_i_i = sys_rst & M1_ua_state[2];
|
| 20456 |
|
|
|
| 20457 |
|
|
|
| 20458 |
|
|
--F1_dout_19 is mips_sys:isys|mips_dvc:imips_dvc|dout_19
|
| 20459 |
|
|
--operation mode is normal
|
| 20460 |
|
|
|
| 20461 |
|
|
F1_dout_19_lut_out = K1_cntr_19 & F1_dout_0_0_a3_4[0] # F1_cmd[19] & F1_dout_0_0_a3_3[0] # !K1_cntr_19 & F1_cmd[19] & F1_dout_0_0_a3_3[0];
|
| 20462 |
|
|
F1_dout_19 = DFFEAS(F1_dout_19_lut_out, E1__clk0, VCC, , , , , , );
|
| 20463 |
|
|
|
| 20464 |
|
|
|
| 20465 |
|
|
--DB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_19
|
| 20466 |
|
|
--operation mode is normal
|
| 20467 |
|
|
|
| 20468 |
|
|
DB1_r32_o_19_lut_out = WB42L1;
|
| 20469 |
|
|
DB1_r32_o_19 = DFFEAS(DB1_r32_o_19_lut_out, E1__clk0, VCC, , , , , , );
|
| 20470 |
|
|
|
| 20471 |
|
|
|
| 20472 |
|
|
--BB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_19
|
| 20473 |
|
|
--operation mode is normal
|
| 20474 |
|
|
|
| 20475 |
|
|
BB1_r32_o_19_lut_out = AB1_r32_o_17;
|
| 20476 |
|
|
BB1_r32_o_19 = DFFEAS(BB1_r32_o_19_lut_out, E1__clk0, VCC, , , , , , );
|
| 20477 |
|
|
|
| 20478 |
|
|
|
| 20479 |
|
|
--ND1_dout_2_a_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_11
|
| 20480 |
|
|
--operation mode is normal
|
| 20481 |
|
|
|
| 20482 |
|
|
ND1_dout_2_a_11 = XD1_mux_fw_1 & !AB1_r32_o_9 # !XD1_mux_fw_1 & !QB1_r32_o_11;
|
| 20483 |
|
|
|
| 20484 |
|
|
|
| 20485 |
|
|
--F1_dout_18 is mips_sys:isys|mips_dvc:imips_dvc|dout_18
|
| 20486 |
|
|
--operation mode is normal
|
| 20487 |
|
|
|
| 20488 |
|
|
F1_dout_18_lut_out = K1_cntr_18 & F1_dout_0_0_a3_4[0] # F1_cmd[18] & F1_dout_0_0_a3_3[0] # !K1_cntr_18 & F1_cmd[18] & F1_dout_0_0_a3_3[0];
|
| 20489 |
|
|
F1_dout_18 = DFFEAS(F1_dout_18_lut_out, E1__clk0, VCC, , , , , , );
|
| 20490 |
|
|
|
| 20491 |
|
|
|
| 20492 |
|
|
--DB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_18
|
| 20493 |
|
|
--operation mode is normal
|
| 20494 |
|
|
|
| 20495 |
|
|
DB1_r32_o_18_lut_out = WB32L1;
|
| 20496 |
|
|
DB1_r32_o_18 = DFFEAS(DB1_r32_o_18_lut_out, E1__clk0, VCC, , , , , , );
|
| 20497 |
|
|
|
| 20498 |
|
|
|
| 20499 |
|
|
--BB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_18
|
| 20500 |
|
|
--operation mode is normal
|
| 20501 |
|
|
|
| 20502 |
|
|
BB1_r32_o_18_lut_out = AB1_r32_o_16;
|
| 20503 |
|
|
BB1_r32_o_18 = DFFEAS(BB1_r32_o_18_lut_out, E1__clk0, VCC, , , , , , );
|
| 20504 |
|
|
|
| 20505 |
|
|
|
| 20506 |
|
|
--ND1_dout_2_a_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_10
|
| 20507 |
|
|
--operation mode is normal
|
| 20508 |
|
|
|
| 20509 |
|
|
ND1_dout_2_a_10 = XD1_mux_fw_1 & !AB1_r32_o_8 # !XD1_mux_fw_1 & !QB1_r32_o_10;
|
| 20510 |
|
|
|
| 20511 |
|
|
|
| 20512 |
|
|
--F1_dout_17 is mips_sys:isys|mips_dvc:imips_dvc|dout_17
|
| 20513 |
|
|
--operation mode is normal
|
| 20514 |
|
|
|
| 20515 |
|
|
F1_dout_17_lut_out = K1_cntr_17 & F1_dout_0_0_a3_4[0] # F1_cmd[17] & F1_dout_0_0_a3_3[0] # !K1_cntr_17 & F1_cmd[17] & F1_dout_0_0_a3_3[0];
|
| 20516 |
|
|
F1_dout_17 = DFFEAS(F1_dout_17_lut_out, E1__clk0, VCC, , , , , , );
|
| 20517 |
|
|
|
| 20518 |
|
|
|
| 20519 |
|
|
--DB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_17
|
| 20520 |
|
|
--operation mode is normal
|
| 20521 |
|
|
|
| 20522 |
|
|
DB1_r32_o_17_lut_out = WB22L1;
|
| 20523 |
|
|
DB1_r32_o_17 = DFFEAS(DB1_r32_o_17_lut_out, E1__clk0, VCC, , , , , , );
|
| 20524 |
|
|
|
| 20525 |
|
|
|
| 20526 |
|
|
--BB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_17
|
| 20527 |
|
|
--operation mode is normal
|
| 20528 |
|
|
|
| 20529 |
|
|
BB1_r32_o_17_lut_out = AB1_r32_o_15;
|
| 20530 |
|
|
BB1_r32_o_17 = DFFEAS(BB1_r32_o_17_lut_out, E1__clk0, VCC, , , , , , );
|
| 20531 |
|
|
|
| 20532 |
|
|
|
| 20533 |
|
|
--ND1_dout_2_a_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_9
|
| 20534 |
|
|
--operation mode is normal
|
| 20535 |
|
|
|
| 20536 |
|
|
ND1_dout_2_a_9 = XD1_mux_fw_1 & !AB1_r32_o_7 # !XD1_mux_fw_1 & !QB1_r32_o_9;
|
| 20537 |
|
|
|
| 20538 |
|
|
|
| 20539 |
|
|
--VD1_un59_hilo_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add1
|
| 20540 |
|
|
--operation mode is arithmetic
|
| 20541 |
|
|
|
| 20542 |
|
|
VD1_un59_hilo_add1_carry_eqn = VD1_un59_hilo_carry_0;
|
| 20543 |
|
|
VD1_un59_hilo_add1 = VD1_hilo_33 $ VD1_op2_reged[1] $ VD1_un59_hilo_add1_carry_eqn;
|
| 20544 |
|
|
|
| 20545 |
|
|
--VD1_un59_hilo_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_1
|
| 20546 |
|
|
--operation mode is arithmetic
|
| 20547 |
|
|
|
| 20548 |
|
|
VD1_un59_hilo_carry_1 = CARRY(VD1_hilo_33 & !VD1_op2_reged[1] & !VD1_un59_hilo_carry_0 # !VD1_hilo_33 & !VD1_un59_hilo_carry_0 # !VD1_op2_reged[1]);
|
| 20549 |
|
|
|
| 20550 |
|
|
|
| 20551 |
|
|
--F1_dout_16 is mips_sys:isys|mips_dvc:imips_dvc|dout_16
|
| 20552 |
|
|
--operation mode is normal
|
| 20553 |
|
|
|
| 20554 |
|
|
F1_dout_16_lut_out = K1_cntr_16 & F1_dout_0_0_a3_4[0] # F1_cmd[16] & F1_dout_0_0_a3_3[0] # !K1_cntr_16 & F1_cmd[16] & F1_dout_0_0_a3_3[0];
|
| 20555 |
|
|
F1_dout_16 = DFFEAS(F1_dout_16_lut_out, E1__clk0, VCC, , , , , , );
|
| 20556 |
|
|
|
| 20557 |
|
|
|
| 20558 |
|
|
--DB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_16
|
| 20559 |
|
|
--operation mode is normal
|
| 20560 |
|
|
|
| 20561 |
|
|
DB1_r32_o_16_lut_out = WB12L1;
|
| 20562 |
|
|
DB1_r32_o_16 = DFFEAS(DB1_r32_o_16_lut_out, E1__clk0, VCC, , , , , , );
|
| 20563 |
|
|
|
| 20564 |
|
|
|
| 20565 |
|
|
--BB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_16
|
| 20566 |
|
|
--operation mode is normal
|
| 20567 |
|
|
|
| 20568 |
|
|
BB1_r32_o_16_lut_out = AB1_r32_o_14;
|
| 20569 |
|
|
BB1_r32_o_16 = DFFEAS(BB1_r32_o_16_lut_out, E1__clk0, VCC, , , , , , );
|
| 20570 |
|
|
|
| 20571 |
|
|
|
| 20572 |
|
|
--VD1_hilo_33_i_m_a[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[32]
|
| 20573 |
|
|
--operation mode is normal
|
| 20574 |
|
|
|
| 20575 |
|
|
VD1_hilo_33_i_m_a[32] = VD1_addnop2 & !VD1_un50_hilo_add0 # !VD1_addnop2 & !VD1_un59_hilo_add0;
|
| 20576 |
|
|
|
| 20577 |
|
|
|
| 20578 |
|
|
--VD1_hilo_22_Z[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[32]
|
| 20579 |
|
|
--operation mode is normal
|
| 20580 |
|
|
|
| 20581 |
|
|
VD1_hilo_22_Z[32] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[32] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[32] # !VD1_sign & !VD1_hilo_22_a[32];
|
| 20582 |
|
|
|
| 20583 |
|
|
|
| 20584 |
|
|
--VD1_hilo_37_iv_0_1_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[0]
|
| 20585 |
|
|
--operation mode is normal
|
| 20586 |
|
|
|
| 20587 |
|
|
VD1_hilo_37_iv_0_1_a[0] = !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_1;
|
| 20588 |
|
|
|
| 20589 |
|
|
|
| 20590 |
|
|
--VD1_un1_op2_reged_1_combout[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[32]
|
| 20591 |
|
|
--operation mode is normal
|
| 20592 |
|
|
|
| 20593 |
|
|
VD1_un1_op2_reged_1_combout[32] = VD1_eqop2_2_32 & VD1_op2_sign_reged # !VD1_eqop2_2_32 & VD1_nop2_reged[32];
|
| 20594 |
|
|
|
| 20595 |
|
|
|
| 20596 |
|
|
--VD1_hilo_24_add31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add31
|
| 20597 |
|
|
--operation mode is arithmetic
|
| 20598 |
|
|
|
| 20599 |
|
|
VD1_hilo_24_add31_carry_eqn = VD1_hilo_24_carry_30;
|
| 20600 |
|
|
VD1_hilo_24_add31 = VD1_hilo_62 $ VD1_un1_op2_reged_1_combout[31] $ VD1_hilo_24_add31_carry_eqn;
|
| 20601 |
|
|
|
| 20602 |
|
|
--VD1_hilo_24_carry_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_31
|
| 20603 |
|
|
--operation mode is arithmetic
|
| 20604 |
|
|
|
| 20605 |
|
|
VD1_hilo_24_carry_31 = CARRY(VD1_hilo_62 & !VD1_un1_op2_reged_1_combout[31] & !VD1_hilo_24_carry_30 # !VD1_hilo_62 & !VD1_hilo_24_carry_30 # !VD1_un1_op2_reged_1_combout[31]);
|
| 20606 |
|
|
|
| 20607 |
|
|
|
| 20608 |
|
|
--DD1_pc_next_0_iv_1_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_30
|
| 20609 |
|
|
--operation mode is normal
|
| 20610 |
|
|
|
| 20611 |
|
|
DD1_pc_next_0_iv_1_30 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_30 # !DD1_pc_next_0_iv_1_a[30];
|
| 20612 |
|
|
|
| 20613 |
|
|
|
| 20614 |
|
|
--DD1_un1_pc_add30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add30
|
| 20615 |
|
|
--operation mode is arithmetic
|
| 20616 |
|
|
|
| 20617 |
|
|
DD1_un1_pc_add30_carry_eqn = DD1_un1_pc_carry_29;
|
| 20618 |
|
|
DD1_un1_pc_add30 = KB1_r32_o_30 $ DD1_un1_pc_prectl_1_0_a4[30] $ !DD1_un1_pc_add30_carry_eqn;
|
| 20619 |
|
|
|
| 20620 |
|
|
--DD1_un1_pc_carry_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_30
|
| 20621 |
|
|
--operation mode is arithmetic
|
| 20622 |
|
|
|
| 20623 |
|
|
DD1_un1_pc_carry_30 = CARRY(KB1_r32_o_30 & DD1_un1_pc_prectl_1_0_a4[30] # !DD1_un1_pc_carry_29 # !KB1_r32_o_30 & DD1_un1_pc_prectl_1_0_a4[30] & !DD1_un1_pc_carry_29);
|
| 20624 |
|
|
|
| 20625 |
|
|
|
| 20626 |
|
|
--DD1_pc_next_0_iv_a_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_a_0
|
| 20627 |
|
|
--operation mode is normal
|
| 20628 |
|
|
|
| 20629 |
|
|
DD1_pc_next_0_iv_a_0 = KB1_r32_o_31 & !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_31 # !KB1_r32_o_31 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_31;
|
| 20630 |
|
|
|
| 20631 |
|
|
|
| 20632 |
|
|
--G1_BUS24839_m[31] is mips_sys:isys|mips_core:mips_core|BUS24839_m[31]
|
| 20633 |
|
|
--operation mode is normal
|
| 20634 |
|
|
|
| 20635 |
|
|
G1_BUS24839_m[31] = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_31;
|
| 20636 |
|
|
|
| 20637 |
|
|
|
| 20638 |
|
|
--DD1_un1_pc_add31 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add31
|
| 20639 |
|
|
--operation mode is normal
|
| 20640 |
|
|
|
| 20641 |
|
|
DD1_un1_pc_add31_carry_eqn = DD1_un1_pc_carry_30;
|
| 20642 |
|
|
DD1_un1_pc_add31 = KB1_r32_o_31 $ DD1_un1_pc_prectl_1_0_a4[31] $ DD1_un1_pc_add31_carry_eqn;
|
| 20643 |
|
|
|
| 20644 |
|
|
|
| 20645 |
|
|
--KB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_28
|
| 20646 |
|
|
--operation mode is normal
|
| 20647 |
|
|
|
| 20648 |
|
|
KB1_r32_o_28_lut_out = DD1_pc_next_0_iv_1_28 # DD1_un1_pc_next46_0 & DD1_un1_pc_add28;
|
| 20649 |
|
|
KB1_r32_o_28 = DFFEAS(KB1_r32_o_28_lut_out, E1__clk0, VCC, , , , , , );
|
| 20650 |
|
|
|
| 20651 |
|
|
|
| 20652 |
|
|
--KB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_29
|
| 20653 |
|
|
--operation mode is normal
|
| 20654 |
|
|
|
| 20655 |
|
|
KB1_r32_o_29_lut_out = DD1_pc_next_0_iv_1_29 # DD1_un1_pc_next46_0 & DD1_un1_pc_add29;
|
| 20656 |
|
|
KB1_r32_o_29 = DFFEAS(KB1_r32_o_29_lut_out, E1__clk0, VCC, , , , , , );
|
| 20657 |
|
|
|
| 20658 |
|
|
|
| 20659 |
|
|
--RD1_r32_o_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_27
|
| 20660 |
|
|
--operation mode is arithmetic
|
| 20661 |
|
|
|
| 20662 |
|
|
RD1_r32_o_27_carry_eqn = RD1_r32_o_cout[25];
|
| 20663 |
|
|
RD1_r32_o_27_lut_out = KB1_r32_o_27 $ (KB1_r32_o_26 & !RD1_r32_o_27_carry_eqn);
|
| 20664 |
|
|
RD1_r32_o_27 = DFFEAS(RD1_r32_o_27_lut_out, E1__clk0, VCC, , , , , , );
|
| 20665 |
|
|
|
| 20666 |
|
|
--RD1_r32_o_cout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[27]
|
| 20667 |
|
|
--operation mode is arithmetic
|
| 20668 |
|
|
|
| 20669 |
|
|
RD1_r32_o_cout[27] = CARRY(KB1_r32_o_26 & KB1_r32_o_27 & !RD1_r32_o_cout[25]);
|
| 20670 |
|
|
|
| 20671 |
|
|
|
| 20672 |
|
|
--PB1_dout_iv_31 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_31
|
| 20673 |
|
|
--operation mode is normal
|
| 20674 |
|
|
|
| 20675 |
|
|
PB1_dout_iv_31 = FD1_reg_bank_m_0 # FD1_wb_o_31 & HD1_dout7_0_a2 # !HD1_dout_iv_a_0;
|
| 20676 |
|
|
|
| 20677 |
|
|
--PB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_31
|
| 20678 |
|
|
--operation mode is normal
|
| 20679 |
|
|
|
| 20680 |
|
|
PB1_r32_o_31 = DFFEAS(PB1_dout_iv_31, E1__clk0, VCC, , , , , , );
|
| 20681 |
|
|
|
| 20682 |
|
|
|
| 20683 |
|
|
--GD1_dout_iv_1_a[31] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[31]
|
| 20684 |
|
|
--operation mode is normal
|
| 20685 |
|
|
|
| 20686 |
|
|
GD1_dout_iv_1_a[31] = FD1_r_data_31 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_29 # !FD1_r_data_31 & !ZD1_mux_fw_1 # !AB1_r32_o_29;
|
| 20687 |
|
|
|
| 20688 |
|
|
|
| 20689 |
|
|
--LD1_q_b[31] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[31]
|
| 20690 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 20691 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 20692 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 20693 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 20694 |
|
|
LD1_q_b[31]_PORT_A_data_in = FD1_wb_o_31;
|
| 20695 |
|
|
LD1_q_b[31]_PORT_A_data_in_reg = DFFE(LD1_q_b[31]_PORT_A_data_in, LD1_q_b[31]_clock_0, , , );
|
| 20696 |
|
|
LD1_q_b[31]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 20697 |
|
|
LD1_q_b[31]_PORT_A_address_reg = DFFE(LD1_q_b[31]_PORT_A_address, LD1_q_b[31]_clock_0, , , );
|
| 20698 |
|
|
LD1_q_b[31]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 20699 |
|
|
LD1_q_b[31]_PORT_B_address_reg = DFFE(LD1_q_b[31]_PORT_B_address, LD1_q_b[31]_clock_1, , , );
|
| 20700 |
|
|
LD1_q_b[31]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 20701 |
|
|
LD1_q_b[31]_PORT_A_write_enable_reg = DFFE(LD1_q_b[31]_PORT_A_write_enable, LD1_q_b[31]_clock_0, , , );
|
| 20702 |
|
|
LD1_q_b[31]_PORT_B_read_enable = VCC;
|
| 20703 |
|
|
LD1_q_b[31]_PORT_B_read_enable_reg = DFFE(LD1_q_b[31]_PORT_B_read_enable, LD1_q_b[31]_clock_1, , , );
|
| 20704 |
|
|
LD1_q_b[31]_clock_0 = E1__clk0;
|
| 20705 |
|
|
LD1_q_b[31]_clock_1 = E1__clk0;
|
| 20706 |
|
|
LD1_q_b[31]_PORT_B_data_out = MEMORY(LD1_q_b[31]_PORT_A_data_in_reg, , LD1_q_b[31]_PORT_A_address_reg, LD1_q_b[31]_PORT_B_address_reg, LD1_q_b[31]_PORT_A_write_enable_reg, LD1_q_b[31]_PORT_B_read_enable_reg, , , LD1_q_b[31]_clock_0, LD1_q_b[31]_clock_1, , , , );
|
| 20707 |
|
|
LD1_q_b[31] = LD1_q_b[31]_PORT_B_data_out[0];
|
| 20708 |
|
|
|
| 20709 |
|
|
|
| 20710 |
|
|
--F1_cmd[31] is mips_sys:isys|mips_dvc:imips_dvc|cmd[31]
|
| 20711 |
|
|
--operation mode is normal
|
| 20712 |
|
|
|
| 20713 |
|
|
F1_cmd[31]_lut_out = CB1_r32_o_31;
|
| 20714 |
|
|
F1_cmd[31] = DFFEAS(F1_cmd[31]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 20715 |
|
|
|
| 20716 |
|
|
|
| 20717 |
|
|
--GD1_dout_iv_1_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_30
|
| 20718 |
|
|
--operation mode is normal
|
| 20719 |
|
|
|
| 20720 |
|
|
GD1_dout_iv_1_30 = FD1_N_20_i_0_s3 & LD1_q_b[30] # !GD1_dout_iv_1_a[30];
|
| 20721 |
|
|
|
| 20722 |
|
|
|
| 20723 |
|
|
--F1_dout_30 is mips_sys:isys|mips_dvc:imips_dvc|dout_30
|
| 20724 |
|
|
--operation mode is normal
|
| 20725 |
|
|
|
| 20726 |
|
|
F1_dout_30_lut_out = K1_cntr_30 & F1_dout_0_0_a3_4[0] # F1_cmd[30] & F1_dout_0_0_a3_3[0] # !K1_cntr_30 & F1_cmd[30] & F1_dout_0_0_a3_3[0];
|
| 20727 |
|
|
F1_dout_30 = DFFEAS(F1_dout_30_lut_out, E1__clk0, VCC, , , , , , );
|
| 20728 |
|
|
|
| 20729 |
|
|
|
| 20730 |
|
|
--DB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_30
|
| 20731 |
|
|
--operation mode is normal
|
| 20732 |
|
|
|
| 20733 |
|
|
DB1_r32_o_30_lut_out = WB53L1;
|
| 20734 |
|
|
DB1_r32_o_30 = DFFEAS(DB1_r32_o_30_lut_out, E1__clk0, VCC, , , , , , );
|
| 20735 |
|
|
|
| 20736 |
|
|
|
| 20737 |
|
|
--BB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_30
|
| 20738 |
|
|
--operation mode is normal
|
| 20739 |
|
|
|
| 20740 |
|
|
BB1_r32_o_30_lut_out = AB1_r32_o_28;
|
| 20741 |
|
|
BB1_r32_o_30 = DFFEAS(BB1_r32_o_30_lut_out, E1__clk0, VCC, , , , , , );
|
| 20742 |
|
|
|
| 20743 |
|
|
|
| 20744 |
|
|
--SD1_r32_o_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_29
|
| 20745 |
|
|
--operation mode is normal
|
| 20746 |
|
|
|
| 20747 |
|
|
SD1_r32_o_29_lut_out = KB1_r32_o_29;
|
| 20748 |
|
|
SD1_r32_o_29 = DFFEAS(SD1_r32_o_29_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 20749 |
|
|
|
| 20750 |
|
|
|
| 20751 |
|
|
--PD1_a_o_3_d[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[29]
|
| 20752 |
|
|
--operation mode is normal
|
| 20753 |
|
|
|
| 20754 |
|
|
PD1_a_o_3_d[29] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_29 # !PD1_un6_a_o & !PD1_a_o_3_d_a[29] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[29];
|
| 20755 |
|
|
|
| 20756 |
|
|
|
| 20757 |
|
|
--TD1_lt_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_26
|
| 20758 |
|
|
--operation mode is arithmetic
|
| 20759 |
|
|
|
| 20760 |
|
|
TD1_lt_26 = CARRY(PD1_a_o_26 & VD1_b_o_iv_26 & !TD1_lt_25 # !PD1_a_o_26 & VD1_b_o_iv_26 # !TD1_lt_25);
|
| 20761 |
|
|
|
| 20762 |
|
|
|
| 20763 |
|
|
--TD1_sum_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_27
|
| 20764 |
|
|
--operation mode is arithmetic
|
| 20765 |
|
|
|
| 20766 |
|
|
TD1_sum_carry_27 = CARRY(VD1_b_o_iv_27 & !TD1_sum_carry_26 # !PD1_a_o_27 # !VD1_b_o_iv_27 & !PD1_a_o_27 & !TD1_sum_carry_26);
|
| 20767 |
|
|
|
| 20768 |
|
|
|
| 20769 |
|
|
--F1_dout_28 is mips_sys:isys|mips_dvc:imips_dvc|dout_28
|
| 20770 |
|
|
--operation mode is normal
|
| 20771 |
|
|
|
| 20772 |
|
|
F1_dout_28_lut_out = K1_cntr_28 & F1_dout_0_0_a3_4[0] # F1_cmd[28] & F1_dout_0_0_a3_3[0] # !K1_cntr_28 & F1_cmd[28] & F1_dout_0_0_a3_3[0];
|
| 20773 |
|
|
F1_dout_28 = DFFEAS(F1_dout_28_lut_out, E1__clk0, VCC, , , , , , );
|
| 20774 |
|
|
|
| 20775 |
|
|
|
| 20776 |
|
|
--DB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_28
|
| 20777 |
|
|
--operation mode is normal
|
| 20778 |
|
|
|
| 20779 |
|
|
DB1_r32_o_28_lut_out = WB33L1;
|
| 20780 |
|
|
DB1_r32_o_28 = DFFEAS(DB1_r32_o_28_lut_out, E1__clk0, VCC, , , , , , );
|
| 20781 |
|
|
|
| 20782 |
|
|
|
| 20783 |
|
|
--BB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_28
|
| 20784 |
|
|
--operation mode is normal
|
| 20785 |
|
|
|
| 20786 |
|
|
BB1_r32_o_28_lut_out = AB1_r32_o_26;
|
| 20787 |
|
|
BB1_r32_o_28 = DFFEAS(BB1_r32_o_28_lut_out, E1__clk0, VCC, , , , , , );
|
| 20788 |
|
|
|
| 20789 |
|
|
|
| 20790 |
|
|
--ND1_dout_2_a_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_27
|
| 20791 |
|
|
--operation mode is normal
|
| 20792 |
|
|
|
| 20793 |
|
|
ND1_dout_2_a_27 = XD1_mux_fw_1 & !AB1_r32_o_25 # !XD1_mux_fw_1 & !QB1_r32_o_27;
|
| 20794 |
|
|
|
| 20795 |
|
|
|
| 20796 |
|
|
--F1_dout_29 is mips_sys:isys|mips_dvc:imips_dvc|dout_29
|
| 20797 |
|
|
--operation mode is normal
|
| 20798 |
|
|
|
| 20799 |
|
|
F1_dout_29_lut_out = K1_cntr_29 & F1_dout_0_0_a3_4[0] # F1_cmd[29] & F1_dout_0_0_a3_3[0] # !K1_cntr_29 & F1_cmd[29] & F1_dout_0_0_a3_3[0];
|
| 20800 |
|
|
F1_dout_29 = DFFEAS(F1_dout_29_lut_out, E1__clk0, VCC, , , , , , );
|
| 20801 |
|
|
|
| 20802 |
|
|
|
| 20803 |
|
|
--DB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_29
|
| 20804 |
|
|
--operation mode is normal
|
| 20805 |
|
|
|
| 20806 |
|
|
DB1_r32_o_29_lut_out = WB43L1;
|
| 20807 |
|
|
DB1_r32_o_29 = DFFEAS(DB1_r32_o_29_lut_out, E1__clk0, VCC, , , , , , );
|
| 20808 |
|
|
|
| 20809 |
|
|
|
| 20810 |
|
|
--BB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_29
|
| 20811 |
|
|
--operation mode is normal
|
| 20812 |
|
|
|
| 20813 |
|
|
BB1_r32_o_29_lut_out = AB1_r32_o_27;
|
| 20814 |
|
|
BB1_r32_o_29 = DFFEAS(BB1_r32_o_29_lut_out, E1__clk0, VCC, , , , , , );
|
| 20815 |
|
|
|
| 20816 |
|
|
|
| 20817 |
|
|
--ND1_dout_2_a_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_26
|
| 20818 |
|
|
--operation mode is normal
|
| 20819 |
|
|
|
| 20820 |
|
|
ND1_dout_2_a_26 = XD1_mux_fw_1 & !AB1_r32_o_24 # !XD1_mux_fw_1 & !QB1_r32_o_26;
|
| 20821 |
|
|
|
| 20822 |
|
|
|
| 20823 |
|
|
--ND1_dout_2_a_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_24
|
| 20824 |
|
|
--operation mode is normal
|
| 20825 |
|
|
|
| 20826 |
|
|
ND1_dout_2_a_24 = XD1_mux_fw_1 & !AB1_r32_o_22 # !XD1_mux_fw_1 & !QB1_r32_o_24;
|
| 20827 |
|
|
|
| 20828 |
|
|
|
| 20829 |
|
|
--ND1_dout_2_a_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_25
|
| 20830 |
|
|
--operation mode is normal
|
| 20831 |
|
|
|
| 20832 |
|
|
ND1_dout_2_a_25 = XD1_mux_fw_1 & !AB1_r32_o_23 # !XD1_mux_fw_1 & !QB1_r32_o_25;
|
| 20833 |
|
|
|
| 20834 |
|
|
|
| 20835 |
|
|
--ND1_dout_2_a_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_15
|
| 20836 |
|
|
--operation mode is normal
|
| 20837 |
|
|
|
| 20838 |
|
|
ND1_dout_2_a_15 = XD1_mux_fw_1 & !AB1_r32_o_13 # !XD1_mux_fw_1 & !QB1_r32_o_15;
|
| 20839 |
|
|
|
| 20840 |
|
|
|
| 20841 |
|
|
--UB1_dout_2_i_i[8] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[8]
|
| 20842 |
|
|
--operation mode is normal
|
| 20843 |
|
|
|
| 20844 |
|
|
UB1_dout_2_i_i[8] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[0] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_i_i_a_x[8];
|
| 20845 |
|
|
|
| 20846 |
|
|
|
| 20847 |
|
|
--UB1_un1_ctl_5 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_ctl_5
|
| 20848 |
|
|
--operation mode is normal
|
| 20849 |
|
|
|
| 20850 |
|
|
UB1_un1_ctl_5 = RB1_ctl_o_0 # RB1_ctl_o_3 & RB1_ctl_o_2 # !RB1_ctl_o_3 & !RB1_ctl_o_1;
|
| 20851 |
|
|
|
| 20852 |
|
|
|
| 20853 |
|
|
--WB31L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_8__Z|lpm_latch:U1|q[0]~56
|
| 20854 |
|
|
--operation mode is normal
|
| 20855 |
|
|
|
| 20856 |
|
|
WB31L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[8] # !UB1_un1_byte_addr_2 & WB31L1;
|
| 20857 |
|
|
|
| 20858 |
|
|
|
| 20859 |
|
|
--M1_clk_ctr27_i_0_a5_4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_0_a5_4
|
| 20860 |
|
|
--operation mode is normal
|
| 20861 |
|
|
|
| 20862 |
|
|
M1_clk_ctr27_i_0_a5_4 = M1_clk_ctr[5] & !M1_clk_ctr[4] & M1_clk_ctr[1] & M1_clk_ctr[9];
|
| 20863 |
|
|
|
| 20864 |
|
|
|
| 20865 |
|
|
--M1_clk_ctr27_i_0_a5_5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_0_a5_5
|
| 20866 |
|
|
--operation mode is normal
|
| 20867 |
|
|
|
| 20868 |
|
|
M1_clk_ctr27_i_0_a5_5 = !M1_clk_ctr_2 & M1_clk_ctr_3 & !M1_clk_ctr[8] & M1_clk_ctr27_i_0_a5_5_a;
|
| 20869 |
|
|
|
| 20870 |
|
|
|
| 20871 |
|
|
--HD1_dout_iv_1_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[2]
|
| 20872 |
|
|
--operation mode is normal
|
| 20873 |
|
|
|
| 20874 |
|
|
HD1_dout_iv_1_a[2] = FD1_r_data_2 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_0 # !FD1_r_data_2 & !YD1_mux_fw_1 # !AB1_r32_o_0;
|
| 20875 |
|
|
|
| 20876 |
|
|
|
| 20877 |
|
|
--LD2_q_b[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[2]
|
| 20878 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 20879 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 20880 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 20881 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 20882 |
|
|
LD2_q_b[2]_PORT_A_data_in = FD1_wb_o_2;
|
| 20883 |
|
|
LD2_q_b[2]_PORT_A_data_in_reg = DFFE(LD2_q_b[2]_PORT_A_data_in, LD2_q_b[2]_clock_0, , , );
|
| 20884 |
|
|
LD2_q_b[2]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 20885 |
|
|
LD2_q_b[2]_PORT_A_address_reg = DFFE(LD2_q_b[2]_PORT_A_address, LD2_q_b[2]_clock_0, , , );
|
| 20886 |
|
|
LD2_q_b[2]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 20887 |
|
|
LD2_q_b[2]_PORT_B_address_reg = DFFE(LD2_q_b[2]_PORT_B_address, LD2_q_b[2]_clock_1, , , );
|
| 20888 |
|
|
LD2_q_b[2]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 20889 |
|
|
LD2_q_b[2]_PORT_A_write_enable_reg = DFFE(LD2_q_b[2]_PORT_A_write_enable, LD2_q_b[2]_clock_0, , , );
|
| 20890 |
|
|
LD2_q_b[2]_PORT_B_read_enable = VCC;
|
| 20891 |
|
|
LD2_q_b[2]_PORT_B_read_enable_reg = DFFE(LD2_q_b[2]_PORT_B_read_enable, LD2_q_b[2]_clock_1, , , );
|
| 20892 |
|
|
LD2_q_b[2]_clock_0 = E1__clk0;
|
| 20893 |
|
|
LD2_q_b[2]_clock_1 = E1__clk0;
|
| 20894 |
|
|
LD2_q_b[2]_PORT_B_data_out = MEMORY(LD2_q_b[2]_PORT_A_data_in_reg, , LD2_q_b[2]_PORT_A_address_reg, LD2_q_b[2]_PORT_B_address_reg, LD2_q_b[2]_PORT_A_write_enable_reg, LD2_q_b[2]_PORT_B_read_enable_reg, , , LD2_q_b[2]_clock_0, LD2_q_b[2]_clock_1, , , , );
|
| 20895 |
|
|
LD2_q_b[2] = LD2_q_b[2]_PORT_B_data_out[0];
|
| 20896 |
|
|
|
| 20897 |
|
|
|
| 20898 |
|
|
--BC1_cmp_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2|cmp_ctl_o_0
|
| 20899 |
|
|
--operation mode is normal
|
| 20900 |
|
|
|
| 20901 |
|
|
BC1_cmp_ctl_o_0_lut_out = WB34L1;
|
| 20902 |
|
|
BC1_cmp_ctl_o_0 = DFFEAS(BC1_cmp_ctl_o_0_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 20903 |
|
|
|
| 20904 |
|
|
|
| 20905 |
|
|
--BD1_res_3_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_3_0
|
| 20906 |
|
|
--operation mode is normal
|
| 20907 |
|
|
|
| 20908 |
|
|
BD1_res_3_0 = BC1_cmp_ctl_o_2 & BC1_cmp_ctl_o_1 $ !PB1_dout_iv_31 # !BC1_cmp_ctl_o_2 & BC1_cmp_ctl_o_1 & BD1_res_2_NE;
|
| 20909 |
|
|
|
| 20910 |
|
|
|
| 20911 |
|
|
--BD1_res_7_0_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_7_0_a
|
| 20912 |
|
|
--operation mode is normal
|
| 20913 |
|
|
|
| 20914 |
|
|
BD1_res_7_0_a = BC1_cmp_ctl_o_2 & !BC1_cmp_ctl_o_1 & BD1_res_5 # !BC1_cmp_ctl_o_2 & BC1_cmp_ctl_o_1 & !BD1_res_5 # !BC1_cmp_ctl_o_1 & !BD1_res_2_NE;
|
| 20915 |
|
|
|
| 20916 |
|
|
|
| 20917 |
|
|
--HD1_dout_iv_1_a[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[3]
|
| 20918 |
|
|
--operation mode is normal
|
| 20919 |
|
|
|
| 20920 |
|
|
HD1_dout_iv_1_a[3] = FD1_r_data_3 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_1 # !FD1_r_data_3 & !YD1_mux_fw_1 # !AB1_r32_o_1;
|
| 20921 |
|
|
|
| 20922 |
|
|
|
| 20923 |
|
|
--LD2_q_b[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[3]
|
| 20924 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 20925 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 20926 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 20927 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 20928 |
|
|
LD2_q_b[3]_PORT_A_data_in = FD1_wb_o_3;
|
| 20929 |
|
|
LD2_q_b[3]_PORT_A_data_in_reg = DFFE(LD2_q_b[3]_PORT_A_data_in, LD2_q_b[3]_clock_0, , , );
|
| 20930 |
|
|
LD2_q_b[3]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 20931 |
|
|
LD2_q_b[3]_PORT_A_address_reg = DFFE(LD2_q_b[3]_PORT_A_address, LD2_q_b[3]_clock_0, , , );
|
| 20932 |
|
|
LD2_q_b[3]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 20933 |
|
|
LD2_q_b[3]_PORT_B_address_reg = DFFE(LD2_q_b[3]_PORT_B_address, LD2_q_b[3]_clock_1, , , );
|
| 20934 |
|
|
LD2_q_b[3]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 20935 |
|
|
LD2_q_b[3]_PORT_A_write_enable_reg = DFFE(LD2_q_b[3]_PORT_A_write_enable, LD2_q_b[3]_clock_0, , , );
|
| 20936 |
|
|
LD2_q_b[3]_PORT_B_read_enable = VCC;
|
| 20937 |
|
|
LD2_q_b[3]_PORT_B_read_enable_reg = DFFE(LD2_q_b[3]_PORT_B_read_enable, LD2_q_b[3]_clock_1, , , );
|
| 20938 |
|
|
LD2_q_b[3]_clock_0 = E1__clk0;
|
| 20939 |
|
|
LD2_q_b[3]_clock_1 = E1__clk0;
|
| 20940 |
|
|
LD2_q_b[3]_PORT_B_data_out = MEMORY(LD2_q_b[3]_PORT_A_data_in_reg, , LD2_q_b[3]_PORT_A_address_reg, LD2_q_b[3]_PORT_B_address_reg, LD2_q_b[3]_PORT_A_write_enable_reg, LD2_q_b[3]_PORT_B_read_enable_reg, , , LD2_q_b[3]_clock_0, LD2_q_b[3]_clock_1, , , , );
|
| 20941 |
|
|
LD2_q_b[3] = LD2_q_b[3]_PORT_B_data_out[0];
|
| 20942 |
|
|
|
| 20943 |
|
|
|
| 20944 |
|
|
--DD1_un1_pc_prectl_1_0_a3_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a3_a[0]
|
| 20945 |
|
|
--operation mode is normal
|
| 20946 |
|
|
|
| 20947 |
|
|
DD1_un1_pc_prectl_1_0_a3_a[0] = !AD1_CurrState_Sreg0_5 & HC1_pc_gen_ctl_o_2 & AD1_CurrState_Sreg0_3 # AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
|
| 20948 |
|
|
|
| 20949 |
|
|
|
| 20950 |
|
|
--HD1_dout_iv_1_a[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[6]
|
| 20951 |
|
|
--operation mode is normal
|
| 20952 |
|
|
|
| 20953 |
|
|
HD1_dout_iv_1_a[6] = FD1_r_data_6 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_4 # !FD1_r_data_6 & !YD1_mux_fw_1 # !AB1_r32_o_4;
|
| 20954 |
|
|
|
| 20955 |
|
|
|
| 20956 |
|
|
--LD2_q_b[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[6]
|
| 20957 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 20958 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 20959 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 20960 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 20961 |
|
|
LD2_q_b[6]_PORT_A_data_in = FD1_wb_o_6;
|
| 20962 |
|
|
LD2_q_b[6]_PORT_A_data_in_reg = DFFE(LD2_q_b[6]_PORT_A_data_in, LD2_q_b[6]_clock_0, , , );
|
| 20963 |
|
|
LD2_q_b[6]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 20964 |
|
|
LD2_q_b[6]_PORT_A_address_reg = DFFE(LD2_q_b[6]_PORT_A_address, LD2_q_b[6]_clock_0, , , );
|
| 20965 |
|
|
LD2_q_b[6]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 20966 |
|
|
LD2_q_b[6]_PORT_B_address_reg = DFFE(LD2_q_b[6]_PORT_B_address, LD2_q_b[6]_clock_1, , , );
|
| 20967 |
|
|
LD2_q_b[6]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 20968 |
|
|
LD2_q_b[6]_PORT_A_write_enable_reg = DFFE(LD2_q_b[6]_PORT_A_write_enable, LD2_q_b[6]_clock_0, , , );
|
| 20969 |
|
|
LD2_q_b[6]_PORT_B_read_enable = VCC;
|
| 20970 |
|
|
LD2_q_b[6]_PORT_B_read_enable_reg = DFFE(LD2_q_b[6]_PORT_B_read_enable, LD2_q_b[6]_clock_1, , , );
|
| 20971 |
|
|
LD2_q_b[6]_clock_0 = E1__clk0;
|
| 20972 |
|
|
LD2_q_b[6]_clock_1 = E1__clk0;
|
| 20973 |
|
|
LD2_q_b[6]_PORT_B_data_out = MEMORY(LD2_q_b[6]_PORT_A_data_in_reg, , LD2_q_b[6]_PORT_A_address_reg, LD2_q_b[6]_PORT_B_address_reg, LD2_q_b[6]_PORT_A_write_enable_reg, LD2_q_b[6]_PORT_B_read_enable_reg, , , LD2_q_b[6]_clock_0, LD2_q_b[6]_clock_1, , , , );
|
| 20974 |
|
|
LD2_q_b[6] = LD2_q_b[6]_PORT_B_data_out[0];
|
| 20975 |
|
|
|
| 20976 |
|
|
|
| 20977 |
|
|
--HD1_dout_iv_1_a[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[7]
|
| 20978 |
|
|
--operation mode is normal
|
| 20979 |
|
|
|
| 20980 |
|
|
HD1_dout_iv_1_a[7] = FD1_r_data_7 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_5 # !FD1_r_data_7 & !YD1_mux_fw_1 # !AB1_r32_o_5;
|
| 20981 |
|
|
|
| 20982 |
|
|
|
| 20983 |
|
|
--LD2_q_b[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[7]
|
| 20984 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 20985 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 20986 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 20987 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 20988 |
|
|
LD2_q_b[7]_PORT_A_data_in = FD1_wb_o_7;
|
| 20989 |
|
|
LD2_q_b[7]_PORT_A_data_in_reg = DFFE(LD2_q_b[7]_PORT_A_data_in, LD2_q_b[7]_clock_0, , , );
|
| 20990 |
|
|
LD2_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 20991 |
|
|
LD2_q_b[7]_PORT_A_address_reg = DFFE(LD2_q_b[7]_PORT_A_address, LD2_q_b[7]_clock_0, , , );
|
| 20992 |
|
|
LD2_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 20993 |
|
|
LD2_q_b[7]_PORT_B_address_reg = DFFE(LD2_q_b[7]_PORT_B_address, LD2_q_b[7]_clock_1, , , );
|
| 20994 |
|
|
LD2_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 20995 |
|
|
LD2_q_b[7]_PORT_A_write_enable_reg = DFFE(LD2_q_b[7]_PORT_A_write_enable, LD2_q_b[7]_clock_0, , , );
|
| 20996 |
|
|
LD2_q_b[7]_PORT_B_read_enable = VCC;
|
| 20997 |
|
|
LD2_q_b[7]_PORT_B_read_enable_reg = DFFE(LD2_q_b[7]_PORT_B_read_enable, LD2_q_b[7]_clock_1, , , );
|
| 20998 |
|
|
LD2_q_b[7]_clock_0 = E1__clk0;
|
| 20999 |
|
|
LD2_q_b[7]_clock_1 = E1__clk0;
|
| 21000 |
|
|
LD2_q_b[7]_PORT_B_data_out = MEMORY(LD2_q_b[7]_PORT_A_data_in_reg, , LD2_q_b[7]_PORT_A_address_reg, LD2_q_b[7]_PORT_B_address_reg, LD2_q_b[7]_PORT_A_write_enable_reg, LD2_q_b[7]_PORT_B_read_enable_reg, , , LD2_q_b[7]_clock_0, LD2_q_b[7]_clock_1, , , , );
|
| 21001 |
|
|
LD2_q_b[7] = LD2_q_b[7]_PORT_B_data_out[0];
|
| 21002 |
|
|
|
| 21003 |
|
|
|
| 21004 |
|
|
--HD1_dout_iv_1_a[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[8]
|
| 21005 |
|
|
--operation mode is normal
|
| 21006 |
|
|
|
| 21007 |
|
|
HD1_dout_iv_1_a[8] = FD1_r_data_8 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_6 # !FD1_r_data_8 & !YD1_mux_fw_1 # !AB1_r32_o_6;
|
| 21008 |
|
|
|
| 21009 |
|
|
|
| 21010 |
|
|
--LD2_q_b[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[8]
|
| 21011 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 21012 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 21013 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 21014 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 21015 |
|
|
LD2_q_b[8]_PORT_A_data_in = FD1_wb_o_8;
|
| 21016 |
|
|
LD2_q_b[8]_PORT_A_data_in_reg = DFFE(LD2_q_b[8]_PORT_A_data_in, LD2_q_b[8]_clock_0, , , );
|
| 21017 |
|
|
LD2_q_b[8]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 21018 |
|
|
LD2_q_b[8]_PORT_A_address_reg = DFFE(LD2_q_b[8]_PORT_A_address, LD2_q_b[8]_clock_0, , , );
|
| 21019 |
|
|
LD2_q_b[8]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 21020 |
|
|
LD2_q_b[8]_PORT_B_address_reg = DFFE(LD2_q_b[8]_PORT_B_address, LD2_q_b[8]_clock_1, , , );
|
| 21021 |
|
|
LD2_q_b[8]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 21022 |
|
|
LD2_q_b[8]_PORT_A_write_enable_reg = DFFE(LD2_q_b[8]_PORT_A_write_enable, LD2_q_b[8]_clock_0, , , );
|
| 21023 |
|
|
LD2_q_b[8]_PORT_B_read_enable = VCC;
|
| 21024 |
|
|
LD2_q_b[8]_PORT_B_read_enable_reg = DFFE(LD2_q_b[8]_PORT_B_read_enable, LD2_q_b[8]_clock_1, , , );
|
| 21025 |
|
|
LD2_q_b[8]_clock_0 = E1__clk0;
|
| 21026 |
|
|
LD2_q_b[8]_clock_1 = E1__clk0;
|
| 21027 |
|
|
LD2_q_b[8]_PORT_B_data_out = MEMORY(LD2_q_b[8]_PORT_A_data_in_reg, , LD2_q_b[8]_PORT_A_address_reg, LD2_q_b[8]_PORT_B_address_reg, LD2_q_b[8]_PORT_A_write_enable_reg, LD2_q_b[8]_PORT_B_read_enable_reg, , , LD2_q_b[8]_clock_0, LD2_q_b[8]_clock_1, , , , );
|
| 21028 |
|
|
LD2_q_b[8] = LD2_q_b[8]_PORT_B_data_out[0];
|
| 21029 |
|
|
|
| 21030 |
|
|
|
| 21031 |
|
|
--HD1_dout_iv_1_a[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[9]
|
| 21032 |
|
|
--operation mode is normal
|
| 21033 |
|
|
|
| 21034 |
|
|
HD1_dout_iv_1_a[9] = FD1_r_data_9 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_7 # !FD1_r_data_9 & !YD1_mux_fw_1 # !AB1_r32_o_7;
|
| 21035 |
|
|
|
| 21036 |
|
|
|
| 21037 |
|
|
--LD2_q_b[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[9]
|
| 21038 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 21039 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 21040 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 21041 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 21042 |
|
|
LD2_q_b[9]_PORT_A_data_in = FD1_wb_o_9;
|
| 21043 |
|
|
LD2_q_b[9]_PORT_A_data_in_reg = DFFE(LD2_q_b[9]_PORT_A_data_in, LD2_q_b[9]_clock_0, , , );
|
| 21044 |
|
|
LD2_q_b[9]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 21045 |
|
|
LD2_q_b[9]_PORT_A_address_reg = DFFE(LD2_q_b[9]_PORT_A_address, LD2_q_b[9]_clock_0, , , );
|
| 21046 |
|
|
LD2_q_b[9]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 21047 |
|
|
LD2_q_b[9]_PORT_B_address_reg = DFFE(LD2_q_b[9]_PORT_B_address, LD2_q_b[9]_clock_1, , , );
|
| 21048 |
|
|
LD2_q_b[9]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 21049 |
|
|
LD2_q_b[9]_PORT_A_write_enable_reg = DFFE(LD2_q_b[9]_PORT_A_write_enable, LD2_q_b[9]_clock_0, , , );
|
| 21050 |
|
|
LD2_q_b[9]_PORT_B_read_enable = VCC;
|
| 21051 |
|
|
LD2_q_b[9]_PORT_B_read_enable_reg = DFFE(LD2_q_b[9]_PORT_B_read_enable, LD2_q_b[9]_clock_1, , , );
|
| 21052 |
|
|
LD2_q_b[9]_clock_0 = E1__clk0;
|
| 21053 |
|
|
LD2_q_b[9]_clock_1 = E1__clk0;
|
| 21054 |
|
|
LD2_q_b[9]_PORT_B_data_out = MEMORY(LD2_q_b[9]_PORT_A_data_in_reg, , LD2_q_b[9]_PORT_A_address_reg, LD2_q_b[9]_PORT_B_address_reg, LD2_q_b[9]_PORT_A_write_enable_reg, LD2_q_b[9]_PORT_B_read_enable_reg, , , LD2_q_b[9]_clock_0, LD2_q_b[9]_clock_1, , , , );
|
| 21055 |
|
|
LD2_q_b[9] = LD2_q_b[9]_PORT_B_data_out[0];
|
| 21056 |
|
|
|
| 21057 |
|
|
|
| 21058 |
|
|
--F1_dout_10 is mips_sys:isys|mips_dvc:imips_dvc|dout_10
|
| 21059 |
|
|
--operation mode is normal
|
| 21060 |
|
|
|
| 21061 |
|
|
F1_dout_10_lut_out = K1_cntr_10 & F1_dout_0_0_a3_4[0] # F1_cmd[10] & F1_dout_0_0_a3_3[0] # !K1_cntr_10 & F1_cmd[10] & F1_dout_0_0_a3_3[0];
|
| 21062 |
|
|
F1_dout_10 = DFFEAS(F1_dout_10_lut_out, E1__clk0, VCC, , , , , , );
|
| 21063 |
|
|
|
| 21064 |
|
|
|
| 21065 |
|
|
--DB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_10
|
| 21066 |
|
|
--operation mode is normal
|
| 21067 |
|
|
|
| 21068 |
|
|
DB1_r32_o_10_lut_out = WB51L1;
|
| 21069 |
|
|
DB1_r32_o_10 = DFFEAS(DB1_r32_o_10_lut_out, E1__clk0, VCC, , , , , , );
|
| 21070 |
|
|
|
| 21071 |
|
|
|
| 21072 |
|
|
--BB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_10
|
| 21073 |
|
|
--operation mode is normal
|
| 21074 |
|
|
|
| 21075 |
|
|
BB1_r32_o_10_lut_out = AB1_r32_o_8;
|
| 21076 |
|
|
BB1_r32_o_10 = DFFEAS(BB1_r32_o_10_lut_out, E1__clk0, VCC, , , , , , );
|
| 21077 |
|
|
|
| 21078 |
|
|
|
| 21079 |
|
|
--HD1_dout_iv_1_a[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[10]
|
| 21080 |
|
|
--operation mode is normal
|
| 21081 |
|
|
|
| 21082 |
|
|
HD1_dout_iv_1_a[10] = FD1_r_data_10 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_8 # !FD1_r_data_10 & !YD1_mux_fw_1 # !AB1_r32_o_8;
|
| 21083 |
|
|
|
| 21084 |
|
|
|
| 21085 |
|
|
--LD2_q_b[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[10]
|
| 21086 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 21087 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 21088 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 21089 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 21090 |
|
|
LD2_q_b[10]_PORT_A_data_in = FD1_wb_o_10;
|
| 21091 |
|
|
LD2_q_b[10]_PORT_A_data_in_reg = DFFE(LD2_q_b[10]_PORT_A_data_in, LD2_q_b[10]_clock_0, , , );
|
| 21092 |
|
|
LD2_q_b[10]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 21093 |
|
|
LD2_q_b[10]_PORT_A_address_reg = DFFE(LD2_q_b[10]_PORT_A_address, LD2_q_b[10]_clock_0, , , );
|
| 21094 |
|
|
LD2_q_b[10]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 21095 |
|
|
LD2_q_b[10]_PORT_B_address_reg = DFFE(LD2_q_b[10]_PORT_B_address, LD2_q_b[10]_clock_1, , , );
|
| 21096 |
|
|
LD2_q_b[10]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 21097 |
|
|
LD2_q_b[10]_PORT_A_write_enable_reg = DFFE(LD2_q_b[10]_PORT_A_write_enable, LD2_q_b[10]_clock_0, , , );
|
| 21098 |
|
|
LD2_q_b[10]_PORT_B_read_enable = VCC;
|
| 21099 |
|
|
LD2_q_b[10]_PORT_B_read_enable_reg = DFFE(LD2_q_b[10]_PORT_B_read_enable, LD2_q_b[10]_clock_1, , , );
|
| 21100 |
|
|
LD2_q_b[10]_clock_0 = E1__clk0;
|
| 21101 |
|
|
LD2_q_b[10]_clock_1 = E1__clk0;
|
| 21102 |
|
|
LD2_q_b[10]_PORT_B_data_out = MEMORY(LD2_q_b[10]_PORT_A_data_in_reg, , LD2_q_b[10]_PORT_A_address_reg, LD2_q_b[10]_PORT_B_address_reg, LD2_q_b[10]_PORT_A_write_enable_reg, LD2_q_b[10]_PORT_B_read_enable_reg, , , LD2_q_b[10]_clock_0, LD2_q_b[10]_clock_1, , , , );
|
| 21103 |
|
|
LD2_q_b[10] = LD2_q_b[10]_PORT_B_data_out[0];
|
| 21104 |
|
|
|
| 21105 |
|
|
|
| 21106 |
|
|
--F1_dout_11 is mips_sys:isys|mips_dvc:imips_dvc|dout_11
|
| 21107 |
|
|
--operation mode is normal
|
| 21108 |
|
|
|
| 21109 |
|
|
F1_dout_11_lut_out = K1_cntr_11 & F1_dout_0_0_a3_4[0] # F1_cmd[11] & F1_dout_0_0_a3_3[0] # !K1_cntr_11 & F1_cmd[11] & F1_dout_0_0_a3_3[0];
|
| 21110 |
|
|
F1_dout_11 = DFFEAS(F1_dout_11_lut_out, E1__clk0, VCC, , , , , , );
|
| 21111 |
|
|
|
| 21112 |
|
|
|
| 21113 |
|
|
--DB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_11
|
| 21114 |
|
|
--operation mode is normal
|
| 21115 |
|
|
|
| 21116 |
|
|
DB1_r32_o_11_lut_out = WB61L1;
|
| 21117 |
|
|
DB1_r32_o_11 = DFFEAS(DB1_r32_o_11_lut_out, E1__clk0, VCC, , , , , , );
|
| 21118 |
|
|
|
| 21119 |
|
|
|
| 21120 |
|
|
--BB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_11
|
| 21121 |
|
|
--operation mode is normal
|
| 21122 |
|
|
|
| 21123 |
|
|
BB1_r32_o_11_lut_out = AB1_r32_o_9;
|
| 21124 |
|
|
BB1_r32_o_11 = DFFEAS(BB1_r32_o_11_lut_out, E1__clk0, VCC, , , , , , );
|
| 21125 |
|
|
|
| 21126 |
|
|
|
| 21127 |
|
|
--HD1_dout_iv_1_a[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[11]
|
| 21128 |
|
|
--operation mode is normal
|
| 21129 |
|
|
|
| 21130 |
|
|
HD1_dout_iv_1_a[11] = FD1_r_data_11 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_9 # !FD1_r_data_11 & !YD1_mux_fw_1 # !AB1_r32_o_9;
|
| 21131 |
|
|
|
| 21132 |
|
|
|
| 21133 |
|
|
--LD2_q_b[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[11]
|
| 21134 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 21135 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 21136 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 21137 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 21138 |
|
|
LD2_q_b[11]_PORT_A_data_in = FD1_wb_o_11;
|
| 21139 |
|
|
LD2_q_b[11]_PORT_A_data_in_reg = DFFE(LD2_q_b[11]_PORT_A_data_in, LD2_q_b[11]_clock_0, , , );
|
| 21140 |
|
|
LD2_q_b[11]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 21141 |
|
|
LD2_q_b[11]_PORT_A_address_reg = DFFE(LD2_q_b[11]_PORT_A_address, LD2_q_b[11]_clock_0, , , );
|
| 21142 |
|
|
LD2_q_b[11]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 21143 |
|
|
LD2_q_b[11]_PORT_B_address_reg = DFFE(LD2_q_b[11]_PORT_B_address, LD2_q_b[11]_clock_1, , , );
|
| 21144 |
|
|
LD2_q_b[11]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 21145 |
|
|
LD2_q_b[11]_PORT_A_write_enable_reg = DFFE(LD2_q_b[11]_PORT_A_write_enable, LD2_q_b[11]_clock_0, , , );
|
| 21146 |
|
|
LD2_q_b[11]_PORT_B_read_enable = VCC;
|
| 21147 |
|
|
LD2_q_b[11]_PORT_B_read_enable_reg = DFFE(LD2_q_b[11]_PORT_B_read_enable, LD2_q_b[11]_clock_1, , , );
|
| 21148 |
|
|
LD2_q_b[11]_clock_0 = E1__clk0;
|
| 21149 |
|
|
LD2_q_b[11]_clock_1 = E1__clk0;
|
| 21150 |
|
|
LD2_q_b[11]_PORT_B_data_out = MEMORY(LD2_q_b[11]_PORT_A_data_in_reg, , LD2_q_b[11]_PORT_A_address_reg, LD2_q_b[11]_PORT_B_address_reg, LD2_q_b[11]_PORT_A_write_enable_reg, LD2_q_b[11]_PORT_B_read_enable_reg, , , LD2_q_b[11]_clock_0, LD2_q_b[11]_clock_1, , , , );
|
| 21151 |
|
|
LD2_q_b[11] = LD2_q_b[11]_PORT_B_data_out[0];
|
| 21152 |
|
|
|
| 21153 |
|
|
|
| 21154 |
|
|
--F1_dout_12 is mips_sys:isys|mips_dvc:imips_dvc|dout_12
|
| 21155 |
|
|
--operation mode is normal
|
| 21156 |
|
|
|
| 21157 |
|
|
F1_dout_12_lut_out = K1_cntr_12 & F1_dout_0_0_a3_4[0] # F1_cmd[12] & F1_dout_0_0_a3_3[0] # !K1_cntr_12 & F1_cmd[12] & F1_dout_0_0_a3_3[0];
|
| 21158 |
|
|
F1_dout_12 = DFFEAS(F1_dout_12_lut_out, E1__clk0, VCC, , , , , , );
|
| 21159 |
|
|
|
| 21160 |
|
|
|
| 21161 |
|
|
--DB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_12
|
| 21162 |
|
|
--operation mode is normal
|
| 21163 |
|
|
|
| 21164 |
|
|
DB1_r32_o_12_lut_out = WB71L1;
|
| 21165 |
|
|
DB1_r32_o_12 = DFFEAS(DB1_r32_o_12_lut_out, E1__clk0, VCC, , , , , , );
|
| 21166 |
|
|
|
| 21167 |
|
|
|
| 21168 |
|
|
--BB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_12
|
| 21169 |
|
|
--operation mode is normal
|
| 21170 |
|
|
|
| 21171 |
|
|
BB1_r32_o_12_lut_out = AB1_r32_o_10;
|
| 21172 |
|
|
BB1_r32_o_12 = DFFEAS(BB1_r32_o_12_lut_out, E1__clk0, VCC, , , , , , );
|
| 21173 |
|
|
|
| 21174 |
|
|
|
| 21175 |
|
|
--HD1_dout_iv_1_a[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[12]
|
| 21176 |
|
|
--operation mode is normal
|
| 21177 |
|
|
|
| 21178 |
|
|
HD1_dout_iv_1_a[12] = FD1_r_data_12 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_10 # !FD1_r_data_12 & !YD1_mux_fw_1 # !AB1_r32_o_10;
|
| 21179 |
|
|
|
| 21180 |
|
|
|
| 21181 |
|
|
--LD2_q_b[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[12]
|
| 21182 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 21183 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 21184 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 21185 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 21186 |
|
|
LD2_q_b[12]_PORT_A_data_in = FD1_wb_o_12;
|
| 21187 |
|
|
LD2_q_b[12]_PORT_A_data_in_reg = DFFE(LD2_q_b[12]_PORT_A_data_in, LD2_q_b[12]_clock_0, , , );
|
| 21188 |
|
|
LD2_q_b[12]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 21189 |
|
|
LD2_q_b[12]_PORT_A_address_reg = DFFE(LD2_q_b[12]_PORT_A_address, LD2_q_b[12]_clock_0, , , );
|
| 21190 |
|
|
LD2_q_b[12]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 21191 |
|
|
LD2_q_b[12]_PORT_B_address_reg = DFFE(LD2_q_b[12]_PORT_B_address, LD2_q_b[12]_clock_1, , , );
|
| 21192 |
|
|
LD2_q_b[12]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 21193 |
|
|
LD2_q_b[12]_PORT_A_write_enable_reg = DFFE(LD2_q_b[12]_PORT_A_write_enable, LD2_q_b[12]_clock_0, , , );
|
| 21194 |
|
|
LD2_q_b[12]_PORT_B_read_enable = VCC;
|
| 21195 |
|
|
LD2_q_b[12]_PORT_B_read_enable_reg = DFFE(LD2_q_b[12]_PORT_B_read_enable, LD2_q_b[12]_clock_1, , , );
|
| 21196 |
|
|
LD2_q_b[12]_clock_0 = E1__clk0;
|
| 21197 |
|
|
LD2_q_b[12]_clock_1 = E1__clk0;
|
| 21198 |
|
|
LD2_q_b[12]_PORT_B_data_out = MEMORY(LD2_q_b[12]_PORT_A_data_in_reg, , LD2_q_b[12]_PORT_A_address_reg, LD2_q_b[12]_PORT_B_address_reg, LD2_q_b[12]_PORT_A_write_enable_reg, LD2_q_b[12]_PORT_B_read_enable_reg, , , LD2_q_b[12]_clock_0, LD2_q_b[12]_clock_1, , , , );
|
| 21199 |
|
|
LD2_q_b[12] = LD2_q_b[12]_PORT_B_data_out[0];
|
| 21200 |
|
|
|
| 21201 |
|
|
|
| 21202 |
|
|
--F1_dout_23 is mips_sys:isys|mips_dvc:imips_dvc|dout_23
|
| 21203 |
|
|
--operation mode is normal
|
| 21204 |
|
|
|
| 21205 |
|
|
F1_dout_23_lut_out = K1_cntr_23 & F1_dout_0_0_a3_4[0] # F1_cmd[23] & F1_dout_0_0_a3_3[0] # !K1_cntr_23 & F1_cmd[23] & F1_dout_0_0_a3_3[0];
|
| 21206 |
|
|
F1_dout_23 = DFFEAS(F1_dout_23_lut_out, E1__clk0, VCC, , , , , , );
|
| 21207 |
|
|
|
| 21208 |
|
|
|
| 21209 |
|
|
--DB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_23
|
| 21210 |
|
|
--operation mode is normal
|
| 21211 |
|
|
|
| 21212 |
|
|
DB1_r32_o_23_lut_out = WB82L1;
|
| 21213 |
|
|
DB1_r32_o_23 = DFFEAS(DB1_r32_o_23_lut_out, E1__clk0, VCC, , , , , , );
|
| 21214 |
|
|
|
| 21215 |
|
|
|
| 21216 |
|
|
--BB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_23
|
| 21217 |
|
|
--operation mode is normal
|
| 21218 |
|
|
|
| 21219 |
|
|
BB1_r32_o_23_lut_out = AB1_r32_o_21;
|
| 21220 |
|
|
BB1_r32_o_23 = DFFEAS(BB1_r32_o_23_lut_out, E1__clk0, VCC, , , , , , );
|
| 21221 |
|
|
|
| 21222 |
|
|
|
| 21223 |
|
|
--UB1_dout_2_0_0[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0[9]
|
| 21224 |
|
|
--operation mode is normal
|
| 21225 |
|
|
|
| 21226 |
|
|
UB1_dout_2_0_0[9] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[1] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_0_0_a_x[9];
|
| 21227 |
|
|
|
| 21228 |
|
|
|
| 21229 |
|
|
--WB41L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_9__Z|lpm_latch:U1|q[0]~56
|
| 21230 |
|
|
--operation mode is normal
|
| 21231 |
|
|
|
| 21232 |
|
|
WB41L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_0_0[9] # !UB1_un1_byte_addr_2 & WB41L1;
|
| 21233 |
|
|
|
| 21234 |
|
|
|
| 21235 |
|
|
--GD1_dout_iv_1_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_11
|
| 21236 |
|
|
--operation mode is normal
|
| 21237 |
|
|
|
| 21238 |
|
|
GD1_dout_iv_1_11 = FD1_N_20_i_0_s3 & LD1_q_b[11] # !GD1_dout_iv_1_a[11];
|
| 21239 |
|
|
|
| 21240 |
|
|
|
| 21241 |
|
|
--GD1_dout_iv_1_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_13
|
| 21242 |
|
|
--operation mode is normal
|
| 21243 |
|
|
|
| 21244 |
|
|
GD1_dout_iv_1_13 = FD1_N_20_i_0_s3 & LD1_q_b[13] # !GD1_dout_iv_1_a[13];
|
| 21245 |
|
|
|
| 21246 |
|
|
|
| 21247 |
|
|
--F1_dout_13 is mips_sys:isys|mips_dvc:imips_dvc|dout_13
|
| 21248 |
|
|
--operation mode is normal
|
| 21249 |
|
|
|
| 21250 |
|
|
F1_dout_13_lut_out = K1_cntr_13 & F1_dout_0_0_a3_4[0] # F1_cmd[13] & F1_dout_0_0_a3_3[0] # !K1_cntr_13 & F1_cmd[13] & F1_dout_0_0_a3_3[0];
|
| 21251 |
|
|
F1_dout_13 = DFFEAS(F1_dout_13_lut_out, E1__clk0, VCC, , , , , , );
|
| 21252 |
|
|
|
| 21253 |
|
|
|
| 21254 |
|
|
--DB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_13
|
| 21255 |
|
|
--operation mode is normal
|
| 21256 |
|
|
|
| 21257 |
|
|
DB1_r32_o_13_lut_out = WB81L1;
|
| 21258 |
|
|
DB1_r32_o_13 = DFFEAS(DB1_r32_o_13_lut_out, E1__clk0, VCC, , , , , , );
|
| 21259 |
|
|
|
| 21260 |
|
|
|
| 21261 |
|
|
--BB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_13
|
| 21262 |
|
|
--operation mode is normal
|
| 21263 |
|
|
|
| 21264 |
|
|
BB1_r32_o_13_lut_out = AB1_r32_o_11;
|
| 21265 |
|
|
BB1_r32_o_13 = DFFEAS(BB1_r32_o_13_lut_out, E1__clk0, VCC, , , , , , );
|
| 21266 |
|
|
|
| 21267 |
|
|
|
| 21268 |
|
|
--GD1_dout_iv_1_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_12
|
| 21269 |
|
|
--operation mode is normal
|
| 21270 |
|
|
|
| 21271 |
|
|
GD1_dout_iv_1_12 = FD1_N_20_i_0_s3 & LD1_q_b[12] # !GD1_dout_iv_1_a[12];
|
| 21272 |
|
|
|
| 21273 |
|
|
|
| 21274 |
|
|
--GD1_dout_iv_1_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_14
|
| 21275 |
|
|
--operation mode is normal
|
| 21276 |
|
|
|
| 21277 |
|
|
GD1_dout_iv_1_14 = FD1_N_20_i_0_s3 & LD1_q_b[14] # !GD1_dout_iv_1_a[14];
|
| 21278 |
|
|
|
| 21279 |
|
|
|
| 21280 |
|
|
--F1_dout_14 is mips_sys:isys|mips_dvc:imips_dvc|dout_14
|
| 21281 |
|
|
--operation mode is normal
|
| 21282 |
|
|
|
| 21283 |
|
|
F1_dout_14_lut_out = K1_cntr_14 & F1_dout_0_0_a3_4[0] # F1_cmd[14] & F1_dout_0_0_a3_3[0] # !K1_cntr_14 & F1_cmd[14] & F1_dout_0_0_a3_3[0];
|
| 21284 |
|
|
F1_dout_14 = DFFEAS(F1_dout_14_lut_out, E1__clk0, VCC, , , , , , );
|
| 21285 |
|
|
|
| 21286 |
|
|
|
| 21287 |
|
|
--DB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_14
|
| 21288 |
|
|
--operation mode is normal
|
| 21289 |
|
|
|
| 21290 |
|
|
DB1_r32_o_14_lut_out = WB91L1;
|
| 21291 |
|
|
DB1_r32_o_14 = DFFEAS(DB1_r32_o_14_lut_out, E1__clk0, VCC, , , , , , );
|
| 21292 |
|
|
|
| 21293 |
|
|
|
| 21294 |
|
|
--BB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_14
|
| 21295 |
|
|
--operation mode is normal
|
| 21296 |
|
|
|
| 21297 |
|
|
BB1_r32_o_14_lut_out = AB1_r32_o_12;
|
| 21298 |
|
|
BB1_r32_o_14 = DFFEAS(BB1_r32_o_14_lut_out, E1__clk0, VCC, , , , , , );
|
| 21299 |
|
|
|
| 21300 |
|
|
|
| 21301 |
|
|
--HD1_dout_iv_1_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[1]
|
| 21302 |
|
|
--operation mode is normal
|
| 21303 |
|
|
|
| 21304 |
|
|
HD1_dout_iv_1_a[1] = FD1_r_data_1 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !RB1_byte_addr_o_1 # !FD1_r_data_1 & !YD1_mux_fw_1 # !RB1_byte_addr_o_1;
|
| 21305 |
|
|
|
| 21306 |
|
|
|
| 21307 |
|
|
--LD2_q_b[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[1]
|
| 21308 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 21309 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 21310 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 21311 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 21312 |
|
|
LD2_q_b[1]_PORT_A_data_in = FD1_wb_o_1;
|
| 21313 |
|
|
LD2_q_b[1]_PORT_A_data_in_reg = DFFE(LD2_q_b[1]_PORT_A_data_in, LD2_q_b[1]_clock_0, , , );
|
| 21314 |
|
|
LD2_q_b[1]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 21315 |
|
|
LD2_q_b[1]_PORT_A_address_reg = DFFE(LD2_q_b[1]_PORT_A_address, LD2_q_b[1]_clock_0, , , );
|
| 21316 |
|
|
LD2_q_b[1]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 21317 |
|
|
LD2_q_b[1]_PORT_B_address_reg = DFFE(LD2_q_b[1]_PORT_B_address, LD2_q_b[1]_clock_1, , , );
|
| 21318 |
|
|
LD2_q_b[1]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 21319 |
|
|
LD2_q_b[1]_PORT_A_write_enable_reg = DFFE(LD2_q_b[1]_PORT_A_write_enable, LD2_q_b[1]_clock_0, , , );
|
| 21320 |
|
|
LD2_q_b[1]_PORT_B_read_enable = VCC;
|
| 21321 |
|
|
LD2_q_b[1]_PORT_B_read_enable_reg = DFFE(LD2_q_b[1]_PORT_B_read_enable, LD2_q_b[1]_clock_1, , , );
|
| 21322 |
|
|
LD2_q_b[1]_clock_0 = E1__clk0;
|
| 21323 |
|
|
LD2_q_b[1]_clock_1 = E1__clk0;
|
| 21324 |
|
|
LD2_q_b[1]_PORT_B_data_out = MEMORY(LD2_q_b[1]_PORT_A_data_in_reg, , LD2_q_b[1]_PORT_A_address_reg, LD2_q_b[1]_PORT_B_address_reg, LD2_q_b[1]_PORT_A_write_enable_reg, LD2_q_b[1]_PORT_B_read_enable_reg, , , LD2_q_b[1]_clock_0, LD2_q_b[1]_clock_1, , , , );
|
| 21325 |
|
|
LD2_q_b[1] = LD2_q_b[1]_PORT_B_data_out[0];
|
| 21326 |
|
|
|
| 21327 |
|
|
|
| 21328 |
|
|
--HD1_dout_iv_1_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[0]
|
| 21329 |
|
|
--operation mode is normal
|
| 21330 |
|
|
|
| 21331 |
|
|
HD1_dout_iv_1_a[0] = FD1_r_data_0 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !RB1_byte_addr_o_0 # !FD1_r_data_0 & !YD1_mux_fw_1 # !RB1_byte_addr_o_0;
|
| 21332 |
|
|
|
| 21333 |
|
|
|
| 21334 |
|
|
--LD2_q_b[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[0]
|
| 21335 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 21336 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 21337 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 21338 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 21339 |
|
|
LD2_q_b[0]_PORT_A_data_in = FD1_wb_o_0;
|
| 21340 |
|
|
LD2_q_b[0]_PORT_A_data_in_reg = DFFE(LD2_q_b[0]_PORT_A_data_in, LD2_q_b[0]_clock_0, , , );
|
| 21341 |
|
|
LD2_q_b[0]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 21342 |
|
|
LD2_q_b[0]_PORT_A_address_reg = DFFE(LD2_q_b[0]_PORT_A_address, LD2_q_b[0]_clock_0, , , );
|
| 21343 |
|
|
LD2_q_b[0]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 21344 |
|
|
LD2_q_b[0]_PORT_B_address_reg = DFFE(LD2_q_b[0]_PORT_B_address, LD2_q_b[0]_clock_1, , , );
|
| 21345 |
|
|
LD2_q_b[0]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 21346 |
|
|
LD2_q_b[0]_PORT_A_write_enable_reg = DFFE(LD2_q_b[0]_PORT_A_write_enable, LD2_q_b[0]_clock_0, , , );
|
| 21347 |
|
|
LD2_q_b[0]_PORT_B_read_enable = VCC;
|
| 21348 |
|
|
LD2_q_b[0]_PORT_B_read_enable_reg = DFFE(LD2_q_b[0]_PORT_B_read_enable, LD2_q_b[0]_clock_1, , , );
|
| 21349 |
|
|
LD2_q_b[0]_clock_0 = E1__clk0;
|
| 21350 |
|
|
LD2_q_b[0]_clock_1 = E1__clk0;
|
| 21351 |
|
|
LD2_q_b[0]_PORT_B_data_out = MEMORY(LD2_q_b[0]_PORT_A_data_in_reg, , LD2_q_b[0]_PORT_A_address_reg, LD2_q_b[0]_PORT_B_address_reg, LD2_q_b[0]_PORT_A_write_enable_reg, LD2_q_b[0]_PORT_B_read_enable_reg, , , LD2_q_b[0]_clock_0, LD2_q_b[0]_clock_1, , , , );
|
| 21352 |
|
|
LD2_q_b[0] = LD2_q_b[0]_PORT_B_data_out[0];
|
| 21353 |
|
|
|
| 21354 |
|
|
|
| 21355 |
|
|
--GD1_dout_iv_1_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_21
|
| 21356 |
|
|
--operation mode is normal
|
| 21357 |
|
|
|
| 21358 |
|
|
GD1_dout_iv_1_21 = FD1_N_20_i_0_s3 & LD1_q_b[21] # !GD1_dout_iv_1_a[21];
|
| 21359 |
|
|
|
| 21360 |
|
|
|
| 21361 |
|
|
--CD1_res_7_0_0_a_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_18
|
| 21362 |
|
|
--operation mode is normal
|
| 21363 |
|
|
|
| 21364 |
|
|
CD1_res_7_0_0_a_18 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_19;
|
| 21365 |
|
|
|
| 21366 |
|
|
|
| 21367 |
|
|
--GD1_dout_iv_1_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_22
|
| 21368 |
|
|
--operation mode is normal
|
| 21369 |
|
|
|
| 21370 |
|
|
GD1_dout_iv_1_22 = FD1_N_20_i_0_s3 & LD1_q_b[22] # !GD1_dout_iv_1_a[22];
|
| 21371 |
|
|
|
| 21372 |
|
|
|
| 21373 |
|
|
--CD1_res_7_0_0_a_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_19
|
| 21374 |
|
|
--operation mode is normal
|
| 21375 |
|
|
|
| 21376 |
|
|
CD1_res_7_0_0_a_19 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_20;
|
| 21377 |
|
|
|
| 21378 |
|
|
|
| 21379 |
|
|
--GD1_dout_iv_1_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_25
|
| 21380 |
|
|
--operation mode is normal
|
| 21381 |
|
|
|
| 21382 |
|
|
GD1_dout_iv_1_25 = FD1_N_20_i_0_s3 & LD1_q_b[25] # !GD1_dout_iv_1_a[25];
|
| 21383 |
|
|
|
| 21384 |
|
|
|
| 21385 |
|
|
--CD1_res_7_0_0_a_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_22
|
| 21386 |
|
|
--operation mode is normal
|
| 21387 |
|
|
|
| 21388 |
|
|
CD1_res_7_0_0_a_22 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_23;
|
| 21389 |
|
|
|
| 21390 |
|
|
|
| 21391 |
|
|
--F1_dout_25 is mips_sys:isys|mips_dvc:imips_dvc|dout_25
|
| 21392 |
|
|
--operation mode is normal
|
| 21393 |
|
|
|
| 21394 |
|
|
F1_dout_25_lut_out = K1_cntr_25 & F1_dout_0_0_a3_4[0] # F1_cmd[25] & F1_dout_0_0_a3_3[0] # !K1_cntr_25 & F1_cmd[25] & F1_dout_0_0_a3_3[0];
|
| 21395 |
|
|
F1_dout_25 = DFFEAS(F1_dout_25_lut_out, E1__clk0, VCC, , , , , , );
|
| 21396 |
|
|
|
| 21397 |
|
|
|
| 21398 |
|
|
--DB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_25
|
| 21399 |
|
|
--operation mode is normal
|
| 21400 |
|
|
|
| 21401 |
|
|
DB1_r32_o_25_lut_out = WB03L1;
|
| 21402 |
|
|
DB1_r32_o_25 = DFFEAS(DB1_r32_o_25_lut_out, E1__clk0, VCC, , , , , , );
|
| 21403 |
|
|
|
| 21404 |
|
|
|
| 21405 |
|
|
--BB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_25
|
| 21406 |
|
|
--operation mode is normal
|
| 21407 |
|
|
|
| 21408 |
|
|
BB1_r32_o_25_lut_out = AB1_r32_o_23;
|
| 21409 |
|
|
BB1_r32_o_25 = DFFEAS(BB1_r32_o_25_lut_out, E1__clk0, VCC, , , , , , );
|
| 21410 |
|
|
|
| 21411 |
|
|
|
| 21412 |
|
|
--GD1_dout_iv_1_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_26
|
| 21413 |
|
|
--operation mode is normal
|
| 21414 |
|
|
|
| 21415 |
|
|
GD1_dout_iv_1_26 = FD1_N_20_i_0_s3 & LD1_q_b[26] # !GD1_dout_iv_1_a[26];
|
| 21416 |
|
|
|
| 21417 |
|
|
|
| 21418 |
|
|
--CD1_res_7_0_0_a_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_23
|
| 21419 |
|
|
--operation mode is normal
|
| 21420 |
|
|
|
| 21421 |
|
|
CD1_res_7_0_0_a_23 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_24;
|
| 21422 |
|
|
|
| 21423 |
|
|
|
| 21424 |
|
|
--F1_dout_26 is mips_sys:isys|mips_dvc:imips_dvc|dout_26
|
| 21425 |
|
|
--operation mode is normal
|
| 21426 |
|
|
|
| 21427 |
|
|
F1_dout_26_lut_out = K1_cntr_26 & F1_dout_0_0_a3_4[0] # F1_cmd[26] & F1_dout_0_0_a3_3[0] # !K1_cntr_26 & F1_cmd[26] & F1_dout_0_0_a3_3[0];
|
| 21428 |
|
|
F1_dout_26 = DFFEAS(F1_dout_26_lut_out, E1__clk0, VCC, , , , , , );
|
| 21429 |
|
|
|
| 21430 |
|
|
|
| 21431 |
|
|
--DB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_26
|
| 21432 |
|
|
--operation mode is normal
|
| 21433 |
|
|
|
| 21434 |
|
|
DB1_r32_o_26_lut_out = WB13L1;
|
| 21435 |
|
|
DB1_r32_o_26 = DFFEAS(DB1_r32_o_26_lut_out, E1__clk0, VCC, , , , , , );
|
| 21436 |
|
|
|
| 21437 |
|
|
|
| 21438 |
|
|
--BB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_26
|
| 21439 |
|
|
--operation mode is normal
|
| 21440 |
|
|
|
| 21441 |
|
|
BB1_r32_o_26_lut_out = AB1_r32_o_24;
|
| 21442 |
|
|
BB1_r32_o_26 = DFFEAS(BB1_r32_o_26_lut_out, E1__clk0, VCC, , , , , , );
|
| 21443 |
|
|
|
| 21444 |
|
|
|
| 21445 |
|
|
--GD1_dout_iv_1_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_29
|
| 21446 |
|
|
--operation mode is normal
|
| 21447 |
|
|
|
| 21448 |
|
|
GD1_dout_iv_1_29 = FD1_N_20_i_0_s3 & LD1_q_b[29] # !GD1_dout_iv_1_a[29];
|
| 21449 |
|
|
|
| 21450 |
|
|
|
| 21451 |
|
|
--GD1_dout_iv_1_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_17
|
| 21452 |
|
|
--operation mode is normal
|
| 21453 |
|
|
|
| 21454 |
|
|
GD1_dout_iv_1_17 = FD1_N_20_i_0_s3 & LD1_q_b[17] # !GD1_dout_iv_1_a[17];
|
| 21455 |
|
|
|
| 21456 |
|
|
|
| 21457 |
|
|
--CD1_res_7_0_0_a_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_14
|
| 21458 |
|
|
--operation mode is normal
|
| 21459 |
|
|
|
| 21460 |
|
|
CD1_res_7_0_0_a_14 = DC1_ext_ctl_o_2 & !DC1_ext_ctl_o_1 & !DC1_ext_ctl_o_0 # !DC1_ext_ctl_o_2 & DC1_ext_ctl_o_0;
|
| 21461 |
|
|
|
| 21462 |
|
|
|
| 21463 |
|
|
--GD1_dout_iv_1_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_18
|
| 21464 |
|
|
--operation mode is normal
|
| 21465 |
|
|
|
| 21466 |
|
|
GD1_dout_iv_1_18 = FD1_N_20_i_0_s3 & LD1_q_b[18] # !GD1_dout_iv_1_a[18];
|
| 21467 |
|
|
|
| 21468 |
|
|
|
| 21469 |
|
|
--CD1_res_7_0_0_a_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_15
|
| 21470 |
|
|
--operation mode is normal
|
| 21471 |
|
|
|
| 21472 |
|
|
CD1_res_7_0_0_a_15 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_16;
|
| 21473 |
|
|
|
| 21474 |
|
|
|
| 21475 |
|
|
--VD1_un134_hilo_combout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[8]
|
| 21476 |
|
|
--operation mode is arithmetic
|
| 21477 |
|
|
|
| 21478 |
|
|
VD1_un134_hilo_combout[8]_carry_eqn = VD1_un134_hilo_cout[6];
|
| 21479 |
|
|
VD1_un134_hilo_combout[8] = VD1_hilo_8 $ (!VD1_un134_hilo_combout[8]_carry_eqn);
|
| 21480 |
|
|
|
| 21481 |
|
|
--VD1_un134_hilo_cout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[8]
|
| 21482 |
|
|
--operation mode is arithmetic
|
| 21483 |
|
|
|
| 21484 |
|
|
VD1_un134_hilo_cout[8] = CARRY(VD1_hilo_8 & VD1_hilo_9 & !VD1_un134_hilo_cout[6]);
|
| 21485 |
|
|
|
| 21486 |
|
|
|
| 21487 |
|
|
--VD1_nop2_reged[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[9]
|
| 21488 |
|
|
--operation mode is arithmetic
|
| 21489 |
|
|
|
| 21490 |
|
|
VD1_nop2_reged[9]_carry_eqn = VD1_nop2_reged_cout[7];
|
| 21491 |
|
|
VD1_nop2_reged[9] = VD1_op2_reged[9] $ (VD1_op2_reged[8] # VD1_nop2_reged[9]_carry_eqn);
|
| 21492 |
|
|
|
| 21493 |
|
|
--VD1_nop2_reged_cout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[9]
|
| 21494 |
|
|
--operation mode is arithmetic
|
| 21495 |
|
|
|
| 21496 |
|
|
VD1_nop2_reged_cout[9] = CARRY(!VD1_op2_reged[9] & !VD1_op2_reged[8] & !VD1_nop2_reged_cout[7]);
|
| 21497 |
|
|
|
| 21498 |
|
|
|
| 21499 |
|
|
--VD1_hilo_37_iv_0_1_a[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[40]
|
| 21500 |
|
|
--operation mode is normal
|
| 21501 |
|
|
|
| 21502 |
|
|
VD1_hilo_37_iv_0_1_a[40] = VD1_hilo_8 & !VD1_hilo_40 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_hilo_8 & VD1_hilo_0_sqmuxa # !VD1_hilo_40 & VD1_hilo_37_iv_0_o3_2[34];
|
| 21503 |
|
|
|
| 21504 |
|
|
|
| 21505 |
|
|
--VD1_hilo_24_add8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add8
|
| 21506 |
|
|
--operation mode is arithmetic
|
| 21507 |
|
|
|
| 21508 |
|
|
VD1_hilo_24_add8_carry_eqn = VD1_hilo_24_carry_7;
|
| 21509 |
|
|
VD1_hilo_24_add8 = VD1_hilo_39 $ VD1_un1_op2_reged_1_combout[8] $ !VD1_hilo_24_add8_carry_eqn;
|
| 21510 |
|
|
|
| 21511 |
|
|
--VD1_hilo_24_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_8
|
| 21512 |
|
|
--operation mode is arithmetic
|
| 21513 |
|
|
|
| 21514 |
|
|
VD1_hilo_24_carry_8 = CARRY(VD1_hilo_39 & VD1_un1_op2_reged_1_combout[8] # !VD1_hilo_24_carry_7 # !VD1_hilo_39 & VD1_un1_op2_reged_1_combout[8] & !VD1_hilo_24_carry_7);
|
| 21515 |
|
|
|
| 21516 |
|
|
|
| 21517 |
|
|
--YB1_rd_sel_2_0_0_a3_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_a3_0[0]
|
| 21518 |
|
|
--operation mode is normal
|
| 21519 |
|
|
|
| 21520 |
|
|
YB1_rd_sel_2_0_0_a3_0[0] = YB1_alu_func_2_0_0_a2_0[1] & !KE1_q_a[6] & YB1_rd_sel_2_0_0_a3_0_a[0] & YB1_alu_func_2_0_0_a2_1_x[3];
|
| 21521 |
|
|
|
| 21522 |
|
|
|
| 21523 |
|
|
--YB1_rd_sel_2_0_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_0_a[1]
|
| 21524 |
|
|
--operation mode is normal
|
| 21525 |
|
|
|
| 21526 |
|
|
YB1_rd_sel_2_0_0_0_a[1] = KE1_q_a[3] & KE1_q_a[2] & !KE1_q_a[4] # !KE1_q_a[3] & KE1_q_a[7];
|
| 21527 |
|
|
|
| 21528 |
|
|
|
| 21529 |
|
|
--YB1_alu_we_1_0_0_a3_1_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3_1_0[0]
|
| 21530 |
|
|
--operation mode is normal
|
| 21531 |
|
|
|
| 21532 |
|
|
YB1_alu_we_1_0_0_a3_1_0[0] = YB1_alu_we_1_0_0_a3_1_0_a[0] & !GE1_q_a[2] & GE1_q_a[1] # !GE1_q_a[3];
|
| 21533 |
|
|
|
| 21534 |
|
|
|
| 21535 |
|
|
--F1_cmd[20] is mips_sys:isys|mips_dvc:imips_dvc|cmd[20]
|
| 21536 |
|
|
--operation mode is normal
|
| 21537 |
|
|
|
| 21538 |
|
|
F1_cmd[20]_lut_out = CB1_r32_o_20;
|
| 21539 |
|
|
F1_cmd[20] = DFFEAS(F1_cmd[20]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 21540 |
|
|
|
| 21541 |
|
|
|
| 21542 |
|
|
--GD1_dout_iv_1_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_20
|
| 21543 |
|
|
--operation mode is normal
|
| 21544 |
|
|
|
| 21545 |
|
|
GD1_dout_iv_1_20 = FD1_N_20_i_0_s3 & LD1_q_b[20] # !GD1_dout_iv_1_a[20];
|
| 21546 |
|
|
|
| 21547 |
|
|
|
| 21548 |
|
|
--AD1_un1_rst_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un1_rst_2
|
| 21549 |
|
|
--operation mode is normal
|
| 21550 |
|
|
|
| 21551 |
|
|
AD1_un1_rst_2 = !AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & AD1_un1_rst_2_a & AD1_un1_rst_2_s;
|
| 21552 |
|
|
|
| 21553 |
|
|
|
| 21554 |
|
|
--WB76L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_0_|lpm_latch:U1|q[0]~56
|
| 21555 |
|
|
--operation mode is normal
|
| 21556 |
|
|
|
| 21557 |
|
|
WB76L1 = !AD1_CurrState_Sreg0[2] & AD1_un1_rst_2 & !AD1_delay_counter_Sreg0[0] # !AD1_un1_rst_2 & WB76L1;
|
| 21558 |
|
|
|
| 21559 |
|
|
|
| 21560 |
|
|
--AD1_un4_next_delay_counter_Sreg0_sum5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum5
|
| 21561 |
|
|
--operation mode is normal
|
| 21562 |
|
|
|
| 21563 |
|
|
AD1_un4_next_delay_counter_Sreg0_sum5 = AD1_delay_counter_Sreg0[5] $ (!AD1_delay_counter_Sreg0[4] & !AD1_un4_next_delay_counter_Sreg0_c3);
|
| 21564 |
|
|
|
| 21565 |
|
|
|
| 21566 |
|
|
--WB27L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_|lpm_latch:U1|q[0]~14
|
| 21567 |
|
|
--operation mode is normal
|
| 21568 |
|
|
|
| 21569 |
|
|
WB27L1 = AD1_CurrState_Sreg0[2] # AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum5 # !AD1_un1_rst_2 & WB27L1;
|
| 21570 |
|
|
|
| 21571 |
|
|
|
| 21572 |
|
|
--YB1_alu_func_2_0_0_a2_2[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_2[4]
|
| 21573 |
|
|
--operation mode is normal
|
| 21574 |
|
|
|
| 21575 |
|
|
YB1_alu_func_2_0_0_a2_2[4] = !KE1_q_a[2] & !KE1_q_a[6] & GE1_q_a[2] & YB1_alu_func_2_0_0_a2_1_x[3];
|
| 21576 |
|
|
|
| 21577 |
|
|
|
| 21578 |
|
|
--YB1_alu_func_2_0_0_1_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1_a[1]
|
| 21579 |
|
|
--operation mode is normal
|
| 21580 |
|
|
|
| 21581 |
|
|
YB1_alu_func_2_0_0_1_a[1] = GE1_q_a[1] & !YB1_alu_func_2_0_0_a2_2_x[1] # !YB1_alu_func_2_0_0_a2_0[1] # !GE1_q_a[1] & !YB1_alu_func_2_0_0_a2_x[0];
|
| 21582 |
|
|
|
| 21583 |
|
|
|
| 21584 |
|
|
--YB1_alu_func_2_i_m3_0_a3_5_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a3_5_a[2]
|
| 21585 |
|
|
--operation mode is normal
|
| 21586 |
|
|
|
| 21587 |
|
|
YB1_alu_func_2_i_m3_0_a3_5_a[2] = GE1_q_a[1] & !KE1_q_a[3] & !KE1_q_a[4] & !GE1_q_a[4];
|
| 21588 |
|
|
|
| 21589 |
|
|
|
| 21590 |
|
|
--YB1_alu_func_2_i_m3_0_a3_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a3_0_x[2]
|
| 21591 |
|
|
--operation mode is normal
|
| 21592 |
|
|
|
| 21593 |
|
|
YB1_alu_func_2_i_m3_0_a3_0_x[2] = KE1_q_a[5] & KE1_q_a[3] $ !KE1_q_a[4];
|
| 21594 |
|
|
|
| 21595 |
|
|
|
| 21596 |
|
|
--YB1_alu_func_2_i_m3_0_2_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_2_a[2]
|
| 21597 |
|
|
--operation mode is normal
|
| 21598 |
|
|
|
| 21599 |
|
|
YB1_alu_func_2_i_m3_0_2_a[2] = !KE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[0] # YB1_cmp_ctl_2_0_0_a2_1[0] & WB93L2;
|
| 21600 |
|
|
|
| 21601 |
|
|
|
| 21602 |
|
|
--YB1_muxa_ctl_2_0_0_a3_1[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a3_1[0]
|
| 21603 |
|
|
--operation mode is normal
|
| 21604 |
|
|
|
| 21605 |
|
|
YB1_muxa_ctl_2_0_0_a3_1[0] = !KE1_q_a[4] & !KE1_q_a[5] & !KE1_q_a[7] & YB1_alu_func_2_0_0_a2_0_x[0];
|
| 21606 |
|
|
|
| 21607 |
|
|
|
| 21608 |
|
|
--YB1_muxb_ctl_2_0_0_a3_0_0_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_a3_0_0_x[0]
|
| 21609 |
|
|
--operation mode is normal
|
| 21610 |
|
|
|
| 21611 |
|
|
YB1_muxb_ctl_2_0_0_a3_0_0_x[0] = YB1_alu_func_2_0_0_a2_0[1] & YB1_muxa_ctl_2_0_0_o2_0[1];
|
| 21612 |
|
|
|
| 21613 |
|
|
|
| 21614 |
|
|
--YB1_muxb_ctl_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_a[0]
|
| 21615 |
|
|
--operation mode is normal
|
| 21616 |
|
|
|
| 21617 |
|
|
YB1_muxb_ctl_2_0_0_a[0] = YB1_alu_func_2_0_0_a2_2_x[1] & !YB1_alu_func_2_0_0_a2_3_x[0] & !YB1_alu_func_2_0_0_a2_3[1] # !WB85L1 # !YB1_alu_func_2_0_0_a2_2_x[1] & !YB1_alu_func_2_0_0_a2_3[1] # !WB85L1;
|
| 21618 |
|
|
|
| 21619 |
|
|
|
| 21620 |
|
|
--YB1_muxb_ctl_2_0_0_0_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_0_Z[1]
|
| 21621 |
|
|
--operation mode is normal
|
| 21622 |
|
|
|
| 21623 |
|
|
YB1_muxb_ctl_2_0_0_0_Z[1] = !KE1_q_a[7] & !KE1_q_a[4] & !KE1_q_a[3] & !YB1_muxb_ctl_2_0_0_0_a[1];
|
| 21624 |
|
|
|
| 21625 |
|
|
|
| 21626 |
|
|
--YB1_muxb_ctl_2_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_a[1]
|
| 21627 |
|
|
--operation mode is normal
|
| 21628 |
|
|
|
| 21629 |
|
|
YB1_muxb_ctl_2_0_0_a[1] = KE1_q_a[7] & KE1_q_a[2] & !KE1_q_a[4] # !KE1_q_a[3];
|
| 21630 |
|
|
|
| 21631 |
|
|
|
| 21632 |
|
|
--YB1_ext_ctl_2_i_m3_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_a[1]
|
| 21633 |
|
|
--operation mode is normal
|
| 21634 |
|
|
|
| 21635 |
|
|
YB1_ext_ctl_2_i_m3_0_a[1] = !KE1_q_a[7] & KE1_q_a[3] # WB15L1 & YB1_fsm_dly_2_0_0_o2_x[2];
|
| 21636 |
|
|
|
| 21637 |
|
|
|
| 21638 |
|
|
--YB1_ext_ctl_2_0_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a[2]
|
| 21639 |
|
|
--operation mode is normal
|
| 21640 |
|
|
|
| 21641 |
|
|
YB1_ext_ctl_2_0_0_a[2] = !YB1_ext_ctl_2_0_0_a3_1_x[2] & YB1_alu_func_2_0_0_o2_x[3] # !YB1_ext_ctl_2_0_0_a2_2_x[2] # !YB1_ext_ctl_2_0_0_a2_0_x[2];
|
| 21642 |
|
|
|
| 21643 |
|
|
|
| 21644 |
|
|
--YB1_ext_ctl_2_i_m3_0_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_a_x[0]
|
| 21645 |
|
|
--operation mode is normal
|
| 21646 |
|
|
|
| 21647 |
|
|
YB1_ext_ctl_2_i_m3_0_a_x[0] = !KE1_q_a[3] & !WB05L2 # !YB1_cmp_ctl_2_0_0_a2_1[0];
|
| 21648 |
|
|
|
| 21649 |
|
|
|
| 21650 |
|
|
--YB1_ext_ctl_2_i_m3_0_2[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_2[0]
|
| 21651 |
|
|
--operation mode is normal
|
| 21652 |
|
|
|
| 21653 |
|
|
YB1_ext_ctl_2_i_m3_0_2[0] = YB1_ext_ctl_2_i_m3_0_0_Z[0] # !KE1_q_a[7] & !KE1_q_a[4] & !YB1_ext_ctl_2_i_m3_0_2_a[0];
|
| 21654 |
|
|
|
| 21655 |
|
|
|
| 21656 |
|
|
--YB1_muxa_ctl_2_0_0_0_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_0_Z[1]
|
| 21657 |
|
|
--operation mode is normal
|
| 21658 |
|
|
|
| 21659 |
|
|
YB1_muxa_ctl_2_0_0_0_Z[1] = KE1_q_a[7] & YB1_muxa_ctl_2_0_0_a2_x[1] # !KE1_q_a[3] # !KE1_q_a[7] & !KE1_q_a[3] & YB1_muxa_ctl_2_0_0_0_a[1];
|
| 21660 |
|
|
|
| 21661 |
|
|
|
| 21662 |
|
|
--YB1_muxa_ctl_2_0_0_2_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_2_a[1]
|
| 21663 |
|
|
--operation mode is normal
|
| 21664 |
|
|
|
| 21665 |
|
|
YB1_muxa_ctl_2_0_0_2_a[1] = GE1_q_a[4] & !YB1_alu_func_2_0_0_o2_x[3] # !YB1_alu_func_2_0_0_a2_2_x[1] # !GE1_q_a[4] & !YB1_muxa_ctl_2_0_0_o2_0[1] & !YB1_alu_func_2_0_0_o2_x[3] # !YB1_alu_func_2_0_0_a2_2_x[1];
|
| 21666 |
|
|
|
| 21667 |
|
|
|
| 21668 |
|
|
--ED1_r32_o_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_22
|
| 21669 |
|
|
--operation mode is normal
|
| 21670 |
|
|
|
| 21671 |
|
|
ED1_r32_o_22_lut_out = JE1_q_a[6];
|
| 21672 |
|
|
ED1_r32_o_22 = DFFEAS(ED1_r32_o_22_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 21673 |
|
|
|
| 21674 |
|
|
|
| 21675 |
|
|
--ED1_r32_o_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_21
|
| 21676 |
|
|
--operation mode is normal
|
| 21677 |
|
|
|
| 21678 |
|
|
ED1_r32_o_21_lut_out = JE1_q_a[5];
|
| 21679 |
|
|
ED1_r32_o_21 = DFFEAS(ED1_r32_o_21_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 21680 |
|
|
|
| 21681 |
|
|
|
| 21682 |
|
|
--ED1_r32_o_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_23
|
| 21683 |
|
|
--operation mode is normal
|
| 21684 |
|
|
|
| 21685 |
|
|
ED1_r32_o_23_lut_out = JE1_q_a[7];
|
| 21686 |
|
|
ED1_r32_o_23 = DFFEAS(ED1_r32_o_23_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 21687 |
|
|
|
| 21688 |
|
|
|
| 21689 |
|
|
--ED1_r32_o_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_24
|
| 21690 |
|
|
--operation mode is normal
|
| 21691 |
|
|
|
| 21692 |
|
|
ED1_r32_o_24_lut_out = KE1_q_a[0];
|
| 21693 |
|
|
ED1_r32_o_24 = DFFEAS(ED1_r32_o_24_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 21694 |
|
|
|
| 21695 |
|
|
|
| 21696 |
|
|
--FD1_un14_qa_NE is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qa_NE
|
| 21697 |
|
|
--operation mode is normal
|
| 21698 |
|
|
|
| 21699 |
|
|
FD1_un14_qa_NE = FD1_un14_qa_NE_1 # FD1_un14_qa_NE_a # FD1_r_wraddress[4] $ FD1_r_rdaddress_a[4];
|
| 21700 |
|
|
|
| 21701 |
|
|
|
| 21702 |
|
|
--FD1_N_18_i_0_s3_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_18_i_0_s3_a
|
| 21703 |
|
|
--operation mode is normal
|
| 21704 |
|
|
|
| 21705 |
|
|
FD1_N_18_i_0_s3_a = !FD1_un23_qa_i_0_a2 & WD1_un30_mux_fw # YD1_un17_mux_fw_NE # !MC1_wb_we_o_0;
|
| 21706 |
|
|
|
| 21707 |
|
|
|
| 21708 |
|
|
--FD1_N_14_i_0_s2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_14_i_0_s2
|
| 21709 |
|
|
--operation mode is normal
|
| 21710 |
|
|
|
| 21711 |
|
|
FD1_N_14_i_0_s2 = !FD1_un23_qa_i_0_a2 & !FD1_un14_qa_NE & !FD1_N_14_i_0_s2_a & !YD1_mux_fw_1;
|
| 21712 |
|
|
|
| 21713 |
|
|
|
| 21714 |
|
|
--FD1_r_rdaddress_a_0_x[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[0]
|
| 21715 |
|
|
--operation mode is normal
|
| 21716 |
|
|
|
| 21717 |
|
|
FD1_r_rdaddress_a_0_x[0] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[0] # !AD1_CurrState_Sreg0_2 & JE1_q_a[5];
|
| 21718 |
|
|
|
| 21719 |
|
|
|
| 21720 |
|
|
--FD1_r_rdaddress_a_0_x[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[1]
|
| 21721 |
|
|
--operation mode is normal
|
| 21722 |
|
|
|
| 21723 |
|
|
FD1_r_rdaddress_a_0_x[1] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[1] # !AD1_CurrState_Sreg0_2 & JE1_q_a[6];
|
| 21724 |
|
|
|
| 21725 |
|
|
|
| 21726 |
|
|
--FD1_r_rdaddress_a_0_x[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[2]
|
| 21727 |
|
|
--operation mode is normal
|
| 21728 |
|
|
|
| 21729 |
|
|
FD1_r_rdaddress_a_0_x[2] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[2] # !AD1_CurrState_Sreg0_2 & JE1_q_a[7];
|
| 21730 |
|
|
|
| 21731 |
|
|
|
| 21732 |
|
|
--FD1_r_rdaddress_a_0_x[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[3]
|
| 21733 |
|
|
--operation mode is normal
|
| 21734 |
|
|
|
| 21735 |
|
|
FD1_r_rdaddress_a_0_x[3] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[3] # !AD1_CurrState_Sreg0_2 & KE1_q_a[0];
|
| 21736 |
|
|
|
| 21737 |
|
|
|
| 21738 |
|
|
--FD1_r_rdaddress_a_0_x[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[4]
|
| 21739 |
|
|
--operation mode is normal
|
| 21740 |
|
|
|
| 21741 |
|
|
FD1_r_rdaddress_a_0_x[4] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[4] # !AD1_CurrState_Sreg0_2 & KE1_q_a[1];
|
| 21742 |
|
|
|
| 21743 |
|
|
|
| 21744 |
|
|
--YD1_un17_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un17_mux_fw_NE_1
|
| 21745 |
|
|
--operation mode is normal
|
| 21746 |
|
|
|
| 21747 |
|
|
YD1_un17_mux_fw_NE_1 = ED1_r32_o_22 & ED1_r32_o_21 $ NB1_r5_o_0 # !NB1_r5_o_1 # !ED1_r32_o_22 & NB1_r5_o_1 # ED1_r32_o_21 $ NB1_r5_o_0;
|
| 21748 |
|
|
|
| 21749 |
|
|
|
| 21750 |
|
|
--YD1_un17_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un17_mux_fw_NE_a
|
| 21751 |
|
|
--operation mode is normal
|
| 21752 |
|
|
|
| 21753 |
|
|
YD1_un17_mux_fw_NE_a = ED1_r32_o_23 & ED1_r32_o_24 $ NB1_r5_o_3 # !NB1_r5_o_2 # !ED1_r32_o_23 & NB1_r5_o_2 # ED1_r32_o_24 $ NB1_r5_o_3;
|
| 21754 |
|
|
|
| 21755 |
|
|
|
| 21756 |
|
|
--YD1_un1_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un1_mux_fw_NE
|
| 21757 |
|
|
--operation mode is normal
|
| 21758 |
|
|
|
| 21759 |
|
|
YD1_un1_mux_fw_NE = YD1_un1_mux_fw_NE_1 # YD1_un1_mux_fw_NE_a # MB1_r5_o_4 $ ED1_r32_o_25;
|
| 21760 |
|
|
|
| 21761 |
|
|
|
| 21762 |
|
|
--GD1_dout_iv_1_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_10
|
| 21763 |
|
|
--operation mode is normal
|
| 21764 |
|
|
|
| 21765 |
|
|
GD1_dout_iv_1_10 = FD1_N_20_i_0_s3 & LD1_q_b[10] # !GD1_dout_iv_1_a[10];
|
| 21766 |
|
|
|
| 21767 |
|
|
|
| 21768 |
|
|
--GD1_dout_iv_1_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_15
|
| 21769 |
|
|
--operation mode is normal
|
| 21770 |
|
|
|
| 21771 |
|
|
GD1_dout_iv_1_15 = FD1_N_20_i_0_s3 & LD1_q_b[15] # !GD1_dout_iv_1_a[15];
|
| 21772 |
|
|
|
| 21773 |
|
|
|
| 21774 |
|
|
--F1_dout_15 is mips_sys:isys|mips_dvc:imips_dvc|dout_15
|
| 21775 |
|
|
--operation mode is normal
|
| 21776 |
|
|
|
| 21777 |
|
|
F1_dout_15_lut_out = K1_cntr_15 & F1_dout_0_0_a3_4[0] # F1_cmd[15] & F1_dout_0_0_a3_3[0] # !K1_cntr_15 & F1_cmd[15] & F1_dout_0_0_a3_3[0];
|
| 21778 |
|
|
F1_dout_15 = DFFEAS(F1_dout_15_lut_out, E1__clk0, VCC, , , , , , );
|
| 21779 |
|
|
|
| 21780 |
|
|
|
| 21781 |
|
|
--DB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_15
|
| 21782 |
|
|
--operation mode is normal
|
| 21783 |
|
|
|
| 21784 |
|
|
DB1_r32_o_15_lut_out = WB02L1;
|
| 21785 |
|
|
DB1_r32_o_15 = DFFEAS(DB1_r32_o_15_lut_out, E1__clk0, VCC, , , , , , );
|
| 21786 |
|
|
|
| 21787 |
|
|
|
| 21788 |
|
|
--BB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_15
|
| 21789 |
|
|
--operation mode is normal
|
| 21790 |
|
|
|
| 21791 |
|
|
BB1_r32_o_15_lut_out = AB1_r32_o_13;
|
| 21792 |
|
|
BB1_r32_o_15 = DFFEAS(BB1_r32_o_15_lut_out, E1__clk0, VCC, , , , , , );
|
| 21793 |
|
|
|
| 21794 |
|
|
|
| 21795 |
|
|
--GD1_dout_iv_1_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_27
|
| 21796 |
|
|
--operation mode is normal
|
| 21797 |
|
|
|
| 21798 |
|
|
GD1_dout_iv_1_27 = FD1_N_20_i_0_s3 & LD1_q_b[27] # !GD1_dout_iv_1_a[27];
|
| 21799 |
|
|
|
| 21800 |
|
|
|
| 21801 |
|
|
--CD1_res_7_0_0_a_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_24
|
| 21802 |
|
|
--operation mode is normal
|
| 21803 |
|
|
|
| 21804 |
|
|
CD1_res_7_0_0_a_24 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_25;
|
| 21805 |
|
|
|
| 21806 |
|
|
|
| 21807 |
|
|
--F1_dout_27 is mips_sys:isys|mips_dvc:imips_dvc|dout_27
|
| 21808 |
|
|
--operation mode is normal
|
| 21809 |
|
|
|
| 21810 |
|
|
F1_dout_27_lut_out = K1_cntr_27 & F1_dout_0_0_a3_4[0] # F1_cmd[27] & F1_dout_0_0_a3_3[0] # !K1_cntr_27 & F1_cmd[27] & F1_dout_0_0_a3_3[0];
|
| 21811 |
|
|
F1_dout_27 = DFFEAS(F1_dout_27_lut_out, E1__clk0, VCC, , , , , , );
|
| 21812 |
|
|
|
| 21813 |
|
|
|
| 21814 |
|
|
--DB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_27
|
| 21815 |
|
|
--operation mode is normal
|
| 21816 |
|
|
|
| 21817 |
|
|
DB1_r32_o_27_lut_out = WB23L1;
|
| 21818 |
|
|
DB1_r32_o_27 = DFFEAS(DB1_r32_o_27_lut_out, E1__clk0, VCC, , , , , , );
|
| 21819 |
|
|
|
| 21820 |
|
|
|
| 21821 |
|
|
--BB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_27
|
| 21822 |
|
|
--operation mode is normal
|
| 21823 |
|
|
|
| 21824 |
|
|
BB1_r32_o_27_lut_out = AB1_r32_o_25;
|
| 21825 |
|
|
BB1_r32_o_27 = DFFEAS(BB1_r32_o_27_lut_out, E1__clk0, VCC, , , , , , );
|
| 21826 |
|
|
|
| 21827 |
|
|
|
| 21828 |
|
|
--GD1_dout_iv_1_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_19
|
| 21829 |
|
|
--operation mode is normal
|
| 21830 |
|
|
|
| 21831 |
|
|
GD1_dout_iv_1_19 = FD1_N_20_i_0_s3 & LD1_q_b[19] # !GD1_dout_iv_1_a[19];
|
| 21832 |
|
|
|
| 21833 |
|
|
|
| 21834 |
|
|
--CD1_res_7_0_0_a_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_16
|
| 21835 |
|
|
--operation mode is normal
|
| 21836 |
|
|
|
| 21837 |
|
|
CD1_res_7_0_0_a_16 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_17;
|
| 21838 |
|
|
|
| 21839 |
|
|
|
| 21840 |
|
|
--CD1_res_7_0_0_a_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_17
|
| 21841 |
|
|
--operation mode is normal
|
| 21842 |
|
|
|
| 21843 |
|
|
CD1_res_7_0_0_a_17 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_18;
|
| 21844 |
|
|
|
| 21845 |
|
|
|
| 21846 |
|
|
--VD1_count[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[2]
|
| 21847 |
|
|
--operation mode is arithmetic
|
| 21848 |
|
|
|
| 21849 |
|
|
VD1_count[2]_carry_eqn = VD1_count_cout[1];
|
| 21850 |
|
|
VD1_count[2]_lut_out = VD1_count[2] $ (!VD1_count[2]_carry_eqn);
|
| 21851 |
|
|
VD1_count[2] = DFFEAS(VD1_count[2]_lut_out, E1__clk0, VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
|
| 21852 |
|
|
|
| 21853 |
|
|
--VD1_count_cout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[2]
|
| 21854 |
|
|
--operation mode is arithmetic
|
| 21855 |
|
|
|
| 21856 |
|
|
VD1_count_cout[2] = CARRY(VD1_count[2] & !VD1_count_cout[1]);
|
| 21857 |
|
|
|
| 21858 |
|
|
|
| 21859 |
|
|
--VD1_over_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_30
|
| 21860 |
|
|
--operation mode is arithmetic
|
| 21861 |
|
|
|
| 21862 |
|
|
VD1_over_carry_30 = CARRY(VD1_b_o_iv_30 & PD1_a_o_30 & !VD1_over_carry_29 # !VD1_b_o_iv_30 & PD1_a_o_30 # !VD1_over_carry_29);
|
| 21863 |
|
|
|
| 21864 |
|
|
|
| 21865 |
|
|
--VD1_eqz_2_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_17
|
| 21866 |
|
|
--operation mode is normal
|
| 21867 |
|
|
|
| 21868 |
|
|
VD1_eqz_2_17 = !VD1_hilo_40 & !VD1_hilo_52 & !VD1_hilo_38 & !VD1_hilo_39;
|
| 21869 |
|
|
|
| 21870 |
|
|
|
| 21871 |
|
|
--VD1_eqz_2_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_21
|
| 21872 |
|
|
--operation mode is normal
|
| 21873 |
|
|
|
| 21874 |
|
|
VD1_eqz_2_21 = !VD1_hilo_45 & !VD1_hilo_59 & !VD1_hilo_51 & !VD1_hilo_53;
|
| 21875 |
|
|
|
| 21876 |
|
|
|
| 21877 |
|
|
--VD1_eqz_2_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_27
|
| 21878 |
|
|
--operation mode is normal
|
| 21879 |
|
|
|
| 21880 |
|
|
VD1_eqz_2_27 = !VD1_hilo_35 & !VD1_hilo_50 & VD1_eqz_2_16 & VD1_eqz_2_27_a;
|
| 21881 |
|
|
|
| 21882 |
|
|
|
| 21883 |
|
|
--VD1_eqz_2_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_30
|
| 21884 |
|
|
--operation mode is normal
|
| 21885 |
|
|
|
| 21886 |
|
|
VD1_eqz_2_30 = VD1_eqz_2_19 & VD1_eqz_2_20 & VD1_eqz_2_22 & VD1_eqz_2_23;
|
| 21887 |
|
|
|
| 21888 |
|
|
|
| 21889 |
|
|
--VD1_eqop2_2_NE_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_11
|
| 21890 |
|
|
--operation mode is normal
|
| 21891 |
|
|
|
| 21892 |
|
|
VD1_eqop2_2_NE_11 = VD1_eqop2_2_NE_121 # VD1_eqop2_2_NE_123 # VD1_eqop2_2_NE_122 # VD1_eqop2_2_NE_11_a;
|
| 21893 |
|
|
|
| 21894 |
|
|
|
| 21895 |
|
|
--VD1_eqop2_2_NE_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_9
|
| 21896 |
|
|
--operation mode is normal
|
| 21897 |
|
|
|
| 21898 |
|
|
VD1_eqop2_2_NE_9 = VD1_eqop2_2_NE_114 # VD1_eqop2_2_NE_115_0 # VD1_eqop2_2_NE_112 # VD1_eqop2_2_NE_113;
|
| 21899 |
|
|
|
| 21900 |
|
|
|
| 21901 |
|
|
--VD1_eqop2_2_NE_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_10
|
| 21902 |
|
|
--operation mode is normal
|
| 21903 |
|
|
|
| 21904 |
|
|
VD1_eqop2_2_NE_10 = VD1_eqop2_2_NE_118 # VD1_eqop2_2_NE_119 # VD1_eqop2_2_NE_116 # VD1_eqop2_2_NE_117;
|
| 21905 |
|
|
|
| 21906 |
|
|
|
| 21907 |
|
|
--VD1_eqop2_2_NE_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_12
|
| 21908 |
|
|
--operation mode is normal
|
| 21909 |
|
|
|
| 21910 |
|
|
VD1_eqop2_2_NE_12 = VD1_eqop2_2_NE_126 # VD1_eqop2_2_NE_124 # VD1_eqop2_2_32 # !VD1_eqop2_2_NE_12_a;
|
| 21911 |
|
|
|
| 21912 |
|
|
|
| 21913 |
|
|
--VD1_nop2_reged[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[32]
|
| 21914 |
|
|
--operation mode is normal
|
| 21915 |
|
|
|
| 21916 |
|
|
VD1_nop2_reged[32]_carry_eqn = VD1_nop2_reged_cout[30];
|
| 21917 |
|
|
VD1_nop2_reged[32] = VD1_op2_sign_reged $ (VD1_nop2_reged[32]_carry_eqn);
|
| 21918 |
|
|
|
| 21919 |
|
|
|
| 21920 |
|
|
--VD1_eqnop2_2_NE_7_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_7_a
|
| 21921 |
|
|
--operation mode is normal
|
| 21922 |
|
|
|
| 21923 |
|
|
VD1_eqnop2_2_NE_7_a = VD1_op2_reged[0] & VD1_hilo_48 $ VD1_nop2_reged[16] # !VD1_hilo[32] # !VD1_op2_reged[0] & VD1_hilo[32] # VD1_hilo_48 $ VD1_nop2_reged[16];
|
| 21924 |
|
|
|
| 21925 |
|
|
|
| 21926 |
|
|
--VD1_eqnop2_2_NE_143 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_143
|
| 21927 |
|
|
--operation mode is normal
|
| 21928 |
|
|
|
| 21929 |
|
|
VD1_eqnop2_2_NE_143 = VD1_hilo_63 & VD1_hilo_47 $ VD1_nop2_reged[15] # !VD1_nop2_reged[31] # !VD1_hilo_63 & VD1_nop2_reged[31] # VD1_hilo_47 $ VD1_nop2_reged[15];
|
| 21930 |
|
|
|
| 21931 |
|
|
|
| 21932 |
|
|
--VD1_eqnop2_2_NE_129 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_129
|
| 21933 |
|
|
--operation mode is normal
|
| 21934 |
|
|
|
| 21935 |
|
|
VD1_eqnop2_2_NE_129 = VD1_hilo_49 & VD1_hilo_33 $ VD1_nop2_reged[1] # !VD1_nop2_reged[17] # !VD1_hilo_49 & VD1_nop2_reged[17] # VD1_hilo_33 $ VD1_nop2_reged[1];
|
| 21936 |
|
|
|
| 21937 |
|
|
|
| 21938 |
|
|
--VD1_eqnop2_2_NE_131 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_131
|
| 21939 |
|
|
--operation mode is normal
|
| 21940 |
|
|
|
| 21941 |
|
|
VD1_eqnop2_2_NE_131 = VD1_hilo_51 & VD1_hilo_35 $ VD1_nop2_reged[3] # !VD1_nop2_reged[19] # !VD1_hilo_51 & VD1_nop2_reged[19] # VD1_hilo_35 $ VD1_nop2_reged[3];
|
| 21942 |
|
|
|
| 21943 |
|
|
|
| 21944 |
|
|
--VD1_eqnop2_2_NE_130 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_130
|
| 21945 |
|
|
--operation mode is normal
|
| 21946 |
|
|
|
| 21947 |
|
|
VD1_eqnop2_2_NE_130 = VD1_hilo_34 & VD1_hilo_50 $ VD1_nop2_reged[18] # !VD1_nop2_reged[2] # !VD1_hilo_34 & VD1_nop2_reged[2] # VD1_hilo_50 $ VD1_nop2_reged[18];
|
| 21948 |
|
|
|
| 21949 |
|
|
|
| 21950 |
|
|
--VD1_eqnop2_2_NE_132_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_132_0
|
| 21951 |
|
|
--operation mode is normal
|
| 21952 |
|
|
|
| 21953 |
|
|
VD1_eqnop2_2_NE_132_0 = VD1_hilo_52 & VD1_hilo_36 $ VD1_nop2_reged[4] # !VD1_nop2_reged[20] # !VD1_hilo_52 & VD1_nop2_reged[20] # VD1_hilo_36 $ VD1_nop2_reged[4];
|
| 21954 |
|
|
|
| 21955 |
|
|
|
| 21956 |
|
|
--VD1_eqnop2_2_NE_133 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_133
|
| 21957 |
|
|
--operation mode is normal
|
| 21958 |
|
|
|
| 21959 |
|
|
VD1_eqnop2_2_NE_133 = VD1_hilo_37 & VD1_hilo_53 $ VD1_nop2_reged[21] # !VD1_nop2_reged[5] # !VD1_hilo_37 & VD1_nop2_reged[5] # VD1_hilo_53 $ VD1_nop2_reged[21];
|
| 21960 |
|
|
|
| 21961 |
|
|
|
| 21962 |
|
|
--VD1_eqnop2_2_NE_134 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_134
|
| 21963 |
|
|
--operation mode is normal
|
| 21964 |
|
|
|
| 21965 |
|
|
VD1_eqnop2_2_NE_134 = VD1_hilo_38 & VD1_hilo_54 $ VD1_nop2_reged[22] # !VD1_nop2_reged[6] # !VD1_hilo_38 & VD1_nop2_reged[6] # VD1_hilo_54 $ VD1_nop2_reged[22];
|
| 21966 |
|
|
|
| 21967 |
|
|
|
| 21968 |
|
|
--VD1_eqnop2_2_NE_135 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_135
|
| 21969 |
|
|
--operation mode is normal
|
| 21970 |
|
|
|
| 21971 |
|
|
VD1_eqnop2_2_NE_135 = VD1_hilo_39 & VD1_hilo_55 $ VD1_nop2_reged[23] # !VD1_nop2_reged[7] # !VD1_hilo_39 & VD1_nop2_reged[7] # VD1_hilo_55 $ VD1_nop2_reged[23];
|
| 21972 |
|
|
|
| 21973 |
|
|
|
| 21974 |
|
|
--VD1_eqnop2_2_NE_10_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_10_a
|
| 21975 |
|
|
--operation mode is normal
|
| 21976 |
|
|
|
| 21977 |
|
|
VD1_eqnop2_2_NE_10_a = VD1_hilo_40 & VD1_hilo_56 $ VD1_nop2_reged[24] # !VD1_nop2_reged[8] # !VD1_hilo_40 & VD1_nop2_reged[8] # VD1_hilo_56 $ VD1_nop2_reged[24];
|
| 21978 |
|
|
|
| 21979 |
|
|
|
| 21980 |
|
|
--VD1_eqnop2_2_NE_141 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_141
|
| 21981 |
|
|
--operation mode is normal
|
| 21982 |
|
|
|
| 21983 |
|
|
VD1_eqnop2_2_NE_141 = VD1_hilo_61 & VD1_hilo_45 $ VD1_nop2_reged[13] # !VD1_nop2_reged[29] # !VD1_hilo_61 & VD1_nop2_reged[29] # VD1_hilo_45 $ VD1_nop2_reged[13];
|
| 21984 |
|
|
|
| 21985 |
|
|
|
| 21986 |
|
|
--VD1_eqnop2_2_NE_142 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_142
|
| 21987 |
|
|
--operation mode is normal
|
| 21988 |
|
|
|
| 21989 |
|
|
VD1_eqnop2_2_NE_142 = VD1_hilo_62 & VD1_hilo_46 $ VD1_nop2_reged[14] # !VD1_nop2_reged[30] # !VD1_hilo_62 & VD1_nop2_reged[30] # VD1_hilo_46 $ VD1_nop2_reged[14];
|
| 21990 |
|
|
|
| 21991 |
|
|
|
| 21992 |
|
|
--VD1_eqnop2_2_NE_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_5
|
| 21993 |
|
|
--operation mode is normal
|
| 21994 |
|
|
|
| 21995 |
|
|
VD1_eqnop2_2_NE_5 = VD1_eqnop2_2_9 # VD1_eqnop2_2_NE_5_a # VD1_hilo_58 $ VD1_nop2_reged[26];
|
| 21996 |
|
|
|
| 21997 |
|
|
|
| 21998 |
|
|
--VD1_eqnop2_2_NE_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_8
|
| 21999 |
|
|
--operation mode is normal
|
| 22000 |
|
|
|
| 22001 |
|
|
VD1_eqnop2_2_NE_8 = VD1_eqnop2_2_NE_8_a # VD1_hilo_59 $ VD1_nop2_reged[27] # !VD1_eqnop2_2_NE_140_i_a2;
|
| 22002 |
|
|
|
| 22003 |
|
|
|
| 22004 |
|
|
--VD1_hilo_33_i_m_a[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[64]
|
| 22005 |
|
|
--operation mode is normal
|
| 22006 |
|
|
|
| 22007 |
|
|
VD1_hilo_33_i_m_a[64] = VD1_addnop2 & !VD1_un50_hilo_add32 # !VD1_addnop2 & !VD1_un59_hilo_add32;
|
| 22008 |
|
|
|
| 22009 |
|
|
|
| 22010 |
|
|
--VD1_hilo_15_3_i[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_3_i[63]
|
| 22011 |
|
|
--operation mode is normal
|
| 22012 |
|
|
|
| 22013 |
|
|
VD1_hilo_15_3_i[63] = VD1_hilo_15_3_i_a[63] # !VD1_hilo[64] & !VD1_hilo_15_1[56];
|
| 22014 |
|
|
|
| 22015 |
|
|
|
| 22016 |
|
|
--VD1_hilo_37_iv_1_a[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1_a[64]
|
| 22017 |
|
|
--operation mode is normal
|
| 22018 |
|
|
|
| 22019 |
|
|
VD1_hilo_37_iv_1_a[64] = VD1_hilo[64] & !VD1_hilo25 # !RC1_alu_func_o_0 # !VD1_hilo[64] & !VD1_hilo25 & !VD1_hilo_0_sqmuxa;
|
| 22020 |
|
|
|
| 22021 |
|
|
|
| 22022 |
|
|
--VD1_nop2_reged_cout[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[0]
|
| 22023 |
|
|
--operation mode is arithmetic
|
| 22024 |
|
|
|
| 22025 |
|
|
VD1_nop2_reged_cout[0] = CARRY(!VD1_op2_reged[1] & !VD1_op2_reged[0]);
|
| 22026 |
|
|
|
| 22027 |
|
|
|
| 22028 |
|
|
--VD1_un1_op2_reged_1_combout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[3]
|
| 22029 |
|
|
--operation mode is normal
|
| 22030 |
|
|
|
| 22031 |
|
|
VD1_un1_op2_reged_1_combout[3] = VD1_eqop2_2_32 & VD1_op2_reged[3] # !VD1_eqop2_2_32 & VD1_nop2_reged[3];
|
| 22032 |
|
|
|
| 22033 |
|
|
|
| 22034 |
|
|
--VD1_hilo_37_iv_0_a3_2[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_2[38]
|
| 22035 |
|
|
--operation mode is normal
|
| 22036 |
|
|
|
| 22037 |
|
|
VD1_hilo_37_iv_0_a3_2[38] = !VD1_hilo_6 & VD1_hilo_0_sqmuxa;
|
| 22038 |
|
|
|
| 22039 |
|
|
|
| 22040 |
|
|
--VD1_hilo_37_iv_0_a3_6[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_6[38]
|
| 22041 |
|
|
--operation mode is normal
|
| 22042 |
|
|
|
| 22043 |
|
|
VD1_hilo_37_iv_0_a3_6[38] = VD1_addop2 & !VD1_addnop2 & !VD1_un59_hilo_add6 & VD1_hilo_3_sqmuxa;
|
| 22044 |
|
|
|
| 22045 |
|
|
|
| 22046 |
|
|
--GD1_dout_iv_1_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_16
|
| 22047 |
|
|
--operation mode is normal
|
| 22048 |
|
|
|
| 22049 |
|
|
GD1_dout_iv_1_16 = FD1_N_20_i_0_s3 & LD1_q_b[16] # !GD1_dout_iv_1_a[16];
|
| 22050 |
|
|
|
| 22051 |
|
|
|
| 22052 |
|
|
--CD1_res_7_0_0_0_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_14
|
| 22053 |
|
|
--operation mode is normal
|
| 22054 |
|
|
|
| 22055 |
|
|
CD1_res_7_0_0_0_14 = ED1_r32_o_0 & CD1_res_7_0_0_a2_16 # ED1_r32_o_15 & CD1_res_7_0_0_0_a[16] # !ED1_r32_o_0 & ED1_r32_o_15 & CD1_res_7_0_0_0_a[16];
|
| 22056 |
|
|
|
| 22057 |
|
|
|
| 22058 |
|
|
--GD1_dout_iv_1_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_28
|
| 22059 |
|
|
--operation mode is normal
|
| 22060 |
|
|
|
| 22061 |
|
|
GD1_dout_iv_1_28 = FD1_N_20_i_0_s3 & LD1_q_b[28] # !GD1_dout_iv_1_a[28];
|
| 22062 |
|
|
|
| 22063 |
|
|
|
| 22064 |
|
|
--GD1_dout_iv_1_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_23
|
| 22065 |
|
|
--operation mode is normal
|
| 22066 |
|
|
|
| 22067 |
|
|
GD1_dout_iv_1_23 = FD1_N_20_i_0_s3 & LD1_q_b[23] # !GD1_dout_iv_1_a[23];
|
| 22068 |
|
|
|
| 22069 |
|
|
|
| 22070 |
|
|
--CD1_res_7_0_0_a_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_20
|
| 22071 |
|
|
--operation mode is normal
|
| 22072 |
|
|
|
| 22073 |
|
|
CD1_res_7_0_0_a_20 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_21;
|
| 22074 |
|
|
|
| 22075 |
|
|
|
| 22076 |
|
|
--GD1_dout_iv_1_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_24
|
| 22077 |
|
|
--operation mode is normal
|
| 22078 |
|
|
|
| 22079 |
|
|
GD1_dout_iv_1_24 = FD1_N_20_i_0_s3 & LD1_q_b[24] # !GD1_dout_iv_1_a[24];
|
| 22080 |
|
|
|
| 22081 |
|
|
|
| 22082 |
|
|
--CD1_res_7_0_0_a_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_21
|
| 22083 |
|
|
--operation mode is normal
|
| 22084 |
|
|
|
| 22085 |
|
|
CD1_res_7_0_0_a_21 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_22;
|
| 22086 |
|
|
|
| 22087 |
|
|
|
| 22088 |
|
|
--F1_dout_24 is mips_sys:isys|mips_dvc:imips_dvc|dout_24
|
| 22089 |
|
|
--operation mode is normal
|
| 22090 |
|
|
|
| 22091 |
|
|
F1_dout_24_lut_out = K1_cntr_24 & F1_dout_0_0_a3_4[0] # F1_cmd[24] & F1_dout_0_0_a3_3[0] # !K1_cntr_24 & F1_cmd[24] & F1_dout_0_0_a3_3[0];
|
| 22092 |
|
|
F1_dout_24 = DFFEAS(F1_dout_24_lut_out, E1__clk0, VCC, , , , , , );
|
| 22093 |
|
|
|
| 22094 |
|
|
|
| 22095 |
|
|
--DB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_24
|
| 22096 |
|
|
--operation mode is normal
|
| 22097 |
|
|
|
| 22098 |
|
|
DB1_r32_o_24_lut_out = WB92L1;
|
| 22099 |
|
|
DB1_r32_o_24 = DFFEAS(DB1_r32_o_24_lut_out, E1__clk0, VCC, , , , , , );
|
| 22100 |
|
|
|
| 22101 |
|
|
|
| 22102 |
|
|
--BB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_24
|
| 22103 |
|
|
--operation mode is normal
|
| 22104 |
|
|
|
| 22105 |
|
|
BB1_r32_o_24_lut_out = AB1_r32_o_22;
|
| 22106 |
|
|
BB1_r32_o_24 = DFFEAS(BB1_r32_o_24_lut_out, E1__clk0, VCC, , , , , , );
|
| 22107 |
|
|
|
| 22108 |
|
|
|
| 22109 |
|
|
--VD1_un50_hilo_add0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add0
|
| 22110 |
|
|
--operation mode is arithmetic
|
| 22111 |
|
|
|
| 22112 |
|
|
VD1_un50_hilo_add0 = VD1_hilo[32] $ VD1_op2_reged[0];
|
| 22113 |
|
|
|
| 22114 |
|
|
--VD1_un50_hilo_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_0
|
| 22115 |
|
|
--operation mode is arithmetic
|
| 22116 |
|
|
|
| 22117 |
|
|
VD1_un50_hilo_carry_0 = CARRY(VD1_hilo[32] & VD1_op2_reged[0]);
|
| 22118 |
|
|
|
| 22119 |
|
|
|
| 22120 |
|
|
--VD1_hilo_33_i_m_a[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[48]
|
| 22121 |
|
|
--operation mode is normal
|
| 22122 |
|
|
|
| 22123 |
|
|
VD1_hilo_33_i_m_a[48] = VD1_addnop2 & !VD1_un50_hilo_add16 # !VD1_addnop2 & !VD1_un59_hilo_add16;
|
| 22124 |
|
|
|
| 22125 |
|
|
|
| 22126 |
|
|
--VD1_hilo_24_add16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add16
|
| 22127 |
|
|
--operation mode is arithmetic
|
| 22128 |
|
|
|
| 22129 |
|
|
VD1_hilo_24_add16_carry_eqn = VD1_hilo_24_carry_15;
|
| 22130 |
|
|
VD1_hilo_24_add16 = VD1_hilo_47 $ VD1_un1_op2_reged_1_combout[16] $ !VD1_hilo_24_add16_carry_eqn;
|
| 22131 |
|
|
|
| 22132 |
|
|
--VD1_hilo_24_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_16
|
| 22133 |
|
|
--operation mode is arithmetic
|
| 22134 |
|
|
|
| 22135 |
|
|
VD1_hilo_24_carry_16 = CARRY(VD1_hilo_47 & VD1_un1_op2_reged_1_combout[16] # !VD1_hilo_24_carry_15 # !VD1_hilo_47 & VD1_un1_op2_reged_1_combout[16] & !VD1_hilo_24_carry_15);
|
| 22136 |
|
|
|
| 22137 |
|
|
|
| 22138 |
|
|
--VD1_hilo_22_a[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[48]
|
| 22139 |
|
|
--operation mode is normal
|
| 22140 |
|
|
|
| 22141 |
|
|
VD1_hilo_22_a[48] = VD1_sign & !VD1_hilo_49 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add17 # !VD1_hilo[0] & !VD1_hilo_49;
|
| 22142 |
|
|
|
| 22143 |
|
|
|
| 22144 |
|
|
--VD1_hilo_15_2[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[48]
|
| 22145 |
|
|
--operation mode is normal
|
| 22146 |
|
|
|
| 22147 |
|
|
VD1_hilo_15_2[48] = VD1_sub_or_yn & VD1_un59_hilo_add17 # !VD1_sub_or_yn & VD1_un50_hilo_add17;
|
| 22148 |
|
|
|
| 22149 |
|
|
|
| 22150 |
|
|
--KB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_16
|
| 22151 |
|
|
--operation mode is normal
|
| 22152 |
|
|
|
| 22153 |
|
|
KB1_r32_o_16_lut_out = DD1_pc_next_0_iv_1_16 # DD1_un1_pc_next46_0 & DD1_un1_pc_add16;
|
| 22154 |
|
|
KB1_r32_o_16 = DFFEAS(KB1_r32_o_16_lut_out, E1__clk0, VCC, , , , , , );
|
| 22155 |
|
|
|
| 22156 |
|
|
|
| 22157 |
|
|
--KB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_17
|
| 22158 |
|
|
--operation mode is normal
|
| 22159 |
|
|
|
| 22160 |
|
|
KB1_r32_o_17_lut_out = DD1_pc_next_0_iv_1_17 # DD1_un1_pc_next46_0 & DD1_un1_pc_add17;
|
| 22161 |
|
|
KB1_r32_o_17 = DFFEAS(KB1_r32_o_17_lut_out, E1__clk0, VCC, , , , , , );
|
| 22162 |
|
|
|
| 22163 |
|
|
|
| 22164 |
|
|
--PD1_a_o_3_d_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[16]
|
| 22165 |
|
|
--operation mode is normal
|
| 22166 |
|
|
|
| 22167 |
|
|
PD1_a_o_3_d_a[16] = PD1_a_o_sn_m2 & !PB1_r32_o_16 # !PD1_a_o_sn_m2 & !AB1_r32_o_14;
|
| 22168 |
|
|
|
| 22169 |
|
|
|
| 22170 |
|
|
--VD1_hilo_33_i_m_a[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[49]
|
| 22171 |
|
|
--operation mode is normal
|
| 22172 |
|
|
|
| 22173 |
|
|
VD1_hilo_33_i_m_a[49] = VD1_addnop2 & !VD1_un50_hilo_add17 # !VD1_addnop2 & !VD1_un59_hilo_add17;
|
| 22174 |
|
|
|
| 22175 |
|
|
|
| 22176 |
|
|
--VD1_hilo_24_add17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add17
|
| 22177 |
|
|
--operation mode is arithmetic
|
| 22178 |
|
|
|
| 22179 |
|
|
VD1_hilo_24_add17_carry_eqn = VD1_hilo_24_carry_16;
|
| 22180 |
|
|
VD1_hilo_24_add17 = VD1_hilo_48 $ VD1_un1_op2_reged_1_combout[17] $ VD1_hilo_24_add17_carry_eqn;
|
| 22181 |
|
|
|
| 22182 |
|
|
--VD1_hilo_24_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_17
|
| 22183 |
|
|
--operation mode is arithmetic
|
| 22184 |
|
|
|
| 22185 |
|
|
VD1_hilo_24_carry_17 = CARRY(VD1_hilo_48 & !VD1_un1_op2_reged_1_combout[17] & !VD1_hilo_24_carry_16 # !VD1_hilo_48 & !VD1_hilo_24_carry_16 # !VD1_un1_op2_reged_1_combout[17]);
|
| 22186 |
|
|
|
| 22187 |
|
|
|
| 22188 |
|
|
--VD1_hilo_22_a[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[49]
|
| 22189 |
|
|
--operation mode is normal
|
| 22190 |
|
|
|
| 22191 |
|
|
VD1_hilo_22_a[49] = VD1_sign & !VD1_hilo_50 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add18 # !VD1_hilo[0] & !VD1_hilo_50;
|
| 22192 |
|
|
|
| 22193 |
|
|
|
| 22194 |
|
|
--VD1_hilo_15_2[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[49]
|
| 22195 |
|
|
--operation mode is normal
|
| 22196 |
|
|
|
| 22197 |
|
|
VD1_hilo_15_2[49] = VD1_sub_or_yn & VD1_un59_hilo_add18 # !VD1_sub_or_yn & VD1_un50_hilo_add18;
|
| 22198 |
|
|
|
| 22199 |
|
|
|
| 22200 |
|
|
--PD1_a_o_3_d_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[17]
|
| 22201 |
|
|
--operation mode is normal
|
| 22202 |
|
|
|
| 22203 |
|
|
PD1_a_o_3_d_a[17] = PD1_a_o_sn_m2 & !PB1_r32_o_17 # !PD1_a_o_sn_m2 & !AB1_r32_o_15;
|
| 22204 |
|
|
|
| 22205 |
|
|
|
| 22206 |
|
|
--VD1_un134_hilo_combout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[12]
|
| 22207 |
|
|
--operation mode is arithmetic
|
| 22208 |
|
|
|
| 22209 |
|
|
VD1_un134_hilo_combout[12]_carry_eqn = VD1_un134_hilo_cout[10];
|
| 22210 |
|
|
VD1_un134_hilo_combout[12] = VD1_hilo_12 $ (!VD1_un134_hilo_combout[12]_carry_eqn);
|
| 22211 |
|
|
|
| 22212 |
|
|
--VD1_un134_hilo_cout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[12]
|
| 22213 |
|
|
--operation mode is arithmetic
|
| 22214 |
|
|
|
| 22215 |
|
|
VD1_un134_hilo_cout[12] = CARRY(VD1_hilo_12 & VD1_hilo_13 & !VD1_un134_hilo_cout[10]);
|
| 22216 |
|
|
|
| 22217 |
|
|
|
| 22218 |
|
|
--VD1_hilo_33_i_m_a[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[46]
|
| 22219 |
|
|
--operation mode is normal
|
| 22220 |
|
|
|
| 22221 |
|
|
VD1_hilo_33_i_m_a[46] = VD1_addnop2 & !VD1_un50_hilo_add14 # !VD1_addnop2 & !VD1_un59_hilo_add14;
|
| 22222 |
|
|
|
| 22223 |
|
|
|
| 22224 |
|
|
--VD1_hilo_24_add14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add14
|
| 22225 |
|
|
--operation mode is arithmetic
|
| 22226 |
|
|
|
| 22227 |
|
|
VD1_hilo_24_add14_carry_eqn = VD1_hilo_24_carry_13;
|
| 22228 |
|
|
VD1_hilo_24_add14 = VD1_hilo_45 $ VD1_un1_op2_reged_1_combout[14] $ !VD1_hilo_24_add14_carry_eqn;
|
| 22229 |
|
|
|
| 22230 |
|
|
--VD1_hilo_24_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_14
|
| 22231 |
|
|
--operation mode is arithmetic
|
| 22232 |
|
|
|
| 22233 |
|
|
VD1_hilo_24_carry_14 = CARRY(VD1_hilo_45 & VD1_un1_op2_reged_1_combout[14] # !VD1_hilo_24_carry_13 # !VD1_hilo_45 & VD1_un1_op2_reged_1_combout[14] & !VD1_hilo_24_carry_13);
|
| 22234 |
|
|
|
| 22235 |
|
|
|
| 22236 |
|
|
--VD1_hilo_22_a[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[46]
|
| 22237 |
|
|
--operation mode is normal
|
| 22238 |
|
|
|
| 22239 |
|
|
VD1_hilo_22_a[46] = VD1_sign & !VD1_hilo_47 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add15 # !VD1_hilo[0] & !VD1_hilo_47;
|
| 22240 |
|
|
|
| 22241 |
|
|
|
| 22242 |
|
|
--VD1_hilo_15_2[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[46]
|
| 22243 |
|
|
--operation mode is normal
|
| 22244 |
|
|
|
| 22245 |
|
|
VD1_hilo_15_2[46] = VD1_sub_or_yn & VD1_un59_hilo_add15 # !VD1_sub_or_yn & VD1_un50_hilo_add15;
|
| 22246 |
|
|
|
| 22247 |
|
|
|
| 22248 |
|
|
--KB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_14
|
| 22249 |
|
|
--operation mode is normal
|
| 22250 |
|
|
|
| 22251 |
|
|
KB1_r32_o_14_lut_out = DD1_pc_next_0_iv_1_14 # DD1_un1_pc_next46_0 & DD1_un1_pc_add14;
|
| 22252 |
|
|
KB1_r32_o_14 = DFFEAS(KB1_r32_o_14_lut_out, E1__clk0, VCC, , , , , , );
|
| 22253 |
|
|
|
| 22254 |
|
|
|
| 22255 |
|
|
--KB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_15
|
| 22256 |
|
|
--operation mode is normal
|
| 22257 |
|
|
|
| 22258 |
|
|
KB1_r32_o_15_lut_out = DD1_pc_next_0_iv_1_15 # DD1_un1_pc_next46_0 & DD1_un1_pc_add15;
|
| 22259 |
|
|
KB1_r32_o_15 = DFFEAS(KB1_r32_o_15_lut_out, E1__clk0, VCC, , , , , , );
|
| 22260 |
|
|
|
| 22261 |
|
|
|
| 22262 |
|
|
--RD1_r32_o_0_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_12
|
| 22263 |
|
|
--operation mode is arithmetic
|
| 22264 |
|
|
|
| 22265 |
|
|
RD1_r32_o_0_12_carry_eqn = RD1_r32_o_cout[10];
|
| 22266 |
|
|
RD1_r32_o_0_12_lut_out = KB1_r32_o_12 $ (RD1_r32_o_0_12_carry_eqn);
|
| 22267 |
|
|
RD1_r32_o_0_12 = DFFEAS(RD1_r32_o_0_12_lut_out, E1__clk0, VCC, , , , , , );
|
| 22268 |
|
|
|
| 22269 |
|
|
--RD1_r32_o_cout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[12]
|
| 22270 |
|
|
--operation mode is arithmetic
|
| 22271 |
|
|
|
| 22272 |
|
|
RD1_r32_o_cout[12] = CARRY(!RD1_r32_o_cout[10] # !KB1_r32_o_13 # !KB1_r32_o_12);
|
| 22273 |
|
|
|
| 22274 |
|
|
|
| 22275 |
|
|
--PD1_a_o_3_d_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[14]
|
| 22276 |
|
|
--operation mode is normal
|
| 22277 |
|
|
|
| 22278 |
|
|
PD1_a_o_3_d_a[14] = PD1_a_o_sn_m2 & !PB1_r32_o_14 # !PD1_a_o_sn_m2 & !AB1_r32_o_12;
|
| 22279 |
|
|
|
| 22280 |
|
|
|
| 22281 |
|
|
--VD1_hilo_33_i_m_a[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[47]
|
| 22282 |
|
|
--operation mode is normal
|
| 22283 |
|
|
|
| 22284 |
|
|
VD1_hilo_33_i_m_a[47] = VD1_addnop2 & !VD1_un50_hilo_add15 # !VD1_addnop2 & !VD1_un59_hilo_add15;
|
| 22285 |
|
|
|
| 22286 |
|
|
|
| 22287 |
|
|
--VD1_hilo_24_add15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add15
|
| 22288 |
|
|
--operation mode is arithmetic
|
| 22289 |
|
|
|
| 22290 |
|
|
VD1_hilo_24_add15_carry_eqn = VD1_hilo_24_carry_14;
|
| 22291 |
|
|
VD1_hilo_24_add15 = VD1_hilo_46 $ VD1_un1_op2_reged_1_combout[15] $ VD1_hilo_24_add15_carry_eqn;
|
| 22292 |
|
|
|
| 22293 |
|
|
--VD1_hilo_24_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_15
|
| 22294 |
|
|
--operation mode is arithmetic
|
| 22295 |
|
|
|
| 22296 |
|
|
VD1_hilo_24_carry_15 = CARRY(VD1_hilo_46 & !VD1_un1_op2_reged_1_combout[15] & !VD1_hilo_24_carry_14 # !VD1_hilo_46 & !VD1_hilo_24_carry_14 # !VD1_un1_op2_reged_1_combout[15]);
|
| 22297 |
|
|
|
| 22298 |
|
|
|
| 22299 |
|
|
--VD1_hilo_22_a[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[47]
|
| 22300 |
|
|
--operation mode is normal
|
| 22301 |
|
|
|
| 22302 |
|
|
VD1_hilo_22_a[47] = VD1_sign & !VD1_hilo_48 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add16 # !VD1_hilo[0] & !VD1_hilo_48;
|
| 22303 |
|
|
|
| 22304 |
|
|
|
| 22305 |
|
|
--VD1_hilo_15_2[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[47]
|
| 22306 |
|
|
--operation mode is normal
|
| 22307 |
|
|
|
| 22308 |
|
|
VD1_hilo_15_2[47] = VD1_sub_or_yn & VD1_un59_hilo_add16 # !VD1_sub_or_yn & VD1_un50_hilo_add16;
|
| 22309 |
|
|
|
| 22310 |
|
|
|
| 22311 |
|
|
--PD1_a_o_3_d_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[15]
|
| 22312 |
|
|
--operation mode is normal
|
| 22313 |
|
|
|
| 22314 |
|
|
PD1_a_o_3_d_a[15] = PD1_a_o_sn_m2 & !PB1_r32_o_15 # !PD1_a_o_sn_m2 & !AB1_r32_o_13;
|
| 22315 |
|
|
|
| 22316 |
|
|
|
| 22317 |
|
|
--UD1_shift_out_52_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52_a[31]
|
| 22318 |
|
|
--operation mode is normal
|
| 22319 |
|
|
|
| 22320 |
|
|
UD1_shift_out_52_a[31] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_12 # !PD1_a_o_0 & !VD1_b_o_iv_13 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 22321 |
|
|
|
| 22322 |
|
|
|
| 22323 |
|
|
--VD1_un59_hilo_add0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add0
|
| 22324 |
|
|
--operation mode is arithmetic
|
| 22325 |
|
|
|
| 22326 |
|
|
VD1_un59_hilo_add0 = VD1_hilo[32] $ VD1_op2_reged[0];
|
| 22327 |
|
|
|
| 22328 |
|
|
--VD1_un59_hilo_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_0
|
| 22329 |
|
|
--operation mode is arithmetic
|
| 22330 |
|
|
|
| 22331 |
|
|
VD1_un59_hilo_carry_0 = CARRY(VD1_hilo[32] & VD1_op2_reged[0]);
|
| 22332 |
|
|
|
| 22333 |
|
|
|
| 22334 |
|
|
--VD1_hilo_37_iv_0_1_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[31]
|
| 22335 |
|
|
--operation mode is normal
|
| 22336 |
|
|
|
| 22337 |
|
|
VD1_hilo_37_iv_0_1_a[31] = VD1_hilo[32] & !VD1_hilo_37_iv_0_a6_0_1[40] & !VD1_hilo_37_iv_0_a3_0[0] # !VD1_un134_hilo_combout[31] # !VD1_hilo[32] & !VD1_hilo_37_iv_0_a3_0[0] # !VD1_un134_hilo_combout[31];
|
| 22338 |
|
|
|
| 22339 |
|
|
|
| 22340 |
|
|
--VD1_hilo_22_i_m_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_i_m_a[63]
|
| 22341 |
|
|
--operation mode is normal
|
| 22342 |
|
|
|
| 22343 |
|
|
VD1_hilo_22_i_m_a[63] = VD1_hilo[0] & !VD1_un59_hilo_add32 # !VD1_hilo[0] & !VD1_hilo[64];
|
| 22344 |
|
|
|
| 22345 |
|
|
|
| 22346 |
|
|
--VD1_hilo_33_3_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_3_a[63]
|
| 22347 |
|
|
--operation mode is normal
|
| 22348 |
|
|
|
| 22349 |
|
|
VD1_hilo_33_3_a[63] = VD1_hilo_33_1[64] & !VD1_un59_hilo_add31 # !VD1_hilo_33_1[64] & !VD1_hilo_63;
|
| 22350 |
|
|
|
| 22351 |
|
|
|
| 22352 |
|
|
--UD1_shift_out_80_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[8]
|
| 22353 |
|
|
--operation mode is normal
|
| 22354 |
|
|
|
| 22355 |
|
|
UD1_shift_out_80_a[8] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_11 # !PD1_a_o_1 & !VD1_b_o_iv_9;
|
| 22356 |
|
|
|
| 22357 |
|
|
|
| 22358 |
|
|
--UD1_shift_out_45_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45_a[28]
|
| 22359 |
|
|
--operation mode is normal
|
| 22360 |
|
|
|
| 22361 |
|
|
UD1_shift_out_45_a[28] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_1 # !PD1_a_o_0 & !VD1_b_o_iv_2 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 22362 |
|
|
|
| 22363 |
|
|
|
| 22364 |
|
|
--RD1_r32_o_0_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_8
|
| 22365 |
|
|
--operation mode is arithmetic
|
| 22366 |
|
|
|
| 22367 |
|
|
RD1_r32_o_0_8_carry_eqn = RD1_r32_o_cout[6];
|
| 22368 |
|
|
RD1_r32_o_0_8_lut_out = KB1_r32_o_8 $ (RD1_r32_o_0_8_carry_eqn);
|
| 22369 |
|
|
RD1_r32_o_0_8 = DFFEAS(RD1_r32_o_0_8_lut_out, E1__clk0, VCC, , , , , , );
|
| 22370 |
|
|
|
| 22371 |
|
|
--RD1_r32_o_cout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[8]
|
| 22372 |
|
|
--operation mode is arithmetic
|
| 22373 |
|
|
|
| 22374 |
|
|
RD1_r32_o_cout[8] = CARRY(!RD1_r32_o_cout[6] # !KB1_r32_o_9 # !KB1_r32_o_8);
|
| 22375 |
|
|
|
| 22376 |
|
|
|
| 22377 |
|
|
--PD1_a_o_3_d[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[8]
|
| 22378 |
|
|
--operation mode is normal
|
| 22379 |
|
|
|
| 22380 |
|
|
PD1_a_o_3_d[8] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_8 # !PD1_un6_a_o & !PD1_a_o_3_d_a[8] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[8];
|
| 22381 |
|
|
|
| 22382 |
|
|
|
| 22383 |
|
|
--UD1_shift_out_80_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[9]
|
| 22384 |
|
|
--operation mode is normal
|
| 22385 |
|
|
|
| 22386 |
|
|
UD1_shift_out_80_a[9] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_12 # !PD1_a_o_1 & !VD1_b_o_iv_10;
|
| 22387 |
|
|
|
| 22388 |
|
|
|
| 22389 |
|
|
--VD1_un134_hilo_combout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[9]
|
| 22390 |
|
|
--operation mode is arithmetic
|
| 22391 |
|
|
|
| 22392 |
|
|
VD1_un134_hilo_combout[9]_carry_eqn = VD1_un134_hilo_cout[7];
|
| 22393 |
|
|
VD1_un134_hilo_combout[9] = VD1_hilo_9 $ (VD1_hilo_8 & !VD1_un134_hilo_combout[9]_carry_eqn);
|
| 22394 |
|
|
|
| 22395 |
|
|
--VD1_un134_hilo_cout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[9]
|
| 22396 |
|
|
--operation mode is arithmetic
|
| 22397 |
|
|
|
| 22398 |
|
|
VD1_un134_hilo_cout[9] = CARRY(VD1_hilo_8 & VD1_hilo_9 & !VD1_un134_hilo_cout[7]);
|
| 22399 |
|
|
|
| 22400 |
|
|
|
| 22401 |
|
|
--VD1_hilo_33_i_m[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[41]
|
| 22402 |
|
|
--operation mode is normal
|
| 22403 |
|
|
|
| 22404 |
|
|
VD1_hilo_33_i_m[41] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[41] # !VD1_hilo_33_1[64] & !VD1_hilo_41;
|
| 22405 |
|
|
|
| 22406 |
|
|
|
| 22407 |
|
|
--VD1_hilo_37_iv_2_a[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[41]
|
| 22408 |
|
|
--operation mode is normal
|
| 22409 |
|
|
|
| 22410 |
|
|
VD1_hilo_37_iv_2_a[41] = VD1_hilo_9 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add9 # !VD1_hilo_9 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add9;
|
| 22411 |
|
|
|
| 22412 |
|
|
|
| 22413 |
|
|
--VD1_hilo_22_Z[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[41]
|
| 22414 |
|
|
--operation mode is normal
|
| 22415 |
|
|
|
| 22416 |
|
|
VD1_hilo_22_Z[41] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[41] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[41] # !VD1_sign & !VD1_hilo_22_a[41];
|
| 22417 |
|
|
|
| 22418 |
|
|
|
| 22419 |
|
|
--RD1_r32_o_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_9
|
| 22420 |
|
|
--operation mode is arithmetic
|
| 22421 |
|
|
|
| 22422 |
|
|
RD1_r32_o_9_carry_eqn = RD1_r32_o_cout[7];
|
| 22423 |
|
|
RD1_r32_o_9_lut_out = KB1_r32_o_9 $ (KB1_r32_o_8 & RD1_r32_o_9_carry_eqn);
|
| 22424 |
|
|
RD1_r32_o_9 = DFFEAS(RD1_r32_o_9_lut_out, E1__clk0, VCC, , , , , , );
|
| 22425 |
|
|
|
| 22426 |
|
|
--RD1_r32_o_cout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[9]
|
| 22427 |
|
|
--operation mode is arithmetic
|
| 22428 |
|
|
|
| 22429 |
|
|
RD1_r32_o_cout[9] = CARRY(!RD1_r32_o_cout[7] # !KB1_r32_o_9 # !KB1_r32_o_8);
|
| 22430 |
|
|
|
| 22431 |
|
|
|
| 22432 |
|
|
--PD1_a_o_3_d[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[9]
|
| 22433 |
|
|
--operation mode is normal
|
| 22434 |
|
|
|
| 22435 |
|
|
PD1_a_o_3_d[9] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_9 # !PD1_un6_a_o & !PD1_a_o_3_d_a[9] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[9];
|
| 22436 |
|
|
|
| 22437 |
|
|
|
| 22438 |
|
|
--VD1_un134_hilo_combout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[10]
|
| 22439 |
|
|
--operation mode is arithmetic
|
| 22440 |
|
|
|
| 22441 |
|
|
VD1_un134_hilo_combout[10]_carry_eqn = VD1_un134_hilo_cout[8];
|
| 22442 |
|
|
VD1_un134_hilo_combout[10] = VD1_hilo_10 $ (VD1_un134_hilo_combout[10]_carry_eqn);
|
| 22443 |
|
|
|
| 22444 |
|
|
--VD1_un134_hilo_cout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[10]
|
| 22445 |
|
|
--operation mode is arithmetic
|
| 22446 |
|
|
|
| 22447 |
|
|
VD1_un134_hilo_cout[10] = CARRY(!VD1_un134_hilo_cout[8] # !VD1_hilo_11 # !VD1_hilo_10);
|
| 22448 |
|
|
|
| 22449 |
|
|
|
| 22450 |
|
|
--VD1_hilo_33_i_m[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[42]
|
| 22451 |
|
|
--operation mode is normal
|
| 22452 |
|
|
|
| 22453 |
|
|
VD1_hilo_33_i_m[42] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[42] # !VD1_hilo_33_1[64] & !VD1_hilo_42;
|
| 22454 |
|
|
|
| 22455 |
|
|
|
| 22456 |
|
|
--VD1_hilo_37_iv_2_a[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[42]
|
| 22457 |
|
|
--operation mode is normal
|
| 22458 |
|
|
|
| 22459 |
|
|
VD1_hilo_37_iv_2_a[42] = VD1_hilo_10 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add10 # !VD1_hilo_10 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add10;
|
| 22460 |
|
|
|
| 22461 |
|
|
|
| 22462 |
|
|
--VD1_hilo_22_Z[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[42]
|
| 22463 |
|
|
--operation mode is normal
|
| 22464 |
|
|
|
| 22465 |
|
|
VD1_hilo_22_Z[42] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[42] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[42] # !VD1_sign & !VD1_hilo_22_a[42];
|
| 22466 |
|
|
|
| 22467 |
|
|
|
| 22468 |
|
|
--PD1_a_o_3_d_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[10]
|
| 22469 |
|
|
--operation mode is normal
|
| 22470 |
|
|
|
| 22471 |
|
|
PD1_a_o_3_d_a[10] = PD1_a_o_sn_m2 & !PB1_r32_o_10 # !PD1_a_o_sn_m2 & !AB1_r32_o_8;
|
| 22472 |
|
|
|
| 22473 |
|
|
|
| 22474 |
|
|
--UD1_shift_out_87_d_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[10]
|
| 22475 |
|
|
--operation mode is normal
|
| 22476 |
|
|
|
| 22477 |
|
|
UD1_shift_out_87_d_a[10] = PD1_a_o_1 & !VD1_b_o_iv_16 # !PD1_a_o_1 & !VD1_b_o_iv_14;
|
| 22478 |
|
|
|
| 22479 |
|
|
|
| 22480 |
|
|
--UD1_shift_out_80[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[10]
|
| 22481 |
|
|
--operation mode is normal
|
| 22482 |
|
|
|
| 22483 |
|
|
UD1_shift_out_80[10] = PD1_a_o_2 & UD1_shift_out_80_a[10] & VD1_b_o_iv_15 # !UD1_shift_out_80_a[10] & VD1_b_o_iv_17 # !PD1_a_o_2 & !UD1_shift_out_80_a[10];
|
| 22484 |
|
|
|
| 22485 |
|
|
|
| 22486 |
|
|
--UD1_shift_out_76_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[10]
|
| 22487 |
|
|
--operation mode is normal
|
| 22488 |
|
|
|
| 22489 |
|
|
UD1_shift_out_76_a[10] = UD1_shift_out587 & !PD1_a_o_3 & PD1_a_o_2 & !PD1_a_o_1;
|
| 22490 |
|
|
|
| 22491 |
|
|
|
| 22492 |
|
|
--UD1_shift_out_77_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[10]
|
| 22493 |
|
|
--operation mode is normal
|
| 22494 |
|
|
|
| 22495 |
|
|
UD1_shift_out_77_a[10] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_1 # !PD1_a_o_0 & !VD1_b_o_iv_2;
|
| 22496 |
|
|
|
| 22497 |
|
|
|
| 22498 |
|
|
--UD1_shift_out_74[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[10]
|
| 22499 |
|
|
--operation mode is normal
|
| 22500 |
|
|
|
| 22501 |
|
|
UD1_shift_out_74[10] = PD1_a_o_3 & !UD1_shift_out_74_a[7] # !PD1_a_o_3 & UD1_shift_out_74_a[7] & UD1_shift_out_79[18] # !UD1_shift_out_74_a[7] & UD1_shift_out_41[2];
|
| 22502 |
|
|
|
| 22503 |
|
|
|
| 22504 |
|
|
--UD1_shift_out_86_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[10]
|
| 22505 |
|
|
--operation mode is normal
|
| 22506 |
|
|
|
| 22507 |
|
|
UD1_shift_out_86_a[10] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_47[2] # !PD1_a_o_2 & !UD1_shift_out_79[18] # !UD1_shift_out587 & !UD1_shift_out_47[2];
|
| 22508 |
|
|
|
| 22509 |
|
|
|
| 22510 |
|
|
--UD1_shift_out_80_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[11]
|
| 22511 |
|
|
--operation mode is normal
|
| 22512 |
|
|
|
| 22513 |
|
|
UD1_shift_out_80_a[11] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_14 # !PD1_a_o_1 & !VD1_b_o_iv_12;
|
| 22514 |
|
|
|
| 22515 |
|
|
|
| 22516 |
|
|
--VD1_un134_hilo_combout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[11]
|
| 22517 |
|
|
--operation mode is arithmetic
|
| 22518 |
|
|
|
| 22519 |
|
|
VD1_un134_hilo_combout[11]_carry_eqn = VD1_un134_hilo_cout[9];
|
| 22520 |
|
|
VD1_un134_hilo_combout[11] = VD1_hilo_11 $ (VD1_hilo_10 & VD1_un134_hilo_combout[11]_carry_eqn);
|
| 22521 |
|
|
|
| 22522 |
|
|
--VD1_un134_hilo_cout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[11]
|
| 22523 |
|
|
--operation mode is arithmetic
|
| 22524 |
|
|
|
| 22525 |
|
|
VD1_un134_hilo_cout[11] = CARRY(!VD1_un134_hilo_cout[9] # !VD1_hilo_11 # !VD1_hilo_10);
|
| 22526 |
|
|
|
| 22527 |
|
|
|
| 22528 |
|
|
--VD1_hilo_33_i_m[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[43]
|
| 22529 |
|
|
--operation mode is normal
|
| 22530 |
|
|
|
| 22531 |
|
|
VD1_hilo_33_i_m[43] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[43] # !VD1_hilo_33_1[64] & !VD1_hilo_43;
|
| 22532 |
|
|
|
| 22533 |
|
|
|
| 22534 |
|
|
--VD1_hilo_37_iv_2_a[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[43]
|
| 22535 |
|
|
--operation mode is normal
|
| 22536 |
|
|
|
| 22537 |
|
|
VD1_hilo_37_iv_2_a[43] = VD1_hilo_11 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add11 # !VD1_hilo_11 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add11;
|
| 22538 |
|
|
|
| 22539 |
|
|
|
| 22540 |
|
|
--VD1_hilo_22_Z[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[43]
|
| 22541 |
|
|
--operation mode is normal
|
| 22542 |
|
|
|
| 22543 |
|
|
VD1_hilo_22_Z[43] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[43] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[43] # !VD1_sign & !VD1_hilo_22_a[43];
|
| 22544 |
|
|
|
| 22545 |
|
|
|
| 22546 |
|
|
--RD1_r32_o_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_11
|
| 22547 |
|
|
--operation mode is arithmetic
|
| 22548 |
|
|
|
| 22549 |
|
|
RD1_r32_o_11_carry_eqn = RD1_r32_o_cout[9];
|
| 22550 |
|
|
RD1_r32_o_11_lut_out = KB1_r32_o_11 $ (KB1_r32_o_10 & !RD1_r32_o_11_carry_eqn);
|
| 22551 |
|
|
RD1_r32_o_11 = DFFEAS(RD1_r32_o_11_lut_out, E1__clk0, VCC, , , , , , );
|
| 22552 |
|
|
|
| 22553 |
|
|
--RD1_r32_o_cout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[11]
|
| 22554 |
|
|
--operation mode is arithmetic
|
| 22555 |
|
|
|
| 22556 |
|
|
RD1_r32_o_cout[11] = CARRY(KB1_r32_o_10 & KB1_r32_o_11 & !RD1_r32_o_cout[9]);
|
| 22557 |
|
|
|
| 22558 |
|
|
|
| 22559 |
|
|
--PD1_a_o_3_d[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[11]
|
| 22560 |
|
|
--operation mode is normal
|
| 22561 |
|
|
|
| 22562 |
|
|
PD1_a_o_3_d[11] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_11 # !PD1_un6_a_o & !PD1_a_o_3_d_a[11] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[11];
|
| 22563 |
|
|
|
| 22564 |
|
|
|
| 22565 |
|
|
--VD1_un134_hilo_combout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[19]
|
| 22566 |
|
|
--operation mode is arithmetic
|
| 22567 |
|
|
|
| 22568 |
|
|
VD1_un134_hilo_combout[19]_carry_eqn = VD1_un134_hilo_cout[17];
|
| 22569 |
|
|
VD1_un134_hilo_combout[19] = VD1_hilo_19 $ (VD1_hilo_18 & VD1_un134_hilo_combout[19]_carry_eqn);
|
| 22570 |
|
|
|
| 22571 |
|
|
--VD1_un134_hilo_cout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[19]
|
| 22572 |
|
|
--operation mode is arithmetic
|
| 22573 |
|
|
|
| 22574 |
|
|
VD1_un134_hilo_cout[19] = CARRY(!VD1_un134_hilo_cout[17] # !VD1_hilo_19 # !VD1_hilo_18);
|
| 22575 |
|
|
|
| 22576 |
|
|
|
| 22577 |
|
|
--VD1_hilo_33_i_m_a[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[53]
|
| 22578 |
|
|
--operation mode is normal
|
| 22579 |
|
|
|
| 22580 |
|
|
VD1_hilo_33_i_m_a[53] = VD1_addnop2 & !VD1_un50_hilo_add21 # !VD1_addnop2 & !VD1_un59_hilo_add21;
|
| 22581 |
|
|
|
| 22582 |
|
|
|
| 22583 |
|
|
--VD1_hilo_24_add21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add21
|
| 22584 |
|
|
--operation mode is arithmetic
|
| 22585 |
|
|
|
| 22586 |
|
|
VD1_hilo_24_add21_carry_eqn = VD1_hilo_24_carry_20;
|
| 22587 |
|
|
VD1_hilo_24_add21 = VD1_hilo_52 $ VD1_un1_op2_reged_1_combout[21] $ VD1_hilo_24_add21_carry_eqn;
|
| 22588 |
|
|
|
| 22589 |
|
|
--VD1_hilo_24_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_21
|
| 22590 |
|
|
--operation mode is arithmetic
|
| 22591 |
|
|
|
| 22592 |
|
|
VD1_hilo_24_carry_21 = CARRY(VD1_hilo_52 & !VD1_un1_op2_reged_1_combout[21] & !VD1_hilo_24_carry_20 # !VD1_hilo_52 & !VD1_hilo_24_carry_20 # !VD1_un1_op2_reged_1_combout[21]);
|
| 22593 |
|
|
|
| 22594 |
|
|
|
| 22595 |
|
|
--VD1_hilo_22_a[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[53]
|
| 22596 |
|
|
--operation mode is normal
|
| 22597 |
|
|
|
| 22598 |
|
|
VD1_hilo_22_a[53] = VD1_sign & !VD1_hilo_54 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add22 # !VD1_hilo[0] & !VD1_hilo_54;
|
| 22599 |
|
|
|
| 22600 |
|
|
|
| 22601 |
|
|
--VD1_hilo_15_2[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[53]
|
| 22602 |
|
|
--operation mode is normal
|
| 22603 |
|
|
|
| 22604 |
|
|
VD1_hilo_15_2[53] = VD1_sub_or_yn & VD1_un59_hilo_add22 # !VD1_sub_or_yn & VD1_un50_hilo_add22;
|
| 22605 |
|
|
|
| 22606 |
|
|
|
| 22607 |
|
|
--KB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_20
|
| 22608 |
|
|
--operation mode is normal
|
| 22609 |
|
|
|
| 22610 |
|
|
KB1_r32_o_20_lut_out = DD1_pc_next_0_iv_1_20 # DD1_un1_pc_next46_0 & DD1_un1_pc_add20;
|
| 22611 |
|
|
KB1_r32_o_20 = DFFEAS(KB1_r32_o_20_lut_out, E1__clk0, VCC, , , , , , );
|
| 22612 |
|
|
|
| 22613 |
|
|
|
| 22614 |
|
|
--KB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_21
|
| 22615 |
|
|
--operation mode is normal
|
| 22616 |
|
|
|
| 22617 |
|
|
KB1_r32_o_21_lut_out = DD1_pc_next_0_iv_1_21 # DD1_un1_pc_next46_0 & DD1_un1_pc_add21;
|
| 22618 |
|
|
KB1_r32_o_21 = DFFEAS(KB1_r32_o_21_lut_out, E1__clk0, VCC, , , , , , );
|
| 22619 |
|
|
|
| 22620 |
|
|
|
| 22621 |
|
|
--RD1_r32_o_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_19
|
| 22622 |
|
|
--operation mode is arithmetic
|
| 22623 |
|
|
|
| 22624 |
|
|
RD1_r32_o_19_carry_eqn = RD1_r32_o_cout[17];
|
| 22625 |
|
|
RD1_r32_o_19_lut_out = KB1_r32_o_19 $ (KB1_r32_o_18 & !RD1_r32_o_19_carry_eqn);
|
| 22626 |
|
|
RD1_r32_o_19 = DFFEAS(RD1_r32_o_19_lut_out, E1__clk0, VCC, , , , , , );
|
| 22627 |
|
|
|
| 22628 |
|
|
--RD1_r32_o_cout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[19]
|
| 22629 |
|
|
--operation mode is arithmetic
|
| 22630 |
|
|
|
| 22631 |
|
|
RD1_r32_o_cout[19] = CARRY(KB1_r32_o_18 & KB1_r32_o_19 & !RD1_r32_o_cout[17]);
|
| 22632 |
|
|
|
| 22633 |
|
|
|
| 22634 |
|
|
--PD1_a_o_3_d_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[21]
|
| 22635 |
|
|
--operation mode is normal
|
| 22636 |
|
|
|
| 22637 |
|
|
PD1_a_o_3_d_a[21] = PD1_a_o_sn_m2 & !PB1_r32_o_21 # !PD1_a_o_sn_m2 & !AB1_r32_o_19;
|
| 22638 |
|
|
|
| 22639 |
|
|
|
| 22640 |
|
|
--VD1_un134_hilo_combout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[18]
|
| 22641 |
|
|
--operation mode is arithmetic
|
| 22642 |
|
|
|
| 22643 |
|
|
VD1_un134_hilo_combout[18]_carry_eqn = VD1_un134_hilo_cout[16];
|
| 22644 |
|
|
VD1_un134_hilo_combout[18] = VD1_hilo_18 $ (VD1_un134_hilo_combout[18]_carry_eqn);
|
| 22645 |
|
|
|
| 22646 |
|
|
--VD1_un134_hilo_cout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[18]
|
| 22647 |
|
|
--operation mode is arithmetic
|
| 22648 |
|
|
|
| 22649 |
|
|
VD1_un134_hilo_cout[18] = CARRY(!VD1_un134_hilo_cout[16] # !VD1_hilo_19 # !VD1_hilo_18);
|
| 22650 |
|
|
|
| 22651 |
|
|
|
| 22652 |
|
|
--VD1_un1_op2_reged_1_i_m6[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_i_m6[20]
|
| 22653 |
|
|
--operation mode is normal
|
| 22654 |
|
|
|
| 22655 |
|
|
VD1_un1_op2_reged_1_i_m6[20] = VD1_eqop2_2_32 & VD1_op2_reged[20] # !VD1_eqop2_2_32 & VD1_nop2_reged[20];
|
| 22656 |
|
|
|
| 22657 |
|
|
|
| 22658 |
|
|
--VD1_hilo_24_add19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add19
|
| 22659 |
|
|
--operation mode is arithmetic
|
| 22660 |
|
|
|
| 22661 |
|
|
VD1_hilo_24_add19_carry_eqn = VD1_hilo_24_carry_18;
|
| 22662 |
|
|
VD1_hilo_24_add19 = VD1_hilo_50 $ VD1_un1_op2_reged_1_combout[19] $ VD1_hilo_24_add19_carry_eqn;
|
| 22663 |
|
|
|
| 22664 |
|
|
--VD1_hilo_24_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_19
|
| 22665 |
|
|
--operation mode is arithmetic
|
| 22666 |
|
|
|
| 22667 |
|
|
VD1_hilo_24_carry_19 = CARRY(VD1_hilo_50 & !VD1_un1_op2_reged_1_combout[19] & !VD1_hilo_24_carry_18 # !VD1_hilo_50 & !VD1_hilo_24_carry_18 # !VD1_un1_op2_reged_1_combout[19]);
|
| 22668 |
|
|
|
| 22669 |
|
|
|
| 22670 |
|
|
--VD1_un59_hilo_add21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add21
|
| 22671 |
|
|
--operation mode is arithmetic
|
| 22672 |
|
|
|
| 22673 |
|
|
VD1_un59_hilo_add21_carry_eqn = VD1_un59_hilo_carry_20;
|
| 22674 |
|
|
VD1_un59_hilo_add21 = VD1_hilo_53 $ VD1_op2_reged[21] $ VD1_un59_hilo_add21_carry_eqn;
|
| 22675 |
|
|
|
| 22676 |
|
|
--VD1_un59_hilo_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_21
|
| 22677 |
|
|
--operation mode is arithmetic
|
| 22678 |
|
|
|
| 22679 |
|
|
VD1_un59_hilo_carry_21 = CARRY(VD1_hilo_53 & !VD1_op2_reged[21] & !VD1_un59_hilo_carry_20 # !VD1_hilo_53 & !VD1_un59_hilo_carry_20 # !VD1_op2_reged[21]);
|
| 22680 |
|
|
|
| 22681 |
|
|
|
| 22682 |
|
|
--VD1_hilo_37_iv_0_1[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[52]
|
| 22683 |
|
|
--operation mode is normal
|
| 22684 |
|
|
|
| 22685 |
|
|
VD1_hilo_37_iv_0_1[52] = VD1_hilo_37_iv_0_1_a[52] # VD1_addop2 & !VD1_un59_hilo_add20 & VD1_hilo_37_iv_0_a2_7[34];
|
| 22686 |
|
|
|
| 22687 |
|
|
|
| 22688 |
|
|
--VD1_un50_hilo_add20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add20
|
| 22689 |
|
|
--operation mode is arithmetic
|
| 22690 |
|
|
|
| 22691 |
|
|
VD1_un50_hilo_add20_carry_eqn = VD1_un50_hilo_carry_19;
|
| 22692 |
|
|
VD1_un50_hilo_add20 = VD1_hilo_52 $ VD1_nop2_reged[20] $ !VD1_un50_hilo_add20_carry_eqn;
|
| 22693 |
|
|
|
| 22694 |
|
|
--VD1_un50_hilo_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_20
|
| 22695 |
|
|
--operation mode is arithmetic
|
| 22696 |
|
|
|
| 22697 |
|
|
VD1_un50_hilo_carry_20 = CARRY(VD1_hilo_52 & VD1_nop2_reged[20] # !VD1_un50_hilo_carry_19 # !VD1_hilo_52 & VD1_nop2_reged[20] & !VD1_un50_hilo_carry_19);
|
| 22698 |
|
|
|
| 22699 |
|
|
|
| 22700 |
|
|
--VD1_hilo_37_iv_0_4_a[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4_a[52]
|
| 22701 |
|
|
--operation mode is normal
|
| 22702 |
|
|
|
| 22703 |
|
|
VD1_hilo_37_iv_0_4_a[52] = !VD1_sub_or_yn & VD1_hilo_37_iv_0_a2_7_2_1[37] & VD1_hilo_1_sqmuxa_1 & !VD1_un50_hilo_add21;
|
| 22704 |
|
|
|
| 22705 |
|
|
|
| 22706 |
|
|
--RD1_r32_o_0_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_18
|
| 22707 |
|
|
--operation mode is arithmetic
|
| 22708 |
|
|
|
| 22709 |
|
|
RD1_r32_o_0_18_carry_eqn = RD1_r32_o_cout[16];
|
| 22710 |
|
|
RD1_r32_o_0_18_lut_out = KB1_r32_o_18 $ (!RD1_r32_o_0_18_carry_eqn);
|
| 22711 |
|
|
RD1_r32_o_0_18 = DFFEAS(RD1_r32_o_0_18_lut_out, E1__clk0, VCC, , , , , , );
|
| 22712 |
|
|
|
| 22713 |
|
|
--RD1_r32_o_cout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[18]
|
| 22714 |
|
|
--operation mode is arithmetic
|
| 22715 |
|
|
|
| 22716 |
|
|
RD1_r32_o_cout[18] = CARRY(KB1_r32_o_18 & KB1_r32_o_19 & !RD1_r32_o_cout[16]);
|
| 22717 |
|
|
|
| 22718 |
|
|
|
| 22719 |
|
|
--PD1_a_o_3_d_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[20]
|
| 22720 |
|
|
--operation mode is normal
|
| 22721 |
|
|
|
| 22722 |
|
|
PD1_a_o_3_d_a[20] = PD1_a_o_sn_m2 & !PB1_r32_o_20 # !PD1_a_o_sn_m2 & !AB1_r32_o_18;
|
| 22723 |
|
|
|
| 22724 |
|
|
|
| 22725 |
|
|
--UD1_shift_out_48_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48_a[28]
|
| 22726 |
|
|
--operation mode is normal
|
| 22727 |
|
|
|
| 22728 |
|
|
UD1_shift_out_48_a[28] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_5 # !PD1_a_o_0 & !VD1_b_o_iv_6 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 22729 |
|
|
|
| 22730 |
|
|
|
| 22731 |
|
|
--UD1_shift_out_80_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[19]
|
| 22732 |
|
|
--operation mode is normal
|
| 22733 |
|
|
|
| 22734 |
|
|
UD1_shift_out_80_a[19] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_22 # !PD1_a_o_1 & !VD1_b_o_iv_20;
|
| 22735 |
|
|
|
| 22736 |
|
|
|
| 22737 |
|
|
--VD1_hilo_37_iv_0_8_a[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_8_a[51]
|
| 22738 |
|
|
--operation mode is normal
|
| 22739 |
|
|
|
| 22740 |
|
|
VD1_hilo_37_iv_0_8_a[51] = VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add19 # !VD1_un50_hilo_add20 # !VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add19;
|
| 22741 |
|
|
|
| 22742 |
|
|
|
| 22743 |
|
|
--VD1_hilo_37_iv_0_6[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6[51]
|
| 22744 |
|
|
--operation mode is normal
|
| 22745 |
|
|
|
| 22746 |
|
|
VD1_hilo_37_iv_0_6[51] = VD1_hilo_37_iv_0_2[51] # VD1_hilo_37_iv_0_6_a[51] # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add19;
|
| 22747 |
|
|
|
| 22748 |
|
|
|
| 22749 |
|
|
--SD1_r32_o_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_19
|
| 22750 |
|
|
--operation mode is normal
|
| 22751 |
|
|
|
| 22752 |
|
|
SD1_r32_o_19_lut_out = KB1_r32_o_19;
|
| 22753 |
|
|
SD1_r32_o_19 = DFFEAS(SD1_r32_o_19_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 22754 |
|
|
|
| 22755 |
|
|
|
| 22756 |
|
|
--PD1_a_o_3_d[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[19]
|
| 22757 |
|
|
--operation mode is normal
|
| 22758 |
|
|
|
| 22759 |
|
|
PD1_a_o_3_d[19] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_19 # !PD1_un6_a_o & !PD1_a_o_3_d_a[19] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[19];
|
| 22760 |
|
|
|
| 22761 |
|
|
|
| 22762 |
|
|
--UD1_shift_out_80_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[18]
|
| 22763 |
|
|
--operation mode is normal
|
| 22764 |
|
|
|
| 22765 |
|
|
UD1_shift_out_80_a[18] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_21 # !PD1_a_o_1 & !VD1_b_o_iv_19;
|
| 22766 |
|
|
|
| 22767 |
|
|
|
| 22768 |
|
|
--UD1_shift_out_52_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52_a[30]
|
| 22769 |
|
|
--operation mode is normal
|
| 22770 |
|
|
|
| 22771 |
|
|
UD1_shift_out_52_a[30] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_11 # !PD1_a_o_0 & !VD1_b_o_iv_12 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 22772 |
|
|
|
| 22773 |
|
|
|
| 22774 |
|
|
--VD1_hilo_37_iv_1_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1_a[18]
|
| 22775 |
|
|
--operation mode is normal
|
| 22776 |
|
|
|
| 22777 |
|
|
VD1_hilo_37_iv_1_a[18] = VD1_hilo_19 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_29_Z[18] # !VD1_hilo_3_sqmuxa # !VD1_hilo_19 & !VD1_hilo_29_Z[18] # !VD1_hilo_3_sqmuxa;
|
| 22778 |
|
|
|
| 22779 |
|
|
|
| 22780 |
|
|
--VD1_un59_hilo_add19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add19
|
| 22781 |
|
|
--operation mode is arithmetic
|
| 22782 |
|
|
|
| 22783 |
|
|
VD1_un59_hilo_add19_carry_eqn = VD1_un59_hilo_carry_18;
|
| 22784 |
|
|
VD1_un59_hilo_add19 = VD1_hilo_51 $ VD1_op2_reged[19] $ VD1_un59_hilo_add19_carry_eqn;
|
| 22785 |
|
|
|
| 22786 |
|
|
--VD1_un59_hilo_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_19
|
| 22787 |
|
|
--operation mode is arithmetic
|
| 22788 |
|
|
|
| 22789 |
|
|
VD1_un59_hilo_carry_19 = CARRY(VD1_hilo_51 & !VD1_op2_reged[19] & !VD1_un59_hilo_carry_18 # !VD1_hilo_51 & !VD1_un59_hilo_carry_18 # !VD1_op2_reged[19]);
|
| 22790 |
|
|
|
| 22791 |
|
|
|
| 22792 |
|
|
--VD1_un50_hilo_add18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add18
|
| 22793 |
|
|
--operation mode is arithmetic
|
| 22794 |
|
|
|
| 22795 |
|
|
VD1_un50_hilo_add18_carry_eqn = VD1_un50_hilo_carry_17;
|
| 22796 |
|
|
VD1_un50_hilo_add18 = VD1_hilo_50 $ VD1_nop2_reged[18] $ !VD1_un50_hilo_add18_carry_eqn;
|
| 22797 |
|
|
|
| 22798 |
|
|
--VD1_un50_hilo_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_18
|
| 22799 |
|
|
--operation mode is arithmetic
|
| 22800 |
|
|
|
| 22801 |
|
|
VD1_un50_hilo_carry_18 = CARRY(VD1_hilo_50 & VD1_nop2_reged[18] # !VD1_un50_hilo_carry_17 # !VD1_hilo_50 & VD1_nop2_reged[18] & !VD1_un50_hilo_carry_17);
|
| 22802 |
|
|
|
| 22803 |
|
|
|
| 22804 |
|
|
--VD1_hilo_37_iv_0_1[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[50]
|
| 22805 |
|
|
--operation mode is normal
|
| 22806 |
|
|
|
| 22807 |
|
|
VD1_hilo_37_iv_0_1[50] = VD1_hilo_37_iv_0_1_a[50] # !VD1_hilo_50 & !VD1_hilo_33_1[64] & VD1_hilo_3_sqmuxa;
|
| 22808 |
|
|
|
| 22809 |
|
|
|
| 22810 |
|
|
--VD1_un50_hilo_add19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add19
|
| 22811 |
|
|
--operation mode is arithmetic
|
| 22812 |
|
|
|
| 22813 |
|
|
VD1_un50_hilo_add19_carry_eqn = VD1_un50_hilo_carry_18;
|
| 22814 |
|
|
VD1_un50_hilo_add19 = VD1_hilo_51 $ VD1_nop2_reged[19] $ VD1_un50_hilo_add19_carry_eqn;
|
| 22815 |
|
|
|
| 22816 |
|
|
--VD1_un50_hilo_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_19
|
| 22817 |
|
|
--operation mode is arithmetic
|
| 22818 |
|
|
|
| 22819 |
|
|
VD1_un50_hilo_carry_19 = CARRY(VD1_hilo_51 & !VD1_nop2_reged[19] & !VD1_un50_hilo_carry_18 # !VD1_hilo_51 & !VD1_un50_hilo_carry_18 # !VD1_nop2_reged[19]);
|
| 22820 |
|
|
|
| 22821 |
|
|
|
| 22822 |
|
|
--VD1_hilo_37_iv_0_5_a[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[50]
|
| 22823 |
|
|
--operation mode is normal
|
| 22824 |
|
|
|
| 22825 |
|
|
VD1_hilo_37_iv_0_5_a[50] = VD1_hilo_51 & !VD1_hilo_50 & VD1_hilo_37_iv_0_a3_1[62] # !VD1_hilo_51 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_hilo_50 & VD1_hilo_37_iv_0_a3_1[62];
|
| 22826 |
|
|
|
| 22827 |
|
|
|
| 22828 |
|
|
--VD1_hilo_24_add18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add18
|
| 22829 |
|
|
--operation mode is arithmetic
|
| 22830 |
|
|
|
| 22831 |
|
|
VD1_hilo_24_add18_carry_eqn = VD1_hilo_24_carry_17;
|
| 22832 |
|
|
VD1_hilo_24_add18 = VD1_hilo_49 $ VD1_un1_op2_reged_1_combout[18] $ !VD1_hilo_24_add18_carry_eqn;
|
| 22833 |
|
|
|
| 22834 |
|
|
--VD1_hilo_24_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_18
|
| 22835 |
|
|
--operation mode is arithmetic
|
| 22836 |
|
|
|
| 22837 |
|
|
VD1_hilo_24_carry_18 = CARRY(VD1_hilo_49 & VD1_un1_op2_reged_1_combout[18] # !VD1_hilo_24_carry_17 # !VD1_hilo_49 & VD1_un1_op2_reged_1_combout[18] & !VD1_hilo_24_carry_17);
|
| 22838 |
|
|
|
| 22839 |
|
|
|
| 22840 |
|
|
--SD1_r32_o_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_18
|
| 22841 |
|
|
--operation mode is normal
|
| 22842 |
|
|
|
| 22843 |
|
|
SD1_r32_o_18_lut_out = KB1_r32_o_18;
|
| 22844 |
|
|
SD1_r32_o_18 = DFFEAS(SD1_r32_o_18_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 22845 |
|
|
|
| 22846 |
|
|
|
| 22847 |
|
|
--PD1_a_o_3_d[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[18]
|
| 22848 |
|
|
--operation mode is normal
|
| 22849 |
|
|
|
| 22850 |
|
|
PD1_a_o_3_d[18] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_18 # !PD1_un6_a_o & !PD1_a_o_3_d_a[18] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[18];
|
| 22851 |
|
|
|
| 22852 |
|
|
|
| 22853 |
|
|
--UD1_shift_out_80_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[26]
|
| 22854 |
|
|
--operation mode is normal
|
| 22855 |
|
|
|
| 22856 |
|
|
UD1_shift_out_80_a[26] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_29 # !PD1_a_o_1 & !VD1_b_o_iv_27;
|
| 22857 |
|
|
|
| 22858 |
|
|
|
| 22859 |
|
|
--UD1_shift_out_77[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[26]
|
| 22860 |
|
|
--operation mode is normal
|
| 22861 |
|
|
|
| 22862 |
|
|
UD1_shift_out_77[26] = PD1_a_o_2 & UD1_shift_out_85_d[18] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[18] # !PD1_a_o_1 & !UD1_shift_out_77_a[26];
|
| 22863 |
|
|
|
| 22864 |
|
|
|
| 22865 |
|
|
--VD1_hilo_37_iv_0_1_a[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[58]
|
| 22866 |
|
|
--operation mode is normal
|
| 22867 |
|
|
|
| 22868 |
|
|
VD1_hilo_37_iv_0_1_a[58] = VD1_hilo_26 & !VD1_hilo_58 & VD1_hilo_37_iv_0_a3_1[62] # !VD1_hilo_26 & VD1_hilo_0_sqmuxa # !VD1_hilo_58 & VD1_hilo_37_iv_0_a3_1[62];
|
| 22869 |
|
|
|
| 22870 |
|
|
|
| 22871 |
|
|
--VD1_hilo_24_add26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add26
|
| 22872 |
|
|
--operation mode is arithmetic
|
| 22873 |
|
|
|
| 22874 |
|
|
VD1_hilo_24_add26_carry_eqn = VD1_hilo_24_carry_25;
|
| 22875 |
|
|
VD1_hilo_24_add26 = VD1_hilo_57 $ VD1_un1_op2_reged_1_combout[26] $ !VD1_hilo_24_add26_carry_eqn;
|
| 22876 |
|
|
|
| 22877 |
|
|
--VD1_hilo_24_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_26
|
| 22878 |
|
|
--operation mode is arithmetic
|
| 22879 |
|
|
|
| 22880 |
|
|
VD1_hilo_24_carry_26 = CARRY(VD1_hilo_57 & VD1_un1_op2_reged_1_combout[26] # !VD1_hilo_24_carry_25 # !VD1_hilo_57 & VD1_un1_op2_reged_1_combout[26] & !VD1_hilo_24_carry_25);
|
| 22881 |
|
|
|
| 22882 |
|
|
|
| 22883 |
|
|
--VD1_hilo_37_iv_0_o3_1_0_1_1[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1_0_1_1[58]
|
| 22884 |
|
|
--operation mode is normal
|
| 22885 |
|
|
|
| 22886 |
|
|
VD1_hilo_37_iv_0_o3_1_0_1_1[58] = VD1_hilo_37_iv_0_o3_1_0_1_1_a[58] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add27;
|
| 22887 |
|
|
|
| 22888 |
|
|
|
| 22889 |
|
|
--VD1_hilo_37_iv_0_o3_a[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_a[58]
|
| 22890 |
|
|
--operation mode is normal
|
| 22891 |
|
|
|
| 22892 |
|
|
VD1_hilo_37_iv_0_o3_a[58] = VD1_addop2 & !VD1_addnop2 & !VD1_un59_hilo_add26 # !VD1_addop2 & VD1_addnop2 & !VD1_un50_hilo_add26;
|
| 22893 |
|
|
|
| 22894 |
|
|
|
| 22895 |
|
|
--RD1_r32_o_0_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_26
|
| 22896 |
|
|
--operation mode is arithmetic
|
| 22897 |
|
|
|
| 22898 |
|
|
RD1_r32_o_0_26_carry_eqn = RD1_r32_o_cout[24];
|
| 22899 |
|
|
RD1_r32_o_0_26_lut_out = KB1_r32_o_26 $ (!RD1_r32_o_0_26_carry_eqn);
|
| 22900 |
|
|
RD1_r32_o_0_26 = DFFEAS(RD1_r32_o_0_26_lut_out, E1__clk0, VCC, , , , , , );
|
| 22901 |
|
|
|
| 22902 |
|
|
--RD1_r32_o_cout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[26]
|
| 22903 |
|
|
--operation mode is arithmetic
|
| 22904 |
|
|
|
| 22905 |
|
|
RD1_r32_o_cout[26] = CARRY(KB1_r32_o_26 & KB1_r32_o_27 & !RD1_r32_o_cout[24]);
|
| 22906 |
|
|
|
| 22907 |
|
|
|
| 22908 |
|
|
--SD1_r32_o_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_26
|
| 22909 |
|
|
--operation mode is normal
|
| 22910 |
|
|
|
| 22911 |
|
|
SD1_r32_o_26_lut_out = KB1_r32_o_26;
|
| 22912 |
|
|
SD1_r32_o_26 = DFFEAS(SD1_r32_o_26_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 22913 |
|
|
|
| 22914 |
|
|
|
| 22915 |
|
|
--PD1_a_o_3_d[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[26]
|
| 22916 |
|
|
--operation mode is normal
|
| 22917 |
|
|
|
| 22918 |
|
|
PD1_a_o_3_d[26] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_26 # !PD1_un6_a_o & !PD1_a_o_3_d_a[26] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[26];
|
| 22919 |
|
|
|
| 22920 |
|
|
|
| 22921 |
|
|
--UD1_shift_out_80_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[27]
|
| 22922 |
|
|
--operation mode is normal
|
| 22923 |
|
|
|
| 22924 |
|
|
UD1_shift_out_80_a[27] = PD1_a_o_2 & !UD1_shift_out_36_0 # !PD1_a_o_2 & !VD1_b_o_iv_30;
|
| 22925 |
|
|
|
| 22926 |
|
|
|
| 22927 |
|
|
--VD1_hilo_37_iv_0_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[27]
|
| 22928 |
|
|
--operation mode is normal
|
| 22929 |
|
|
|
| 22930 |
|
|
VD1_hilo_37_iv_0_a[27] = VD1_add1 & !VD1_un134_hilo_combout[27] # !VD1_add1 & !VD1_hilo_27;
|
| 22931 |
|
|
|
| 22932 |
|
|
|
| 22933 |
|
|
--VD1_hilo_24_add27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add27
|
| 22934 |
|
|
--operation mode is arithmetic
|
| 22935 |
|
|
|
| 22936 |
|
|
VD1_hilo_24_add27_carry_eqn = VD1_hilo_24_carry_26;
|
| 22937 |
|
|
VD1_hilo_24_add27 = VD1_hilo_58 $ VD1_un1_op2_reged_1_combout[27] $ VD1_hilo_24_add27_carry_eqn;
|
| 22938 |
|
|
|
| 22939 |
|
|
--VD1_hilo_24_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_27
|
| 22940 |
|
|
--operation mode is arithmetic
|
| 22941 |
|
|
|
| 22942 |
|
|
VD1_hilo_24_carry_27 = CARRY(VD1_hilo_58 & !VD1_un1_op2_reged_1_combout[27] & !VD1_hilo_24_carry_26 # !VD1_hilo_58 & !VD1_hilo_24_carry_26 # !VD1_un1_op2_reged_1_combout[27]);
|
| 22943 |
|
|
|
| 22944 |
|
|
|
| 22945 |
|
|
--VD1_hilo_37_iv_0_6[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6[59]
|
| 22946 |
|
|
--operation mode is normal
|
| 22947 |
|
|
|
| 22948 |
|
|
VD1_hilo_37_iv_0_6[59] = VD1_hilo_37_iv_0_3[59] # VD1_hilo_37_iv_0_6_a[59] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add28;
|
| 22949 |
|
|
|
| 22950 |
|
|
|
| 22951 |
|
|
--SD1_r32_o_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_27
|
| 22952 |
|
|
--operation mode is normal
|
| 22953 |
|
|
|
| 22954 |
|
|
SD1_r32_o_27_lut_out = KB1_r32_o_27;
|
| 22955 |
|
|
SD1_r32_o_27 = DFFEAS(SD1_r32_o_27_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 22956 |
|
|
|
| 22957 |
|
|
|
| 22958 |
|
|
--PD1_a_o_3_d[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[27]
|
| 22959 |
|
|
--operation mode is normal
|
| 22960 |
|
|
|
| 22961 |
|
|
PD1_a_o_3_d[27] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_27 # !PD1_un6_a_o & !PD1_a_o_3_d_a[27] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[27];
|
| 22962 |
|
|
|
| 22963 |
|
|
|
| 22964 |
|
|
--SD1_r32_o_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_28
|
| 22965 |
|
|
--operation mode is normal
|
| 22966 |
|
|
|
| 22967 |
|
|
SD1_r32_o_28_lut_out = KB1_r32_o_28;
|
| 22968 |
|
|
SD1_r32_o_28 = DFFEAS(SD1_r32_o_28_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 22969 |
|
|
|
| 22970 |
|
|
|
| 22971 |
|
|
--PD1_a_o_3_d[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[28]
|
| 22972 |
|
|
--operation mode is normal
|
| 22973 |
|
|
|
| 22974 |
|
|
PD1_a_o_3_d[28] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_28 # !PD1_un6_a_o & !PD1_a_o_3_d_a[28] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[28];
|
| 22975 |
|
|
|
| 22976 |
|
|
|
| 22977 |
|
|
--VD1_hilo_60 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_60
|
| 22978 |
|
|
--operation mode is normal
|
| 22979 |
|
|
|
| 22980 |
|
|
VD1_hilo_60_lut_out = VD1_hilo_37_iv_0_a[60] & !VD1_hilo_37_iv_0_a3[57] & PD1_a_o_28 # !VD1_hilo_37_iv_0_a3_1[0];
|
| 22981 |
|
|
VD1_hilo_60 = DFFEAS(VD1_hilo_60_lut_out, E1__clk0, VCC, , C1_G_505, , , !sys_rst, );
|
| 22982 |
|
|
|
| 22983 |
|
|
|
| 22984 |
|
|
--UD1_shift_out_75_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75_a[28]
|
| 22985 |
|
|
--operation mode is normal
|
| 22986 |
|
|
|
| 22987 |
|
|
UD1_shift_out_75_a[28] = PD1_a_o_3 & !PD1_a_o_2 # !PD1_a_o_3 & PD1_a_o_2 & !UD1_shift_out_48[28] # !PD1_a_o_2 & !UD1_shift_out_52[28];
|
| 22988 |
|
|
|
| 22989 |
|
|
|
| 22990 |
|
|
--UD1_shift_out_77_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[28]
|
| 22991 |
|
|
--operation mode is normal
|
| 22992 |
|
|
|
| 22993 |
|
|
UD1_shift_out_77_a[28] = PD1_a_o_2 & !UD1_shift_out_54[28] # !PD1_a_o_2 & !PD1_a_o_1;
|
| 22994 |
|
|
|
| 22995 |
|
|
|
| 22996 |
|
|
--VD1_hilo_37_iv_0_6[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6[61]
|
| 22997 |
|
|
--operation mode is normal
|
| 22998 |
|
|
|
| 22999 |
|
|
VD1_hilo_37_iv_0_6[61] = VD1_hilo_37_iv_0_3[61] # VD1_hilo_37_iv_0_6_a[61] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add30;
|
| 23000 |
|
|
|
| 23001 |
|
|
|
| 23002 |
|
|
--VD1_hilo_33_i_m_a[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[45]
|
| 23003 |
|
|
--operation mode is normal
|
| 23004 |
|
|
|
| 23005 |
|
|
VD1_hilo_33_i_m_a[45] = VD1_addnop2 & !VD1_un50_hilo_add13 # !VD1_addnop2 & !VD1_un59_hilo_add13;
|
| 23006 |
|
|
|
| 23007 |
|
|
|
| 23008 |
|
|
--VD1_hilo_24_add13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add13
|
| 23009 |
|
|
--operation mode is arithmetic
|
| 23010 |
|
|
|
| 23011 |
|
|
VD1_hilo_24_add13_carry_eqn = VD1_hilo_24_carry_12;
|
| 23012 |
|
|
VD1_hilo_24_add13 = VD1_hilo_44 $ VD1_un1_op2_reged_1_combout[13] $ VD1_hilo_24_add13_carry_eqn;
|
| 23013 |
|
|
|
| 23014 |
|
|
--VD1_hilo_24_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_13
|
| 23015 |
|
|
--operation mode is arithmetic
|
| 23016 |
|
|
|
| 23017 |
|
|
VD1_hilo_24_carry_13 = CARRY(VD1_hilo_44 & !VD1_un1_op2_reged_1_combout[13] & !VD1_hilo_24_carry_12 # !VD1_hilo_44 & !VD1_hilo_24_carry_12 # !VD1_un1_op2_reged_1_combout[13]);
|
| 23018 |
|
|
|
| 23019 |
|
|
|
| 23020 |
|
|
--VD1_hilo_22_a[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[45]
|
| 23021 |
|
|
--operation mode is normal
|
| 23022 |
|
|
|
| 23023 |
|
|
VD1_hilo_22_a[45] = VD1_sign & !VD1_hilo_46 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add14 # !VD1_hilo[0] & !VD1_hilo_46;
|
| 23024 |
|
|
|
| 23025 |
|
|
|
| 23026 |
|
|
--VD1_hilo_15_2[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[45]
|
| 23027 |
|
|
--operation mode is normal
|
| 23028 |
|
|
|
| 23029 |
|
|
VD1_hilo_15_2[45] = VD1_sub_or_yn & VD1_un59_hilo_add14 # !VD1_sub_or_yn & VD1_un50_hilo_add14;
|
| 23030 |
|
|
|
| 23031 |
|
|
|
| 23032 |
|
|
--KB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_13
|
| 23033 |
|
|
--operation mode is normal
|
| 23034 |
|
|
|
| 23035 |
|
|
KB1_r32_o_13_lut_out = DD1_pc_next_0_iv_1_13 # DD1_un1_pc_next46_0 & DD1_un1_pc_add13;
|
| 23036 |
|
|
KB1_r32_o_13 = DFFEAS(KB1_r32_o_13_lut_out, E1__clk0, VCC, , , , , , );
|
| 23037 |
|
|
|
| 23038 |
|
|
|
| 23039 |
|
|
--PD1_a_o_3_d_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[13]
|
| 23040 |
|
|
--operation mode is normal
|
| 23041 |
|
|
|
| 23042 |
|
|
PD1_a_o_3_d_a[13] = PD1_a_o_sn_m2 & !PB1_r32_o_13 # !PD1_a_o_sn_m2 & !AB1_r32_o_11;
|
| 23043 |
|
|
|
| 23044 |
|
|
|
| 23045 |
|
|
--VD1_hilo_37_iv_0_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[28]
|
| 23046 |
|
|
--operation mode is normal
|
| 23047 |
|
|
|
| 23048 |
|
|
VD1_hilo_37_iv_0_a[28] = VD1_hilo_29 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_27 # !VD1_hilo_29 & !VD1_hilo_2_sqmuxa # !VD1_hilo_27;
|
| 23049 |
|
|
|
| 23050 |
|
|
|
| 23051 |
|
|
--VD1_hilo_37_iv_0_0[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[28]
|
| 23052 |
|
|
--operation mode is normal
|
| 23053 |
|
|
|
| 23054 |
|
|
VD1_hilo_37_iv_0_0[28] = VD1_hilo_28 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[28] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_28 & VD1_un134_hilo_combout[28] & VD1_hilo_37_iv_0_a3_0[0];
|
| 23055 |
|
|
|
| 23056 |
|
|
|
| 23057 |
|
|
--VD1_un134_hilo_combout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[27]
|
| 23058 |
|
|
--operation mode is arithmetic
|
| 23059 |
|
|
|
| 23060 |
|
|
VD1_un134_hilo_combout[27]_carry_eqn = VD1_un134_hilo_cout[25];
|
| 23061 |
|
|
VD1_un134_hilo_combout[27] = VD1_hilo_27 $ (VD1_hilo_26 & VD1_un134_hilo_combout[27]_carry_eqn);
|
| 23062 |
|
|
|
| 23063 |
|
|
--VD1_un134_hilo_cout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[27]
|
| 23064 |
|
|
--operation mode is arithmetic
|
| 23065 |
|
|
|
| 23066 |
|
|
VD1_un134_hilo_cout[27] = CARRY(!VD1_un134_hilo_cout[25] # !VD1_hilo_27 # !VD1_hilo_26);
|
| 23067 |
|
|
|
| 23068 |
|
|
|
| 23069 |
|
|
--VD1_un134_hilo_combout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[24]
|
| 23070 |
|
|
--operation mode is arithmetic
|
| 23071 |
|
|
|
| 23072 |
|
|
VD1_un134_hilo_combout[24]_carry_eqn = VD1_un134_hilo_cout[22];
|
| 23073 |
|
|
VD1_un134_hilo_combout[24] = VD1_hilo_24 $ (!VD1_un134_hilo_combout[24]_carry_eqn);
|
| 23074 |
|
|
|
| 23075 |
|
|
--VD1_un134_hilo_cout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[24]
|
| 23076 |
|
|
--operation mode is arithmetic
|
| 23077 |
|
|
|
| 23078 |
|
|
VD1_un134_hilo_cout[24] = CARRY(VD1_hilo_24 & VD1_hilo_25 & !VD1_un134_hilo_cout[22]);
|
| 23079 |
|
|
|
| 23080 |
|
|
|
| 23081 |
|
|
--PB1_dout_iv_30 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_30
|
| 23082 |
|
|
--operation mode is normal
|
| 23083 |
|
|
|
| 23084 |
|
|
PB1_dout_iv_30 = HD1_dout_iv_1_30 # FD1_wb_o_30 & HD1_dout7_0_a2;
|
| 23085 |
|
|
|
| 23086 |
|
|
--PB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_30
|
| 23087 |
|
|
--operation mode is normal
|
| 23088 |
|
|
|
| 23089 |
|
|
PB1_r32_o_30 = DFFEAS(PB1_dout_iv_30, E1__clk0, VCC, , , , , , );
|
| 23090 |
|
|
|
| 23091 |
|
|
|
| 23092 |
|
|
--VD1_nop2_reged[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[30]
|
| 23093 |
|
|
--operation mode is arithmetic
|
| 23094 |
|
|
|
| 23095 |
|
|
VD1_nop2_reged[30]_carry_eqn = VD1_nop2_reged_cout[28];
|
| 23096 |
|
|
VD1_nop2_reged[30] = VD1_op2_reged[30] $ !VD1_nop2_reged[30]_carry_eqn;
|
| 23097 |
|
|
|
| 23098 |
|
|
--VD1_nop2_reged_cout[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[30]
|
| 23099 |
|
|
--operation mode is arithmetic
|
| 23100 |
|
|
|
| 23101 |
|
|
VD1_nop2_reged_cout[30] = CARRY(VD1_op2_reged[31] # VD1_op2_reged[30] # !VD1_nop2_reged_cout[28]);
|
| 23102 |
|
|
|
| 23103 |
|
|
|
| 23104 |
|
|
--VD1_un1_op2_reged_1_combout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[29]
|
| 23105 |
|
|
--operation mode is normal
|
| 23106 |
|
|
|
| 23107 |
|
|
VD1_un1_op2_reged_1_combout[29] = VD1_eqop2_2_32 & VD1_op2_reged[29] # !VD1_eqop2_2_32 & VD1_nop2_reged[29];
|
| 23108 |
|
|
|
| 23109 |
|
|
|
| 23110 |
|
|
--VD1_hilo_24_add28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add28
|
| 23111 |
|
|
--operation mode is arithmetic
|
| 23112 |
|
|
|
| 23113 |
|
|
VD1_hilo_24_add28_carry_eqn = VD1_hilo_24_carry_27;
|
| 23114 |
|
|
VD1_hilo_24_add28 = VD1_hilo_59 $ VD1_un1_op2_reged_1_combout[28] $ !VD1_hilo_24_add28_carry_eqn;
|
| 23115 |
|
|
|
| 23116 |
|
|
--VD1_hilo_24_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_28
|
| 23117 |
|
|
--operation mode is arithmetic
|
| 23118 |
|
|
|
| 23119 |
|
|
VD1_hilo_24_carry_28 = CARRY(VD1_hilo_59 & VD1_un1_op2_reged_1_combout[28] # !VD1_hilo_24_carry_27 # !VD1_hilo_59 & VD1_un1_op2_reged_1_combout[28] & !VD1_hilo_24_carry_27);
|
| 23120 |
|
|
|
| 23121 |
|
|
|
| 23122 |
|
|
--VD1_un50_hilo_add29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add29
|
| 23123 |
|
|
--operation mode is arithmetic
|
| 23124 |
|
|
|
| 23125 |
|
|
VD1_un50_hilo_add29_carry_eqn = VD1_un50_hilo_carry_28;
|
| 23126 |
|
|
VD1_un50_hilo_add29 = VD1_hilo_61 $ VD1_nop2_reged[29] $ VD1_un50_hilo_add29_carry_eqn;
|
| 23127 |
|
|
|
| 23128 |
|
|
--VD1_un50_hilo_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_29
|
| 23129 |
|
|
--operation mode is arithmetic
|
| 23130 |
|
|
|
| 23131 |
|
|
VD1_un50_hilo_carry_29 = CARRY(VD1_hilo_61 & !VD1_nop2_reged[29] & !VD1_un50_hilo_carry_28 # !VD1_hilo_61 & !VD1_un50_hilo_carry_28 # !VD1_nop2_reged[29]);
|
| 23132 |
|
|
|
| 23133 |
|
|
|
| 23134 |
|
|
--VD1_nop2_reged[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[31]
|
| 23135 |
|
|
--operation mode is normal
|
| 23136 |
|
|
|
| 23137 |
|
|
VD1_nop2_reged[31]_carry_eqn = VD1_nop2_reged_cout[29];
|
| 23138 |
|
|
VD1_nop2_reged[31] = VD1_op2_reged[31] $ (VD1_op2_reged[30] # !VD1_nop2_reged[31]_carry_eqn);
|
| 23139 |
|
|
|
| 23140 |
|
|
|
| 23141 |
|
|
--VD1_un59_hilo_add29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add29
|
| 23142 |
|
|
--operation mode is arithmetic
|
| 23143 |
|
|
|
| 23144 |
|
|
VD1_un59_hilo_add29_carry_eqn = VD1_un59_hilo_carry_28;
|
| 23145 |
|
|
VD1_un59_hilo_add29 = VD1_hilo_61 $ VD1_op2_reged[29] $ VD1_un59_hilo_add29_carry_eqn;
|
| 23146 |
|
|
|
| 23147 |
|
|
--VD1_un59_hilo_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_29
|
| 23148 |
|
|
--operation mode is arithmetic
|
| 23149 |
|
|
|
| 23150 |
|
|
VD1_un59_hilo_carry_29 = CARRY(VD1_hilo_61 & !VD1_op2_reged[29] & !VD1_un59_hilo_carry_28 # !VD1_hilo_61 & !VD1_un59_hilo_carry_28 # !VD1_op2_reged[29]);
|
| 23151 |
|
|
|
| 23152 |
|
|
|
| 23153 |
|
|
--UD1_shift_out_85_c[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_c[30]
|
| 23154 |
|
|
--operation mode is normal
|
| 23155 |
|
|
|
| 23156 |
|
|
UD1_shift_out_85_c[30] = PD1_a_o_2 & PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_68[30] # !PD1_a_o_1 & VD1_b_o_iv_29;
|
| 23157 |
|
|
|
| 23158 |
|
|
|
| 23159 |
|
|
--UD1_shift_out_80_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[12]
|
| 23160 |
|
|
--operation mode is normal
|
| 23161 |
|
|
|
| 23162 |
|
|
UD1_shift_out_80_a[12] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_15 # !PD1_a_o_1 & !VD1_b_o_iv_13;
|
| 23163 |
|
|
|
| 23164 |
|
|
|
| 23165 |
|
|
--UD1_shift_out_79_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[12]
|
| 23166 |
|
|
--operation mode is normal
|
| 23167 |
|
|
|
| 23168 |
|
|
UD1_shift_out_79_a[12] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_21 # !PD1_a_o_0 & !VD1_b_o_iv_20;
|
| 23169 |
|
|
|
| 23170 |
|
|
|
| 23171 |
|
|
--VD1_un50_hilo_add13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add13
|
| 23172 |
|
|
--operation mode is arithmetic
|
| 23173 |
|
|
|
| 23174 |
|
|
VD1_un50_hilo_add13_carry_eqn = VD1_un50_hilo_carry_12;
|
| 23175 |
|
|
VD1_un50_hilo_add13 = VD1_hilo_45 $ VD1_nop2_reged[13] $ VD1_un50_hilo_add13_carry_eqn;
|
| 23176 |
|
|
|
| 23177 |
|
|
--VD1_un50_hilo_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_13
|
| 23178 |
|
|
--operation mode is arithmetic
|
| 23179 |
|
|
|
| 23180 |
|
|
VD1_un50_hilo_carry_13 = CARRY(VD1_hilo_45 & !VD1_nop2_reged[13] & !VD1_un50_hilo_carry_12 # !VD1_hilo_45 & !VD1_un50_hilo_carry_12 # !VD1_nop2_reged[13]);
|
| 23181 |
|
|
|
| 23182 |
|
|
|
| 23183 |
|
|
--VD1_hilo_24_add12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add12
|
| 23184 |
|
|
--operation mode is arithmetic
|
| 23185 |
|
|
|
| 23186 |
|
|
VD1_hilo_24_add12_carry_eqn = VD1_hilo_24_carry_11;
|
| 23187 |
|
|
VD1_hilo_24_add12 = VD1_hilo_43 $ VD1_un1_op2_reged_1_combout[12] $ !VD1_hilo_24_add12_carry_eqn;
|
| 23188 |
|
|
|
| 23189 |
|
|
--VD1_hilo_24_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_12
|
| 23190 |
|
|
--operation mode is arithmetic
|
| 23191 |
|
|
|
| 23192 |
|
|
VD1_hilo_24_carry_12 = CARRY(VD1_hilo_43 & VD1_un1_op2_reged_1_combout[12] # !VD1_hilo_24_carry_11 # !VD1_hilo_43 & VD1_un1_op2_reged_1_combout[12] & !VD1_hilo_24_carry_11);
|
| 23193 |
|
|
|
| 23194 |
|
|
|
| 23195 |
|
|
--VD1_hilo_37_iv_0_o3_0[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_0[44]
|
| 23196 |
|
|
--operation mode is normal
|
| 23197 |
|
|
|
| 23198 |
|
|
VD1_hilo_37_iv_0_o3_0[44] = VD1_hilo_37_iv_0_o3_0_a[44] # !VD1_un59_hilo_add13 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 23199 |
|
|
|
| 23200 |
|
|
|
| 23201 |
|
|
--VD1_hilo_37_iv_0_2[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[44]
|
| 23202 |
|
|
--operation mode is normal
|
| 23203 |
|
|
|
| 23204 |
|
|
VD1_hilo_37_iv_0_2[44] = VD1_hilo_37_iv_0_a2_0[38] # VD1_hilo_37_iv_0_2_a[44] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add12;
|
| 23205 |
|
|
|
| 23206 |
|
|
|
| 23207 |
|
|
--PD1_a_o_3_d[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[12]
|
| 23208 |
|
|
--operation mode is normal
|
| 23209 |
|
|
|
| 23210 |
|
|
PD1_a_o_3_d[12] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_12 # !PD1_un6_a_o & !PD1_a_o_3_d_a[12] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[12];
|
| 23211 |
|
|
|
| 23212 |
|
|
|
| 23213 |
|
|
--UD1_shift_out_80_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[24]
|
| 23214 |
|
|
--operation mode is normal
|
| 23215 |
|
|
|
| 23216 |
|
|
UD1_shift_out_80_a[24] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_27 # !PD1_a_o_1 & !VD1_b_o_iv_25;
|
| 23217 |
|
|
|
| 23218 |
|
|
|
| 23219 |
|
|
--UD1_shift_out_77[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[24]
|
| 23220 |
|
|
--operation mode is normal
|
| 23221 |
|
|
|
| 23222 |
|
|
UD1_shift_out_77[24] = PD1_a_o_2 & UD1_shift_out_85_d[16] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[16] # !PD1_a_o_1 & !UD1_shift_out_77_a[24];
|
| 23223 |
|
|
|
| 23224 |
|
|
|
| 23225 |
|
|
--VD1_hilo_37_iv_0[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[24]
|
| 23226 |
|
|
--operation mode is normal
|
| 23227 |
|
|
|
| 23228 |
|
|
VD1_hilo_37_iv_0[24] = VD1_hilo_25 & VD1_hilo_1_sqmuxa_1 # VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[24] # !VD1_hilo_25 & VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[24];
|
| 23229 |
|
|
|
| 23230 |
|
|
|
| 23231 |
|
|
--VD1_hilo_33_i_m[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[56]
|
| 23232 |
|
|
--operation mode is normal
|
| 23233 |
|
|
|
| 23234 |
|
|
VD1_hilo_33_i_m[56] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[56] # !VD1_hilo_33_1[64] & !VD1_hilo_56;
|
| 23235 |
|
|
|
| 23236 |
|
|
|
| 23237 |
|
|
--VD1_hilo_37_iv_2_a[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[56]
|
| 23238 |
|
|
--operation mode is normal
|
| 23239 |
|
|
|
| 23240 |
|
|
VD1_hilo_37_iv_2_a[56] = VD1_hilo_24 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add24 # !VD1_hilo_24 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add24;
|
| 23241 |
|
|
|
| 23242 |
|
|
|
| 23243 |
|
|
--VD1_hilo_22_Z[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[56]
|
| 23244 |
|
|
--operation mode is normal
|
| 23245 |
|
|
|
| 23246 |
|
|
VD1_hilo_22_Z[56] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[56] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[56] # !VD1_sign & !VD1_hilo_22_a[56];
|
| 23247 |
|
|
|
| 23248 |
|
|
|
| 23249 |
|
|
--RD1_r32_o_0_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_24
|
| 23250 |
|
|
--operation mode is arithmetic
|
| 23251 |
|
|
|
| 23252 |
|
|
RD1_r32_o_0_24_carry_eqn = RD1_r32_o_cout[22];
|
| 23253 |
|
|
RD1_r32_o_0_24_lut_out = KB1_r32_o_24 $ (RD1_r32_o_0_24_carry_eqn);
|
| 23254 |
|
|
RD1_r32_o_0_24 = DFFEAS(RD1_r32_o_0_24_lut_out, E1__clk0, VCC, , , , , , );
|
| 23255 |
|
|
|
| 23256 |
|
|
--RD1_r32_o_cout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[24]
|
| 23257 |
|
|
--operation mode is arithmetic
|
| 23258 |
|
|
|
| 23259 |
|
|
RD1_r32_o_cout[24] = CARRY(!RD1_r32_o_cout[22] # !KB1_r32_o_25 # !KB1_r32_o_24);
|
| 23260 |
|
|
|
| 23261 |
|
|
|
| 23262 |
|
|
--SD1_r32_o_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_24
|
| 23263 |
|
|
--operation mode is normal
|
| 23264 |
|
|
|
| 23265 |
|
|
SD1_r32_o_24_lut_out = KB1_r32_o_24;
|
| 23266 |
|
|
SD1_r32_o_24 = DFFEAS(SD1_r32_o_24_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 23267 |
|
|
|
| 23268 |
|
|
|
| 23269 |
|
|
--PD1_a_o_3_d[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[24]
|
| 23270 |
|
|
--operation mode is normal
|
| 23271 |
|
|
|
| 23272 |
|
|
PD1_a_o_3_d[24] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_24 # !PD1_un6_a_o & !PD1_a_o_3_d_a[24] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[24];
|
| 23273 |
|
|
|
| 23274 |
|
|
|
| 23275 |
|
|
--UD1_shift_out_80_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[25]
|
| 23276 |
|
|
--operation mode is normal
|
| 23277 |
|
|
|
| 23278 |
|
|
UD1_shift_out_80_a[25] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_28 # !PD1_a_o_1 & !VD1_b_o_iv_26;
|
| 23279 |
|
|
|
| 23280 |
|
|
|
| 23281 |
|
|
--UD1_shift_out_75_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75_a[25]
|
| 23282 |
|
|
--operation mode is normal
|
| 23283 |
|
|
|
| 23284 |
|
|
UD1_shift_out_75_a[25] = PD1_a_o_3 & !UD1_shift_out_63[17] # !PD1_a_o_3 & !UD1_shift_out_48[29];
|
| 23285 |
|
|
|
| 23286 |
|
|
|
| 23287 |
|
|
--VD1_un134_hilo_combout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[25]
|
| 23288 |
|
|
--operation mode is arithmetic
|
| 23289 |
|
|
|
| 23290 |
|
|
VD1_un134_hilo_combout[25]_carry_eqn = VD1_un134_hilo_cout[23];
|
| 23291 |
|
|
VD1_un134_hilo_combout[25] = VD1_hilo_25 $ (VD1_hilo_24 & !VD1_un134_hilo_combout[25]_carry_eqn);
|
| 23292 |
|
|
|
| 23293 |
|
|
--VD1_un134_hilo_cout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[25]
|
| 23294 |
|
|
--operation mode is arithmetic
|
| 23295 |
|
|
|
| 23296 |
|
|
VD1_un134_hilo_cout[25] = CARRY(VD1_hilo_24 & VD1_hilo_25 & !VD1_un134_hilo_cout[23]);
|
| 23297 |
|
|
|
| 23298 |
|
|
|
| 23299 |
|
|
--VD1_hilo_37_iv_0_5[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[57]
|
| 23300 |
|
|
--operation mode is normal
|
| 23301 |
|
|
|
| 23302 |
|
|
VD1_hilo_37_iv_0_5[57] = VD1_hilo_37_iv_0_2[57] # VD1_hilo_37_iv_0_5_a[57] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add25;
|
| 23303 |
|
|
|
| 23304 |
|
|
|
| 23305 |
|
|
--VD1_hilo_37_iv_0_8_a[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_8_a[57]
|
| 23306 |
|
|
--operation mode is normal
|
| 23307 |
|
|
|
| 23308 |
|
|
VD1_hilo_37_iv_0_8_a[57] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add26 # !VD1_hilo_24_add25 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add26;
|
| 23309 |
|
|
|
| 23310 |
|
|
|
| 23311 |
|
|
--RD1_r32_o_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_25
|
| 23312 |
|
|
--operation mode is arithmetic
|
| 23313 |
|
|
|
| 23314 |
|
|
RD1_r32_o_25_carry_eqn = RD1_r32_o_cout[23];
|
| 23315 |
|
|
RD1_r32_o_25_lut_out = KB1_r32_o_25 $ (KB1_r32_o_24 & RD1_r32_o_25_carry_eqn);
|
| 23316 |
|
|
RD1_r32_o_25 = DFFEAS(RD1_r32_o_25_lut_out, E1__clk0, VCC, , , , , , );
|
| 23317 |
|
|
|
| 23318 |
|
|
--RD1_r32_o_cout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[25]
|
| 23319 |
|
|
--operation mode is arithmetic
|
| 23320 |
|
|
|
| 23321 |
|
|
RD1_r32_o_cout[25] = CARRY(!RD1_r32_o_cout[23] # !KB1_r32_o_25 # !KB1_r32_o_24);
|
| 23322 |
|
|
|
| 23323 |
|
|
|
| 23324 |
|
|
--SD1_r32_o_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_25
|
| 23325 |
|
|
--operation mode is normal
|
| 23326 |
|
|
|
| 23327 |
|
|
SD1_r32_o_25_lut_out = KB1_r32_o_25;
|
| 23328 |
|
|
SD1_r32_o_25 = DFFEAS(SD1_r32_o_25_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 23329 |
|
|
|
| 23330 |
|
|
|
| 23331 |
|
|
--PD1_a_o_3_d[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[25]
|
| 23332 |
|
|
--operation mode is normal
|
| 23333 |
|
|
|
| 23334 |
|
|
PD1_a_o_3_d[25] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_25 # !PD1_un6_a_o & !PD1_a_o_3_d_a[25] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[25];
|
| 23335 |
|
|
|
| 23336 |
|
|
|
| 23337 |
|
|
--UD1_shift_out_80_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[22]
|
| 23338 |
|
|
--operation mode is normal
|
| 23339 |
|
|
|
| 23340 |
|
|
UD1_shift_out_80_a[22] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_25 # !PD1_a_o_1 & !VD1_b_o_iv_23;
|
| 23341 |
|
|
|
| 23342 |
|
|
|
| 23343 |
|
|
--UD1_shift_out_54_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54_a[30]
|
| 23344 |
|
|
--operation mode is normal
|
| 23345 |
|
|
|
| 23346 |
|
|
UD1_shift_out_54_a[30] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_15 # !PD1_a_o_0 & !VD1_b_o_iv_16 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 23347 |
|
|
|
| 23348 |
|
|
|
| 23349 |
|
|
--UD1_shift_out_79_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[22]
|
| 23350 |
|
|
--operation mode is normal
|
| 23351 |
|
|
|
| 23352 |
|
|
UD1_shift_out_79_a[22] = PD1_a_o_0 & !VD1_b_o_iv_31 # !PD1_a_o_0 & !VD1_b_o_iv_30;
|
| 23353 |
|
|
|
| 23354 |
|
|
|
| 23355 |
|
|
--VD1_un134_hilo_combout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[22]
|
| 23356 |
|
|
--operation mode is arithmetic
|
| 23357 |
|
|
|
| 23358 |
|
|
VD1_un134_hilo_combout[22]_carry_eqn = VD1_un134_hilo_cout[20];
|
| 23359 |
|
|
VD1_un134_hilo_combout[22] = VD1_hilo_22 $ (VD1_un134_hilo_combout[22]_carry_eqn);
|
| 23360 |
|
|
|
| 23361 |
|
|
--VD1_un134_hilo_cout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[22]
|
| 23362 |
|
|
--operation mode is arithmetic
|
| 23363 |
|
|
|
| 23364 |
|
|
VD1_un134_hilo_cout[22] = CARRY(!VD1_un134_hilo_cout[20] # !VD1_hilo_23 # !VD1_hilo_22);
|
| 23365 |
|
|
|
| 23366 |
|
|
|
| 23367 |
|
|
--VD1_hilo_37_iv_0_o5_0_0[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5_0_0[54]
|
| 23368 |
|
|
--operation mode is normal
|
| 23369 |
|
|
|
| 23370 |
|
|
VD1_hilo_37_iv_0_o5_0_0[54] = VD1_hilo_55 & !VD1_un59_hilo_add23 & VD1_hilo_37_iv_0_a6_1_0[40] # !VD1_hilo_55 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_un59_hilo_add23 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 23371 |
|
|
|
| 23372 |
|
|
|
| 23373 |
|
|
--VD1_hilo_37_iv_0_0[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[54]
|
| 23374 |
|
|
--operation mode is normal
|
| 23375 |
|
|
|
| 23376 |
|
|
VD1_hilo_37_iv_0_0[54] = VD1_hilo_22 & !VD1_un59_hilo_add22 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_hilo_22 & VD1_hilo_0_sqmuxa # !VD1_un59_hilo_add22 & VD1_hilo_37_iv_0_a3_2[62];
|
| 23377 |
|
|
|
| 23378 |
|
|
|
| 23379 |
|
|
--VD1_hilo_24_add22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add22
|
| 23380 |
|
|
--operation mode is arithmetic
|
| 23381 |
|
|
|
| 23382 |
|
|
VD1_hilo_24_add22_carry_eqn = VD1_hilo_24_carry_21;
|
| 23383 |
|
|
VD1_hilo_24_add22 = VD1_hilo_53 $ VD1_un1_op2_reged_1_combout[22] $ !VD1_hilo_24_add22_carry_eqn;
|
| 23384 |
|
|
|
| 23385 |
|
|
--VD1_hilo_24_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_22
|
| 23386 |
|
|
--operation mode is arithmetic
|
| 23387 |
|
|
|
| 23388 |
|
|
VD1_hilo_24_carry_22 = CARRY(VD1_hilo_53 & VD1_un1_op2_reged_1_combout[22] # !VD1_hilo_24_carry_21 # !VD1_hilo_53 & VD1_un1_op2_reged_1_combout[22] & !VD1_hilo_24_carry_21);
|
| 23389 |
|
|
|
| 23390 |
|
|
|
| 23391 |
|
|
--VD1_hilo_37_iv_0_3_a[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3_a[54]
|
| 23392 |
|
|
--operation mode is normal
|
| 23393 |
|
|
|
| 23394 |
|
|
VD1_hilo_37_iv_0_3_a[54] = VD1_hilo_54 & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add22 # !VD1_hilo_54 & VD1_hilo_37_iv_0_a3_1[62] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add22;
|
| 23395 |
|
|
|
| 23396 |
|
|
|
| 23397 |
|
|
--VD1_un50_hilo_add23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add23
|
| 23398 |
|
|
--operation mode is arithmetic
|
| 23399 |
|
|
|
| 23400 |
|
|
VD1_un50_hilo_add23_carry_eqn = VD1_un50_hilo_carry_22;
|
| 23401 |
|
|
VD1_un50_hilo_add23 = VD1_hilo_55 $ VD1_nop2_reged[23] $ VD1_un50_hilo_add23_carry_eqn;
|
| 23402 |
|
|
|
| 23403 |
|
|
--VD1_un50_hilo_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_23
|
| 23404 |
|
|
--operation mode is arithmetic
|
| 23405 |
|
|
|
| 23406 |
|
|
VD1_un50_hilo_carry_23 = CARRY(VD1_hilo_55 & !VD1_nop2_reged[23] & !VD1_un50_hilo_carry_22 # !VD1_hilo_55 & !VD1_un50_hilo_carry_22 # !VD1_nop2_reged[23]);
|
| 23407 |
|
|
|
| 23408 |
|
|
|
| 23409 |
|
|
--RD1_r32_o_0_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_22
|
| 23410 |
|
|
--operation mode is arithmetic
|
| 23411 |
|
|
|
| 23412 |
|
|
RD1_r32_o_0_22_carry_eqn = RD1_r32_o_cout[20];
|
| 23413 |
|
|
RD1_r32_o_0_22_lut_out = KB1_r32_o_22 $ (!RD1_r32_o_0_22_carry_eqn);
|
| 23414 |
|
|
RD1_r32_o_0_22 = DFFEAS(RD1_r32_o_0_22_lut_out, E1__clk0, VCC, , , , , , );
|
| 23415 |
|
|
|
| 23416 |
|
|
--RD1_r32_o_cout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[22]
|
| 23417 |
|
|
--operation mode is arithmetic
|
| 23418 |
|
|
|
| 23419 |
|
|
RD1_r32_o_cout[22] = CARRY(KB1_r32_o_22 & KB1_r32_o_23 & !RD1_r32_o_cout[20]);
|
| 23420 |
|
|
|
| 23421 |
|
|
|
| 23422 |
|
|
--SD1_r32_o_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_22
|
| 23423 |
|
|
--operation mode is normal
|
| 23424 |
|
|
|
| 23425 |
|
|
SD1_r32_o_22_lut_out = KB1_r32_o_22;
|
| 23426 |
|
|
SD1_r32_o_22 = DFFEAS(SD1_r32_o_22_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 23427 |
|
|
|
| 23428 |
|
|
|
| 23429 |
|
|
--PD1_a_o_3_d[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[22]
|
| 23430 |
|
|
--operation mode is normal
|
| 23431 |
|
|
|
| 23432 |
|
|
PD1_a_o_3_d[22] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_22 # !PD1_un6_a_o & !PD1_a_o_3_d_a[22] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[22];
|
| 23433 |
|
|
|
| 23434 |
|
|
|
| 23435 |
|
|
--UD1_shift_out_80_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[23]
|
| 23436 |
|
|
--operation mode is normal
|
| 23437 |
|
|
|
| 23438 |
|
|
UD1_shift_out_80_a[23] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_26 # !PD1_a_o_1 & !VD1_b_o_iv_24;
|
| 23439 |
|
|
|
| 23440 |
|
|
|
| 23441 |
|
|
--UD1_shift_out_54_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54_a[31]
|
| 23442 |
|
|
--operation mode is normal
|
| 23443 |
|
|
|
| 23444 |
|
|
UD1_shift_out_54_a[31] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_16 # !PD1_a_o_0 & !VD1_b_o_iv_17 # !PD1_a_o_1 & !PD1_a_o_0;
|
| 23445 |
|
|
|
| 23446 |
|
|
|
| 23447 |
|
|
--VD1_hilo_37_iv_0_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[23]
|
| 23448 |
|
|
--operation mode is normal
|
| 23449 |
|
|
|
| 23450 |
|
|
VD1_hilo_37_iv_0_a[23] = VD1_add1 & !VD1_un134_hilo_combout[23] # !VD1_add1 & !VD1_hilo_23;
|
| 23451 |
|
|
|
| 23452 |
|
|
|
| 23453 |
|
|
--VD1_hilo_33_i_m[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[55]
|
| 23454 |
|
|
--operation mode is normal
|
| 23455 |
|
|
|
| 23456 |
|
|
VD1_hilo_33_i_m[55] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[55] # !VD1_hilo_33_1[64] & !VD1_hilo_55;
|
| 23457 |
|
|
|
| 23458 |
|
|
|
| 23459 |
|
|
--VD1_hilo_37_iv_2_a[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[55]
|
| 23460 |
|
|
--operation mode is normal
|
| 23461 |
|
|
|
| 23462 |
|
|
VD1_hilo_37_iv_2_a[55] = VD1_hilo_23 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add23 # !VD1_hilo_23 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add23;
|
| 23463 |
|
|
|
| 23464 |
|
|
|
| 23465 |
|
|
--VD1_hilo_22_Z[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[55]
|
| 23466 |
|
|
--operation mode is normal
|
| 23467 |
|
|
|
| 23468 |
|
|
VD1_hilo_22_Z[55] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[55] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[55] # !VD1_sign & !VD1_hilo_22_a[55];
|
| 23469 |
|
|
|
| 23470 |
|
|
|
| 23471 |
|
|
--RD1_r32_o_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_23
|
| 23472 |
|
|
--operation mode is arithmetic
|
| 23473 |
|
|
|
| 23474 |
|
|
RD1_r32_o_23_carry_eqn = RD1_r32_o_cout[21];
|
| 23475 |
|
|
RD1_r32_o_23_lut_out = KB1_r32_o_23 $ (KB1_r32_o_22 & !RD1_r32_o_23_carry_eqn);
|
| 23476 |
|
|
RD1_r32_o_23 = DFFEAS(RD1_r32_o_23_lut_out, E1__clk0, VCC, , , , , , );
|
| 23477 |
|
|
|
| 23478 |
|
|
--RD1_r32_o_cout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[23]
|
| 23479 |
|
|
--operation mode is arithmetic
|
| 23480 |
|
|
|
| 23481 |
|
|
RD1_r32_o_cout[23] = CARRY(KB1_r32_o_22 & KB1_r32_o_23 & !RD1_r32_o_cout[21]);
|
| 23482 |
|
|
|
| 23483 |
|
|
|
| 23484 |
|
|
--SD1_r32_o_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_23
|
| 23485 |
|
|
--operation mode is normal
|
| 23486 |
|
|
|
| 23487 |
|
|
SD1_r32_o_23_lut_out = KB1_r32_o_23;
|
| 23488 |
|
|
SD1_r32_o_23 = DFFEAS(SD1_r32_o_23_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 23489 |
|
|
|
| 23490 |
|
|
|
| 23491 |
|
|
--PD1_a_o_3_d[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[23]
|
| 23492 |
|
|
--operation mode is normal
|
| 23493 |
|
|
|
| 23494 |
|
|
PD1_a_o_3_d[23] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_23 # !PD1_un6_a_o & !PD1_a_o_3_d_a[23] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[23];
|
| 23495 |
|
|
|
| 23496 |
|
|
|
| 23497 |
|
|
--F1_cmd[22] is mips_sys:isys|mips_dvc:imips_dvc|cmd[22]
|
| 23498 |
|
|
--operation mode is normal
|
| 23499 |
|
|
|
| 23500 |
|
|
F1_cmd[22]_lut_out = CB1_r32_o_22;
|
| 23501 |
|
|
F1_cmd[22] = DFFEAS(F1_cmd[22]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23502 |
|
|
|
| 23503 |
|
|
|
| 23504 |
|
|
--F1_cmd[21] is mips_sys:isys|mips_dvc:imips_dvc|cmd[21]
|
| 23505 |
|
|
--operation mode is normal
|
| 23506 |
|
|
|
| 23507 |
|
|
F1_cmd[21]_lut_out = CB1_r32_o_21;
|
| 23508 |
|
|
F1_cmd[21] = DFFEAS(F1_cmd[21]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23509 |
|
|
|
| 23510 |
|
|
|
| 23511 |
|
|
--F1_cmd[19] is mips_sys:isys|mips_dvc:imips_dvc|cmd[19]
|
| 23512 |
|
|
--operation mode is normal
|
| 23513 |
|
|
|
| 23514 |
|
|
F1_cmd[19]_lut_out = CB1_r32_o_19;
|
| 23515 |
|
|
F1_cmd[19] = DFFEAS(F1_cmd[19]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23516 |
|
|
|
| 23517 |
|
|
|
| 23518 |
|
|
--F1_cmd[18] is mips_sys:isys|mips_dvc:imips_dvc|cmd[18]
|
| 23519 |
|
|
--operation mode is normal
|
| 23520 |
|
|
|
| 23521 |
|
|
F1_cmd[18]_lut_out = CB1_r32_o_18;
|
| 23522 |
|
|
F1_cmd[18] = DFFEAS(F1_cmd[18]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23523 |
|
|
|
| 23524 |
|
|
|
| 23525 |
|
|
--F1_cmd[17] is mips_sys:isys|mips_dvc:imips_dvc|cmd[17]
|
| 23526 |
|
|
--operation mode is normal
|
| 23527 |
|
|
|
| 23528 |
|
|
F1_cmd[17]_lut_out = CB1_r32_o_17;
|
| 23529 |
|
|
F1_cmd[17] = DFFEAS(F1_cmd[17]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23530 |
|
|
|
| 23531 |
|
|
|
| 23532 |
|
|
--F1_cmd[16] is mips_sys:isys|mips_dvc:imips_dvc|cmd[16]
|
| 23533 |
|
|
--operation mode is normal
|
| 23534 |
|
|
|
| 23535 |
|
|
F1_cmd[16]_lut_out = CB1_r32_o_16;
|
| 23536 |
|
|
F1_cmd[16] = DFFEAS(F1_cmd[16]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23537 |
|
|
|
| 23538 |
|
|
|
| 23539 |
|
|
--VD1_hilo_22_a[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[32]
|
| 23540 |
|
|
--operation mode is normal
|
| 23541 |
|
|
|
| 23542 |
|
|
VD1_hilo_22_a[32] = VD1_sign & !VD1_hilo_33 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add1 # !VD1_hilo[0] & !VD1_hilo_33;
|
| 23543 |
|
|
|
| 23544 |
|
|
|
| 23545 |
|
|
--VD1_hilo_15_2[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[32]
|
| 23546 |
|
|
--operation mode is normal
|
| 23547 |
|
|
|
| 23548 |
|
|
VD1_hilo_15_2[32] = VD1_sub_or_yn & VD1_un59_hilo_add1 # !VD1_sub_or_yn & VD1_un50_hilo_add1;
|
| 23549 |
|
|
|
| 23550 |
|
|
|
| 23551 |
|
|
--VD1_un1_op2_reged_1_combout[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[31]
|
| 23552 |
|
|
--operation mode is normal
|
| 23553 |
|
|
|
| 23554 |
|
|
VD1_un1_op2_reged_1_combout[31] = VD1_eqop2_2_32 & VD1_op2_reged[31] # !VD1_eqop2_2_32 & VD1_nop2_reged[31];
|
| 23555 |
|
|
|
| 23556 |
|
|
|
| 23557 |
|
|
--DD1_pc_next_0_iv_1_a[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[30]
|
| 23558 |
|
|
--operation mode is normal
|
| 23559 |
|
|
|
| 23560 |
|
|
DD1_pc_next_0_iv_1_a[30] = KB1_r32_o_30 & !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_30 # !KB1_r32_o_30 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_30;
|
| 23561 |
|
|
|
| 23562 |
|
|
|
| 23563 |
|
|
--DD1_un1_pc_prectl_1_0_a4[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[30]
|
| 23564 |
|
|
--operation mode is normal
|
| 23565 |
|
|
|
| 23566 |
|
|
DD1_un1_pc_prectl_1_0_a4[30] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_a3_0 # ED1_r32_o_14 & CD1_res_7_0_0_a2_16;
|
| 23567 |
|
|
|
| 23568 |
|
|
|
| 23569 |
|
|
--DD1_un1_pc_add29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add29
|
| 23570 |
|
|
--operation mode is arithmetic
|
| 23571 |
|
|
|
| 23572 |
|
|
DD1_un1_pc_add29_carry_eqn = DD1_un1_pc_carry_28;
|
| 23573 |
|
|
DD1_un1_pc_add29 = KB1_r32_o_29 $ DD1_un1_pc_prectl_1_0_a4[29] $ DD1_un1_pc_add29_carry_eqn;
|
| 23574 |
|
|
|
| 23575 |
|
|
--DD1_un1_pc_carry_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_29
|
| 23576 |
|
|
--operation mode is arithmetic
|
| 23577 |
|
|
|
| 23578 |
|
|
DD1_un1_pc_carry_29 = CARRY(KB1_r32_o_29 & !DD1_un1_pc_prectl_1_0_a4[29] & !DD1_un1_pc_carry_28 # !KB1_r32_o_29 & !DD1_un1_pc_carry_28 # !DD1_un1_pc_prectl_1_0_a4[29]);
|
| 23579 |
|
|
|
| 23580 |
|
|
|
| 23581 |
|
|
--DD1_un1_pc_prectl_1_0_a4[31] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[31]
|
| 23582 |
|
|
--operation mode is normal
|
| 23583 |
|
|
|
| 23584 |
|
|
DD1_un1_pc_prectl_1_0_a4[31] = FB1_res_7_0_0_31 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 23585 |
|
|
|
| 23586 |
|
|
|
| 23587 |
|
|
--DD1_pc_next_0_iv_1_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_28
|
| 23588 |
|
|
--operation mode is normal
|
| 23589 |
|
|
|
| 23590 |
|
|
DD1_pc_next_0_iv_1_28 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_28 # !DD1_pc_next_0_iv_1_a[28];
|
| 23591 |
|
|
|
| 23592 |
|
|
|
| 23593 |
|
|
--DD1_un1_pc_add28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add28
|
| 23594 |
|
|
--operation mode is arithmetic
|
| 23595 |
|
|
|
| 23596 |
|
|
DD1_un1_pc_add28_carry_eqn = DD1_un1_pc_carry_27;
|
| 23597 |
|
|
DD1_un1_pc_add28 = KB1_r32_o_28 $ DD1_un1_pc_prectl_1_0_a4[28] $ !DD1_un1_pc_add28_carry_eqn;
|
| 23598 |
|
|
|
| 23599 |
|
|
--DD1_un1_pc_carry_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_28
|
| 23600 |
|
|
--operation mode is arithmetic
|
| 23601 |
|
|
|
| 23602 |
|
|
DD1_un1_pc_carry_28 = CARRY(KB1_r32_o_28 & DD1_un1_pc_prectl_1_0_a4[28] # !DD1_un1_pc_carry_27 # !KB1_r32_o_28 & DD1_un1_pc_prectl_1_0_a4[28] & !DD1_un1_pc_carry_27);
|
| 23603 |
|
|
|
| 23604 |
|
|
|
| 23605 |
|
|
--DD1_pc_next_0_iv_1_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_29
|
| 23606 |
|
|
--operation mode is normal
|
| 23607 |
|
|
|
| 23608 |
|
|
DD1_pc_next_0_iv_1_29 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_29 # !DD1_pc_next_0_iv_1_a[29];
|
| 23609 |
|
|
|
| 23610 |
|
|
|
| 23611 |
|
|
--KB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_26
|
| 23612 |
|
|
--operation mode is normal
|
| 23613 |
|
|
|
| 23614 |
|
|
KB1_r32_o_26_lut_out = DD1_pc_next_0_iv_1_26 # DD1_un1_pc_next46_0 & DD1_un1_pc_add26;
|
| 23615 |
|
|
KB1_r32_o_26 = DFFEAS(KB1_r32_o_26_lut_out, E1__clk0, VCC, , , , , , );
|
| 23616 |
|
|
|
| 23617 |
|
|
|
| 23618 |
|
|
--KB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_27
|
| 23619 |
|
|
--operation mode is normal
|
| 23620 |
|
|
|
| 23621 |
|
|
KB1_r32_o_27_lut_out = DD1_pc_next_0_iv_1_27 # DD1_un1_pc_next46_0 & DD1_un1_pc_add27;
|
| 23622 |
|
|
KB1_r32_o_27 = DFFEAS(KB1_r32_o_27_lut_out, E1__clk0, VCC, , , , , , );
|
| 23623 |
|
|
|
| 23624 |
|
|
|
| 23625 |
|
|
--HD1_dout_iv_a_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_a_0
|
| 23626 |
|
|
--operation mode is normal
|
| 23627 |
|
|
|
| 23628 |
|
|
HD1_dout_iv_a_0 = FD1_r_data_31 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_29 # !FD1_r_data_31 & !YD1_mux_fw_1 # !AB1_r32_o_29;
|
| 23629 |
|
|
|
| 23630 |
|
|
|
| 23631 |
|
|
--FD1_reg_bank_m_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|reg_bank_m_0
|
| 23632 |
|
|
--operation mode is normal
|
| 23633 |
|
|
|
| 23634 |
|
|
FD1_reg_bank_m_0 = FD1_N_18_i_0_s3 & LD2_q_b[31];
|
| 23635 |
|
|
|
| 23636 |
|
|
|
| 23637 |
|
|
--UB1_dout_2_i_i_x[31] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[31]
|
| 23638 |
|
|
--operation mode is normal
|
| 23639 |
|
|
|
| 23640 |
|
|
UB1_dout_2_i_i_x[31] = UB1_dout_2_i_i_a2[16] # KE1_q_b[7] & UB1_dout_2_i_i_a3_0[16];
|
| 23641 |
|
|
|
| 23642 |
|
|
|
| 23643 |
|
|
--UB1_un1_ctl_6_2_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_ctl_6_2_0
|
| 23644 |
|
|
--operation mode is normal
|
| 23645 |
|
|
|
| 23646 |
|
|
UB1_un1_ctl_6_2_0 = RB1_byte_addr_o_0 & UB1_un1_ctl_5 # !RB1_byte_addr_o_0 & RB1_ctl_o_0 # !UB1_un1_ctl_6_2_0_a;
|
| 23647 |
|
|
|
| 23648 |
|
|
|
| 23649 |
|
|
--WB63L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_31__Z|lpm_latch:U1|q[0]~56
|
| 23650 |
|
|
--operation mode is normal
|
| 23651 |
|
|
|
| 23652 |
|
|
WB63L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[31] # !UB1_un1_byte_addr_2 & WB63L1;
|
| 23653 |
|
|
|
| 23654 |
|
|
|
| 23655 |
|
|
--GD1_dout_iv_1_a[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[30]
|
| 23656 |
|
|
--operation mode is normal
|
| 23657 |
|
|
|
| 23658 |
|
|
GD1_dout_iv_1_a[30] = FD1_r_data_30 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_28 # !FD1_r_data_30 & !ZD1_mux_fw_1 # !AB1_r32_o_28;
|
| 23659 |
|
|
|
| 23660 |
|
|
|
| 23661 |
|
|
--LD1_q_b[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[30]
|
| 23662 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 23663 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 23664 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 23665 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 23666 |
|
|
LD1_q_b[30]_PORT_A_data_in = FD1_wb_o_30;
|
| 23667 |
|
|
LD1_q_b[30]_PORT_A_data_in_reg = DFFE(LD1_q_b[30]_PORT_A_data_in, LD1_q_b[30]_clock_0, , , );
|
| 23668 |
|
|
LD1_q_b[30]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 23669 |
|
|
LD1_q_b[30]_PORT_A_address_reg = DFFE(LD1_q_b[30]_PORT_A_address, LD1_q_b[30]_clock_0, , , );
|
| 23670 |
|
|
LD1_q_b[30]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 23671 |
|
|
LD1_q_b[30]_PORT_B_address_reg = DFFE(LD1_q_b[30]_PORT_B_address, LD1_q_b[30]_clock_1, , , );
|
| 23672 |
|
|
LD1_q_b[30]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 23673 |
|
|
LD1_q_b[30]_PORT_A_write_enable_reg = DFFE(LD1_q_b[30]_PORT_A_write_enable, LD1_q_b[30]_clock_0, , , );
|
| 23674 |
|
|
LD1_q_b[30]_PORT_B_read_enable = VCC;
|
| 23675 |
|
|
LD1_q_b[30]_PORT_B_read_enable_reg = DFFE(LD1_q_b[30]_PORT_B_read_enable, LD1_q_b[30]_clock_1, , , );
|
| 23676 |
|
|
LD1_q_b[30]_clock_0 = E1__clk0;
|
| 23677 |
|
|
LD1_q_b[30]_clock_1 = E1__clk0;
|
| 23678 |
|
|
LD1_q_b[30]_PORT_B_data_out = MEMORY(LD1_q_b[30]_PORT_A_data_in_reg, , LD1_q_b[30]_PORT_A_address_reg, LD1_q_b[30]_PORT_B_address_reg, LD1_q_b[30]_PORT_A_write_enable_reg, LD1_q_b[30]_PORT_B_read_enable_reg, , , LD1_q_b[30]_clock_0, LD1_q_b[30]_clock_1, , , , );
|
| 23679 |
|
|
LD1_q_b[30] = LD1_q_b[30]_PORT_B_data_out[0];
|
| 23680 |
|
|
|
| 23681 |
|
|
|
| 23682 |
|
|
--F1_cmd[30] is mips_sys:isys|mips_dvc:imips_dvc|cmd[30]
|
| 23683 |
|
|
--operation mode is normal
|
| 23684 |
|
|
|
| 23685 |
|
|
F1_cmd[30]_lut_out = CB1_r32_o_30;
|
| 23686 |
|
|
F1_cmd[30] = DFFEAS(F1_cmd[30]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23687 |
|
|
|
| 23688 |
|
|
|
| 23689 |
|
|
--PD1_a_o_3_d_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[29]
|
| 23690 |
|
|
--operation mode is normal
|
| 23691 |
|
|
|
| 23692 |
|
|
PD1_a_o_3_d_a[29] = PD1_a_o_sn_m2 & !PB1_r32_o_29 # !PD1_a_o_sn_m2 & !AB1_r32_o_27;
|
| 23693 |
|
|
|
| 23694 |
|
|
|
| 23695 |
|
|
--TD1_lt_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_25
|
| 23696 |
|
|
--operation mode is arithmetic
|
| 23697 |
|
|
|
| 23698 |
|
|
TD1_lt_25 = CARRY(PD1_a_o_25 & !TD1_lt_24 # !VD1_b_o_iv_25 # !PD1_a_o_25 & !VD1_b_o_iv_25 & !TD1_lt_24);
|
| 23699 |
|
|
|
| 23700 |
|
|
|
| 23701 |
|
|
--TD1_sum_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_26
|
| 23702 |
|
|
--operation mode is arithmetic
|
| 23703 |
|
|
|
| 23704 |
|
|
TD1_sum_carry_26 = CARRY(VD1_b_o_iv_26 & PD1_a_o_26 & !TD1_sum_carry_25 # !VD1_b_o_iv_26 & PD1_a_o_26 # !TD1_sum_carry_25);
|
| 23705 |
|
|
|
| 23706 |
|
|
|
| 23707 |
|
|
--F1_cmd[28] is mips_sys:isys|mips_dvc:imips_dvc|cmd[28]
|
| 23708 |
|
|
--operation mode is normal
|
| 23709 |
|
|
|
| 23710 |
|
|
F1_cmd[28]_lut_out = CB1_r32_o_28;
|
| 23711 |
|
|
F1_cmd[28] = DFFEAS(F1_cmd[28]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23712 |
|
|
|
| 23713 |
|
|
|
| 23714 |
|
|
--F1_cmd[29] is mips_sys:isys|mips_dvc:imips_dvc|cmd[29]
|
| 23715 |
|
|
--operation mode is normal
|
| 23716 |
|
|
|
| 23717 |
|
|
F1_cmd[29]_lut_out = CB1_r32_o_29;
|
| 23718 |
|
|
F1_cmd[29] = DFFEAS(F1_cmd[29]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23719 |
|
|
|
| 23720 |
|
|
|
| 23721 |
|
|
--UB1_dout_2_0_0_o2_0[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_o2_0[9]
|
| 23722 |
|
|
--operation mode is normal
|
| 23723 |
|
|
|
| 23724 |
|
|
UB1_dout_2_0_0_o2_0[9] = !RB1_byte_addr_o_1 & !RB1_byte_addr_o_0 & !UB1_dout_2_0_0_o2_0_a[9];
|
| 23725 |
|
|
|
| 23726 |
|
|
|
| 23727 |
|
|
--UB1_dout_2_i_i_a_x[8] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a_x[8]
|
| 23728 |
|
|
--operation mode is normal
|
| 23729 |
|
|
|
| 23730 |
|
|
UB1_dout_2_i_i_a_x[8] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[0];
|
| 23731 |
|
|
|
| 23732 |
|
|
|
| 23733 |
|
|
--UB1_dout_2_0_0_a2_1[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a2_1[9]
|
| 23734 |
|
|
--operation mode is normal
|
| 23735 |
|
|
|
| 23736 |
|
|
UB1_dout_2_0_0_a2_1[9] = !RB1_ctl_o_2 & UB1_dout_2_i_i_a3[15] # UB1_dout_2_0_0_a2_1_a[9] & UB1_dout_2_i_i_a3_1[15];
|
| 23737 |
|
|
|
| 23738 |
|
|
|
| 23739 |
|
|
--M1_clk_ctr27_i_0_a5_5_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_0_a5_5_a
|
| 23740 |
|
|
--operation mode is normal
|
| 23741 |
|
|
|
| 23742 |
|
|
M1_clk_ctr27_i_0_a5_5_a = M1_clk_ctr[11] & !M1_clk_ctr[10];
|
| 23743 |
|
|
|
| 23744 |
|
|
|
| 23745 |
|
|
--YB1_pc_gen_ctl_2_i_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_0
|
| 23746 |
|
|
--operation mode is normal
|
| 23747 |
|
|
|
| 23748 |
|
|
YB1_pc_gen_ctl_2_i_0_0 = !YB1_pc_gen_ctl_2_i_0_5[2] & !KE1_q_a[3] & !YB1_pc_gen_ctl_2_i_0_a[2] # !YB1_fsm_dly_2_0_0_a2_x[2];
|
| 23749 |
|
|
|
| 23750 |
|
|
|
| 23751 |
|
|
--WB26L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1|q[0]~68
|
| 23752 |
|
|
--operation mode is normal
|
| 23753 |
|
|
|
| 23754 |
|
|
WB26L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_pc_gen_ctl_2_i_0_0 # !YB1_un1_muxa_ctl370_x & WB26L2;
|
| 23755 |
|
|
|
| 23756 |
|
|
|
| 23757 |
|
|
--WB26L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1|q[0]~69
|
| 23758 |
|
|
--operation mode is normal
|
| 23759 |
|
|
|
| 23760 |
|
|
WB26L2 = WB26L1 & !YB1_un1_ins_i_23_2_0;
|
| 23761 |
|
|
|
| 23762 |
|
|
|
| 23763 |
|
|
--YB1_pc_gen_ctl_2_i_m3_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_0
|
| 23764 |
|
|
--operation mode is normal
|
| 23765 |
|
|
|
| 23766 |
|
|
YB1_pc_gen_ctl_2_i_m3_0_0 = YB1_pc_gen_ctl_2_i_m3_0_5[0] # !GE1_q_a[4] & YB1_pc_gen_ctl_2_i_m3_0_a_x[0] & YB1_muxa_ctl_2_0_0_o2_0[1];
|
| 23767 |
|
|
|
| 23768 |
|
|
|
| 23769 |
|
|
--WB06L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1|q[0]~68
|
| 23770 |
|
|
--operation mode is normal
|
| 23771 |
|
|
|
| 23772 |
|
|
WB06L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_pc_gen_ctl_2_i_m3_0_0 # !YB1_un1_muxa_ctl370_x & WB06L2;
|
| 23773 |
|
|
|
| 23774 |
|
|
|
| 23775 |
|
|
--WB06L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1|q[0]~69
|
| 23776 |
|
|
--operation mode is normal
|
| 23777 |
|
|
|
| 23778 |
|
|
WB06L2 = WB06L1 & !YB1_un1_ins_i_23_2_0;
|
| 23779 |
|
|
|
| 23780 |
|
|
|
| 23781 |
|
|
--YB1_pc_gen_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_0_0_0
|
| 23782 |
|
|
--operation mode is normal
|
| 23783 |
|
|
|
| 23784 |
|
|
YB1_pc_gen_ctl_2_0_0_0 = YB1_pc_gen_ctl_2_0_0_a2_x[1] & YB1_alu_func_2_0_0_a2_3_x[0] & YB1_alu_func_2_0_0_a2_2_x[0] # !YB1_pc_gen_ctl_2_0_0_a[1];
|
| 23785 |
|
|
|
| 23786 |
|
|
|
| 23787 |
|
|
--WB16L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:pc_gen_ctl_1_1_|lpm_latch:U1|q[0]~56
|
| 23788 |
|
|
--operation mode is normal
|
| 23789 |
|
|
|
| 23790 |
|
|
WB16L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_pc_gen_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB16L1;
|
| 23791 |
|
|
|
| 23792 |
|
|
|
| 23793 |
|
|
--BC1_cmp_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2|cmp_ctl_o_2
|
| 23794 |
|
|
--operation mode is normal
|
| 23795 |
|
|
|
| 23796 |
|
|
BC1_cmp_ctl_o_2_lut_out = WB54L1;
|
| 23797 |
|
|
BC1_cmp_ctl_o_2 = DFFEAS(BC1_cmp_ctl_o_2_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 23798 |
|
|
|
| 23799 |
|
|
|
| 23800 |
|
|
--BC1_cmp_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2|cmp_ctl_o_1
|
| 23801 |
|
|
--operation mode is normal
|
| 23802 |
|
|
|
| 23803 |
|
|
BC1_cmp_ctl_o_1_lut_out = WB44L1;
|
| 23804 |
|
|
BC1_cmp_ctl_o_1 = DFFEAS(BC1_cmp_ctl_o_1_lut_out, E1__clk0, VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
|
| 23805 |
|
|
|
| 23806 |
|
|
|
| 23807 |
|
|
--BD1_res_2_NE is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE
|
| 23808 |
|
|
--operation mode is normal
|
| 23809 |
|
|
|
| 23810 |
|
|
BD1_res_2_NE = BD1_res_2_NE_12_0 # BD1_res_2_NE_9_0 # BD1_res_2_NE_11_0 # BD1_res_2_NE_10_0;
|
| 23811 |
|
|
|
| 23812 |
|
|
|
| 23813 |
|
|
--BD1_res_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_5
|
| 23814 |
|
|
--operation mode is normal
|
| 23815 |
|
|
|
| 23816 |
|
|
BD1_res_5 = !PB1_dout_iv_31 & BD1_un10_res_27 # BD1_un10_res_28;
|
| 23817 |
|
|
|
| 23818 |
|
|
|
| 23819 |
|
|
--F1_cmd[10] is mips_sys:isys|mips_dvc:imips_dvc|cmd[10]
|
| 23820 |
|
|
--operation mode is normal
|
| 23821 |
|
|
|
| 23822 |
|
|
F1_cmd[10]_lut_out = CB1_r32_o_10;
|
| 23823 |
|
|
F1_cmd[10] = DFFEAS(F1_cmd[10]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23824 |
|
|
|
| 23825 |
|
|
|
| 23826 |
|
|
--F1_cmd[11] is mips_sys:isys|mips_dvc:imips_dvc|cmd[11]
|
| 23827 |
|
|
--operation mode is normal
|
| 23828 |
|
|
|
| 23829 |
|
|
F1_cmd[11]_lut_out = CB1_r32_o_11;
|
| 23830 |
|
|
F1_cmd[11] = DFFEAS(F1_cmd[11]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23831 |
|
|
|
| 23832 |
|
|
|
| 23833 |
|
|
--F1_cmd[12] is mips_sys:isys|mips_dvc:imips_dvc|cmd[12]
|
| 23834 |
|
|
--operation mode is normal
|
| 23835 |
|
|
|
| 23836 |
|
|
F1_cmd[12]_lut_out = CB1_r32_o_12;
|
| 23837 |
|
|
F1_cmd[12] = DFFEAS(F1_cmd[12]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23838 |
|
|
|
| 23839 |
|
|
|
| 23840 |
|
|
--F1_cmd[23] is mips_sys:isys|mips_dvc:imips_dvc|cmd[23]
|
| 23841 |
|
|
--operation mode is normal
|
| 23842 |
|
|
|
| 23843 |
|
|
F1_cmd[23]_lut_out = CB1_r32_o_23;
|
| 23844 |
|
|
F1_cmd[23] = DFFEAS(F1_cmd[23]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23845 |
|
|
|
| 23846 |
|
|
|
| 23847 |
|
|
--UB1_dout_2_0_0_a_x[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a_x[9]
|
| 23848 |
|
|
--operation mode is normal
|
| 23849 |
|
|
|
| 23850 |
|
|
UB1_dout_2_0_0_a_x[9] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[1];
|
| 23851 |
|
|
|
| 23852 |
|
|
|
| 23853 |
|
|
--GD1_dout_iv_1_a[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[11]
|
| 23854 |
|
|
--operation mode is normal
|
| 23855 |
|
|
|
| 23856 |
|
|
GD1_dout_iv_1_a[11] = FD1_r_data_11 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_9 # !FD1_r_data_11 & !ZD1_mux_fw_1 # !AB1_r32_o_9;
|
| 23857 |
|
|
|
| 23858 |
|
|
|
| 23859 |
|
|
--LD1_q_b[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[11]
|
| 23860 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 23861 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 23862 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 23863 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 23864 |
|
|
LD1_q_b[11]_PORT_A_data_in = FD1_wb_o_11;
|
| 23865 |
|
|
LD1_q_b[11]_PORT_A_data_in_reg = DFFE(LD1_q_b[11]_PORT_A_data_in, LD1_q_b[11]_clock_0, , , );
|
| 23866 |
|
|
LD1_q_b[11]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 23867 |
|
|
LD1_q_b[11]_PORT_A_address_reg = DFFE(LD1_q_b[11]_PORT_A_address, LD1_q_b[11]_clock_0, , , );
|
| 23868 |
|
|
LD1_q_b[11]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 23869 |
|
|
LD1_q_b[11]_PORT_B_address_reg = DFFE(LD1_q_b[11]_PORT_B_address, LD1_q_b[11]_clock_1, , , );
|
| 23870 |
|
|
LD1_q_b[11]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 23871 |
|
|
LD1_q_b[11]_PORT_A_write_enable_reg = DFFE(LD1_q_b[11]_PORT_A_write_enable, LD1_q_b[11]_clock_0, , , );
|
| 23872 |
|
|
LD1_q_b[11]_PORT_B_read_enable = VCC;
|
| 23873 |
|
|
LD1_q_b[11]_PORT_B_read_enable_reg = DFFE(LD1_q_b[11]_PORT_B_read_enable, LD1_q_b[11]_clock_1, , , );
|
| 23874 |
|
|
LD1_q_b[11]_clock_0 = E1__clk0;
|
| 23875 |
|
|
LD1_q_b[11]_clock_1 = E1__clk0;
|
| 23876 |
|
|
LD1_q_b[11]_PORT_B_data_out = MEMORY(LD1_q_b[11]_PORT_A_data_in_reg, , LD1_q_b[11]_PORT_A_address_reg, LD1_q_b[11]_PORT_B_address_reg, LD1_q_b[11]_PORT_A_write_enable_reg, LD1_q_b[11]_PORT_B_read_enable_reg, , , LD1_q_b[11]_clock_0, LD1_q_b[11]_clock_1, , , , );
|
| 23877 |
|
|
LD1_q_b[11] = LD1_q_b[11]_PORT_B_data_out[0];
|
| 23878 |
|
|
|
| 23879 |
|
|
|
| 23880 |
|
|
--GD1_dout_iv_1_a[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[13]
|
| 23881 |
|
|
--operation mode is normal
|
| 23882 |
|
|
|
| 23883 |
|
|
GD1_dout_iv_1_a[13] = FD1_r_data_13 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_11 # !FD1_r_data_13 & !ZD1_mux_fw_1 # !AB1_r32_o_11;
|
| 23884 |
|
|
|
| 23885 |
|
|
|
| 23886 |
|
|
--LD1_q_b[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[13]
|
| 23887 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 23888 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 23889 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 23890 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 23891 |
|
|
LD1_q_b[13]_PORT_A_data_in = FD1_wb_o_13;
|
| 23892 |
|
|
LD1_q_b[13]_PORT_A_data_in_reg = DFFE(LD1_q_b[13]_PORT_A_data_in, LD1_q_b[13]_clock_0, , , );
|
| 23893 |
|
|
LD1_q_b[13]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 23894 |
|
|
LD1_q_b[13]_PORT_A_address_reg = DFFE(LD1_q_b[13]_PORT_A_address, LD1_q_b[13]_clock_0, , , );
|
| 23895 |
|
|
LD1_q_b[13]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 23896 |
|
|
LD1_q_b[13]_PORT_B_address_reg = DFFE(LD1_q_b[13]_PORT_B_address, LD1_q_b[13]_clock_1, , , );
|
| 23897 |
|
|
LD1_q_b[13]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 23898 |
|
|
LD1_q_b[13]_PORT_A_write_enable_reg = DFFE(LD1_q_b[13]_PORT_A_write_enable, LD1_q_b[13]_clock_0, , , );
|
| 23899 |
|
|
LD1_q_b[13]_PORT_B_read_enable = VCC;
|
| 23900 |
|
|
LD1_q_b[13]_PORT_B_read_enable_reg = DFFE(LD1_q_b[13]_PORT_B_read_enable, LD1_q_b[13]_clock_1, , , );
|
| 23901 |
|
|
LD1_q_b[13]_clock_0 = E1__clk0;
|
| 23902 |
|
|
LD1_q_b[13]_clock_1 = E1__clk0;
|
| 23903 |
|
|
LD1_q_b[13]_PORT_B_data_out = MEMORY(LD1_q_b[13]_PORT_A_data_in_reg, , LD1_q_b[13]_PORT_A_address_reg, LD1_q_b[13]_PORT_B_address_reg, LD1_q_b[13]_PORT_A_write_enable_reg, LD1_q_b[13]_PORT_B_read_enable_reg, , , LD1_q_b[13]_clock_0, LD1_q_b[13]_clock_1, , , , );
|
| 23904 |
|
|
LD1_q_b[13] = LD1_q_b[13]_PORT_B_data_out[0];
|
| 23905 |
|
|
|
| 23906 |
|
|
|
| 23907 |
|
|
--F1_cmd[13] is mips_sys:isys|mips_dvc:imips_dvc|cmd[13]
|
| 23908 |
|
|
--operation mode is normal
|
| 23909 |
|
|
|
| 23910 |
|
|
F1_cmd[13]_lut_out = CB1_r32_o_13;
|
| 23911 |
|
|
F1_cmd[13] = DFFEAS(F1_cmd[13]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23912 |
|
|
|
| 23913 |
|
|
|
| 23914 |
|
|
--GD1_dout_iv_1_a[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[12]
|
| 23915 |
|
|
--operation mode is normal
|
| 23916 |
|
|
|
| 23917 |
|
|
GD1_dout_iv_1_a[12] = FD1_r_data_12 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_10 # !FD1_r_data_12 & !ZD1_mux_fw_1 # !AB1_r32_o_10;
|
| 23918 |
|
|
|
| 23919 |
|
|
|
| 23920 |
|
|
--LD1_q_b[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[12]
|
| 23921 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 23922 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 23923 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 23924 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 23925 |
|
|
LD1_q_b[12]_PORT_A_data_in = FD1_wb_o_12;
|
| 23926 |
|
|
LD1_q_b[12]_PORT_A_data_in_reg = DFFE(LD1_q_b[12]_PORT_A_data_in, LD1_q_b[12]_clock_0, , , );
|
| 23927 |
|
|
LD1_q_b[12]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 23928 |
|
|
LD1_q_b[12]_PORT_A_address_reg = DFFE(LD1_q_b[12]_PORT_A_address, LD1_q_b[12]_clock_0, , , );
|
| 23929 |
|
|
LD1_q_b[12]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 23930 |
|
|
LD1_q_b[12]_PORT_B_address_reg = DFFE(LD1_q_b[12]_PORT_B_address, LD1_q_b[12]_clock_1, , , );
|
| 23931 |
|
|
LD1_q_b[12]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 23932 |
|
|
LD1_q_b[12]_PORT_A_write_enable_reg = DFFE(LD1_q_b[12]_PORT_A_write_enable, LD1_q_b[12]_clock_0, , , );
|
| 23933 |
|
|
LD1_q_b[12]_PORT_B_read_enable = VCC;
|
| 23934 |
|
|
LD1_q_b[12]_PORT_B_read_enable_reg = DFFE(LD1_q_b[12]_PORT_B_read_enable, LD1_q_b[12]_clock_1, , , );
|
| 23935 |
|
|
LD1_q_b[12]_clock_0 = E1__clk0;
|
| 23936 |
|
|
LD1_q_b[12]_clock_1 = E1__clk0;
|
| 23937 |
|
|
LD1_q_b[12]_PORT_B_data_out = MEMORY(LD1_q_b[12]_PORT_A_data_in_reg, , LD1_q_b[12]_PORT_A_address_reg, LD1_q_b[12]_PORT_B_address_reg, LD1_q_b[12]_PORT_A_write_enable_reg, LD1_q_b[12]_PORT_B_read_enable_reg, , , LD1_q_b[12]_clock_0, LD1_q_b[12]_clock_1, , , , );
|
| 23938 |
|
|
LD1_q_b[12] = LD1_q_b[12]_PORT_B_data_out[0];
|
| 23939 |
|
|
|
| 23940 |
|
|
|
| 23941 |
|
|
--GD1_dout_iv_1_a[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[14]
|
| 23942 |
|
|
--operation mode is normal
|
| 23943 |
|
|
|
| 23944 |
|
|
GD1_dout_iv_1_a[14] = FD1_r_data_14 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_12 # !FD1_r_data_14 & !ZD1_mux_fw_1 # !AB1_r32_o_12;
|
| 23945 |
|
|
|
| 23946 |
|
|
|
| 23947 |
|
|
--LD1_q_b[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[14]
|
| 23948 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 23949 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 23950 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 23951 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 23952 |
|
|
LD1_q_b[14]_PORT_A_data_in = FD1_wb_o_14;
|
| 23953 |
|
|
LD1_q_b[14]_PORT_A_data_in_reg = DFFE(LD1_q_b[14]_PORT_A_data_in, LD1_q_b[14]_clock_0, , , );
|
| 23954 |
|
|
LD1_q_b[14]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 23955 |
|
|
LD1_q_b[14]_PORT_A_address_reg = DFFE(LD1_q_b[14]_PORT_A_address, LD1_q_b[14]_clock_0, , , );
|
| 23956 |
|
|
LD1_q_b[14]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 23957 |
|
|
LD1_q_b[14]_PORT_B_address_reg = DFFE(LD1_q_b[14]_PORT_B_address, LD1_q_b[14]_clock_1, , , );
|
| 23958 |
|
|
LD1_q_b[14]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 23959 |
|
|
LD1_q_b[14]_PORT_A_write_enable_reg = DFFE(LD1_q_b[14]_PORT_A_write_enable, LD1_q_b[14]_clock_0, , , );
|
| 23960 |
|
|
LD1_q_b[14]_PORT_B_read_enable = VCC;
|
| 23961 |
|
|
LD1_q_b[14]_PORT_B_read_enable_reg = DFFE(LD1_q_b[14]_PORT_B_read_enable, LD1_q_b[14]_clock_1, , , );
|
| 23962 |
|
|
LD1_q_b[14]_clock_0 = E1__clk0;
|
| 23963 |
|
|
LD1_q_b[14]_clock_1 = E1__clk0;
|
| 23964 |
|
|
LD1_q_b[14]_PORT_B_data_out = MEMORY(LD1_q_b[14]_PORT_A_data_in_reg, , LD1_q_b[14]_PORT_A_address_reg, LD1_q_b[14]_PORT_B_address_reg, LD1_q_b[14]_PORT_A_write_enable_reg, LD1_q_b[14]_PORT_B_read_enable_reg, , , LD1_q_b[14]_clock_0, LD1_q_b[14]_clock_1, , , , );
|
| 23965 |
|
|
LD1_q_b[14] = LD1_q_b[14]_PORT_B_data_out[0];
|
| 23966 |
|
|
|
| 23967 |
|
|
|
| 23968 |
|
|
--F1_cmd[14] is mips_sys:isys|mips_dvc:imips_dvc|cmd[14]
|
| 23969 |
|
|
--operation mode is normal
|
| 23970 |
|
|
|
| 23971 |
|
|
F1_cmd[14]_lut_out = CB1_r32_o_14;
|
| 23972 |
|
|
F1_cmd[14] = DFFEAS(F1_cmd[14]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 23973 |
|
|
|
| 23974 |
|
|
|
| 23975 |
|
|
--GD1_dout_iv_1_a[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[21]
|
| 23976 |
|
|
--operation mode is normal
|
| 23977 |
|
|
|
| 23978 |
|
|
GD1_dout_iv_1_a[21] = FD1_r_data_21 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_19 # !FD1_r_data_21 & !ZD1_mux_fw_1 # !AB1_r32_o_19;
|
| 23979 |
|
|
|
| 23980 |
|
|
|
| 23981 |
|
|
--LD1_q_b[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[21]
|
| 23982 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 23983 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 23984 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 23985 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 23986 |
|
|
LD1_q_b[21]_PORT_A_data_in = FD1_wb_o_21;
|
| 23987 |
|
|
LD1_q_b[21]_PORT_A_data_in_reg = DFFE(LD1_q_b[21]_PORT_A_data_in, LD1_q_b[21]_clock_0, , , );
|
| 23988 |
|
|
LD1_q_b[21]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 23989 |
|
|
LD1_q_b[21]_PORT_A_address_reg = DFFE(LD1_q_b[21]_PORT_A_address, LD1_q_b[21]_clock_0, , , );
|
| 23990 |
|
|
LD1_q_b[21]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 23991 |
|
|
LD1_q_b[21]_PORT_B_address_reg = DFFE(LD1_q_b[21]_PORT_B_address, LD1_q_b[21]_clock_1, , , );
|
| 23992 |
|
|
LD1_q_b[21]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 23993 |
|
|
LD1_q_b[21]_PORT_A_write_enable_reg = DFFE(LD1_q_b[21]_PORT_A_write_enable, LD1_q_b[21]_clock_0, , , );
|
| 23994 |
|
|
LD1_q_b[21]_PORT_B_read_enable = VCC;
|
| 23995 |
|
|
LD1_q_b[21]_PORT_B_read_enable_reg = DFFE(LD1_q_b[21]_PORT_B_read_enable, LD1_q_b[21]_clock_1, , , );
|
| 23996 |
|
|
LD1_q_b[21]_clock_0 = E1__clk0;
|
| 23997 |
|
|
LD1_q_b[21]_clock_1 = E1__clk0;
|
| 23998 |
|
|
LD1_q_b[21]_PORT_B_data_out = MEMORY(LD1_q_b[21]_PORT_A_data_in_reg, , LD1_q_b[21]_PORT_A_address_reg, LD1_q_b[21]_PORT_B_address_reg, LD1_q_b[21]_PORT_A_write_enable_reg, LD1_q_b[21]_PORT_B_read_enable_reg, , , LD1_q_b[21]_clock_0, LD1_q_b[21]_clock_1, , , , );
|
| 23999 |
|
|
LD1_q_b[21] = LD1_q_b[21]_PORT_B_data_out[0];
|
| 24000 |
|
|
|
| 24001 |
|
|
|
| 24002 |
|
|
--GD1_dout_iv_1_a[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[22]
|
| 24003 |
|
|
--operation mode is normal
|
| 24004 |
|
|
|
| 24005 |
|
|
GD1_dout_iv_1_a[22] = FD1_r_data_22 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_20 # !FD1_r_data_22 & !ZD1_mux_fw_1 # !AB1_r32_o_20;
|
| 24006 |
|
|
|
| 24007 |
|
|
|
| 24008 |
|
|
--LD1_q_b[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[22]
|
| 24009 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24010 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24011 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24012 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24013 |
|
|
LD1_q_b[22]_PORT_A_data_in = FD1_wb_o_22;
|
| 24014 |
|
|
LD1_q_b[22]_PORT_A_data_in_reg = DFFE(LD1_q_b[22]_PORT_A_data_in, LD1_q_b[22]_clock_0, , , );
|
| 24015 |
|
|
LD1_q_b[22]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24016 |
|
|
LD1_q_b[22]_PORT_A_address_reg = DFFE(LD1_q_b[22]_PORT_A_address, LD1_q_b[22]_clock_0, , , );
|
| 24017 |
|
|
LD1_q_b[22]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24018 |
|
|
LD1_q_b[22]_PORT_B_address_reg = DFFE(LD1_q_b[22]_PORT_B_address, LD1_q_b[22]_clock_1, , , );
|
| 24019 |
|
|
LD1_q_b[22]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24020 |
|
|
LD1_q_b[22]_PORT_A_write_enable_reg = DFFE(LD1_q_b[22]_PORT_A_write_enable, LD1_q_b[22]_clock_0, , , );
|
| 24021 |
|
|
LD1_q_b[22]_PORT_B_read_enable = VCC;
|
| 24022 |
|
|
LD1_q_b[22]_PORT_B_read_enable_reg = DFFE(LD1_q_b[22]_PORT_B_read_enable, LD1_q_b[22]_clock_1, , , );
|
| 24023 |
|
|
LD1_q_b[22]_clock_0 = E1__clk0;
|
| 24024 |
|
|
LD1_q_b[22]_clock_1 = E1__clk0;
|
| 24025 |
|
|
LD1_q_b[22]_PORT_B_data_out = MEMORY(LD1_q_b[22]_PORT_A_data_in_reg, , LD1_q_b[22]_PORT_A_address_reg, LD1_q_b[22]_PORT_B_address_reg, LD1_q_b[22]_PORT_A_write_enable_reg, LD1_q_b[22]_PORT_B_read_enable_reg, , , LD1_q_b[22]_clock_0, LD1_q_b[22]_clock_1, , , , );
|
| 24026 |
|
|
LD1_q_b[22] = LD1_q_b[22]_PORT_B_data_out[0];
|
| 24027 |
|
|
|
| 24028 |
|
|
|
| 24029 |
|
|
--GD1_dout_iv_1_a[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[25]
|
| 24030 |
|
|
--operation mode is normal
|
| 24031 |
|
|
|
| 24032 |
|
|
GD1_dout_iv_1_a[25] = FD1_r_data_25 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_23 # !FD1_r_data_25 & !ZD1_mux_fw_1 # !AB1_r32_o_23;
|
| 24033 |
|
|
|
| 24034 |
|
|
|
| 24035 |
|
|
--LD1_q_b[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[25]
|
| 24036 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24037 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24038 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24039 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24040 |
|
|
LD1_q_b[25]_PORT_A_data_in = FD1_wb_o_25;
|
| 24041 |
|
|
LD1_q_b[25]_PORT_A_data_in_reg = DFFE(LD1_q_b[25]_PORT_A_data_in, LD1_q_b[25]_clock_0, , , );
|
| 24042 |
|
|
LD1_q_b[25]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24043 |
|
|
LD1_q_b[25]_PORT_A_address_reg = DFFE(LD1_q_b[25]_PORT_A_address, LD1_q_b[25]_clock_0, , , );
|
| 24044 |
|
|
LD1_q_b[25]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24045 |
|
|
LD1_q_b[25]_PORT_B_address_reg = DFFE(LD1_q_b[25]_PORT_B_address, LD1_q_b[25]_clock_1, , , );
|
| 24046 |
|
|
LD1_q_b[25]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24047 |
|
|
LD1_q_b[25]_PORT_A_write_enable_reg = DFFE(LD1_q_b[25]_PORT_A_write_enable, LD1_q_b[25]_clock_0, , , );
|
| 24048 |
|
|
LD1_q_b[25]_PORT_B_read_enable = VCC;
|
| 24049 |
|
|
LD1_q_b[25]_PORT_B_read_enable_reg = DFFE(LD1_q_b[25]_PORT_B_read_enable, LD1_q_b[25]_clock_1, , , );
|
| 24050 |
|
|
LD1_q_b[25]_clock_0 = E1__clk0;
|
| 24051 |
|
|
LD1_q_b[25]_clock_1 = E1__clk0;
|
| 24052 |
|
|
LD1_q_b[25]_PORT_B_data_out = MEMORY(LD1_q_b[25]_PORT_A_data_in_reg, , LD1_q_b[25]_PORT_A_address_reg, LD1_q_b[25]_PORT_B_address_reg, LD1_q_b[25]_PORT_A_write_enable_reg, LD1_q_b[25]_PORT_B_read_enable_reg, , , LD1_q_b[25]_clock_0, LD1_q_b[25]_clock_1, , , , );
|
| 24053 |
|
|
LD1_q_b[25] = LD1_q_b[25]_PORT_B_data_out[0];
|
| 24054 |
|
|
|
| 24055 |
|
|
|
| 24056 |
|
|
--F1_cmd[25] is mips_sys:isys|mips_dvc:imips_dvc|cmd[25]
|
| 24057 |
|
|
--operation mode is normal
|
| 24058 |
|
|
|
| 24059 |
|
|
F1_cmd[25]_lut_out = CB1_r32_o_25;
|
| 24060 |
|
|
F1_cmd[25] = DFFEAS(F1_cmd[25]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 24061 |
|
|
|
| 24062 |
|
|
|
| 24063 |
|
|
--GD1_dout_iv_1_a[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[26]
|
| 24064 |
|
|
--operation mode is normal
|
| 24065 |
|
|
|
| 24066 |
|
|
GD1_dout_iv_1_a[26] = FD1_r_data_26 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_24 # !FD1_r_data_26 & !ZD1_mux_fw_1 # !AB1_r32_o_24;
|
| 24067 |
|
|
|
| 24068 |
|
|
|
| 24069 |
|
|
--LD1_q_b[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[26]
|
| 24070 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24071 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24072 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24073 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24074 |
|
|
LD1_q_b[26]_PORT_A_data_in = FD1_wb_o_26;
|
| 24075 |
|
|
LD1_q_b[26]_PORT_A_data_in_reg = DFFE(LD1_q_b[26]_PORT_A_data_in, LD1_q_b[26]_clock_0, , , );
|
| 24076 |
|
|
LD1_q_b[26]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24077 |
|
|
LD1_q_b[26]_PORT_A_address_reg = DFFE(LD1_q_b[26]_PORT_A_address, LD1_q_b[26]_clock_0, , , );
|
| 24078 |
|
|
LD1_q_b[26]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24079 |
|
|
LD1_q_b[26]_PORT_B_address_reg = DFFE(LD1_q_b[26]_PORT_B_address, LD1_q_b[26]_clock_1, , , );
|
| 24080 |
|
|
LD1_q_b[26]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24081 |
|
|
LD1_q_b[26]_PORT_A_write_enable_reg = DFFE(LD1_q_b[26]_PORT_A_write_enable, LD1_q_b[26]_clock_0, , , );
|
| 24082 |
|
|
LD1_q_b[26]_PORT_B_read_enable = VCC;
|
| 24083 |
|
|
LD1_q_b[26]_PORT_B_read_enable_reg = DFFE(LD1_q_b[26]_PORT_B_read_enable, LD1_q_b[26]_clock_1, , , );
|
| 24084 |
|
|
LD1_q_b[26]_clock_0 = E1__clk0;
|
| 24085 |
|
|
LD1_q_b[26]_clock_1 = E1__clk0;
|
| 24086 |
|
|
LD1_q_b[26]_PORT_B_data_out = MEMORY(LD1_q_b[26]_PORT_A_data_in_reg, , LD1_q_b[26]_PORT_A_address_reg, LD1_q_b[26]_PORT_B_address_reg, LD1_q_b[26]_PORT_A_write_enable_reg, LD1_q_b[26]_PORT_B_read_enable_reg, , , LD1_q_b[26]_clock_0, LD1_q_b[26]_clock_1, , , , );
|
| 24087 |
|
|
LD1_q_b[26] = LD1_q_b[26]_PORT_B_data_out[0];
|
| 24088 |
|
|
|
| 24089 |
|
|
|
| 24090 |
|
|
--F1_cmd[26] is mips_sys:isys|mips_dvc:imips_dvc|cmd[26]
|
| 24091 |
|
|
--operation mode is normal
|
| 24092 |
|
|
|
| 24093 |
|
|
F1_cmd[26]_lut_out = CB1_r32_o_26;
|
| 24094 |
|
|
F1_cmd[26] = DFFEAS(F1_cmd[26]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 24095 |
|
|
|
| 24096 |
|
|
|
| 24097 |
|
|
--GD1_dout_iv_1_a[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[29]
|
| 24098 |
|
|
--operation mode is normal
|
| 24099 |
|
|
|
| 24100 |
|
|
GD1_dout_iv_1_a[29] = FD1_r_data_29 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_27 # !FD1_r_data_29 & !ZD1_mux_fw_1 # !AB1_r32_o_27;
|
| 24101 |
|
|
|
| 24102 |
|
|
|
| 24103 |
|
|
--LD1_q_b[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[29]
|
| 24104 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24105 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24106 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24107 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24108 |
|
|
LD1_q_b[29]_PORT_A_data_in = FD1_wb_o_29;
|
| 24109 |
|
|
LD1_q_b[29]_PORT_A_data_in_reg = DFFE(LD1_q_b[29]_PORT_A_data_in, LD1_q_b[29]_clock_0, , , );
|
| 24110 |
|
|
LD1_q_b[29]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24111 |
|
|
LD1_q_b[29]_PORT_A_address_reg = DFFE(LD1_q_b[29]_PORT_A_address, LD1_q_b[29]_clock_0, , , );
|
| 24112 |
|
|
LD1_q_b[29]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24113 |
|
|
LD1_q_b[29]_PORT_B_address_reg = DFFE(LD1_q_b[29]_PORT_B_address, LD1_q_b[29]_clock_1, , , );
|
| 24114 |
|
|
LD1_q_b[29]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24115 |
|
|
LD1_q_b[29]_PORT_A_write_enable_reg = DFFE(LD1_q_b[29]_PORT_A_write_enable, LD1_q_b[29]_clock_0, , , );
|
| 24116 |
|
|
LD1_q_b[29]_PORT_B_read_enable = VCC;
|
| 24117 |
|
|
LD1_q_b[29]_PORT_B_read_enable_reg = DFFE(LD1_q_b[29]_PORT_B_read_enable, LD1_q_b[29]_clock_1, , , );
|
| 24118 |
|
|
LD1_q_b[29]_clock_0 = E1__clk0;
|
| 24119 |
|
|
LD1_q_b[29]_clock_1 = E1__clk0;
|
| 24120 |
|
|
LD1_q_b[29]_PORT_B_data_out = MEMORY(LD1_q_b[29]_PORT_A_data_in_reg, , LD1_q_b[29]_PORT_A_address_reg, LD1_q_b[29]_PORT_B_address_reg, LD1_q_b[29]_PORT_A_write_enable_reg, LD1_q_b[29]_PORT_B_read_enable_reg, , , LD1_q_b[29]_clock_0, LD1_q_b[29]_clock_1, , , , );
|
| 24121 |
|
|
LD1_q_b[29] = LD1_q_b[29]_PORT_B_data_out[0];
|
| 24122 |
|
|
|
| 24123 |
|
|
|
| 24124 |
|
|
--GD1_dout_iv_1_a[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[17]
|
| 24125 |
|
|
--operation mode is normal
|
| 24126 |
|
|
|
| 24127 |
|
|
GD1_dout_iv_1_a[17] = FD1_r_data_17 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_15 # !FD1_r_data_17 & !ZD1_mux_fw_1 # !AB1_r32_o_15;
|
| 24128 |
|
|
|
| 24129 |
|
|
|
| 24130 |
|
|
--LD1_q_b[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[17]
|
| 24131 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24132 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24133 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24134 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24135 |
|
|
LD1_q_b[17]_PORT_A_data_in = FD1_wb_o_17;
|
| 24136 |
|
|
LD1_q_b[17]_PORT_A_data_in_reg = DFFE(LD1_q_b[17]_PORT_A_data_in, LD1_q_b[17]_clock_0, , , );
|
| 24137 |
|
|
LD1_q_b[17]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24138 |
|
|
LD1_q_b[17]_PORT_A_address_reg = DFFE(LD1_q_b[17]_PORT_A_address, LD1_q_b[17]_clock_0, , , );
|
| 24139 |
|
|
LD1_q_b[17]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24140 |
|
|
LD1_q_b[17]_PORT_B_address_reg = DFFE(LD1_q_b[17]_PORT_B_address, LD1_q_b[17]_clock_1, , , );
|
| 24141 |
|
|
LD1_q_b[17]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24142 |
|
|
LD1_q_b[17]_PORT_A_write_enable_reg = DFFE(LD1_q_b[17]_PORT_A_write_enable, LD1_q_b[17]_clock_0, , , );
|
| 24143 |
|
|
LD1_q_b[17]_PORT_B_read_enable = VCC;
|
| 24144 |
|
|
LD1_q_b[17]_PORT_B_read_enable_reg = DFFE(LD1_q_b[17]_PORT_B_read_enable, LD1_q_b[17]_clock_1, , , );
|
| 24145 |
|
|
LD1_q_b[17]_clock_0 = E1__clk0;
|
| 24146 |
|
|
LD1_q_b[17]_clock_1 = E1__clk0;
|
| 24147 |
|
|
LD1_q_b[17]_PORT_B_data_out = MEMORY(LD1_q_b[17]_PORT_A_data_in_reg, , LD1_q_b[17]_PORT_A_address_reg, LD1_q_b[17]_PORT_B_address_reg, LD1_q_b[17]_PORT_A_write_enable_reg, LD1_q_b[17]_PORT_B_read_enable_reg, , , LD1_q_b[17]_clock_0, LD1_q_b[17]_clock_1, , , , );
|
| 24148 |
|
|
LD1_q_b[17] = LD1_q_b[17]_PORT_B_data_out[0];
|
| 24149 |
|
|
|
| 24150 |
|
|
|
| 24151 |
|
|
--GD1_dout_iv_1_a[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[18]
|
| 24152 |
|
|
--operation mode is normal
|
| 24153 |
|
|
|
| 24154 |
|
|
GD1_dout_iv_1_a[18] = FD1_r_data_18 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_16 # !FD1_r_data_18 & !ZD1_mux_fw_1 # !AB1_r32_o_16;
|
| 24155 |
|
|
|
| 24156 |
|
|
|
| 24157 |
|
|
--LD1_q_b[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[18]
|
| 24158 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24159 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24160 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24161 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24162 |
|
|
LD1_q_b[18]_PORT_A_data_in = FD1_wb_o_18;
|
| 24163 |
|
|
LD1_q_b[18]_PORT_A_data_in_reg = DFFE(LD1_q_b[18]_PORT_A_data_in, LD1_q_b[18]_clock_0, , , );
|
| 24164 |
|
|
LD1_q_b[18]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24165 |
|
|
LD1_q_b[18]_PORT_A_address_reg = DFFE(LD1_q_b[18]_PORT_A_address, LD1_q_b[18]_clock_0, , , );
|
| 24166 |
|
|
LD1_q_b[18]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24167 |
|
|
LD1_q_b[18]_PORT_B_address_reg = DFFE(LD1_q_b[18]_PORT_B_address, LD1_q_b[18]_clock_1, , , );
|
| 24168 |
|
|
LD1_q_b[18]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24169 |
|
|
LD1_q_b[18]_PORT_A_write_enable_reg = DFFE(LD1_q_b[18]_PORT_A_write_enable, LD1_q_b[18]_clock_0, , , );
|
| 24170 |
|
|
LD1_q_b[18]_PORT_B_read_enable = VCC;
|
| 24171 |
|
|
LD1_q_b[18]_PORT_B_read_enable_reg = DFFE(LD1_q_b[18]_PORT_B_read_enable, LD1_q_b[18]_clock_1, , , );
|
| 24172 |
|
|
LD1_q_b[18]_clock_0 = E1__clk0;
|
| 24173 |
|
|
LD1_q_b[18]_clock_1 = E1__clk0;
|
| 24174 |
|
|
LD1_q_b[18]_PORT_B_data_out = MEMORY(LD1_q_b[18]_PORT_A_data_in_reg, , LD1_q_b[18]_PORT_A_address_reg, LD1_q_b[18]_PORT_B_address_reg, LD1_q_b[18]_PORT_A_write_enable_reg, LD1_q_b[18]_PORT_B_read_enable_reg, , , LD1_q_b[18]_clock_0, LD1_q_b[18]_clock_1, , , , );
|
| 24175 |
|
|
LD1_q_b[18] = LD1_q_b[18]_PORT_B_data_out[0];
|
| 24176 |
|
|
|
| 24177 |
|
|
|
| 24178 |
|
|
--VD1_un1_op2_reged_1_combout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[8]
|
| 24179 |
|
|
--operation mode is normal
|
| 24180 |
|
|
|
| 24181 |
|
|
VD1_un1_op2_reged_1_combout[8] = VD1_eqop2_2_32 & VD1_op2_reged[8] # !VD1_eqop2_2_32 & VD1_nop2_reged[8];
|
| 24182 |
|
|
|
| 24183 |
|
|
|
| 24184 |
|
|
--YB1_rd_sel_2_0_0_a3_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_a3_0_a[0]
|
| 24185 |
|
|
--operation mode is normal
|
| 24186 |
|
|
|
| 24187 |
|
|
YB1_rd_sel_2_0_0_a3_0_a[0] = !KE1_q_a[2] & GE1_q_a[1] & !GE1_q_a[2] # !GE1_q_a[3];
|
| 24188 |
|
|
|
| 24189 |
|
|
|
| 24190 |
|
|
--YB1_alu_we_1_0_0_a3_1_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3_1_0_a[0]
|
| 24191 |
|
|
--operation mode is normal
|
| 24192 |
|
|
|
| 24193 |
|
|
YB1_alu_we_1_0_0_a3_1_0_a[0] = !KE1_q_a[2] & !KE1_q_a[6] & GE1_q_a[5] & !GE1_q_a[4];
|
| 24194 |
|
|
|
| 24195 |
|
|
|
| 24196 |
|
|
--UB1_dout_2_i_i_x[20] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[20]
|
| 24197 |
|
|
--operation mode is normal
|
| 24198 |
|
|
|
| 24199 |
|
|
UB1_dout_2_i_i_x[20] = UB1_dout_2_i_i_a2[16] # JE1_q_b[4] & UB1_dout_2_i_i_a3_0[16];
|
| 24200 |
|
|
|
| 24201 |
|
|
|
| 24202 |
|
|
--WB52L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_20__Z|lpm_latch:U1|q[0]~56
|
| 24203 |
|
|
--operation mode is normal
|
| 24204 |
|
|
|
| 24205 |
|
|
WB52L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[20] # !UB1_un1_byte_addr_2 & WB52L1;
|
| 24206 |
|
|
|
| 24207 |
|
|
|
| 24208 |
|
|
--GD1_dout_iv_1_a[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[20]
|
| 24209 |
|
|
--operation mode is normal
|
| 24210 |
|
|
|
| 24211 |
|
|
GD1_dout_iv_1_a[20] = FD1_r_data_20 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_18 # !FD1_r_data_20 & !ZD1_mux_fw_1 # !AB1_r32_o_18;
|
| 24212 |
|
|
|
| 24213 |
|
|
|
| 24214 |
|
|
--LD1_q_b[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[20]
|
| 24215 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24216 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24217 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24218 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24219 |
|
|
LD1_q_b[20]_PORT_A_data_in = FD1_wb_o_20;
|
| 24220 |
|
|
LD1_q_b[20]_PORT_A_data_in_reg = DFFE(LD1_q_b[20]_PORT_A_data_in, LD1_q_b[20]_clock_0, , , );
|
| 24221 |
|
|
LD1_q_b[20]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24222 |
|
|
LD1_q_b[20]_PORT_A_address_reg = DFFE(LD1_q_b[20]_PORT_A_address, LD1_q_b[20]_clock_0, , , );
|
| 24223 |
|
|
LD1_q_b[20]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24224 |
|
|
LD1_q_b[20]_PORT_B_address_reg = DFFE(LD1_q_b[20]_PORT_B_address, LD1_q_b[20]_clock_1, , , );
|
| 24225 |
|
|
LD1_q_b[20]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24226 |
|
|
LD1_q_b[20]_PORT_A_write_enable_reg = DFFE(LD1_q_b[20]_PORT_A_write_enable, LD1_q_b[20]_clock_0, , , );
|
| 24227 |
|
|
LD1_q_b[20]_PORT_B_read_enable = VCC;
|
| 24228 |
|
|
LD1_q_b[20]_PORT_B_read_enable_reg = DFFE(LD1_q_b[20]_PORT_B_read_enable, LD1_q_b[20]_clock_1, , , );
|
| 24229 |
|
|
LD1_q_b[20]_clock_0 = E1__clk0;
|
| 24230 |
|
|
LD1_q_b[20]_clock_1 = E1__clk0;
|
| 24231 |
|
|
LD1_q_b[20]_PORT_B_data_out = MEMORY(LD1_q_b[20]_PORT_A_data_in_reg, , LD1_q_b[20]_PORT_A_address_reg, LD1_q_b[20]_PORT_B_address_reg, LD1_q_b[20]_PORT_A_write_enable_reg, LD1_q_b[20]_PORT_B_read_enable_reg, , , LD1_q_b[20]_clock_0, LD1_q_b[20]_clock_1, , , , );
|
| 24232 |
|
|
LD1_q_b[20] = LD1_q_b[20]_PORT_B_data_out[0];
|
| 24233 |
|
|
|
| 24234 |
|
|
|
| 24235 |
|
|
--AD1_un1_rst_2_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un1_rst_2_a
|
| 24236 |
|
|
--operation mode is normal
|
| 24237 |
|
|
|
| 24238 |
|
|
AD1_un1_rst_2_a = !AD1_CurrState_Sreg0_3 & AD1_delay_counter_Sreg0[0] # AD1_delay_counter_Sreg0[5] # !AD1_un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0;
|
| 24239 |
|
|
|
| 24240 |
|
|
|
| 24241 |
|
|
--AD1_un1_rst_2_s is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un1_rst_2_s
|
| 24242 |
|
|
--operation mode is normal
|
| 24243 |
|
|
|
| 24244 |
|
|
AD1_un1_rst_2_s = !AD1_CurrState_Sreg0[7] & !AD1_CurrState_Sreg0_5 & sys_rst & !AD1_CurrState_Sreg0_2;
|
| 24245 |
|
|
|
| 24246 |
|
|
|
| 24247 |
|
|
--AD1_un4_next_delay_counter_Sreg0_c3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_c3
|
| 24248 |
|
|
--operation mode is normal
|
| 24249 |
|
|
|
| 24250 |
|
|
AD1_un4_next_delay_counter_Sreg0_c3 = AD1_delay_counter_Sreg0[1] # AD1_delay_counter_Sreg0[0] # AD1_delay_counter_Sreg0[2] # AD1_delay_counter_Sreg0[3];
|
| 24251 |
|
|
|
| 24252 |
|
|
|
| 24253 |
|
|
--AD1_un4_next_delay_counter_Sreg0_sum1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum1
|
| 24254 |
|
|
--operation mode is normal
|
| 24255 |
|
|
|
| 24256 |
|
|
AD1_un4_next_delay_counter_Sreg0_sum1 = AD1_delay_counter_Sreg0[1] $ !AD1_delay_counter_Sreg0[0];
|
| 24257 |
|
|
|
| 24258 |
|
|
|
| 24259 |
|
|
--WB86L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_1_|lpm_latch:U1|q[0]~14
|
| 24260 |
|
|
--operation mode is normal
|
| 24261 |
|
|
|
| 24262 |
|
|
WB86L1 = AD1_CurrState_Sreg0[2] # AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum1 # !AD1_un1_rst_2 & WB86L1;
|
| 24263 |
|
|
|
| 24264 |
|
|
|
| 24265 |
|
|
--AD1_un4_next_delay_counter_Sreg0_sum2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum2
|
| 24266 |
|
|
--operation mode is normal
|
| 24267 |
|
|
|
| 24268 |
|
|
AD1_un4_next_delay_counter_Sreg0_sum2 = AD1_delay_counter_Sreg0[2] $ (!AD1_delay_counter_Sreg0[1] & !AD1_delay_counter_Sreg0[0]);
|
| 24269 |
|
|
|
| 24270 |
|
|
|
| 24271 |
|
|
--WB96L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z|lpm_latch:U1|q[0]~56
|
| 24272 |
|
|
--operation mode is normal
|
| 24273 |
|
|
|
| 24274 |
|
|
WB96L1 = !AD1_CurrState_Sreg0[2] & AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum2 # !AD1_un1_rst_2 & WB96L1;
|
| 24275 |
|
|
|
| 24276 |
|
|
|
| 24277 |
|
|
--AD1_un4_next_delay_counter_Sreg0_sum3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum3
|
| 24278 |
|
|
--operation mode is normal
|
| 24279 |
|
|
|
| 24280 |
|
|
AD1_un4_next_delay_counter_Sreg0_sum3 = AD1_delay_counter_Sreg0[3] $ (!AD1_delay_counter_Sreg0[1] & !AD1_delay_counter_Sreg0[0] & !AD1_delay_counter_Sreg0[2]);
|
| 24281 |
|
|
|
| 24282 |
|
|
|
| 24283 |
|
|
--WB07L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z|lpm_latch:U1|q[0]~56
|
| 24284 |
|
|
--operation mode is normal
|
| 24285 |
|
|
|
| 24286 |
|
|
WB07L1 = !AD1_CurrState_Sreg0[2] & AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum3 # !AD1_un1_rst_2 & WB07L1;
|
| 24287 |
|
|
|
| 24288 |
|
|
|
| 24289 |
|
|
--AD1_un4_next_delay_counter_Sreg0_sum4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum4
|
| 24290 |
|
|
--operation mode is normal
|
| 24291 |
|
|
|
| 24292 |
|
|
AD1_un4_next_delay_counter_Sreg0_sum4 = AD1_delay_counter_Sreg0[4] $ !AD1_un4_next_delay_counter_Sreg0_c3;
|
| 24293 |
|
|
|
| 24294 |
|
|
|
| 24295 |
|
|
--WB17L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z|lpm_latch:U1|q[0]~56
|
| 24296 |
|
|
--operation mode is normal
|
| 24297 |
|
|
|
| 24298 |
|
|
WB17L1 = !AD1_CurrState_Sreg0[2] & AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum4 # !AD1_un1_rst_2 & WB17L1;
|
| 24299 |
|
|
|
| 24300 |
|
|
|
| 24301 |
|
|
--YB1_muxa_ctl_2_0_0_o2_0[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_o2_0[1]
|
| 24302 |
|
|
--operation mode is normal
|
| 24303 |
|
|
|
| 24304 |
|
|
YB1_muxa_ctl_2_0_0_o2_0[1] = GE1_q_a[5] & YB1_muxa_ctl_2_0_0_a2_0_0[1] # YB1_alu_func_2_0_0_a2_0_x[3] & !YB1_alu_func_2_0_0_o2_x[3] # !GE1_q_a[5] & YB1_alu_func_2_0_0_a2_0_x[3] & !YB1_alu_func_2_0_0_o2_x[3];
|
| 24305 |
|
|
|
| 24306 |
|
|
|
| 24307 |
|
|
--YB1_muxb_ctl_2_0_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_0_a[1]
|
| 24308 |
|
|
--operation mode is normal
|
| 24309 |
|
|
|
| 24310 |
|
|
YB1_muxb_ctl_2_0_0_0_a[1] = JE1_q_a[7] & !YB1_fsm_dly_2_0_0_o2_x[2] # !WB95L2 # !JE1_q_a[7] & !YB1_fsm_dly_2_0_0_a2_0[2] & !YB1_fsm_dly_2_0_0_o2_x[2] # !WB95L2;
|
| 24311 |
|
|
|
| 24312 |
|
|
|
| 24313 |
|
|
--YB1_ext_ctl_2_0_0_a3_1_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a3_1_x[2]
|
| 24314 |
|
|
--operation mode is normal
|
| 24315 |
|
|
|
| 24316 |
|
|
YB1_ext_ctl_2_0_0_a3_1_x[2] = KE1_q_a[2] & KE1_q_a[3] & KE1_q_a[4];
|
| 24317 |
|
|
|
| 24318 |
|
|
|
| 24319 |
|
|
--YB1_ext_ctl_2_i_m3_0_0_Z[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_0_Z[0]
|
| 24320 |
|
|
--operation mode is normal
|
| 24321 |
|
|
|
| 24322 |
|
|
YB1_ext_ctl_2_i_m3_0_0_Z[0] = !KE1_q_a[4] & YB1_ext_ctl_2_i_m3_0_0_a[0] # !KE1_q_a[2] & KE1_q_a[5];
|
| 24323 |
|
|
|
| 24324 |
|
|
|
| 24325 |
|
|
--YB1_ext_ctl_2_i_m3_0_2_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_2_a[0]
|
| 24326 |
|
|
--operation mode is normal
|
| 24327 |
|
|
|
| 24328 |
|
|
YB1_ext_ctl_2_i_m3_0_2_a[0] = YB1_cmp_ctl_2_0_0_a2_0[0] & !WB05L2 & YB1_alu_func_2_0_0_o2_x[3] # !YB1_ext_ctl_2_0_0_a2_2_x[2] # !YB1_cmp_ctl_2_0_0_a2_0[0] & YB1_alu_func_2_0_0_o2_x[3] # !YB1_ext_ctl_2_0_0_a2_2_x[2];
|
| 24329 |
|
|
|
| 24330 |
|
|
|
| 24331 |
|
|
--YB1_muxa_ctl_2_0_0_a2_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a2_x[1]
|
| 24332 |
|
|
--operation mode is normal
|
| 24333 |
|
|
|
| 24334 |
|
|
YB1_muxa_ctl_2_0_0_a2_x[1] = !KE1_q_a[4] & KE1_q_a[2];
|
| 24335 |
|
|
|
| 24336 |
|
|
|
| 24337 |
|
|
--YB1_muxa_ctl_2_0_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_0_a[1]
|
| 24338 |
|
|
--operation mode is normal
|
| 24339 |
|
|
|
| 24340 |
|
|
YB1_muxa_ctl_2_0_0_0_a[1] = !KE1_q_a[4] & WB75L2 & YB1_cmp_ctl_2_0_0_a2_0[0] # YB1_cmp_ctl_2_0_0_a2_1[0];
|
| 24341 |
|
|
|
| 24342 |
|
|
|
| 24343 |
|
|
--FD1_r_rdaddress_a[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[4]
|
| 24344 |
|
|
--operation mode is normal
|
| 24345 |
|
|
|
| 24346 |
|
|
FD1_r_rdaddress_a[4]_lut_out = KE1_q_a[1];
|
| 24347 |
|
|
FD1_r_rdaddress_a[4] = DFFEAS(FD1_r_rdaddress_a[4]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 24348 |
|
|
|
| 24349 |
|
|
|
| 24350 |
|
|
--FD1_un14_qa_NE_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qa_NE_1
|
| 24351 |
|
|
--operation mode is normal
|
| 24352 |
|
|
|
| 24353 |
|
|
FD1_un14_qa_NE_1 = FD1_r_rdaddress_a[1] & FD1_r_rdaddress_a[0] $ FD1_r_wraddress[0] # !FD1_r_wraddress[1] # !FD1_r_rdaddress_a[1] & FD1_r_wraddress[1] # FD1_r_rdaddress_a[0] $ FD1_r_wraddress[0];
|
| 24354 |
|
|
|
| 24355 |
|
|
|
| 24356 |
|
|
--FD1_un14_qa_NE_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qa_NE_a
|
| 24357 |
|
|
--operation mode is normal
|
| 24358 |
|
|
|
| 24359 |
|
|
FD1_un14_qa_NE_a = FD1_r_rdaddress_a[2] & FD1_r_rdaddress_a[3] $ FD1_r_wraddress[3] # !FD1_r_wraddress[2] # !FD1_r_rdaddress_a[2] & FD1_r_wraddress[2] # FD1_r_rdaddress_a[3] $ FD1_r_wraddress[3];
|
| 24360 |
|
|
|
| 24361 |
|
|
|
| 24362 |
|
|
--FD1_un23_qa_i_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un23_qa_i_0_a2
|
| 24363 |
|
|
--operation mode is normal
|
| 24364 |
|
|
|
| 24365 |
|
|
FD1_un23_qa_i_0_a2 = !FD1_r_rdaddress_a[4] & !FD1_r_rdaddress_a[0] & !FD1_r_rdaddress_a[1] & FD1_un23_qa_i_0_a2_a;
|
| 24366 |
|
|
|
| 24367 |
|
|
|
| 24368 |
|
|
--FD1_N_14_i_0_s2_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_14_i_0_s2_a
|
| 24369 |
|
|
--operation mode is normal
|
| 24370 |
|
|
|
| 24371 |
|
|
FD1_N_14_i_0_s2_a = MC1_wb_we_o_0 & !WD1_un30_mux_fw & !YD1_un17_mux_fw_NE # !FD1_r_wren;
|
| 24372 |
|
|
|
| 24373 |
|
|
|
| 24374 |
|
|
--FD1_r_rdaddress_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[0]
|
| 24375 |
|
|
--operation mode is normal
|
| 24376 |
|
|
|
| 24377 |
|
|
FD1_r_rdaddress_a[0]_lut_out = JE1_q_a[5];
|
| 24378 |
|
|
FD1_r_rdaddress_a[0] = DFFEAS(FD1_r_rdaddress_a[0]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 24379 |
|
|
|
| 24380 |
|
|
|
| 24381 |
|
|
--FD1_r_rdaddress_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[1]
|
| 24382 |
|
|
--operation mode is normal
|
| 24383 |
|
|
|
| 24384 |
|
|
FD1_r_rdaddress_a[1]_lut_out = JE1_q_a[6];
|
| 24385 |
|
|
FD1_r_rdaddress_a[1] = DFFEAS(FD1_r_rdaddress_a[1]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 24386 |
|
|
|
| 24387 |
|
|
|
| 24388 |
|
|
--FD1_r_rdaddress_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[2]
|
| 24389 |
|
|
--operation mode is normal
|
| 24390 |
|
|
|
| 24391 |
|
|
FD1_r_rdaddress_a[2]_lut_out = JE1_q_a[7];
|
| 24392 |
|
|
FD1_r_rdaddress_a[2] = DFFEAS(FD1_r_rdaddress_a[2]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 24393 |
|
|
|
| 24394 |
|
|
|
| 24395 |
|
|
--FD1_r_rdaddress_a[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[3]
|
| 24396 |
|
|
--operation mode is normal
|
| 24397 |
|
|
|
| 24398 |
|
|
FD1_r_rdaddress_a[3]_lut_out = KE1_q_a[0];
|
| 24399 |
|
|
FD1_r_rdaddress_a[3] = DFFEAS(FD1_r_rdaddress_a[3]_lut_out, E1__clk0, VCC, , !AD1_CurrState_Sreg0_2, , , , );
|
| 24400 |
|
|
|
| 24401 |
|
|
|
| 24402 |
|
|
--YD1_un1_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un1_mux_fw_NE_1
|
| 24403 |
|
|
--operation mode is normal
|
| 24404 |
|
|
|
| 24405 |
|
|
YD1_un1_mux_fw_NE_1 = ED1_r32_o_22 & ED1_r32_o_21 $ MB1_r5_o_0 # !MB1_r5_o_1 # !ED1_r32_o_22 & MB1_r5_o_1 # ED1_r32_o_21 $ MB1_r5_o_0;
|
| 24406 |
|
|
|
| 24407 |
|
|
|
| 24408 |
|
|
--YD1_un1_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un1_mux_fw_NE_a
|
| 24409 |
|
|
--operation mode is normal
|
| 24410 |
|
|
|
| 24411 |
|
|
YD1_un1_mux_fw_NE_a = ED1_r32_o_23 & ED1_r32_o_24 $ MB1_r5_o_3 # !MB1_r5_o_2 # !ED1_r32_o_23 & MB1_r5_o_2 # ED1_r32_o_24 $ MB1_r5_o_3;
|
| 24412 |
|
|
|
| 24413 |
|
|
|
| 24414 |
|
|
--GD1_dout_iv_1_a[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[10]
|
| 24415 |
|
|
--operation mode is normal
|
| 24416 |
|
|
|
| 24417 |
|
|
GD1_dout_iv_1_a[10] = FD1_r_data_10 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_8 # !FD1_r_data_10 & !ZD1_mux_fw_1 # !AB1_r32_o_8;
|
| 24418 |
|
|
|
| 24419 |
|
|
|
| 24420 |
|
|
--LD1_q_b[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[10]
|
| 24421 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24422 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24423 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24424 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24425 |
|
|
LD1_q_b[10]_PORT_A_data_in = FD1_wb_o_10;
|
| 24426 |
|
|
LD1_q_b[10]_PORT_A_data_in_reg = DFFE(LD1_q_b[10]_PORT_A_data_in, LD1_q_b[10]_clock_0, , , );
|
| 24427 |
|
|
LD1_q_b[10]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24428 |
|
|
LD1_q_b[10]_PORT_A_address_reg = DFFE(LD1_q_b[10]_PORT_A_address, LD1_q_b[10]_clock_0, , , );
|
| 24429 |
|
|
LD1_q_b[10]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24430 |
|
|
LD1_q_b[10]_PORT_B_address_reg = DFFE(LD1_q_b[10]_PORT_B_address, LD1_q_b[10]_clock_1, , , );
|
| 24431 |
|
|
LD1_q_b[10]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24432 |
|
|
LD1_q_b[10]_PORT_A_write_enable_reg = DFFE(LD1_q_b[10]_PORT_A_write_enable, LD1_q_b[10]_clock_0, , , );
|
| 24433 |
|
|
LD1_q_b[10]_PORT_B_read_enable = VCC;
|
| 24434 |
|
|
LD1_q_b[10]_PORT_B_read_enable_reg = DFFE(LD1_q_b[10]_PORT_B_read_enable, LD1_q_b[10]_clock_1, , , );
|
| 24435 |
|
|
LD1_q_b[10]_clock_0 = E1__clk0;
|
| 24436 |
|
|
LD1_q_b[10]_clock_1 = E1__clk0;
|
| 24437 |
|
|
LD1_q_b[10]_PORT_B_data_out = MEMORY(LD1_q_b[10]_PORT_A_data_in_reg, , LD1_q_b[10]_PORT_A_address_reg, LD1_q_b[10]_PORT_B_address_reg, LD1_q_b[10]_PORT_A_write_enable_reg, LD1_q_b[10]_PORT_B_read_enable_reg, , , LD1_q_b[10]_clock_0, LD1_q_b[10]_clock_1, , , , );
|
| 24438 |
|
|
LD1_q_b[10] = LD1_q_b[10]_PORT_B_data_out[0];
|
| 24439 |
|
|
|
| 24440 |
|
|
|
| 24441 |
|
|
--GD1_dout_iv_1_a[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[15]
|
| 24442 |
|
|
--operation mode is normal
|
| 24443 |
|
|
|
| 24444 |
|
|
GD1_dout_iv_1_a[15] = FD1_r_data_15 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_13 # !FD1_r_data_15 & !ZD1_mux_fw_1 # !AB1_r32_o_13;
|
| 24445 |
|
|
|
| 24446 |
|
|
|
| 24447 |
|
|
--LD1_q_b[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[15]
|
| 24448 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24449 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24450 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24451 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24452 |
|
|
LD1_q_b[15]_PORT_A_data_in = FD1_wb_o_15;
|
| 24453 |
|
|
LD1_q_b[15]_PORT_A_data_in_reg = DFFE(LD1_q_b[15]_PORT_A_data_in, LD1_q_b[15]_clock_0, , , );
|
| 24454 |
|
|
LD1_q_b[15]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24455 |
|
|
LD1_q_b[15]_PORT_A_address_reg = DFFE(LD1_q_b[15]_PORT_A_address, LD1_q_b[15]_clock_0, , , );
|
| 24456 |
|
|
LD1_q_b[15]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24457 |
|
|
LD1_q_b[15]_PORT_B_address_reg = DFFE(LD1_q_b[15]_PORT_B_address, LD1_q_b[15]_clock_1, , , );
|
| 24458 |
|
|
LD1_q_b[15]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24459 |
|
|
LD1_q_b[15]_PORT_A_write_enable_reg = DFFE(LD1_q_b[15]_PORT_A_write_enable, LD1_q_b[15]_clock_0, , , );
|
| 24460 |
|
|
LD1_q_b[15]_PORT_B_read_enable = VCC;
|
| 24461 |
|
|
LD1_q_b[15]_PORT_B_read_enable_reg = DFFE(LD1_q_b[15]_PORT_B_read_enable, LD1_q_b[15]_clock_1, , , );
|
| 24462 |
|
|
LD1_q_b[15]_clock_0 = E1__clk0;
|
| 24463 |
|
|
LD1_q_b[15]_clock_1 = E1__clk0;
|
| 24464 |
|
|
LD1_q_b[15]_PORT_B_data_out = MEMORY(LD1_q_b[15]_PORT_A_data_in_reg, , LD1_q_b[15]_PORT_A_address_reg, LD1_q_b[15]_PORT_B_address_reg, LD1_q_b[15]_PORT_A_write_enable_reg, LD1_q_b[15]_PORT_B_read_enable_reg, , , LD1_q_b[15]_clock_0, LD1_q_b[15]_clock_1, , , , );
|
| 24465 |
|
|
LD1_q_b[15] = LD1_q_b[15]_PORT_B_data_out[0];
|
| 24466 |
|
|
|
| 24467 |
|
|
|
| 24468 |
|
|
--F1_cmd[15] is mips_sys:isys|mips_dvc:imips_dvc|cmd[15]
|
| 24469 |
|
|
--operation mode is normal
|
| 24470 |
|
|
|
| 24471 |
|
|
F1_cmd[15]_lut_out = CB1_r32_o_15;
|
| 24472 |
|
|
F1_cmd[15] = DFFEAS(F1_cmd[15]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 24473 |
|
|
|
| 24474 |
|
|
|
| 24475 |
|
|
--GD1_dout_iv_1_a[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[27]
|
| 24476 |
|
|
--operation mode is normal
|
| 24477 |
|
|
|
| 24478 |
|
|
GD1_dout_iv_1_a[27] = FD1_r_data_27 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_25 # !FD1_r_data_27 & !ZD1_mux_fw_1 # !AB1_r32_o_25;
|
| 24479 |
|
|
|
| 24480 |
|
|
|
| 24481 |
|
|
--LD1_q_b[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[27]
|
| 24482 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24483 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24484 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24485 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24486 |
|
|
LD1_q_b[27]_PORT_A_data_in = FD1_wb_o_27;
|
| 24487 |
|
|
LD1_q_b[27]_PORT_A_data_in_reg = DFFE(LD1_q_b[27]_PORT_A_data_in, LD1_q_b[27]_clock_0, , , );
|
| 24488 |
|
|
LD1_q_b[27]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24489 |
|
|
LD1_q_b[27]_PORT_A_address_reg = DFFE(LD1_q_b[27]_PORT_A_address, LD1_q_b[27]_clock_0, , , );
|
| 24490 |
|
|
LD1_q_b[27]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24491 |
|
|
LD1_q_b[27]_PORT_B_address_reg = DFFE(LD1_q_b[27]_PORT_B_address, LD1_q_b[27]_clock_1, , , );
|
| 24492 |
|
|
LD1_q_b[27]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24493 |
|
|
LD1_q_b[27]_PORT_A_write_enable_reg = DFFE(LD1_q_b[27]_PORT_A_write_enable, LD1_q_b[27]_clock_0, , , );
|
| 24494 |
|
|
LD1_q_b[27]_PORT_B_read_enable = VCC;
|
| 24495 |
|
|
LD1_q_b[27]_PORT_B_read_enable_reg = DFFE(LD1_q_b[27]_PORT_B_read_enable, LD1_q_b[27]_clock_1, , , );
|
| 24496 |
|
|
LD1_q_b[27]_clock_0 = E1__clk0;
|
| 24497 |
|
|
LD1_q_b[27]_clock_1 = E1__clk0;
|
| 24498 |
|
|
LD1_q_b[27]_PORT_B_data_out = MEMORY(LD1_q_b[27]_PORT_A_data_in_reg, , LD1_q_b[27]_PORT_A_address_reg, LD1_q_b[27]_PORT_B_address_reg, LD1_q_b[27]_PORT_A_write_enable_reg, LD1_q_b[27]_PORT_B_read_enable_reg, , , LD1_q_b[27]_clock_0, LD1_q_b[27]_clock_1, , , , );
|
| 24499 |
|
|
LD1_q_b[27] = LD1_q_b[27]_PORT_B_data_out[0];
|
| 24500 |
|
|
|
| 24501 |
|
|
|
| 24502 |
|
|
--F1_cmd[27] is mips_sys:isys|mips_dvc:imips_dvc|cmd[27]
|
| 24503 |
|
|
--operation mode is normal
|
| 24504 |
|
|
|
| 24505 |
|
|
F1_cmd[27]_lut_out = CB1_r32_o_27;
|
| 24506 |
|
|
F1_cmd[27] = DFFEAS(F1_cmd[27]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 24507 |
|
|
|
| 24508 |
|
|
|
| 24509 |
|
|
--GD1_dout_iv_1_a[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[19]
|
| 24510 |
|
|
--operation mode is normal
|
| 24511 |
|
|
|
| 24512 |
|
|
GD1_dout_iv_1_a[19] = FD1_r_data_19 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_17 # !FD1_r_data_19 & !ZD1_mux_fw_1 # !AB1_r32_o_17;
|
| 24513 |
|
|
|
| 24514 |
|
|
|
| 24515 |
|
|
--LD1_q_b[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[19]
|
| 24516 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24517 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24518 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24519 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24520 |
|
|
LD1_q_b[19]_PORT_A_data_in = FD1_wb_o_19;
|
| 24521 |
|
|
LD1_q_b[19]_PORT_A_data_in_reg = DFFE(LD1_q_b[19]_PORT_A_data_in, LD1_q_b[19]_clock_0, , , );
|
| 24522 |
|
|
LD1_q_b[19]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24523 |
|
|
LD1_q_b[19]_PORT_A_address_reg = DFFE(LD1_q_b[19]_PORT_A_address, LD1_q_b[19]_clock_0, , , );
|
| 24524 |
|
|
LD1_q_b[19]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24525 |
|
|
LD1_q_b[19]_PORT_B_address_reg = DFFE(LD1_q_b[19]_PORT_B_address, LD1_q_b[19]_clock_1, , , );
|
| 24526 |
|
|
LD1_q_b[19]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24527 |
|
|
LD1_q_b[19]_PORT_A_write_enable_reg = DFFE(LD1_q_b[19]_PORT_A_write_enable, LD1_q_b[19]_clock_0, , , );
|
| 24528 |
|
|
LD1_q_b[19]_PORT_B_read_enable = VCC;
|
| 24529 |
|
|
LD1_q_b[19]_PORT_B_read_enable_reg = DFFE(LD1_q_b[19]_PORT_B_read_enable, LD1_q_b[19]_clock_1, , , );
|
| 24530 |
|
|
LD1_q_b[19]_clock_0 = E1__clk0;
|
| 24531 |
|
|
LD1_q_b[19]_clock_1 = E1__clk0;
|
| 24532 |
|
|
LD1_q_b[19]_PORT_B_data_out = MEMORY(LD1_q_b[19]_PORT_A_data_in_reg, , LD1_q_b[19]_PORT_A_address_reg, LD1_q_b[19]_PORT_B_address_reg, LD1_q_b[19]_PORT_A_write_enable_reg, LD1_q_b[19]_PORT_B_read_enable_reg, , , LD1_q_b[19]_clock_0, LD1_q_b[19]_clock_1, , , , );
|
| 24533 |
|
|
LD1_q_b[19] = LD1_q_b[19]_PORT_B_data_out[0];
|
| 24534 |
|
|
|
| 24535 |
|
|
|
| 24536 |
|
|
--VD1_count[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[1]
|
| 24537 |
|
|
--operation mode is arithmetic
|
| 24538 |
|
|
|
| 24539 |
|
|
VD1_count[1]_carry_eqn = VD1_count_cout[0];
|
| 24540 |
|
|
VD1_count[1]_lut_out = VD1_count[1] $ (VD1_count[1]_carry_eqn);
|
| 24541 |
|
|
VD1_count[1] = DFFEAS(VD1_count[1]_lut_out, E1__clk0, VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
|
| 24542 |
|
|
|
| 24543 |
|
|
--VD1_count_cout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[1]
|
| 24544 |
|
|
--operation mode is arithmetic
|
| 24545 |
|
|
|
| 24546 |
|
|
VD1_count_cout[1] = CARRY(!VD1_count_cout[0] # !VD1_count[1]);
|
| 24547 |
|
|
|
| 24548 |
|
|
|
| 24549 |
|
|
--VD1_over_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_29
|
| 24550 |
|
|
--operation mode is arithmetic
|
| 24551 |
|
|
|
| 24552 |
|
|
VD1_over_carry_29 = CARRY(VD1_b_o_iv_29 & !VD1_over_carry_28 # !PD1_a_o_29 # !VD1_b_o_iv_29 & !PD1_a_o_29 & !VD1_over_carry_28);
|
| 24553 |
|
|
|
| 24554 |
|
|
|
| 24555 |
|
|
--VD1_eqz_2_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_16
|
| 24556 |
|
|
--operation mode is normal
|
| 24557 |
|
|
|
| 24558 |
|
|
VD1_eqz_2_16 = !VD1_hilo[32] & !VD1_hilo_37 & !VD1_hilo_33;
|
| 24559 |
|
|
|
| 24560 |
|
|
|
| 24561 |
|
|
--VD1_eqz_2_27_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_27_a
|
| 24562 |
|
|
--operation mode is normal
|
| 24563 |
|
|
|
| 24564 |
|
|
VD1_eqz_2_27_a = !VD1_hilo_34 & !VD1_hilo_36 & !VD1_hilo_46 & !VD1_hilo_49;
|
| 24565 |
|
|
|
| 24566 |
|
|
|
| 24567 |
|
|
--VD1_eqz_2_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_19
|
| 24568 |
|
|
--operation mode is normal
|
| 24569 |
|
|
|
| 24570 |
|
|
VD1_eqz_2_19 = !VD1_hilo_41 & !VD1_hilo_44 & !VD1_hilo_62 & !VD1_hilo_63;
|
| 24571 |
|
|
|
| 24572 |
|
|
|
| 24573 |
|
|
--VD1_eqz_2_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_20
|
| 24574 |
|
|
--operation mode is normal
|
| 24575 |
|
|
|
| 24576 |
|
|
VD1_eqz_2_20 = !VD1_hilo_55 & !VD1_hilo_60 & !VD1_hilo_58 & !VD1_hilo_61;
|
| 24577 |
|
|
|
| 24578 |
|
|
|
| 24579 |
|
|
--VD1_eqz_2_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_22
|
| 24580 |
|
|
--operation mode is normal
|
| 24581 |
|
|
|
| 24582 |
|
|
VD1_eqz_2_22 = !VD1_hilo_42 & !VD1_hilo_43 & !VD1_hilo_56 & !VD1_hilo[64];
|
| 24583 |
|
|
|
| 24584 |
|
|
|
| 24585 |
|
|
--VD1_eqz_2_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_23
|
| 24586 |
|
|
--operation mode is normal
|
| 24587 |
|
|
|
| 24588 |
|
|
VD1_eqz_2_23 = !VD1_hilo_54 & !VD1_hilo_57 & !VD1_hilo_47 & !VD1_hilo_48;
|
| 24589 |
|
|
|
| 24590 |
|
|
|
| 24591 |
|
|
--VD1_eqop2_2_NE_121 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_121
|
| 24592 |
|
|
--operation mode is normal
|
| 24593 |
|
|
|
| 24594 |
|
|
VD1_eqop2_2_NE_121 = VD1_op2_reged[26] & VD1_op2_reged[10] $ VD1_hilo_42 # !VD1_hilo_58 # !VD1_op2_reged[26] & VD1_hilo_58 # VD1_op2_reged[10] $ VD1_hilo_42;
|
| 24595 |
|
|
|
| 24596 |
|
|
|
| 24597 |
|
|
--VD1_eqop2_2_NE_123 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_123
|
| 24598 |
|
|
--operation mode is normal
|
| 24599 |
|
|
|
| 24600 |
|
|
VD1_eqop2_2_NE_123 = VD1_op2_reged[28] & VD1_op2_reged[12] $ VD1_hilo_44 # !VD1_hilo_60 # !VD1_op2_reged[28] & VD1_hilo_60 # VD1_op2_reged[12] $ VD1_hilo_44;
|
| 24601 |
|
|
|
| 24602 |
|
|
|
| 24603 |
|
|
--VD1_eqop2_2_NE_122 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_122
|
| 24604 |
|
|
--operation mode is normal
|
| 24605 |
|
|
|
| 24606 |
|
|
VD1_eqop2_2_NE_122 = VD1_op2_reged[27] & VD1_op2_reged[11] $ VD1_hilo_43 # !VD1_hilo_59 # !VD1_op2_reged[27] & VD1_hilo_59 # VD1_op2_reged[11] $ VD1_hilo_43;
|
| 24607 |
|
|
|
| 24608 |
|
|
|
| 24609 |
|
|
--VD1_eqop2_2_NE_11_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_11_a
|
| 24610 |
|
|
--operation mode is normal
|
| 24611 |
|
|
|
| 24612 |
|
|
VD1_eqop2_2_NE_11_a = VD1_op2_reged[9] & VD1_op2_reged[25] $ VD1_hilo_57 # !VD1_hilo_41 # !VD1_op2_reged[9] & VD1_hilo_41 # VD1_op2_reged[25] $ VD1_hilo_57;
|
| 24613 |
|
|
|
| 24614 |
|
|
|
| 24615 |
|
|
--VD1_eqop2_2_NE_114 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_114
|
| 24616 |
|
|
--operation mode is normal
|
| 24617 |
|
|
|
| 24618 |
|
|
VD1_eqop2_2_NE_114 = VD1_op2_reged[19] & VD1_op2_reged[3] $ VD1_hilo_35 # !VD1_hilo_51 # !VD1_op2_reged[19] & VD1_hilo_51 # VD1_op2_reged[3] $ VD1_hilo_35;
|
| 24619 |
|
|
|
| 24620 |
|
|
|
| 24621 |
|
|
--VD1_eqop2_2_NE_115_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_115_0
|
| 24622 |
|
|
--operation mode is normal
|
| 24623 |
|
|
|
| 24624 |
|
|
VD1_eqop2_2_NE_115_0 = VD1_op2_reged[4] & VD1_op2_reged[20] $ VD1_hilo_52 # !VD1_hilo_36 # !VD1_op2_reged[4] & VD1_hilo_36 # VD1_op2_reged[20] $ VD1_hilo_52;
|
| 24625 |
|
|
|
| 24626 |
|
|
|
| 24627 |
|
|
--VD1_eqop2_2_NE_112 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_112
|
| 24628 |
|
|
--operation mode is normal
|
| 24629 |
|
|
|
| 24630 |
|
|
VD1_eqop2_2_NE_112 = VD1_op2_reged[17] & VD1_op2_reged[1] $ VD1_hilo_33 # !VD1_hilo_49 # !VD1_op2_reged[17] & VD1_hilo_49 # VD1_op2_reged[1] $ VD1_hilo_33;
|
| 24631 |
|
|
|
| 24632 |
|
|
|
| 24633 |
|
|
--VD1_eqop2_2_NE_113 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_113
|
| 24634 |
|
|
--operation mode is normal
|
| 24635 |
|
|
|
| 24636 |
|
|
VD1_eqop2_2_NE_113 = VD1_op2_reged[18] & VD1_op2_reged[2] $ VD1_hilo_34 # !VD1_hilo_50 # !VD1_op2_reged[18] & VD1_hilo_50 # VD1_op2_reged[2] $ VD1_hilo_34;
|
| 24637 |
|
|
|
| 24638 |
|
|
|
| 24639 |
|
|
--VD1_eqop2_2_NE_118 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_118
|
| 24640 |
|
|
--operation mode is normal
|
| 24641 |
|
|
|
| 24642 |
|
|
VD1_eqop2_2_NE_118 = VD1_op2_reged[23] & VD1_op2_reged[7] $ VD1_hilo_39 # !VD1_hilo_55 # !VD1_op2_reged[23] & VD1_hilo_55 # VD1_op2_reged[7] $ VD1_hilo_39;
|
| 24643 |
|
|
|
| 24644 |
|
|
|
| 24645 |
|
|
--VD1_eqop2_2_NE_119 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_119
|
| 24646 |
|
|
--operation mode is normal
|
| 24647 |
|
|
|
| 24648 |
|
|
VD1_eqop2_2_NE_119 = VD1_op2_reged[24] & VD1_op2_reged[8] $ VD1_hilo_40 # !VD1_hilo_56 # !VD1_op2_reged[24] & VD1_hilo_56 # VD1_op2_reged[8] $ VD1_hilo_40;
|
| 24649 |
|
|
|
| 24650 |
|
|
|
| 24651 |
|
|
--VD1_eqop2_2_NE_116 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_116
|
| 24652 |
|
|
--operation mode is normal
|
| 24653 |
|
|
|
| 24654 |
|
|
VD1_eqop2_2_NE_116 = VD1_op2_reged[21] & VD1_op2_reged[5] $ VD1_hilo_37 # !VD1_hilo_53 # !VD1_op2_reged[21] & VD1_hilo_53 # VD1_op2_reged[5] $ VD1_hilo_37;
|
| 24655 |
|
|
|
| 24656 |
|
|
|
| 24657 |
|
|
--VD1_eqop2_2_NE_117 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_117
|
| 24658 |
|
|
--operation mode is normal
|
| 24659 |
|
|
|
| 24660 |
|
|
VD1_eqop2_2_NE_117 = VD1_op2_reged[22] & VD1_op2_reged[6] $ VD1_hilo_38 # !VD1_hilo_54 # !VD1_op2_reged[22] & VD1_hilo_54 # VD1_op2_reged[6] $ VD1_hilo_38;
|
| 24661 |
|
|
|
| 24662 |
|
|
|
| 24663 |
|
|
--VD1_eqop2_2_NE_126 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_126
|
| 24664 |
|
|
--operation mode is normal
|
| 24665 |
|
|
|
| 24666 |
|
|
VD1_eqop2_2_NE_126 = VD1_op2_reged[31] & VD1_op2_reged[15] $ VD1_hilo_47 # !VD1_hilo_63 # !VD1_op2_reged[31] & VD1_hilo_63 # VD1_op2_reged[15] $ VD1_hilo_47;
|
| 24667 |
|
|
|
| 24668 |
|
|
|
| 24669 |
|
|
--VD1_eqop2_2_NE_124 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_124
|
| 24670 |
|
|
--operation mode is normal
|
| 24671 |
|
|
|
| 24672 |
|
|
VD1_eqop2_2_NE_124 = VD1_op2_reged[29] & VD1_op2_reged[13] $ VD1_hilo_45 # !VD1_hilo_61 # !VD1_op2_reged[29] & VD1_hilo_61 # VD1_op2_reged[13] $ VD1_hilo_45;
|
| 24673 |
|
|
|
| 24674 |
|
|
|
| 24675 |
|
|
--VD1_eqop2_2_NE_12_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_12_a
|
| 24676 |
|
|
--operation mode is normal
|
| 24677 |
|
|
|
| 24678 |
|
|
VD1_eqop2_2_NE_12_a = !VD1_eqop2_2_0 & VD1_eqop2_2_NE_125_i_a2 & VD1_op2_reged[16] $ !VD1_hilo_48;
|
| 24679 |
|
|
|
| 24680 |
|
|
|
| 24681 |
|
|
--VD1_nop2_reged[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[16]
|
| 24682 |
|
|
--operation mode is arithmetic
|
| 24683 |
|
|
|
| 24684 |
|
|
VD1_nop2_reged[16]_carry_eqn = VD1_nop2_reged_cout[14];
|
| 24685 |
|
|
VD1_nop2_reged[16] = VD1_op2_reged[16] $ VD1_nop2_reged[16]_carry_eqn;
|
| 24686 |
|
|
|
| 24687 |
|
|
--VD1_nop2_reged_cout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[16]
|
| 24688 |
|
|
--operation mode is arithmetic
|
| 24689 |
|
|
|
| 24690 |
|
|
VD1_nop2_reged_cout[16] = CARRY(!VD1_op2_reged[17] & !VD1_op2_reged[16] & !VD1_nop2_reged_cout[14]);
|
| 24691 |
|
|
|
| 24692 |
|
|
|
| 24693 |
|
|
--VD1_nop2_reged[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[15]
|
| 24694 |
|
|
--operation mode is arithmetic
|
| 24695 |
|
|
|
| 24696 |
|
|
VD1_nop2_reged[15]_carry_eqn = VD1_nop2_reged_cout[13];
|
| 24697 |
|
|
VD1_nop2_reged[15] = VD1_op2_reged[15] $ (VD1_op2_reged[14] # !VD1_nop2_reged[15]_carry_eqn);
|
| 24698 |
|
|
|
| 24699 |
|
|
--VD1_nop2_reged_cout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[15]
|
| 24700 |
|
|
--operation mode is arithmetic
|
| 24701 |
|
|
|
| 24702 |
|
|
VD1_nop2_reged_cout[15] = CARRY(VD1_op2_reged[15] # VD1_op2_reged[14] # !VD1_nop2_reged_cout[13]);
|
| 24703 |
|
|
|
| 24704 |
|
|
|
| 24705 |
|
|
--VD1_nop2_reged[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[17]
|
| 24706 |
|
|
--operation mode is arithmetic
|
| 24707 |
|
|
|
| 24708 |
|
|
VD1_nop2_reged[17]_carry_eqn = VD1_nop2_reged_cout[15];
|
| 24709 |
|
|
VD1_nop2_reged[17] = VD1_op2_reged[17] $ (VD1_op2_reged[16] # VD1_nop2_reged[17]_carry_eqn);
|
| 24710 |
|
|
|
| 24711 |
|
|
--VD1_nop2_reged_cout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[17]
|
| 24712 |
|
|
--operation mode is arithmetic
|
| 24713 |
|
|
|
| 24714 |
|
|
VD1_nop2_reged_cout[17] = CARRY(!VD1_op2_reged[17] & !VD1_op2_reged[16] & !VD1_nop2_reged_cout[15]);
|
| 24715 |
|
|
|
| 24716 |
|
|
|
| 24717 |
|
|
--VD1_nop2_reged[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[19]
|
| 24718 |
|
|
--operation mode is arithmetic
|
| 24719 |
|
|
|
| 24720 |
|
|
VD1_nop2_reged[19]_carry_eqn = VD1_nop2_reged_cout[17];
|
| 24721 |
|
|
VD1_nop2_reged[19] = VD1_op2_reged[19] $ (VD1_op2_reged[18] # !VD1_nop2_reged[19]_carry_eqn);
|
| 24722 |
|
|
|
| 24723 |
|
|
--VD1_nop2_reged_cout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[19]
|
| 24724 |
|
|
--operation mode is arithmetic
|
| 24725 |
|
|
|
| 24726 |
|
|
VD1_nop2_reged_cout[19] = CARRY(VD1_op2_reged[19] # VD1_op2_reged[18] # !VD1_nop2_reged_cout[17]);
|
| 24727 |
|
|
|
| 24728 |
|
|
|
| 24729 |
|
|
--VD1_nop2_reged[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[18]
|
| 24730 |
|
|
--operation mode is arithmetic
|
| 24731 |
|
|
|
| 24732 |
|
|
VD1_nop2_reged[18]_carry_eqn = VD1_nop2_reged_cout[16];
|
| 24733 |
|
|
VD1_nop2_reged[18] = VD1_op2_reged[18] $ !VD1_nop2_reged[18]_carry_eqn;
|
| 24734 |
|
|
|
| 24735 |
|
|
--VD1_nop2_reged_cout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[18]
|
| 24736 |
|
|
--operation mode is arithmetic
|
| 24737 |
|
|
|
| 24738 |
|
|
VD1_nop2_reged_cout[18] = CARRY(VD1_op2_reged[19] # VD1_op2_reged[18] # !VD1_nop2_reged_cout[16]);
|
| 24739 |
|
|
|
| 24740 |
|
|
|
| 24741 |
|
|
--VD1_nop2_reged[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[20]
|
| 24742 |
|
|
--operation mode is arithmetic
|
| 24743 |
|
|
|
| 24744 |
|
|
VD1_nop2_reged[20]_carry_eqn = VD1_nop2_reged_cout[18];
|
| 24745 |
|
|
VD1_nop2_reged[20] = VD1_op2_reged[20] $ VD1_nop2_reged[20]_carry_eqn;
|
| 24746 |
|
|
|
| 24747 |
|
|
--VD1_nop2_reged_cout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[20]
|
| 24748 |
|
|
--operation mode is arithmetic
|
| 24749 |
|
|
|
| 24750 |
|
|
VD1_nop2_reged_cout[20] = CARRY(!VD1_op2_reged[21] & !VD1_op2_reged[20] & !VD1_nop2_reged_cout[18]);
|
| 24751 |
|
|
|
| 24752 |
|
|
|
| 24753 |
|
|
--VD1_nop2_reged[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[21]
|
| 24754 |
|
|
--operation mode is arithmetic
|
| 24755 |
|
|
|
| 24756 |
|
|
VD1_nop2_reged[21]_carry_eqn = VD1_nop2_reged_cout[19];
|
| 24757 |
|
|
VD1_nop2_reged[21] = VD1_op2_reged[21] $ (VD1_op2_reged[20] # VD1_nop2_reged[21]_carry_eqn);
|
| 24758 |
|
|
|
| 24759 |
|
|
--VD1_nop2_reged_cout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[21]
|
| 24760 |
|
|
--operation mode is arithmetic
|
| 24761 |
|
|
|
| 24762 |
|
|
VD1_nop2_reged_cout[21] = CARRY(!VD1_op2_reged[21] & !VD1_op2_reged[20] & !VD1_nop2_reged_cout[19]);
|
| 24763 |
|
|
|
| 24764 |
|
|
|
| 24765 |
|
|
--VD1_nop2_reged[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[22]
|
| 24766 |
|
|
--operation mode is arithmetic
|
| 24767 |
|
|
|
| 24768 |
|
|
VD1_nop2_reged[22]_carry_eqn = VD1_nop2_reged_cout[20];
|
| 24769 |
|
|
VD1_nop2_reged[22] = VD1_op2_reged[22] $ !VD1_nop2_reged[22]_carry_eqn;
|
| 24770 |
|
|
|
| 24771 |
|
|
--VD1_nop2_reged_cout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[22]
|
| 24772 |
|
|
--operation mode is arithmetic
|
| 24773 |
|
|
|
| 24774 |
|
|
VD1_nop2_reged_cout[22] = CARRY(VD1_op2_reged[23] # VD1_op2_reged[22] # !VD1_nop2_reged_cout[20]);
|
| 24775 |
|
|
|
| 24776 |
|
|
|
| 24777 |
|
|
--VD1_nop2_reged[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[23]
|
| 24778 |
|
|
--operation mode is arithmetic
|
| 24779 |
|
|
|
| 24780 |
|
|
VD1_nop2_reged[23]_carry_eqn = VD1_nop2_reged_cout[21];
|
| 24781 |
|
|
VD1_nop2_reged[23] = VD1_op2_reged[23] $ (VD1_op2_reged[22] # !VD1_nop2_reged[23]_carry_eqn);
|
| 24782 |
|
|
|
| 24783 |
|
|
--VD1_nop2_reged_cout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[23]
|
| 24784 |
|
|
--operation mode is arithmetic
|
| 24785 |
|
|
|
| 24786 |
|
|
VD1_nop2_reged_cout[23] = CARRY(VD1_op2_reged[23] # VD1_op2_reged[22] # !VD1_nop2_reged_cout[21]);
|
| 24787 |
|
|
|
| 24788 |
|
|
|
| 24789 |
|
|
--VD1_nop2_reged[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[24]
|
| 24790 |
|
|
--operation mode is arithmetic
|
| 24791 |
|
|
|
| 24792 |
|
|
VD1_nop2_reged[24]_carry_eqn = VD1_nop2_reged_cout[22];
|
| 24793 |
|
|
VD1_nop2_reged[24] = VD1_op2_reged[24] $ VD1_nop2_reged[24]_carry_eqn;
|
| 24794 |
|
|
|
| 24795 |
|
|
--VD1_nop2_reged_cout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[24]
|
| 24796 |
|
|
--operation mode is arithmetic
|
| 24797 |
|
|
|
| 24798 |
|
|
VD1_nop2_reged_cout[24] = CARRY(!VD1_op2_reged[25] & !VD1_op2_reged[24] & !VD1_nop2_reged_cout[22]);
|
| 24799 |
|
|
|
| 24800 |
|
|
|
| 24801 |
|
|
--VD1_nop2_reged[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[13]
|
| 24802 |
|
|
--operation mode is arithmetic
|
| 24803 |
|
|
|
| 24804 |
|
|
VD1_nop2_reged[13]_carry_eqn = VD1_nop2_reged_cout[11];
|
| 24805 |
|
|
VD1_nop2_reged[13] = VD1_op2_reged[13] $ (VD1_op2_reged[12] # VD1_nop2_reged[13]_carry_eqn);
|
| 24806 |
|
|
|
| 24807 |
|
|
--VD1_nop2_reged_cout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[13]
|
| 24808 |
|
|
--operation mode is arithmetic
|
| 24809 |
|
|
|
| 24810 |
|
|
VD1_nop2_reged_cout[13] = CARRY(!VD1_op2_reged[13] & !VD1_op2_reged[12] & !VD1_nop2_reged_cout[11]);
|
| 24811 |
|
|
|
| 24812 |
|
|
|
| 24813 |
|
|
--VD1_nop2_reged[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[29]
|
| 24814 |
|
|
--operation mode is arithmetic
|
| 24815 |
|
|
|
| 24816 |
|
|
VD1_nop2_reged[29]_carry_eqn = VD1_nop2_reged_cout[27];
|
| 24817 |
|
|
VD1_nop2_reged[29] = VD1_op2_reged[29] $ (VD1_op2_reged[28] # VD1_nop2_reged[29]_carry_eqn);
|
| 24818 |
|
|
|
| 24819 |
|
|
--VD1_nop2_reged_cout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[29]
|
| 24820 |
|
|
--operation mode is arithmetic
|
| 24821 |
|
|
|
| 24822 |
|
|
VD1_nop2_reged_cout[29] = CARRY(!VD1_op2_reged[29] & !VD1_op2_reged[28] & !VD1_nop2_reged_cout[27]);
|
| 24823 |
|
|
|
| 24824 |
|
|
|
| 24825 |
|
|
--VD1_nop2_reged[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[14]
|
| 24826 |
|
|
--operation mode is arithmetic
|
| 24827 |
|
|
|
| 24828 |
|
|
VD1_nop2_reged[14]_carry_eqn = VD1_nop2_reged_cout[12];
|
| 24829 |
|
|
VD1_nop2_reged[14] = VD1_op2_reged[14] $ !VD1_nop2_reged[14]_carry_eqn;
|
| 24830 |
|
|
|
| 24831 |
|
|
--VD1_nop2_reged_cout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[14]
|
| 24832 |
|
|
--operation mode is arithmetic
|
| 24833 |
|
|
|
| 24834 |
|
|
VD1_nop2_reged_cout[14] = CARRY(VD1_op2_reged[15] # VD1_op2_reged[14] # !VD1_nop2_reged_cout[12]);
|
| 24835 |
|
|
|
| 24836 |
|
|
|
| 24837 |
|
|
--VD1_nop2_reged[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[26]
|
| 24838 |
|
|
--operation mode is arithmetic
|
| 24839 |
|
|
|
| 24840 |
|
|
VD1_nop2_reged[26]_carry_eqn = VD1_nop2_reged_cout[24];
|
| 24841 |
|
|
VD1_nop2_reged[26] = VD1_op2_reged[26] $ !VD1_nop2_reged[26]_carry_eqn;
|
| 24842 |
|
|
|
| 24843 |
|
|
--VD1_nop2_reged_cout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[26]
|
| 24844 |
|
|
--operation mode is arithmetic
|
| 24845 |
|
|
|
| 24846 |
|
|
VD1_nop2_reged_cout[26] = CARRY(VD1_op2_reged[27] # VD1_op2_reged[26] # !VD1_nop2_reged_cout[24]);
|
| 24847 |
|
|
|
| 24848 |
|
|
|
| 24849 |
|
|
--VD1_eqnop2_2_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_9
|
| 24850 |
|
|
--operation mode is normal
|
| 24851 |
|
|
|
| 24852 |
|
|
VD1_eqnop2_2_9 = VD1_hilo_41 $ VD1_nop2_reged[9];
|
| 24853 |
|
|
|
| 24854 |
|
|
|
| 24855 |
|
|
--VD1_eqnop2_2_NE_5_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_5_a
|
| 24856 |
|
|
--operation mode is normal
|
| 24857 |
|
|
|
| 24858 |
|
|
VD1_eqnop2_2_NE_5_a = VD1_hilo_42 & VD1_hilo_57 $ VD1_nop2_reged[25] # !VD1_nop2_reged[10] # !VD1_hilo_42 & VD1_nop2_reged[10] # VD1_hilo_57 $ VD1_nop2_reged[25];
|
| 24859 |
|
|
|
| 24860 |
|
|
|
| 24861 |
|
|
--VD1_nop2_reged[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[27]
|
| 24862 |
|
|
--operation mode is arithmetic
|
| 24863 |
|
|
|
| 24864 |
|
|
VD1_nop2_reged[27]_carry_eqn = VD1_nop2_reged_cout[25];
|
| 24865 |
|
|
VD1_nop2_reged[27] = VD1_op2_reged[27] $ (VD1_op2_reged[26] # !VD1_nop2_reged[27]_carry_eqn);
|
| 24866 |
|
|
|
| 24867 |
|
|
--VD1_nop2_reged_cout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[27]
|
| 24868 |
|
|
--operation mode is arithmetic
|
| 24869 |
|
|
|
| 24870 |
|
|
VD1_nop2_reged_cout[27] = CARRY(VD1_op2_reged[27] # VD1_op2_reged[26] # !VD1_nop2_reged_cout[25]);
|
| 24871 |
|
|
|
| 24872 |
|
|
|
| 24873 |
|
|
--VD1_eqnop2_2_NE_8_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_8_a
|
| 24874 |
|
|
--operation mode is normal
|
| 24875 |
|
|
|
| 24876 |
|
|
VD1_eqnop2_2_NE_8_a = VD1_hilo_43 $ VD1_nop2_reged[11];
|
| 24877 |
|
|
|
| 24878 |
|
|
|
| 24879 |
|
|
--VD1_eqnop2_2_NE_140_i_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_140_i_a2
|
| 24880 |
|
|
--operation mode is normal
|
| 24881 |
|
|
|
| 24882 |
|
|
VD1_eqnop2_2_NE_140_i_a2 = VD1_hilo_60 & VD1_nop2_reged[28] & VD1_hilo_44 $ !VD1_nop2_reged[12] # !VD1_hilo_60 & !VD1_nop2_reged[28] & VD1_hilo_44 $ !VD1_nop2_reged[12];
|
| 24883 |
|
|
|
| 24884 |
|
|
|
| 24885 |
|
|
--VD1_un59_hilo_add32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add32
|
| 24886 |
|
|
--operation mode is normal
|
| 24887 |
|
|
|
| 24888 |
|
|
VD1_un59_hilo_add32_carry_eqn = VD1_un59_hilo_carry_31;
|
| 24889 |
|
|
VD1_un59_hilo_add32 = VD1_hilo[64] $ VD1_op2_sign_reged $ !VD1_un59_hilo_add32_carry_eqn;
|
| 24890 |
|
|
|
| 24891 |
|
|
|
| 24892 |
|
|
--VD1_un50_hilo_add32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add32
|
| 24893 |
|
|
--operation mode is normal
|
| 24894 |
|
|
|
| 24895 |
|
|
VD1_un50_hilo_add32_carry_eqn = VD1_un50_hilo_carry_31;
|
| 24896 |
|
|
VD1_un50_hilo_add32 = VD1_hilo[64] $ VD1_nop2_reged[32] $ !VD1_un50_hilo_add32_carry_eqn;
|
| 24897 |
|
|
|
| 24898 |
|
|
|
| 24899 |
|
|
--VD1_hilo_15_3_i_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_3_i_a[63]
|
| 24900 |
|
|
--operation mode is normal
|
| 24901 |
|
|
|
| 24902 |
|
|
VD1_hilo_15_3_i_a[63] = VD1_sub_or_yn & !VD1_hilo[0] & !VD1_un59_hilo_add32 # !VD1_sub_or_yn & VD1_hilo[0] & !VD1_un50_hilo_add32;
|
| 24903 |
|
|
|
| 24904 |
|
|
|
| 24905 |
|
|
--GD1_dout_iv_1_a[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[16]
|
| 24906 |
|
|
--operation mode is normal
|
| 24907 |
|
|
|
| 24908 |
|
|
GD1_dout_iv_1_a[16] = FD1_r_data_16 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_14 # !FD1_r_data_16 & !ZD1_mux_fw_1 # !AB1_r32_o_14;
|
| 24909 |
|
|
|
| 24910 |
|
|
|
| 24911 |
|
|
--LD1_q_b[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[16]
|
| 24912 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24913 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24914 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24915 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24916 |
|
|
LD1_q_b[16]_PORT_A_data_in = FD1_wb_o_16;
|
| 24917 |
|
|
LD1_q_b[16]_PORT_A_data_in_reg = DFFE(LD1_q_b[16]_PORT_A_data_in, LD1_q_b[16]_clock_0, , , );
|
| 24918 |
|
|
LD1_q_b[16]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24919 |
|
|
LD1_q_b[16]_PORT_A_address_reg = DFFE(LD1_q_b[16]_PORT_A_address, LD1_q_b[16]_clock_0, , , );
|
| 24920 |
|
|
LD1_q_b[16]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24921 |
|
|
LD1_q_b[16]_PORT_B_address_reg = DFFE(LD1_q_b[16]_PORT_B_address, LD1_q_b[16]_clock_1, , , );
|
| 24922 |
|
|
LD1_q_b[16]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24923 |
|
|
LD1_q_b[16]_PORT_A_write_enable_reg = DFFE(LD1_q_b[16]_PORT_A_write_enable, LD1_q_b[16]_clock_0, , , );
|
| 24924 |
|
|
LD1_q_b[16]_PORT_B_read_enable = VCC;
|
| 24925 |
|
|
LD1_q_b[16]_PORT_B_read_enable_reg = DFFE(LD1_q_b[16]_PORT_B_read_enable, LD1_q_b[16]_clock_1, , , );
|
| 24926 |
|
|
LD1_q_b[16]_clock_0 = E1__clk0;
|
| 24927 |
|
|
LD1_q_b[16]_clock_1 = E1__clk0;
|
| 24928 |
|
|
LD1_q_b[16]_PORT_B_data_out = MEMORY(LD1_q_b[16]_PORT_A_data_in_reg, , LD1_q_b[16]_PORT_A_address_reg, LD1_q_b[16]_PORT_B_address_reg, LD1_q_b[16]_PORT_A_write_enable_reg, LD1_q_b[16]_PORT_B_read_enable_reg, , , LD1_q_b[16]_clock_0, LD1_q_b[16]_clock_1, , , , );
|
| 24929 |
|
|
LD1_q_b[16] = LD1_q_b[16]_PORT_B_data_out[0];
|
| 24930 |
|
|
|
| 24931 |
|
|
|
| 24932 |
|
|
--CD1_res_7_0_0_0_a[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_a[16]
|
| 24933 |
|
|
--operation mode is normal
|
| 24934 |
|
|
|
| 24935 |
|
|
CD1_res_7_0_0_0_a[16] = !DC1_ext_ctl_o_1 & !DC1_ext_ctl_o_2 & DC1_ext_ctl_o_0;
|
| 24936 |
|
|
|
| 24937 |
|
|
|
| 24938 |
|
|
--GD1_dout_iv_1_a[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[28]
|
| 24939 |
|
|
--operation mode is normal
|
| 24940 |
|
|
|
| 24941 |
|
|
GD1_dout_iv_1_a[28] = FD1_r_data_28 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_26 # !FD1_r_data_28 & !ZD1_mux_fw_1 # !AB1_r32_o_26;
|
| 24942 |
|
|
|
| 24943 |
|
|
|
| 24944 |
|
|
--LD1_q_b[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[28]
|
| 24945 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24946 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24947 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24948 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24949 |
|
|
LD1_q_b[28]_PORT_A_data_in = FD1_wb_o_28;
|
| 24950 |
|
|
LD1_q_b[28]_PORT_A_data_in_reg = DFFE(LD1_q_b[28]_PORT_A_data_in, LD1_q_b[28]_clock_0, , , );
|
| 24951 |
|
|
LD1_q_b[28]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24952 |
|
|
LD1_q_b[28]_PORT_A_address_reg = DFFE(LD1_q_b[28]_PORT_A_address, LD1_q_b[28]_clock_0, , , );
|
| 24953 |
|
|
LD1_q_b[28]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24954 |
|
|
LD1_q_b[28]_PORT_B_address_reg = DFFE(LD1_q_b[28]_PORT_B_address, LD1_q_b[28]_clock_1, , , );
|
| 24955 |
|
|
LD1_q_b[28]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24956 |
|
|
LD1_q_b[28]_PORT_A_write_enable_reg = DFFE(LD1_q_b[28]_PORT_A_write_enable, LD1_q_b[28]_clock_0, , , );
|
| 24957 |
|
|
LD1_q_b[28]_PORT_B_read_enable = VCC;
|
| 24958 |
|
|
LD1_q_b[28]_PORT_B_read_enable_reg = DFFE(LD1_q_b[28]_PORT_B_read_enable, LD1_q_b[28]_clock_1, , , );
|
| 24959 |
|
|
LD1_q_b[28]_clock_0 = E1__clk0;
|
| 24960 |
|
|
LD1_q_b[28]_clock_1 = E1__clk0;
|
| 24961 |
|
|
LD1_q_b[28]_PORT_B_data_out = MEMORY(LD1_q_b[28]_PORT_A_data_in_reg, , LD1_q_b[28]_PORT_A_address_reg, LD1_q_b[28]_PORT_B_address_reg, LD1_q_b[28]_PORT_A_write_enable_reg, LD1_q_b[28]_PORT_B_read_enable_reg, , , LD1_q_b[28]_clock_0, LD1_q_b[28]_clock_1, , , , );
|
| 24962 |
|
|
LD1_q_b[28] = LD1_q_b[28]_PORT_B_data_out[0];
|
| 24963 |
|
|
|
| 24964 |
|
|
|
| 24965 |
|
|
--GD1_dout_iv_1_a[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[23]
|
| 24966 |
|
|
--operation mode is normal
|
| 24967 |
|
|
|
| 24968 |
|
|
GD1_dout_iv_1_a[23] = FD1_r_data_23 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_21 # !FD1_r_data_23 & !ZD1_mux_fw_1 # !AB1_r32_o_21;
|
| 24969 |
|
|
|
| 24970 |
|
|
|
| 24971 |
|
|
--LD1_q_b[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[23]
|
| 24972 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 24973 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 24974 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 24975 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 24976 |
|
|
LD1_q_b[23]_PORT_A_data_in = FD1_wb_o_23;
|
| 24977 |
|
|
LD1_q_b[23]_PORT_A_data_in_reg = DFFE(LD1_q_b[23]_PORT_A_data_in, LD1_q_b[23]_clock_0, , , );
|
| 24978 |
|
|
LD1_q_b[23]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 24979 |
|
|
LD1_q_b[23]_PORT_A_address_reg = DFFE(LD1_q_b[23]_PORT_A_address, LD1_q_b[23]_clock_0, , , );
|
| 24980 |
|
|
LD1_q_b[23]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 24981 |
|
|
LD1_q_b[23]_PORT_B_address_reg = DFFE(LD1_q_b[23]_PORT_B_address, LD1_q_b[23]_clock_1, , , );
|
| 24982 |
|
|
LD1_q_b[23]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 24983 |
|
|
LD1_q_b[23]_PORT_A_write_enable_reg = DFFE(LD1_q_b[23]_PORT_A_write_enable, LD1_q_b[23]_clock_0, , , );
|
| 24984 |
|
|
LD1_q_b[23]_PORT_B_read_enable = VCC;
|
| 24985 |
|
|
LD1_q_b[23]_PORT_B_read_enable_reg = DFFE(LD1_q_b[23]_PORT_B_read_enable, LD1_q_b[23]_clock_1, , , );
|
| 24986 |
|
|
LD1_q_b[23]_clock_0 = E1__clk0;
|
| 24987 |
|
|
LD1_q_b[23]_clock_1 = E1__clk0;
|
| 24988 |
|
|
LD1_q_b[23]_PORT_B_data_out = MEMORY(LD1_q_b[23]_PORT_A_data_in_reg, , LD1_q_b[23]_PORT_A_address_reg, LD1_q_b[23]_PORT_B_address_reg, LD1_q_b[23]_PORT_A_write_enable_reg, LD1_q_b[23]_PORT_B_read_enable_reg, , , LD1_q_b[23]_clock_0, LD1_q_b[23]_clock_1, , , , );
|
| 24989 |
|
|
LD1_q_b[23] = LD1_q_b[23]_PORT_B_data_out[0];
|
| 24990 |
|
|
|
| 24991 |
|
|
|
| 24992 |
|
|
--GD1_dout_iv_1_a[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[24]
|
| 24993 |
|
|
--operation mode is normal
|
| 24994 |
|
|
|
| 24995 |
|
|
GD1_dout_iv_1_a[24] = FD1_r_data_24 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_22 # !FD1_r_data_24 & !ZD1_mux_fw_1 # !AB1_r32_o_22;
|
| 24996 |
|
|
|
| 24997 |
|
|
|
| 24998 |
|
|
--LD1_q_b[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[24]
|
| 24999 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 25000 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 25001 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 25002 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 25003 |
|
|
LD1_q_b[24]_PORT_A_data_in = FD1_wb_o_24;
|
| 25004 |
|
|
LD1_q_b[24]_PORT_A_data_in_reg = DFFE(LD1_q_b[24]_PORT_A_data_in, LD1_q_b[24]_clock_0, , , );
|
| 25005 |
|
|
LD1_q_b[24]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 25006 |
|
|
LD1_q_b[24]_PORT_A_address_reg = DFFE(LD1_q_b[24]_PORT_A_address, LD1_q_b[24]_clock_0, , , );
|
| 25007 |
|
|
LD1_q_b[24]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
|
| 25008 |
|
|
LD1_q_b[24]_PORT_B_address_reg = DFFE(LD1_q_b[24]_PORT_B_address, LD1_q_b[24]_clock_1, , , );
|
| 25009 |
|
|
LD1_q_b[24]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 25010 |
|
|
LD1_q_b[24]_PORT_A_write_enable_reg = DFFE(LD1_q_b[24]_PORT_A_write_enable, LD1_q_b[24]_clock_0, , , );
|
| 25011 |
|
|
LD1_q_b[24]_PORT_B_read_enable = VCC;
|
| 25012 |
|
|
LD1_q_b[24]_PORT_B_read_enable_reg = DFFE(LD1_q_b[24]_PORT_B_read_enable, LD1_q_b[24]_clock_1, , , );
|
| 25013 |
|
|
LD1_q_b[24]_clock_0 = E1__clk0;
|
| 25014 |
|
|
LD1_q_b[24]_clock_1 = E1__clk0;
|
| 25015 |
|
|
LD1_q_b[24]_PORT_B_data_out = MEMORY(LD1_q_b[24]_PORT_A_data_in_reg, , LD1_q_b[24]_PORT_A_address_reg, LD1_q_b[24]_PORT_B_address_reg, LD1_q_b[24]_PORT_A_write_enable_reg, LD1_q_b[24]_PORT_B_read_enable_reg, , , LD1_q_b[24]_clock_0, LD1_q_b[24]_clock_1, , , , );
|
| 25016 |
|
|
LD1_q_b[24] = LD1_q_b[24]_PORT_B_data_out[0];
|
| 25017 |
|
|
|
| 25018 |
|
|
|
| 25019 |
|
|
--F1_cmd[24] is mips_sys:isys|mips_dvc:imips_dvc|cmd[24]
|
| 25020 |
|
|
--operation mode is normal
|
| 25021 |
|
|
|
| 25022 |
|
|
F1_cmd[24]_lut_out = CB1_r32_o_24;
|
| 25023 |
|
|
F1_cmd[24] = DFFEAS(F1_cmd[24]_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );
|
| 25024 |
|
|
|
| 25025 |
|
|
|
| 25026 |
|
|
--VD1_un59_hilo_add16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add16
|
| 25027 |
|
|
--operation mode is arithmetic
|
| 25028 |
|
|
|
| 25029 |
|
|
VD1_un59_hilo_add16_carry_eqn = VD1_un59_hilo_carry_15;
|
| 25030 |
|
|
VD1_un59_hilo_add16 = VD1_hilo_48 $ VD1_op2_reged[16] $ !VD1_un59_hilo_add16_carry_eqn;
|
| 25031 |
|
|
|
| 25032 |
|
|
--VD1_un59_hilo_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_16
|
| 25033 |
|
|
--operation mode is arithmetic
|
| 25034 |
|
|
|
| 25035 |
|
|
VD1_un59_hilo_carry_16 = CARRY(VD1_hilo_48 & VD1_op2_reged[16] # !VD1_un59_hilo_carry_15 # !VD1_hilo_48 & VD1_op2_reged[16] & !VD1_un59_hilo_carry_15);
|
| 25036 |
|
|
|
| 25037 |
|
|
|
| 25038 |
|
|
--VD1_un50_hilo_add16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add16
|
| 25039 |
|
|
--operation mode is arithmetic
|
| 25040 |
|
|
|
| 25041 |
|
|
VD1_un50_hilo_add16_carry_eqn = VD1_un50_hilo_carry_15;
|
| 25042 |
|
|
VD1_un50_hilo_add16 = VD1_hilo_48 $ VD1_nop2_reged[16] $ !VD1_un50_hilo_add16_carry_eqn;
|
| 25043 |
|
|
|
| 25044 |
|
|
--VD1_un50_hilo_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_16
|
| 25045 |
|
|
--operation mode is arithmetic
|
| 25046 |
|
|
|
| 25047 |
|
|
VD1_un50_hilo_carry_16 = CARRY(VD1_hilo_48 & VD1_nop2_reged[16] # !VD1_un50_hilo_carry_15 # !VD1_hilo_48 & VD1_nop2_reged[16] & !VD1_un50_hilo_carry_15);
|
| 25048 |
|
|
|
| 25049 |
|
|
|
| 25050 |
|
|
--VD1_un1_op2_reged_1_combout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[16]
|
| 25051 |
|
|
--operation mode is normal
|
| 25052 |
|
|
|
| 25053 |
|
|
VD1_un1_op2_reged_1_combout[16] = VD1_eqop2_2_32 & VD1_op2_reged[16] # !VD1_eqop2_2_32 & VD1_nop2_reged[16];
|
| 25054 |
|
|
|
| 25055 |
|
|
|
| 25056 |
|
|
--VD1_un59_hilo_add17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add17
|
| 25057 |
|
|
--operation mode is arithmetic
|
| 25058 |
|
|
|
| 25059 |
|
|
VD1_un59_hilo_add17_carry_eqn = VD1_un59_hilo_carry_16;
|
| 25060 |
|
|
VD1_un59_hilo_add17 = VD1_hilo_49 $ VD1_op2_reged[17] $ VD1_un59_hilo_add17_carry_eqn;
|
| 25061 |
|
|
|
| 25062 |
|
|
--VD1_un59_hilo_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_17
|
| 25063 |
|
|
--operation mode is arithmetic
|
| 25064 |
|
|
|
| 25065 |
|
|
VD1_un59_hilo_carry_17 = CARRY(VD1_hilo_49 & !VD1_op2_reged[17] & !VD1_un59_hilo_carry_16 # !VD1_hilo_49 & !VD1_un59_hilo_carry_16 # !VD1_op2_reged[17]);
|
| 25066 |
|
|
|
| 25067 |
|
|
|
| 25068 |
|
|
--VD1_un50_hilo_add17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add17
|
| 25069 |
|
|
--operation mode is arithmetic
|
| 25070 |
|
|
|
| 25071 |
|
|
VD1_un50_hilo_add17_carry_eqn = VD1_un50_hilo_carry_16;
|
| 25072 |
|
|
VD1_un50_hilo_add17 = VD1_hilo_49 $ VD1_nop2_reged[17] $ VD1_un50_hilo_add17_carry_eqn;
|
| 25073 |
|
|
|
| 25074 |
|
|
--VD1_un50_hilo_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_17
|
| 25075 |
|
|
--operation mode is arithmetic
|
| 25076 |
|
|
|
| 25077 |
|
|
VD1_un50_hilo_carry_17 = CARRY(VD1_hilo_49 & !VD1_nop2_reged[17] & !VD1_un50_hilo_carry_16 # !VD1_hilo_49 & !VD1_un50_hilo_carry_16 # !VD1_nop2_reged[17]);
|
| 25078 |
|
|
|
| 25079 |
|
|
|
| 25080 |
|
|
--DD1_pc_next_0_iv_1_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_16
|
| 25081 |
|
|
--operation mode is normal
|
| 25082 |
|
|
|
| 25083 |
|
|
DD1_pc_next_0_iv_1_16 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_16 # !DD1_pc_next_0_iv_1_a[16];
|
| 25084 |
|
|
|
| 25085 |
|
|
|
| 25086 |
|
|
--DD1_un1_pc_add16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add16
|
| 25087 |
|
|
--operation mode is arithmetic
|
| 25088 |
|
|
|
| 25089 |
|
|
DD1_un1_pc_add16_carry_eqn = DD1_un1_pc_carry_15;
|
| 25090 |
|
|
DD1_un1_pc_add16 = KB1_r32_o_16 $ DD1_un1_pc_prectl_1_0_a4[16] $ !DD1_un1_pc_add16_carry_eqn;
|
| 25091 |
|
|
|
| 25092 |
|
|
--DD1_un1_pc_carry_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_16
|
| 25093 |
|
|
--operation mode is arithmetic
|
| 25094 |
|
|
|
| 25095 |
|
|
DD1_un1_pc_carry_16 = CARRY(KB1_r32_o_16 & DD1_un1_pc_prectl_1_0_a4[16] # !DD1_un1_pc_carry_15 # !KB1_r32_o_16 & DD1_un1_pc_prectl_1_0_a4[16] & !DD1_un1_pc_carry_15);
|
| 25096 |
|
|
|
| 25097 |
|
|
|
| 25098 |
|
|
--DD1_pc_next_0_iv_1_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_17
|
| 25099 |
|
|
--operation mode is normal
|
| 25100 |
|
|
|
| 25101 |
|
|
DD1_pc_next_0_iv_1_17 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_17 # !DD1_pc_next_0_iv_1_a[17];
|
| 25102 |
|
|
|
| 25103 |
|
|
|
| 25104 |
|
|
--DD1_un1_pc_add17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add17
|
| 25105 |
|
|
--operation mode is arithmetic
|
| 25106 |
|
|
|
| 25107 |
|
|
DD1_un1_pc_add17_carry_eqn = DD1_un1_pc_carry_16;
|
| 25108 |
|
|
DD1_un1_pc_add17 = KB1_r32_o_17 $ DD1_un1_pc_prectl_1_0_a4[17] $ DD1_un1_pc_add17_carry_eqn;
|
| 25109 |
|
|
|
| 25110 |
|
|
--DD1_un1_pc_carry_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_17
|
| 25111 |
|
|
--operation mode is arithmetic
|
| 25112 |
|
|
|
| 25113 |
|
|
DD1_un1_pc_carry_17 = CARRY(KB1_r32_o_17 & !DD1_un1_pc_prectl_1_0_a4[17] & !DD1_un1_pc_carry_16 # !KB1_r32_o_17 & !DD1_un1_pc_carry_16 # !DD1_un1_pc_prectl_1_0_a4[17]);
|
| 25114 |
|
|
|
| 25115 |
|
|
|
| 25116 |
|
|
--PB1_dout_iv_16 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_16
|
| 25117 |
|
|
--operation mode is normal
|
| 25118 |
|
|
|
| 25119 |
|
|
PB1_dout_iv_16 = HD1_dout_iv_1_16 # FD1_wb_o_16 & HD1_dout7_0_a2;
|
| 25120 |
|
|
|
| 25121 |
|
|
--PB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_16
|
| 25122 |
|
|
--operation mode is normal
|
| 25123 |
|
|
|
| 25124 |
|
|
PB1_r32_o_16 = DFFEAS(PB1_dout_iv_16, E1__clk0, VCC, , , , , , );
|
| 25125 |
|
|
|
| 25126 |
|
|
|
| 25127 |
|
|
--VD1_un1_op2_reged_1_combout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[17]
|
| 25128 |
|
|
--operation mode is normal
|
| 25129 |
|
|
|
| 25130 |
|
|
VD1_un1_op2_reged_1_combout[17] = VD1_eqop2_2_32 & VD1_op2_reged[17] # !VD1_eqop2_2_32 & VD1_nop2_reged[17];
|
| 25131 |
|
|
|
| 25132 |
|
|
|
| 25133 |
|
|
--VD1_un59_hilo_add18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add18
|
| 25134 |
|
|
--operation mode is arithmetic
|
| 25135 |
|
|
|
| 25136 |
|
|
VD1_un59_hilo_add18_carry_eqn = VD1_un59_hilo_carry_17;
|
| 25137 |
|
|
VD1_un59_hilo_add18 = VD1_hilo_50 $ VD1_op2_reged[18] $ !VD1_un59_hilo_add18_carry_eqn;
|
| 25138 |
|
|
|
| 25139 |
|
|
--VD1_un59_hilo_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_18
|
| 25140 |
|
|
--operation mode is arithmetic
|
| 25141 |
|
|
|
| 25142 |
|
|
VD1_un59_hilo_carry_18 = CARRY(VD1_hilo_50 & VD1_op2_reged[18] # !VD1_un59_hilo_carry_17 # !VD1_hilo_50 & VD1_op2_reged[18] & !VD1_un59_hilo_carry_17);
|
| 25143 |
|
|
|
| 25144 |
|
|
|
| 25145 |
|
|
--PB1_dout_iv_17 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_17
|
| 25146 |
|
|
--operation mode is normal
|
| 25147 |
|
|
|
| 25148 |
|
|
PB1_dout_iv_17 = HD1_dout_iv_1_17 # FD1_wb_o_17 & HD1_dout7_0_a2;
|
| 25149 |
|
|
|
| 25150 |
|
|
--PB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_17
|
| 25151 |
|
|
--operation mode is normal
|
| 25152 |
|
|
|
| 25153 |
|
|
PB1_r32_o_17 = DFFEAS(PB1_dout_iv_17, E1__clk0, VCC, , , , , , );
|
| 25154 |
|
|
|
| 25155 |
|
|
|
| 25156 |
|
|
--VD1_un59_hilo_add14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add14
|
| 25157 |
|
|
--operation mode is arithmetic
|
| 25158 |
|
|
|
| 25159 |
|
|
VD1_un59_hilo_add14_carry_eqn = VD1_un59_hilo_carry_13;
|
| 25160 |
|
|
VD1_un59_hilo_add14 = VD1_hilo_46 $ VD1_op2_reged[14] $ !VD1_un59_hilo_add14_carry_eqn;
|
| 25161 |
|
|
|
| 25162 |
|
|
--VD1_un59_hilo_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_14
|
| 25163 |
|
|
--operation mode is arithmetic
|
| 25164 |
|
|
|
| 25165 |
|
|
VD1_un59_hilo_carry_14 = CARRY(VD1_hilo_46 & VD1_op2_reged[14] # !VD1_un59_hilo_carry_13 # !VD1_hilo_46 & VD1_op2_reged[14] & !VD1_un59_hilo_carry_13);
|
| 25166 |
|
|
|
| 25167 |
|
|
|
| 25168 |
|
|
--VD1_un50_hilo_add14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add14
|
| 25169 |
|
|
--operation mode is arithmetic
|
| 25170 |
|
|
|
| 25171 |
|
|
VD1_un50_hilo_add14_carry_eqn = VD1_un50_hilo_carry_13;
|
| 25172 |
|
|
VD1_un50_hilo_add14 = VD1_hilo_46 $ VD1_nop2_reged[14] $ !VD1_un50_hilo_add14_carry_eqn;
|
| 25173 |
|
|
|
| 25174 |
|
|
--VD1_un50_hilo_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_14
|
| 25175 |
|
|
--operation mode is arithmetic
|
| 25176 |
|
|
|
| 25177 |
|
|
VD1_un50_hilo_carry_14 = CARRY(VD1_hilo_46 & VD1_nop2_reged[14] # !VD1_un50_hilo_carry_13 # !VD1_hilo_46 & VD1_nop2_reged[14] & !VD1_un50_hilo_carry_13);
|
| 25178 |
|
|
|
| 25179 |
|
|
|
| 25180 |
|
|
--VD1_un1_op2_reged_1_combout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[14]
|
| 25181 |
|
|
--operation mode is normal
|
| 25182 |
|
|
|
| 25183 |
|
|
VD1_un1_op2_reged_1_combout[14] = VD1_eqop2_2_32 & VD1_op2_reged[14] # !VD1_eqop2_2_32 & VD1_nop2_reged[14];
|
| 25184 |
|
|
|
| 25185 |
|
|
|
| 25186 |
|
|
--VD1_un59_hilo_add15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add15
|
| 25187 |
|
|
--operation mode is arithmetic
|
| 25188 |
|
|
|
| 25189 |
|
|
VD1_un59_hilo_add15_carry_eqn = VD1_un59_hilo_carry_14;
|
| 25190 |
|
|
VD1_un59_hilo_add15 = VD1_hilo_47 $ VD1_op2_reged[15] $ VD1_un59_hilo_add15_carry_eqn;
|
| 25191 |
|
|
|
| 25192 |
|
|
--VD1_un59_hilo_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_15
|
| 25193 |
|
|
--operation mode is arithmetic
|
| 25194 |
|
|
|
| 25195 |
|
|
VD1_un59_hilo_carry_15 = CARRY(VD1_hilo_47 & !VD1_op2_reged[15] & !VD1_un59_hilo_carry_14 # !VD1_hilo_47 & !VD1_un59_hilo_carry_14 # !VD1_op2_reged[15]);
|
| 25196 |
|
|
|
| 25197 |
|
|
|
| 25198 |
|
|
--VD1_un50_hilo_add15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add15
|
| 25199 |
|
|
--operation mode is arithmetic
|
| 25200 |
|
|
|
| 25201 |
|
|
VD1_un50_hilo_add15_carry_eqn = VD1_un50_hilo_carry_14;
|
| 25202 |
|
|
VD1_un50_hilo_add15 = VD1_hilo_47 $ VD1_nop2_reged[15] $ VD1_un50_hilo_add15_carry_eqn;
|
| 25203 |
|
|
|
| 25204 |
|
|
--VD1_un50_hilo_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_15
|
| 25205 |
|
|
--operation mode is arithmetic
|
| 25206 |
|
|
|
| 25207 |
|
|
VD1_un50_hilo_carry_15 = CARRY(VD1_hilo_47 & !VD1_nop2_reged[15] & !VD1_un50_hilo_carry_14 # !VD1_hilo_47 & !VD1_un50_hilo_carry_14 # !VD1_nop2_reged[15]);
|
| 25208 |
|
|
|
| 25209 |
|
|
|
| 25210 |
|
|
--DD1_pc_next_0_iv_1_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_14
|
| 25211 |
|
|
--operation mode is normal
|
| 25212 |
|
|
|
| 25213 |
|
|
DD1_pc_next_0_iv_1_14 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_14 # !DD1_pc_next_0_iv_1_a[14];
|
| 25214 |
|
|
|
| 25215 |
|
|
|
| 25216 |
|
|
--DD1_un1_pc_add14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add14
|
| 25217 |
|
|
--operation mode is arithmetic
|
| 25218 |
|
|
|
| 25219 |
|
|
DD1_un1_pc_add14_carry_eqn = DD1_un1_pc_carry_13;
|
| 25220 |
|
|
DD1_un1_pc_add14 = KB1_r32_o_14 $ DD1_un1_pc_prectl_1_0_a4[14] $ !DD1_un1_pc_add14_carry_eqn;
|
| 25221 |
|
|
|
| 25222 |
|
|
--DD1_un1_pc_carry_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_14
|
| 25223 |
|
|
--operation mode is arithmetic
|
| 25224 |
|
|
|
| 25225 |
|
|
DD1_un1_pc_carry_14 = CARRY(KB1_r32_o_14 & DD1_un1_pc_prectl_1_0_a4[14] # !DD1_un1_pc_carry_13 # !KB1_r32_o_14 & DD1_un1_pc_prectl_1_0_a4[14] & !DD1_un1_pc_carry_13);
|
| 25226 |
|
|
|
| 25227 |
|
|
|
| 25228 |
|
|
--DD1_pc_next_0_iv_1_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_15
|
| 25229 |
|
|
--operation mode is normal
|
| 25230 |
|
|
|
| 25231 |
|
|
DD1_pc_next_0_iv_1_15 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_15 # !DD1_pc_next_0_iv_1_a[15];
|
| 25232 |
|
|
|
| 25233 |
|
|
|
| 25234 |
|
|
--DD1_un1_pc_add15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add15
|
| 25235 |
|
|
--operation mode is arithmetic
|
| 25236 |
|
|
|
| 25237 |
|
|
DD1_un1_pc_add15_carry_eqn = DD1_un1_pc_carry_14;
|
| 25238 |
|
|
DD1_un1_pc_add15 = KB1_r32_o_15 $ DD1_un1_pc_prectl_1_0_a4[15] $ DD1_un1_pc_add15_carry_eqn;
|
| 25239 |
|
|
|
| 25240 |
|
|
--DD1_un1_pc_carry_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_15
|
| 25241 |
|
|
--operation mode is arithmetic
|
| 25242 |
|
|
|
| 25243 |
|
|
DD1_un1_pc_carry_15 = CARRY(KB1_r32_o_15 & !DD1_un1_pc_prectl_1_0_a4[15] & !DD1_un1_pc_carry_14 # !KB1_r32_o_15 & !DD1_un1_pc_carry_14 # !DD1_un1_pc_prectl_1_0_a4[15]);
|
| 25244 |
|
|
|
| 25245 |
|
|
|
| 25246 |
|
|
--PB1_dout_iv_14 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_14
|
| 25247 |
|
|
--operation mode is normal
|
| 25248 |
|
|
|
| 25249 |
|
|
PB1_dout_iv_14 = HD1_dout_iv_1_14 # FD1_wb_o_14 & HD1_dout7_0_a2;
|
| 25250 |
|
|
|
| 25251 |
|
|
--PB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_14
|
| 25252 |
|
|
--operation mode is normal
|
| 25253 |
|
|
|
| 25254 |
|
|
PB1_r32_o_14 = DFFEAS(PB1_dout_iv_14, E1__clk0, VCC, , , , , , );
|
| 25255 |
|
|
|
| 25256 |
|
|
|
| 25257 |
|
|
--VD1_un1_op2_reged_1_combout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[15]
|
| 25258 |
|
|
--operation mode is normal
|
| 25259 |
|
|
|
| 25260 |
|
|
VD1_un1_op2_reged_1_combout[15] = VD1_eqop2_2_32 & VD1_op2_reged[15] # !VD1_eqop2_2_32 & VD1_nop2_reged[15];
|
| 25261 |
|
|
|
| 25262 |
|
|
|
| 25263 |
|
|
--PB1_dout_iv_15 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_15
|
| 25264 |
|
|
--operation mode is normal
|
| 25265 |
|
|
|
| 25266 |
|
|
PB1_dout_iv_15 = HD1_dout_iv_1_15 # FD1_wb_o_15 & HD1_dout7_0_a2;
|
| 25267 |
|
|
|
| 25268 |
|
|
--PB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_15
|
| 25269 |
|
|
--operation mode is normal
|
| 25270 |
|
|
|
| 25271 |
|
|
PB1_r32_o_15 = DFFEAS(PB1_dout_iv_15, E1__clk0, VCC, , , , , , );
|
| 25272 |
|
|
|
| 25273 |
|
|
|
| 25274 |
|
|
--VD1_un134_hilo_combout[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[31]
|
| 25275 |
|
|
--operation mode is normal
|
| 25276 |
|
|
|
| 25277 |
|
|
VD1_un134_hilo_combout[31]_carry_eqn = VD1_un134_hilo_cout[29];
|
| 25278 |
|
|
VD1_un134_hilo_combout[31] = VD1_hilo_31 $ (VD1_hilo_30 & VD1_un134_hilo_combout[31]_carry_eqn);
|
| 25279 |
|
|
|
| 25280 |
|
|
|
| 25281 |
|
|
--PD1_a_o_3_d_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[8]
|
| 25282 |
|
|
--operation mode is normal
|
| 25283 |
|
|
|
| 25284 |
|
|
PD1_a_o_3_d_a[8] = PD1_a_o_sn_m2 & !PB1_r32_o_8 # !PD1_a_o_sn_m2 & !AB1_r32_o_6;
|
| 25285 |
|
|
|
| 25286 |
|
|
|
| 25287 |
|
|
--VD1_hilo_33_i_m_a[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[41]
|
| 25288 |
|
|
--operation mode is normal
|
| 25289 |
|
|
|
| 25290 |
|
|
VD1_hilo_33_i_m_a[41] = VD1_addnop2 & !VD1_un50_hilo_add9 # !VD1_addnop2 & !VD1_un59_hilo_add9;
|
| 25291 |
|
|
|
| 25292 |
|
|
|
| 25293 |
|
|
--VD1_hilo_24_add9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add9
|
| 25294 |
|
|
--operation mode is arithmetic
|
| 25295 |
|
|
|
| 25296 |
|
|
VD1_hilo_24_add9_carry_eqn = VD1_hilo_24_carry_8;
|
| 25297 |
|
|
VD1_hilo_24_add9 = VD1_hilo_40 $ VD1_un1_op2_reged_1_combout[9] $ VD1_hilo_24_add9_carry_eqn;
|
| 25298 |
|
|
|
| 25299 |
|
|
--VD1_hilo_24_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_9
|
| 25300 |
|
|
--operation mode is arithmetic
|
| 25301 |
|
|
|
| 25302 |
|
|
VD1_hilo_24_carry_9 = CARRY(VD1_hilo_40 & !VD1_un1_op2_reged_1_combout[9] & !VD1_hilo_24_carry_8 # !VD1_hilo_40 & !VD1_hilo_24_carry_8 # !VD1_un1_op2_reged_1_combout[9]);
|
| 25303 |
|
|
|
| 25304 |
|
|
|
| 25305 |
|
|
--VD1_hilo_22_a[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[41]
|
| 25306 |
|
|
--operation mode is normal
|
| 25307 |
|
|
|
| 25308 |
|
|
VD1_hilo_22_a[41] = VD1_sign & !VD1_hilo_42 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add10 # !VD1_hilo[0] & !VD1_hilo_42;
|
| 25309 |
|
|
|
| 25310 |
|
|
|
| 25311 |
|
|
--VD1_hilo_15_2[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[41]
|
| 25312 |
|
|
--operation mode is normal
|
| 25313 |
|
|
|
| 25314 |
|
|
VD1_hilo_15_2[41] = VD1_sub_or_yn & VD1_un59_hilo_add10 # !VD1_sub_or_yn & VD1_un50_hilo_add10;
|
| 25315 |
|
|
|
| 25316 |
|
|
|
| 25317 |
|
|
--PD1_a_o_3_d_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[9]
|
| 25318 |
|
|
--operation mode is normal
|
| 25319 |
|
|
|
| 25320 |
|
|
PD1_a_o_3_d_a[9] = PD1_a_o_sn_m2 & !PB1_r32_o_9 # !PD1_a_o_sn_m2 & !AB1_r32_o_7;
|
| 25321 |
|
|
|
| 25322 |
|
|
|
| 25323 |
|
|
--VD1_hilo_33_i_m_a[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[42]
|
| 25324 |
|
|
--operation mode is normal
|
| 25325 |
|
|
|
| 25326 |
|
|
VD1_hilo_33_i_m_a[42] = VD1_addnop2 & !VD1_un50_hilo_add10 # !VD1_addnop2 & !VD1_un59_hilo_add10;
|
| 25327 |
|
|
|
| 25328 |
|
|
|
| 25329 |
|
|
--VD1_hilo_24_add10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add10
|
| 25330 |
|
|
--operation mode is arithmetic
|
| 25331 |
|
|
|
| 25332 |
|
|
VD1_hilo_24_add10_carry_eqn = VD1_hilo_24_carry_9;
|
| 25333 |
|
|
VD1_hilo_24_add10 = VD1_hilo_41 $ VD1_un1_op2_reged_1_combout[10] $ !VD1_hilo_24_add10_carry_eqn;
|
| 25334 |
|
|
|
| 25335 |
|
|
--VD1_hilo_24_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_10
|
| 25336 |
|
|
--operation mode is arithmetic
|
| 25337 |
|
|
|
| 25338 |
|
|
VD1_hilo_24_carry_10 = CARRY(VD1_hilo_41 & VD1_un1_op2_reged_1_combout[10] # !VD1_hilo_24_carry_9 # !VD1_hilo_41 & VD1_un1_op2_reged_1_combout[10] & !VD1_hilo_24_carry_9);
|
| 25339 |
|
|
|
| 25340 |
|
|
|
| 25341 |
|
|
--VD1_hilo_22_a[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[42]
|
| 25342 |
|
|
--operation mode is normal
|
| 25343 |
|
|
|
| 25344 |
|
|
VD1_hilo_22_a[42] = VD1_sign & !VD1_hilo_43 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add11 # !VD1_hilo[0] & !VD1_hilo_43;
|
| 25345 |
|
|
|
| 25346 |
|
|
|
| 25347 |
|
|
--VD1_hilo_15_2[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[42]
|
| 25348 |
|
|
--operation mode is normal
|
| 25349 |
|
|
|
| 25350 |
|
|
VD1_hilo_15_2[42] = VD1_sub_or_yn & VD1_un59_hilo_add11 # !VD1_sub_or_yn & VD1_un50_hilo_add11;
|
| 25351 |
|
|
|
| 25352 |
|
|
|
| 25353 |
|
|
--UD1_shift_out_80_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[10]
|
| 25354 |
|
|
--operation mode is normal
|
| 25355 |
|
|
|
| 25356 |
|
|
UD1_shift_out_80_a[10] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_13 # !PD1_a_o_1 & !VD1_b_o_iv_11;
|
| 25357 |
|
|
|
| 25358 |
|
|
|
| 25359 |
|
|
--VD1_hilo_33_i_m_a[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[43]
|
| 25360 |
|
|
--operation mode is normal
|
| 25361 |
|
|
|
| 25362 |
|
|
VD1_hilo_33_i_m_a[43] = VD1_addnop2 & !VD1_un50_hilo_add11 # !VD1_addnop2 & !VD1_un59_hilo_add11;
|
| 25363 |
|
|
|
| 25364 |
|
|
|
| 25365 |
|
|
--VD1_hilo_24_add11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add11
|
| 25366 |
|
|
--operation mode is arithmetic
|
| 25367 |
|
|
|
| 25368 |
|
|
VD1_hilo_24_add11_carry_eqn = VD1_hilo_24_carry_10;
|
| 25369 |
|
|
VD1_hilo_24_add11 = VD1_hilo_42 $ VD1_un1_op2_reged_1_combout[11] $ VD1_hilo_24_add11_carry_eqn;
|
| 25370 |
|
|
|
| 25371 |
|
|
--VD1_hilo_24_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_11
|
| 25372 |
|
|
--operation mode is arithmetic
|
| 25373 |
|
|
|
| 25374 |
|
|
VD1_hilo_24_carry_11 = CARRY(VD1_hilo_42 & !VD1_un1_op2_reged_1_combout[11] & !VD1_hilo_24_carry_10 # !VD1_hilo_42 & !VD1_hilo_24_carry_10 # !VD1_un1_op2_reged_1_combout[11]);
|
| 25375 |
|
|
|
| 25376 |
|
|
|
| 25377 |
|
|
--VD1_hilo_22_a[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[43]
|
| 25378 |
|
|
--operation mode is normal
|
| 25379 |
|
|
|
| 25380 |
|
|
VD1_hilo_22_a[43] = VD1_sign & !VD1_hilo_44 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add12 # !VD1_hilo[0] & !VD1_hilo_44;
|
| 25381 |
|
|
|
| 25382 |
|
|
|
| 25383 |
|
|
--VD1_hilo_15_2[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[43]
|
| 25384 |
|
|
--operation mode is normal
|
| 25385 |
|
|
|
| 25386 |
|
|
VD1_hilo_15_2[43] = VD1_sub_or_yn & VD1_un59_hilo_add12 # !VD1_sub_or_yn & VD1_un50_hilo_add12;
|
| 25387 |
|
|
|
| 25388 |
|
|
|
| 25389 |
|
|
--PD1_a_o_3_d_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[11]
|
| 25390 |
|
|
--operation mode is normal
|
| 25391 |
|
|
|
| 25392 |
|
|
PD1_a_o_3_d_a[11] = PD1_a_o_sn_m2 & !PB1_r32_o_11 # !PD1_a_o_sn_m2 & !AB1_r32_o_9;
|
| 25393 |
|
|
|
| 25394 |
|
|
|
| 25395 |
|
|
--VD1_un50_hilo_add21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add21
|
| 25396 |
|
|
--operation mode is arithmetic
|
| 25397 |
|
|
|
| 25398 |
|
|
VD1_un50_hilo_add21_carry_eqn = VD1_un50_hilo_carry_20;
|
| 25399 |
|
|
VD1_un50_hilo_add21 = VD1_hilo_53 $ VD1_nop2_reged[21] $ VD1_un50_hilo_add21_carry_eqn;
|
| 25400 |
|
|
|
| 25401 |
|
|
--VD1_un50_hilo_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_21
|
| 25402 |
|
|
--operation mode is arithmetic
|
| 25403 |
|
|
|
| 25404 |
|
|
VD1_un50_hilo_carry_21 = CARRY(VD1_hilo_53 & !VD1_nop2_reged[21] & !VD1_un50_hilo_carry_20 # !VD1_hilo_53 & !VD1_un50_hilo_carry_20 # !VD1_nop2_reged[21]);
|
| 25405 |
|
|
|
| 25406 |
|
|
|
| 25407 |
|
|
--VD1_un1_op2_reged_1_combout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[21]
|
| 25408 |
|
|
--operation mode is normal
|
| 25409 |
|
|
|
| 25410 |
|
|
VD1_un1_op2_reged_1_combout[21] = VD1_eqop2_2_32 & VD1_op2_reged[21] # !VD1_eqop2_2_32 & VD1_nop2_reged[21];
|
| 25411 |
|
|
|
| 25412 |
|
|
|
| 25413 |
|
|
--VD1_un59_hilo_add22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add22
|
| 25414 |
|
|
--operation mode is arithmetic
|
| 25415 |
|
|
|
| 25416 |
|
|
VD1_un59_hilo_add22_carry_eqn = VD1_un59_hilo_carry_21;
|
| 25417 |
|
|
VD1_un59_hilo_add22 = VD1_hilo_54 $ VD1_op2_reged[22] $ !VD1_un59_hilo_add22_carry_eqn;
|
| 25418 |
|
|
|
| 25419 |
|
|
--VD1_un59_hilo_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_22
|
| 25420 |
|
|
--operation mode is arithmetic
|
| 25421 |
|
|
|
| 25422 |
|
|
VD1_un59_hilo_carry_22 = CARRY(VD1_hilo_54 & VD1_op2_reged[22] # !VD1_un59_hilo_carry_21 # !VD1_hilo_54 & VD1_op2_reged[22] & !VD1_un59_hilo_carry_21);
|
| 25423 |
|
|
|
| 25424 |
|
|
|
| 25425 |
|
|
--VD1_un50_hilo_add22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add22
|
| 25426 |
|
|
--operation mode is arithmetic
|
| 25427 |
|
|
|
| 25428 |
|
|
VD1_un50_hilo_add22_carry_eqn = VD1_un50_hilo_carry_21;
|
| 25429 |
|
|
VD1_un50_hilo_add22 = VD1_hilo_54 $ VD1_nop2_reged[22] $ !VD1_un50_hilo_add22_carry_eqn;
|
| 25430 |
|
|
|
| 25431 |
|
|
--VD1_un50_hilo_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_22
|
| 25432 |
|
|
--operation mode is arithmetic
|
| 25433 |
|
|
|
| 25434 |
|
|
VD1_un50_hilo_carry_22 = CARRY(VD1_hilo_54 & VD1_nop2_reged[22] # !VD1_un50_hilo_carry_21 # !VD1_hilo_54 & VD1_nop2_reged[22] & !VD1_un50_hilo_carry_21);
|
| 25435 |
|
|
|
| 25436 |
|
|
|
| 25437 |
|
|
--DD1_pc_next_0_iv_1_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_20
|
| 25438 |
|
|
--operation mode is normal
|
| 25439 |
|
|
|
| 25440 |
|
|
DD1_pc_next_0_iv_1_20 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_20 # !DD1_pc_next_0_iv_1_a[20];
|
| 25441 |
|
|
|
| 25442 |
|
|
|
| 25443 |
|
|
--DD1_un1_pc_add20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add20
|
| 25444 |
|
|
--operation mode is arithmetic
|
| 25445 |
|
|
|
| 25446 |
|
|
DD1_un1_pc_add20_carry_eqn = DD1_un1_pc_carry_19;
|
| 25447 |
|
|
DD1_un1_pc_add20 = KB1_r32_o_20 $ DD1_un1_pc_prectl_1_0_a4[20] $ !DD1_un1_pc_add20_carry_eqn;
|
| 25448 |
|
|
|
| 25449 |
|
|
--DD1_un1_pc_carry_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_20
|
| 25450 |
|
|
--operation mode is arithmetic
|
| 25451 |
|
|
|
| 25452 |
|
|
DD1_un1_pc_carry_20 = CARRY(KB1_r32_o_20 & DD1_un1_pc_prectl_1_0_a4[20] # !DD1_un1_pc_carry_19 # !KB1_r32_o_20 & DD1_un1_pc_prectl_1_0_a4[20] & !DD1_un1_pc_carry_19);
|
| 25453 |
|
|
|
| 25454 |
|
|
|
| 25455 |
|
|
--DD1_pc_next_0_iv_1_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_21
|
| 25456 |
|
|
--operation mode is normal
|
| 25457 |
|
|
|
| 25458 |
|
|
DD1_pc_next_0_iv_1_21 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_21 # !DD1_pc_next_0_iv_1_a[21];
|
| 25459 |
|
|
|
| 25460 |
|
|
|
| 25461 |
|
|
--DD1_un1_pc_add21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add21
|
| 25462 |
|
|
--operation mode is arithmetic
|
| 25463 |
|
|
|
| 25464 |
|
|
DD1_un1_pc_add21_carry_eqn = DD1_un1_pc_carry_20;
|
| 25465 |
|
|
DD1_un1_pc_add21 = KB1_r32_o_21 $ DD1_un1_pc_prectl_1_0_a4[21] $ DD1_un1_pc_add21_carry_eqn;
|
| 25466 |
|
|
|
| 25467 |
|
|
--DD1_un1_pc_carry_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_21
|
| 25468 |
|
|
--operation mode is arithmetic
|
| 25469 |
|
|
|
| 25470 |
|
|
DD1_un1_pc_carry_21 = CARRY(KB1_r32_o_21 & !DD1_un1_pc_prectl_1_0_a4[21] & !DD1_un1_pc_carry_20 # !KB1_r32_o_21 & !DD1_un1_pc_carry_20 # !DD1_un1_pc_prectl_1_0_a4[21]);
|
| 25471 |
|
|
|
| 25472 |
|
|
|
| 25473 |
|
|
--KB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_18
|
| 25474 |
|
|
--operation mode is normal
|
| 25475 |
|
|
|
| 25476 |
|
|
KB1_r32_o_18_lut_out = DD1_pc_next_0_iv_1_18 # DD1_un1_pc_next46_0 & DD1_un1_pc_add18;
|
| 25477 |
|
|
KB1_r32_o_18 = DFFEAS(KB1_r32_o_18_lut_out, E1__clk0, VCC, , , , , , );
|
| 25478 |
|
|
|
| 25479 |
|
|
|
| 25480 |
|
|
--KB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_19
|
| 25481 |
|
|
--operation mode is normal
|
| 25482 |
|
|
|
| 25483 |
|
|
KB1_r32_o_19_lut_out = DD1_pc_next_0_iv_1_19 # DD1_un1_pc_next46_0 & DD1_un1_pc_add19;
|
| 25484 |
|
|
KB1_r32_o_19 = DFFEAS(KB1_r32_o_19_lut_out, E1__clk0, VCC, , , , , , );
|
| 25485 |
|
|
|
| 25486 |
|
|
|
| 25487 |
|
|
--PB1_dout_iv_21 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_21
|
| 25488 |
|
|
--operation mode is normal
|
| 25489 |
|
|
|
| 25490 |
|
|
PB1_dout_iv_21 = HD1_dout_iv_1_21 # FD1_wb_o_21 & HD1_dout7_0_a2;
|
| 25491 |
|
|
|
| 25492 |
|
|
--PB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_21
|
| 25493 |
|
|
--operation mode is normal
|
| 25494 |
|
|
|
| 25495 |
|
|
PB1_r32_o_21 = DFFEAS(PB1_dout_iv_21, E1__clk0, VCC, , , , , , );
|
| 25496 |
|
|
|
| 25497 |
|
|
|
| 25498 |
|
|
--VD1_un1_op2_reged_1_combout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[19]
|
| 25499 |
|
|
--operation mode is normal
|
| 25500 |
|
|
|
| 25501 |
|
|
VD1_un1_op2_reged_1_combout[19] = VD1_eqop2_2_32 & VD1_op2_reged[19] # !VD1_eqop2_2_32 & VD1_nop2_reged[19];
|
| 25502 |
|
|
|
| 25503 |
|
|
|
| 25504 |
|
|
--VD1_un59_hilo_add20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add20
|
| 25505 |
|
|
--operation mode is arithmetic
|
| 25506 |
|
|
|
| 25507 |
|
|
VD1_un59_hilo_add20_carry_eqn = VD1_un59_hilo_carry_19;
|
| 25508 |
|
|
VD1_un59_hilo_add20 = VD1_hilo_52 $ VD1_op2_reged[20] $ !VD1_un59_hilo_add20_carry_eqn;
|
| 25509 |
|
|
|
| 25510 |
|
|
--VD1_un59_hilo_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_20
|
| 25511 |
|
|
--operation mode is arithmetic
|
| 25512 |
|
|
|
| 25513 |
|
|
VD1_un59_hilo_carry_20 = CARRY(VD1_hilo_52 & VD1_op2_reged[20] # !VD1_un59_hilo_carry_19 # !VD1_hilo_52 & VD1_op2_reged[20] & !VD1_un59_hilo_carry_19);
|
| 25514 |
|
|
|
| 25515 |
|
|
|
| 25516 |
|
|
--VD1_hilo_37_iv_0_1_a[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[52]
|
| 25517 |
|
|
--operation mode is normal
|
| 25518 |
|
|
|
| 25519 |
|
|
VD1_hilo_37_iv_0_1_a[52] = VD1_hilo_20 & !VD1_hilo_52 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_hilo_20 & VD1_hilo_0_sqmuxa # !VD1_hilo_52 & VD1_hilo_37_iv_0_o3_2[34];
|
| 25520 |
|
|
|
| 25521 |
|
|
|
| 25522 |
|
|
--PB1_dout_iv_20 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_20
|
| 25523 |
|
|
--operation mode is normal
|
| 25524 |
|
|
|
| 25525 |
|
|
PB1_dout_iv_20 = HD1_dout_iv_1_20 # FD1_wb_o_20 & HD1_dout7_0_a2;
|
| 25526 |
|
|
|
| 25527 |
|
|
--PB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_20
|
| 25528 |
|
|
--operation mode is normal
|
| 25529 |
|
|
|
| 25530 |
|
|
PB1_r32_o_20 = DFFEAS(PB1_dout_iv_20, E1__clk0, VCC, , , , , , );
|
| 25531 |
|
|
|
| 25532 |
|
|
|
| 25533 |
|
|
--VD1_hilo_37_iv_0_2[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[51]
|
| 25534 |
|
|
--operation mode is normal
|
| 25535 |
|
|
|
| 25536 |
|
|
VD1_hilo_37_iv_0_2[51] = VD1_hilo_37_iv_0_2_a[51] # !VD1_hilo_51 & VD1_hilo_37_iv_0_a3_1[62] # VD1_hilo_37_iv_0_a3_4[62];
|
| 25537 |
|
|
|
| 25538 |
|
|
|
| 25539 |
|
|
--VD1_hilo_37_iv_0_6_a[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6_a[51]
|
| 25540 |
|
|
--operation mode is normal
|
| 25541 |
|
|
|
| 25542 |
|
|
VD1_hilo_37_iv_0_6_a[51] = VD1_hilo_52 & !VD1_un59_hilo_add20 & VD1_hilo_37_iv_0_a6_1_0[40] # !VD1_hilo_52 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_un59_hilo_add20 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 25543 |
|
|
|
| 25544 |
|
|
|
| 25545 |
|
|
--PD1_a_o_3_d_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[19]
|
| 25546 |
|
|
--operation mode is normal
|
| 25547 |
|
|
|
| 25548 |
|
|
PD1_a_o_3_d_a[19] = PD1_a_o_sn_m2 & !PB1_r32_o_19 # !PD1_a_o_sn_m2 & !AB1_r32_o_17;
|
| 25549 |
|
|
|
| 25550 |
|
|
|
| 25551 |
|
|
--VD1_hilo_29_Z[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_29_Z[18]
|
| 25552 |
|
|
--operation mode is normal
|
| 25553 |
|
|
|
| 25554 |
|
|
VD1_hilo_29_Z[18] = VD1_add1 & VD1_un134_hilo_combout[18] # !VD1_add1 & VD1_hilo_18;
|
| 25555 |
|
|
|
| 25556 |
|
|
|
| 25557 |
|
|
--VD1_hilo_37_iv_0_1_a[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[50]
|
| 25558 |
|
|
--operation mode is normal
|
| 25559 |
|
|
|
| 25560 |
|
|
VD1_hilo_37_iv_0_1_a[50] = VD1_hilo_18 & !VD1_un59_hilo_add18 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_hilo_18 & VD1_hilo_0_sqmuxa # !VD1_un59_hilo_add18 & VD1_hilo_37_iv_0_a3_2[62];
|
| 25561 |
|
|
|
| 25562 |
|
|
|
| 25563 |
|
|
--VD1_un1_op2_reged_1_combout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[18]
|
| 25564 |
|
|
--operation mode is normal
|
| 25565 |
|
|
|
| 25566 |
|
|
VD1_un1_op2_reged_1_combout[18] = VD1_eqop2_2_32 & VD1_op2_reged[18] # !VD1_eqop2_2_32 & VD1_nop2_reged[18];
|
| 25567 |
|
|
|
| 25568 |
|
|
|
| 25569 |
|
|
--PD1_a_o_3_d_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[18]
|
| 25570 |
|
|
--operation mode is normal
|
| 25571 |
|
|
|
| 25572 |
|
|
PD1_a_o_3_d_a[18] = PD1_a_o_sn_m2 & !PB1_r32_o_18 # !PD1_a_o_sn_m2 & !AB1_r32_o_16;
|
| 25573 |
|
|
|
| 25574 |
|
|
|
| 25575 |
|
|
--VD1_un1_op2_reged_1_combout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[26]
|
| 25576 |
|
|
--operation mode is normal
|
| 25577 |
|
|
|
| 25578 |
|
|
VD1_un1_op2_reged_1_combout[26] = VD1_eqop2_2_32 & VD1_op2_reged[26] # !VD1_eqop2_2_32 & VD1_nop2_reged[26];
|
| 25579 |
|
|
|
| 25580 |
|
|
|
| 25581 |
|
|
--VD1_hilo_24_add25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add25
|
| 25582 |
|
|
--operation mode is arithmetic
|
| 25583 |
|
|
|
| 25584 |
|
|
VD1_hilo_24_add25_carry_eqn = VD1_hilo_24_carry_24;
|
| 25585 |
|
|
VD1_hilo_24_add25 = VD1_hilo_56 $ VD1_un1_op2_reged_1_combout[25] $ VD1_hilo_24_add25_carry_eqn;
|
| 25586 |
|
|
|
| 25587 |
|
|
--VD1_hilo_24_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_25
|
| 25588 |
|
|
--operation mode is arithmetic
|
| 25589 |
|
|
|
| 25590 |
|
|
VD1_hilo_24_carry_25 = CARRY(VD1_hilo_56 & !VD1_un1_op2_reged_1_combout[25] & !VD1_hilo_24_carry_24 # !VD1_hilo_56 & !VD1_hilo_24_carry_24 # !VD1_un1_op2_reged_1_combout[25]);
|
| 25591 |
|
|
|
| 25592 |
|
|
|
| 25593 |
|
|
--VD1_un50_hilo_add27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add27
|
| 25594 |
|
|
--operation mode is arithmetic
|
| 25595 |
|
|
|
| 25596 |
|
|
VD1_un50_hilo_add27_carry_eqn = VD1_un50_hilo_carry_26;
|
| 25597 |
|
|
VD1_un50_hilo_add27 = VD1_hilo_59 $ VD1_nop2_reged[27] $ VD1_un50_hilo_add27_carry_eqn;
|
| 25598 |
|
|
|
| 25599 |
|
|
--VD1_un50_hilo_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_27
|
| 25600 |
|
|
--operation mode is arithmetic
|
| 25601 |
|
|
|
| 25602 |
|
|
VD1_un50_hilo_carry_27 = CARRY(VD1_hilo_59 & !VD1_nop2_reged[27] & !VD1_un50_hilo_carry_26 # !VD1_hilo_59 & !VD1_un50_hilo_carry_26 # !VD1_nop2_reged[27]);
|
| 25603 |
|
|
|
| 25604 |
|
|
|
| 25605 |
|
|
--VD1_hilo_37_iv_0_o3_1_0_1_1_a[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1_0_1_1_a[58]
|
| 25606 |
|
|
--operation mode is normal
|
| 25607 |
|
|
|
| 25608 |
|
|
VD1_hilo_37_iv_0_o3_1_0_1_1_a[58] = VD1_hilo_59 & !VD1_un59_hilo_add27 & VD1_hilo_37_iv_0_a6_1_0[40] # !VD1_hilo_59 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_un59_hilo_add27 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 25609 |
|
|
|
| 25610 |
|
|
|
| 25611 |
|
|
--VD1_un59_hilo_add26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add26
|
| 25612 |
|
|
--operation mode is arithmetic
|
| 25613 |
|
|
|
| 25614 |
|
|
VD1_un59_hilo_add26_carry_eqn = VD1_un59_hilo_carry_25;
|
| 25615 |
|
|
VD1_un59_hilo_add26 = VD1_hilo_58 $ VD1_op2_reged[26] $ !VD1_un59_hilo_add26_carry_eqn;
|
| 25616 |
|
|
|
| 25617 |
|
|
--VD1_un59_hilo_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_26
|
| 25618 |
|
|
--operation mode is arithmetic
|
| 25619 |
|
|
|
| 25620 |
|
|
VD1_un59_hilo_carry_26 = CARRY(VD1_hilo_58 & VD1_op2_reged[26] # !VD1_un59_hilo_carry_25 # !VD1_hilo_58 & VD1_op2_reged[26] & !VD1_un59_hilo_carry_25);
|
| 25621 |
|
|
|
| 25622 |
|
|
|
| 25623 |
|
|
--VD1_un50_hilo_add26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add26
|
| 25624 |
|
|
--operation mode is arithmetic
|
| 25625 |
|
|
|
| 25626 |
|
|
VD1_un50_hilo_add26_carry_eqn = VD1_un50_hilo_carry_25;
|
| 25627 |
|
|
VD1_un50_hilo_add26 = VD1_hilo_58 $ VD1_nop2_reged[26] $ !VD1_un50_hilo_add26_carry_eqn;
|
| 25628 |
|
|
|
| 25629 |
|
|
--VD1_un50_hilo_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_26
|
| 25630 |
|
|
--operation mode is arithmetic
|
| 25631 |
|
|
|
| 25632 |
|
|
VD1_un50_hilo_carry_26 = CARRY(VD1_hilo_58 & VD1_nop2_reged[26] # !VD1_un50_hilo_carry_25 # !VD1_hilo_58 & VD1_nop2_reged[26] & !VD1_un50_hilo_carry_25);
|
| 25633 |
|
|
|
| 25634 |
|
|
|
| 25635 |
|
|
--PD1_a_o_3_d_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[26]
|
| 25636 |
|
|
--operation mode is normal
|
| 25637 |
|
|
|
| 25638 |
|
|
PD1_a_o_3_d_a[26] = PD1_a_o_sn_m2 & !PB1_r32_o_26 # !PD1_a_o_sn_m2 & !AB1_r32_o_24;
|
| 25639 |
|
|
|
| 25640 |
|
|
|
| 25641 |
|
|
--VD1_un1_op2_reged_1_combout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[27]
|
| 25642 |
|
|
--operation mode is normal
|
| 25643 |
|
|
|
| 25644 |
|
|
VD1_un1_op2_reged_1_combout[27] = VD1_eqop2_2_32 & VD1_op2_reged[27] # !VD1_eqop2_2_32 & VD1_nop2_reged[27];
|
| 25645 |
|
|
|
| 25646 |
|
|
|
| 25647 |
|
|
--VD1_un50_hilo_add28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add28
|
| 25648 |
|
|
--operation mode is arithmetic
|
| 25649 |
|
|
|
| 25650 |
|
|
VD1_un50_hilo_add28_carry_eqn = VD1_un50_hilo_carry_27;
|
| 25651 |
|
|
VD1_un50_hilo_add28 = VD1_hilo_60 $ VD1_nop2_reged[28] $ !VD1_un50_hilo_add28_carry_eqn;
|
| 25652 |
|
|
|
| 25653 |
|
|
--VD1_un50_hilo_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_28
|
| 25654 |
|
|
--operation mode is arithmetic
|
| 25655 |
|
|
|
| 25656 |
|
|
VD1_un50_hilo_carry_28 = CARRY(VD1_hilo_60 & VD1_nop2_reged[28] # !VD1_un50_hilo_carry_27 # !VD1_hilo_60 & VD1_nop2_reged[28] & !VD1_un50_hilo_carry_27);
|
| 25657 |
|
|
|
| 25658 |
|
|
|
| 25659 |
|
|
--VD1_hilo_37_iv_0_3[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[59]
|
| 25660 |
|
|
--operation mode is normal
|
| 25661 |
|
|
|
| 25662 |
|
|
VD1_hilo_37_iv_0_3[59] = VD1_hilo_37_iv_0_a5_0[59] # VD1_hilo_37_iv_0_1[59] # !VD1_un59_hilo_add28 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 25663 |
|
|
|
| 25664 |
|
|
|
| 25665 |
|
|
--VD1_hilo_37_iv_0_6_a[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6_a[59]
|
| 25666 |
|
|
--operation mode is normal
|
| 25667 |
|
|
|
| 25668 |
|
|
VD1_hilo_37_iv_0_6_a[59] = VD1_hilo_60 & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add27 # !VD1_hilo_60 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add27;
|
| 25669 |
|
|
|
| 25670 |
|
|
|
| 25671 |
|
|
--PD1_a_o_3_d_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[27]
|
| 25672 |
|
|
--operation mode is normal
|
| 25673 |
|
|
|
| 25674 |
|
|
PD1_a_o_3_d_a[27] = PD1_a_o_sn_m2 & !PB1_r32_o_27 # !PD1_a_o_sn_m2 & !AB1_r32_o_25;
|
| 25675 |
|
|
|
| 25676 |
|
|
|
| 25677 |
|
|
--PD1_a_o_3_d_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[28]
|
| 25678 |
|
|
--operation mode is normal
|
| 25679 |
|
|
|
| 25680 |
|
|
PD1_a_o_3_d_a[28] = PD1_a_o_sn_m2 & !PB1_r32_o_28 # !PD1_a_o_sn_m2 & !AB1_r32_o_26;
|
| 25681 |
|
|
|
| 25682 |
|
|
|
| 25683 |
|
|
--VD1_hilo_37_iv_0_a[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[60]
|
| 25684 |
|
|
--operation mode is normal
|
| 25685 |
|
|
|
| 25686 |
|
|
VD1_hilo_37_iv_0_a[60] = !VD1_hilo_37_iv_0_6[60] & VD1_hilo_24_add28 # !VD1_hilo_2_sqmuxa;
|
| 25687 |
|
|
|
| 25688 |
|
|
|
| 25689 |
|
|
--VD1_hilo_37_iv_0_3[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[61]
|
| 25690 |
|
|
--operation mode is normal
|
| 25691 |
|
|
|
| 25692 |
|
|
VD1_hilo_37_iv_0_3[61] = VD1_hilo_37_iv_0_a5_0[61] # VD1_hilo_37_iv_0_1[61] # !VD1_un59_hilo_add30 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 25693 |
|
|
|
| 25694 |
|
|
|
| 25695 |
|
|
--VD1_hilo_37_iv_0_6_a[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6_a[61]
|
| 25696 |
|
|
--operation mode is normal
|
| 25697 |
|
|
|
| 25698 |
|
|
VD1_hilo_37_iv_0_6_a[61] = VD1_hilo_62 & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add29 # !VD1_hilo_62 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add29;
|
| 25699 |
|
|
|
| 25700 |
|
|
|
| 25701 |
|
|
--VD1_un59_hilo_add13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add13
|
| 25702 |
|
|
--operation mode is arithmetic
|
| 25703 |
|
|
|
| 25704 |
|
|
VD1_un59_hilo_add13_carry_eqn = VD1_un59_hilo_carry_12;
|
| 25705 |
|
|
VD1_un59_hilo_add13 = VD1_hilo_45 $ VD1_op2_reged[13] $ VD1_un59_hilo_add13_carry_eqn;
|
| 25706 |
|
|
|
| 25707 |
|
|
--VD1_un59_hilo_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_13
|
| 25708 |
|
|
--operation mode is arithmetic
|
| 25709 |
|
|
|
| 25710 |
|
|
VD1_un59_hilo_carry_13 = CARRY(VD1_hilo_45 & !VD1_op2_reged[13] & !VD1_un59_hilo_carry_12 # !VD1_hilo_45 & !VD1_un59_hilo_carry_12 # !VD1_op2_reged[13]);
|
| 25711 |
|
|
|
| 25712 |
|
|
|
| 25713 |
|
|
--VD1_un1_op2_reged_1_combout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[13]
|
| 25714 |
|
|
--operation mode is normal
|
| 25715 |
|
|
|
| 25716 |
|
|
VD1_un1_op2_reged_1_combout[13] = VD1_eqop2_2_32 & VD1_op2_reged[13] # !VD1_eqop2_2_32 & VD1_nop2_reged[13];
|
| 25717 |
|
|
|
| 25718 |
|
|
|
| 25719 |
|
|
--DD1_pc_next_0_iv_1_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_13
|
| 25720 |
|
|
--operation mode is normal
|
| 25721 |
|
|
|
| 25722 |
|
|
DD1_pc_next_0_iv_1_13 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_13 # !DD1_pc_next_0_iv_1_a[13];
|
| 25723 |
|
|
|
| 25724 |
|
|
|
| 25725 |
|
|
--DD1_un1_pc_add13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add13
|
| 25726 |
|
|
--operation mode is arithmetic
|
| 25727 |
|
|
|
| 25728 |
|
|
DD1_un1_pc_add13_carry_eqn = DD1_un1_pc_carry_12;
|
| 25729 |
|
|
DD1_un1_pc_add13 = KB1_r32_o_13 $ DD1_un1_pc_prectl_1_0_a4[13] $ DD1_un1_pc_add13_carry_eqn;
|
| 25730 |
|
|
|
| 25731 |
|
|
--DD1_un1_pc_carry_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_13
|
| 25732 |
|
|
--operation mode is arithmetic
|
| 25733 |
|
|
|
| 25734 |
|
|
DD1_un1_pc_carry_13 = CARRY(KB1_r32_o_13 & !DD1_un1_pc_prectl_1_0_a4[13] & !DD1_un1_pc_carry_12 # !KB1_r32_o_13 & !DD1_un1_pc_carry_12 # !DD1_un1_pc_prectl_1_0_a4[13]);
|
| 25735 |
|
|
|
| 25736 |
|
|
|
| 25737 |
|
|
--PB1_dout_iv_13 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_13
|
| 25738 |
|
|
--operation mode is normal
|
| 25739 |
|
|
|
| 25740 |
|
|
PB1_dout_iv_13 = HD1_dout_iv_1_13 # FD1_wb_o_13 & HD1_dout7_0_a2;
|
| 25741 |
|
|
|
| 25742 |
|
|
--PB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_13
|
| 25743 |
|
|
--operation mode is normal
|
| 25744 |
|
|
|
| 25745 |
|
|
PB1_r32_o_13 = DFFEAS(PB1_dout_iv_13, E1__clk0, VCC, , , , , , );
|
| 25746 |
|
|
|
| 25747 |
|
|
|
| 25748 |
|
|
--HD1_dout_iv_1_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_30
|
| 25749 |
|
|
--operation mode is normal
|
| 25750 |
|
|
|
| 25751 |
|
|
HD1_dout_iv_1_30 = FD1_N_18_i_0_s3 & LD2_q_b[30] # !HD1_dout_iv_1_a[30];
|
| 25752 |
|
|
|
| 25753 |
|
|
|
| 25754 |
|
|
--VD1_nop2_reged[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[28]
|
| 25755 |
|
|
--operation mode is arithmetic
|
| 25756 |
|
|
|
| 25757 |
|
|
VD1_nop2_reged[28]_carry_eqn = VD1_nop2_reged_cout[26];
|
| 25758 |
|
|
VD1_nop2_reged[28] = VD1_op2_reged[28] $ VD1_nop2_reged[28]_carry_eqn;
|
| 25759 |
|
|
|
| 25760 |
|
|
--VD1_nop2_reged_cout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[28]
|
| 25761 |
|
|
--operation mode is arithmetic
|
| 25762 |
|
|
|
| 25763 |
|
|
VD1_nop2_reged_cout[28] = CARRY(!VD1_op2_reged[29] & !VD1_op2_reged[28] & !VD1_nop2_reged_cout[26]);
|
| 25764 |
|
|
|
| 25765 |
|
|
|
| 25766 |
|
|
--VD1_un1_op2_reged_1_combout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[28]
|
| 25767 |
|
|
--operation mode is normal
|
| 25768 |
|
|
|
| 25769 |
|
|
VD1_un1_op2_reged_1_combout[28] = VD1_eqop2_2_32 & VD1_op2_reged[28] # !VD1_eqop2_2_32 & VD1_nop2_reged[28];
|
| 25770 |
|
|
|
| 25771 |
|
|
|
| 25772 |
|
|
--VD1_un59_hilo_add28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add28
|
| 25773 |
|
|
--operation mode is arithmetic
|
| 25774 |
|
|
|
| 25775 |
|
|
VD1_un59_hilo_add28_carry_eqn = VD1_un59_hilo_carry_27;
|
| 25776 |
|
|
VD1_un59_hilo_add28 = VD1_hilo_60 $ VD1_op2_reged[28] $ !VD1_un59_hilo_add28_carry_eqn;
|
| 25777 |
|
|
|
| 25778 |
|
|
--VD1_un59_hilo_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_28
|
| 25779 |
|
|
--operation mode is arithmetic
|
| 25780 |
|
|
|
| 25781 |
|
|
VD1_un59_hilo_carry_28 = CARRY(VD1_hilo_60 & VD1_op2_reged[28] # !VD1_un59_hilo_carry_27 # !VD1_hilo_60 & VD1_op2_reged[28] & !VD1_un59_hilo_carry_27);
|
| 25782 |
|
|
|
| 25783 |
|
|
|
| 25784 |
|
|
--UD1_shift_out_68[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[30]
|
| 25785 |
|
|
--operation mode is normal
|
| 25786 |
|
|
|
| 25787 |
|
|
UD1_shift_out_68[30] = PD1_a_o_0 & VD1_b_o_iv_27 # !PD1_a_o_0 & VD1_b_o_iv_28;
|
| 25788 |
|
|
|
| 25789 |
|
|
|
| 25790 |
|
|
--VD1_un50_hilo_add12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add12
|
| 25791 |
|
|
--operation mode is arithmetic
|
| 25792 |
|
|
|
| 25793 |
|
|
VD1_un50_hilo_add12_carry_eqn = VD1_un50_hilo_carry_11;
|
| 25794 |
|
|
VD1_un50_hilo_add12 = VD1_hilo_44 $ VD1_nop2_reged[12] $ !VD1_un50_hilo_add12_carry_eqn;
|
| 25795 |
|
|
|
| 25796 |
|
|
--VD1_un50_hilo_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_12
|
| 25797 |
|
|
--operation mode is arithmetic
|
| 25798 |
|
|
|
| 25799 |
|
|
VD1_un50_hilo_carry_12 = CARRY(VD1_hilo_44 & VD1_nop2_reged[12] # !VD1_un50_hilo_carry_11 # !VD1_hilo_44 & VD1_nop2_reged[12] & !VD1_un50_hilo_carry_11);
|
| 25800 |
|
|
|
| 25801 |
|
|
|
| 25802 |
|
|
--VD1_un1_op2_reged_1_combout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[12]
|
| 25803 |
|
|
--operation mode is normal
|
| 25804 |
|
|
|
| 25805 |
|
|
VD1_un1_op2_reged_1_combout[12] = VD1_eqop2_2_32 & VD1_op2_reged[12] # !VD1_eqop2_2_32 & VD1_nop2_reged[12];
|
| 25806 |
|
|
|
| 25807 |
|
|
|
| 25808 |
|
|
--VD1_hilo_37_iv_0_o3_0_a[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_0_a[44]
|
| 25809 |
|
|
--operation mode is normal
|
| 25810 |
|
|
|
| 25811 |
|
|
VD1_hilo_37_iv_0_o3_0_a[44] = VD1_hilo_12 & !VD1_hilo_45 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_hilo_12 & VD1_hilo_0_sqmuxa # !VD1_hilo_45 & VD1_hilo_37_iv_0_a6_0_1[40];
|
| 25812 |
|
|
|
| 25813 |
|
|
|
| 25814 |
|
|
--VD1_hilo_37_iv_0_2_a[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2_a[44]
|
| 25815 |
|
|
--operation mode is normal
|
| 25816 |
|
|
|
| 25817 |
|
|
VD1_hilo_37_iv_0_2_a[44] = VD1_hilo_44 & !VD1_un59_hilo_add12 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_hilo_44 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_un59_hilo_add12 & VD1_hilo_37_iv_0_a3_2[62];
|
| 25818 |
|
|
|
| 25819 |
|
|
|
| 25820 |
|
|
--PD1_a_o_3_d_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[12]
|
| 25821 |
|
|
--operation mode is normal
|
| 25822 |
|
|
|
| 25823 |
|
|
PD1_a_o_3_d_a[12] = PD1_a_o_sn_m2 & !PB1_r32_o_12 # !PD1_a_o_sn_m2 & !AB1_r32_o_10;
|
| 25824 |
|
|
|
| 25825 |
|
|
|
| 25826 |
|
|
--VD1_hilo_37_iv_0_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[24]
|
| 25827 |
|
|
--operation mode is normal
|
| 25828 |
|
|
|
| 25829 |
|
|
VD1_hilo_37_iv_0_a[24] = VD1_add1 & !VD1_un134_hilo_combout[24] # !VD1_add1 & !VD1_hilo_24;
|
| 25830 |
|
|
|
| 25831 |
|
|
|
| 25832 |
|
|
--VD1_hilo_33_i_m_a[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[56]
|
| 25833 |
|
|
--operation mode is normal
|
| 25834 |
|
|
|
| 25835 |
|
|
VD1_hilo_33_i_m_a[56] = VD1_addnop2 & !VD1_un50_hilo_add24 # !VD1_addnop2 & !VD1_un59_hilo_add24;
|
| 25836 |
|
|
|
| 25837 |
|
|
|
| 25838 |
|
|
--VD1_hilo_24_add24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add24
|
| 25839 |
|
|
--operation mode is arithmetic
|
| 25840 |
|
|
|
| 25841 |
|
|
VD1_hilo_24_add24_carry_eqn = VD1_hilo_24_carry_23;
|
| 25842 |
|
|
VD1_hilo_24_add24 = VD1_hilo_55 $ VD1_un1_op2_reged_1_combout[24] $ !VD1_hilo_24_add24_carry_eqn;
|
| 25843 |
|
|
|
| 25844 |
|
|
--VD1_hilo_24_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_24
|
| 25845 |
|
|
--operation mode is arithmetic
|
| 25846 |
|
|
|
| 25847 |
|
|
VD1_hilo_24_carry_24 = CARRY(VD1_hilo_55 & VD1_un1_op2_reged_1_combout[24] # !VD1_hilo_24_carry_23 # !VD1_hilo_55 & VD1_un1_op2_reged_1_combout[24] & !VD1_hilo_24_carry_23);
|
| 25848 |
|
|
|
| 25849 |
|
|
|
| 25850 |
|
|
--VD1_hilo_22_a[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[56]
|
| 25851 |
|
|
--operation mode is normal
|
| 25852 |
|
|
|
| 25853 |
|
|
VD1_hilo_22_a[56] = VD1_sign & !VD1_hilo_57 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add25 # !VD1_hilo[0] & !VD1_hilo_57;
|
| 25854 |
|
|
|
| 25855 |
|
|
|
| 25856 |
|
|
--VD1_hilo_15_2[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[56]
|
| 25857 |
|
|
--operation mode is normal
|
| 25858 |
|
|
|
| 25859 |
|
|
VD1_hilo_15_2[56] = VD1_sub_or_yn & VD1_un59_hilo_add25 # !VD1_sub_or_yn & VD1_un50_hilo_add25;
|
| 25860 |
|
|
|
| 25861 |
|
|
|
| 25862 |
|
|
--KB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_24
|
| 25863 |
|
|
--operation mode is normal
|
| 25864 |
|
|
|
| 25865 |
|
|
KB1_r32_o_24_lut_out = DD1_pc_next_0_iv_1_24 # DD1_un1_pc_next46_0 & DD1_un1_pc_add24;
|
| 25866 |
|
|
KB1_r32_o_24 = DFFEAS(KB1_r32_o_24_lut_out, E1__clk0, VCC, , , , , , );
|
| 25867 |
|
|
|
| 25868 |
|
|
|
| 25869 |
|
|
--KB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_25
|
| 25870 |
|
|
--operation mode is normal
|
| 25871 |
|
|
|
| 25872 |
|
|
KB1_r32_o_25_lut_out = DD1_pc_next_0_iv_1_25 # DD1_un1_pc_next46_0 & DD1_un1_pc_add25;
|
| 25873 |
|
|
KB1_r32_o_25 = DFFEAS(KB1_r32_o_25_lut_out, E1__clk0, VCC, , , , , , );
|
| 25874 |
|
|
|
| 25875 |
|
|
|
| 25876 |
|
|
--PD1_a_o_3_d_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[24]
|
| 25877 |
|
|
--operation mode is normal
|
| 25878 |
|
|
|
| 25879 |
|
|
PD1_a_o_3_d_a[24] = PD1_a_o_sn_m2 & !PB1_r32_o_24 # !PD1_a_o_sn_m2 & !AB1_r32_o_22;
|
| 25880 |
|
|
|
| 25881 |
|
|
|
| 25882 |
|
|
--VD1_un134_hilo_combout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[23]
|
| 25883 |
|
|
--operation mode is arithmetic
|
| 25884 |
|
|
|
| 25885 |
|
|
VD1_un134_hilo_combout[23]_carry_eqn = VD1_un134_hilo_cout[21];
|
| 25886 |
|
|
VD1_un134_hilo_combout[23] = VD1_hilo_23 $ (VD1_hilo_22 & VD1_un134_hilo_combout[23]_carry_eqn);
|
| 25887 |
|
|
|
| 25888 |
|
|
--VD1_un134_hilo_cout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[23]
|
| 25889 |
|
|
--operation mode is arithmetic
|
| 25890 |
|
|
|
| 25891 |
|
|
VD1_un134_hilo_cout[23] = CARRY(!VD1_un134_hilo_cout[21] # !VD1_hilo_23 # !VD1_hilo_22);
|
| 25892 |
|
|
|
| 25893 |
|
|
|
| 25894 |
|
|
--VD1_hilo_37_iv_0_2[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[57]
|
| 25895 |
|
|
--operation mode is normal
|
| 25896 |
|
|
|
| 25897 |
|
|
VD1_hilo_37_iv_0_2[57] = VD1_hilo_37_iv_0_2_a[57] # !VD1_hilo_57 & VD1_hilo_37_iv_0_a3_1[62] # VD1_hilo_37_iv_0_a3_4[62];
|
| 25898 |
|
|
|
| 25899 |
|
|
|
| 25900 |
|
|
--VD1_un50_hilo_add25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add25
|
| 25901 |
|
|
--operation mode is arithmetic
|
| 25902 |
|
|
|
| 25903 |
|
|
VD1_un50_hilo_add25_carry_eqn = VD1_un50_hilo_carry_24;
|
| 25904 |
|
|
VD1_un50_hilo_add25 = VD1_hilo_57 $ VD1_nop2_reged[25] $ VD1_un50_hilo_add25_carry_eqn;
|
| 25905 |
|
|
|
| 25906 |
|
|
--VD1_un50_hilo_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_25
|
| 25907 |
|
|
--operation mode is arithmetic
|
| 25908 |
|
|
|
| 25909 |
|
|
VD1_un50_hilo_carry_25 = CARRY(VD1_hilo_57 & !VD1_nop2_reged[25] & !VD1_un50_hilo_carry_24 # !VD1_hilo_57 & !VD1_un50_hilo_carry_24 # !VD1_nop2_reged[25]);
|
| 25910 |
|
|
|
| 25911 |
|
|
|
| 25912 |
|
|
--VD1_hilo_37_iv_0_5_a[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[57]
|
| 25913 |
|
|
--operation mode is normal
|
| 25914 |
|
|
|
| 25915 |
|
|
VD1_hilo_37_iv_0_5_a[57] = VD1_hilo_58 & !VD1_un59_hilo_add26 & VD1_hilo_37_iv_0_a6_1_0[40] # !VD1_hilo_58 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_un59_hilo_add26 & VD1_hilo_37_iv_0_a6_1_0[40];
|
| 25916 |
|
|
|
| 25917 |
|
|
|
| 25918 |
|
|
--PD1_a_o_3_d_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[25]
|
| 25919 |
|
|
--operation mode is normal
|
| 25920 |
|
|
|
| 25921 |
|
|
PD1_a_o_3_d_a[25] = PD1_a_o_sn_m2 & !PB1_r32_o_25 # !PD1_a_o_sn_m2 & !AB1_r32_o_23;
|
| 25922 |
|
|
|
| 25923 |
|
|
|
| 25924 |
|
|
--VD1_un59_hilo_add23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add23
|
| 25925 |
|
|
--operation mode is arithmetic
|
| 25926 |
|
|
|
| 25927 |
|
|
VD1_un59_hilo_add23_carry_eqn = VD1_un59_hilo_carry_22;
|
| 25928 |
|
|
VD1_un59_hilo_add23 = VD1_hilo_55 $ VD1_op2_reged[23] $ VD1_un59_hilo_add23_carry_eqn;
|
| 25929 |
|
|
|
| 25930 |
|
|
--VD1_un59_hilo_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_23
|
| 25931 |
|
|
--operation mode is arithmetic
|
| 25932 |
|
|
|
| 25933 |
|
|
VD1_un59_hilo_carry_23 = CARRY(VD1_hilo_55 & !VD1_op2_reged[23] & !VD1_un59_hilo_carry_22 # !VD1_hilo_55 & !VD1_un59_hilo_carry_22 # !VD1_op2_reged[23]);
|
| 25934 |
|
|
|
| 25935 |
|
|
|
| 25936 |
|
|
--VD1_un1_op2_reged_1_combout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[22]
|
| 25937 |
|
|
--operation mode is normal
|
| 25938 |
|
|
|
| 25939 |
|
|
VD1_un1_op2_reged_1_combout[22] = VD1_eqop2_2_32 & VD1_op2_reged[22] # !VD1_eqop2_2_32 & VD1_nop2_reged[22];
|
| 25940 |
|
|
|
| 25941 |
|
|
|
| 25942 |
|
|
--KB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_22
|
| 25943 |
|
|
--operation mode is normal
|
| 25944 |
|
|
|
| 25945 |
|
|
KB1_r32_o_22_lut_out = DD1_pc_next_0_iv_1_22 # DD1_un1_pc_next46_0 & DD1_un1_pc_add22;
|
| 25946 |
|
|
KB1_r32_o_22 = DFFEAS(KB1_r32_o_22_lut_out, E1__clk0, VCC, , , , , , );
|
| 25947 |
|
|
|
| 25948 |
|
|
|
| 25949 |
|
|
--KB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_23
|
| 25950 |
|
|
--operation mode is normal
|
| 25951 |
|
|
|
| 25952 |
|
|
KB1_r32_o_23_lut_out = DD1_pc_next_0_iv_1_23 # DD1_un1_pc_next46_0 & DD1_un1_pc_add23;
|
| 25953 |
|
|
KB1_r32_o_23 = DFFEAS(KB1_r32_o_23_lut_out, E1__clk0, VCC, , , , , , );
|
| 25954 |
|
|
|
| 25955 |
|
|
|
| 25956 |
|
|
--PD1_a_o_3_d_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[22]
|
| 25957 |
|
|
--operation mode is normal
|
| 25958 |
|
|
|
| 25959 |
|
|
PD1_a_o_3_d_a[22] = PD1_a_o_sn_m2 & !PB1_r32_o_22 # !PD1_a_o_sn_m2 & !AB1_r32_o_20;
|
| 25960 |
|
|
|
| 25961 |
|
|
|
| 25962 |
|
|
--VD1_hilo_33_i_m_a[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[55]
|
| 25963 |
|
|
--operation mode is normal
|
| 25964 |
|
|
|
| 25965 |
|
|
VD1_hilo_33_i_m_a[55] = VD1_addnop2 & !VD1_un50_hilo_add23 # !VD1_addnop2 & !VD1_un59_hilo_add23;
|
| 25966 |
|
|
|
| 25967 |
|
|
|
| 25968 |
|
|
--VD1_hilo_24_add23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add23
|
| 25969 |
|
|
--operation mode is arithmetic
|
| 25970 |
|
|
|
| 25971 |
|
|
VD1_hilo_24_add23_carry_eqn = VD1_hilo_24_carry_22;
|
| 25972 |
|
|
VD1_hilo_24_add23 = VD1_hilo_54 $ VD1_un1_op2_reged_1_combout[23] $ VD1_hilo_24_add23_carry_eqn;
|
| 25973 |
|
|
|
| 25974 |
|
|
--VD1_hilo_24_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_23
|
| 25975 |
|
|
--operation mode is arithmetic
|
| 25976 |
|
|
|
| 25977 |
|
|
VD1_hilo_24_carry_23 = CARRY(VD1_hilo_54 & !VD1_un1_op2_reged_1_combout[23] & !VD1_hilo_24_carry_22 # !VD1_hilo_54 & !VD1_hilo_24_carry_22 # !VD1_un1_op2_reged_1_combout[23]);
|
| 25978 |
|
|
|
| 25979 |
|
|
|
| 25980 |
|
|
--VD1_hilo_22_a[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[55]
|
| 25981 |
|
|
--operation mode is normal
|
| 25982 |
|
|
|
| 25983 |
|
|
VD1_hilo_22_a[55] = VD1_sign & !VD1_hilo_56 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add24 # !VD1_hilo[0] & !VD1_hilo_56;
|
| 25984 |
|
|
|
| 25985 |
|
|
|
| 25986 |
|
|
--VD1_hilo_15_2[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[55]
|
| 25987 |
|
|
--operation mode is normal
|
| 25988 |
|
|
|
| 25989 |
|
|
VD1_hilo_15_2[55] = VD1_sub_or_yn & VD1_un59_hilo_add24 # !VD1_sub_or_yn & VD1_un50_hilo_add24;
|
| 25990 |
|
|
|
| 25991 |
|
|
|
| 25992 |
|
|
--PD1_a_o_3_d_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[23]
|
| 25993 |
|
|
--operation mode is normal
|
| 25994 |
|
|
|
| 25995 |
|
|
PD1_a_o_3_d_a[23] = PD1_a_o_sn_m2 & !PB1_r32_o_23 # !PD1_a_o_sn_m2 & !AB1_r32_o_21;
|
| 25996 |
|
|
|
| 25997 |
|
|
|
| 25998 |
|
|
--UB1_dout_2_i_i_x[22] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[22]
|
| 25999 |
|
|
--operation mode is normal
|
| 26000 |
|
|
|
| 26001 |
|
|
UB1_dout_2_i_i_x[22] = UB1_dout_2_i_i_a2[16] # JE1_q_b[6] & UB1_dout_2_i_i_a3_0[16];
|
| 26002 |
|
|
|
| 26003 |
|
|
|
| 26004 |
|
|
--WB72L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_22__Z|lpm_latch:U1|q[0]~56
|
| 26005 |
|
|
--operation mode is normal
|
| 26006 |
|
|
|
| 26007 |
|
|
WB72L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[22] # !UB1_un1_byte_addr_2 & WB72L1;
|
| 26008 |
|
|
|
| 26009 |
|
|
|
| 26010 |
|
|
--UB1_dout_2_i_i_x[21] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[21]
|
| 26011 |
|
|
--operation mode is normal
|
| 26012 |
|
|
|
| 26013 |
|
|
UB1_dout_2_i_i_x[21] = UB1_dout_2_i_i_a2[16] # JE1_q_b[5] & UB1_dout_2_i_i_a3_0[16];
|
| 26014 |
|
|
|
| 26015 |
|
|
|
| 26016 |
|
|
--WB62L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_21__Z|lpm_latch:U1|q[0]~56
|
| 26017 |
|
|
--operation mode is normal
|
| 26018 |
|
|
|
| 26019 |
|
|
WB62L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[21] # !UB1_un1_byte_addr_2 & WB62L1;
|
| 26020 |
|
|
|
| 26021 |
|
|
|
| 26022 |
|
|
--UB1_dout_2_i_i_x[19] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[19]
|
| 26023 |
|
|
--operation mode is normal
|
| 26024 |
|
|
|
| 26025 |
|
|
UB1_dout_2_i_i_x[19] = UB1_dout_2_i_i_a2[16] # JE1_q_b[3] & UB1_dout_2_i_i_a3_0[16];
|
| 26026 |
|
|
|
| 26027 |
|
|
|
| 26028 |
|
|
--WB42L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_19__Z|lpm_latch:U1|q[0]~56
|
| 26029 |
|
|
--operation mode is normal
|
| 26030 |
|
|
|
| 26031 |
|
|
WB42L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[19] # !UB1_un1_byte_addr_2 & WB42L1;
|
| 26032 |
|
|
|
| 26033 |
|
|
|
| 26034 |
|
|
--UB1_dout_2_i_i_x[18] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[18]
|
| 26035 |
|
|
--operation mode is normal
|
| 26036 |
|
|
|
| 26037 |
|
|
UB1_dout_2_i_i_x[18] = UB1_dout_2_i_i_a2[16] # JE1_q_b[2] & UB1_dout_2_i_i_a3_0[16];
|
| 26038 |
|
|
|
| 26039 |
|
|
|
| 26040 |
|
|
--WB32L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_18__Z|lpm_latch:U1|q[0]~56
|
| 26041 |
|
|
--operation mode is normal
|
| 26042 |
|
|
|
| 26043 |
|
|
WB32L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[18] # !UB1_un1_byte_addr_2 & WB32L1;
|
| 26044 |
|
|
|
| 26045 |
|
|
|
| 26046 |
|
|
--UB1_dout_2_i_i_x[17] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[17]
|
| 26047 |
|
|
--operation mode is normal
|
| 26048 |
|
|
|
| 26049 |
|
|
UB1_dout_2_i_i_x[17] = UB1_dout_2_i_i_a2[16] # JE1_q_b[1] & UB1_dout_2_i_i_a3_0[16];
|
| 26050 |
|
|
|
| 26051 |
|
|
|
| 26052 |
|
|
--WB22L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_17__Z|lpm_latch:U1|q[0]~56
|
| 26053 |
|
|
--operation mode is normal
|
| 26054 |
|
|
|
| 26055 |
|
|
WB22L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[17] # !UB1_un1_byte_addr_2 & WB22L1;
|
| 26056 |
|
|
|
| 26057 |
|
|
|
| 26058 |
|
|
--UB1_dout_2_i_i_x[16] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[16]
|
| 26059 |
|
|
--operation mode is normal
|
| 26060 |
|
|
|
| 26061 |
|
|
UB1_dout_2_i_i_x[16] = UB1_dout_2_i_i_a2[16] # JE1_q_b[0] & UB1_dout_2_i_i_a3_0[16];
|
| 26062 |
|
|
|
| 26063 |
|
|
|
| 26064 |
|
|
--WB12L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_16__Z|lpm_latch:U1|q[0]~56
|
| 26065 |
|
|
--operation mode is normal
|
| 26066 |
|
|
|
| 26067 |
|
|
WB12L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[16] # !UB1_un1_byte_addr_2 & WB12L1;
|
| 26068 |
|
|
|
| 26069 |
|
|
|
| 26070 |
|
|
--DD1_un1_pc_prectl_1_0_a4[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[29]
|
| 26071 |
|
|
--operation mode is normal
|
| 26072 |
|
|
|
| 26073 |
|
|
DD1_un1_pc_prectl_1_0_a4[29] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_a3_0 # ED1_r32_o_13 & CD1_res_7_0_0_a2_16;
|
| 26074 |
|
|
|
| 26075 |
|
|
|
| 26076 |
|
|
--DD1_pc_next_0_iv_1_a[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[28]
|
| 26077 |
|
|
--operation mode is normal
|
| 26078 |
|
|
|
| 26079 |
|
|
DD1_pc_next_0_iv_1_a[28] = KB1_r32_o_28 & !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_28 # !KB1_r32_o_28 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_28;
|
| 26080 |
|
|
|
| 26081 |
|
|
|
| 26082 |
|
|
--PB1_dout_iv_28 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_28
|
| 26083 |
|
|
--operation mode is normal
|
| 26084 |
|
|
|
| 26085 |
|
|
PB1_dout_iv_28 = HD1_dout_iv_1_28 # FD1_wb_o_28 & HD1_dout7_0_a2;
|
| 26086 |
|
|
|
| 26087 |
|
|
--PB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_28
|
| 26088 |
|
|
--operation mode is normal
|
| 26089 |
|
|
|
| 26090 |
|
|
PB1_r32_o_28 = DFFEAS(PB1_dout_iv_28, E1__clk0, VCC, , , , , , );
|
| 26091 |
|
|
|
| 26092 |
|
|
|
| 26093 |
|
|
--DD1_un1_pc_prectl_1_0_a4[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[28]
|
| 26094 |
|
|
--operation mode is normal
|
| 26095 |
|
|
|
| 26096 |
|
|
DD1_un1_pc_prectl_1_0_a4[28] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_a3_0 # ED1_r32_o_12 & CD1_res_7_0_0_a2_16;
|
| 26097 |
|
|
|
| 26098 |
|
|
|
| 26099 |
|
|
--DD1_un1_pc_add27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add27
|
| 26100 |
|
|
--operation mode is arithmetic
|
| 26101 |
|
|
|
| 26102 |
|
|
DD1_un1_pc_add27_carry_eqn = DD1_un1_pc_carry_26;
|
| 26103 |
|
|
DD1_un1_pc_add27 = KB1_r32_o_27 $ DD1_un1_pc_prectl_1_0_a4[27] $ DD1_un1_pc_add27_carry_eqn;
|
| 26104 |
|
|
|
| 26105 |
|
|
--DD1_un1_pc_carry_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_27
|
| 26106 |
|
|
--operation mode is arithmetic
|
| 26107 |
|
|
|
| 26108 |
|
|
DD1_un1_pc_carry_27 = CARRY(KB1_r32_o_27 & !DD1_un1_pc_prectl_1_0_a4[27] & !DD1_un1_pc_carry_26 # !KB1_r32_o_27 & !DD1_un1_pc_carry_26 # !DD1_un1_pc_prectl_1_0_a4[27]);
|
| 26109 |
|
|
|
| 26110 |
|
|
|
| 26111 |
|
|
--DD1_pc_next_0_iv_1_a[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[29]
|
| 26112 |
|
|
--operation mode is normal
|
| 26113 |
|
|
|
| 26114 |
|
|
DD1_pc_next_0_iv_1_a[29] = KB1_r32_o_29 & !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_29 # !KB1_r32_o_29 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_29;
|
| 26115 |
|
|
|
| 26116 |
|
|
|
| 26117 |
|
|
--PB1_dout_iv_29 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_29
|
| 26118 |
|
|
--operation mode is normal
|
| 26119 |
|
|
|
| 26120 |
|
|
PB1_dout_iv_29 = HD1_dout_iv_1_29 # FD1_wb_o_29 & HD1_dout7_0_a2;
|
| 26121 |
|
|
|
| 26122 |
|
|
--PB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_29
|
| 26123 |
|
|
--operation mode is normal
|
| 26124 |
|
|
|
| 26125 |
|
|
PB1_r32_o_29 = DFFEAS(PB1_dout_iv_29, E1__clk0, VCC, , , , , , );
|
| 26126 |
|
|
|
| 26127 |
|
|
|
| 26128 |
|
|
--DD1_pc_next_0_iv_1_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_26
|
| 26129 |
|
|
--operation mode is normal
|
| 26130 |
|
|
|
| 26131 |
|
|
DD1_pc_next_0_iv_1_26 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_26 # !DD1_pc_next_0_iv_1_a[26];
|
| 26132 |
|
|
|
| 26133 |
|
|
|
| 26134 |
|
|
--DD1_un1_pc_add26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add26
|
| 26135 |
|
|
--operation mode is arithmetic
|
| 26136 |
|
|
|
| 26137 |
|
|
DD1_un1_pc_add26_carry_eqn = DD1_un1_pc_carry_25;
|
| 26138 |
|
|
DD1_un1_pc_add26 = KB1_r32_o_26 $ DD1_un1_pc_prectl_1_0_a4[26] $ !DD1_un1_pc_add26_carry_eqn;
|
| 26139 |
|
|
|
| 26140 |
|
|
--DD1_un1_pc_carry_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_26
|
| 26141 |
|
|
--operation mode is arithmetic
|
| 26142 |
|
|
|
| 26143 |
|
|
DD1_un1_pc_carry_26 = CARRY(KB1_r32_o_26 & DD1_un1_pc_prectl_1_0_a4[26] # !DD1_un1_pc_carry_25 # !KB1_r32_o_26 & DD1_un1_pc_prectl_1_0_a4[26] & !DD1_un1_pc_carry_25);
|
| 26144 |
|
|
|
| 26145 |
|
|
|
| 26146 |
|
|
--DD1_pc_next_0_iv_1_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_27
|
| 26147 |
|
|
--operation mode is normal
|
| 26148 |
|
|
|
| 26149 |
|
|
DD1_pc_next_0_iv_1_27 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_27 # !DD1_pc_next_0_iv_1_a[27];
|
| 26150 |
|
|
|
| 26151 |
|
|
|
| 26152 |
|
|
--LD2_q_b[31] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[31]
|
| 26153 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 26154 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 26155 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 26156 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 26157 |
|
|
LD2_q_b[31]_PORT_A_data_in = FD1_wb_o_31;
|
| 26158 |
|
|
LD2_q_b[31]_PORT_A_data_in_reg = DFFE(LD2_q_b[31]_PORT_A_data_in, LD2_q_b[31]_clock_0, , , );
|
| 26159 |
|
|
LD2_q_b[31]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 26160 |
|
|
LD2_q_b[31]_PORT_A_address_reg = DFFE(LD2_q_b[31]_PORT_A_address, LD2_q_b[31]_clock_0, , , );
|
| 26161 |
|
|
LD2_q_b[31]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 26162 |
|
|
LD2_q_b[31]_PORT_B_address_reg = DFFE(LD2_q_b[31]_PORT_B_address, LD2_q_b[31]_clock_1, , , );
|
| 26163 |
|
|
LD2_q_b[31]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 26164 |
|
|
LD2_q_b[31]_PORT_A_write_enable_reg = DFFE(LD2_q_b[31]_PORT_A_write_enable, LD2_q_b[31]_clock_0, , , );
|
| 26165 |
|
|
LD2_q_b[31]_PORT_B_read_enable = VCC;
|
| 26166 |
|
|
LD2_q_b[31]_PORT_B_read_enable_reg = DFFE(LD2_q_b[31]_PORT_B_read_enable, LD2_q_b[31]_clock_1, , , );
|
| 26167 |
|
|
LD2_q_b[31]_clock_0 = E1__clk0;
|
| 26168 |
|
|
LD2_q_b[31]_clock_1 = E1__clk0;
|
| 26169 |
|
|
LD2_q_b[31]_PORT_B_data_out = MEMORY(LD2_q_b[31]_PORT_A_data_in_reg, , LD2_q_b[31]_PORT_A_address_reg, LD2_q_b[31]_PORT_B_address_reg, LD2_q_b[31]_PORT_A_write_enable_reg, LD2_q_b[31]_PORT_B_read_enable_reg, , , LD2_q_b[31]_clock_0, LD2_q_b[31]_clock_1, , , , );
|
| 26170 |
|
|
LD2_q_b[31] = LD2_q_b[31]_PORT_B_data_out[0];
|
| 26171 |
|
|
|
| 26172 |
|
|
|
| 26173 |
|
|
--UB1_dout_2_i_i_a3_0[16] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3_0[16]
|
| 26174 |
|
|
--operation mode is normal
|
| 26175 |
|
|
|
| 26176 |
|
|
UB1_dout_2_i_i_a3_0[16] = RB1_ctl_o_1 & RB1_ctl_o_2 & RB1_byte_addr_o_0 # !RB1_ctl_o_3;
|
| 26177 |
|
|
|
| 26178 |
|
|
|
| 26179 |
|
|
--UB1_dout_2_i_i_a2[16] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2[16]
|
| 26180 |
|
|
--operation mode is normal
|
| 26181 |
|
|
|
| 26182 |
|
|
UB1_dout_2_i_i_a2[16] = !RB1_ctl_o_2 & UB1_dout_2_i_i_a3[15] # UB1_dout_2_i_i_a2_a[16] & UB1_dout_2_i_i_a3_1[15];
|
| 26183 |
|
|
|
| 26184 |
|
|
|
| 26185 |
|
|
--UB1_un1_ctl_6_2_0_a is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_ctl_6_2_0_a
|
| 26186 |
|
|
--operation mode is normal
|
| 26187 |
|
|
|
| 26188 |
|
|
UB1_un1_ctl_6_2_0_a = RB1_ctl_o_1 & !RB1_ctl_o_3 # !RB1_ctl_o_1 & RB1_ctl_o_3 & !RB1_ctl_o_2;
|
| 26189 |
|
|
|
| 26190 |
|
|
|
| 26191 |
|
|
--UB1_dout_2_i_i_x[30] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[30]
|
| 26192 |
|
|
--operation mode is normal
|
| 26193 |
|
|
|
| 26194 |
|
|
UB1_dout_2_i_i_x[30] = UB1_dout_2_i_i_a2[16] # KE1_q_b[6] & UB1_dout_2_i_i_a3_0[16];
|
| 26195 |
|
|
|
| 26196 |
|
|
|
| 26197 |
|
|
--WB53L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_30__Z|lpm_latch:U1|q[0]~56
|
| 26198 |
|
|
--operation mode is normal
|
| 26199 |
|
|
|
| 26200 |
|
|
WB53L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[30] # !UB1_un1_byte_addr_2 & WB53L1;
|
| 26201 |
|
|
|
| 26202 |
|
|
|
| 26203 |
|
|
--TD1_lt_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_24
|
| 26204 |
|
|
--operation mode is arithmetic
|
| 26205 |
|
|
|
| 26206 |
|
|
TD1_lt_24 = CARRY(PD1_a_o_24 & VD1_b_o_iv_24 & !TD1_lt_23 # !PD1_a_o_24 & VD1_b_o_iv_24 # !TD1_lt_23);
|
| 26207 |
|
|
|
| 26208 |
|
|
|
| 26209 |
|
|
--TD1_sum_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_25
|
| 26210 |
|
|
--operation mode is arithmetic
|
| 26211 |
|
|
|
| 26212 |
|
|
TD1_sum_carry_25 = CARRY(VD1_b_o_iv_25 & !TD1_sum_carry_24 # !PD1_a_o_25 # !VD1_b_o_iv_25 & !PD1_a_o_25 & !TD1_sum_carry_24);
|
| 26213 |
|
|
|
| 26214 |
|
|
|
| 26215 |
|
|
--UB1_dout_2_i_i_x[28] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[28]
|
| 26216 |
|
|
--operation mode is normal
|
| 26217 |
|
|
|
| 26218 |
|
|
UB1_dout_2_i_i_x[28] = UB1_dout_2_i_i_a2[16] # KE1_q_b[4] & UB1_dout_2_i_i_a3_0[16];
|
| 26219 |
|
|
|
| 26220 |
|
|
|
| 26221 |
|
|
--WB33L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_28__Z|lpm_latch:U1|q[0]~56
|
| 26222 |
|
|
--operation mode is normal
|
| 26223 |
|
|
|
| 26224 |
|
|
WB33L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[28] # !UB1_un1_byte_addr_2 & WB33L1;
|
| 26225 |
|
|
|
| 26226 |
|
|
|
| 26227 |
|
|
--UB1_dout_2_i_i_x[29] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[29]
|
| 26228 |
|
|
--operation mode is normal
|
| 26229 |
|
|
|
| 26230 |
|
|
UB1_dout_2_i_i_x[29] = UB1_dout_2_i_i_a2[16] # KE1_q_b[5] & UB1_dout_2_i_i_a3_0[16];
|
| 26231 |
|
|
|
| 26232 |
|
|
|
| 26233 |
|
|
--WB43L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_29__Z|lpm_latch:U1|q[0]~56
|
| 26234 |
|
|
--operation mode is normal
|
| 26235 |
|
|
|
| 26236 |
|
|
WB43L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[29] # !UB1_un1_byte_addr_2 & WB43L1;
|
| 26237 |
|
|
|
| 26238 |
|
|
|
| 26239 |
|
|
--UB1_dout_2_0_0_o2_0_a[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_o2_0_a[9]
|
| 26240 |
|
|
--operation mode is normal
|
| 26241 |
|
|
|
| 26242 |
|
|
UB1_dout_2_0_0_o2_0_a[9] = RB1_ctl_o_1 & !RB1_ctl_o_3 # !RB1_ctl_o_1 & RB1_ctl_o_2;
|
| 26243 |
|
|
|
| 26244 |
|
|
|
| 26245 |
|
|
--UB1_dout_2_0_0_o2_1[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_o2_1[9]
|
| 26246 |
|
|
--operation mode is normal
|
| 26247 |
|
|
|
| 26248 |
|
|
UB1_dout_2_0_0_o2_1[9] = RB1_ctl_o_2 & RB1_ctl_o_1 & RB1_byte_addr_o_0 # !UB1_dout_2_0_0_o2_1_a[9] # !RB1_ctl_o_2 & !RB1_byte_addr_o_0 & !UB1_dout_2_0_0_o2_1_a[9];
|
| 26249 |
|
|
|
| 26250 |
|
|
|
| 26251 |
|
|
--UB1_dout_2_0_0_a2_1_a[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a2_1_a[9]
|
| 26252 |
|
|
--operation mode is normal
|
| 26253 |
|
|
|
| 26254 |
|
|
UB1_dout_2_0_0_a2_1_a[9] = RB1_ctl_o_1 & !RB1_ctl_o_3;
|
| 26255 |
|
|
|
| 26256 |
|
|
|
| 26257 |
|
|
--UB1_dout_2_i_i_a3[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3[15]
|
| 26258 |
|
|
--operation mode is normal
|
| 26259 |
|
|
|
| 26260 |
|
|
UB1_dout_2_i_i_a3[15] = RB1_ctl_o_1 & RB1_byte_addr_o_0 & !UB1_dout_2_i_i_a3_a_x[15];
|
| 26261 |
|
|
|
| 26262 |
|
|
|
| 26263 |
|
|
--UB1_dout_2_i_i_a3_1[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3_1[15]
|
| 26264 |
|
|
--operation mode is normal
|
| 26265 |
|
|
|
| 26266 |
|
|
UB1_dout_2_i_i_a3_1[15] = !RB1_byte_addr_o_0 & RB1_byte_addr_o_1 & HE1_q_b[7] # !RB1_byte_addr_o_1 & KE1_q_b[7];
|
| 26267 |
|
|
|
| 26268 |
|
|
|
| 26269 |
|
|
--YB1_pc_gen_ctl_2_i_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a[2]
|
| 26270 |
|
|
--operation mode is normal
|
| 26271 |
|
|
|
| 26272 |
|
|
YB1_pc_gen_ctl_2_i_0_a[2] = !WB26L2 & YB1_cmp_ctl_2_0_0_a2_0[0] # KE1_q_a[2] & YB1_alu_we_1s_1_o2_0_x[0];
|
| 26273 |
|
|
|
| 26274 |
|
|
|
| 26275 |
|
|
--YB1_pc_gen_ctl_2_i_0_5[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_5[2]
|
| 26276 |
|
|
--operation mode is normal
|
| 26277 |
|
|
|
| 26278 |
|
|
YB1_pc_gen_ctl_2_i_0_5[2] = YB1_pc_gen_ctl_2_i_0_a3_5[2] # YB1_pc_gen_ctl_2_i_0_a3[2] # YB1_pc_gen_ctl_2_i_0_1_x[2] # !YB1_pc_gen_ctl_2_i_0_5_a[2];
|
| 26279 |
|
|
|
| 26280 |
|
|
|
| 26281 |
|
|
--YB1_pc_gen_ctl_2_i_m3_0_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_a_x[0]
|
| 26282 |
|
|
--operation mode is normal
|
| 26283 |
|
|
|
| 26284 |
|
|
YB1_pc_gen_ctl_2_i_m3_0_a_x[0] = !KE1_q_a[4] & !KE1_q_a[7];
|
| 26285 |
|
|
|
| 26286 |
|
|
|
| 26287 |
|
|
--YB1_pc_gen_ctl_2_i_m3_0_5[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_5[0]
|
| 26288 |
|
|
--operation mode is normal
|
| 26289 |
|
|
|
| 26290 |
|
|
YB1_pc_gen_ctl_2_i_m3_0_5[0] = YB1_pc_gen_ctl_2_i_m3_0_2[0] # !KE1_q_a[4] & !YB1_pc_gen_ctl_2_i_m3_0_5_a[0] # !YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0];
|
| 26291 |
|
|
|
| 26292 |
|
|
|
| 26293 |
|
|
--YB1_pc_gen_ctl_2_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_0_0_a[1]
|
| 26294 |
|
|
--operation mode is normal
|
| 26295 |
|
|
|
| 26296 |
|
|
YB1_pc_gen_ctl_2_0_0_a[1] = !YB1_pc_gen_ctl_2_0_0_a3[1] & !YB1_fsm_dly_2_0_0_a2_0[2] # !JE1_q_a[7] # !YB1_alu_func_2_0_0_a2_0[1];
|
| 26297 |
|
|
|
| 26298 |
|
|
|
| 26299 |
|
|
--YB1_cmp_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_0
|
| 26300 |
|
|
--operation mode is normal
|
| 26301 |
|
|
|
| 26302 |
|
|
YB1_cmp_ctl_2_0_0_0 = YB1_cmp_ctl_2_0_0_1_Z[0] # YB1_alu_func_2_0_0_a2_0[1] & YB1_cmp_ctl_2_0_0_a2_1[0] & WB34L1;
|
| 26303 |
|
|
|
| 26304 |
|
|
|
| 26305 |
|
|
--WB34L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_|lpm_latch:U1|q[0]~56
|
| 26306 |
|
|
--operation mode is normal
|
| 26307 |
|
|
|
| 26308 |
|
|
WB34L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_cmp_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB34L1;
|
| 26309 |
|
|
|
| 26310 |
|
|
|
| 26311 |
|
|
--BD1_res_2_NE_12_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_12_0
|
| 26312 |
|
|
--operation mode is normal
|
| 26313 |
|
|
|
| 26314 |
|
|
BD1_res_2_NE_12_0 = BD1_res_2_NE_16 # BD1_res_2_NE_17 # BD1_res_2_NE_7_0;
|
| 26315 |
|
|
|
| 26316 |
|
|
|
| 26317 |
|
|
--BD1_res_2_NE_9_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_9_0
|
| 26318 |
|
|
--operation mode is normal
|
| 26319 |
|
|
|
| 26320 |
|
|
BD1_res_2_NE_9_0 = BD1_res_2_NE_4 # BD1_res_2_NE_5 # BD1_res_2_NE_1;
|
| 26321 |
|
|
|
| 26322 |
|
|
|
| 26323 |
|
|
--BD1_res_2_NE_11_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_11_0
|
| 26324 |
|
|
--operation mode is normal
|
| 26325 |
|
|
|
| 26326 |
|
|
BD1_res_2_NE_11_0 = BD1_N_18 # BD1_res_2_NE_13 # BD1_N_16 # BD1_N_17;
|
| 26327 |
|
|
|
| 26328 |
|
|
|
| 26329 |
|
|
--BD1_res_2_NE_10_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_10_0
|
| 26330 |
|
|
--operation mode is normal
|
| 26331 |
|
|
|
| 26332 |
|
|
BD1_res_2_NE_10_0 = BD1_res_2_NE_8 # BD1_N_15 # BD1_res_2_NE_6 # BD1_N_13;
|
| 26333 |
|
|
|
| 26334 |
|
|
|
| 26335 |
|
|
--BD1_un10_res_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_27
|
| 26336 |
|
|
--operation mode is normal
|
| 26337 |
|
|
|
| 26338 |
|
|
BD1_un10_res_27 = BD1_un10_res_16 # BD1_un10_res_17 # BD1_un10_res_23;
|
| 26339 |
|
|
|
| 26340 |
|
|
|
| 26341 |
|
|
--BD1_un10_res_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_28
|
| 26342 |
|
|
--operation mode is normal
|
| 26343 |
|
|
|
| 26344 |
|
|
BD1_un10_res_28 = BD1_un10_res_18 # BD1_un10_res_19 # BD1_un10_res_20 # BD1_un10_res_21;
|
| 26345 |
|
|
|
| 26346 |
|
|
|
| 26347 |
|
|
--UB1_dout_2_0_0[10] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0[10]
|
| 26348 |
|
|
--operation mode is normal
|
| 26349 |
|
|
|
| 26350 |
|
|
UB1_dout_2_0_0[10] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[2] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_0_0_a_x[10];
|
| 26351 |
|
|
|
| 26352 |
|
|
|
| 26353 |
|
|
--WB51L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_10__Z|lpm_latch:U1|q[0]~56
|
| 26354 |
|
|
--operation mode is normal
|
| 26355 |
|
|
|
| 26356 |
|
|
WB51L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_0_0[10] # !UB1_un1_byte_addr_2 & WB51L1;
|
| 26357 |
|
|
|
| 26358 |
|
|
|
| 26359 |
|
|
--UB1_dout_2_i_i[11] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[11]
|
| 26360 |
|
|
--operation mode is normal
|
| 26361 |
|
|
|
| 26362 |
|
|
UB1_dout_2_i_i[11] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[3] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_i_i_a_x[11];
|
| 26363 |
|
|
|
| 26364 |
|
|
|
| 26365 |
|
|
--WB61L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_11__Z|lpm_latch:U1|q[0]~56
|
| 26366 |
|
|
--operation mode is normal
|
| 26367 |
|
|
|
| 26368 |
|
|
WB61L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[11] # !UB1_un1_byte_addr_2 & WB61L1;
|
| 26369 |
|
|
|
| 26370 |
|
|
|
| 26371 |
|
|
--UB1_dout_2_0_0[12] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0[12]
|
| 26372 |
|
|
--operation mode is normal
|
| 26373 |
|
|
|
| 26374 |
|
|
UB1_dout_2_0_0[12] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[4] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_0_0_a_x[12];
|
| 26375 |
|
|
|
| 26376 |
|
|
|
| 26377 |
|
|
--WB71L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_12__Z|lpm_latch:U1|q[0]~56
|
| 26378 |
|
|
--operation mode is normal
|
| 26379 |
|
|
|
| 26380 |
|
|
WB71L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_0_0[12] # !UB1_un1_byte_addr_2 & WB71L1;
|
| 26381 |
|
|
|
| 26382 |
|
|
|
| 26383 |
|
|
--UB1_dout_2_i_i[23] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[23]
|
| 26384 |
|
|
--operation mode is normal
|
| 26385 |
|
|
|
| 26386 |
|
|
UB1_dout_2_i_i[23] = JE1_q_b[7] & UB1_dout_2_i_i_a3_0[16] # !RB1_ctl_o_2 & !UB1_dout_2_i_i_a[23] # !JE1_q_b[7] & !RB1_ctl_o_2 & !UB1_dout_2_i_i_a[23];
|
| 26387 |
|
|
|
| 26388 |
|
|
|
| 26389 |
|
|
--WB82L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_23__Z|lpm_latch:U1|q[0]~56
|
| 26390 |
|
|
--operation mode is normal
|
| 26391 |
|
|
|
| 26392 |
|
|
WB82L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[23] # !UB1_un1_byte_addr_2 & WB82L1;
|
| 26393 |
|
|
|
| 26394 |
|
|
|
| 26395 |
|
|
--UB1_dout_2_i_i[13] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[13]
|
| 26396 |
|
|
--operation mode is normal
|
| 26397 |
|
|
|
| 26398 |
|
|
UB1_dout_2_i_i[13] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[5] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_i_i_a_x[13];
|
| 26399 |
|
|
|
| 26400 |
|
|
|
| 26401 |
|
|
--WB81L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_13__Z|lpm_latch:U1|q[0]~56
|
| 26402 |
|
|
--operation mode is normal
|
| 26403 |
|
|
|
| 26404 |
|
|
WB81L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[13] # !UB1_un1_byte_addr_2 & WB81L1;
|
| 26405 |
|
|
|
| 26406 |
|
|
|
| 26407 |
|
|
--UB1_dout_2_i_i[14] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[14]
|
| 26408 |
|
|
--operation mode is normal
|
| 26409 |
|
|
|
| 26410 |
|
|
UB1_dout_2_i_i[14] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[6] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_i_i_a_x[14];
|
| 26411 |
|
|
|
| 26412 |
|
|
|
| 26413 |
|
|
--WB91L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_14__Z|lpm_latch:U1|q[0]~56
|
| 26414 |
|
|
--operation mode is normal
|
| 26415 |
|
|
|
| 26416 |
|
|
WB91L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[14] # !UB1_un1_byte_addr_2 & WB91L1;
|
| 26417 |
|
|
|
| 26418 |
|
|
|
| 26419 |
|
|
--UB1_dout_2_i_i_x[25] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[25]
|
| 26420 |
|
|
--operation mode is normal
|
| 26421 |
|
|
|
| 26422 |
|
|
UB1_dout_2_i_i_x[25] = UB1_dout_2_i_i_a2[16] # KE1_q_b[1] & UB1_dout_2_i_i_a3_0[16];
|
| 26423 |
|
|
|
| 26424 |
|
|
|
| 26425 |
|
|
--WB03L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_25__Z|lpm_latch:U1|q[0]~56
|
| 26426 |
|
|
--operation mode is normal
|
| 26427 |
|
|
|
| 26428 |
|
|
WB03L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[25] # !UB1_un1_byte_addr_2 & WB03L1;
|
| 26429 |
|
|
|
| 26430 |
|
|
|
| 26431 |
|
|
--UB1_dout_2_i_i_x[26] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[26]
|
| 26432 |
|
|
--operation mode is normal
|
| 26433 |
|
|
|
| 26434 |
|
|
UB1_dout_2_i_i_x[26] = UB1_dout_2_i_i_a2[16] # KE1_q_b[2] & UB1_dout_2_i_i_a3_0[16];
|
| 26435 |
|
|
|
| 26436 |
|
|
|
| 26437 |
|
|
--WB13L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_26__Z|lpm_latch:U1|q[0]~56
|
| 26438 |
|
|
--operation mode is normal
|
| 26439 |
|
|
|
| 26440 |
|
|
WB13L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[26] # !UB1_un1_byte_addr_2 & WB13L1;
|
| 26441 |
|
|
|
| 26442 |
|
|
|
| 26443 |
|
|
--YB1_muxa_ctl_2_0_0_a2_0_0[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a2_0_0[1]
|
| 26444 |
|
|
--operation mode is normal
|
| 26445 |
|
|
|
| 26446 |
|
|
YB1_muxa_ctl_2_0_0_a2_0_0[1] = !KE1_q_a[6] & !KE1_q_a[2] & YB1_muxa_ctl_2_0_0_a2_0_0_a_x[1] # !GE1_q_a[3];
|
| 26447 |
|
|
|
| 26448 |
|
|
|
| 26449 |
|
|
--YB1_ext_ctl_2_i_m3_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_0_a[0]
|
| 26450 |
|
|
--operation mode is normal
|
| 26451 |
|
|
|
| 26452 |
|
|
YB1_ext_ctl_2_i_m3_0_0_a[0] = GE1_q_a[3] & !GE1_q_a[0] & !KE1_q_a[7] & YB1_alu_func_2_0_0_a2_1[4];
|
| 26453 |
|
|
|
| 26454 |
|
|
|
| 26455 |
|
|
--FD1_un23_qa_i_0_a2_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un23_qa_i_0_a2_a
|
| 26456 |
|
|
--operation mode is normal
|
| 26457 |
|
|
|
| 26458 |
|
|
FD1_un23_qa_i_0_a2_a = !FD1_r_rdaddress_a[2] & !FD1_r_rdaddress_a[3];
|
| 26459 |
|
|
|
| 26460 |
|
|
|
| 26461 |
|
|
--UB1_dout_2_i_i[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[15]
|
| 26462 |
|
|
--operation mode is normal
|
| 26463 |
|
|
|
| 26464 |
|
|
UB1_dout_2_i_i[15] = UB1_dout_2_i_i_1[15] # !RB1_ctl_o_2 & UB1_dout_2_i_i_a3_1[15];
|
| 26465 |
|
|
|
| 26466 |
|
|
|
| 26467 |
|
|
--WB02L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_15__Z|lpm_latch:U1|q[0]~56
|
| 26468 |
|
|
--operation mode is normal
|
| 26469 |
|
|
|
| 26470 |
|
|
WB02L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[15] # !UB1_un1_byte_addr_2 & WB02L1;
|
| 26471 |
|
|
|
| 26472 |
|
|
|
| 26473 |
|
|
--UB1_dout_2_i_i_x[27] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[27]
|
| 26474 |
|
|
--operation mode is normal
|
| 26475 |
|
|
|
| 26476 |
|
|
UB1_dout_2_i_i_x[27] = UB1_dout_2_i_i_a2[16] # KE1_q_b[3] & UB1_dout_2_i_i_a3_0[16];
|
| 26477 |
|
|
|
| 26478 |
|
|
|
| 26479 |
|
|
--WB23L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_27__Z|lpm_latch:U1|q[0]~56
|
| 26480 |
|
|
--operation mode is normal
|
| 26481 |
|
|
|
| 26482 |
|
|
WB23L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[27] # !UB1_un1_byte_addr_2 & WB23L1;
|
| 26483 |
|
|
|
| 26484 |
|
|
|
| 26485 |
|
|
--VD1_count[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[0]
|
| 26486 |
|
|
--operation mode is arithmetic
|
| 26487 |
|
|
|
| 26488 |
|
|
VD1_count[0]_lut_out = VD1_count[0] $ VD1_un1_rdy_0_sqmuxa_3_combout;
|
| 26489 |
|
|
VD1_count[0] = DFFEAS(VD1_count[0]_lut_out, E1__clk0, VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
|
| 26490 |
|
|
|
| 26491 |
|
|
--VD1_count_cout[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[0]
|
| 26492 |
|
|
--operation mode is arithmetic
|
| 26493 |
|
|
|
| 26494 |
|
|
VD1_count_cout[0] = CARRY(VD1_count[0] & VD1_un1_rdy_0_sqmuxa_3_combout);
|
| 26495 |
|
|
|
| 26496 |
|
|
|
| 26497 |
|
|
--VD1_over_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_28
|
| 26498 |
|
|
--operation mode is arithmetic
|
| 26499 |
|
|
|
| 26500 |
|
|
VD1_over_carry_28 = CARRY(VD1_b_o_iv_28 & PD1_a_o_28 & !VD1_over_carry_27 # !VD1_b_o_iv_28 & PD1_a_o_28 # !VD1_over_carry_27);
|
| 26501 |
|
|
|
| 26502 |
|
|
|
| 26503 |
|
|
--VD1_eqop2_2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_0
|
| 26504 |
|
|
--operation mode is normal
|
| 26505 |
|
|
|
| 26506 |
|
|
VD1_eqop2_2_0 = VD1_op2_reged[0] $ VD1_hilo[32];
|
| 26507 |
|
|
|
| 26508 |
|
|
|
| 26509 |
|
|
--VD1_eqop2_2_NE_125_i_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_125_i_a2
|
| 26510 |
|
|
--operation mode is normal
|
| 26511 |
|
|
|
| 26512 |
|
|
VD1_eqop2_2_NE_125_i_a2 = VD1_op2_reged[14] & VD1_hilo_46 & VD1_op2_reged[30] $ !VD1_hilo_62 # !VD1_op2_reged[14] & !VD1_hilo_46 & VD1_op2_reged[30] $ !VD1_hilo_62;
|
| 26513 |
|
|
|
| 26514 |
|
|
|
| 26515 |
|
|
--VD1_nop2_reged[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[11]
|
| 26516 |
|
|
--operation mode is arithmetic
|
| 26517 |
|
|
|
| 26518 |
|
|
VD1_nop2_reged[11]_carry_eqn = VD1_nop2_reged_cout[9];
|
| 26519 |
|
|
VD1_nop2_reged[11] = VD1_op2_reged[11] $ (VD1_op2_reged[10] # !VD1_nop2_reged[11]_carry_eqn);
|
| 26520 |
|
|
|
| 26521 |
|
|
--VD1_nop2_reged_cout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[11]
|
| 26522 |
|
|
--operation mode is arithmetic
|
| 26523 |
|
|
|
| 26524 |
|
|
VD1_nop2_reged_cout[11] = CARRY(VD1_op2_reged[11] # VD1_op2_reged[10] # !VD1_nop2_reged_cout[9]);
|
| 26525 |
|
|
|
| 26526 |
|
|
|
| 26527 |
|
|
--VD1_nop2_reged[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[12]
|
| 26528 |
|
|
--operation mode is arithmetic
|
| 26529 |
|
|
|
| 26530 |
|
|
VD1_nop2_reged[12]_carry_eqn = VD1_nop2_reged_cout[10];
|
| 26531 |
|
|
VD1_nop2_reged[12] = VD1_op2_reged[12] $ VD1_nop2_reged[12]_carry_eqn;
|
| 26532 |
|
|
|
| 26533 |
|
|
--VD1_nop2_reged_cout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[12]
|
| 26534 |
|
|
--operation mode is arithmetic
|
| 26535 |
|
|
|
| 26536 |
|
|
VD1_nop2_reged_cout[12] = CARRY(!VD1_op2_reged[13] & !VD1_op2_reged[12] & !VD1_nop2_reged_cout[10]);
|
| 26537 |
|
|
|
| 26538 |
|
|
|
| 26539 |
|
|
--VD1_nop2_reged[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[10]
|
| 26540 |
|
|
--operation mode is arithmetic
|
| 26541 |
|
|
|
| 26542 |
|
|
VD1_nop2_reged[10]_carry_eqn = VD1_nop2_reged_cout[8];
|
| 26543 |
|
|
VD1_nop2_reged[10] = VD1_op2_reged[10] $ !VD1_nop2_reged[10]_carry_eqn;
|
| 26544 |
|
|
|
| 26545 |
|
|
--VD1_nop2_reged_cout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[10]
|
| 26546 |
|
|
--operation mode is arithmetic
|
| 26547 |
|
|
|
| 26548 |
|
|
VD1_nop2_reged_cout[10] = CARRY(VD1_op2_reged[11] # VD1_op2_reged[10] # !VD1_nop2_reged_cout[8]);
|
| 26549 |
|
|
|
| 26550 |
|
|
|
| 26551 |
|
|
--VD1_nop2_reged[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[25]
|
| 26552 |
|
|
--operation mode is arithmetic
|
| 26553 |
|
|
|
| 26554 |
|
|
VD1_nop2_reged[25]_carry_eqn = VD1_nop2_reged_cout[23];
|
| 26555 |
|
|
VD1_nop2_reged[25] = VD1_op2_reged[25] $ (VD1_op2_reged[24] # VD1_nop2_reged[25]_carry_eqn);
|
| 26556 |
|
|
|
| 26557 |
|
|
--VD1_nop2_reged_cout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[25]
|
| 26558 |
|
|
--operation mode is arithmetic
|
| 26559 |
|
|
|
| 26560 |
|
|
VD1_nop2_reged_cout[25] = CARRY(!VD1_op2_reged[25] & !VD1_op2_reged[24] & !VD1_nop2_reged_cout[23]);
|
| 26561 |
|
|
|
| 26562 |
|
|
|
| 26563 |
|
|
--UB1_dout_2_i_i_x[24] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[24]
|
| 26564 |
|
|
--operation mode is normal
|
| 26565 |
|
|
|
| 26566 |
|
|
UB1_dout_2_i_i_x[24] = UB1_dout_2_i_i_a2[16] # KE1_q_b[0] & UB1_dout_2_i_i_a3_0[16];
|
| 26567 |
|
|
|
| 26568 |
|
|
|
| 26569 |
|
|
--WB92L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_24__Z|lpm_latch:U1|q[0]~56
|
| 26570 |
|
|
--operation mode is normal
|
| 26571 |
|
|
|
| 26572 |
|
|
WB92L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[24] # !UB1_un1_byte_addr_2 & WB92L1;
|
| 26573 |
|
|
|
| 26574 |
|
|
|
| 26575 |
|
|
--DD1_pc_next_0_iv_1_a[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[16]
|
| 26576 |
|
|
--operation mode is normal
|
| 26577 |
|
|
|
| 26578 |
|
|
DD1_pc_next_0_iv_1_a[16] = SD1_r32_o_16 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_16 # !SD1_r32_o_16 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_16;
|
| 26579 |
|
|
|
| 26580 |
|
|
|
| 26581 |
|
|
--DD1_un1_pc_prectl_1_0_a4[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[16]
|
| 26582 |
|
|
--operation mode is normal
|
| 26583 |
|
|
|
| 26584 |
|
|
DD1_un1_pc_prectl_1_0_a4[16] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_0_14 # ED1_r32_o_14 & CD1_res_7_0_0_o3_0;
|
| 26585 |
|
|
|
| 26586 |
|
|
|
| 26587 |
|
|
--DD1_pc_next_0_iv_1_a[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[17]
|
| 26588 |
|
|
--operation mode is normal
|
| 26589 |
|
|
|
| 26590 |
|
|
DD1_pc_next_0_iv_1_a[17] = SD1_r32_o_17 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_17 # !SD1_r32_o_17 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_17;
|
| 26591 |
|
|
|
| 26592 |
|
|
|
| 26593 |
|
|
--DD1_un1_pc_prectl_1_0_a4[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[17]
|
| 26594 |
|
|
--operation mode is normal
|
| 26595 |
|
|
|
| 26596 |
|
|
DD1_un1_pc_prectl_1_0_a4[17] = FB1_res_7_0_0_17 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 26597 |
|
|
|
| 26598 |
|
|
|
| 26599 |
|
|
--HD1_dout_iv_1_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_16
|
| 26600 |
|
|
--operation mode is normal
|
| 26601 |
|
|
|
| 26602 |
|
|
HD1_dout_iv_1_16 = FD1_N_18_i_0_s3 & LD2_q_b[16] # !HD1_dout_iv_1_a[16];
|
| 26603 |
|
|
|
| 26604 |
|
|
|
| 26605 |
|
|
--HD1_dout_iv_1_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_17
|
| 26606 |
|
|
--operation mode is normal
|
| 26607 |
|
|
|
| 26608 |
|
|
HD1_dout_iv_1_17 = FD1_N_18_i_0_s3 & LD2_q_b[17] # !HD1_dout_iv_1_a[17];
|
| 26609 |
|
|
|
| 26610 |
|
|
|
| 26611 |
|
|
--DD1_pc_next_0_iv_1_a[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[14]
|
| 26612 |
|
|
--operation mode is normal
|
| 26613 |
|
|
|
| 26614 |
|
|
DD1_pc_next_0_iv_1_a[14] = SD1_r32_o_14 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_14 # !SD1_r32_o_14 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_14;
|
| 26615 |
|
|
|
| 26616 |
|
|
|
| 26617 |
|
|
--DD1_un1_pc_prectl_1_0_a4[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[14]
|
| 26618 |
|
|
--operation mode is normal
|
| 26619 |
|
|
|
| 26620 |
|
|
DD1_un1_pc_prectl_1_0_a4[14] = FB1_res_7_0_0_14 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 26621 |
|
|
|
| 26622 |
|
|
|
| 26623 |
|
|
--DD1_pc_next_0_iv_1_a[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[15]
|
| 26624 |
|
|
--operation mode is normal
|
| 26625 |
|
|
|
| 26626 |
|
|
DD1_pc_next_0_iv_1_a[15] = SD1_r32_o_15 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_15 # !SD1_r32_o_15 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_15;
|
| 26627 |
|
|
|
| 26628 |
|
|
|
| 26629 |
|
|
--DD1_un1_pc_prectl_1_0_a4[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[15]
|
| 26630 |
|
|
--operation mode is normal
|
| 26631 |
|
|
|
| 26632 |
|
|
DD1_un1_pc_prectl_1_0_a4[15] = FB1_res_7_0_0_15 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 26633 |
|
|
|
| 26634 |
|
|
|
| 26635 |
|
|
--HD1_dout_iv_1_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_14
|
| 26636 |
|
|
--operation mode is normal
|
| 26637 |
|
|
|
| 26638 |
|
|
HD1_dout_iv_1_14 = FD1_N_18_i_0_s3 & LD2_q_b[14] # !HD1_dout_iv_1_a[14];
|
| 26639 |
|
|
|
| 26640 |
|
|
|
| 26641 |
|
|
--HD1_dout_iv_1_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_15
|
| 26642 |
|
|
--operation mode is normal
|
| 26643 |
|
|
|
| 26644 |
|
|
HD1_dout_iv_1_15 = FD1_N_18_i_0_s3 & LD2_q_b[15] # !HD1_dout_iv_1_a[15];
|
| 26645 |
|
|
|
| 26646 |
|
|
|
| 26647 |
|
|
--VD1_un1_op2_reged_1_combout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[9]
|
| 26648 |
|
|
--operation mode is normal
|
| 26649 |
|
|
|
| 26650 |
|
|
VD1_un1_op2_reged_1_combout[9] = VD1_eqop2_2_32 & VD1_op2_reged[9] # !VD1_eqop2_2_32 & VD1_nop2_reged[9];
|
| 26651 |
|
|
|
| 26652 |
|
|
|
| 26653 |
|
|
--VD1_un59_hilo_add10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add10
|
| 26654 |
|
|
--operation mode is arithmetic
|
| 26655 |
|
|
|
| 26656 |
|
|
VD1_un59_hilo_add10_carry_eqn = VD1_un59_hilo_carry_9;
|
| 26657 |
|
|
VD1_un59_hilo_add10 = VD1_hilo_42 $ VD1_op2_reged[10] $ !VD1_un59_hilo_add10_carry_eqn;
|
| 26658 |
|
|
|
| 26659 |
|
|
--VD1_un59_hilo_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_10
|
| 26660 |
|
|
--operation mode is arithmetic
|
| 26661 |
|
|
|
| 26662 |
|
|
VD1_un59_hilo_carry_10 = CARRY(VD1_hilo_42 & VD1_op2_reged[10] # !VD1_un59_hilo_carry_9 # !VD1_hilo_42 & VD1_op2_reged[10] & !VD1_un59_hilo_carry_9);
|
| 26663 |
|
|
|
| 26664 |
|
|
|
| 26665 |
|
|
--VD1_un50_hilo_add10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add10
|
| 26666 |
|
|
--operation mode is arithmetic
|
| 26667 |
|
|
|
| 26668 |
|
|
VD1_un50_hilo_add10_carry_eqn = VD1_un50_hilo_carry_9;
|
| 26669 |
|
|
VD1_un50_hilo_add10 = VD1_hilo_42 $ VD1_nop2_reged[10] $ !VD1_un50_hilo_add10_carry_eqn;
|
| 26670 |
|
|
|
| 26671 |
|
|
--VD1_un50_hilo_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_10
|
| 26672 |
|
|
--operation mode is arithmetic
|
| 26673 |
|
|
|
| 26674 |
|
|
VD1_un50_hilo_carry_10 = CARRY(VD1_hilo_42 & VD1_nop2_reged[10] # !VD1_un50_hilo_carry_9 # !VD1_hilo_42 & VD1_nop2_reged[10] & !VD1_un50_hilo_carry_9);
|
| 26675 |
|
|
|
| 26676 |
|
|
|
| 26677 |
|
|
--VD1_un1_op2_reged_1_combout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[10]
|
| 26678 |
|
|
--operation mode is normal
|
| 26679 |
|
|
|
| 26680 |
|
|
VD1_un1_op2_reged_1_combout[10] = VD1_eqop2_2_32 & VD1_op2_reged[10] # !VD1_eqop2_2_32 & VD1_nop2_reged[10];
|
| 26681 |
|
|
|
| 26682 |
|
|
|
| 26683 |
|
|
--VD1_un59_hilo_add11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add11
|
| 26684 |
|
|
--operation mode is arithmetic
|
| 26685 |
|
|
|
| 26686 |
|
|
VD1_un59_hilo_add11_carry_eqn = VD1_un59_hilo_carry_10;
|
| 26687 |
|
|
VD1_un59_hilo_add11 = VD1_hilo_43 $ VD1_op2_reged[11] $ VD1_un59_hilo_add11_carry_eqn;
|
| 26688 |
|
|
|
| 26689 |
|
|
--VD1_un59_hilo_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_11
|
| 26690 |
|
|
--operation mode is arithmetic
|
| 26691 |
|
|
|
| 26692 |
|
|
VD1_un59_hilo_carry_11 = CARRY(VD1_hilo_43 & !VD1_op2_reged[11] & !VD1_un59_hilo_carry_10 # !VD1_hilo_43 & !VD1_un59_hilo_carry_10 # !VD1_op2_reged[11]);
|
| 26693 |
|
|
|
| 26694 |
|
|
|
| 26695 |
|
|
--VD1_un50_hilo_add11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add11
|
| 26696 |
|
|
--operation mode is arithmetic
|
| 26697 |
|
|
|
| 26698 |
|
|
VD1_un50_hilo_add11_carry_eqn = VD1_un50_hilo_carry_10;
|
| 26699 |
|
|
VD1_un50_hilo_add11 = VD1_hilo_43 $ VD1_nop2_reged[11] $ VD1_un50_hilo_add11_carry_eqn;
|
| 26700 |
|
|
|
| 26701 |
|
|
--VD1_un50_hilo_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_11
|
| 26702 |
|
|
--operation mode is arithmetic
|
| 26703 |
|
|
|
| 26704 |
|
|
VD1_un50_hilo_carry_11 = CARRY(VD1_hilo_43 & !VD1_nop2_reged[11] & !VD1_un50_hilo_carry_10 # !VD1_hilo_43 & !VD1_un50_hilo_carry_10 # !VD1_nop2_reged[11]);
|
| 26705 |
|
|
|
| 26706 |
|
|
|
| 26707 |
|
|
--VD1_un1_op2_reged_1_combout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[11]
|
| 26708 |
|
|
--operation mode is normal
|
| 26709 |
|
|
|
| 26710 |
|
|
VD1_un1_op2_reged_1_combout[11] = VD1_eqop2_2_32 & VD1_op2_reged[11] # !VD1_eqop2_2_32 & VD1_nop2_reged[11];
|
| 26711 |
|
|
|
| 26712 |
|
|
|
| 26713 |
|
|
--VD1_un59_hilo_add12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add12
|
| 26714 |
|
|
--operation mode is arithmetic
|
| 26715 |
|
|
|
| 26716 |
|
|
VD1_un59_hilo_add12_carry_eqn = VD1_un59_hilo_carry_11;
|
| 26717 |
|
|
VD1_un59_hilo_add12 = VD1_hilo_44 $ VD1_op2_reged[12] $ !VD1_un59_hilo_add12_carry_eqn;
|
| 26718 |
|
|
|
| 26719 |
|
|
--VD1_un59_hilo_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_12
|
| 26720 |
|
|
--operation mode is arithmetic
|
| 26721 |
|
|
|
| 26722 |
|
|
VD1_un59_hilo_carry_12 = CARRY(VD1_hilo_44 & VD1_op2_reged[12] # !VD1_un59_hilo_carry_11 # !VD1_hilo_44 & VD1_op2_reged[12] & !VD1_un59_hilo_carry_11);
|
| 26723 |
|
|
|
| 26724 |
|
|
|
| 26725 |
|
|
--DD1_pc_next_0_iv_1_a[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[20]
|
| 26726 |
|
|
--operation mode is normal
|
| 26727 |
|
|
|
| 26728 |
|
|
DD1_pc_next_0_iv_1_a[20] = SD1_r32_o_20 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_20 # !SD1_r32_o_20 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_20;
|
| 26729 |
|
|
|
| 26730 |
|
|
|
| 26731 |
|
|
--DD1_un1_pc_prectl_1_0_a4[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[20]
|
| 26732 |
|
|
--operation mode is normal
|
| 26733 |
|
|
|
| 26734 |
|
|
DD1_un1_pc_prectl_1_0_a4[20] = FB1_res_7_0_0_20 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 26735 |
|
|
|
| 26736 |
|
|
|
| 26737 |
|
|
--DD1_un1_pc_add19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add19
|
| 26738 |
|
|
--operation mode is arithmetic
|
| 26739 |
|
|
|
| 26740 |
|
|
DD1_un1_pc_add19_carry_eqn = DD1_un1_pc_carry_18;
|
| 26741 |
|
|
DD1_un1_pc_add19 = KB1_r32_o_19 $ DD1_un1_pc_prectl_1_0_a4[19] $ DD1_un1_pc_add19_carry_eqn;
|
| 26742 |
|
|
|
| 26743 |
|
|
--DD1_un1_pc_carry_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_19
|
| 26744 |
|
|
--operation mode is arithmetic
|
| 26745 |
|
|
|
| 26746 |
|
|
DD1_un1_pc_carry_19 = CARRY(KB1_r32_o_19 & !DD1_un1_pc_prectl_1_0_a4[19] & !DD1_un1_pc_carry_18 # !KB1_r32_o_19 & !DD1_un1_pc_carry_18 # !DD1_un1_pc_prectl_1_0_a4[19]);
|
| 26747 |
|
|
|
| 26748 |
|
|
|
| 26749 |
|
|
--DD1_pc_next_0_iv_1_a[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[21]
|
| 26750 |
|
|
--operation mode is normal
|
| 26751 |
|
|
|
| 26752 |
|
|
DD1_pc_next_0_iv_1_a[21] = SD1_r32_o_21 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_21 # !SD1_r32_o_21 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_21;
|
| 26753 |
|
|
|
| 26754 |
|
|
|
| 26755 |
|
|
--DD1_un1_pc_prectl_1_0_a4[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[21]
|
| 26756 |
|
|
--operation mode is normal
|
| 26757 |
|
|
|
| 26758 |
|
|
DD1_un1_pc_prectl_1_0_a4[21] = FB1_res_7_0_0_21 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 26759 |
|
|
|
| 26760 |
|
|
|
| 26761 |
|
|
--DD1_pc_next_0_iv_1_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_18
|
| 26762 |
|
|
--operation mode is normal
|
| 26763 |
|
|
|
| 26764 |
|
|
DD1_pc_next_0_iv_1_18 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_18 # !DD1_pc_next_0_iv_1_a[18];
|
| 26765 |
|
|
|
| 26766 |
|
|
|
| 26767 |
|
|
--DD1_un1_pc_add18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add18
|
| 26768 |
|
|
--operation mode is arithmetic
|
| 26769 |
|
|
|
| 26770 |
|
|
DD1_un1_pc_add18_carry_eqn = DD1_un1_pc_carry_17;
|
| 26771 |
|
|
DD1_un1_pc_add18 = KB1_r32_o_18 $ DD1_un1_pc_prectl_1_0_a4[18] $ !DD1_un1_pc_add18_carry_eqn;
|
| 26772 |
|
|
|
| 26773 |
|
|
--DD1_un1_pc_carry_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_18
|
| 26774 |
|
|
--operation mode is arithmetic
|
| 26775 |
|
|
|
| 26776 |
|
|
DD1_un1_pc_carry_18 = CARRY(KB1_r32_o_18 & DD1_un1_pc_prectl_1_0_a4[18] # !DD1_un1_pc_carry_17 # !KB1_r32_o_18 & DD1_un1_pc_prectl_1_0_a4[18] & !DD1_un1_pc_carry_17);
|
| 26777 |
|
|
|
| 26778 |
|
|
|
| 26779 |
|
|
--DD1_pc_next_0_iv_1_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_19
|
| 26780 |
|
|
--operation mode is normal
|
| 26781 |
|
|
|
| 26782 |
|
|
DD1_pc_next_0_iv_1_19 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_19 # !DD1_pc_next_0_iv_1_a[19];
|
| 26783 |
|
|
|
| 26784 |
|
|
|
| 26785 |
|
|
--HD1_dout_iv_1_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_21
|
| 26786 |
|
|
--operation mode is normal
|
| 26787 |
|
|
|
| 26788 |
|
|
HD1_dout_iv_1_21 = FD1_N_18_i_0_s3 & LD2_q_b[21] # !HD1_dout_iv_1_a[21];
|
| 26789 |
|
|
|
| 26790 |
|
|
|
| 26791 |
|
|
--HD1_dout_iv_1_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_20
|
| 26792 |
|
|
--operation mode is normal
|
| 26793 |
|
|
|
| 26794 |
|
|
HD1_dout_iv_1_20 = FD1_N_18_i_0_s3 & LD2_q_b[20] # !HD1_dout_iv_1_a[20];
|
| 26795 |
|
|
|
| 26796 |
|
|
|
| 26797 |
|
|
--VD1_hilo_37_iv_0_2_a[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2_a[51]
|
| 26798 |
|
|
--operation mode is normal
|
| 26799 |
|
|
|
| 26800 |
|
|
VD1_hilo_37_iv_0_2_a[51] = VD1_hilo_19 & !VD1_un59_hilo_add19 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_hilo_19 & VD1_hilo_0_sqmuxa # !VD1_un59_hilo_add19 & VD1_hilo_37_iv_0_a3_2[62];
|
| 26801 |
|
|
|
| 26802 |
|
|
|
| 26803 |
|
|
--PB1_dout_iv_19 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_19
|
| 26804 |
|
|
--operation mode is normal
|
| 26805 |
|
|
|
| 26806 |
|
|
PB1_dout_iv_19 = HD1_dout_iv_1_19 # FD1_wb_o_19 & HD1_dout7_0_a2;
|
| 26807 |
|
|
|
| 26808 |
|
|
--PB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_19
|
| 26809 |
|
|
--operation mode is normal
|
| 26810 |
|
|
|
| 26811 |
|
|
PB1_r32_o_19 = DFFEAS(PB1_dout_iv_19, E1__clk0, VCC, , , , , , );
|
| 26812 |
|
|
|
| 26813 |
|
|
|
| 26814 |
|
|
--PB1_dout_iv_18 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_18
|
| 26815 |
|
|
--operation mode is normal
|
| 26816 |
|
|
|
| 26817 |
|
|
PB1_dout_iv_18 = HD1_dout_iv_1_18 # FD1_wb_o_18 & HD1_dout7_0_a2;
|
| 26818 |
|
|
|
| 26819 |
|
|
--PB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_18
|
| 26820 |
|
|
--operation mode is normal
|
| 26821 |
|
|
|
| 26822 |
|
|
PB1_r32_o_18 = DFFEAS(PB1_dout_iv_18, E1__clk0, VCC, , , , , , );
|
| 26823 |
|
|
|
| 26824 |
|
|
|
| 26825 |
|
|
--VD1_un1_op2_reged_1_combout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[25]
|
| 26826 |
|
|
--operation mode is normal
|
| 26827 |
|
|
|
| 26828 |
|
|
VD1_un1_op2_reged_1_combout[25] = VD1_eqop2_2_32 & VD1_op2_reged[25] # !VD1_eqop2_2_32 & VD1_nop2_reged[25];
|
| 26829 |
|
|
|
| 26830 |
|
|
|
| 26831 |
|
|
--VD1_un59_hilo_add27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add27
|
| 26832 |
|
|
--operation mode is arithmetic
|
| 26833 |
|
|
|
| 26834 |
|
|
VD1_un59_hilo_add27_carry_eqn = VD1_un59_hilo_carry_26;
|
| 26835 |
|
|
VD1_un59_hilo_add27 = VD1_hilo_59 $ VD1_op2_reged[27] $ VD1_un59_hilo_add27_carry_eqn;
|
| 26836 |
|
|
|
| 26837 |
|
|
--VD1_un59_hilo_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_27
|
| 26838 |
|
|
--operation mode is arithmetic
|
| 26839 |
|
|
|
| 26840 |
|
|
VD1_un59_hilo_carry_27 = CARRY(VD1_hilo_59 & !VD1_op2_reged[27] & !VD1_un59_hilo_carry_26 # !VD1_hilo_59 & !VD1_un59_hilo_carry_26 # !VD1_op2_reged[27]);
|
| 26841 |
|
|
|
| 26842 |
|
|
|
| 26843 |
|
|
--VD1_un59_hilo_add25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add25
|
| 26844 |
|
|
--operation mode is arithmetic
|
| 26845 |
|
|
|
| 26846 |
|
|
VD1_un59_hilo_add25_carry_eqn = VD1_un59_hilo_carry_24;
|
| 26847 |
|
|
VD1_un59_hilo_add25 = VD1_hilo_57 $ VD1_op2_reged[25] $ VD1_un59_hilo_add25_carry_eqn;
|
| 26848 |
|
|
|
| 26849 |
|
|
--VD1_un59_hilo_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_25
|
| 26850 |
|
|
--operation mode is arithmetic
|
| 26851 |
|
|
|
| 26852 |
|
|
VD1_un59_hilo_carry_25 = CARRY(VD1_hilo_57 & !VD1_op2_reged[25] & !VD1_un59_hilo_carry_24 # !VD1_hilo_57 & !VD1_un59_hilo_carry_24 # !VD1_op2_reged[25]);
|
| 26853 |
|
|
|
| 26854 |
|
|
|
| 26855 |
|
|
--PB1_dout_iv_26 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_26
|
| 26856 |
|
|
--operation mode is normal
|
| 26857 |
|
|
|
| 26858 |
|
|
PB1_dout_iv_26 = HD1_dout_iv_1_26 # FD1_wb_o_26 & HD1_dout7_0_a2;
|
| 26859 |
|
|
|
| 26860 |
|
|
--PB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_26
|
| 26861 |
|
|
--operation mode is normal
|
| 26862 |
|
|
|
| 26863 |
|
|
PB1_r32_o_26 = DFFEAS(PB1_dout_iv_26, E1__clk0, VCC, , , , , , );
|
| 26864 |
|
|
|
| 26865 |
|
|
|
| 26866 |
|
|
--VD1_hilo_37_iv_0_a5_0[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a5_0[59]
|
| 26867 |
|
|
--operation mode is normal
|
| 26868 |
|
|
|
| 26869 |
|
|
VD1_hilo_37_iv_0_a5_0[59] = !VD1_hilo_59 & VD1_hilo_37_iv_0_a3_1[62];
|
| 26870 |
|
|
|
| 26871 |
|
|
|
| 26872 |
|
|
--VD1_hilo_37_iv_0_1[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[59]
|
| 26873 |
|
|
--operation mode is normal
|
| 26874 |
|
|
|
| 26875 |
|
|
VD1_hilo_37_iv_0_1[59] = VD1_hilo_37_iv_0_0[59] # !VD1_un59_hilo_add27 & VD1_hilo_37_iv_0_a3_2[62];
|
| 26876 |
|
|
|
| 26877 |
|
|
|
| 26878 |
|
|
--PB1_dout_iv_27 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_27
|
| 26879 |
|
|
--operation mode is normal
|
| 26880 |
|
|
|
| 26881 |
|
|
PB1_dout_iv_27 = HD1_dout_iv_1_27 # FD1_wb_o_27 & HD1_dout7_0_a2;
|
| 26882 |
|
|
|
| 26883 |
|
|
--PB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_27
|
| 26884 |
|
|
--operation mode is normal
|
| 26885 |
|
|
|
| 26886 |
|
|
PB1_r32_o_27 = DFFEAS(PB1_dout_iv_27, E1__clk0, VCC, , , , , , );
|
| 26887 |
|
|
|
| 26888 |
|
|
|
| 26889 |
|
|
--VD1_hilo_37_iv_0_6[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6[60]
|
| 26890 |
|
|
--operation mode is normal
|
| 26891 |
|
|
|
| 26892 |
|
|
VD1_hilo_37_iv_0_6[60] = VD1_hilo_37_iv_0_3[60] # VD1_hilo_37_iv_0_6_a[60] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add29;
|
| 26893 |
|
|
|
| 26894 |
|
|
|
| 26895 |
|
|
--VD1_hilo_37_iv_0_a5_0[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a5_0[61]
|
| 26896 |
|
|
--operation mode is normal
|
| 26897 |
|
|
|
| 26898 |
|
|
VD1_hilo_37_iv_0_a5_0[61] = !VD1_hilo_61 & VD1_hilo_37_iv_0_a3_1[62];
|
| 26899 |
|
|
|
| 26900 |
|
|
|
| 26901 |
|
|
--VD1_hilo_37_iv_0_1[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[61]
|
| 26902 |
|
|
--operation mode is normal
|
| 26903 |
|
|
|
| 26904 |
|
|
VD1_hilo_37_iv_0_1[61] = VD1_hilo_37_iv_0_0[61] # !VD1_un59_hilo_add29 & VD1_hilo_37_iv_0_a3_2[62];
|
| 26905 |
|
|
|
| 26906 |
|
|
|
| 26907 |
|
|
--DD1_pc_next_0_iv_1_a[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[13]
|
| 26908 |
|
|
--operation mode is normal
|
| 26909 |
|
|
|
| 26910 |
|
|
DD1_pc_next_0_iv_1_a[13] = SD1_r32_o_13 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_13 # !SD1_r32_o_13 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_13;
|
| 26911 |
|
|
|
| 26912 |
|
|
|
| 26913 |
|
|
--DD1_un1_pc_prectl_1_0_a4[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[13]
|
| 26914 |
|
|
--operation mode is normal
|
| 26915 |
|
|
|
| 26916 |
|
|
DD1_un1_pc_prectl_1_0_a4[13] = FB1_res_7_0_0_13 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 26917 |
|
|
|
| 26918 |
|
|
|
| 26919 |
|
|
--HD1_dout_iv_1_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_13
|
| 26920 |
|
|
--operation mode is normal
|
| 26921 |
|
|
|
| 26922 |
|
|
HD1_dout_iv_1_13 = FD1_N_18_i_0_s3 & LD2_q_b[13] # !HD1_dout_iv_1_a[13];
|
| 26923 |
|
|
|
| 26924 |
|
|
|
| 26925 |
|
|
--HD1_dout_iv_1_a[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[30]
|
| 26926 |
|
|
--operation mode is normal
|
| 26927 |
|
|
|
| 26928 |
|
|
HD1_dout_iv_1_a[30] = FD1_r_data_30 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_28 # !FD1_r_data_30 & !YD1_mux_fw_1 # !AB1_r32_o_28;
|
| 26929 |
|
|
|
| 26930 |
|
|
|
| 26931 |
|
|
--LD2_q_b[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[30]
|
| 26932 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 26933 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 26934 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 26935 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 26936 |
|
|
LD2_q_b[30]_PORT_A_data_in = FD1_wb_o_30;
|
| 26937 |
|
|
LD2_q_b[30]_PORT_A_data_in_reg = DFFE(LD2_q_b[30]_PORT_A_data_in, LD2_q_b[30]_clock_0, , , );
|
| 26938 |
|
|
LD2_q_b[30]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 26939 |
|
|
LD2_q_b[30]_PORT_A_address_reg = DFFE(LD2_q_b[30]_PORT_A_address, LD2_q_b[30]_clock_0, , , );
|
| 26940 |
|
|
LD2_q_b[30]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 26941 |
|
|
LD2_q_b[30]_PORT_B_address_reg = DFFE(LD2_q_b[30]_PORT_B_address, LD2_q_b[30]_clock_1, , , );
|
| 26942 |
|
|
LD2_q_b[30]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 26943 |
|
|
LD2_q_b[30]_PORT_A_write_enable_reg = DFFE(LD2_q_b[30]_PORT_A_write_enable, LD2_q_b[30]_clock_0, , , );
|
| 26944 |
|
|
LD2_q_b[30]_PORT_B_read_enable = VCC;
|
| 26945 |
|
|
LD2_q_b[30]_PORT_B_read_enable_reg = DFFE(LD2_q_b[30]_PORT_B_read_enable, LD2_q_b[30]_clock_1, , , );
|
| 26946 |
|
|
LD2_q_b[30]_clock_0 = E1__clk0;
|
| 26947 |
|
|
LD2_q_b[30]_clock_1 = E1__clk0;
|
| 26948 |
|
|
LD2_q_b[30]_PORT_B_data_out = MEMORY(LD2_q_b[30]_PORT_A_data_in_reg, , LD2_q_b[30]_PORT_A_address_reg, LD2_q_b[30]_PORT_B_address_reg, LD2_q_b[30]_PORT_A_write_enable_reg, LD2_q_b[30]_PORT_B_read_enable_reg, , , LD2_q_b[30]_clock_0, LD2_q_b[30]_clock_1, , , , );
|
| 26949 |
|
|
LD2_q_b[30] = LD2_q_b[30]_PORT_B_data_out[0];
|
| 26950 |
|
|
|
| 26951 |
|
|
|
| 26952 |
|
|
--VD1_un59_hilo_add24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add24
|
| 26953 |
|
|
--operation mode is arithmetic
|
| 26954 |
|
|
|
| 26955 |
|
|
VD1_un59_hilo_add24_carry_eqn = VD1_un59_hilo_carry_23;
|
| 26956 |
|
|
VD1_un59_hilo_add24 = VD1_hilo_56 $ VD1_op2_reged[24] $ !VD1_un59_hilo_add24_carry_eqn;
|
| 26957 |
|
|
|
| 26958 |
|
|
--VD1_un59_hilo_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_24
|
| 26959 |
|
|
--operation mode is arithmetic
|
| 26960 |
|
|
|
| 26961 |
|
|
VD1_un59_hilo_carry_24 = CARRY(VD1_hilo_56 & VD1_op2_reged[24] # !VD1_un59_hilo_carry_23 # !VD1_hilo_56 & VD1_op2_reged[24] & !VD1_un59_hilo_carry_23);
|
| 26962 |
|
|
|
| 26963 |
|
|
|
| 26964 |
|
|
--VD1_un50_hilo_add24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add24
|
| 26965 |
|
|
--operation mode is arithmetic
|
| 26966 |
|
|
|
| 26967 |
|
|
VD1_un50_hilo_add24_carry_eqn = VD1_un50_hilo_carry_23;
|
| 26968 |
|
|
VD1_un50_hilo_add24 = VD1_hilo_56 $ VD1_nop2_reged[24] $ !VD1_un50_hilo_add24_carry_eqn;
|
| 26969 |
|
|
|
| 26970 |
|
|
--VD1_un50_hilo_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_24
|
| 26971 |
|
|
--operation mode is arithmetic
|
| 26972 |
|
|
|
| 26973 |
|
|
VD1_un50_hilo_carry_24 = CARRY(VD1_hilo_56 & VD1_nop2_reged[24] # !VD1_un50_hilo_carry_23 # !VD1_hilo_56 & VD1_nop2_reged[24] & !VD1_un50_hilo_carry_23);
|
| 26974 |
|
|
|
| 26975 |
|
|
|
| 26976 |
|
|
--VD1_un1_op2_reged_1_combout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[24]
|
| 26977 |
|
|
--operation mode is normal
|
| 26978 |
|
|
|
| 26979 |
|
|
VD1_un1_op2_reged_1_combout[24] = VD1_eqop2_2_32 & VD1_op2_reged[24] # !VD1_eqop2_2_32 & VD1_nop2_reged[24];
|
| 26980 |
|
|
|
| 26981 |
|
|
|
| 26982 |
|
|
--DD1_pc_next_0_iv_1_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_24
|
| 26983 |
|
|
--operation mode is normal
|
| 26984 |
|
|
|
| 26985 |
|
|
DD1_pc_next_0_iv_1_24 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_24 # !DD1_pc_next_0_iv_1_a[24];
|
| 26986 |
|
|
|
| 26987 |
|
|
|
| 26988 |
|
|
--DD1_un1_pc_add24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add24
|
| 26989 |
|
|
--operation mode is arithmetic
|
| 26990 |
|
|
|
| 26991 |
|
|
DD1_un1_pc_add24_carry_eqn = DD1_un1_pc_carry_23;
|
| 26992 |
|
|
DD1_un1_pc_add24 = KB1_r32_o_24 $ DD1_un1_pc_prectl_1_0_a4[24] $ !DD1_un1_pc_add24_carry_eqn;
|
| 26993 |
|
|
|
| 26994 |
|
|
--DD1_un1_pc_carry_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_24
|
| 26995 |
|
|
--operation mode is arithmetic
|
| 26996 |
|
|
|
| 26997 |
|
|
DD1_un1_pc_carry_24 = CARRY(KB1_r32_o_24 & DD1_un1_pc_prectl_1_0_a4[24] # !DD1_un1_pc_carry_23 # !KB1_r32_o_24 & DD1_un1_pc_prectl_1_0_a4[24] & !DD1_un1_pc_carry_23);
|
| 26998 |
|
|
|
| 26999 |
|
|
|
| 27000 |
|
|
--DD1_pc_next_0_iv_1_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_25
|
| 27001 |
|
|
--operation mode is normal
|
| 27002 |
|
|
|
| 27003 |
|
|
DD1_pc_next_0_iv_1_25 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_25 # !DD1_pc_next_0_iv_1_a[25];
|
| 27004 |
|
|
|
| 27005 |
|
|
|
| 27006 |
|
|
--DD1_un1_pc_add25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add25
|
| 27007 |
|
|
--operation mode is arithmetic
|
| 27008 |
|
|
|
| 27009 |
|
|
DD1_un1_pc_add25_carry_eqn = DD1_un1_pc_carry_24;
|
| 27010 |
|
|
DD1_un1_pc_add25 = KB1_r32_o_25 $ DD1_un1_pc_prectl_1_0_a4[25] $ DD1_un1_pc_add25_carry_eqn;
|
| 27011 |
|
|
|
| 27012 |
|
|
--DD1_un1_pc_carry_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_25
|
| 27013 |
|
|
--operation mode is arithmetic
|
| 27014 |
|
|
|
| 27015 |
|
|
DD1_un1_pc_carry_25 = CARRY(KB1_r32_o_25 & !DD1_un1_pc_prectl_1_0_a4[25] & !DD1_un1_pc_carry_24 # !KB1_r32_o_25 & !DD1_un1_pc_carry_24 # !DD1_un1_pc_prectl_1_0_a4[25]);
|
| 27016 |
|
|
|
| 27017 |
|
|
|
| 27018 |
|
|
--PB1_dout_iv_24 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_24
|
| 27019 |
|
|
--operation mode is normal
|
| 27020 |
|
|
|
| 27021 |
|
|
PB1_dout_iv_24 = HD1_dout_iv_1_24 # FD1_wb_o_24 & HD1_dout7_0_a2;
|
| 27022 |
|
|
|
| 27023 |
|
|
--PB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_24
|
| 27024 |
|
|
--operation mode is normal
|
| 27025 |
|
|
|
| 27026 |
|
|
PB1_r32_o_24 = DFFEAS(PB1_dout_iv_24, E1__clk0, VCC, , , , , , );
|
| 27027 |
|
|
|
| 27028 |
|
|
|
| 27029 |
|
|
--VD1_hilo_37_iv_0_2_a[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2_a[57]
|
| 27030 |
|
|
--operation mode is normal
|
| 27031 |
|
|
|
| 27032 |
|
|
VD1_hilo_37_iv_0_2_a[57] = VD1_hilo_25 & !VD1_un59_hilo_add25 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_hilo_25 & VD1_hilo_0_sqmuxa # !VD1_un59_hilo_add25 & VD1_hilo_37_iv_0_a3_2[62];
|
| 27033 |
|
|
|
| 27034 |
|
|
|
| 27035 |
|
|
--PB1_dout_iv_25 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_25
|
| 27036 |
|
|
--operation mode is normal
|
| 27037 |
|
|
|
| 27038 |
|
|
PB1_dout_iv_25 = HD1_dout_iv_1_25 # FD1_wb_o_25 & HD1_dout7_0_a2;
|
| 27039 |
|
|
|
| 27040 |
|
|
--PB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_25
|
| 27041 |
|
|
--operation mode is normal
|
| 27042 |
|
|
|
| 27043 |
|
|
PB1_r32_o_25 = DFFEAS(PB1_dout_iv_25, E1__clk0, VCC, , , , , , );
|
| 27044 |
|
|
|
| 27045 |
|
|
|
| 27046 |
|
|
--DD1_pc_next_0_iv_1_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_22
|
| 27047 |
|
|
--operation mode is normal
|
| 27048 |
|
|
|
| 27049 |
|
|
DD1_pc_next_0_iv_1_22 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_22 # !DD1_pc_next_0_iv_1_a[22];
|
| 27050 |
|
|
|
| 27051 |
|
|
|
| 27052 |
|
|
--DD1_un1_pc_add22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add22
|
| 27053 |
|
|
--operation mode is arithmetic
|
| 27054 |
|
|
|
| 27055 |
|
|
DD1_un1_pc_add22_carry_eqn = DD1_un1_pc_carry_21;
|
| 27056 |
|
|
DD1_un1_pc_add22 = KB1_r32_o_22 $ DD1_un1_pc_prectl_1_0_a4[22] $ !DD1_un1_pc_add22_carry_eqn;
|
| 27057 |
|
|
|
| 27058 |
|
|
--DD1_un1_pc_carry_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_22
|
| 27059 |
|
|
--operation mode is arithmetic
|
| 27060 |
|
|
|
| 27061 |
|
|
DD1_un1_pc_carry_22 = CARRY(KB1_r32_o_22 & DD1_un1_pc_prectl_1_0_a4[22] # !DD1_un1_pc_carry_21 # !KB1_r32_o_22 & DD1_un1_pc_prectl_1_0_a4[22] & !DD1_un1_pc_carry_21);
|
| 27062 |
|
|
|
| 27063 |
|
|
|
| 27064 |
|
|
--DD1_pc_next_0_iv_1_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_23
|
| 27065 |
|
|
--operation mode is normal
|
| 27066 |
|
|
|
| 27067 |
|
|
DD1_pc_next_0_iv_1_23 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_23 # !DD1_pc_next_0_iv_1_a[23];
|
| 27068 |
|
|
|
| 27069 |
|
|
|
| 27070 |
|
|
--DD1_un1_pc_add23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add23
|
| 27071 |
|
|
--operation mode is arithmetic
|
| 27072 |
|
|
|
| 27073 |
|
|
DD1_un1_pc_add23_carry_eqn = DD1_un1_pc_carry_22;
|
| 27074 |
|
|
DD1_un1_pc_add23 = KB1_r32_o_23 $ DD1_un1_pc_prectl_1_0_a4[23] $ DD1_un1_pc_add23_carry_eqn;
|
| 27075 |
|
|
|
| 27076 |
|
|
--DD1_un1_pc_carry_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_23
|
| 27077 |
|
|
--operation mode is arithmetic
|
| 27078 |
|
|
|
| 27079 |
|
|
DD1_un1_pc_carry_23 = CARRY(KB1_r32_o_23 & !DD1_un1_pc_prectl_1_0_a4[23] & !DD1_un1_pc_carry_22 # !KB1_r32_o_23 & !DD1_un1_pc_carry_22 # !DD1_un1_pc_prectl_1_0_a4[23]);
|
| 27080 |
|
|
|
| 27081 |
|
|
|
| 27082 |
|
|
--PB1_dout_iv_22 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_22
|
| 27083 |
|
|
--operation mode is normal
|
| 27084 |
|
|
|
| 27085 |
|
|
PB1_dout_iv_22 = HD1_dout_iv_1_22 # FD1_wb_o_22 & HD1_dout7_0_a2;
|
| 27086 |
|
|
|
| 27087 |
|
|
--PB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_22
|
| 27088 |
|
|
--operation mode is normal
|
| 27089 |
|
|
|
| 27090 |
|
|
PB1_r32_o_22 = DFFEAS(PB1_dout_iv_22, E1__clk0, VCC, , , , , , );
|
| 27091 |
|
|
|
| 27092 |
|
|
|
| 27093 |
|
|
--VD1_un1_op2_reged_1_combout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[23]
|
| 27094 |
|
|
--operation mode is normal
|
| 27095 |
|
|
|
| 27096 |
|
|
VD1_un1_op2_reged_1_combout[23] = VD1_eqop2_2_32 & VD1_op2_reged[23] # !VD1_eqop2_2_32 & VD1_nop2_reged[23];
|
| 27097 |
|
|
|
| 27098 |
|
|
|
| 27099 |
|
|
--PB1_dout_iv_23 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_23
|
| 27100 |
|
|
--operation mode is normal
|
| 27101 |
|
|
|
| 27102 |
|
|
PB1_dout_iv_23 = HD1_dout_iv_1_23 # FD1_wb_o_23 & HD1_dout7_0_a2;
|
| 27103 |
|
|
|
| 27104 |
|
|
--PB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_23
|
| 27105 |
|
|
--operation mode is normal
|
| 27106 |
|
|
|
| 27107 |
|
|
PB1_r32_o_23 = DFFEAS(PB1_dout_iv_23, E1__clk0, VCC, , , , , , );
|
| 27108 |
|
|
|
| 27109 |
|
|
|
| 27110 |
|
|
--HD1_dout_iv_1_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_28
|
| 27111 |
|
|
--operation mode is normal
|
| 27112 |
|
|
|
| 27113 |
|
|
HD1_dout_iv_1_28 = FD1_N_18_i_0_s3 & LD2_q_b[28] # !HD1_dout_iv_1_a[28];
|
| 27114 |
|
|
|
| 27115 |
|
|
|
| 27116 |
|
|
--DD1_un1_pc_prectl_1_0_a4[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[27]
|
| 27117 |
|
|
--operation mode is normal
|
| 27118 |
|
|
|
| 27119 |
|
|
DD1_un1_pc_prectl_1_0_a4[27] = FB1_res_7_0_0_27 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 27120 |
|
|
|
| 27121 |
|
|
|
| 27122 |
|
|
--HD1_dout_iv_1_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_29
|
| 27123 |
|
|
--operation mode is normal
|
| 27124 |
|
|
|
| 27125 |
|
|
HD1_dout_iv_1_29 = FD1_N_18_i_0_s3 & LD2_q_b[29] # !HD1_dout_iv_1_a[29];
|
| 27126 |
|
|
|
| 27127 |
|
|
|
| 27128 |
|
|
--DD1_pc_next_0_iv_1_a[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[26]
|
| 27129 |
|
|
--operation mode is normal
|
| 27130 |
|
|
|
| 27131 |
|
|
DD1_pc_next_0_iv_1_a[26] = SD1_r32_o_26 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_26 # !SD1_r32_o_26 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_26;
|
| 27132 |
|
|
|
| 27133 |
|
|
|
| 27134 |
|
|
--DD1_un1_pc_prectl_1_0_a4[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[26]
|
| 27135 |
|
|
--operation mode is normal
|
| 27136 |
|
|
|
| 27137 |
|
|
DD1_un1_pc_prectl_1_0_a4[26] = FB1_res_7_0_0_26 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 27138 |
|
|
|
| 27139 |
|
|
|
| 27140 |
|
|
--DD1_pc_next_0_iv_1_a[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[27]
|
| 27141 |
|
|
--operation mode is normal
|
| 27142 |
|
|
|
| 27143 |
|
|
DD1_pc_next_0_iv_1_a[27] = SD1_r32_o_27 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_27 # !SD1_r32_o_27 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_27;
|
| 27144 |
|
|
|
| 27145 |
|
|
|
| 27146 |
|
|
--UB1_dout_2_i_i_a2_a[16] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_a[16]
|
| 27147 |
|
|
--operation mode is normal
|
| 27148 |
|
|
|
| 27149 |
|
|
UB1_dout_2_i_i_a2_a[16] = !RB1_ctl_o_3 # !RB1_ctl_o_1;
|
| 27150 |
|
|
|
| 27151 |
|
|
|
| 27152 |
|
|
--TD1_lt_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_23
|
| 27153 |
|
|
--operation mode is arithmetic
|
| 27154 |
|
|
|
| 27155 |
|
|
TD1_lt_23 = CARRY(PD1_a_o_23 & !TD1_lt_22 # !VD1_b_o_iv_23 # !PD1_a_o_23 & !VD1_b_o_iv_23 & !TD1_lt_22);
|
| 27156 |
|
|
|
| 27157 |
|
|
|
| 27158 |
|
|
--TD1_sum_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_24
|
| 27159 |
|
|
--operation mode is arithmetic
|
| 27160 |
|
|
|
| 27161 |
|
|
TD1_sum_carry_24 = CARRY(VD1_b_o_iv_24 & PD1_a_o_24 & !TD1_sum_carry_23 # !VD1_b_o_iv_24 & PD1_a_o_24 # !TD1_sum_carry_23);
|
| 27162 |
|
|
|
| 27163 |
|
|
|
| 27164 |
|
|
--UB1_dout_2_0_0_o2_1_a[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_o2_1_a[9]
|
| 27165 |
|
|
--operation mode is normal
|
| 27166 |
|
|
|
| 27167 |
|
|
UB1_dout_2_0_0_o2_1_a[9] = RB1_ctl_o_1 & RB1_ctl_o_3 & !RB1_byte_addr_o_1 # !RB1_ctl_o_3 & !RB1_ctl_o_2 # !RB1_ctl_o_1 & !RB1_ctl_o_2 & !RB1_byte_addr_o_1;
|
| 27168 |
|
|
|
| 27169 |
|
|
|
| 27170 |
|
|
--UB1_dout_2_i_i_a3_a_x[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3_a_x[15]
|
| 27171 |
|
|
--operation mode is normal
|
| 27172 |
|
|
|
| 27173 |
|
|
UB1_dout_2_i_i_a3_a_x[15] = RB1_byte_addr_o_1 & !GE1_q_b[7] # !RB1_byte_addr_o_1 & !JE1_q_b[7];
|
| 27174 |
|
|
|
| 27175 |
|
|
|
| 27176 |
|
|
--YB1_pc_gen_ctl_2_i_0_a3_5[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_5[2]
|
| 27177 |
|
|
--operation mode is normal
|
| 27178 |
|
|
|
| 27179 |
|
|
YB1_pc_gen_ctl_2_i_0_a3_5[2] = KE1_q_a[2] & YB1_pc_gen_ctl_2_i_0_a3_5_0_x[2] & !YB1_alu_we_1s_1_o2_0_x[0] & YB1_fsm_dly_2_0_0_a2_x[2];
|
| 27180 |
|
|
|
| 27181 |
|
|
|
| 27182 |
|
|
--YB1_pc_gen_ctl_2_i_0_a3[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3[2]
|
| 27183 |
|
|
--operation mode is normal
|
| 27184 |
|
|
|
| 27185 |
|
|
YB1_pc_gen_ctl_2_i_0_a3[2] = GE1_q_a[2] & YB1_pc_gen_ctl_2_i_0_a2_0_x[2] & GE1_q_a[3] # !GE1_q_a[5];
|
| 27186 |
|
|
|
| 27187 |
|
|
|
| 27188 |
|
|
--YB1_pc_gen_ctl_2_i_0_5_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_5_a[2]
|
| 27189 |
|
|
--operation mode is normal
|
| 27190 |
|
|
|
| 27191 |
|
|
YB1_pc_gen_ctl_2_i_0_5_a[2] = GE1_q_a[4] & !GE1_q_a[5] # !GE1_q_a[4] & GE1_q_a[5] # !YB1_alu_func_2_0_0_o2_x[3] # !YB1_pc_gen_ctl_2_i_0_a2_0_x[2];
|
| 27192 |
|
|
|
| 27193 |
|
|
|
| 27194 |
|
|
--YB1_pc_gen_ctl_2_i_0_1_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_1_x[2]
|
| 27195 |
|
|
--operation mode is normal
|
| 27196 |
|
|
|
| 27197 |
|
|
YB1_pc_gen_ctl_2_i_0_1_x[2] = YB1_pc_gen_ctl_2_i_0_a3_3[2] # YB1_pc_gen_ctl_2_i_0_0_Z[2];
|
| 27198 |
|
|
|
| 27199 |
|
|
|
| 27200 |
|
|
--YB1_pc_gen_ctl_2_i_m3_0_5_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_5_a[0]
|
| 27201 |
|
|
--operation mode is normal
|
| 27202 |
|
|
|
| 27203 |
|
|
YB1_pc_gen_ctl_2_i_m3_0_5_a[0] = KE1_q_a[7] & !KE1_q_a[2] & !KE1_q_a[6] # !KE1_q_a[7] & !KE1_q_a[3];
|
| 27204 |
|
|
|
| 27205 |
|
|
|
| 27206 |
|
|
--YB1_pc_gen_ctl_2_i_m3_0_2[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_2[0]
|
| 27207 |
|
|
--operation mode is normal
|
| 27208 |
|
|
|
| 27209 |
|
|
YB1_pc_gen_ctl_2_i_m3_0_2[0] = KE1_q_a[5] # !KE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[4] # !YB1_pc_gen_ctl_2_i_m3_0_2_a[0];
|
| 27210 |
|
|
|
| 27211 |
|
|
|
| 27212 |
|
|
--YB1_pc_gen_ctl_2_0_0_a3[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_0_0_a3[1]
|
| 27213 |
|
|
--operation mode is normal
|
| 27214 |
|
|
|
| 27215 |
|
|
YB1_pc_gen_ctl_2_0_0_a3[1] = YB1_alu_func_2_0_0_a2_0[1] & WB16L1 & YB1_cmp_ctl_2_0_0_a2_0[0] # YB1_cmp_ctl_2_0_0_a2_1[0];
|
| 27216 |
|
|
|
| 27217 |
|
|
|
| 27218 |
|
|
--YB1_cmp_ctl_2_0_0_1_Z[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1_Z[0]
|
| 27219 |
|
|
--operation mode is normal
|
| 27220 |
|
|
|
| 27221 |
|
|
YB1_cmp_ctl_2_0_0_1_Z[0] = WB34L1 & YB1_cmp_ctl_2_0_0_a2_0[0] & YB1_ext_ctl_2_0_0_a2_0_x[2] # !YB1_cmp_ctl_2_0_0_1_a[0];
|
| 27222 |
|
|
|
| 27223 |
|
|
|
| 27224 |
|
|
--YB1_cmp_ctl_2_0_0_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_2
|
| 27225 |
|
|
--operation mode is normal
|
| 27226 |
|
|
|
| 27227 |
|
|
YB1_cmp_ctl_2_0_0_2 = YB1_alu_func_2_0_0_a2_0[1] & YB1_cmp_ctl_2_0_0_a2_x[0] & YB1_alu_func_2_0_0_a2_0_x[0] # !YB1_cmp_ctl_2_0_0_a[2] # !YB1_alu_func_2_0_0_a2_0[1] & YB1_cmp_ctl_2_0_0_a2_x[0] & YB1_alu_func_2_0_0_a2_0_x[0];
|
| 27228 |
|
|
|
| 27229 |
|
|
|
| 27230 |
|
|
--WB54L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_2_|lpm_latch:U1|q[0]~56
|
| 27231 |
|
|
--operation mode is normal
|
| 27232 |
|
|
|
| 27233 |
|
|
WB54L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_cmp_ctl_2_0_0_2 # !YB1_un1_muxa_ctl370_x & WB54L1;
|
| 27234 |
|
|
|
| 27235 |
|
|
|
| 27236 |
|
|
--YB1_cmp_ctl_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1
|
| 27237 |
|
|
--operation mode is normal
|
| 27238 |
|
|
|
| 27239 |
|
|
YB1_cmp_ctl_2_0_0_1 = WB44L1 & YB1_cmp_ctl_2_0_0_a2_0[0] & YB1_alu_func_2_0_0_a2_0[1] # !YB1_cmp_ctl_2_0_0_a[1];
|
| 27240 |
|
|
|
| 27241 |
|
|
|
| 27242 |
|
|
--WB44L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_1_|lpm_latch:U1|q[0]~56
|
| 27243 |
|
|
--operation mode is normal
|
| 27244 |
|
|
|
| 27245 |
|
|
WB44L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_cmp_ctl_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB44L1;
|
| 27246 |
|
|
|
| 27247 |
|
|
|
| 27248 |
|
|
--BD1_res_2_NE_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_16
|
| 27249 |
|
|
--operation mode is normal
|
| 27250 |
|
|
|
| 27251 |
|
|
BD1_res_2_NE_16 = QB1_dout_iv_30 & QB1_dout_iv_14 $ PB1_dout_iv_14 # !PB1_dout_iv_30 # !QB1_dout_iv_30 & PB1_dout_iv_30 # QB1_dout_iv_14 $ PB1_dout_iv_14;
|
| 27252 |
|
|
|
| 27253 |
|
|
|
| 27254 |
|
|
--BD1_res_2_NE_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_17
|
| 27255 |
|
|
--operation mode is normal
|
| 27256 |
|
|
|
| 27257 |
|
|
BD1_res_2_NE_17 = QB1_dout_iv_31 & QB1_dout_iv_15 $ PB1_dout_iv_15 # !PB1_dout_iv_31 # !QB1_dout_iv_31 & PB1_dout_iv_31 # QB1_dout_iv_15 $ PB1_dout_iv_15;
|
| 27258 |
|
|
|
| 27259 |
|
|
|
| 27260 |
|
|
--BD1_res_2_NE_7_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_7_0
|
| 27261 |
|
|
--operation mode is normal
|
| 27262 |
|
|
|
| 27263 |
|
|
BD1_res_2_NE_7_0 = BD1_res_2_12 # BD1_res_2_NE_7_0_a # QB1_dout_iv_28 $ PB1_dout_iv_28;
|
| 27264 |
|
|
|
| 27265 |
|
|
|
| 27266 |
|
|
--BD1_res_2_NE_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_4
|
| 27267 |
|
|
--operation mode is normal
|
| 27268 |
|
|
|
| 27269 |
|
|
BD1_res_2_NE_4 = QB1_dout_iv_18 & QB1_dout_iv_2 $ PB1_dout_iv_2 # !PB1_dout_iv_18 # !QB1_dout_iv_18 & PB1_dout_iv_18 # QB1_dout_iv_2 $ PB1_dout_iv_2;
|
| 27270 |
|
|
|
| 27271 |
|
|
|
| 27272 |
|
|
--BD1_res_2_NE_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_5
|
| 27273 |
|
|
--operation mode is normal
|
| 27274 |
|
|
|
| 27275 |
|
|
BD1_res_2_NE_5 = QB1_dout_iv_19 & QB1_dout_iv_3 $ PB1_dout_iv_3 # !PB1_dout_iv_19 # !QB1_dout_iv_19 & PB1_dout_iv_19 # QB1_dout_iv_3 $ PB1_dout_iv_3;
|
| 27276 |
|
|
|
| 27277 |
|
|
|
| 27278 |
|
|
--BD1_res_2_NE_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_1
|
| 27279 |
|
|
--operation mode is normal
|
| 27280 |
|
|
|
| 27281 |
|
|
BD1_res_2_NE_1 = BD1_res_2_0 # BD1_res_2_NE_1_a # QB1_dout_iv_16 $ PB1_dout_iv_16;
|
| 27282 |
|
|
|
| 27283 |
|
|
|
| 27284 |
|
|
--BD1_N_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_18
|
| 27285 |
|
|
--operation mode is normal
|
| 27286 |
|
|
|
| 27287 |
|
|
BD1_N_18 = QB1_dout_iv_26 & QB1_dout_iv_10 $ PB1_dout_iv_10 # !PB1_dout_iv_26 # !QB1_dout_iv_26 & PB1_dout_iv_26 # QB1_dout_iv_10 $ PB1_dout_iv_10;
|
| 27288 |
|
|
|
| 27289 |
|
|
|
| 27290 |
|
|
--BD1_res_2_NE_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_13
|
| 27291 |
|
|
--operation mode is normal
|
| 27292 |
|
|
|
| 27293 |
|
|
BD1_res_2_NE_13 = QB1_dout_iv_27 & QB1_dout_iv_11 $ PB1_dout_iv_11 # !PB1_dout_iv_27 # !QB1_dout_iv_27 & PB1_dout_iv_27 # QB1_dout_iv_11 $ PB1_dout_iv_11;
|
| 27294 |
|
|
|
| 27295 |
|
|
|
| 27296 |
|
|
--BD1_N_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_16
|
| 27297 |
|
|
--operation mode is normal
|
| 27298 |
|
|
|
| 27299 |
|
|
BD1_N_16 = QB1_dout_iv_24 & QB1_dout_iv_8 $ PB1_dout_iv_8 # !PB1_dout_iv_24 # !QB1_dout_iv_24 & PB1_dout_iv_24 # QB1_dout_iv_8 $ PB1_dout_iv_8;
|
| 27300 |
|
|
|
| 27301 |
|
|
|
| 27302 |
|
|
--BD1_N_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_17
|
| 27303 |
|
|
--operation mode is normal
|
| 27304 |
|
|
|
| 27305 |
|
|
BD1_N_17 = QB1_dout_iv_25 & QB1_dout_iv_9 $ PB1_dout_iv_9 # !PB1_dout_iv_25 # !QB1_dout_iv_25 & PB1_dout_iv_25 # QB1_dout_iv_9 $ PB1_dout_iv_9;
|
| 27306 |
|
|
|
| 27307 |
|
|
|
| 27308 |
|
|
--BD1_res_2_NE_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_8
|
| 27309 |
|
|
--operation mode is normal
|
| 27310 |
|
|
|
| 27311 |
|
|
BD1_res_2_NE_8 = QB1_dout_iv_22 & QB1_dout_iv_6 $ PB1_dout_iv_6 # !PB1_dout_iv_22 # !QB1_dout_iv_22 & PB1_dout_iv_22 # QB1_dout_iv_6 $ PB1_dout_iv_6;
|
| 27312 |
|
|
|
| 27313 |
|
|
|
| 27314 |
|
|
--BD1_N_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_15
|
| 27315 |
|
|
--operation mode is normal
|
| 27316 |
|
|
|
| 27317 |
|
|
BD1_N_15 = QB1_dout_iv_23 & QB1_dout_iv_7 $ PB1_dout_iv_7 # !PB1_dout_iv_23 # !QB1_dout_iv_23 & PB1_dout_iv_23 # QB1_dout_iv_7 $ PB1_dout_iv_7;
|
| 27318 |
|
|
|
| 27319 |
|
|
|
| 27320 |
|
|
--BD1_res_2_NE_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_6
|
| 27321 |
|
|
--operation mode is normal
|
| 27322 |
|
|
|
| 27323 |
|
|
BD1_res_2_NE_6 = QB1_dout_iv_20 & QB1_dout_iv_4 $ PB1_dout_iv_4 # !PB1_dout_iv_20 # !QB1_dout_iv_20 & PB1_dout_iv_20 # QB1_dout_iv_4 $ PB1_dout_iv_4;
|
| 27324 |
|
|
|
| 27325 |
|
|
|
| 27326 |
|
|
--BD1_N_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_13
|
| 27327 |
|
|
--operation mode is normal
|
| 27328 |
|
|
|
| 27329 |
|
|
BD1_N_13 = QB1_dout_iv_21 & QB1_dout_iv_5 $ PB1_dout_iv_5 # !PB1_dout_iv_21 # !QB1_dout_iv_21 & PB1_dout_iv_21 # QB1_dout_iv_5 $ PB1_dout_iv_5;
|
| 27330 |
|
|
|
| 27331 |
|
|
|
| 27332 |
|
|
--BD1_un10_res_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_16
|
| 27333 |
|
|
--operation mode is normal
|
| 27334 |
|
|
|
| 27335 |
|
|
BD1_un10_res_16 = PB1_dout_iv_4 # PB1_dout_iv_16 # PB1_dout_iv_1 # PB1_dout_iv_21;
|
| 27336 |
|
|
|
| 27337 |
|
|
|
| 27338 |
|
|
--BD1_un10_res_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_17
|
| 27339 |
|
|
--operation mode is normal
|
| 27340 |
|
|
|
| 27341 |
|
|
BD1_un10_res_17 = PB1_dout_iv_0 # PB1_dout_iv_26 # PB1_dout_iv_11 # PB1_dout_iv_27;
|
| 27342 |
|
|
|
| 27343 |
|
|
|
| 27344 |
|
|
--BD1_un10_res_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_23
|
| 27345 |
|
|
--operation mode is normal
|
| 27346 |
|
|
|
| 27347 |
|
|
BD1_un10_res_23 = PB1_dout_iv_20 # PB1_dout_iv_23 # PB1_dout_iv_5 # !BD1_un10_res_23_a;
|
| 27348 |
|
|
|
| 27349 |
|
|
|
| 27350 |
|
|
--BD1_un10_res_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_18
|
| 27351 |
|
|
--operation mode is normal
|
| 27352 |
|
|
|
| 27353 |
|
|
BD1_un10_res_18 = PB1_dout_iv_10 # PB1_dout_iv_22 # PB1_dout_iv_6 # PB1_dout_iv_7;
|
| 27354 |
|
|
|
| 27355 |
|
|
|
| 27356 |
|
|
--BD1_un10_res_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_19
|
| 27357 |
|
|
--operation mode is normal
|
| 27358 |
|
|
|
| 27359 |
|
|
BD1_un10_res_19 = PB1_dout_iv_13 # PB1_dout_iv_30 # PB1_dout_iv_12 # PB1_dout_iv_28;
|
| 27360 |
|
|
|
| 27361 |
|
|
|
| 27362 |
|
|
--BD1_un10_res_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_20
|
| 27363 |
|
|
--operation mode is normal
|
| 27364 |
|
|
|
| 27365 |
|
|
BD1_un10_res_20 = PB1_dout_iv_9 # PB1_dout_iv_24 # PB1_dout_iv_8 # PB1_dout_iv_25;
|
| 27366 |
|
|
|
| 27367 |
|
|
|
| 27368 |
|
|
--BD1_un10_res_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_21
|
| 27369 |
|
|
--operation mode is normal
|
| 27370 |
|
|
|
| 27371 |
|
|
BD1_un10_res_21 = PB1_dout_iv_3 # PB1_dout_iv_18 # PB1_dout_iv_2 # PB1_dout_iv_17;
|
| 27372 |
|
|
|
| 27373 |
|
|
|
| 27374 |
|
|
--UB1_dout_2_0_0_a_x[10] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a_x[10]
|
| 27375 |
|
|
--operation mode is normal
|
| 27376 |
|
|
|
| 27377 |
|
|
UB1_dout_2_0_0_a_x[10] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[2];
|
| 27378 |
|
|
|
| 27379 |
|
|
|
| 27380 |
|
|
--UB1_dout_2_i_i_a_x[11] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a_x[11]
|
| 27381 |
|
|
--operation mode is normal
|
| 27382 |
|
|
|
| 27383 |
|
|
UB1_dout_2_i_i_a_x[11] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[3];
|
| 27384 |
|
|
|
| 27385 |
|
|
|
| 27386 |
|
|
--UB1_dout_2_0_0_a_x[12] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a_x[12]
|
| 27387 |
|
|
--operation mode is normal
|
| 27388 |
|
|
|
| 27389 |
|
|
UB1_dout_2_0_0_a_x[12] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[4];
|
| 27390 |
|
|
|
| 27391 |
|
|
|
| 27392 |
|
|
--UB1_dout_2_i_i_a[23] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a[23]
|
| 27393 |
|
|
--operation mode is normal
|
| 27394 |
|
|
|
| 27395 |
|
|
UB1_dout_2_i_i_a[23] = !UB1_dout_2_i_i_a3[15] & RB1_ctl_o_1 & RB1_ctl_o_3 # !UB1_dout_2_i_i_a3_1[15];
|
| 27396 |
|
|
|
| 27397 |
|
|
|
| 27398 |
|
|
--UB1_dout_2_i_i_a_x[13] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a_x[13]
|
| 27399 |
|
|
--operation mode is normal
|
| 27400 |
|
|
|
| 27401 |
|
|
UB1_dout_2_i_i_a_x[13] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[5];
|
| 27402 |
|
|
|
| 27403 |
|
|
|
| 27404 |
|
|
--UB1_dout_2_i_i_a_x[14] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a_x[14]
|
| 27405 |
|
|
--operation mode is normal
|
| 27406 |
|
|
|
| 27407 |
|
|
UB1_dout_2_i_i_a_x[14] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[6];
|
| 27408 |
|
|
|
| 27409 |
|
|
|
| 27410 |
|
|
--YB1_muxa_ctl_2_0_0_a2_0_0_a_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a2_0_0_a_x[1]
|
| 27411 |
|
|
--operation mode is normal
|
| 27412 |
|
|
|
| 27413 |
|
|
YB1_muxa_ctl_2_0_0_a2_0_0_a_x[1] = GE1_q_a[1] & !GE1_q_a[2];
|
| 27414 |
|
|
|
| 27415 |
|
|
|
| 27416 |
|
|
--UB1_dout_2_i_i_1[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_1[15]
|
| 27417 |
|
|
--operation mode is normal
|
| 27418 |
|
|
|
| 27419 |
|
|
UB1_dout_2_i_i_1[15] = RB1_ctl_o_2 & RB1_ctl_o_1 & !UB1_dout_2_i_i_1_a[15] # !RB1_ctl_o_2 & UB1_dout_2_i_i_a3[15] # RB1_ctl_o_1 & UB1_dout_2_i_i_1_a[15];
|
| 27420 |
|
|
|
| 27421 |
|
|
|
| 27422 |
|
|
--VD1_un1_rdy_0_sqmuxa_3_combout is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_rdy_0_sqmuxa_3_combout
|
| 27423 |
|
|
--operation mode is normal
|
| 27424 |
|
|
|
| 27425 |
|
|
VD1_un1_rdy_0_sqmuxa_3_combout = VD1_rdy_0_sqmuxa # !VD1_count[5] & !VD1_overflow & VD1_addnop2110;
|
| 27426 |
|
|
|
| 27427 |
|
|
|
| 27428 |
|
|
--VD1_over_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_27
|
| 27429 |
|
|
--operation mode is arithmetic
|
| 27430 |
|
|
|
| 27431 |
|
|
VD1_over_carry_27 = CARRY(VD1_b_o_iv_27 & !VD1_over_carry_26 # !PD1_a_o_27 # !VD1_b_o_iv_27 & !PD1_a_o_27 & !VD1_over_carry_26);
|
| 27432 |
|
|
|
| 27433 |
|
|
|
| 27434 |
|
|
--HD1_dout_iv_1_a[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[16]
|
| 27435 |
|
|
--operation mode is normal
|
| 27436 |
|
|
|
| 27437 |
|
|
HD1_dout_iv_1_a[16] = FD1_r_data_16 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_14 # !FD1_r_data_16 & !YD1_mux_fw_1 # !AB1_r32_o_14;
|
| 27438 |
|
|
|
| 27439 |
|
|
|
| 27440 |
|
|
--LD2_q_b[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[16]
|
| 27441 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27442 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27443 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27444 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27445 |
|
|
LD2_q_b[16]_PORT_A_data_in = FD1_wb_o_16;
|
| 27446 |
|
|
LD2_q_b[16]_PORT_A_data_in_reg = DFFE(LD2_q_b[16]_PORT_A_data_in, LD2_q_b[16]_clock_0, , , );
|
| 27447 |
|
|
LD2_q_b[16]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27448 |
|
|
LD2_q_b[16]_PORT_A_address_reg = DFFE(LD2_q_b[16]_PORT_A_address, LD2_q_b[16]_clock_0, , , );
|
| 27449 |
|
|
LD2_q_b[16]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27450 |
|
|
LD2_q_b[16]_PORT_B_address_reg = DFFE(LD2_q_b[16]_PORT_B_address, LD2_q_b[16]_clock_1, , , );
|
| 27451 |
|
|
LD2_q_b[16]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27452 |
|
|
LD2_q_b[16]_PORT_A_write_enable_reg = DFFE(LD2_q_b[16]_PORT_A_write_enable, LD2_q_b[16]_clock_0, , , );
|
| 27453 |
|
|
LD2_q_b[16]_PORT_B_read_enable = VCC;
|
| 27454 |
|
|
LD2_q_b[16]_PORT_B_read_enable_reg = DFFE(LD2_q_b[16]_PORT_B_read_enable, LD2_q_b[16]_clock_1, , , );
|
| 27455 |
|
|
LD2_q_b[16]_clock_0 = E1__clk0;
|
| 27456 |
|
|
LD2_q_b[16]_clock_1 = E1__clk0;
|
| 27457 |
|
|
LD2_q_b[16]_PORT_B_data_out = MEMORY(LD2_q_b[16]_PORT_A_data_in_reg, , LD2_q_b[16]_PORT_A_address_reg, LD2_q_b[16]_PORT_B_address_reg, LD2_q_b[16]_PORT_A_write_enable_reg, LD2_q_b[16]_PORT_B_read_enable_reg, , , LD2_q_b[16]_clock_0, LD2_q_b[16]_clock_1, , , , );
|
| 27458 |
|
|
LD2_q_b[16] = LD2_q_b[16]_PORT_B_data_out[0];
|
| 27459 |
|
|
|
| 27460 |
|
|
|
| 27461 |
|
|
--HD1_dout_iv_1_a[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[17]
|
| 27462 |
|
|
--operation mode is normal
|
| 27463 |
|
|
|
| 27464 |
|
|
HD1_dout_iv_1_a[17] = FD1_r_data_17 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_15 # !FD1_r_data_17 & !YD1_mux_fw_1 # !AB1_r32_o_15;
|
| 27465 |
|
|
|
| 27466 |
|
|
|
| 27467 |
|
|
--LD2_q_b[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[17]
|
| 27468 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27469 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27470 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27471 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27472 |
|
|
LD2_q_b[17]_PORT_A_data_in = FD1_wb_o_17;
|
| 27473 |
|
|
LD2_q_b[17]_PORT_A_data_in_reg = DFFE(LD2_q_b[17]_PORT_A_data_in, LD2_q_b[17]_clock_0, , , );
|
| 27474 |
|
|
LD2_q_b[17]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27475 |
|
|
LD2_q_b[17]_PORT_A_address_reg = DFFE(LD2_q_b[17]_PORT_A_address, LD2_q_b[17]_clock_0, , , );
|
| 27476 |
|
|
LD2_q_b[17]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27477 |
|
|
LD2_q_b[17]_PORT_B_address_reg = DFFE(LD2_q_b[17]_PORT_B_address, LD2_q_b[17]_clock_1, , , );
|
| 27478 |
|
|
LD2_q_b[17]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27479 |
|
|
LD2_q_b[17]_PORT_A_write_enable_reg = DFFE(LD2_q_b[17]_PORT_A_write_enable, LD2_q_b[17]_clock_0, , , );
|
| 27480 |
|
|
LD2_q_b[17]_PORT_B_read_enable = VCC;
|
| 27481 |
|
|
LD2_q_b[17]_PORT_B_read_enable_reg = DFFE(LD2_q_b[17]_PORT_B_read_enable, LD2_q_b[17]_clock_1, , , );
|
| 27482 |
|
|
LD2_q_b[17]_clock_0 = E1__clk0;
|
| 27483 |
|
|
LD2_q_b[17]_clock_1 = E1__clk0;
|
| 27484 |
|
|
LD2_q_b[17]_PORT_B_data_out = MEMORY(LD2_q_b[17]_PORT_A_data_in_reg, , LD2_q_b[17]_PORT_A_address_reg, LD2_q_b[17]_PORT_B_address_reg, LD2_q_b[17]_PORT_A_write_enable_reg, LD2_q_b[17]_PORT_B_read_enable_reg, , , LD2_q_b[17]_clock_0, LD2_q_b[17]_clock_1, , , , );
|
| 27485 |
|
|
LD2_q_b[17] = LD2_q_b[17]_PORT_B_data_out[0];
|
| 27486 |
|
|
|
| 27487 |
|
|
|
| 27488 |
|
|
--HD1_dout_iv_1_a[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[14]
|
| 27489 |
|
|
--operation mode is normal
|
| 27490 |
|
|
|
| 27491 |
|
|
HD1_dout_iv_1_a[14] = FD1_r_data_14 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_12 # !FD1_r_data_14 & !YD1_mux_fw_1 # !AB1_r32_o_12;
|
| 27492 |
|
|
|
| 27493 |
|
|
|
| 27494 |
|
|
--LD2_q_b[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[14]
|
| 27495 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27496 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27497 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27498 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27499 |
|
|
LD2_q_b[14]_PORT_A_data_in = FD1_wb_o_14;
|
| 27500 |
|
|
LD2_q_b[14]_PORT_A_data_in_reg = DFFE(LD2_q_b[14]_PORT_A_data_in, LD2_q_b[14]_clock_0, , , );
|
| 27501 |
|
|
LD2_q_b[14]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27502 |
|
|
LD2_q_b[14]_PORT_A_address_reg = DFFE(LD2_q_b[14]_PORT_A_address, LD2_q_b[14]_clock_0, , , );
|
| 27503 |
|
|
LD2_q_b[14]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27504 |
|
|
LD2_q_b[14]_PORT_B_address_reg = DFFE(LD2_q_b[14]_PORT_B_address, LD2_q_b[14]_clock_1, , , );
|
| 27505 |
|
|
LD2_q_b[14]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27506 |
|
|
LD2_q_b[14]_PORT_A_write_enable_reg = DFFE(LD2_q_b[14]_PORT_A_write_enable, LD2_q_b[14]_clock_0, , , );
|
| 27507 |
|
|
LD2_q_b[14]_PORT_B_read_enable = VCC;
|
| 27508 |
|
|
LD2_q_b[14]_PORT_B_read_enable_reg = DFFE(LD2_q_b[14]_PORT_B_read_enable, LD2_q_b[14]_clock_1, , , );
|
| 27509 |
|
|
LD2_q_b[14]_clock_0 = E1__clk0;
|
| 27510 |
|
|
LD2_q_b[14]_clock_1 = E1__clk0;
|
| 27511 |
|
|
LD2_q_b[14]_PORT_B_data_out = MEMORY(LD2_q_b[14]_PORT_A_data_in_reg, , LD2_q_b[14]_PORT_A_address_reg, LD2_q_b[14]_PORT_B_address_reg, LD2_q_b[14]_PORT_A_write_enable_reg, LD2_q_b[14]_PORT_B_read_enable_reg, , , LD2_q_b[14]_clock_0, LD2_q_b[14]_clock_1, , , , );
|
| 27512 |
|
|
LD2_q_b[14] = LD2_q_b[14]_PORT_B_data_out[0];
|
| 27513 |
|
|
|
| 27514 |
|
|
|
| 27515 |
|
|
--HD1_dout_iv_1_a[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[15]
|
| 27516 |
|
|
--operation mode is normal
|
| 27517 |
|
|
|
| 27518 |
|
|
HD1_dout_iv_1_a[15] = FD1_r_data_15 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_13 # !FD1_r_data_15 & !YD1_mux_fw_1 # !AB1_r32_o_13;
|
| 27519 |
|
|
|
| 27520 |
|
|
|
| 27521 |
|
|
--LD2_q_b[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[15]
|
| 27522 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27523 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27524 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27525 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27526 |
|
|
LD2_q_b[15]_PORT_A_data_in = FD1_wb_o_15;
|
| 27527 |
|
|
LD2_q_b[15]_PORT_A_data_in_reg = DFFE(LD2_q_b[15]_PORT_A_data_in, LD2_q_b[15]_clock_0, , , );
|
| 27528 |
|
|
LD2_q_b[15]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27529 |
|
|
LD2_q_b[15]_PORT_A_address_reg = DFFE(LD2_q_b[15]_PORT_A_address, LD2_q_b[15]_clock_0, , , );
|
| 27530 |
|
|
LD2_q_b[15]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27531 |
|
|
LD2_q_b[15]_PORT_B_address_reg = DFFE(LD2_q_b[15]_PORT_B_address, LD2_q_b[15]_clock_1, , , );
|
| 27532 |
|
|
LD2_q_b[15]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27533 |
|
|
LD2_q_b[15]_PORT_A_write_enable_reg = DFFE(LD2_q_b[15]_PORT_A_write_enable, LD2_q_b[15]_clock_0, , , );
|
| 27534 |
|
|
LD2_q_b[15]_PORT_B_read_enable = VCC;
|
| 27535 |
|
|
LD2_q_b[15]_PORT_B_read_enable_reg = DFFE(LD2_q_b[15]_PORT_B_read_enable, LD2_q_b[15]_clock_1, , , );
|
| 27536 |
|
|
LD2_q_b[15]_clock_0 = E1__clk0;
|
| 27537 |
|
|
LD2_q_b[15]_clock_1 = E1__clk0;
|
| 27538 |
|
|
LD2_q_b[15]_PORT_B_data_out = MEMORY(LD2_q_b[15]_PORT_A_data_in_reg, , LD2_q_b[15]_PORT_A_address_reg, LD2_q_b[15]_PORT_B_address_reg, LD2_q_b[15]_PORT_A_write_enable_reg, LD2_q_b[15]_PORT_B_read_enable_reg, , , LD2_q_b[15]_clock_0, LD2_q_b[15]_clock_1, , , , );
|
| 27539 |
|
|
LD2_q_b[15] = LD2_q_b[15]_PORT_B_data_out[0];
|
| 27540 |
|
|
|
| 27541 |
|
|
|
| 27542 |
|
|
--DD1_un1_pc_prectl_1_0_a4[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[19]
|
| 27543 |
|
|
--operation mode is normal
|
| 27544 |
|
|
|
| 27545 |
|
|
DD1_un1_pc_prectl_1_0_a4[19] = FB1_res_7_0_0_19 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 27546 |
|
|
|
| 27547 |
|
|
|
| 27548 |
|
|
--DD1_pc_next_0_iv_1_a[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[18]
|
| 27549 |
|
|
--operation mode is normal
|
| 27550 |
|
|
|
| 27551 |
|
|
DD1_pc_next_0_iv_1_a[18] = SD1_r32_o_18 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_18 # !SD1_r32_o_18 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_18;
|
| 27552 |
|
|
|
| 27553 |
|
|
|
| 27554 |
|
|
--DD1_un1_pc_prectl_1_0_a4[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[18]
|
| 27555 |
|
|
--operation mode is normal
|
| 27556 |
|
|
|
| 27557 |
|
|
DD1_un1_pc_prectl_1_0_a4[18] = FB1_res_7_0_0_18 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 27558 |
|
|
|
| 27559 |
|
|
|
| 27560 |
|
|
--DD1_pc_next_0_iv_1_a[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[19]
|
| 27561 |
|
|
--operation mode is normal
|
| 27562 |
|
|
|
| 27563 |
|
|
DD1_pc_next_0_iv_1_a[19] = SD1_r32_o_19 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_19 # !SD1_r32_o_19 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_19;
|
| 27564 |
|
|
|
| 27565 |
|
|
|
| 27566 |
|
|
--HD1_dout_iv_1_a[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[21]
|
| 27567 |
|
|
--operation mode is normal
|
| 27568 |
|
|
|
| 27569 |
|
|
HD1_dout_iv_1_a[21] = FD1_r_data_21 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_19 # !FD1_r_data_21 & !YD1_mux_fw_1 # !AB1_r32_o_19;
|
| 27570 |
|
|
|
| 27571 |
|
|
|
| 27572 |
|
|
--LD2_q_b[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[21]
|
| 27573 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27574 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27575 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27576 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27577 |
|
|
LD2_q_b[21]_PORT_A_data_in = FD1_wb_o_21;
|
| 27578 |
|
|
LD2_q_b[21]_PORT_A_data_in_reg = DFFE(LD2_q_b[21]_PORT_A_data_in, LD2_q_b[21]_clock_0, , , );
|
| 27579 |
|
|
LD2_q_b[21]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27580 |
|
|
LD2_q_b[21]_PORT_A_address_reg = DFFE(LD2_q_b[21]_PORT_A_address, LD2_q_b[21]_clock_0, , , );
|
| 27581 |
|
|
LD2_q_b[21]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27582 |
|
|
LD2_q_b[21]_PORT_B_address_reg = DFFE(LD2_q_b[21]_PORT_B_address, LD2_q_b[21]_clock_1, , , );
|
| 27583 |
|
|
LD2_q_b[21]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27584 |
|
|
LD2_q_b[21]_PORT_A_write_enable_reg = DFFE(LD2_q_b[21]_PORT_A_write_enable, LD2_q_b[21]_clock_0, , , );
|
| 27585 |
|
|
LD2_q_b[21]_PORT_B_read_enable = VCC;
|
| 27586 |
|
|
LD2_q_b[21]_PORT_B_read_enable_reg = DFFE(LD2_q_b[21]_PORT_B_read_enable, LD2_q_b[21]_clock_1, , , );
|
| 27587 |
|
|
LD2_q_b[21]_clock_0 = E1__clk0;
|
| 27588 |
|
|
LD2_q_b[21]_clock_1 = E1__clk0;
|
| 27589 |
|
|
LD2_q_b[21]_PORT_B_data_out = MEMORY(LD2_q_b[21]_PORT_A_data_in_reg, , LD2_q_b[21]_PORT_A_address_reg, LD2_q_b[21]_PORT_B_address_reg, LD2_q_b[21]_PORT_A_write_enable_reg, LD2_q_b[21]_PORT_B_read_enable_reg, , , LD2_q_b[21]_clock_0, LD2_q_b[21]_clock_1, , , , );
|
| 27590 |
|
|
LD2_q_b[21] = LD2_q_b[21]_PORT_B_data_out[0];
|
| 27591 |
|
|
|
| 27592 |
|
|
|
| 27593 |
|
|
--HD1_dout_iv_1_a[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[20]
|
| 27594 |
|
|
--operation mode is normal
|
| 27595 |
|
|
|
| 27596 |
|
|
HD1_dout_iv_1_a[20] = FD1_r_data_20 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_18 # !FD1_r_data_20 & !YD1_mux_fw_1 # !AB1_r32_o_18;
|
| 27597 |
|
|
|
| 27598 |
|
|
|
| 27599 |
|
|
--LD2_q_b[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[20]
|
| 27600 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27601 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27602 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27603 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27604 |
|
|
LD2_q_b[20]_PORT_A_data_in = FD1_wb_o_20;
|
| 27605 |
|
|
LD2_q_b[20]_PORT_A_data_in_reg = DFFE(LD2_q_b[20]_PORT_A_data_in, LD2_q_b[20]_clock_0, , , );
|
| 27606 |
|
|
LD2_q_b[20]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27607 |
|
|
LD2_q_b[20]_PORT_A_address_reg = DFFE(LD2_q_b[20]_PORT_A_address, LD2_q_b[20]_clock_0, , , );
|
| 27608 |
|
|
LD2_q_b[20]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27609 |
|
|
LD2_q_b[20]_PORT_B_address_reg = DFFE(LD2_q_b[20]_PORT_B_address, LD2_q_b[20]_clock_1, , , );
|
| 27610 |
|
|
LD2_q_b[20]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27611 |
|
|
LD2_q_b[20]_PORT_A_write_enable_reg = DFFE(LD2_q_b[20]_PORT_A_write_enable, LD2_q_b[20]_clock_0, , , );
|
| 27612 |
|
|
LD2_q_b[20]_PORT_B_read_enable = VCC;
|
| 27613 |
|
|
LD2_q_b[20]_PORT_B_read_enable_reg = DFFE(LD2_q_b[20]_PORT_B_read_enable, LD2_q_b[20]_clock_1, , , );
|
| 27614 |
|
|
LD2_q_b[20]_clock_0 = E1__clk0;
|
| 27615 |
|
|
LD2_q_b[20]_clock_1 = E1__clk0;
|
| 27616 |
|
|
LD2_q_b[20]_PORT_B_data_out = MEMORY(LD2_q_b[20]_PORT_A_data_in_reg, , LD2_q_b[20]_PORT_A_address_reg, LD2_q_b[20]_PORT_B_address_reg, LD2_q_b[20]_PORT_A_write_enable_reg, LD2_q_b[20]_PORT_B_read_enable_reg, , , LD2_q_b[20]_clock_0, LD2_q_b[20]_clock_1, , , , );
|
| 27617 |
|
|
LD2_q_b[20] = LD2_q_b[20]_PORT_B_data_out[0];
|
| 27618 |
|
|
|
| 27619 |
|
|
|
| 27620 |
|
|
--HD1_dout_iv_1_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_19
|
| 27621 |
|
|
--operation mode is normal
|
| 27622 |
|
|
|
| 27623 |
|
|
HD1_dout_iv_1_19 = FD1_N_18_i_0_s3 & LD2_q_b[19] # !HD1_dout_iv_1_a[19];
|
| 27624 |
|
|
|
| 27625 |
|
|
|
| 27626 |
|
|
--HD1_dout_iv_1_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_18
|
| 27627 |
|
|
--operation mode is normal
|
| 27628 |
|
|
|
| 27629 |
|
|
HD1_dout_iv_1_18 = FD1_N_18_i_0_s3 & LD2_q_b[18] # !HD1_dout_iv_1_a[18];
|
| 27630 |
|
|
|
| 27631 |
|
|
|
| 27632 |
|
|
--HD1_dout_iv_1_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_26
|
| 27633 |
|
|
--operation mode is normal
|
| 27634 |
|
|
|
| 27635 |
|
|
HD1_dout_iv_1_26 = FD1_N_18_i_0_s3 & LD2_q_b[26] # !HD1_dout_iv_1_a[26];
|
| 27636 |
|
|
|
| 27637 |
|
|
|
| 27638 |
|
|
--VD1_hilo_37_iv_0_0[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[59]
|
| 27639 |
|
|
--operation mode is normal
|
| 27640 |
|
|
|
| 27641 |
|
|
VD1_hilo_37_iv_0_0[59] = VD1_hilo_27 & !VD1_hilo_59 & VD1_hilo_37_iv_0_a3_4[62] # !VD1_hilo_27 & VD1_hilo_0_sqmuxa # !VD1_hilo_59 & VD1_hilo_37_iv_0_a3_4[62];
|
| 27642 |
|
|
|
| 27643 |
|
|
|
| 27644 |
|
|
--HD1_dout_iv_1_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_27
|
| 27645 |
|
|
--operation mode is normal
|
| 27646 |
|
|
|
| 27647 |
|
|
HD1_dout_iv_1_27 = FD1_N_18_i_0_s3 & LD2_q_b[27] # !HD1_dout_iv_1_a[27];
|
| 27648 |
|
|
|
| 27649 |
|
|
|
| 27650 |
|
|
--VD1_hilo_37_iv_0_3[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[60]
|
| 27651 |
|
|
--operation mode is normal
|
| 27652 |
|
|
|
| 27653 |
|
|
VD1_hilo_37_iv_0_3[60] = VD1_hilo_37_iv_0_a5_0[60] # VD1_hilo_37_iv_0_1[60] # !VD1_hilo_61 & VD1_hilo_37_iv_0_a6_0_1[40];
|
| 27654 |
|
|
|
| 27655 |
|
|
|
| 27656 |
|
|
--VD1_hilo_37_iv_0_6_a[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6_a[60]
|
| 27657 |
|
|
--operation mode is normal
|
| 27658 |
|
|
|
| 27659 |
|
|
VD1_hilo_37_iv_0_6_a[60] = VD1_un59_hilo_add29 & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add28 # !VD1_un59_hilo_add29 & VD1_hilo_37_iv_0_a6_1_0[40] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add28;
|
| 27660 |
|
|
|
| 27661 |
|
|
|
| 27662 |
|
|
--VD1_hilo_37_iv_0_0[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[61]
|
| 27663 |
|
|
--operation mode is normal
|
| 27664 |
|
|
|
| 27665 |
|
|
VD1_hilo_37_iv_0_0[61] = VD1_hilo_29 & !VD1_hilo_61 & VD1_hilo_37_iv_0_a3_4[62] # !VD1_hilo_29 & VD1_hilo_0_sqmuxa # !VD1_hilo_61 & VD1_hilo_37_iv_0_a3_4[62];
|
| 27666 |
|
|
|
| 27667 |
|
|
|
| 27668 |
|
|
--HD1_dout_iv_1_a[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[13]
|
| 27669 |
|
|
--operation mode is normal
|
| 27670 |
|
|
|
| 27671 |
|
|
HD1_dout_iv_1_a[13] = FD1_r_data_13 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_11 # !FD1_r_data_13 & !YD1_mux_fw_1 # !AB1_r32_o_11;
|
| 27672 |
|
|
|
| 27673 |
|
|
|
| 27674 |
|
|
--LD2_q_b[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[13]
|
| 27675 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27676 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27677 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27678 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27679 |
|
|
LD2_q_b[13]_PORT_A_data_in = FD1_wb_o_13;
|
| 27680 |
|
|
LD2_q_b[13]_PORT_A_data_in_reg = DFFE(LD2_q_b[13]_PORT_A_data_in, LD2_q_b[13]_clock_0, , , );
|
| 27681 |
|
|
LD2_q_b[13]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27682 |
|
|
LD2_q_b[13]_PORT_A_address_reg = DFFE(LD2_q_b[13]_PORT_A_address, LD2_q_b[13]_clock_0, , , );
|
| 27683 |
|
|
LD2_q_b[13]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27684 |
|
|
LD2_q_b[13]_PORT_B_address_reg = DFFE(LD2_q_b[13]_PORT_B_address, LD2_q_b[13]_clock_1, , , );
|
| 27685 |
|
|
LD2_q_b[13]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27686 |
|
|
LD2_q_b[13]_PORT_A_write_enable_reg = DFFE(LD2_q_b[13]_PORT_A_write_enable, LD2_q_b[13]_clock_0, , , );
|
| 27687 |
|
|
LD2_q_b[13]_PORT_B_read_enable = VCC;
|
| 27688 |
|
|
LD2_q_b[13]_PORT_B_read_enable_reg = DFFE(LD2_q_b[13]_PORT_B_read_enable, LD2_q_b[13]_clock_1, , , );
|
| 27689 |
|
|
LD2_q_b[13]_clock_0 = E1__clk0;
|
| 27690 |
|
|
LD2_q_b[13]_clock_1 = E1__clk0;
|
| 27691 |
|
|
LD2_q_b[13]_PORT_B_data_out = MEMORY(LD2_q_b[13]_PORT_A_data_in_reg, , LD2_q_b[13]_PORT_A_address_reg, LD2_q_b[13]_PORT_B_address_reg, LD2_q_b[13]_PORT_A_write_enable_reg, LD2_q_b[13]_PORT_B_read_enable_reg, , , LD2_q_b[13]_clock_0, LD2_q_b[13]_clock_1, , , , );
|
| 27692 |
|
|
LD2_q_b[13] = LD2_q_b[13]_PORT_B_data_out[0];
|
| 27693 |
|
|
|
| 27694 |
|
|
|
| 27695 |
|
|
--DD1_pc_next_0_iv_1_a[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[24]
|
| 27696 |
|
|
--operation mode is normal
|
| 27697 |
|
|
|
| 27698 |
|
|
DD1_pc_next_0_iv_1_a[24] = SD1_r32_o_24 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_24 # !SD1_r32_o_24 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_24;
|
| 27699 |
|
|
|
| 27700 |
|
|
|
| 27701 |
|
|
--DD1_un1_pc_prectl_1_0_a4[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[24]
|
| 27702 |
|
|
--operation mode is normal
|
| 27703 |
|
|
|
| 27704 |
|
|
DD1_un1_pc_prectl_1_0_a4[24] = FB1_res_7_0_0_24 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 27705 |
|
|
|
| 27706 |
|
|
|
| 27707 |
|
|
--DD1_pc_next_0_iv_1_a[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[25]
|
| 27708 |
|
|
--operation mode is normal
|
| 27709 |
|
|
|
| 27710 |
|
|
DD1_pc_next_0_iv_1_a[25] = SD1_r32_o_25 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_25 # !SD1_r32_o_25 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_25;
|
| 27711 |
|
|
|
| 27712 |
|
|
|
| 27713 |
|
|
--DD1_un1_pc_prectl_1_0_a4[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[25]
|
| 27714 |
|
|
--operation mode is normal
|
| 27715 |
|
|
|
| 27716 |
|
|
DD1_un1_pc_prectl_1_0_a4[25] = FB1_res_7_0_0_25 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 27717 |
|
|
|
| 27718 |
|
|
|
| 27719 |
|
|
--HD1_dout_iv_1_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_24
|
| 27720 |
|
|
--operation mode is normal
|
| 27721 |
|
|
|
| 27722 |
|
|
HD1_dout_iv_1_24 = FD1_N_18_i_0_s3 & LD2_q_b[24] # !HD1_dout_iv_1_a[24];
|
| 27723 |
|
|
|
| 27724 |
|
|
|
| 27725 |
|
|
--HD1_dout_iv_1_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_25
|
| 27726 |
|
|
--operation mode is normal
|
| 27727 |
|
|
|
| 27728 |
|
|
HD1_dout_iv_1_25 = FD1_N_18_i_0_s3 & LD2_q_b[25] # !HD1_dout_iv_1_a[25];
|
| 27729 |
|
|
|
| 27730 |
|
|
|
| 27731 |
|
|
--DD1_pc_next_0_iv_1_a[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[22]
|
| 27732 |
|
|
--operation mode is normal
|
| 27733 |
|
|
|
| 27734 |
|
|
DD1_pc_next_0_iv_1_a[22] = SD1_r32_o_22 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_22 # !SD1_r32_o_22 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_22;
|
| 27735 |
|
|
|
| 27736 |
|
|
|
| 27737 |
|
|
--DD1_un1_pc_prectl_1_0_a4[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[22]
|
| 27738 |
|
|
--operation mode is normal
|
| 27739 |
|
|
|
| 27740 |
|
|
DD1_un1_pc_prectl_1_0_a4[22] = FB1_res_7_0_0_22 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 27741 |
|
|
|
| 27742 |
|
|
|
| 27743 |
|
|
--DD1_pc_next_0_iv_1_a[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[23]
|
| 27744 |
|
|
--operation mode is normal
|
| 27745 |
|
|
|
| 27746 |
|
|
DD1_pc_next_0_iv_1_a[23] = SD1_r32_o_23 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_23 # !SD1_r32_o_23 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_23;
|
| 27747 |
|
|
|
| 27748 |
|
|
|
| 27749 |
|
|
--DD1_un1_pc_prectl_1_0_a4[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[23]
|
| 27750 |
|
|
--operation mode is normal
|
| 27751 |
|
|
|
| 27752 |
|
|
DD1_un1_pc_prectl_1_0_a4[23] = FB1_res_7_0_0_23 & DD1_un1_pc_prectl_1_0_a3[0];
|
| 27753 |
|
|
|
| 27754 |
|
|
|
| 27755 |
|
|
--HD1_dout_iv_1_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_22
|
| 27756 |
|
|
--operation mode is normal
|
| 27757 |
|
|
|
| 27758 |
|
|
HD1_dout_iv_1_22 = FD1_N_18_i_0_s3 & LD2_q_b[22] # !HD1_dout_iv_1_a[22];
|
| 27759 |
|
|
|
| 27760 |
|
|
|
| 27761 |
|
|
--HD1_dout_iv_1_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_23
|
| 27762 |
|
|
--operation mode is normal
|
| 27763 |
|
|
|
| 27764 |
|
|
HD1_dout_iv_1_23 = FD1_N_18_i_0_s3 & LD2_q_b[23] # !HD1_dout_iv_1_a[23];
|
| 27765 |
|
|
|
| 27766 |
|
|
|
| 27767 |
|
|
--HD1_dout_iv_1_a[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[28]
|
| 27768 |
|
|
--operation mode is normal
|
| 27769 |
|
|
|
| 27770 |
|
|
HD1_dout_iv_1_a[28] = FD1_r_data_28 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_26 # !FD1_r_data_28 & !YD1_mux_fw_1 # !AB1_r32_o_26;
|
| 27771 |
|
|
|
| 27772 |
|
|
|
| 27773 |
|
|
--LD2_q_b[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[28]
|
| 27774 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27775 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27776 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27777 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27778 |
|
|
LD2_q_b[28]_PORT_A_data_in = FD1_wb_o_28;
|
| 27779 |
|
|
LD2_q_b[28]_PORT_A_data_in_reg = DFFE(LD2_q_b[28]_PORT_A_data_in, LD2_q_b[28]_clock_0, , , );
|
| 27780 |
|
|
LD2_q_b[28]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27781 |
|
|
LD2_q_b[28]_PORT_A_address_reg = DFFE(LD2_q_b[28]_PORT_A_address, LD2_q_b[28]_clock_0, , , );
|
| 27782 |
|
|
LD2_q_b[28]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27783 |
|
|
LD2_q_b[28]_PORT_B_address_reg = DFFE(LD2_q_b[28]_PORT_B_address, LD2_q_b[28]_clock_1, , , );
|
| 27784 |
|
|
LD2_q_b[28]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27785 |
|
|
LD2_q_b[28]_PORT_A_write_enable_reg = DFFE(LD2_q_b[28]_PORT_A_write_enable, LD2_q_b[28]_clock_0, , , );
|
| 27786 |
|
|
LD2_q_b[28]_PORT_B_read_enable = VCC;
|
| 27787 |
|
|
LD2_q_b[28]_PORT_B_read_enable_reg = DFFE(LD2_q_b[28]_PORT_B_read_enable, LD2_q_b[28]_clock_1, , , );
|
| 27788 |
|
|
LD2_q_b[28]_clock_0 = E1__clk0;
|
| 27789 |
|
|
LD2_q_b[28]_clock_1 = E1__clk0;
|
| 27790 |
|
|
LD2_q_b[28]_PORT_B_data_out = MEMORY(LD2_q_b[28]_PORT_A_data_in_reg, , LD2_q_b[28]_PORT_A_address_reg, LD2_q_b[28]_PORT_B_address_reg, LD2_q_b[28]_PORT_A_write_enable_reg, LD2_q_b[28]_PORT_B_read_enable_reg, , , LD2_q_b[28]_clock_0, LD2_q_b[28]_clock_1, , , , );
|
| 27791 |
|
|
LD2_q_b[28] = LD2_q_b[28]_PORT_B_data_out[0];
|
| 27792 |
|
|
|
| 27793 |
|
|
|
| 27794 |
|
|
--HD1_dout_iv_1_a[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[29]
|
| 27795 |
|
|
--operation mode is normal
|
| 27796 |
|
|
|
| 27797 |
|
|
HD1_dout_iv_1_a[29] = FD1_r_data_29 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_27 # !FD1_r_data_29 & !YD1_mux_fw_1 # !AB1_r32_o_27;
|
| 27798 |
|
|
|
| 27799 |
|
|
|
| 27800 |
|
|
--LD2_q_b[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[29]
|
| 27801 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27802 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27803 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27804 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27805 |
|
|
LD2_q_b[29]_PORT_A_data_in = FD1_wb_o_29;
|
| 27806 |
|
|
LD2_q_b[29]_PORT_A_data_in_reg = DFFE(LD2_q_b[29]_PORT_A_data_in, LD2_q_b[29]_clock_0, , , );
|
| 27807 |
|
|
LD2_q_b[29]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27808 |
|
|
LD2_q_b[29]_PORT_A_address_reg = DFFE(LD2_q_b[29]_PORT_A_address, LD2_q_b[29]_clock_0, , , );
|
| 27809 |
|
|
LD2_q_b[29]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27810 |
|
|
LD2_q_b[29]_PORT_B_address_reg = DFFE(LD2_q_b[29]_PORT_B_address, LD2_q_b[29]_clock_1, , , );
|
| 27811 |
|
|
LD2_q_b[29]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27812 |
|
|
LD2_q_b[29]_PORT_A_write_enable_reg = DFFE(LD2_q_b[29]_PORT_A_write_enable, LD2_q_b[29]_clock_0, , , );
|
| 27813 |
|
|
LD2_q_b[29]_PORT_B_read_enable = VCC;
|
| 27814 |
|
|
LD2_q_b[29]_PORT_B_read_enable_reg = DFFE(LD2_q_b[29]_PORT_B_read_enable, LD2_q_b[29]_clock_1, , , );
|
| 27815 |
|
|
LD2_q_b[29]_clock_0 = E1__clk0;
|
| 27816 |
|
|
LD2_q_b[29]_clock_1 = E1__clk0;
|
| 27817 |
|
|
LD2_q_b[29]_PORT_B_data_out = MEMORY(LD2_q_b[29]_PORT_A_data_in_reg, , LD2_q_b[29]_PORT_A_address_reg, LD2_q_b[29]_PORT_B_address_reg, LD2_q_b[29]_PORT_A_write_enable_reg, LD2_q_b[29]_PORT_B_read_enable_reg, , , LD2_q_b[29]_clock_0, LD2_q_b[29]_clock_1, , , , );
|
| 27818 |
|
|
LD2_q_b[29] = LD2_q_b[29]_PORT_B_data_out[0];
|
| 27819 |
|
|
|
| 27820 |
|
|
|
| 27821 |
|
|
--TD1_lt_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_22
|
| 27822 |
|
|
--operation mode is arithmetic
|
| 27823 |
|
|
|
| 27824 |
|
|
TD1_lt_22 = CARRY(PD1_a_o_22 & VD1_b_o_iv_22 & !TD1_lt_21 # !PD1_a_o_22 & VD1_b_o_iv_22 # !TD1_lt_21);
|
| 27825 |
|
|
|
| 27826 |
|
|
|
| 27827 |
|
|
--TD1_sum_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_23
|
| 27828 |
|
|
--operation mode is arithmetic
|
| 27829 |
|
|
|
| 27830 |
|
|
TD1_sum_carry_23 = CARRY(VD1_b_o_iv_23 & !TD1_sum_carry_22 # !PD1_a_o_23 # !VD1_b_o_iv_23 & !PD1_a_o_23 & !TD1_sum_carry_22);
|
| 27831 |
|
|
|
| 27832 |
|
|
|
| 27833 |
|
|
--YB1_pc_gen_ctl_2_i_0_a3_5_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_5_0_x[2]
|
| 27834 |
|
|
--operation mode is normal
|
| 27835 |
|
|
|
| 27836 |
|
|
YB1_pc_gen_ctl_2_i_0_a3_5_0_x[2] = !JE1_q_a[0] & JE1_q_a[4];
|
| 27837 |
|
|
|
| 27838 |
|
|
|
| 27839 |
|
|
--YB1_pc_gen_ctl_2_i_0_a2_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a2_0_x[2]
|
| 27840 |
|
|
--operation mode is normal
|
| 27841 |
|
|
|
| 27842 |
|
|
YB1_pc_gen_ctl_2_i_0_a2_0_x[2] = !KE1_q_a[2] & !KE1_q_a[6] & YB1_fsm_dly_2_0_0_a2_x[2];
|
| 27843 |
|
|
|
| 27844 |
|
|
|
| 27845 |
|
|
--YB1_pc_gen_ctl_2_i_0_a3_3[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_3[2]
|
| 27846 |
|
|
--operation mode is normal
|
| 27847 |
|
|
|
| 27848 |
|
|
YB1_pc_gen_ctl_2_i_0_a3_3[2] = !WB26L2 & JE1_q_a[4] & KE1_q_a[2] & YB1_fsm_dly_2_0_0_a2_x[2];
|
| 27849 |
|
|
|
| 27850 |
|
|
|
| 27851 |
|
|
--YB1_pc_gen_ctl_2_i_0_0_Z[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_0_Z[2]
|
| 27852 |
|
|
--operation mode is normal
|
| 27853 |
|
|
|
| 27854 |
|
|
YB1_pc_gen_ctl_2_i_0_0_Z[2] = YB1_pc_gen_ctl_2_i_0_a3_2[2] # GE1_q_a[3] & YB1_pc_gen_ctl_2_0_0_a2_x[1] & YB1_pc_gen_ctl_2_i_0_a2_0_x[2];
|
| 27855 |
|
|
|
| 27856 |
|
|
|
| 27857 |
|
|
--YB1_pc_gen_ctl_2_i_m3_0_2_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_2_a[0]
|
| 27858 |
|
|
--operation mode is normal
|
| 27859 |
|
|
|
| 27860 |
|
|
YB1_pc_gen_ctl_2_i_m3_0_2_a[0] = KE1_q_a[7] & !YB1_fsm_dly_2_0_0_o2_x[2] # !WB06L2 # !KE1_q_a[7] & !YB1_alu_func_2_0_0_a2_2_x[1] & !YB1_fsm_dly_2_0_0_o2_x[2] # !WB06L2;
|
| 27861 |
|
|
|
| 27862 |
|
|
|
| 27863 |
|
|
--YB1_cmp_ctl_2_0_0_1_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1_a[0]
|
| 27864 |
|
|
--operation mode is normal
|
| 27865 |
|
|
|
| 27866 |
|
|
YB1_cmp_ctl_2_0_0_1_a[0] = !KE1_q_a[3] & KE1_q_a[2] # KE1_q_a[7] # !YB1_cmp_ctl_2_0_0_a2_x[0];
|
| 27867 |
|
|
|
| 27868 |
|
|
|
| 27869 |
|
|
--YB1_cmp_ctl_2_0_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a[2]
|
| 27870 |
|
|
--operation mode is normal
|
| 27871 |
|
|
|
| 27872 |
|
|
YB1_cmp_ctl_2_0_0_a[2] = JE1_q_a[4] & !YB1_ext_ctl_2_0_0_o2[2] # !WB54L1 # !JE1_q_a[4] & !YB1_pc_gen_ctl_2_i_0_a2_1[2] & !YB1_ext_ctl_2_0_0_o2[2] # !WB54L1;
|
| 27873 |
|
|
|
| 27874 |
|
|
|
| 27875 |
|
|
--YB1_cmp_ctl_2_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a[1]
|
| 27876 |
|
|
--operation mode is normal
|
| 27877 |
|
|
|
| 27878 |
|
|
YB1_cmp_ctl_2_0_0_a[1] = !YB1_cmp_ctl_2_0_0_1_Z[1] & !YB1_ext_ctl_2_0_0_a2_0_x[2] # !KE1_q_a[4] # !KE1_q_a[2];
|
| 27879 |
|
|
|
| 27880 |
|
|
|
| 27881 |
|
|
--BD1_res_2_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_12
|
| 27882 |
|
|
--operation mode is normal
|
| 27883 |
|
|
|
| 27884 |
|
|
BD1_res_2_12 = QB1_dout_iv_12 $ (HD1_dout_iv_1_12 # FD1_wb_o_12 & HD1_dout7_0_a2);
|
| 27885 |
|
|
|
| 27886 |
|
|
|
| 27887 |
|
|
--BD1_res_2_NE_7_0_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_7_0_a
|
| 27888 |
|
|
--operation mode is normal
|
| 27889 |
|
|
|
| 27890 |
|
|
BD1_res_2_NE_7_0_a = QB1_dout_iv_13 & QB1_dout_iv_29 $ PB1_dout_iv_29 # !PB1_dout_iv_13 # !QB1_dout_iv_13 & PB1_dout_iv_13 # QB1_dout_iv_29 $ PB1_dout_iv_29;
|
| 27891 |
|
|
|
| 27892 |
|
|
|
| 27893 |
|
|
--BD1_res_2_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_0
|
| 27894 |
|
|
--operation mode is normal
|
| 27895 |
|
|
|
| 27896 |
|
|
BD1_res_2_0 = QB1_dout_iv_0 $ (HD1_dout_iv_1_0 # FD1_wb_o_0 & HD1_dout7_0_a2);
|
| 27897 |
|
|
|
| 27898 |
|
|
|
| 27899 |
|
|
--BD1_res_2_NE_1_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_1_a
|
| 27900 |
|
|
--operation mode is normal
|
| 27901 |
|
|
|
| 27902 |
|
|
BD1_res_2_NE_1_a = QB1_dout_iv_1 & QB1_dout_iv_17 $ PB1_dout_iv_17 # !PB1_dout_iv_1 # !QB1_dout_iv_1 & PB1_dout_iv_1 # QB1_dout_iv_17 $ PB1_dout_iv_17;
|
| 27903 |
|
|
|
| 27904 |
|
|
|
| 27905 |
|
|
--BD1_un10_res_23_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_23_a
|
| 27906 |
|
|
--operation mode is normal
|
| 27907 |
|
|
|
| 27908 |
|
|
BD1_un10_res_23_a = !PB1_dout_iv_14 & !PB1_dout_iv_19 & !PB1_dout_iv_15 & !PB1_dout_iv_29;
|
| 27909 |
|
|
|
| 27910 |
|
|
|
| 27911 |
|
|
--UB1_dout_2_i_i_1_a[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_1_a[15]
|
| 27912 |
|
|
--operation mode is normal
|
| 27913 |
|
|
|
| 27914 |
|
|
UB1_dout_2_i_i_1_a[15] = UB1_dout_2_i_i_o3_0[7] & !HE1_q_b[7] & RB1_ctl_o_2 # !UB1_dout_2_i_i_o3_0[7] & KE1_q_b[7] $ (RB1_ctl_o_2);
|
| 27915 |
|
|
|
| 27916 |
|
|
|
| 27917 |
|
|
--VD1_over_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_26
|
| 27918 |
|
|
--operation mode is arithmetic
|
| 27919 |
|
|
|
| 27920 |
|
|
VD1_over_carry_26 = CARRY(VD1_b_o_iv_26 & PD1_a_o_26 & !VD1_over_carry_25 # !VD1_b_o_iv_26 & PD1_a_o_26 # !VD1_over_carry_25);
|
| 27921 |
|
|
|
| 27922 |
|
|
|
| 27923 |
|
|
--HD1_dout_iv_1_a[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[19]
|
| 27924 |
|
|
--operation mode is normal
|
| 27925 |
|
|
|
| 27926 |
|
|
HD1_dout_iv_1_a[19] = FD1_r_data_19 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_17 # !FD1_r_data_19 & !YD1_mux_fw_1 # !AB1_r32_o_17;
|
| 27927 |
|
|
|
| 27928 |
|
|
|
| 27929 |
|
|
--LD2_q_b[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[19]
|
| 27930 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27931 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27932 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27933 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27934 |
|
|
LD2_q_b[19]_PORT_A_data_in = FD1_wb_o_19;
|
| 27935 |
|
|
LD2_q_b[19]_PORT_A_data_in_reg = DFFE(LD2_q_b[19]_PORT_A_data_in, LD2_q_b[19]_clock_0, , , );
|
| 27936 |
|
|
LD2_q_b[19]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27937 |
|
|
LD2_q_b[19]_PORT_A_address_reg = DFFE(LD2_q_b[19]_PORT_A_address, LD2_q_b[19]_clock_0, , , );
|
| 27938 |
|
|
LD2_q_b[19]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27939 |
|
|
LD2_q_b[19]_PORT_B_address_reg = DFFE(LD2_q_b[19]_PORT_B_address, LD2_q_b[19]_clock_1, , , );
|
| 27940 |
|
|
LD2_q_b[19]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27941 |
|
|
LD2_q_b[19]_PORT_A_write_enable_reg = DFFE(LD2_q_b[19]_PORT_A_write_enable, LD2_q_b[19]_clock_0, , , );
|
| 27942 |
|
|
LD2_q_b[19]_PORT_B_read_enable = VCC;
|
| 27943 |
|
|
LD2_q_b[19]_PORT_B_read_enable_reg = DFFE(LD2_q_b[19]_PORT_B_read_enable, LD2_q_b[19]_clock_1, , , );
|
| 27944 |
|
|
LD2_q_b[19]_clock_0 = E1__clk0;
|
| 27945 |
|
|
LD2_q_b[19]_clock_1 = E1__clk0;
|
| 27946 |
|
|
LD2_q_b[19]_PORT_B_data_out = MEMORY(LD2_q_b[19]_PORT_A_data_in_reg, , LD2_q_b[19]_PORT_A_address_reg, LD2_q_b[19]_PORT_B_address_reg, LD2_q_b[19]_PORT_A_write_enable_reg, LD2_q_b[19]_PORT_B_read_enable_reg, , , LD2_q_b[19]_clock_0, LD2_q_b[19]_clock_1, , , , );
|
| 27947 |
|
|
LD2_q_b[19] = LD2_q_b[19]_PORT_B_data_out[0];
|
| 27948 |
|
|
|
| 27949 |
|
|
|
| 27950 |
|
|
--HD1_dout_iv_1_a[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[18]
|
| 27951 |
|
|
--operation mode is normal
|
| 27952 |
|
|
|
| 27953 |
|
|
HD1_dout_iv_1_a[18] = FD1_r_data_18 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_16 # !FD1_r_data_18 & !YD1_mux_fw_1 # !AB1_r32_o_16;
|
| 27954 |
|
|
|
| 27955 |
|
|
|
| 27956 |
|
|
--LD2_q_b[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[18]
|
| 27957 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27958 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27959 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27960 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27961 |
|
|
LD2_q_b[18]_PORT_A_data_in = FD1_wb_o_18;
|
| 27962 |
|
|
LD2_q_b[18]_PORT_A_data_in_reg = DFFE(LD2_q_b[18]_PORT_A_data_in, LD2_q_b[18]_clock_0, , , );
|
| 27963 |
|
|
LD2_q_b[18]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27964 |
|
|
LD2_q_b[18]_PORT_A_address_reg = DFFE(LD2_q_b[18]_PORT_A_address, LD2_q_b[18]_clock_0, , , );
|
| 27965 |
|
|
LD2_q_b[18]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27966 |
|
|
LD2_q_b[18]_PORT_B_address_reg = DFFE(LD2_q_b[18]_PORT_B_address, LD2_q_b[18]_clock_1, , , );
|
| 27967 |
|
|
LD2_q_b[18]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27968 |
|
|
LD2_q_b[18]_PORT_A_write_enable_reg = DFFE(LD2_q_b[18]_PORT_A_write_enable, LD2_q_b[18]_clock_0, , , );
|
| 27969 |
|
|
LD2_q_b[18]_PORT_B_read_enable = VCC;
|
| 27970 |
|
|
LD2_q_b[18]_PORT_B_read_enable_reg = DFFE(LD2_q_b[18]_PORT_B_read_enable, LD2_q_b[18]_clock_1, , , );
|
| 27971 |
|
|
LD2_q_b[18]_clock_0 = E1__clk0;
|
| 27972 |
|
|
LD2_q_b[18]_clock_1 = E1__clk0;
|
| 27973 |
|
|
LD2_q_b[18]_PORT_B_data_out = MEMORY(LD2_q_b[18]_PORT_A_data_in_reg, , LD2_q_b[18]_PORT_A_address_reg, LD2_q_b[18]_PORT_B_address_reg, LD2_q_b[18]_PORT_A_write_enable_reg, LD2_q_b[18]_PORT_B_read_enable_reg, , , LD2_q_b[18]_clock_0, LD2_q_b[18]_clock_1, , , , );
|
| 27974 |
|
|
LD2_q_b[18] = LD2_q_b[18]_PORT_B_data_out[0];
|
| 27975 |
|
|
|
| 27976 |
|
|
|
| 27977 |
|
|
--HD1_dout_iv_1_a[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[26]
|
| 27978 |
|
|
--operation mode is normal
|
| 27979 |
|
|
|
| 27980 |
|
|
HD1_dout_iv_1_a[26] = FD1_r_data_26 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_24 # !FD1_r_data_26 & !YD1_mux_fw_1 # !AB1_r32_o_24;
|
| 27981 |
|
|
|
| 27982 |
|
|
|
| 27983 |
|
|
--LD2_q_b[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[26]
|
| 27984 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 27985 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 27986 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 27987 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 27988 |
|
|
LD2_q_b[26]_PORT_A_data_in = FD1_wb_o_26;
|
| 27989 |
|
|
LD2_q_b[26]_PORT_A_data_in_reg = DFFE(LD2_q_b[26]_PORT_A_data_in, LD2_q_b[26]_clock_0, , , );
|
| 27990 |
|
|
LD2_q_b[26]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 27991 |
|
|
LD2_q_b[26]_PORT_A_address_reg = DFFE(LD2_q_b[26]_PORT_A_address, LD2_q_b[26]_clock_0, , , );
|
| 27992 |
|
|
LD2_q_b[26]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 27993 |
|
|
LD2_q_b[26]_PORT_B_address_reg = DFFE(LD2_q_b[26]_PORT_B_address, LD2_q_b[26]_clock_1, , , );
|
| 27994 |
|
|
LD2_q_b[26]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 27995 |
|
|
LD2_q_b[26]_PORT_A_write_enable_reg = DFFE(LD2_q_b[26]_PORT_A_write_enable, LD2_q_b[26]_clock_0, , , );
|
| 27996 |
|
|
LD2_q_b[26]_PORT_B_read_enable = VCC;
|
| 27997 |
|
|
LD2_q_b[26]_PORT_B_read_enable_reg = DFFE(LD2_q_b[26]_PORT_B_read_enable, LD2_q_b[26]_clock_1, , , );
|
| 27998 |
|
|
LD2_q_b[26]_clock_0 = E1__clk0;
|
| 27999 |
|
|
LD2_q_b[26]_clock_1 = E1__clk0;
|
| 28000 |
|
|
LD2_q_b[26]_PORT_B_data_out = MEMORY(LD2_q_b[26]_PORT_A_data_in_reg, , LD2_q_b[26]_PORT_A_address_reg, LD2_q_b[26]_PORT_B_address_reg, LD2_q_b[26]_PORT_A_write_enable_reg, LD2_q_b[26]_PORT_B_read_enable_reg, , , LD2_q_b[26]_clock_0, LD2_q_b[26]_clock_1, , , , );
|
| 28001 |
|
|
LD2_q_b[26] = LD2_q_b[26]_PORT_B_data_out[0];
|
| 28002 |
|
|
|
| 28003 |
|
|
|
| 28004 |
|
|
--HD1_dout_iv_1_a[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[27]
|
| 28005 |
|
|
--operation mode is normal
|
| 28006 |
|
|
|
| 28007 |
|
|
HD1_dout_iv_1_a[27] = FD1_r_data_27 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_25 # !FD1_r_data_27 & !YD1_mux_fw_1 # !AB1_r32_o_25;
|
| 28008 |
|
|
|
| 28009 |
|
|
|
| 28010 |
|
|
--LD2_q_b[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[27]
|
| 28011 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 28012 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 28013 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 28014 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 28015 |
|
|
LD2_q_b[27]_PORT_A_data_in = FD1_wb_o_27;
|
| 28016 |
|
|
LD2_q_b[27]_PORT_A_data_in_reg = DFFE(LD2_q_b[27]_PORT_A_data_in, LD2_q_b[27]_clock_0, , , );
|
| 28017 |
|
|
LD2_q_b[27]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 28018 |
|
|
LD2_q_b[27]_PORT_A_address_reg = DFFE(LD2_q_b[27]_PORT_A_address, LD2_q_b[27]_clock_0, , , );
|
| 28019 |
|
|
LD2_q_b[27]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 28020 |
|
|
LD2_q_b[27]_PORT_B_address_reg = DFFE(LD2_q_b[27]_PORT_B_address, LD2_q_b[27]_clock_1, , , );
|
| 28021 |
|
|
LD2_q_b[27]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 28022 |
|
|
LD2_q_b[27]_PORT_A_write_enable_reg = DFFE(LD2_q_b[27]_PORT_A_write_enable, LD2_q_b[27]_clock_0, , , );
|
| 28023 |
|
|
LD2_q_b[27]_PORT_B_read_enable = VCC;
|
| 28024 |
|
|
LD2_q_b[27]_PORT_B_read_enable_reg = DFFE(LD2_q_b[27]_PORT_B_read_enable, LD2_q_b[27]_clock_1, , , );
|
| 28025 |
|
|
LD2_q_b[27]_clock_0 = E1__clk0;
|
| 28026 |
|
|
LD2_q_b[27]_clock_1 = E1__clk0;
|
| 28027 |
|
|
LD2_q_b[27]_PORT_B_data_out = MEMORY(LD2_q_b[27]_PORT_A_data_in_reg, , LD2_q_b[27]_PORT_A_address_reg, LD2_q_b[27]_PORT_B_address_reg, LD2_q_b[27]_PORT_A_write_enable_reg, LD2_q_b[27]_PORT_B_read_enable_reg, , , LD2_q_b[27]_clock_0, LD2_q_b[27]_clock_1, , , , );
|
| 28028 |
|
|
LD2_q_b[27] = LD2_q_b[27]_PORT_B_data_out[0];
|
| 28029 |
|
|
|
| 28030 |
|
|
|
| 28031 |
|
|
--VD1_hilo_37_iv_0_a5_0[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a5_0[60]
|
| 28032 |
|
|
--operation mode is normal
|
| 28033 |
|
|
|
| 28034 |
|
|
VD1_hilo_37_iv_0_a5_0[60] = !VD1_hilo_60 & VD1_hilo_37_iv_0_a3_1[62];
|
| 28035 |
|
|
|
| 28036 |
|
|
|
| 28037 |
|
|
--VD1_hilo_37_iv_0_1[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[60]
|
| 28038 |
|
|
--operation mode is normal
|
| 28039 |
|
|
|
| 28040 |
|
|
VD1_hilo_37_iv_0_1[60] = VD1_hilo_37_iv_0_0[60] # !VD1_un59_hilo_add28 & VD1_hilo_37_iv_0_a3_2[62];
|
| 28041 |
|
|
|
| 28042 |
|
|
|
| 28043 |
|
|
--HD1_dout_iv_1_a[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[24]
|
| 28044 |
|
|
--operation mode is normal
|
| 28045 |
|
|
|
| 28046 |
|
|
HD1_dout_iv_1_a[24] = FD1_r_data_24 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_22 # !FD1_r_data_24 & !YD1_mux_fw_1 # !AB1_r32_o_22;
|
| 28047 |
|
|
|
| 28048 |
|
|
|
| 28049 |
|
|
--LD2_q_b[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[24]
|
| 28050 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 28051 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 28052 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 28053 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 28054 |
|
|
LD2_q_b[24]_PORT_A_data_in = FD1_wb_o_24;
|
| 28055 |
|
|
LD2_q_b[24]_PORT_A_data_in_reg = DFFE(LD2_q_b[24]_PORT_A_data_in, LD2_q_b[24]_clock_0, , , );
|
| 28056 |
|
|
LD2_q_b[24]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 28057 |
|
|
LD2_q_b[24]_PORT_A_address_reg = DFFE(LD2_q_b[24]_PORT_A_address, LD2_q_b[24]_clock_0, , , );
|
| 28058 |
|
|
LD2_q_b[24]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 28059 |
|
|
LD2_q_b[24]_PORT_B_address_reg = DFFE(LD2_q_b[24]_PORT_B_address, LD2_q_b[24]_clock_1, , , );
|
| 28060 |
|
|
LD2_q_b[24]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 28061 |
|
|
LD2_q_b[24]_PORT_A_write_enable_reg = DFFE(LD2_q_b[24]_PORT_A_write_enable, LD2_q_b[24]_clock_0, , , );
|
| 28062 |
|
|
LD2_q_b[24]_PORT_B_read_enable = VCC;
|
| 28063 |
|
|
LD2_q_b[24]_PORT_B_read_enable_reg = DFFE(LD2_q_b[24]_PORT_B_read_enable, LD2_q_b[24]_clock_1, , , );
|
| 28064 |
|
|
LD2_q_b[24]_clock_0 = E1__clk0;
|
| 28065 |
|
|
LD2_q_b[24]_clock_1 = E1__clk0;
|
| 28066 |
|
|
LD2_q_b[24]_PORT_B_data_out = MEMORY(LD2_q_b[24]_PORT_A_data_in_reg, , LD2_q_b[24]_PORT_A_address_reg, LD2_q_b[24]_PORT_B_address_reg, LD2_q_b[24]_PORT_A_write_enable_reg, LD2_q_b[24]_PORT_B_read_enable_reg, , , LD2_q_b[24]_clock_0, LD2_q_b[24]_clock_1, , , , );
|
| 28067 |
|
|
LD2_q_b[24] = LD2_q_b[24]_PORT_B_data_out[0];
|
| 28068 |
|
|
|
| 28069 |
|
|
|
| 28070 |
|
|
--HD1_dout_iv_1_a[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[25]
|
| 28071 |
|
|
--operation mode is normal
|
| 28072 |
|
|
|
| 28073 |
|
|
HD1_dout_iv_1_a[25] = FD1_r_data_25 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_23 # !FD1_r_data_25 & !YD1_mux_fw_1 # !AB1_r32_o_23;
|
| 28074 |
|
|
|
| 28075 |
|
|
|
| 28076 |
|
|
--LD2_q_b[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[25]
|
| 28077 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 28078 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 28079 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 28080 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 28081 |
|
|
LD2_q_b[25]_PORT_A_data_in = FD1_wb_o_25;
|
| 28082 |
|
|
LD2_q_b[25]_PORT_A_data_in_reg = DFFE(LD2_q_b[25]_PORT_A_data_in, LD2_q_b[25]_clock_0, , , );
|
| 28083 |
|
|
LD2_q_b[25]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 28084 |
|
|
LD2_q_b[25]_PORT_A_address_reg = DFFE(LD2_q_b[25]_PORT_A_address, LD2_q_b[25]_clock_0, , , );
|
| 28085 |
|
|
LD2_q_b[25]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 28086 |
|
|
LD2_q_b[25]_PORT_B_address_reg = DFFE(LD2_q_b[25]_PORT_B_address, LD2_q_b[25]_clock_1, , , );
|
| 28087 |
|
|
LD2_q_b[25]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 28088 |
|
|
LD2_q_b[25]_PORT_A_write_enable_reg = DFFE(LD2_q_b[25]_PORT_A_write_enable, LD2_q_b[25]_clock_0, , , );
|
| 28089 |
|
|
LD2_q_b[25]_PORT_B_read_enable = VCC;
|
| 28090 |
|
|
LD2_q_b[25]_PORT_B_read_enable_reg = DFFE(LD2_q_b[25]_PORT_B_read_enable, LD2_q_b[25]_clock_1, , , );
|
| 28091 |
|
|
LD2_q_b[25]_clock_0 = E1__clk0;
|
| 28092 |
|
|
LD2_q_b[25]_clock_1 = E1__clk0;
|
| 28093 |
|
|
LD2_q_b[25]_PORT_B_data_out = MEMORY(LD2_q_b[25]_PORT_A_data_in_reg, , LD2_q_b[25]_PORT_A_address_reg, LD2_q_b[25]_PORT_B_address_reg, LD2_q_b[25]_PORT_A_write_enable_reg, LD2_q_b[25]_PORT_B_read_enable_reg, , , LD2_q_b[25]_clock_0, LD2_q_b[25]_clock_1, , , , );
|
| 28094 |
|
|
LD2_q_b[25] = LD2_q_b[25]_PORT_B_data_out[0];
|
| 28095 |
|
|
|
| 28096 |
|
|
|
| 28097 |
|
|
--HD1_dout_iv_1_a[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[22]
|
| 28098 |
|
|
--operation mode is normal
|
| 28099 |
|
|
|
| 28100 |
|
|
HD1_dout_iv_1_a[22] = FD1_r_data_22 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_20 # !FD1_r_data_22 & !YD1_mux_fw_1 # !AB1_r32_o_20;
|
| 28101 |
|
|
|
| 28102 |
|
|
|
| 28103 |
|
|
--LD2_q_b[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[22]
|
| 28104 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 28105 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 28106 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 28107 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 28108 |
|
|
LD2_q_b[22]_PORT_A_data_in = FD1_wb_o_22;
|
| 28109 |
|
|
LD2_q_b[22]_PORT_A_data_in_reg = DFFE(LD2_q_b[22]_PORT_A_data_in, LD2_q_b[22]_clock_0, , , );
|
| 28110 |
|
|
LD2_q_b[22]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 28111 |
|
|
LD2_q_b[22]_PORT_A_address_reg = DFFE(LD2_q_b[22]_PORT_A_address, LD2_q_b[22]_clock_0, , , );
|
| 28112 |
|
|
LD2_q_b[22]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 28113 |
|
|
LD2_q_b[22]_PORT_B_address_reg = DFFE(LD2_q_b[22]_PORT_B_address, LD2_q_b[22]_clock_1, , , );
|
| 28114 |
|
|
LD2_q_b[22]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 28115 |
|
|
LD2_q_b[22]_PORT_A_write_enable_reg = DFFE(LD2_q_b[22]_PORT_A_write_enable, LD2_q_b[22]_clock_0, , , );
|
| 28116 |
|
|
LD2_q_b[22]_PORT_B_read_enable = VCC;
|
| 28117 |
|
|
LD2_q_b[22]_PORT_B_read_enable_reg = DFFE(LD2_q_b[22]_PORT_B_read_enable, LD2_q_b[22]_clock_1, , , );
|
| 28118 |
|
|
LD2_q_b[22]_clock_0 = E1__clk0;
|
| 28119 |
|
|
LD2_q_b[22]_clock_1 = E1__clk0;
|
| 28120 |
|
|
LD2_q_b[22]_PORT_B_data_out = MEMORY(LD2_q_b[22]_PORT_A_data_in_reg, , LD2_q_b[22]_PORT_A_address_reg, LD2_q_b[22]_PORT_B_address_reg, LD2_q_b[22]_PORT_A_write_enable_reg, LD2_q_b[22]_PORT_B_read_enable_reg, , , LD2_q_b[22]_clock_0, LD2_q_b[22]_clock_1, , , , );
|
| 28121 |
|
|
LD2_q_b[22] = LD2_q_b[22]_PORT_B_data_out[0];
|
| 28122 |
|
|
|
| 28123 |
|
|
|
| 28124 |
|
|
--HD1_dout_iv_1_a[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[23]
|
| 28125 |
|
|
--operation mode is normal
|
| 28126 |
|
|
|
| 28127 |
|
|
HD1_dout_iv_1_a[23] = FD1_r_data_23 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_21 # !FD1_r_data_23 & !YD1_mux_fw_1 # !AB1_r32_o_21;
|
| 28128 |
|
|
|
| 28129 |
|
|
|
| 28130 |
|
|
--LD2_q_b[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[23]
|
| 28131 |
|
|
--RAM Block Operation Mode: Simple Dual-Port
|
| 28132 |
|
|
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
|
| 28133 |
|
|
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
|
| 28134 |
|
|
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
|
| 28135 |
|
|
LD2_q_b[23]_PORT_A_data_in = FD1_wb_o_23;
|
| 28136 |
|
|
LD2_q_b[23]_PORT_A_data_in_reg = DFFE(LD2_q_b[23]_PORT_A_data_in, LD2_q_b[23]_clock_0, , , );
|
| 28137 |
|
|
LD2_q_b[23]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
|
| 28138 |
|
|
LD2_q_b[23]_PORT_A_address_reg = DFFE(LD2_q_b[23]_PORT_A_address, LD2_q_b[23]_clock_0, , , );
|
| 28139 |
|
|
LD2_q_b[23]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
|
| 28140 |
|
|
LD2_q_b[23]_PORT_B_address_reg = DFFE(LD2_q_b[23]_PORT_B_address, LD2_q_b[23]_clock_1, , , );
|
| 28141 |
|
|
LD2_q_b[23]_PORT_A_write_enable = MC1_wb_we_o_0;
|
| 28142 |
|
|
LD2_q_b[23]_PORT_A_write_enable_reg = DFFE(LD2_q_b[23]_PORT_A_write_enable, LD2_q_b[23]_clock_0, , , );
|
| 28143 |
|
|
LD2_q_b[23]_PORT_B_read_enable = VCC;
|
| 28144 |
|
|
LD2_q_b[23]_PORT_B_read_enable_reg = DFFE(LD2_q_b[23]_PORT_B_read_enable, LD2_q_b[23]_clock_1, , , );
|
| 28145 |
|
|
LD2_q_b[23]_clock_0 = E1__clk0;
|
| 28146 |
|
|
LD2_q_b[23]_clock_1 = E1__clk0;
|
| 28147 |
|
|
LD2_q_b[23]_PORT_B_data_out = MEMORY(LD2_q_b[23]_PORT_A_data_in_reg, , LD2_q_b[23]_PORT_A_address_reg, LD2_q_b[23]_PORT_B_address_reg, LD2_q_b[23]_PORT_A_write_enable_reg, LD2_q_b[23]_PORT_B_read_enable_reg, , , LD2_q_b[23]_clock_0, LD2_q_b[23]_clock_1, , , , );
|
| 28148 |
|
|
LD2_q_b[23] = LD2_q_b[23]_PORT_B_data_out[0];
|
| 28149 |
|
|
|
| 28150 |
|
|
|
| 28151 |
|
|
--TD1_lt_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_21
|
| 28152 |
|
|
--operation mode is arithmetic
|
| 28153 |
|
|
|
| 28154 |
|
|
TD1_lt_21 = CARRY(PD1_a_o_21 & !TD1_lt_20 # !VD1_b_o_iv_21 # !PD1_a_o_21 & !VD1_b_o_iv_21 & !TD1_lt_20);
|
| 28155 |
|
|
|
| 28156 |
|
|
|
| 28157 |
|
|
--TD1_sum_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_22
|
| 28158 |
|
|
--operation mode is arithmetic
|
| 28159 |
|
|
|
| 28160 |
|
|
TD1_sum_carry_22 = CARRY(VD1_b_o_iv_22 & PD1_a_o_22 & !TD1_sum_carry_21 # !VD1_b_o_iv_22 & PD1_a_o_22 # !TD1_sum_carry_21);
|
| 28161 |
|
|
|
| 28162 |
|
|
|
| 28163 |
|
|
--YB1_pc_gen_ctl_2_i_0_a3_2[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_2[2]
|
| 28164 |
|
|
--operation mode is normal
|
| 28165 |
|
|
|
| 28166 |
|
|
YB1_pc_gen_ctl_2_i_0_a3_2[2] = KE1_q_a[3] & !KE1_q_a[5] & !KE1_q_a[4] & YB1_pc_gen_ctl_2_i_0_a3_2_a_x[2];
|
| 28167 |
|
|
|
| 28168 |
|
|
|
| 28169 |
|
|
--YB1_pc_gen_ctl_2_i_0_a2_1[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a2_1[2]
|
| 28170 |
|
|
--operation mode is normal
|
| 28171 |
|
|
|
| 28172 |
|
|
YB1_pc_gen_ctl_2_i_0_a2_1[2] = !JE1_q_a[2] & !JE1_q_a[3] & !JE1_q_a[1] & KE1_q_a[2];
|
| 28173 |
|
|
|
| 28174 |
|
|
|
| 28175 |
|
|
--YB1_cmp_ctl_2_0_0_1_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1_Z[1]
|
| 28176 |
|
|
--operation mode is normal
|
| 28177 |
|
|
|
| 28178 |
|
|
YB1_cmp_ctl_2_0_0_1_Z[1] = YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x & YB1_ext_ctl_2_0_0_a2_0_x[2] & !YB1_cmp_ctl_2_0_0_1_a[1] # !YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x & YB1_cmp_ctl_2_0_0_a2_x[0] # YB1_ext_ctl_2_0_0_a2_0_x[2] & !YB1_cmp_ctl_2_0_0_1_a[1];
|
| 28179 |
|
|
|
| 28180 |
|
|
|
| 28181 |
|
|
--VD1_over_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_25
|
| 28182 |
|
|
--operation mode is arithmetic
|
| 28183 |
|
|
|
| 28184 |
|
|
VD1_over_carry_25 = CARRY(VD1_b_o_iv_25 & !VD1_over_carry_24 # !PD1_a_o_25 # !VD1_b_o_iv_25 & !PD1_a_o_25 & !VD1_over_carry_24);
|
| 28185 |
|
|
|
| 28186 |
|
|
|
| 28187 |
|
|
--VD1_hilo_37_iv_0_0[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[60]
|
| 28188 |
|
|
--operation mode is normal
|
| 28189 |
|
|
|
| 28190 |
|
|
VD1_hilo_37_iv_0_0[60] = VD1_hilo_28 & !VD1_hilo_60 & VD1_hilo_37_iv_0_a3_4[62] # !VD1_hilo_28 & VD1_hilo_0_sqmuxa # !VD1_hilo_60 & VD1_hilo_37_iv_0_a3_4[62];
|
| 28191 |
|
|
|
| 28192 |
|
|
|
| 28193 |
|
|
--TD1_lt_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_20
|
| 28194 |
|
|
--operation mode is arithmetic
|
| 28195 |
|
|
|
| 28196 |
|
|
TD1_lt_20 = CARRY(PD1_a_o_20 & VD1_b_o_iv_20 & !TD1_lt_19 # !PD1_a_o_20 & VD1_b_o_iv_20 # !TD1_lt_19);
|
| 28197 |
|
|
|
| 28198 |
|
|
|
| 28199 |
|
|
--TD1_sum_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_21
|
| 28200 |
|
|
--operation mode is arithmetic
|
| 28201 |
|
|
|
| 28202 |
|
|
TD1_sum_carry_21 = CARRY(VD1_b_o_iv_21 & !TD1_sum_carry_20 # !PD1_a_o_21 # !VD1_b_o_iv_21 & !PD1_a_o_21 & !TD1_sum_carry_20);
|
| 28203 |
|
|
|
| 28204 |
|
|
|
| 28205 |
|
|
--YB1_pc_gen_ctl_2_i_0_a3_2_a_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_2_a_x[2]
|
| 28206 |
|
|
--operation mode is normal
|
| 28207 |
|
|
|
| 28208 |
|
|
YB1_pc_gen_ctl_2_i_0_a3_2_a_x[2] = !KE1_q_a[2] & !KE1_q_a[6];
|
| 28209 |
|
|
|
| 28210 |
|
|
|
| 28211 |
|
|
--YB1_cmp_ctl_2_0_0_1_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1_a[1]
|
| 28212 |
|
|
--operation mode is normal
|
| 28213 |
|
|
|
| 28214 |
|
|
YB1_cmp_ctl_2_0_0_1_a[1] = YB1_cmp_ctl_2_0_0_a2_1[0] & !WB44L1 & JE1_q_a[0] # !YB1_cmp_ctl_2_0_0_a2_x[2] # !YB1_cmp_ctl_2_0_0_a2_1[0] & JE1_q_a[0] # !YB1_cmp_ctl_2_0_0_a2_x[2];
|
| 28215 |
|
|
|
| 28216 |
|
|
|
| 28217 |
|
|
--VD1_over_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_24
|
| 28218 |
|
|
--operation mode is arithmetic
|
| 28219 |
|
|
|
| 28220 |
|
|
VD1_over_carry_24 = CARRY(VD1_b_o_iv_24 & PD1_a_o_24 & !VD1_over_carry_23 # !VD1_b_o_iv_24 & PD1_a_o_24 # !VD1_over_carry_23);
|
| 28221 |
|
|
|
| 28222 |
|
|
|
| 28223 |
|
|
--TD1_lt_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_19
|
| 28224 |
|
|
--operation mode is arithmetic
|
| 28225 |
|
|
|
| 28226 |
|
|
TD1_lt_19 = CARRY(PD1_a_o_19 & !TD1_lt_18 # !VD1_b_o_iv_19 # !PD1_a_o_19 & !VD1_b_o_iv_19 & !TD1_lt_18);
|
| 28227 |
|
|
|
| 28228 |
|
|
|
| 28229 |
|
|
--TD1_sum_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_20
|
| 28230 |
|
|
--operation mode is arithmetic
|
| 28231 |
|
|
|
| 28232 |
|
|
TD1_sum_carry_20 = CARRY(VD1_b_o_iv_20 & PD1_a_o_20 & !TD1_sum_carry_19 # !VD1_b_o_iv_20 & PD1_a_o_20 # !TD1_sum_carry_19);
|
| 28233 |
|
|
|
| 28234 |
|
|
|
| 28235 |
|
|
--VD1_over_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_23
|
| 28236 |
|
|
--operation mode is arithmetic
|
| 28237 |
|
|
|
| 28238 |
|
|
VD1_over_carry_23 = CARRY(VD1_b_o_iv_23 & !VD1_over_carry_22 # !PD1_a_o_23 # !VD1_b_o_iv_23 & !PD1_a_o_23 & !VD1_over_carry_22);
|
| 28239 |
|
|
|
| 28240 |
|
|
|
| 28241 |
|
|
--TD1_lt_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_18
|
| 28242 |
|
|
--operation mode is arithmetic
|
| 28243 |
|
|
|
| 28244 |
|
|
TD1_lt_18 = CARRY(PD1_a_o_18 & VD1_b_o_iv_18 & !TD1_lt_17 # !PD1_a_o_18 & VD1_b_o_iv_18 # !TD1_lt_17);
|
| 28245 |
|
|
|
| 28246 |
|
|
|
| 28247 |
|
|
--TD1_sum_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_19
|
| 28248 |
|
|
--operation mode is arithmetic
|
| 28249 |
|
|
|
| 28250 |
|
|
TD1_sum_carry_19 = CARRY(VD1_b_o_iv_19 & !TD1_sum_carry_18 # !PD1_a_o_19 # !VD1_b_o_iv_19 & !PD1_a_o_19 & !TD1_sum_carry_18);
|
| 28251 |
|
|
|
| 28252 |
|
|
|
| 28253 |
|
|
--VD1_over_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_22
|
| 28254 |
|
|
--operation mode is arithmetic
|
| 28255 |
|
|
|
| 28256 |
|
|
VD1_over_carry_22 = CARRY(VD1_b_o_iv_22 & PD1_a_o_22 & !VD1_over_carry_21 # !VD1_b_o_iv_22 & PD1_a_o_22 # !VD1_over_carry_21);
|
| 28257 |
|
|
|
| 28258 |
|
|
|
| 28259 |
|
|
--TD1_lt_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_17
|
| 28260 |
|
|
--operation mode is arithmetic
|
| 28261 |
|
|
|
| 28262 |
|
|
TD1_lt_17 = CARRY(PD1_a_o_17 & !TD1_lt_16 # !VD1_b_o_iv_17 # !PD1_a_o_17 & !VD1_b_o_iv_17 & !TD1_lt_16);
|
| 28263 |
|
|
|
| 28264 |
|
|
|
| 28265 |
|
|
--TD1_sum_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_18
|
| 28266 |
|
|
--operation mode is arithmetic
|
| 28267 |
|
|
|
| 28268 |
|
|
TD1_sum_carry_18 = CARRY(VD1_b_o_iv_18 & PD1_a_o_18 & !TD1_sum_carry_17 # !VD1_b_o_iv_18 & PD1_a_o_18 # !TD1_sum_carry_17);
|
| 28269 |
|
|
|
| 28270 |
|
|
|
| 28271 |
|
|
--VD1_over_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_21
|
| 28272 |
|
|
--operation mode is arithmetic
|
| 28273 |
|
|
|
| 28274 |
|
|
VD1_over_carry_21 = CARRY(VD1_b_o_iv_21 & !VD1_over_carry_20 # !PD1_a_o_21 # !VD1_b_o_iv_21 & !PD1_a_o_21 & !VD1_over_carry_20);
|
| 28275 |
|
|
|
| 28276 |
|
|
|
| 28277 |
|
|
--TD1_lt_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_16
|
| 28278 |
|
|
--operation mode is arithmetic
|
| 28279 |
|
|
|
| 28280 |
|
|
TD1_lt_16 = CARRY(PD1_a_o_16 & VD1_b_o_iv_16 & !TD1_lt_15 # !PD1_a_o_16 & VD1_b_o_iv_16 # !TD1_lt_15);
|
| 28281 |
|
|
|
| 28282 |
|
|
|
| 28283 |
|
|
--TD1_sum_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_17
|
| 28284 |
|
|
--operation mode is arithmetic
|
| 28285 |
|
|
|
| 28286 |
|
|
TD1_sum_carry_17 = CARRY(VD1_b_o_iv_17 & !TD1_sum_carry_16 # !PD1_a_o_17 # !VD1_b_o_iv_17 & !PD1_a_o_17 & !TD1_sum_carry_16);
|
| 28287 |
|
|
|
| 28288 |
|
|
|
| 28289 |
|
|
--VD1_over_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_20
|
| 28290 |
|
|
--operation mode is arithmetic
|
| 28291 |
|
|
|
| 28292 |
|
|
VD1_over_carry_20 = CARRY(VD1_b_o_iv_20 & PD1_a_o_20 & !VD1_over_carry_19 # !VD1_b_o_iv_20 & PD1_a_o_20 # !VD1_over_carry_19);
|
| 28293 |
|
|
|
| 28294 |
|
|
|
| 28295 |
|
|
--TD1_lt_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_15
|
| 28296 |
|
|
--operation mode is arithmetic
|
| 28297 |
|
|
|
| 28298 |
|
|
TD1_lt_15 = CARRY(PD1_a_o_15 & !TD1_lt_14 # !VD1_b_o_iv_15 # !PD1_a_o_15 & !VD1_b_o_iv_15 & !TD1_lt_14);
|
| 28299 |
|
|
|
| 28300 |
|
|
|
| 28301 |
|
|
--TD1_sum_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_16
|
| 28302 |
|
|
--operation mode is arithmetic
|
| 28303 |
|
|
|
| 28304 |
|
|
TD1_sum_carry_16 = CARRY(VD1_b_o_iv_16 & PD1_a_o_16 & !TD1_sum_carry_15 # !VD1_b_o_iv_16 & PD1_a_o_16 # !TD1_sum_carry_15);
|
| 28305 |
|
|
|
| 28306 |
|
|
|
| 28307 |
|
|
--VD1_over_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_19
|
| 28308 |
|
|
--operation mode is arithmetic
|
| 28309 |
|
|
|
| 28310 |
|
|
VD1_over_carry_19 = CARRY(VD1_b_o_iv_19 & !VD1_over_carry_18 # !PD1_a_o_19 # !VD1_b_o_iv_19 & !PD1_a_o_19 & !VD1_over_carry_18);
|
| 28311 |
|
|
|
| 28312 |
|
|
|
| 28313 |
|
|
--TD1_lt_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_14
|
| 28314 |
|
|
--operation mode is arithmetic
|
| 28315 |
|
|
|
| 28316 |
|
|
TD1_lt_14 = CARRY(PD1_a_o_14 & VD1_b_o_iv_14 & !TD1_lt_13 # !PD1_a_o_14 & VD1_b_o_iv_14 # !TD1_lt_13);
|
| 28317 |
|
|
|
| 28318 |
|
|
|
| 28319 |
|
|
--TD1_sum_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_15
|
| 28320 |
|
|
--operation mode is arithmetic
|
| 28321 |
|
|
|
| 28322 |
|
|
TD1_sum_carry_15 = CARRY(VD1_b_o_iv_15 & !TD1_sum_carry_14 # !PD1_a_o_15 # !VD1_b_o_iv_15 & !PD1_a_o_15 & !TD1_sum_carry_14);
|
| 28323 |
|
|
|
| 28324 |
|
|
|
| 28325 |
|
|
--VD1_over_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_18
|
| 28326 |
|
|
--operation mode is arithmetic
|
| 28327 |
|
|
|
| 28328 |
|
|
VD1_over_carry_18 = CARRY(VD1_b_o_iv_18 & PD1_a_o_18 & !VD1_over_carry_17 # !VD1_b_o_iv_18 & PD1_a_o_18 # !VD1_over_carry_17);
|
| 28329 |
|
|
|
| 28330 |
|
|
|
| 28331 |
|
|
--TD1_lt_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_13
|
| 28332 |
|
|
--operation mode is arithmetic
|
| 28333 |
|
|
|
| 28334 |
|
|
TD1_lt_13 = CARRY(PD1_a_o_13 & !TD1_lt_12 # !VD1_b_o_iv_13 # !PD1_a_o_13 & !VD1_b_o_iv_13 & !TD1_lt_12);
|
| 28335 |
|
|
|
| 28336 |
|
|
|
| 28337 |
|
|
--TD1_sum_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_14
|
| 28338 |
|
|
--operation mode is arithmetic
|
| 28339 |
|
|
|
| 28340 |
|
|
TD1_sum_carry_14 = CARRY(VD1_b_o_iv_14 & PD1_a_o_14 & !TD1_sum_carry_13 # !VD1_b_o_iv_14 & PD1_a_o_14 # !TD1_sum_carry_13);
|
| 28341 |
|
|
|
| 28342 |
|
|
|
| 28343 |
|
|
--VD1_over_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_17
|
| 28344 |
|
|
--operation mode is arithmetic
|
| 28345 |
|
|
|
| 28346 |
|
|
VD1_over_carry_17 = CARRY(VD1_b_o_iv_17 & !VD1_over_carry_16 # !PD1_a_o_17 # !VD1_b_o_iv_17 & !PD1_a_o_17 & !VD1_over_carry_16);
|
| 28347 |
|
|
|
| 28348 |
|
|
|
| 28349 |
|
|
--TD1_lt_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_12
|
| 28350 |
|
|
--operation mode is arithmetic
|
| 28351 |
|
|
|
| 28352 |
|
|
TD1_lt_12 = CARRY(PD1_a_o_12 & VD1_b_o_iv_12 & !TD1_lt_11 # !PD1_a_o_12 & VD1_b_o_iv_12 # !TD1_lt_11);
|
| 28353 |
|
|
|
| 28354 |
|
|
|
| 28355 |
|
|
--TD1_sum_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_13
|
| 28356 |
|
|
--operation mode is arithmetic
|
| 28357 |
|
|
|
| 28358 |
|
|
TD1_sum_carry_13 = CARRY(VD1_b_o_iv_13 & !TD1_sum_carry_12 # !PD1_a_o_13 # !VD1_b_o_iv_13 & !PD1_a_o_13 & !TD1_sum_carry_12);
|
| 28359 |
|
|
|
| 28360 |
|
|
|
| 28361 |
|
|
--VD1_over_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_16
|
| 28362 |
|
|
--operation mode is arithmetic
|
| 28363 |
|
|
|
| 28364 |
|
|
VD1_over_carry_16 = CARRY(VD1_b_o_iv_16 & PD1_a_o_16 & !VD1_over_carry_15 # !VD1_b_o_iv_16 & PD1_a_o_16 # !VD1_over_carry_15);
|
| 28365 |
|
|
|
| 28366 |
|
|
|
| 28367 |
|
|
--TD1_lt_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_11
|
| 28368 |
|
|
--operation mode is arithmetic
|
| 28369 |
|
|
|
| 28370 |
|
|
TD1_lt_11 = CARRY(PD1_a_o_11 & !TD1_lt_10 # !VD1_b_o_iv_11 # !PD1_a_o_11 & !VD1_b_o_iv_11 & !TD1_lt_10);
|
| 28371 |
|
|
|
| 28372 |
|
|
|
| 28373 |
|
|
--TD1_sum_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_12
|
| 28374 |
|
|
--operation mode is arithmetic
|
| 28375 |
|
|
|
| 28376 |
|
|
TD1_sum_carry_12 = CARRY(VD1_b_o_iv_12 & PD1_a_o_12 & !TD1_sum_carry_11 # !VD1_b_o_iv_12 & PD1_a_o_12 # !TD1_sum_carry_11);
|
| 28377 |
|
|
|
| 28378 |
|
|
|
| 28379 |
|
|
--VD1_over_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_15
|
| 28380 |
|
|
--operation mode is arithmetic
|
| 28381 |
|
|
|
| 28382 |
|
|
VD1_over_carry_15 = CARRY(VD1_b_o_iv_15 & !VD1_over_carry_14 # !PD1_a_o_15 # !VD1_b_o_iv_15 & !PD1_a_o_15 & !VD1_over_carry_14);
|
| 28383 |
|
|
|
| 28384 |
|
|
|
| 28385 |
|
|
--TD1_lt_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_10
|
| 28386 |
|
|
--operation mode is arithmetic
|
| 28387 |
|
|
|
| 28388 |
|
|
TD1_lt_10 = CARRY(PD1_a_o_10 & VD1_b_o_iv_10 & !TD1_lt_9 # !PD1_a_o_10 & VD1_b_o_iv_10 # !TD1_lt_9);
|
| 28389 |
|
|
|
| 28390 |
|
|
|
| 28391 |
|
|
--TD1_sum_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_11
|
| 28392 |
|
|
--operation mode is arithmetic
|
| 28393 |
|
|
|
| 28394 |
|
|
TD1_sum_carry_11 = CARRY(VD1_b_o_iv_11 & !TD1_sum_carry_10 # !PD1_a_o_11 # !VD1_b_o_iv_11 & !PD1_a_o_11 & !TD1_sum_carry_10);
|
| 28395 |
|
|
|
| 28396 |
|
|
|
| 28397 |
|
|
--VD1_over_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_14
|
| 28398 |
|
|
--operation mode is arithmetic
|
| 28399 |
|
|
|
| 28400 |
|
|
VD1_over_carry_14 = CARRY(VD1_b_o_iv_14 & PD1_a_o_14 & !VD1_over_carry_13 # !VD1_b_o_iv_14 & PD1_a_o_14 # !VD1_over_carry_13);
|
| 28401 |
|
|
|
| 28402 |
|
|
|
| 28403 |
|
|
--TD1_lt_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_9
|
| 28404 |
|
|
--operation mode is arithmetic
|
| 28405 |
|
|
|
| 28406 |
|
|
TD1_lt_9 = CARRY(PD1_a_o_9 & !TD1_lt_8 # !VD1_b_o_iv_9 # !PD1_a_o_9 & !VD1_b_o_iv_9 & !TD1_lt_8);
|
| 28407 |
|
|
|
| 28408 |
|
|
|
| 28409 |
|
|
--TD1_sum_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_10
|
| 28410 |
|
|
--operation mode is arithmetic
|
| 28411 |
|
|
|
| 28412 |
|
|
TD1_sum_carry_10 = CARRY(VD1_b_o_iv_10 & PD1_a_o_10 & !TD1_sum_carry_9 # !VD1_b_o_iv_10 & PD1_a_o_10 # !TD1_sum_carry_9);
|
| 28413 |
|
|
|
| 28414 |
|
|
|
| 28415 |
|
|
--VD1_over_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_13
|
| 28416 |
|
|
--operation mode is arithmetic
|
| 28417 |
|
|
|
| 28418 |
|
|
VD1_over_carry_13 = CARRY(VD1_b_o_iv_13 & !VD1_over_carry_12 # !PD1_a_o_13 # !VD1_b_o_iv_13 & !PD1_a_o_13 & !VD1_over_carry_12);
|
| 28419 |
|
|
|
| 28420 |
|
|
|
| 28421 |
|
|
--TD1_lt_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_8
|
| 28422 |
|
|
--operation mode is arithmetic
|
| 28423 |
|
|
|
| 28424 |
|
|
TD1_lt_8 = CARRY(PD1_a_o_8 & VD1_b_o_iv_8 & !TD1_lt_7 # !PD1_a_o_8 & VD1_b_o_iv_8 # !TD1_lt_7);
|
| 28425 |
|
|
|
| 28426 |
|
|
|
| 28427 |
|
|
--TD1_sum_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_9
|
| 28428 |
|
|
--operation mode is arithmetic
|
| 28429 |
|
|
|
| 28430 |
|
|
TD1_sum_carry_9 = CARRY(VD1_b_o_iv_9 & !TD1_sum_carry_8 # !PD1_a_o_9 # !VD1_b_o_iv_9 & !PD1_a_o_9 & !TD1_sum_carry_8);
|
| 28431 |
|
|
|
| 28432 |
|
|
|
| 28433 |
|
|
--VD1_over_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_12
|
| 28434 |
|
|
--operation mode is arithmetic
|
| 28435 |
|
|
|
| 28436 |
|
|
VD1_over_carry_12 = CARRY(VD1_b_o_iv_12 & PD1_a_o_12 & !VD1_over_carry_11 # !VD1_b_o_iv_12 & PD1_a_o_12 # !VD1_over_carry_11);
|
| 28437 |
|
|
|
| 28438 |
|
|
|
| 28439 |
|
|
--TD1_lt_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_7
|
| 28440 |
|
|
--operation mode is arithmetic
|
| 28441 |
|
|
|
| 28442 |
|
|
TD1_lt_7 = CARRY(PD1_a_o_7 & !TD1_lt_6 # !VD1_b_o_iv_7 # !PD1_a_o_7 & !VD1_b_o_iv_7 & !TD1_lt_6);
|
| 28443 |
|
|
|
| 28444 |
|
|
|
| 28445 |
|
|
--TD1_sum_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_8
|
| 28446 |
|
|
--operation mode is arithmetic
|
| 28447 |
|
|
|
| 28448 |
|
|
TD1_sum_carry_8 = CARRY(VD1_b_o_iv_8 & PD1_a_o_8 & !TD1_sum_carry_7 # !VD1_b_o_iv_8 & PD1_a_o_8 # !TD1_sum_carry_7);
|
| 28449 |
|
|
|
| 28450 |
|
|
|
| 28451 |
|
|
--VD1_over_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_11
|
| 28452 |
|
|
--operation mode is arithmetic
|
| 28453 |
|
|
|
| 28454 |
|
|
VD1_over_carry_11 = CARRY(VD1_b_o_iv_11 & !VD1_over_carry_10 # !PD1_a_o_11 # !VD1_b_o_iv_11 & !PD1_a_o_11 & !VD1_over_carry_10);
|
| 28455 |
|
|
|
| 28456 |
|
|
|
| 28457 |
|
|
--TD1_lt_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_6
|
| 28458 |
|
|
--operation mode is arithmetic
|
| 28459 |
|
|
|
| 28460 |
|
|
TD1_lt_6 = CARRY(PD1_a_o_6 & VD1_b_o_iv_6 & !TD1_lt_5 # !PD1_a_o_6 & VD1_b_o_iv_6 # !TD1_lt_5);
|
| 28461 |
|
|
|
| 28462 |
|
|
|
| 28463 |
|
|
--TD1_sum_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_7
|
| 28464 |
|
|
--operation mode is arithmetic
|
| 28465 |
|
|
|
| 28466 |
|
|
TD1_sum_carry_7 = CARRY(VD1_b_o_iv_7 & !TD1_sum_carry_6 # !PD1_a_o_7 # !VD1_b_o_iv_7 & !PD1_a_o_7 & !TD1_sum_carry_6);
|
| 28467 |
|
|
|
| 28468 |
|
|
|
| 28469 |
|
|
--VD1_over_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_10
|
| 28470 |
|
|
--operation mode is arithmetic
|
| 28471 |
|
|
|
| 28472 |
|
|
VD1_over_carry_10 = CARRY(VD1_b_o_iv_10 & PD1_a_o_10 & !VD1_over_carry_9 # !VD1_b_o_iv_10 & PD1_a_o_10 # !VD1_over_carry_9);
|
| 28473 |
|
|
|
| 28474 |
|
|
|
| 28475 |
|
|
--TD1_lt_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_5
|
| 28476 |
|
|
--operation mode is arithmetic
|
| 28477 |
|
|
|
| 28478 |
|
|
TD1_lt_5 = CARRY(PD1_a_o_5 & !TD1_lt_4 # !VD1_b_o_iv_5 # !PD1_a_o_5 & !VD1_b_o_iv_5 & !TD1_lt_4);
|
| 28479 |
|
|
|
| 28480 |
|
|
|
| 28481 |
|
|
--TD1_sum_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_6
|
| 28482 |
|
|
--operation mode is arithmetic
|
| 28483 |
|
|
|
| 28484 |
|
|
TD1_sum_carry_6 = CARRY(VD1_b_o_iv_6 & PD1_a_o_6 & !TD1_sum_carry_5 # !VD1_b_o_iv_6 & PD1_a_o_6 # !TD1_sum_carry_5);
|
| 28485 |
|
|
|
| 28486 |
|
|
|
| 28487 |
|
|
--VD1_over_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_9
|
| 28488 |
|
|
--operation mode is arithmetic
|
| 28489 |
|
|
|
| 28490 |
|
|
VD1_over_carry_9 = CARRY(VD1_b_o_iv_9 & !VD1_over_carry_8 # !PD1_a_o_9 # !VD1_b_o_iv_9 & !PD1_a_o_9 & !VD1_over_carry_8);
|
| 28491 |
|
|
|
| 28492 |
|
|
|
| 28493 |
|
|
--TD1_lt_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_4
|
| 28494 |
|
|
--operation mode is arithmetic
|
| 28495 |
|
|
|
| 28496 |
|
|
TD1_lt_4 = CARRY(PD1_a_o_4 & VD1_b_o_iv_4 & !TD1_lt_3 # !PD1_a_o_4 & VD1_b_o_iv_4 # !TD1_lt_3);
|
| 28497 |
|
|
|
| 28498 |
|
|
|
| 28499 |
|
|
--TD1_sum_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_5
|
| 28500 |
|
|
--operation mode is arithmetic
|
| 28501 |
|
|
|
| 28502 |
|
|
TD1_sum_carry_5 = CARRY(VD1_b_o_iv_5 & !TD1_sum_carry_4 # !PD1_a_o_5 # !VD1_b_o_iv_5 & !PD1_a_o_5 & !TD1_sum_carry_4);
|
| 28503 |
|
|
|
| 28504 |
|
|
|
| 28505 |
|
|
--VD1_over_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_8
|
| 28506 |
|
|
--operation mode is arithmetic
|
| 28507 |
|
|
|
| 28508 |
|
|
VD1_over_carry_8 = CARRY(VD1_b_o_iv_8 & PD1_a_o_8 & !VD1_over_carry_7 # !VD1_b_o_iv_8 & PD1_a_o_8 # !VD1_over_carry_7);
|
| 28509 |
|
|
|
| 28510 |
|
|
|
| 28511 |
|
|
--TD1_lt_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_3
|
| 28512 |
|
|
--operation mode is arithmetic
|
| 28513 |
|
|
|
| 28514 |
|
|
TD1_lt_3 = CARRY(PD1_a_o_3 & !TD1_lt_2 # !VD1_b_o_iv_3 # !PD1_a_o_3 & !VD1_b_o_iv_3 & !TD1_lt_2);
|
| 28515 |
|
|
|
| 28516 |
|
|
|
| 28517 |
|
|
--TD1_sum_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_4
|
| 28518 |
|
|
--operation mode is arithmetic
|
| 28519 |
|
|
|
| 28520 |
|
|
TD1_sum_carry_4 = CARRY(VD1_b_o_iv_4 & PD1_a_o_4 & !TD1_sum_carry_3 # !VD1_b_o_iv_4 & PD1_a_o_4 # !TD1_sum_carry_3);
|
| 28521 |
|
|
|
| 28522 |
|
|
|
| 28523 |
|
|
--VD1_over_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_7
|
| 28524 |
|
|
--operation mode is arithmetic
|
| 28525 |
|
|
|
| 28526 |
|
|
VD1_over_carry_7 = CARRY(VD1_b_o_iv_7 & !VD1_over_carry_6 # !PD1_a_o_7 # !VD1_b_o_iv_7 & !PD1_a_o_7 & !VD1_over_carry_6);
|
| 28527 |
|
|
|
| 28528 |
|
|
|
| 28529 |
|
|
--TD1_lt_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_2
|
| 28530 |
|
|
--operation mode is arithmetic
|
| 28531 |
|
|
|
| 28532 |
|
|
TD1_lt_2 = CARRY(PD1_a_o_2 & VD1_b_o_iv_2 & !TD1_lt_1 # !PD1_a_o_2 & VD1_b_o_iv_2 # !TD1_lt_1);
|
| 28533 |
|
|
|
| 28534 |
|
|
|
| 28535 |
|
|
--TD1_sum_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_3
|
| 28536 |
|
|
--operation mode is arithmetic
|
| 28537 |
|
|
|
| 28538 |
|
|
TD1_sum_carry_3 = CARRY(VD1_b_o_iv_3 & !TD1_sum_carry_2 # !PD1_a_o_3 # !VD1_b_o_iv_3 & !PD1_a_o_3 & !TD1_sum_carry_2);
|
| 28539 |
|
|
|
| 28540 |
|
|
|
| 28541 |
|
|
--VD1_over_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_6
|
| 28542 |
|
|
--operation mode is arithmetic
|
| 28543 |
|
|
|
| 28544 |
|
|
VD1_over_carry_6 = CARRY(VD1_b_o_iv_6 & PD1_a_o_6 & !VD1_over_carry_5 # !VD1_b_o_iv_6 & PD1_a_o_6 # !VD1_over_carry_5);
|
| 28545 |
|
|
|
| 28546 |
|
|
|
| 28547 |
|
|
--TD1_lt_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_1
|
| 28548 |
|
|
--operation mode is arithmetic
|
| 28549 |
|
|
|
| 28550 |
|
|
TD1_lt_1 = CARRY(PD1_a_o_1 & !TD1_lt_0 # !VD1_b_o_iv_1 # !PD1_a_o_1 & !VD1_b_o_iv_1 & !TD1_lt_0);
|
| 28551 |
|
|
|
| 28552 |
|
|
|
| 28553 |
|
|
--TD1_sum_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_2
|
| 28554 |
|
|
--operation mode is arithmetic
|
| 28555 |
|
|
|
| 28556 |
|
|
TD1_sum_carry_2 = CARRY(VD1_b_o_iv_2 & PD1_a_o_2 & !TD1_sum_carry_1 # !VD1_b_o_iv_2 & PD1_a_o_2 # !TD1_sum_carry_1);
|
| 28557 |
|
|
|
| 28558 |
|
|
|
| 28559 |
|
|
--VD1_over_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_5
|
| 28560 |
|
|
--operation mode is arithmetic
|
| 28561 |
|
|
|
| 28562 |
|
|
VD1_over_carry_5 = CARRY(VD1_b_o_iv_5 & !VD1_over_carry_4 # !PD1_a_o_5 # !VD1_b_o_iv_5 & !PD1_a_o_5 & !VD1_over_carry_4);
|
| 28563 |
|
|
|
| 28564 |
|
|
|
| 28565 |
|
|
--TD1_lt_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_0
|
| 28566 |
|
|
--operation mode is arithmetic
|
| 28567 |
|
|
|
| 28568 |
|
|
TD1_lt_0 = CARRY(!PD1_a_o_0 & VD1_b_o_iv_0);
|
| 28569 |
|
|
|
| 28570 |
|
|
|
| 28571 |
|
|
--TD1_sum_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_1
|
| 28572 |
|
|
--operation mode is arithmetic
|
| 28573 |
|
|
|
| 28574 |
|
|
TD1_sum_carry_1 = CARRY(VD1_b_o_iv_1 & !TD1_sum_carry_0 # !PD1_a_o_1 # !VD1_b_o_iv_1 & !PD1_a_o_1 & !TD1_sum_carry_0);
|
| 28575 |
|
|
|
| 28576 |
|
|
|
| 28577 |
|
|
--VD1_over_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_4
|
| 28578 |
|
|
--operation mode is arithmetic
|
| 28579 |
|
|
|
| 28580 |
|
|
VD1_over_carry_4 = CARRY(VD1_b_o_iv_4 & PD1_a_o_4 & !VD1_over_carry_3 # !VD1_b_o_iv_4 & PD1_a_o_4 # !VD1_over_carry_3);
|
| 28581 |
|
|
|
| 28582 |
|
|
|
| 28583 |
|
|
--TD1_sum_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_0
|
| 28584 |
|
|
--operation mode is arithmetic
|
| 28585 |
|
|
|
| 28586 |
|
|
TD1_sum_carry_0 = CARRY(PD1_a_o_0 # !VD1_b_o_iv_0);
|
| 28587 |
|
|
|
| 28588 |
|
|
|
| 28589 |
|
|
--VD1_over_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_3
|
| 28590 |
|
|
--operation mode is arithmetic
|
| 28591 |
|
|
|
| 28592 |
|
|
VD1_over_carry_3 = CARRY(VD1_b_o_iv_3 & !VD1_over_carry_2 # !PD1_a_o_3 # !VD1_b_o_iv_3 & !PD1_a_o_3 & !VD1_over_carry_2);
|
| 28593 |
|
|
|
| 28594 |
|
|
|
| 28595 |
|
|
--VD1_over_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_2
|
| 28596 |
|
|
--operation mode is arithmetic
|
| 28597 |
|
|
|
| 28598 |
|
|
VD1_over_carry_2 = CARRY(VD1_b_o_iv_2 & PD1_a_o_2 & !VD1_over_carry_1 # !VD1_b_o_iv_2 & PD1_a_o_2 # !VD1_over_carry_1);
|
| 28599 |
|
|
|
| 28600 |
|
|
|
| 28601 |
|
|
--VD1_over_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_1
|
| 28602 |
|
|
--operation mode is arithmetic
|
| 28603 |
|
|
|
| 28604 |
|
|
VD1_over_carry_1 = CARRY(VD1_b_o_iv_1 & !VD1_over_carry_0 # !PD1_a_o_1 # !VD1_b_o_iv_1 & !PD1_a_o_1 & !VD1_over_carry_0);
|
| 28605 |
|
|
|
| 28606 |
|
|
|
| 28607 |
|
|
--VD1_over_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_0
|
| 28608 |
|
|
--operation mode is arithmetic
|
| 28609 |
|
|
|
| 28610 |
|
|
VD1_over_carry_0 = CARRY(!VD1_b_o_iv_0 & PD1_a_o_0);
|
| 28611 |
|
|
|
| 28612 |
|
|
|
| 28613 |
|
|
--~GND is ~GND
|
| 28614 |
|
|
--operation mode is normal
|
| 28615 |
|
|
|
| 28616 |
|
|
~GND = GND;
|
| 28617 |
|
|
|
| 28618 |
|
|
|
| 28619 |
|
|
--clk is clk
|
| 28620 |
|
|
--operation mode is input
|
| 28621 |
|
|
|
| 28622 |
|
|
clk = INPUT();
|
| 28623 |
|
|
|
| 28624 |
|
|
|
| 28625 |
|
|
--rst is rst
|
| 28626 |
|
|
--operation mode is input
|
| 28627 |
|
|
|
| 28628 |
|
|
rst = INPUT();
|
| 28629 |
|
|
|
| 28630 |
|
|
|
| 28631 |
|
|
--ser_txd is ser_txd
|
| 28632 |
|
|
--operation mode is output
|
| 28633 |
|
|
|
| 28634 |
|
|
ser_txd = OUTPUT(N1_txd);
|
| 28635 |
|
|
|
| 28636 |
|
|
|
| 28637 |
|
|
--seg7led1[6] is seg7led1[6]
|
| 28638 |
|
|
--operation mode is output
|
| 28639 |
|
|
|
| 28640 |
|
|
seg7led1[6] = OUTPUT(H1_N_62_i);
|
| 28641 |
|
|
|
| 28642 |
|
|
|
| 28643 |
|
|
--seg7led1[5] is seg7led1[5]
|
| 28644 |
|
|
--operation mode is output
|
| 28645 |
|
|
|
| 28646 |
|
|
seg7led1[5] = OUTPUT(H1_N_60_i);
|
| 28647 |
|
|
|
| 28648 |
|
|
|
| 28649 |
|
|
--seg7led1[4] is seg7led1[4]
|
| 28650 |
|
|
--operation mode is output
|
| 28651 |
|
|
|
| 28652 |
|
|
seg7led1[4] = OUTPUT(H1_N_58_i);
|
| 28653 |
|
|
|
| 28654 |
|
|
|
| 28655 |
|
|
--seg7led1[3] is seg7led1[3]
|
| 28656 |
|
|
--operation mode is output
|
| 28657 |
|
|
|
| 28658 |
|
|
seg7led1[3] = OUTPUT(H1_m18_0);
|
| 28659 |
|
|
|
| 28660 |
|
|
|
| 28661 |
|
|
--seg7led1[2] is seg7led1[2]
|
| 28662 |
|
|
--operation mode is output
|
| 28663 |
|
|
|
| 28664 |
|
|
seg7led1[2] = OUTPUT(H1_m15_0);
|
| 28665 |
|
|
|
| 28666 |
|
|
|
| 28667 |
|
|
--seg7led1[1] is seg7led1[1]
|
| 28668 |
|
|
--operation mode is output
|
| 28669 |
|
|
|
| 28670 |
|
|
seg7led1[1] = OUTPUT(H1_m11_0);
|
| 28671 |
|
|
|
| 28672 |
|
|
|
| 28673 |
|
|
--seg7led1[0] is seg7led1[0]
|
| 28674 |
|
|
--operation mode is output
|
| 28675 |
|
|
|
| 28676 |
|
|
seg7led1[0] = OUTPUT(H1_N_44_i);
|
| 28677 |
|
|
|
| 28678 |
|
|
|
| 28679 |
|
|
--seg7led2[6] is seg7led2[6]
|
| 28680 |
|
|
--operation mode is output
|
| 28681 |
|
|
|
| 28682 |
|
|
seg7led2[6] = OUTPUT(H1_N_31_i);
|
| 28683 |
|
|
|
| 28684 |
|
|
|
| 28685 |
|
|
--seg7led2[5] is seg7led2[5]
|
| 28686 |
|
|
--operation mode is output
|
| 28687 |
|
|
|
| 28688 |
|
|
seg7led2[5] = OUTPUT(H1_N_29_i);
|
| 28689 |
|
|
|
| 28690 |
|
|
|
| 28691 |
|
|
--seg7led2[4] is seg7led2[4]
|
| 28692 |
|
|
--operation mode is output
|
| 28693 |
|
|
|
| 28694 |
|
|
seg7led2[4] = OUTPUT(H1_N_27_i);
|
| 28695 |
|
|
|
| 28696 |
|
|
|
| 28697 |
|
|
--seg7led2[3] is seg7led2[3]
|
| 28698 |
|
|
--operation mode is output
|
| 28699 |
|
|
|
| 28700 |
|
|
seg7led2[3] = OUTPUT(H1_m18);
|
| 28701 |
|
|
|
| 28702 |
|
|
|
| 28703 |
|
|
--seg7led2[2] is seg7led2[2]
|
| 28704 |
|
|
--operation mode is output
|
| 28705 |
|
|
|
| 28706 |
|
|
seg7led2[2] = OUTPUT(H1_m15);
|
| 28707 |
|
|
|
| 28708 |
|
|
|
| 28709 |
|
|
--seg7led2[1] is seg7led2[1]
|
| 28710 |
|
|
--operation mode is output
|
| 28711 |
|
|
|
| 28712 |
|
|
seg7led2[1] = OUTPUT(H1_m11);
|
| 28713 |
|
|
|
| 28714 |
|
|
|
| 28715 |
|
|
--seg7led2[0] is seg7led2[0]
|
| 28716 |
|
|
--operation mode is output
|
| 28717 |
|
|
|
| 28718 |
|
|
seg7led2[0] = OUTPUT(H1_N_13_i);
|
| 28719 |
|
|
|
| 28720 |
|
|
|
| 28721 |
|
|
--lcd_data[7] is lcd_data[7]
|
| 28722 |
|
|
--operation mode is output
|
| 28723 |
|
|
|
| 28724 |
|
|
lcd_data[7] = OUTPUT(F1_lcd_data_7);
|
| 28725 |
|
|
|
| 28726 |
|
|
|
| 28727 |
|
|
--lcd_data[6] is lcd_data[6]
|
| 28728 |
|
|
--operation mode is output
|
| 28729 |
|
|
|
| 28730 |
|
|
lcd_data[6] = OUTPUT(F1_lcd_data_6);
|
| 28731 |
|
|
|
| 28732 |
|
|
|
| 28733 |
|
|
--lcd_data[5] is lcd_data[5]
|
| 28734 |
|
|
--operation mode is output
|
| 28735 |
|
|
|
| 28736 |
|
|
lcd_data[5] = OUTPUT(F1_lcd_data_5);
|
| 28737 |
|
|
|
| 28738 |
|
|
|
| 28739 |
|
|
--lcd_data[4] is lcd_data[4]
|
| 28740 |
|
|
--operation mode is output
|
| 28741 |
|
|
|
| 28742 |
|
|
lcd_data[4] = OUTPUT(F1_lcd_data_4);
|
| 28743 |
|
|
|
| 28744 |
|
|
|
| 28745 |
|
|
--lcd_data[3] is lcd_data[3]
|
| 28746 |
|
|
--operation mode is output
|
| 28747 |
|
|
|
| 28748 |
|
|
lcd_data[3] = OUTPUT(F1_lcd_data_3);
|
| 28749 |
|
|
|
| 28750 |
|
|
|
| 28751 |
|
|
--lcd_data[2] is lcd_data[2]
|
| 28752 |
|
|
--operation mode is output
|
| 28753 |
|
|
|
| 28754 |
|
|
lcd_data[2] = OUTPUT(F1_lcd_data_2);
|
| 28755 |
|
|
|
| 28756 |
|
|
|
| 28757 |
|
|
--lcd_data[1] is lcd_data[1]
|
| 28758 |
|
|
--operation mode is output
|
| 28759 |
|
|
|
| 28760 |
|
|
lcd_data[1] = OUTPUT(F1_lcd_data_1);
|
| 28761 |
|
|
|
| 28762 |
|
|
|
| 28763 |
|
|
--lcd_data[0] is lcd_data[0]
|
| 28764 |
|
|
--operation mode is output
|
| 28765 |
|
|
|
| 28766 |
|
|
lcd_data[0] = OUTPUT(F1_lcd_data_0);
|
| 28767 |
|
|
|
| 28768 |
|
|
|
| 28769 |
|
|
--lcd_rs is lcd_rs
|
| 28770 |
|
|
--operation mode is output
|
| 28771 |
|
|
|
| 28772 |
|
|
lcd_rs = OUTPUT(F1_cmd_2);
|
| 28773 |
|
|
|
| 28774 |
|
|
|
| 28775 |
|
|
--lcd_rw is lcd_rw
|
| 28776 |
|
|
--operation mode is output
|
| 28777 |
|
|
|
| 28778 |
|
|
lcd_rw = OUTPUT(F1_cmd_3);
|
| 28779 |
|
|
|
| 28780 |
|
|
|
| 28781 |
|
|
--lcd_en is lcd_en
|
| 28782 |
|
|
--operation mode is output
|
| 28783 |
|
|
|
| 28784 |
|
|
lcd_en = OUTPUT(F1_cmd_4);
|
| 28785 |
|
|
|
| 28786 |
|
|
|
| 28787 |
|
|
--led1 is led1
|
| 28788 |
|
|
--operation mode is output
|
| 28789 |
|
|
|
| 28790 |
|
|
led1 = OUTPUT(F1_cmd_5);
|
| 28791 |
|
|
|
| 28792 |
|
|
|
| 28793 |
|
|
--led2 is led2
|
| 28794 |
|
|
--operation mode is output
|
| 28795 |
|
|
|
| 28796 |
|
|
led2 = OUTPUT(F1_cmd_6);
|
| 28797 |
|
|
|
| 28798 |
|
|
|
| 28799 |
|
|
--key1 is key1
|
| 28800 |
|
|
--operation mode is input
|
| 28801 |
|
|
|
| 28802 |
|
|
key1 = INPUT();
|
| 28803 |
|
|
|
| 28804 |
|
|
|
| 28805 |
|
|
--key2 is key2
|
| 28806 |
|
|
--operation mode is input
|
| 28807 |
|
|
|
| 28808 |
|
|
key2 = INPUT();
|
| 28809 |
|
|
|
| 28810 |
|
|
|
| 28811 |
|
|
--ser_rxd is ser_rxd
|
| 28812 |
|
|
--operation mode is input
|
| 28813 |
|
|
|
| 28814 |
|
|
ser_rxd = INPUT();
|
| 28815 |
|
|
|
| 28816 |
|
|
|
