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mcupro |
Analysis & Synthesis report for mips_top
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Mon Oct 13 11:59:16 2008
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Version 4.2 Build 157 12/07/2004 SJ Full Version
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Hierarchy
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5. Cut Buffers Inserted to Break Combinational Loops
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6. General Register Statistics
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7. WYSIWYG Cells
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8. Analysis & Synthesis Resource Utilization by Entity
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9. Analysis & Synthesis Equations
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10. Analysis & Synthesis Source Files Read
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11. Analysis & Synthesis Resource Usage Summary
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12. Analysis & Synthesis RAM Summary
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13. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2004 Altera Corporation
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Any megafunction design, and related netlist (encrypted or decrypted),
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support information, device programming or simulation file, and any other
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associated documentation or information provided by Altera or a partner
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under Altera's Megafunction Partnership Program may be used only
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to program PLD devices (but not masked PLD devices) from Altera. Any
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other use of such megafunction design, netlist, support information,
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device programming or simulation file, or any other related documentation
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or information is prohibited for any other purpose, including, but not
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limited to modification, reverse engineering, de-compiling, or use with
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any other silicon devices, unless such use is explicitly licensed under
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a separate agreement with Altera or a megafunction partner. Title to the
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intellectual property, including patents, copyrights, trademarks, trade
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secrets, or maskworks, embodied in any such megafunction design, netlist,
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support information, device programming or simulation file, or any other
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related documentation or information provided by Altera or a megafunction
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partner, remains with Altera, the megafunction partner, or their respective
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licensors. No other licenses, including any licenses needed under any third
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party's intellectual property, are provided herein.
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+------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+-----------------------------+------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Mon Oct 13 11:59:16 2008 ;
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; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;
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; Revision Name ; mips_top ;
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; Top-level Entity Name ; mips_top ;
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; Family ; Cyclone ;
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; Total logic elements ; 3,649 ;
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; Total pins ; 33 ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 71,680 ;
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; Total PLLs ; 1 ;
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+-----------------------------+------------------------------------------+
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+---------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+--------------------------------------------------------------------+--------------+---------------+
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; Option ; Setting ; Default Value ;
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+--------------------------------------------------------------------+--------------+---------------+
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; Device ; EP1C6Q240C6 ; ;
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; Family name ; Cyclone ; Stratix ;
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; Use smart compilation ; Normal ; Normal ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; Create Debugging Nodes for IP Cores ; off ; off ;
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; Preserve fewer node names ; On ; On ;
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; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL93 ; VHDL93 ;
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; Top-level entity name ; mips_top ; mips_top ;
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; State Machine Processing ; Auto ; Auto ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
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; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Remove Duplicate Logic ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Perform gate-level register retiming ; Off ; Off ;
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; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
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; Auto ROM Replacement ; On ; On ;
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; Auto RAM Replacement ; On ; On ;
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; Auto Shift Register Replacement ; On ; On ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
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; Auto RAM Block Balancing ; On ; On ;
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; Auto Resource Sharing ; Off ; Off ;
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; Allow Any RAM Size For Recognition ; Off ; Off ;
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; Allow Any ROM Size For Recognition ; Off ; Off ;
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; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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; Enable M512 Memory Blocks ; On ; On ;
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+--------------------------------------------------------------------+--------------+---------------+
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+-----------+
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; Hierarchy ;
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+-----------+
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mips_top
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|-- pll50:Ipll
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|-- altpll:altpll_component
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|-- mips_sys:isys
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|-- mips_dvc:imips_dvc
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|-- seg7led_cv:iseg7_cv
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|-- uart0:iuart0
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|-- rxd_d:rxd_rdy_hold_lw
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|-- uart_read:uart_rd_tak
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|-- uart_write:uart_txd
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|-- fifo512_cyclone:fifo
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|-- scfifo_Z1:scfifo_component
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|-- scfifo:U1
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|-- scfifo_e4u:auto_generated
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|-- a_dpfifo_lqr:dpfifo
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|-- a_fefifo_s7f:fifo_state
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|-- cntr_cc7:count_usedw
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|-- dpram_4cm:FIFOram
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|-- altsyncram_ihc1:altsyncram1
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|-- cntr_ud8:rd_ptr_count
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|-- cntr_ud8:wr_ptr
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|-- tmr0:mips_tmr0
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|-- mips_core:mips_core
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|-- mem_module:MEM_CTL
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|-- infile_dmem_ctl_reg:dmem_ctl_post
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|-- mem_addr_ctl:i_mem_addr_ctl
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|-- SYNLPM_LATRS1:wr_en_1_0_
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|-- lpm_latch:U1
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|-- SYNLPM_LATRS1:wr_en_1_1_
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|-- lpm_latch:U1
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|-- SYNLPM_LATRS1:wr_en_1_2_
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|-- lpm_latch:U1
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|-- SYNLPM_LATRS1:wr_en_1_3_
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|-- lpm_latch:U1
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|-- mem_din_ctl:i_mem_din_ctl
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|-- mem_dout_ctl:i_mem_dout_ctl
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|-- SYNLPM_LATR1:dout_1_0__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_1__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_2__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_3__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_4__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_5__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_6__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_7__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_8__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_9__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_10__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_11__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_12__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_13__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_14__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_15__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_16__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_17__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_18__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_19__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_20__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_21__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_22__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_23__Z
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| 203 |
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_24__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_25__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_26__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_27__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_28__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_29__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_30__Z
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:dout_1_31__Z
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| 219 |
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|-- lpm_latch:U1
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|-- r32_reg_1:alu_pass0
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|-- r32_reg_2:alu_pass1
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|-- r32_reg_3:cop_data_reg
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|-- r32_reg_4:cop_dout_reg
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| 224 |
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|-- decode_pipe:decoder_pipe
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|-- decoder:idecoder
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|-- SYNLPM_LATR1:alu_func_1_0_
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|-- lpm_latch:U1
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|-- SYNLPM_LATR1:alu_func_1_1_
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| 229 |
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|-- lpm_latch:U1
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|-- SYNLPM_LATRS1:alu_func_1_2_
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| 231 |
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|-- lpm_latch:U1
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| 232 |
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|-- SYNLPM_LATRS1:alu_func_1_3_
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| 233 |
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|-- lpm_latch:U1
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| 234 |
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|-- SYNLPM_LATR1:alu_func_1_4_
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| 235 |
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|-- lpm_latch:U1
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| 236 |
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|-- SYNLPM_LATR1:alu_we_0_
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| 237 |
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|-- lpm_latch:U1
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| 238 |
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|-- SYNLPM_LATR1:cmp_ctl_1_0_
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| 239 |
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|-- lpm_latch:U1
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| 240 |
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|-- SYNLPM_LATR1:cmp_ctl_1_1_
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| 241 |
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|-- lpm_latch:U1
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| 242 |
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|-- SYNLPM_LATR1:cmp_ctl_1_2_
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| 243 |
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|-- lpm_latch:U1
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| 244 |
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|-- SYNLPM_LATRS1:dmem_ctl_1_0_
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| 245 |
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|-- lpm_latch:U1
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| 246 |
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|-- SYNLPM_LATRS1:dmem_ctl_1_1_
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| 247 |
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|-- lpm_latch:U1
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| 248 |
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|-- SYNLPM_LATRS1:dmem_ctl_1_2_
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| 249 |
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|-- lpm_latch:U1
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| 250 |
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|-- SYNLPM_LATR1:dmem_ctl_1_3_
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| 251 |
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|-- lpm_latch:U1
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| 252 |
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|-- SYNLPM_LATRS1:ext_ctl_1_0_
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| 253 |
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|-- lpm_latch:U1
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| 254 |
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|-- SYNLPM_LATR1:ext_ctl_1_1_
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| 255 |
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|-- lpm_latch:U1
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| 256 |
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|-- SYNLPM_LATR1:ext_ctl_1_2_
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| 257 |
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|-- lpm_latch:U1
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| 258 |
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|-- SYNLPM_LATR1:fsm_dly_1_0_
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| 259 |
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|-- lpm_latch:U1
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| 260 |
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|-- SYNLPM_LATR1:fsm_dly_1_1__Z
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| 261 |
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|-- lpm_latch:U1
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| 262 |
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|-- SYNLPM_LATR1:fsm_dly_1_2__Z
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| 263 |
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|-- lpm_latch:U1
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| 264 |
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|-- SYNLPM_LATR1:muxa_ctl_1_0_
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| 265 |
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|-- lpm_latch:U1
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| 266 |
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|-- SYNLPM_LATRS1:muxa_ctl_1_1_
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| 267 |
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|-- lpm_latch:U1
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| 268 |
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|-- SYNLPM_LATR1:muxb_ctl_1_0_
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| 269 |
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|-- lpm_latch:U1
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| 270 |
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|-- SYNLPM_LATRS1:muxb_ctl_1_1_
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| 271 |
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|-- lpm_latch:U1
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| 272 |
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|-- SYNLPM_LATRS1:pc_gen_ctl_1_0_
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| 273 |
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|-- lpm_latch:U1
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| 274 |
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|-- SYNLPM_LATR1:pc_gen_ctl_1_1_
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| 275 |
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|-- lpm_latch:U1
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| 276 |
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|-- SYNLPM_LATRS1:pc_gen_ctl_1_2_
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| 277 |
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|-- lpm_latch:U1
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| 278 |
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|-- SYNLPM_LATR1:rd_sel_1_0_
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| 279 |
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|-- lpm_latch:U1
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| 280 |
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|-- SYNLPM_LATRS1:rd_sel_1_1_
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| 281 |
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|-- lpm_latch:U1
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| 282 |
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|-- SYNLPM_LATR1:wb_mux_0_
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| 283 |
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|-- lpm_latch:U1
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| 284 |
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|-- SYNLPM_LATR1:wb_we_0_
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| 285 |
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|-- lpm_latch:U1
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| 286 |
|
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|-- pipelinedregs:pipereg
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| 287 |
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|-- muxb_ctl_reg_clr_cls:U1
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| 288 |
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|-- cmp_ctl_reg_clr_cls:U2
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| 289 |
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|-- dmem_ctl_reg_clr_cls:U3
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| 290 |
|
|
|-- ext_ctl_reg_clr_cls:U4
|
| 291 |
|
|
|-- rd_sel_reg_clr_cls:U5
|
| 292 |
|
|
|-- alu_we_reg_clr_cls:U6
|
| 293 |
|
|
|-- muxa_ctl_reg_clr_cls:U7
|
| 294 |
|
|
|-- pc_gen_ctl_reg_clr_cls:U8
|
| 295 |
|
|
|-- dmem_ctl_reg:U9
|
| 296 |
|
|
|-- wb_mux_ctl_reg_clr_cls:U10
|
| 297 |
|
|
|-- wb_we_reg_clr_cls:U11
|
| 298 |
|
|
|-- wb_we_reg:U12
|
| 299 |
|
|
|-- wb_mux_ctl_reg_clr:U13
|
| 300 |
|
|
|-- muxb_ctl_reg_clr:U14
|
| 301 |
|
|
|-- dmem_ctl_reg_clr:U15
|
| 302 |
|
|
|-- alu_func_reg_clr:U16
|
| 303 |
|
|
|-- muxa_ctl_reg_clr:U17
|
| 304 |
|
|
|-- wb_mux_ctl_reg:U18
|
| 305 |
|
|
|-- wb_we_reg_clr:U19
|
| 306 |
|
|
|-- wb_we_reg_1:U20
|
| 307 |
|
|
|-- wb_mux_ctl_reg_1:U21
|
| 308 |
|
|
|-- wb_we_reg_2:U22
|
| 309 |
|
|
|-- alu_we_reg_clr:U24
|
| 310 |
|
|
|-- alu_func_reg_clr_cls:U26
|
| 311 |
|
|
|-- r32_reg_5:ext_reg
|
| 312 |
|
|
|-- rf_stage:iRF_stage
|
| 313 |
|
|
|-- ctl_FSM:MIAN_FSM
|
| 314 |
|
|
|-- SYNLPM_LATR1:next_delay_counter_Sreg0_0_
|
| 315 |
|
|
|-- lpm_latch:U1
|
| 316 |
|
|
|-- SYNLPM_LATS1:next_delay_counter_Sreg0_1_
|
| 317 |
|
|
|-- lpm_latch:U1
|
| 318 |
|
|
|-- SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z
|
| 319 |
|
|
|-- lpm_latch:U1
|
| 320 |
|
|
|-- SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z
|
| 321 |
|
|
|-- lpm_latch:U1
|
| 322 |
|
|
|-- SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z
|
| 323 |
|
|
|-- lpm_latch:U1
|
| 324 |
|
|
|-- SYNLPM_LATS1:next_delay_counter_Sreg0_5_
|
| 325 |
|
|
|-- lpm_latch:U1
|
| 326 |
|
|
|-- compare:i_cmp
|
| 327 |
|
|
|-- ext:i_ext
|
| 328 |
|
|
|-- pc_gen:i_pc_gen
|
| 329 |
|
|
|-- r32_reg_clr_cls:ins_reg
|
| 330 |
|
|
|-- reg_array:reg_bank_cZ
|
| 331 |
|
|
|-- altsyncram:reg_bank_1_I_1_Z
|
| 332 |
|
|
|-- altsyncram_3mc1:auto_generated
|
| 333 |
|
|
|-- altsyncram:reg_bank_I_1_Z
|
| 334 |
|
|
|-- altsyncram_3mc1:auto_generated
|
| 335 |
|
|
|-- fwd_mux:rf_fwd_rt
|
| 336 |
|
|
|-- fwd_mux_1:rs_fwd_rs
|
| 337 |
|
|
|-- exec_stage:iexec_stage
|
| 338 |
|
|
|-- big_alu:MIPS_alu
|
| 339 |
|
|
|-- alu:mips_alu
|
| 340 |
|
|
|-- shifter_tak:mips_shifter
|
| 341 |
|
|
|-- muldiv_ff:muldiv_ff
|
| 342 |
|
|
|-- fwd_mux_2:dmem_fw_mux
|
| 343 |
|
|
|-- alu_muxa:i_alu_muxa
|
| 344 |
|
|
|-- alu_muxb:i_alu_muxb
|
| 345 |
|
|
|-- r32_reg:pc_nxt
|
| 346 |
|
|
|-- r32_reg_cls:spc
|
| 347 |
|
|
|-- forward:iforward
|
| 348 |
|
|
|-- forward_node_fw_alu_rs:fw_alu_rs
|
| 349 |
|
|
|-- forward_node_fw_alu_rs_1:fw_alu_rt
|
| 350 |
|
|
|-- forward_node_fw_alu_rs_2:fw_cmp_rs
|
| 351 |
|
|
|-- forward_node_fw_alu_rs_3:fw_cmp_rt
|
| 352 |
|
|
|-- fw_latch5:fw_reg_rns
|
| 353 |
|
|
|-- fw_latch5_1:fw_reg_rnt
|
| 354 |
|
|
|-- r32_reg_6:pc
|
| 355 |
|
|
|-- r5_reg:rnd_pass0
|
| 356 |
|
|
|-- r5_reg_1:rnd_pass1
|
| 357 |
|
|
|-- r5_reg_2:rnd_pass2
|
| 358 |
|
|
|-- r32_reg_7:rs_reg
|
| 359 |
|
|
|-- r32_reg_8:rt_reg
|
| 360 |
|
|
|-- mem_array:ram_8k
|
| 361 |
|
|
|-- ram2048x8_0:ram0
|
| 362 |
|
|
|-- altsyncram:altsyncram_component
|
| 363 |
|
|
|-- altsyncram_eht1:auto_generated
|
| 364 |
|
|
|-- ram2048x8_1:ram1
|
| 365 |
|
|
|-- altsyncram:altsyncram_component
|
| 366 |
|
|
|-- altsyncram_fht1:auto_generated
|
| 367 |
|
|
|-- ram2048x8_2:ram2
|
| 368 |
|
|
|-- altsyncram:altsyncram_component
|
| 369 |
|
|
|-- altsyncram_ght1:auto_generated
|
| 370 |
|
|
|-- ram2048x8_3:ram3
|
| 371 |
|
|
|-- altsyncram:altsyncram_component
|
| 372 |
|
|
|-- altsyncram_hht1:auto_generated
|
| 373 |
|
|
|
| 374 |
|
|
|
| 375 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------+
|
| 376 |
|
|
; Cut Buffers Inserted to Break Combinational Loops ;
|
| 377 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------+----+
|
| 378 |
|
|
; Buffer Name ; ;
|
| 379 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------+----+
|
| 380 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_7__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 381 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_6__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 382 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_5__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 383 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_4__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 384 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_3__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 385 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_2__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 386 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_1__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 387 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_0__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 388 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 389 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_4_|lpm_latch:U1|q[0]~0 ; ;
|
| 390 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 391 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1|q[0]~0 ; ;
|
| 392 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 393 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 394 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_mux_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 395 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_we_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 396 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_we_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 397 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 398 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 399 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 400 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1|q[0]~0 ; ;
|
| 401 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1|q[0]~0 ; ;
|
| 402 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxa_ctl_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 403 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:rd_sel_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 404 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 405 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 406 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:dmem_ctl_1_3_|lpm_latch:U1|q[0]~0 ; ;
|
| 407 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 408 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1|q[0]~0 ; ;
|
| 409 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxb_ctl_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 410 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 411 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 412 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_2_|lpm_latch:U1|q[0]~0 ; ;
|
| 413 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 414 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_8__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 415 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_9__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 416 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 417 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_|lpm_latch:U1|q[0]~0 ; ;
|
| 418 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 419 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1|q[0]~0 ; ;
|
| 420 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_31__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 421 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1|q[0]~0 ; ;
|
| 422 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 423 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:pc_gen_ctl_1_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 424 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 425 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 426 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 427 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 428 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_30__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 429 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_28__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 430 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_29__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 431 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_11__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 432 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_13__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 433 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_12__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 434 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_14__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 435 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_21__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 436 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_22__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 437 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_25__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 438 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_26__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 439 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_17__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 440 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_18__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 441 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_10__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 442 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_15__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 443 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_27__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 444 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_19__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 445 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_20__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 446 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_16__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 447 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_23__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 448 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_24__Z|lpm_latch:U1|q[0]~0 ; ;
|
| 449 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_|lpm_latch:U1|q[0]~0 ; ;
|
| 450 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_2_|lpm_latch:U1|q[0]~0 ; ;
|
| 451 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_1_|lpm_latch:U1|q[0]~0 ; ;
|
| 452 |
|
|
; Number of buffers inserted to break combinational loops ; 72 ;
|
| 453 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------+----+
|
| 454 |
|
|
|
| 455 |
|
|
|
| 456 |
|
|
+------------------------------------------------------+
|
| 457 |
|
|
; General Register Statistics ;
|
| 458 |
|
|
+----------------------------------------------+-------+
|
| 459 |
|
|
; Statistic ; Value ;
|
| 460 |
|
|
+----------------------------------------------+-------+
|
| 461 |
|
|
; Total registers ; 863 ;
|
| 462 |
|
|
; Number of registers using Synchronous Clear ; 268 ;
|
| 463 |
|
|
; Number of registers using Synchronous Load ; 32 ;
|
| 464 |
|
|
; Number of registers using Asynchronous Clear ; 1 ;
|
| 465 |
|
|
; Number of registers using Asynchronous Load ; 0 ;
|
| 466 |
|
|
; Number of registers using Clock Enable ; 352 ;
|
| 467 |
|
|
; Number of registers using Output Enable ; 0 ;
|
| 468 |
|
|
; Number of registers using Preset ; 0 ;
|
| 469 |
|
|
+----------------------------------------------+-------+
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
+----------------------------------------------------------------+
|
| 473 |
|
|
; WYSIWYG Cells ;
|
| 474 |
|
|
+--------------------------------------------------------+-------+
|
| 475 |
|
|
; Statistic ; Value ;
|
| 476 |
|
|
+--------------------------------------------------------+-------+
|
| 477 |
|
|
; Number of WYSIWYG cells ; 3548 ;
|
| 478 |
|
|
; Number of synthesis-generated cells ; 101 ;
|
| 479 |
|
|
; Number of WYSIWYG LUTs ; 3262 ;
|
| 480 |
|
|
; Number of synthesis-generated LUTs ; 99 ;
|
| 481 |
|
|
; Number of WYSIWYG registers ; 859 ;
|
| 482 |
|
|
; Number of synthesis-generated registers ; 4 ;
|
| 483 |
|
|
; Number of cells with combinational logic only ; 2786 ;
|
| 484 |
|
|
; Number of cells with registers only ; 288 ;
|
| 485 |
|
|
; Number of cells with combinational logic and registers ; 575 ;
|
| 486 |
|
|
+--------------------------------------------------------+-------+
|
| 487 |
|
|
|
| 488 |
|
|
|
| 489 |
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 490 |
|
|
; Analysis & Synthesis Resource Utilization by Entity ;
|
| 491 |
|
|
+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 492 |
|
|
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
|
| 493 |
|
|
+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 494 |
|
|
; |mips_top ; 3649 (3) ; 863 ; 71680 ; 33 ; 0 ; 2786 (1) ; 288 (2) ; 575 (0) ; 460 (0) ; |mips_top ;
|
| 495 |
|
|
; |mem_array:ram_8k| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k ;
|
| 496 |
|
|
; |ram2048x8_0:ram0| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0 ;
|
| 497 |
|
|
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component ;
|
| 498 |
|
|
; |altsyncram_eht1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated ;
|
| 499 |
|
|
; |ram2048x8_1:ram1| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1 ;
|
| 500 |
|
|
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component ;
|
| 501 |
|
|
; |altsyncram_fht1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated ;
|
| 502 |
|
|
; |ram2048x8_2:ram2| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2 ;
|
| 503 |
|
|
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component ;
|
| 504 |
|
|
; |altsyncram_ght1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated ;
|
| 505 |
|
|
; |ram2048x8_3:ram3| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3 ;
|
| 506 |
|
|
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component ;
|
| 507 |
|
|
; |altsyncram_hht1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated ;
|
| 508 |
|
|
; |mips_sys:isys| ; 3646 (44) ; 861 ; 6144 ; 31 ; 0 ; 2785 (44) ; 286 (0) ; 575 (0) ; 460 (0) ; |mips_top|mips_sys:isys ;
|
| 509 |
|
|
; |mips_core:mips_core| ; 3242 (31) ; 604 ; 2048 ; 0 ; 0 ; 2638 (31) ; 215 (0) ; 389 (0) ; 363 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core ;
|
| 510 |
|
|
; |decode_pipe:decoder_pipe| ; 277 (0) ; 52 ; 0 ; 0 ; 0 ; 225 (0) ; 50 (0) ; 2 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe ;
|
| 511 |
|
|
; |decoder:idecoder| ; 225 (184) ; 0 ; 0 ; 0 ; 0 ; 225 (184) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder ;
|
| 512 |
|
|
; |SYNLPM_LATR1:alu_func_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_0_ ;
|
| 513 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_0_|lpm_latch:U1 ;
|
| 514 |
|
|
; |SYNLPM_LATR1:alu_func_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_1_ ;
|
| 515 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_1_|lpm_latch:U1 ;
|
| 516 |
|
|
; |SYNLPM_LATR1:alu_func_1_4_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_4_ ;
|
| 517 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_4_|lpm_latch:U1 ;
|
| 518 |
|
|
; |SYNLPM_LATR1:alu_we_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_we_0_ ;
|
| 519 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_we_0_|lpm_latch:U1 ;
|
| 520 |
|
|
; |SYNLPM_LATR1:cmp_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_ ;
|
| 521 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_|lpm_latch:U1 ;
|
| 522 |
|
|
; |SYNLPM_LATR1:cmp_ctl_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_1_ ;
|
| 523 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_1_|lpm_latch:U1 ;
|
| 524 |
|
|
; |SYNLPM_LATR1:cmp_ctl_1_2_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_2_ ;
|
| 525 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_2_|lpm_latch:U1 ;
|
| 526 |
|
|
; |SYNLPM_LATR1:dmem_ctl_1_3_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:dmem_ctl_1_3_ ;
|
| 527 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:dmem_ctl_1_3_|lpm_latch:U1 ;
|
| 528 |
|
|
; |SYNLPM_LATR1:ext_ctl_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_1_ ;
|
| 529 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_1_|lpm_latch:U1 ;
|
| 530 |
|
|
; |SYNLPM_LATR1:ext_ctl_1_2_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_2_ ;
|
| 531 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_2_|lpm_latch:U1 ;
|
| 532 |
|
|
; |SYNLPM_LATR1:fsm_dly_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_ ;
|
| 533 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_|lpm_latch:U1 ;
|
| 534 |
|
|
; |SYNLPM_LATR1:fsm_dly_1_1__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z ;
|
| 535 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z|lpm_latch:U1 ;
|
| 536 |
|
|
; |SYNLPM_LATR1:fsm_dly_1_2__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z ;
|
| 537 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z|lpm_latch:U1 ;
|
| 538 |
|
|
; |SYNLPM_LATR1:muxa_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxa_ctl_1_0_ ;
|
| 539 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxa_ctl_1_0_|lpm_latch:U1 ;
|
| 540 |
|
|
; |SYNLPM_LATR1:muxb_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxb_ctl_1_0_ ;
|
| 541 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxb_ctl_1_0_|lpm_latch:U1 ;
|
| 542 |
|
|
; |SYNLPM_LATR1:pc_gen_ctl_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:pc_gen_ctl_1_1_ ;
|
| 543 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:pc_gen_ctl_1_1_|lpm_latch:U1 ;
|
| 544 |
|
|
; |SYNLPM_LATR1:rd_sel_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:rd_sel_1_0_ ;
|
| 545 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:rd_sel_1_0_|lpm_latch:U1 ;
|
| 546 |
|
|
; |SYNLPM_LATR1:wb_mux_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_mux_0_ ;
|
| 547 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_mux_0_|lpm_latch:U1 ;
|
| 548 |
|
|
; |SYNLPM_LATR1:wb_we_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_we_0_ ;
|
| 549 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_we_0_|lpm_latch:U1 ;
|
| 550 |
|
|
; |SYNLPM_LATRS1:alu_func_1_2_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_ ;
|
| 551 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1 ;
|
| 552 |
|
|
; |SYNLPM_LATRS1:alu_func_1_3_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_ ;
|
| 553 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1 ;
|
| 554 |
|
|
; |SYNLPM_LATRS1:dmem_ctl_1_0_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_ ;
|
| 555 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1 ;
|
| 556 |
|
|
; |SYNLPM_LATRS1:dmem_ctl_1_1_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_ ;
|
| 557 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1 ;
|
| 558 |
|
|
; |SYNLPM_LATRS1:dmem_ctl_1_2_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_ ;
|
| 559 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1 ;
|
| 560 |
|
|
; |SYNLPM_LATRS1:ext_ctl_1_0_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_ ;
|
| 561 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1 ;
|
| 562 |
|
|
; |SYNLPM_LATRS1:muxa_ctl_1_1_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_ ;
|
| 563 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1 ;
|
| 564 |
|
|
; |SYNLPM_LATRS1:muxb_ctl_1_1_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_ ;
|
| 565 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1 ;
|
| 566 |
|
|
; |SYNLPM_LATRS1:pc_gen_ctl_1_0_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_ ;
|
| 567 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1 ;
|
| 568 |
|
|
; |SYNLPM_LATRS1:pc_gen_ctl_1_2_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_ ;
|
| 569 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1 ;
|
| 570 |
|
|
; |SYNLPM_LATRS1:rd_sel_1_1_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_ ;
|
| 571 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1 ;
|
| 572 |
|
|
; |pipelinedregs:pipereg| ; 52 (0) ; 52 ; 0 ; 0 ; 0 ; 0 (0) ; 50 (0) ; 2 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg ;
|
| 573 |
|
|
; |alu_func_reg_clr:U16| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16 ;
|
| 574 |
|
|
; |alu_func_reg_clr_cls:U26| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26 ;
|
| 575 |
|
|
; |alu_we_reg_clr:U24| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr:U24 ;
|
| 576 |
|
|
; |alu_we_reg_clr_cls:U6| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr_cls:U6 ;
|
| 577 |
|
|
; |cmp_ctl_reg_clr_cls:U2| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2 ;
|
| 578 |
|
|
; |dmem_ctl_reg:U9| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9 ;
|
| 579 |
|
|
; |dmem_ctl_reg_clr:U15| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15 ;
|
| 580 |
|
|
; |dmem_ctl_reg_clr_cls:U3| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3 ;
|
| 581 |
|
|
; |ext_ctl_reg_clr_cls:U4| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4 ;
|
| 582 |
|
|
; |muxa_ctl_reg_clr:U17| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17 ;
|
| 583 |
|
|
; |muxa_ctl_reg_clr_cls:U7| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr_cls:U7 ;
|
| 584 |
|
|
; |muxb_ctl_reg_clr:U14| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr:U14 ;
|
| 585 |
|
|
; |muxb_ctl_reg_clr_cls:U1| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr_cls:U1 ;
|
| 586 |
|
|
; |pc_gen_ctl_reg_clr_cls:U8| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8 ;
|
| 587 |
|
|
; |rd_sel_reg_clr_cls:U5| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|rd_sel_reg_clr_cls:U5 ;
|
| 588 |
|
|
; |wb_mux_ctl_reg:U18| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg:U18 ;
|
| 589 |
|
|
; |wb_mux_ctl_reg_1:U21| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_1:U21 ;
|
| 590 |
|
|
; |wb_mux_ctl_reg_clr:U13| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr:U13 ;
|
| 591 |
|
|
; |wb_mux_ctl_reg_clr_cls:U10| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr_cls:U10 ;
|
| 592 |
|
|
; |wb_we_reg:U12| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg:U12 ;
|
| 593 |
|
|
; |wb_we_reg_1:U20| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_1:U20 ;
|
| 594 |
|
|
; |wb_we_reg_2:U22| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_2:U22 ;
|
| 595 |
|
|
; |wb_we_reg_clr:U19| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr:U19 ;
|
| 596 |
|
|
; |wb_we_reg_clr_cls:U11| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr_cls:U11 ;
|
| 597 |
|
|
; |exec_stage:iexec_stage| ; 1982 (1) ; 179 ; 0 ; 0 ; 0 ; 1803 (1) ; 34 (0) ; 145 (0) ; 331 (1) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage ;
|
| 598 |
|
|
; |alu_muxa:i_alu_muxa| ; 162 (162) ; 0 ; 0 ; 0 ; 0 ; 162 (162) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa ;
|
| 599 |
|
|
; |alu_muxb:i_alu_muxb| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb ;
|
| 600 |
|
|
; |big_alu:MIPS_alu| ; 1716 (95) ; 115 ; 0 ; 0 ; 0 ; 1601 (95) ; 1 (0) ; 114 (0) ; 301 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu ;
|
| 601 |
|
|
; |alu:mips_alu| ; 242 (242) ; 0 ; 0 ; 0 ; 0 ; 242 (242) ; 0 (0) ; 0 (0) ; 98 (98) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu ;
|
| 602 |
|
|
; |muldiv_ff:muldiv_ff| ; 769 (769) ; 115 ; 0 ; 0 ; 0 ; 654 (654) ; 1 (1) ; 114 (114) ; 203 (203) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff ;
|
| 603 |
|
|
; |shifter_tak:mips_shifter| ; 610 (610) ; 0 ; 0 ; 0 ; 0 ; 610 (610) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter ;
|
| 604 |
|
|
; |fwd_mux_2:dmem_fw_mux| ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux ;
|
| 605 |
|
|
; |r32_reg:pc_nxt| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 31 (31) ; 29 (29) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt ;
|
| 606 |
|
|
; |r32_reg_cls:spc| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc ;
|
| 607 |
|
|
; |forward:iforward| ; 43 (0) ; 10 ; 0 ; 0 ; 0 ; 33 (0) ; 10 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward ;
|
| 608 |
|
|
; |forward_node_fw_alu_rs:fw_alu_rs| ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs ;
|
| 609 |
|
|
; |forward_node_fw_alu_rs_1:fw_alu_rt| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt ;
|
| 610 |
|
|
; |forward_node_fw_alu_rs_2:fw_cmp_rs| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs ;
|
| 611 |
|
|
; |forward_node_fw_alu_rs_3:fw_cmp_rt| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt ;
|
| 612 |
|
|
; |fw_latch5:fw_reg_rns| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns ;
|
| 613 |
|
|
; |fw_latch5_1:fw_reg_rnt| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt ;
|
| 614 |
|
|
; |mem_module:MEM_CTL| ; 176 (0) ; 6 ; 0 ; 0 ; 0 ; 170 (0) ; 0 (0) ; 6 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL ;
|
| 615 |
|
|
; |infile_dmem_ctl_reg:dmem_ctl_post| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post ;
|
| 616 |
|
|
; |mem_addr_ctl:i_mem_addr_ctl| ; 14 (6) ; 0 ; 0 ; 0 ; 0 ; 14 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl ;
|
| 617 |
|
|
; |SYNLPM_LATRS1:wr_en_1_0_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_ ;
|
| 618 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1 ;
|
| 619 |
|
|
; |SYNLPM_LATRS1:wr_en_1_1_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_ ;
|
| 620 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1 ;
|
| 621 |
|
|
; |SYNLPM_LATRS1:wr_en_1_2_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_ ;
|
| 622 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1 ;
|
| 623 |
|
|
; |SYNLPM_LATRS1:wr_en_1_3_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_ ;
|
| 624 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1 ;
|
| 625 |
|
|
; |mem_din_ctl:i_mem_din_ctl| ; 34 (34) ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl ;
|
| 626 |
|
|
; |mem_dout_ctl:i_mem_dout_ctl| ; 122 (90) ; 0 ; 0 ; 0 ; 0 ; 122 (90) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl ;
|
| 627 |
|
|
; |SYNLPM_LATR1:dout_1_0__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_0__Z ;
|
| 628 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_0__Z|lpm_latch:U1 ;
|
| 629 |
|
|
; |SYNLPM_LATR1:dout_1_10__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_10__Z ;
|
| 630 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_10__Z|lpm_latch:U1 ;
|
| 631 |
|
|
; |SYNLPM_LATR1:dout_1_11__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_11__Z ;
|
| 632 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_11__Z|lpm_latch:U1 ;
|
| 633 |
|
|
; |SYNLPM_LATR1:dout_1_12__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_12__Z ;
|
| 634 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_12__Z|lpm_latch:U1 ;
|
| 635 |
|
|
; |SYNLPM_LATR1:dout_1_13__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_13__Z ;
|
| 636 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_13__Z|lpm_latch:U1 ;
|
| 637 |
|
|
; |SYNLPM_LATR1:dout_1_14__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_14__Z ;
|
| 638 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_14__Z|lpm_latch:U1 ;
|
| 639 |
|
|
; |SYNLPM_LATR1:dout_1_15__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_15__Z ;
|
| 640 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_15__Z|lpm_latch:U1 ;
|
| 641 |
|
|
; |SYNLPM_LATR1:dout_1_16__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_16__Z ;
|
| 642 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_16__Z|lpm_latch:U1 ;
|
| 643 |
|
|
; |SYNLPM_LATR1:dout_1_17__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_17__Z ;
|
| 644 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_17__Z|lpm_latch:U1 ;
|
| 645 |
|
|
; |SYNLPM_LATR1:dout_1_18__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_18__Z ;
|
| 646 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_18__Z|lpm_latch:U1 ;
|
| 647 |
|
|
; |SYNLPM_LATR1:dout_1_19__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_19__Z ;
|
| 648 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_19__Z|lpm_latch:U1 ;
|
| 649 |
|
|
; |SYNLPM_LATR1:dout_1_1__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_1__Z ;
|
| 650 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_1__Z|lpm_latch:U1 ;
|
| 651 |
|
|
; |SYNLPM_LATR1:dout_1_20__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_20__Z ;
|
| 652 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_20__Z|lpm_latch:U1 ;
|
| 653 |
|
|
; |SYNLPM_LATR1:dout_1_21__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_21__Z ;
|
| 654 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_21__Z|lpm_latch:U1 ;
|
| 655 |
|
|
; |SYNLPM_LATR1:dout_1_22__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_22__Z ;
|
| 656 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_22__Z|lpm_latch:U1 ;
|
| 657 |
|
|
; |SYNLPM_LATR1:dout_1_23__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_23__Z ;
|
| 658 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_23__Z|lpm_latch:U1 ;
|
| 659 |
|
|
; |SYNLPM_LATR1:dout_1_24__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_24__Z ;
|
| 660 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_24__Z|lpm_latch:U1 ;
|
| 661 |
|
|
; |SYNLPM_LATR1:dout_1_25__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_25__Z ;
|
| 662 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_25__Z|lpm_latch:U1 ;
|
| 663 |
|
|
; |SYNLPM_LATR1:dout_1_26__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_26__Z ;
|
| 664 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_26__Z|lpm_latch:U1 ;
|
| 665 |
|
|
; |SYNLPM_LATR1:dout_1_27__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_27__Z ;
|
| 666 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_27__Z|lpm_latch:U1 ;
|
| 667 |
|
|
; |SYNLPM_LATR1:dout_1_28__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_28__Z ;
|
| 668 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_28__Z|lpm_latch:U1 ;
|
| 669 |
|
|
; |SYNLPM_LATR1:dout_1_29__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_29__Z ;
|
| 670 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_29__Z|lpm_latch:U1 ;
|
| 671 |
|
|
; |SYNLPM_LATR1:dout_1_2__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_2__Z ;
|
| 672 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_2__Z|lpm_latch:U1 ;
|
| 673 |
|
|
; |SYNLPM_LATR1:dout_1_30__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_30__Z ;
|
| 674 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_30__Z|lpm_latch:U1 ;
|
| 675 |
|
|
; |SYNLPM_LATR1:dout_1_31__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_31__Z ;
|
| 676 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_31__Z|lpm_latch:U1 ;
|
| 677 |
|
|
; |SYNLPM_LATR1:dout_1_3__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_3__Z ;
|
| 678 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_3__Z|lpm_latch:U1 ;
|
| 679 |
|
|
; |SYNLPM_LATR1:dout_1_4__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_4__Z ;
|
| 680 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_4__Z|lpm_latch:U1 ;
|
| 681 |
|
|
; |SYNLPM_LATR1:dout_1_5__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_5__Z ;
|
| 682 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_5__Z|lpm_latch:U1 ;
|
| 683 |
|
|
; |SYNLPM_LATR1:dout_1_6__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_6__Z ;
|
| 684 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_6__Z|lpm_latch:U1 ;
|
| 685 |
|
|
; |SYNLPM_LATR1:dout_1_7__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_7__Z ;
|
| 686 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_7__Z|lpm_latch:U1 ;
|
| 687 |
|
|
; |SYNLPM_LATR1:dout_1_8__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_8__Z ;
|
| 688 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_8__Z|lpm_latch:U1 ;
|
| 689 |
|
|
; |SYNLPM_LATR1:dout_1_9__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_9__Z ;
|
| 690 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_9__Z|lpm_latch:U1 ;
|
| 691 |
|
|
; |r32_reg_1:alu_pass0| ; 30 (30) ; 30 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 30 (30) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0 ;
|
| 692 |
|
|
; |r32_reg_2:alu_pass1| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1 ;
|
| 693 |
|
|
; |r32_reg_3:cop_data_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg ;
|
| 694 |
|
|
; |r32_reg_4:cop_dout_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg ;
|
| 695 |
|
|
; |r32_reg_5:ext_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg ;
|
| 696 |
|
|
; |r32_reg_6:pc| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_6:pc ;
|
| 697 |
|
|
; |r32_reg_7:rs_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg ;
|
| 698 |
|
|
; |r32_reg_8:rt_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg ;
|
| 699 |
|
|
; |r5_reg:rnd_pass0| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0 ;
|
| 700 |
|
|
; |r5_reg_1:rnd_pass1| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1 ;
|
| 701 |
|
|
; |r5_reg_2:rnd_pass2| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2 ;
|
| 702 |
|
|
; |rf_stage:iRF_stage| ; 464 (0) ; 88 ; 2048 ; 0 ; 0 ; 376 (0) ; 47 (0) ; 41 (0) ; 32 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage ;
|
| 703 |
|
|
; |compare:i_cmp| ; 37 (37) ; 0 ; 0 ; 0 ; 0 ; 37 (37) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp ;
|
| 704 |
|
|
; |ctl_FSM:MIAN_FSM| ; 39 (33) ; 14 ; 0 ; 0 ; 0 ; 25 (19) ; 5 (5) ; 9 (9) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM ;
|
| 705 |
|
|
; |SYNLPM_LATR1:next_delay_counter_Sreg0_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_0_ ;
|
| 706 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_0_|lpm_latch:U1 ;
|
| 707 |
|
|
; |SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z ;
|
| 708 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z|lpm_latch:U1 ;
|
| 709 |
|
|
; |SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z ;
|
| 710 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z|lpm_latch:U1 ;
|
| 711 |
|
|
; |SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z ;
|
| 712 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z|lpm_latch:U1 ;
|
| 713 |
|
|
; |SYNLPM_LATS1:next_delay_counter_Sreg0_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_1_ ;
|
| 714 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_1_|lpm_latch:U1 ;
|
| 715 |
|
|
; |SYNLPM_LATS1:next_delay_counter_Sreg0_5_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_ ;
|
| 716 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_|lpm_latch:U1 ;
|
| 717 |
|
|
; |ext:i_ext| ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; 22 (22) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext ;
|
| 718 |
|
|
; |fwd_mux:rf_fwd_rt| ; 65 (65) ; 0 ; 0 ; 0 ; 0 ; 65 (65) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt ;
|
| 719 |
|
|
; |fwd_mux_1:rs_fwd_rs| ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; 64 (64) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs ;
|
| 720 |
|
|
; |pc_gen:i_pc_gen| ; 136 (136) ; 0 ; 0 ; 0 ; 0 ; 136 (136) ; 0 (0) ; 0 (0) ; 32 (32) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen ;
|
| 721 |
|
|
; |r32_reg_clr_cls:ins_reg| ; 26 (26) ; 26 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (26) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg ;
|
| 722 |
|
|
; |reg_array:reg_bank_cZ| ; 75 (75) ; 48 ; 2048 ; 0 ; 0 ; 27 (27) ; 16 (16) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ ;
|
| 723 |
|
|
; |altsyncram:reg_bank_1_I_1_Z| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z ;
|
| 724 |
|
|
; |altsyncram_3mc1:auto_generated| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated ;
|
| 725 |
|
|
; |altsyncram:reg_bank_I_1_Z| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z ;
|
| 726 |
|
|
; |altsyncram_3mc1:auto_generated| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated ;
|
| 727 |
|
|
; |mips_dvc:imips_dvc| ; 360 (121) ; 257 ; 4096 ; 0 ; 0 ; 103 (37) ; 71 (50) ; 186 (34) ; 97 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc ;
|
| 728 |
|
|
; |seg7led_cv:iseg7_cv| ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv ;
|
| 729 |
|
|
; |tmr0:mips_tmr0| ; 76 (76) ; 64 ; 0 ; 0 ; 0 ; 12 (12) ; 0 (0) ; 64 (64) ; 32 (32) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0 ;
|
| 730 |
|
|
; |uart0:iuart0| ; 149 (0) ; 109 ; 4096 ; 0 ; 0 ; 40 (0) ; 21 (0) ; 88 (0) ; 65 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0 ;
|
| 731 |
|
|
; |rxd_d:rxd_rdy_hold_lw| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|rxd_d:rxd_rdy_hold_lw ;
|
| 732 |
|
|
; |uart_read:uart_rd_tak| ; 55 (55) ; 42 ; 0 ; 0 ; 0 ; 13 (13) ; 18 (18) ; 24 (24) ; 19 (19) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak ;
|
| 733 |
|
|
; |uart_write:uart_txd| ; 93 (55) ; 66 ; 4096 ; 0 ; 0 ; 27 (18) ; 3 (3) ; 63 (34) ; 46 (19) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd ;
|
| 734 |
|
|
; |fifo512_cyclone:fifo| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo ;
|
| 735 |
|
|
; |scfifo_Z1:scfifo_component| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component ;
|
| 736 |
|
|
; |scfifo:U1| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1 ;
|
| 737 |
|
|
; |scfifo_e4u:auto_generated| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated ;
|
| 738 |
|
|
; |a_dpfifo_lqr:dpfifo| ; 38 (2) ; 29 ; 4096 ; 0 ; 0 ; 9 (2) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo ;
|
| 739 |
|
|
; |a_fefifo_s7f:fifo_state| ; 18 (9) ; 11 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 11 (2) ; 9 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state ;
|
| 740 |
|
|
; |cntr_cc7:count_usedw| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw ;
|
| 741 |
|
|
; |cntr_ud8:rd_ptr_count| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count ;
|
| 742 |
|
|
; |cntr_ud8:wr_ptr| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr ;
|
| 743 |
|
|
; |dpram_4cm:FIFOram| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram ;
|
| 744 |
|
|
; |altsyncram_ihc1:altsyncram1| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1 ;
|
| 745 |
|
|
; |pll50:Ipll| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|pll50:Ipll ;
|
| 746 |
|
|
; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|pll50:Ipll|altpll:altpll_component ;
|
| 747 |
|
|
+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 748 |
|
|
|
| 749 |
|
|
|
| 750 |
|
|
+--------------------------------+
|
| 751 |
|
|
; Analysis & Synthesis Equations ;
|
| 752 |
|
|
+--------------------------------+
|
| 753 |
|
|
The equations can be found in E:/mips789/mips789/quartus2/mips_top.map.eqn.
|
| 754 |
|
|
|
| 755 |
|
|
|
| 756 |
|
|
+---------------------------------------------------------------------------------------------------------------------------+
|
| 757 |
|
|
; Analysis & Synthesis Source Files Read ;
|
| 758 |
|
|
+-------------------------------------+-----------------+-------------------------------------------------------------------+
|
| 759 |
|
|
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
|
| 760 |
|
|
+-------------------------------------+-----------------+-------------------------------------------------------------------+
|
| 761 |
|
|
; ../synplify_prj/rev_1/mips_sys.vqm ; yes ; E:/mips789/mips789/synplify_prj/rev_1/mips_sys.vqm ;
|
| 762 |
|
|
; ../rtl/verilog/altera/mips_top.v ; yes ; E:/mips789/mips789/rtl/verilog/altera/mips_top.v ;
|
| 763 |
|
|
; ../rtl/verilog/altera/pll50.v ; yes ; E:/mips789/mips789/rtl/verilog/altera/pll50.v ;
|
| 764 |
|
|
; ../rtl/verilog/altera/ram2048x8_0.v ; yes ; E:/mips789/mips789/rtl/verilog/altera/ram2048x8_0.v ;
|
| 765 |
|
|
; ../rtl/verilog/altera/ram2048x8_1.v ; yes ; E:/mips789/mips789/rtl/verilog/altera/ram2048x8_1.v ;
|
| 766 |
|
|
; ../rtl/verilog/altera/ram2048x8_2.v ; yes ; E:/mips789/mips789/rtl/verilog/altera/ram2048x8_2.v ;
|
| 767 |
|
|
; ../rtl/verilog/altera/ram2048x8_3.v ; yes ; E:/mips789/mips789/rtl/verilog/altera/ram2048x8_3.v ;
|
| 768 |
|
|
; ../rtl/verilog/altera/ram_module.v ; yes ; E:/mips789/mips789/rtl/verilog/altera/ram_module.v ;
|
| 769 |
|
|
; altpll.tdf ; yes ; c:/altera/quartus42/libraries/megafunctions/altpll.tdf ;
|
| 770 |
|
|
; aglobal42.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/aglobal42.inc ;
|
| 771 |
|
|
; stratix_pll.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/stratix_pll.inc ;
|
| 772 |
|
|
; stratixii_pll.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/stratixii_pll.inc ;
|
| 773 |
|
|
; cycloneii_pll.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/cycloneii_pll.inc ;
|
| 774 |
|
|
; altsyncram.tdf ; yes ; c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf ;
|
| 775 |
|
|
; stratix_ram_block.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/stratix_ram_block.inc ;
|
| 776 |
|
|
; lpm_mux.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_mux.inc ;
|
| 777 |
|
|
; lpm_decode.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_decode.inc ;
|
| 778 |
|
|
; altsyncram.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/altsyncram.inc ;
|
| 779 |
|
|
; a_rdenreg.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/a_rdenreg.inc ;
|
| 780 |
|
|
; altrom.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/altrom.inc ;
|
| 781 |
|
|
; altram.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/altram.inc ;
|
| 782 |
|
|
; altdpram.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/altdpram.inc ;
|
| 783 |
|
|
; altqpram.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/altqpram.inc ;
|
| 784 |
|
|
; db/altsyncram_hht1.tdf ; yes ; E:/mips789/mips789/quartus2/db/altsyncram_hht1.tdf ;
|
| 785 |
|
|
; db/altsyncram_ght1.tdf ; yes ; E:/mips789/mips789/quartus2/db/altsyncram_ght1.tdf ;
|
| 786 |
|
|
; db/altsyncram_fht1.tdf ; yes ; E:/mips789/mips789/quartus2/db/altsyncram_fht1.tdf ;
|
| 787 |
|
|
; db/altsyncram_eht1.tdf ; yes ; E:/mips789/mips789/quartus2/db/altsyncram_eht1.tdf ;
|
| 788 |
|
|
; lpm_latch.tdf ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_latch.tdf ;
|
| 789 |
|
|
; lpm_constant.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_constant.inc ;
|
| 790 |
|
|
; db/altsyncram_3mc1.tdf ; yes ; E:/mips789/mips789/quartus2/db/altsyncram_3mc1.tdf ;
|
| 791 |
|
|
; scfifo.tdf ; yes ; c:/altera/quartus42/libraries/megafunctions/scfifo.tdf ;
|
| 792 |
|
|
; a_regfifo.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/a_regfifo.inc ;
|
| 793 |
|
|
; a_dpfifo.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/a_dpfifo.inc ;
|
| 794 |
|
|
; a_i2fifo.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/a_i2fifo.inc ;
|
| 795 |
|
|
; a_fffifo.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/a_fffifo.inc ;
|
| 796 |
|
|
; a_f2fifo.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/a_f2fifo.inc ;
|
| 797 |
|
|
; db/scfifo_e4u.tdf ; yes ; E:/mips789/mips789/quartus2/db/scfifo_e4u.tdf ;
|
| 798 |
|
|
; db/a_dpfifo_lqr.tdf ; yes ; E:/mips789/mips789/quartus2/db/a_dpfifo_lqr.tdf ;
|
| 799 |
|
|
; db/a_fefifo_s7f.tdf ; yes ; E:/mips789/mips789/quartus2/db/a_fefifo_s7f.tdf ;
|
| 800 |
|
|
; db/cntr_cc7.tdf ; yes ; E:/mips789/mips789/quartus2/db/cntr_cc7.tdf ;
|
| 801 |
|
|
; db/dpram_4cm.tdf ; yes ; E:/mips789/mips789/quartus2/db/dpram_4cm.tdf ;
|
| 802 |
|
|
; db/altsyncram_ihc1.tdf ; yes ; E:/mips789/mips789/quartus2/db/altsyncram_ihc1.tdf ;
|
| 803 |
|
|
; db/cntr_ud8.tdf ; yes ; E:/mips789/mips789/quartus2/db/cntr_ud8.tdf ;
|
| 804 |
|
|
+-------------------------------------+-----------------+-------------------------------------------------------------------+
|
| 805 |
|
|
|
| 806 |
|
|
|
| 807 |
|
|
+------------------------------------------------------------------------------+
|
| 808 |
|
|
; Analysis & Synthesis Resource Usage Summary ;
|
| 809 |
|
|
+-----------------------------------+------------------------------------------+
|
| 810 |
|
|
; Resource ; Usage ;
|
| 811 |
|
|
+-----------------------------------+------------------------------------------+
|
| 812 |
|
|
; Logic cells ; 3,649 ;
|
| 813 |
|
|
; Total combinational functions ; 3361 ;
|
| 814 |
|
|
; Total 4-input functions ; 1697 ;
|
| 815 |
|
|
; Total 3-input functions ; 885 ;
|
| 816 |
|
|
; Total 2-input functions ; 699 ;
|
| 817 |
|
|
; Total 1-input functions ; 78 ;
|
| 818 |
|
|
; Total 0-input functions ; 2 ;
|
| 819 |
|
|
; Combinational cells for routing ; 0 ;
|
| 820 |
|
|
; Total registers ; 863 ;
|
| 821 |
|
|
; Total logic cells in carry chains ; 460 ;
|
| 822 |
|
|
; I/O pins ; 33 ;
|
| 823 |
|
|
; Total memory bits ; 71680 ;
|
| 824 |
|
|
; Total PLLs ; 1 ;
|
| 825 |
|
|
; Maximum fan-out node ; pll50:Ipll|altpll:altpll_component|_clk0 ;
|
| 826 |
|
|
; Maximum fan-out ; 967 ;
|
| 827 |
|
|
; Total fan-out ; 15034 ;
|
| 828 |
|
|
; Average fan-out ; 3.97 ;
|
| 829 |
|
|
+-----------------------------------+------------------------------------------+
|
| 830 |
|
|
|
| 831 |
|
|
|
| 832 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 833 |
|
|
; Analysis & Synthesis RAM Summary ;
|
| 834 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------+
|
| 835 |
|
|
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
|
| 836 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------+
|
| 837 |
|
|
; mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; 16384 ; qu2_ram0.mif ;
|
| 838 |
|
|
; mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; 16384 ; qu2_ram1.mif ;
|
| 839 |
|
|
; mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; 16384 ; qu2_ram2.mif ;
|
| 840 |
|
|
; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; 16384 ; qu2_ram3.mif ;
|
| 841 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; None ;
|
| 842 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; None ;
|
| 843 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 8 ; 512 ; 8 ; 4096 ; None ;
|
| 844 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------+
|
| 845 |
|
|
|
| 846 |
|
|
|
| 847 |
|
|
+-------------------------------+
|
| 848 |
|
|
; Analysis & Synthesis Messages ;
|
| 849 |
|
|
+-------------------------------+
|
| 850 |
|
|
Info: *******************************************************************
|
| 851 |
|
|
Info: Running Quartus II Analysis & Synthesis
|
| 852 |
|
|
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
|
| 853 |
|
|
Info: Processing started: Mon Oct 13 11:58:03 2008
|
| 854 |
|
|
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off mips_top -c mips_top
|
| 855 |
|
|
Info: Found 83 design units, including 83 entities, in source file ../synplify_prj/rev_1/mips_sys.vqm
|
| 856 |
|
|
Info: Found entity 1: infile_dmem_ctl_reg
|
| 857 |
|
|
Info: Found entity 2: SYNLPM_LATRS1
|
| 858 |
|
|
Info: Found entity 3: mem_addr_ctl
|
| 859 |
|
|
Info: Found entity 4: mem_din_ctl
|
| 860 |
|
|
Info: Found entity 5: SYNLPM_LATR1
|
| 861 |
|
|
Info: Found entity 6: mem_dout_ctl
|
| 862 |
|
|
Info: Found entity 7: mem_module
|
| 863 |
|
|
Info: Found entity 8: SYNLPM_LATS1
|
| 864 |
|
|
Info: Found entity 9: ctl_FSM
|
| 865 |
|
|
Info: Found entity 10: pc_gen
|
| 866 |
|
|
Info: Found entity 11: compare
|
| 867 |
|
|
Info: Found entity 12: ext
|
| 868 |
|
|
Info: Found entity 13: r32_reg_clr_cls
|
| 869 |
|
|
Info: Found entity 14: reg_array
|
| 870 |
|
|
Info: Found entity 15: fwd_mux
|
| 871 |
|
|
Info: Found entity 16: fwd_mux_1
|
| 872 |
|
|
Info: Found entity 17: rf_stage
|
| 873 |
|
|
Info: Found entity 18: muldiv_ff
|
| 874 |
|
|
Info: Found entity 19: alu
|
| 875 |
|
|
Info: Found entity 20: shifter_tak
|
| 876 |
|
|
Info: Found entity 21: big_alu
|
| 877 |
|
|
Info: Found entity 22: fwd_mux_2
|
| 878 |
|
|
Info: Found entity 23: alu_muxa
|
| 879 |
|
|
Info: Found entity 24: alu_muxb
|
| 880 |
|
|
Info: Found entity 25: r32_reg
|
| 881 |
|
|
Info: Found entity 26: r32_reg_cls
|
| 882 |
|
|
Info: Found entity 27: exec_stage
|
| 883 |
|
|
Info: Found entity 28: r32_reg_1
|
| 884 |
|
|
Info: Found entity 29: r32_reg_2
|
| 885 |
|
|
Info: Found entity 30: r32_reg_3
|
| 886 |
|
|
Info: Found entity 31: r32_reg_4
|
| 887 |
|
|
Info: Found entity 32: decoder
|
| 888 |
|
|
Info: Found entity 33: muxb_ctl_reg_clr_cls
|
| 889 |
|
|
Info: Found entity 34: wb_mux_ctl_reg_clr_cls
|
| 890 |
|
|
Info: Found entity 35: wb_we_reg_clr_cls
|
| 891 |
|
|
Info: Found entity 36: wb_we_reg
|
| 892 |
|
|
Info: Found entity 37: wb_mux_ctl_reg_clr
|
| 893 |
|
|
Info: Found entity 38: muxb_ctl_reg_clr
|
| 894 |
|
|
Info: Found entity 39: dmem_ctl_reg_clr
|
| 895 |
|
|
Info: Found entity 40: alu_func_reg_clr
|
| 896 |
|
|
Info: Found entity 41: muxa_ctl_reg_clr
|
| 897 |
|
|
Info: Found entity 42: wb_mux_ctl_reg
|
| 898 |
|
|
Info: Found entity 43: wb_we_reg_clr
|
| 899 |
|
|
Info: Found entity 44: cmp_ctl_reg_clr_cls
|
| 900 |
|
|
Info: Found entity 45: wb_we_reg_1
|
| 901 |
|
|
Info: Found entity 46: wb_mux_ctl_reg_1
|
| 902 |
|
|
Info: Found entity 47: wb_we_reg_2
|
| 903 |
|
|
Info: Found entity 48: alu_we_reg_clr
|
| 904 |
|
|
Info: Found entity 49: alu_func_reg_clr_cls
|
| 905 |
|
|
Info: Found entity 50: dmem_ctl_reg_clr_cls
|
| 906 |
|
|
Info: Found entity 51: ext_ctl_reg_clr_cls
|
| 907 |
|
|
Info: Found entity 52: rd_sel_reg_clr_cls
|
| 908 |
|
|
Info: Found entity 53: alu_we_reg_clr_cls
|
| 909 |
|
|
Info: Found entity 54: muxa_ctl_reg_clr_cls
|
| 910 |
|
|
Info: Found entity 55: pc_gen_ctl_reg_clr_cls
|
| 911 |
|
|
Info: Found entity 56: dmem_ctl_reg
|
| 912 |
|
|
Info: Found entity 57: pipelinedregs
|
| 913 |
|
|
Info: Found entity 58: decode_pipe
|
| 914 |
|
|
Info: Found entity 59: r32_reg_5
|
| 915 |
|
|
Info: Found entity 60: forward_node_fw_alu_rs
|
| 916 |
|
|
Info: Found entity 61: forward_node_fw_alu_rs_1
|
| 917 |
|
|
Info: Found entity 62: forward_node_fw_alu_rs_2
|
| 918 |
|
|
Info: Found entity 63: forward_node_fw_alu_rs_3
|
| 919 |
|
|
Info: Found entity 64: fw_latch5
|
| 920 |
|
|
Info: Found entity 65: fw_latch5_1
|
| 921 |
|
|
Info: Found entity 66: forward
|
| 922 |
|
|
Info: Found entity 67: r32_reg_6
|
| 923 |
|
|
Info: Found entity 68: r5_reg
|
| 924 |
|
|
Info: Found entity 69: r5_reg_1
|
| 925 |
|
|
Info: Found entity 70: r5_reg_2
|
| 926 |
|
|
Info: Found entity 71: r32_reg_7
|
| 927 |
|
|
Info: Found entity 72: r32_reg_8
|
| 928 |
|
|
Info: Found entity 73: mips_core
|
| 929 |
|
|
Info: Found entity 74: uart_read
|
| 930 |
|
|
Info: Found entity 75: rxd_d
|
| 931 |
|
|
Info: Found entity 76: scfifo_Z1
|
| 932 |
|
|
Info: Found entity 77: fifo512_cyclone
|
| 933 |
|
|
Info: Found entity 78: uart_write
|
| 934 |
|
|
Info: Found entity 79: uart0
|
| 935 |
|
|
Info: Found entity 80: seg7led_cv
|
| 936 |
|
|
Info: Found entity 81: tmr0
|
| 937 |
|
|
Info: Found entity 82: mips_dvc
|
| 938 |
|
|
Info: Found entity 83: mips_sys
|
| 939 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/mips_top.v
|
| 940 |
|
|
Info: Found entity 1: mips_top
|
| 941 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll25.v
|
| 942 |
|
|
Info: Found entity 1: pll25
|
| 943 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll40.v
|
| 944 |
|
|
Info: Found entity 1: pll40
|
| 945 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll45.v
|
| 946 |
|
|
Info: Found entity 1: pll45
|
| 947 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll50.v
|
| 948 |
|
|
Info: Found entity 1: pll50
|
| 949 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/pll75.v
|
| 950 |
|
|
Info: Found entity 1: pll75
|
| 951 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram2048x8_0.v
|
| 952 |
|
|
Info: Found entity 1: ram2048x8_0
|
| 953 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram2048x8_1.v
|
| 954 |
|
|
Info: Found entity 1: ram2048x8_1
|
| 955 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram2048x8_2.v
|
| 956 |
|
|
Info: Found entity 1: ram2048x8_2
|
| 957 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram2048x8_3.v
|
| 958 |
|
|
Info: Found entity 1: ram2048x8_3
|
| 959 |
|
|
Info: Found 1 design units, including 1 entities, in source file ../rtl/verilog/altera/ram_module.v
|
| 960 |
|
|
Info: Found entity 1: mem_array
|
| 961 |
|
|
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altpll.tdf
|
| 962 |
|
|
Info: Found entity 1: altpll
|
| 963 |
|
|
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf
|
| 964 |
|
|
Info: Found entity 1: altsyncram
|
| 965 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hht1.tdf
|
| 966 |
|
|
Info: Found entity 1: altsyncram_hht1
|
| 967 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ght1.tdf
|
| 968 |
|
|
Info: Found entity 1: altsyncram_ght1
|
| 969 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fht1.tdf
|
| 970 |
|
|
Info: Found entity 1: altsyncram_fht1
|
| 971 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_eht1.tdf
|
| 972 |
|
|
Info: Found entity 1: altsyncram_eht1
|
| 973 |
|
|
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_latch.tdf
|
| 974 |
|
|
Info: Found entity 1: lpm_latch
|
| 975 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3mc1.tdf
|
| 976 |
|
|
Info: Found entity 1: altsyncram_3mc1
|
| 977 |
|
|
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/scfifo.tdf
|
| 978 |
|
|
Info: Found entity 1: scfifo
|
| 979 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/scfifo_e4u.tdf
|
| 980 |
|
|
Info: Found entity 1: scfifo_e4u
|
| 981 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_lqr.tdf
|
| 982 |
|
|
Info: Found entity 1: a_dpfifo_lqr
|
| 983 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_s7f.tdf
|
| 984 |
|
|
Info: Found entity 1: a_fefifo_s7f
|
| 985 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/cntr_cc7.tdf
|
| 986 |
|
|
Info: Found entity 1: cntr_cc7
|
| 987 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/dpram_4cm.tdf
|
| 988 |
|
|
Info: Found entity 1: dpram_4cm
|
| 989 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ihc1.tdf
|
| 990 |
|
|
Info: Found entity 1: altsyncram_ihc1
|
| 991 |
|
|
Info: Found 1 design units, including 1 entities, in source file db/cntr_ud8.tdf
|
| 992 |
|
|
Info: Found entity 1: cntr_ud8
|
| 993 |
|
|
Info: WYSIWYG I/O primitives converted to equivalent logic
|
| 994 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|clk_in" converted to equivalent logic
|
| 995 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|rst_in" converted to equivalent logic
|
| 996 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_7_" converted to equivalent logic
|
| 997 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_20_" converted to equivalent logic
|
| 998 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_22_" converted to equivalent logic
|
| 999 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_21_" converted to equivalent logic
|
| 1000 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_20_" converted to equivalent logic
|
| 1001 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_19_" converted to equivalent logic
|
| 1002 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_18_" converted to equivalent logic
|
| 1003 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_17_" converted to equivalent logic
|
| 1004 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_16_" converted to equivalent logic
|
| 1005 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_23_" converted to equivalent logic
|
| 1006 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_16_" converted to equivalent logic
|
| 1007 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_17_" converted to equivalent logic
|
| 1008 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_18_" converted to equivalent logic
|
| 1009 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_19_" converted to equivalent logic
|
| 1010 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_6_" converted to equivalent logic
|
| 1011 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_14_" converted to equivalent logic
|
| 1012 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_30_" converted to equivalent logic
|
| 1013 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_5_" converted to equivalent logic
|
| 1014 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_13_" converted to equivalent logic
|
| 1015 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_29_" converted to equivalent logic
|
| 1016 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_4_" converted to equivalent logic
|
| 1017 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_28_" converted to equivalent logic
|
| 1018 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_12_" converted to equivalent logic
|
| 1019 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_3_" converted to equivalent logic
|
| 1020 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_11_" converted to equivalent logic
|
| 1021 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_27_" converted to equivalent logic
|
| 1022 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_2_" converted to equivalent logic
|
| 1023 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_26_" converted to equivalent logic
|
| 1024 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_10_" converted to equivalent logic
|
| 1025 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_1_" converted to equivalent logic
|
| 1026 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_25_" converted to equivalent logic
|
| 1027 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_9_" converted to equivalent logic
|
| 1028 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_0_" converted to equivalent logic
|
| 1029 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_8_" converted to equivalent logic
|
| 1030 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_24_" converted to equivalent logic
|
| 1031 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_wr_en_o[0]" converted to equivalent logic
|
| 1032 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[2]" converted to equivalent logic
|
| 1033 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[3]" converted to equivalent logic
|
| 1034 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[4]" converted to equivalent logic
|
| 1035 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[5]" converted to equivalent logic
|
| 1036 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[6]" converted to equivalent logic
|
| 1037 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[7]" converted to equivalent logic
|
| 1038 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[8]" converted to equivalent logic
|
| 1039 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[9]" converted to equivalent logic
|
| 1040 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[10]" converted to equivalent logic
|
| 1041 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[11]" converted to equivalent logic
|
| 1042 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_pc_o[12]" converted to equivalent logic
|
| 1043 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[7]" converted to equivalent logic
|
| 1044 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[2]" converted to equivalent logic
|
| 1045 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[3]" converted to equivalent logic
|
| 1046 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[4]" converted to equivalent logic
|
| 1047 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[5]" converted to equivalent logic
|
| 1048 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[6]" converted to equivalent logic
|
| 1049 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[7]" converted to equivalent logic
|
| 1050 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[8]" converted to equivalent logic
|
| 1051 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[9]" converted to equivalent logic
|
| 1052 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[10]" converted to equivalent logic
|
| 1053 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[11]" converted to equivalent logic
|
| 1054 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_addr_o[12]" converted to equivalent logic
|
| 1055 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_15_" converted to equivalent logic
|
| 1056 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_din_in_31_" converted to equivalent logic
|
| 1057 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_15_" converted to equivalent logic
|
| 1058 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_14_" converted to equivalent logic
|
| 1059 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_13_" converted to equivalent logic
|
| 1060 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_12_" converted to equivalent logic
|
| 1061 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_11_" converted to equivalent logic
|
| 1062 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_wr_en_o[2]" converted to equivalent logic
|
| 1063 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[20]" converted to equivalent logic
|
| 1064 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_30_" converted to equivalent logic
|
| 1065 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_31_" converted to equivalent logic
|
| 1066 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_2_" converted to equivalent logic
|
| 1067 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_3_" converted to equivalent logic
|
| 1068 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_5_" converted to equivalent logic
|
| 1069 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_26_" converted to equivalent logic
|
| 1070 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_28_" converted to equivalent logic
|
| 1071 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_29_" converted to equivalent logic
|
| 1072 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_27_" converted to equivalent logic
|
| 1073 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[22]" converted to equivalent logic
|
| 1074 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[21]" converted to equivalent logic
|
| 1075 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[19]" converted to equivalent logic
|
| 1076 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[18]" converted to equivalent logic
|
| 1077 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[17]" converted to equivalent logic
|
| 1078 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[16]" converted to equivalent logic
|
| 1079 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[23]" converted to equivalent logic
|
| 1080 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_0_" converted to equivalent logic
|
| 1081 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_7_" converted to equivalent logic
|
| 1082 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_1_" converted to equivalent logic
|
| 1083 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_6_" converted to equivalent logic
|
| 1084 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_23_" converted to equivalent logic
|
| 1085 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_4_" converted to equivalent logic
|
| 1086 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_10_" converted to equivalent logic
|
| 1087 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[6]" converted to equivalent logic
|
| 1088 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_wr_en_o[1]" converted to equivalent logic
|
| 1089 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[14]" converted to equivalent logic
|
| 1090 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_wr_en_o[3]" converted to equivalent logic
|
| 1091 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[30]" converted to equivalent logic
|
| 1092 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[5]" converted to equivalent logic
|
| 1093 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[13]" converted to equivalent logic
|
| 1094 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[29]" converted to equivalent logic
|
| 1095 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[4]" converted to equivalent logic
|
| 1096 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[28]" converted to equivalent logic
|
| 1097 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[12]" converted to equivalent logic
|
| 1098 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[3]" converted to equivalent logic
|
| 1099 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[11]" converted to equivalent logic
|
| 1100 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[27]" converted to equivalent logic
|
| 1101 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[2]" converted to equivalent logic
|
| 1102 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[26]" converted to equivalent logic
|
| 1103 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[10]" converted to equivalent logic
|
| 1104 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[1]" converted to equivalent logic
|
| 1105 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[25]" converted to equivalent logic
|
| 1106 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[9]" converted to equivalent logic
|
| 1107 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[0]" converted to equivalent logic
|
| 1108 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[8]" converted to equivalent logic
|
| 1109 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[24]" converted to equivalent logic
|
| 1110 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[15]" converted to equivalent logic
|
| 1111 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_dout[31]" converted to equivalent logic
|
| 1112 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_9_" converted to equivalent logic
|
| 1113 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_8_" converted to equivalent logic
|
| 1114 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_25_" converted to equivalent logic
|
| 1115 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_21_" converted to equivalent logic
|
| 1116 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_22_" converted to equivalent logic
|
| 1117 |
|
|
Info: WYSIWYG I/O primitive "mips_sys:isys|zz_ins_i_in_24_" converted to equivalent logic
|
| 1118 |
|
|
Info: Implemented 3787 device resources after synthesis - the final resource count might be different
|
| 1119 |
|
|
Info: Implemented 5 input pins
|
| 1120 |
|
|
Info: Implemented 28 output pins
|
| 1121 |
|
|
Info: Implemented 3649 logic cells
|
| 1122 |
|
|
Info: Implemented 104 RAM segments
|
| 1123 |
|
|
Info: Implemented 1 ClockLock PLLs
|
| 1124 |
|
|
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
|
| 1125 |
|
|
Info: Processing ended: Mon Oct 13 11:59:16 2008
|
| 1126 |
|
|
Info: Elapsed time: 00:01:13
|
| 1127 |
|
|
|
| 1128 |
|
|
|
