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[/] [mips789/] [tags/] [arelease/] [rtl/] [verilog/] [EXEC_stage.v] - Blame information for rev 36

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/******************************************************************
 *                                                                *
 *    Author: Liwei                                               *
 *                                                                *
 *    This file is part of the "mips789" project.                 *
 *    Downloaded from:                                            *
 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
 *                                                                *
 *    If you encountered any problem, please contact me via       *
 *    Email:mcupro@opencores.org  or mcupro@163.com               *
 *                                                                *
 ******************************************************************/
 
`include "mips789_defs.v"
 
module exec_stage
    (
        clk,rst,spc_cls_i,alu_func,
        dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
        muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
        muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
        dmem_data_ur_o,zz_spc_o
    );
 
    input clk;
    wire clk;
    input rst;
    wire rst;
    input spc_cls_i;
    wire spc_cls_i;
    input [4:0] alu_func;
    wire [4:0] alu_func;
    input [2:0] dmem_fw_ctl;
    wire [2:0] dmem_fw_ctl;
    input [31:0] ext_i;
    wire [31:0] ext_i;
    input [31:0] fw_alu;
    wire [31:0] fw_alu;
    input [31:0] fw_dmem;
    wire [31:0] fw_dmem;
    input [1:0] muxa_ctl_i;
    wire [1:0] muxa_ctl_i;
    input [2:0] muxa_fw_ctl;
    wire [2:0] muxa_fw_ctl;
    input [1:0] muxb_ctl_i;
    wire [1:0] muxb_ctl_i;
    input [2:0] muxb_fw_ctl;
    wire [2:0] muxb_fw_ctl;
    input [31:0] pc_i;
    wire [31:0] pc_i;
    input [31:0] rs_i;
    wire [31:0] rs_i;
    input [31:0] rt_i;
    wire [31:0] rt_i;
    output [31:0] alu_ur_o;
    wire [31:0] alu_ur_o;
    output [31:0] dmem_data_ur_o;
    wire [31:0] dmem_data_ur_o;
    output [31:0] zz_spc_o;
    wire [31:0] zz_spc_o;
 
    wire [31:0] BUS2332;
    wire [31:0] BUS2446;
    wire [31:0] BUS468;
    wire [31:0] BUS476;
 
 
    big_alu MIPS_alu
            (
                .a(BUS476),
                .b(BUS468),
                .c(alu_ur_o),
                .clk(clk),
                .ctl(alu_func),
                .rst(rst)
            );
 
    add32 add4
          (
              .d_i(pc_i),
              .d_o(BUS2446)
          );
 
 
    fwd_mux dmem_fw_mux
            (
                .dout(dmem_data_ur_o),
                .fw_alu(fw_alu),
                .fw_ctl(dmem_fw_ctl),
                .fw_dmem(fw_dmem),
                .din(rt_i)
            );
 
 
 
    alu_muxa i_alu_muxa
             (
                 .a_o(BUS476),
                 .ctl(muxa_ctl_i),
                 .ext(ext_i),
                 .fw_alu(fw_alu),
                 .fw_ctl(muxa_fw_ctl),
                 .fw_mem(fw_dmem),
                 .pc(BUS2332),
                 .rs(rs_i),
                 .spc(zz_spc_o)
             );
 
 
 
    alu_muxb i_alu_muxb
             (
                 .b_o(BUS468),
                 .ctl(muxb_ctl_i),
                 .ext(ext_i),
                 .fw_alu(fw_alu),
                 .fw_ctl(muxb_fw_ctl),
                 .fw_mem(fw_dmem),
                 .rt(rt_i)
             );
 
 
 
    r32_reg pc_nxt
            (
                .clk(clk),
                .r32_i(BUS2446),
                .r32_o(BUS2332)
            );
 
 
 
    r32_reg_cls spc
                (
                    .clk(clk),
                    .cls(spc_cls_i),
                    .r32_i(pc_i),
                    .r32_o(zz_spc_o)
                );
 
endmodule
 
module big_alu(clk,rst,a,b,c,ctl);
    input  clk,rst ;
    input  [31:0] a,b ;
    output [31:0] c ;
    input  [4:0]ctl ;
 
    wire [31:0] mul_div_c;
    wire [31:0] alu_c;
    wire [31:0] shift_c;
 
    assign c =mul_div_c | alu_c | shift_c ;//save the pc to register
 
    muldiv_ff muldiv_ff(
                  .clk_i(clk),
                  .rst_i(rst),//sys signal
                  .op_type(ctl),
                  .op1(a),
                  .op2(b),
                  //    .busy_o(busy),
                  .res(mul_div_c)
              );
 
    /*
    muldiv mips_muldiv(
               .ready(busy),
               .rst(rst),
               .op1(a),
               .op2(b),
               .clk(clk),
               .dout(mul_div_c),
               .func(ctl)
           );
    */
    alu mips_alu(
            .a(a),
            .b(b),
            .alu_out(alu_c),
            .alu_func(ctl)
 
        );
 
    shifter_tak mips_shifter(
                    .a(b),
                    .shift_out(shift_c),
                    .shift_func(ctl),
                    .shift_amount(a)
                );
 
endmodule
 
module alu_muxa(
        input [31:0]spc,
        input [31:0]pc,
        input [31:0]fw_mem,
        input [31:0]rs,
        input [31:0]fw_alu,
        input [31:0]ext,
        input [1:0] ctl,
        input [2:0] fw_ctl,
        output reg [31:0]a_o
    );
 
    always @(*)
    begin
        case (ctl)
            `MUXA_RS:   a_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rs;
            `MUXA_PC:   a_o = pc;
            `MUXA_EXT:  a_o = ext;
            `MUXA_SPC:  a_o = spc;
            default :   a_o = rs;
        endcase
    end
endmodule
 
module alu_muxb(
        input [31:0] rt,
        input [31:0]fw_alu,
        input [31:0]fw_mem,
        input [31:0]ext ,
        input [1:0]ctl ,
        input [2:0]fw_ctl ,
        output reg [31:0] b_o
    );
    always@(*)
    case (ctl)
        `MUXB_RT :b_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
        `MUXB_EXT :     b_o=ext;
        default b_o=rt;
    endcase
endmodule
 
 
 
//This file is based on YACC ->alu.v and  UCORE ->alu.v
 
module alu (a,b,alu_out,alu_func);
 
    input [31:0] a,b;
    output reg [31:0] alu_out;
    input [4:0]  alu_func;
    reg [32:0] sum;
 
    always @(*)
    begin
        case (alu_func)
 
            `ALU_PA     : alu_out=a;
            `ALU_PB     : alu_out=b;
            `ALU_ADD    : alu_out=a+b;
            `ALU_SUB  ,
            `ALU_SUBU   : alu_out=a + (~b)+1;
            `ALU_OR     : alu_out=a | b;
            `ALU_AND    : alu_out=a & b;
            `ALU_XOR    : alu_out=a ^ b;
            `ALU_NOR    : alu_out=~(a | b);
            `ALU_SLTU   : alu_out=(a < b)?1:0;
            `ALU_SLT :
            begin
                sum={a[31],a}+~{b[31],b}+33'h0_0000_0001;
                alu_out={31'h0000_0000,sum[32]};
            end
            default : alu_out=32'h0;
        endcase
    end
endmodule
 
module
    shifter_tak(
            input [31:0] a,
            output reg [31:0] shift_out,
            input [4:0] shift_func,//connect to alu_func_ctl
            input [31:0] shift_amount//connect to b
        );
 
    always @ (*)
    begin
        if( shift_func == `ALU_SLL  )
        begin
            case ( shift_amount[4:0] )
                5'b00000: shift_out=a;
                5'b00001: shift_out={a[30:0],1'b0};
                5'b00010: shift_out={a[29:0],2'b0};
                5'b00011: shift_out={a[28:0],3'b0};
                5'b00100: shift_out={a[27:0],4'b0};
                5'b00101: shift_out={a[26:0],5'b0};
                5'b00110: shift_out={a[25:0],6'b0};
                5'b00111: shift_out={a[24:0],7'b0};
                5'b01000: shift_out={a[23:0],8'b0};
                5'b01001: shift_out={a[22:0],9'b0};
                5'b01010: shift_out={a[21:0],10'b0};
                5'b01011: shift_out={a[20:0],11'b0};
                5'b01100: shift_out={a[19:0],12'b0};
                5'b01101: shift_out={a[18:0],13'b0};
                5'b01110: shift_out={a[17:0],14'b0};
                5'b01111: shift_out={a[16:0],15'b0};
                5'b10000: shift_out={a[15:0],16'b0};
                5'b10001: shift_out={a[14:0],17'b0};
                5'b10010: shift_out={a[13:0],18'b0};
                5'b10011: shift_out={a[12:0],19'b0};
                5'b10100: shift_out={a[11:0],20'b0};
                5'b10101: shift_out={a[10:0],21'b0};
                5'b10110: shift_out={a[9:0],22'b0};
                5'b10111: shift_out={a[8:0],23'b0};
                5'b11000: shift_out={a[7:0],24'b0};
                5'b11001: shift_out={a[6:0],25'b0};
                5'b11010: shift_out={a[5:0],26'b0};
                5'b11011: shift_out={a[4:0],27'b0};
                5'b11100: shift_out={a[3:0],28'b0};
                5'b11101: shift_out={a[2:0],29'b0};
                5'b11110: shift_out={a[1:0],30'b0};
                5'b11111: shift_out={a[0],31'b0};
                default shift_out ='d0;
            endcase
        end else if (shift_func== `ALU_SRL) begin
            case (shift_amount[4:0])
                5'b00000: shift_out=a;
                5'b00001: shift_out={1'b0,a[31:1]};
                5'b00010: shift_out={2'b0,a[31:2]};
                5'b00011: shift_out={3'b0,a[31:3]};
                5'b00100: shift_out={4'b0,a[31:4]};
                5'b00101: shift_out={5'b0,a[31:5]};
                5'b00110: shift_out={6'b0,a[31:6]};
                5'b00111: shift_out={7'b0,a[31:7]};
                5'b01000: shift_out={8'b0,a[31:8]};
                5'b01001: shift_out={9'b0,a[31:9]};
                5'b01010: shift_out={10'b0,a[31:10]};
                5'b01011: shift_out={11'b0,a[31:11]};
                5'b01100: shift_out={12'b0,a[31:12]};
                5'b01101: shift_out={13'b0,a[31:13]};
                5'b01110: shift_out={14'b0,a[31:14]};
                5'b01111: shift_out={15'b0,a[31:15]};
                5'b10000: shift_out={16'b0,a[31:16]};
                5'b10001: shift_out={17'b0,a[31:17]};
                5'b10010: shift_out={18'b0,a[31:18]};
                5'b10011: shift_out={19'b0,a[31:19]};
                5'b10100: shift_out={20'b0,a[31:20]};
                5'b10101: shift_out={21'b0,a[31:21]};
                5'b10110: shift_out={22'b0,a[31:22]};
                5'b10111: shift_out={23'b0,a[31:23]};
                5'b11000: shift_out={24'b0,a[31:24]};
                5'b11001: shift_out={25'b0,a[31:25]};
                5'b11010: shift_out={26'b0,a[31:26]};
                5'b11011: shift_out={27'b0,a[31:27]};
                5'b11100: shift_out={28'b0,a[31:28]};
                5'b11101: shift_out={29'b0,a[31:29]};
                5'b11110: shift_out={30'b0,a[31:30]};
                5'b11111: shift_out={31'b0,a[31:31]};
                default : shift_out = 0;
            endcase
        end else
            if (shift_func==`ALU_SRA)
            begin// SHIFT_RIGHT_SIGNED
                case ( shift_amount[4:0])
                    5'b00000: shift_out=a;
                    5'b00001: shift_out={a[31],a[31:1]};
                    5'b00010: shift_out={{2{a[31]}},a[31:2]};
                    5'b00011: shift_out={{3{a[31]}},a[31:3]};
                    5'b00100: shift_out={{4{a[31]}},a[31:4]};
                    5'b00101: shift_out={{5{a[31]}},a[31:5]};
                    5'b00110: shift_out={{6{a[31]}},a[31:6]};
                    5'b00111: shift_out={{7{a[31]}},a[31:7]};
                    5'b01000: shift_out={{8{a[31]}},a[31:8]};
                    5'b01001: shift_out={{9{a[31]}},a[31:9]};
                    5'b01010: shift_out={{10{a[31]}},a[31:10]};
                    5'b01011: shift_out={{11{a[31]}},a[31:11]};
                    5'b01100: shift_out={{12{a[31]}},a[31:12]};
                    5'b01101: shift_out={{13{a[31]}},a[31:13]};
                    5'b01110: shift_out={{14{a[31]}},a[31:14]};
                    5'b01111: shift_out={{15{a[31]}},a[31:15]};
                    5'b10000: shift_out={{16{a[31]}},a[31:16]};
                    5'b10001: shift_out={{17{a[31]}},a[31:17]};
                    5'b10010: shift_out={{18{a[31]}},a[31:18]};
                    5'b10011: shift_out={{19{a[31]}},a[31:19]};
                    5'b10100: shift_out={{20{a[31]}},a[31:20]};
                    5'b10101: shift_out={{21{a[31]}},a[31:21]};
                    5'b10110: shift_out={{22{a[31]}},a[31:22]};
                    5'b10111: shift_out={{23{a[31]}},a[31:23]};
                    5'b11000: shift_out={{24{a[31]}},a[31:24]};
                    5'b11001: shift_out={{25{a[31]}},a[31:25]};
                    5'b11010: shift_out={{26{a[31]}},a[31:26]};
                    5'b11011: shift_out={{27{a[31]}},a[31:27]};
                    5'b11100: shift_out={{28{a[31]}},a[31:28]};
                    5'b11101: shift_out={{29{a[31]}},a[31:29]};
                    5'b11110: shift_out={{30{a[31]}},a[31:30]};
                    5'b11111: shift_out={{31{a[31]}},a[31:31]};
                    default shift_out='d0;
                endcase
            end
            else                         shift_out='d0;
    end
endmodule
 
module muldiv(ready,rst,op1,op2,clk,dout,func);
    input         clk,rst;
    wire       sign;
    input [4:0] func ;
    input [31:0] op2, op1;
    output [31:0] dout;
    output        ready;
    reg [31:0]    quotient, quotient_temp;
    reg [63:0]    dividend_copy, divider_copy, diff;
    reg           negative_output;
 
    reg [63:0]    product, product_temp;
 
    reg [31:0]    multiplier_copy;
    reg [63:0]    multiplicand_copy;
 
    reg [6:0]     mul_bit,div_bit;
    wire          ready = ((mul_bit==0)&&(div_bit==0));
 
    wire  [31:0]  dividend, divider;
 
    wire [31:0]  remainder;
    wire [31:0] multiplier,multiplicand;
 
    reg [31:0] hi,lo;
 
    assign dout = (func==`ALU_MFHI)?hi:(func==`ALU_MFLO)?lo:0;
 
    assign  remainder = (!negative_output) ?
            dividend_copy[31:0] :
            ~dividend_copy[31:0] + 1'b1;
 
    assign multiplier=op2;
    assign multiplicand=op1;
    assign dividend=op1;
    assign  divider = op2;
    assign sign = ((func==`ALU_MULT)||(func==`ALU_DIV));
 
    initial
    begin
        hi=0;
        lo=0;
    end
    always @( posedge clk /*or negedge rst */)
        if (~rst)
        begin
            mul_bit=0;
            div_bit=0;
            /*
            hi=0;
            lo=0;
            */
            negative_output = 0;
        end
        else
        begin
            if((ready)&&((func==`ALU_MULT)||(func==`ALU_MULTTU)))
            begin
                mul_bit               = 33;
                product           = 0;
                product_temp      = 0;
                multiplicand_copy = (!sign || !multiplicand[31]) ?
                                  { 32'd0, multiplicand } :
                                  { 32'd0, ~multiplicand + 1'b1};
                multiplier_copy   = (!sign || !multiplier[31]) ?multiplier :~multiplier + 1'b1;
 
                negative_output = sign &&
                                ((multiplier[31] && !multiplicand[31])
                                 ||(!multiplier[31] && multiplicand[31]));
            end
            if ( mul_bit > 1 )
            begin
 
                if( multiplier_copy[0] == 1'b1 )
                    product_temp = product_temp +multiplicand_copy;
 
 
                product = (!negative_output) ?
                        product_temp :
                        ~product_temp + 1'b1;
 
                multiplier_copy = multiplier_copy >> 1;
                multiplicand_copy = multiplicand_copy << 1;
                mul_bit = mul_bit - 1'b1;
            end
            else if (mul_bit == 1)
            begin
                hi =  product[63:32];
                lo =  product[31:0];
                mul_bit=0;
            end
 
            if((ready)&&((func==`ALU_DIV)||(func==`ALU_DIVU)))
            begin
                div_bit = 33;
                quotient = 0;
                quotient_temp = 0;
                dividend_copy = (!sign || !dividend[31]) ?
                              {32'd0,dividend} :
                              {32'd0,~dividend + 1'b1};
 
                divider_copy = (!sign || !divider[31]) ?
                             {1'b0,divider,31'd0} :
                             {1'b0,~divider + 1'b1,31'd0};
 
                negative_output = sign &&
                                ((divider[31] && !dividend[31])
                                 ||(!divider[31] && dividend[31]));
            end
            else if (div_bit > 1)
            begin
                diff = dividend_copy - divider_copy;
                quotient_temp = quotient_temp << 1;
                if( !diff[63] )
                begin
                    dividend_copy = diff;
                    quotient_temp[0] = 1'd1;
                end
                quotient = (!negative_output) ?quotient_temp :~quotient_temp + 1'b1;
                divider_copy = divider_copy >> 1;
                div_bit = div_bit - 1'b1;
            end
            else if (div_bit == 1)
            begin
                lo =  quotient;
                hi =  remainder;
                div_bit=0;
            end
        end
 
endmodule
 
//creatied by Zhangfeifei
//modified by Liwei
module muldiv_ff
    (
        clk_i,rst_i,
        op_type,op1,op2,
        rdy,res
    );
 
    parameter  OP_MULT  = `ALU_MULT;
    parameter  OP_MULTU = `ALU_MULTU;
    parameter  OP_DIV   = `ALU_DIV;
    parameter  OP_DIVU  = `ALU_DIVU;
    parameter  OP_MFHI  = `ALU_MFHI;
    parameter  OP_MFLO  = `ALU_MFLO;
 
    parameter  OP_MTHI  = `ALU_MTHI;
    parameter  OP_MTLO  = `ALU_MTLO;
 
    parameter  OP_NONE  = `ALU_NOP;
 
    input         clk_i;
    input         rst_i;
    input  [4:0]  op_type;
    input  [31:0] op1;
    input  [31:0] op2;
    output [31:0] res;
    output        rdy;
 
    reg           rdy;
 
    reg    [64:0] hilo;
    reg    [32:0] op2_reged;
    reg    [5:0]  count;
    reg           op1_sign_reged;
    reg           op2_sign_reged;
    reg           sub_or_yn;
 
    wire   [32:0] nop2_reged;
    assign nop2_reged = ~op2_reged +1;
 
    reg           sign;
    reg           mul;
    reg           start;
 
    assign res = (op_type == OP_MFLO )?hilo[31:0]:((op_type == OP_MFHI))?hilo[63:32]:0;//op_type == OP_MFHI or other
 
    reg           overflow;
    reg           finish;
    reg           add1;  //if the quotient will add 1 at the end of the divide operation
    reg           addop2; //if the remainder will add op2 at the end of the divide operation
    reg           addnop2;//if the remainder will add ~op2+1 at the end of the divide operation
 
 
    always @( posedge clk_i  /*or negedge rst_i*/)
    begin
        if(~rst_i)
        begin
            count          = 6'bx;
            hilo           = 65'b0;
            op2_reged      = 33'bx;
            op1_sign_reged = 1'bx;
            op2_sign_reged = 1'bx;
            sub_or_yn      = 1'bx;
            rdy            = 1'b1;
            start          = 1'bx;
            sign           = 1'bx;
            mul            = 1'bx;
 
            finish         = 1'bx;
            add1           = 1'bx;
            addop2         = 1'bx;
            addnop2        = 1'bx;
        end
        else begin
 
            if(op_type == OP_MTHI || op_type == OP_MTLO)
            begin
                if(op_type == OP_MTHI) hilo[64:32] = {1'b0,op1};
                if(op_type == OP_MTLO) hilo[31:0]  = op1;
                rdy = 1;
            end
            else if(rdy)
            begin
                start = (op_type == OP_MULT) || (op_type == OP_MULTU) || (op_type == OP_DIV)  || (op_type == OP_DIVU);
                mul   = (op_type == OP_MULT) || (op_type == OP_MULTU);
                sign  = (op_type == OP_MULT) || (op_type == OP_DIV);
 
                if(start)
                begin:START_SECTION
                    reg [32:0] over;
 
                    op2_reged       = {sign        ?op2[31]      :1'b0 ,op2};
                    hilo            = {~mul && sign?{33{op1[31]}}:33'b0,op1};
                    count           = 6'b000000;
                    rdy             = 0;
                    op1_sign_reged  = sign?op1[31]:0;
                    op2_sign_reged  = sign?op2[31]:0;
                    sub_or_yn       = 0;
 
                    over            = ~op2_reged + {op1[31],op1};
                    overflow        = sign && ~mul ? op1_sign_reged && op2_sign_reged && ~over[32] : 0;
 
                    finish          = 0;
                end
            end
            else if(start)
            begin
                if(overflow)
                begin
                    hilo[63:0] = {hilo[31:0],32'b0};
                    rdy        = 1;
                end
                else if(!count[5])
                begin
                    if(mul)
                    begin
                        if(sign)
                        begin
                            case({hilo[0],sub_or_yn})
                                2'b10:hilo[64:32] = hilo[64:32] + nop2_reged;
                                2'b01:hilo[64:32] = hilo[64:32] + op2_reged;
                                default:;
                            endcase
                            {hilo[63:0],sub_or_yn} = hilo[64:0];
                        end
                        else begin
                            if(hilo[0]) hilo[64:32] = hilo[64:32] + op2_reged;
                            hilo      = {1'b0,hilo[64:1]};
                        end
                    end
                    else begin
                        sub_or_yn  = hilo[64]== op2_sign_reged;
                        hilo[64:1] = hilo[63:0];
 
                        hilo[64:32] = sub_or_yn ? hilo[64:32] + nop2_reged : hilo[64:32] + op2_reged;
 
                        hilo[0]    = hilo[64]== op2_sign_reged;
                    end
 
                    count        = count + 1'b1;
                end
                else begin
                    if(finish)
                    begin
                        if(add1)   hilo[31:0]  = hilo[31:0] + 1;
                        case({addop2,addnop2})
                            2'b10:   hilo[64:32] = hilo[64:32] + op2_reged;
                            2'b01:   hilo[64:32] = hilo[64:32] + nop2_reged;
                            default: ;
                        endcase
                        rdy = 1;
                    end
                    else begin
                        {add1,addop2,addnop2} = 3'b000;
                        finish                = 1;
 
                        if(~mul)
                        begin:LAST_CYCLE_DEAL_SECTION
                            reg eqz,eqop2,eqnop2;
                            eqz    = hilo[64:32] == 0;
                            eqop2  = hilo[64:32] == op2_reged;
                            eqnop2 = hilo[64:32] == nop2_reged;
                            casex({op1_sign_reged,op2_sign_reged,eqz,eqop2,eqnop2})
                                5'b101xx : {add1,addop2,addnop2} = 3'b000;
                                5'b100x1 : {add1,addop2,addnop2} = 3'b010;
                                5'b111xx : {add1,addop2,addnop2} = 3'b100;
                                5'b1101x : {add1,addop2,addnop2} = 3'b101;
                                default :
                                begin:LAST_CYCLE_DEAL_SECTION_DEFAULT
 
                                    reg op1s_eq_op2s,op1s_eq_h64;
                                    op1s_eq_op2s = op1_sign_reged == op2_sign_reged;
                                    op1s_eq_h64  = op1_sign_reged == hilo[64];
 
                                    add1 = ~op1s_eq_op2s;
                                    case({op1s_eq_op2s,op1s_eq_h64})//synthesis parallel_case
                                        2'b00:   {addop2,addnop2} = 2'b01;
                                        2'b10:   {addop2,addnop2} = 2'b10;
                                        default: {addop2,addnop2} = 2'b00;
                                    endcase
                                end
                            endcase
                        end
                    end
                end
            end
        end
    end
endmodule
 
 

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[/] [mips789/] [tags/] [arelease/] [rtl/] [verilog/] [EXEC_stage.v] - Blame information for rev 36

Line No.	Rev	Author	Line
1	35	mcupro	`/******************************************************************`
2			`* *`
3			`* Author: Liwei *`
4			`* *`
5			`* This file is part of the "mips789" project. *`
6			`* Downloaded from: *`
7			`* http://www.opencores.org/pdownloads.cgi/list/mips789 *`
8			`* *`
9			`* If you encountered any problem, please contact me via *`
10			`* Email:mcupro@opencores.org or mcupro@163.com *`
11			`* *`
12			`******************************************************************/`
13	10	mcupro
14	35	mcupro	`include "mips789_defs.v"
15
16	10	mcupro	`module exec_stage`
17			`(`
18			`clk,rst,spc_cls_i,alu_func,`
19			`dmem_fw_ctl,ext_i,fw_alu,fw_dmem,`
20			`muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,`
21			`muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,`
22			`dmem_data_ur_o,zz_spc_o`
23			`);`
24
25			`input clk;`
26			`wire clk;`
27			`input rst;`
28			`wire rst;`
29			`input spc_cls_i;`
30			`wire spc_cls_i;`
31			`input [4:0] alu_func;`
32			`wire [4:0] alu_func;`
33			`input [2:0] dmem_fw_ctl;`
34			`wire [2:0] dmem_fw_ctl;`
35			`input [31:0] ext_i;`
36			`wire [31:0] ext_i;`
37			`input [31:0] fw_alu;`
38			`wire [31:0] fw_alu;`
39			`input [31:0] fw_dmem;`
40			`wire [31:0] fw_dmem;`
41			`input [1:0] muxa_ctl_i;`
42			`wire [1:0] muxa_ctl_i;`
43			`input [2:0] muxa_fw_ctl;`
44			`wire [2:0] muxa_fw_ctl;`
45			`input [1:0] muxb_ctl_i;`
46			`wire [1:0] muxb_ctl_i;`
47			`input [2:0] muxb_fw_ctl;`
48			`wire [2:0] muxb_fw_ctl;`
49			`input [31:0] pc_i;`
50			`wire [31:0] pc_i;`
51			`input [31:0] rs_i;`
52			`wire [31:0] rs_i;`
53			`input [31:0] rt_i;`
54			`wire [31:0] rt_i;`
55			`output [31:0] alu_ur_o;`
56			`wire [31:0] alu_ur_o;`
57			`output [31:0] dmem_data_ur_o;`
58			`wire [31:0] dmem_data_ur_o;`
59			`output [31:0] zz_spc_o;`
60			`wire [31:0] zz_spc_o;`
61
62			`wire [31:0] BUS2332;`
63			`wire [31:0] BUS2446;`
64			`wire [31:0] BUS468;`
65			`wire [31:0] BUS476;`
66
67
68			`big_alu MIPS_alu`
69			`(`
70			`.a(BUS476),`
71			`.b(BUS468),`
72			`.c(alu_ur_o),`
73			`.clk(clk),`
74			`.ctl(alu_func),`
75			`.rst(rst)`
76			`);`
77
78			`add32 add4`
79			`(`
80			`.d_i(pc_i),`
81			`.d_o(BUS2446)`
82			`);`
83
84
85			`fwd_mux dmem_fw_mux`
86			`(`
87			`.dout(dmem_data_ur_o),`
88			`.fw_alu(fw_alu),`
89			`.fw_ctl(dmem_fw_ctl),`
90			`.fw_dmem(fw_dmem),`
91			`.din(rt_i)`
92			`);`
93
94
95
96			`alu_muxa i_alu_muxa`
97			`(`
98			`.a_o(BUS476),`
99			`.ctl(muxa_ctl_i),`
100			`.ext(ext_i),`
101			`.fw_alu(fw_alu),`
102			`.fw_ctl(muxa_fw_ctl),`
103			`.fw_mem(fw_dmem),`
104			`.pc(BUS2332),`
105			`.rs(rs_i),`
106			`.spc(zz_spc_o)`
107			`);`
108
109
110
111			`alu_muxb i_alu_muxb`
112			`(`
113			`.b_o(BUS468),`
114			`.ctl(muxb_ctl_i),`
115			`.ext(ext_i),`
116			`.fw_alu(fw_alu),`
117			`.fw_ctl(muxb_fw_ctl),`
118			`.fw_mem(fw_dmem),`
119			`.rt(rt_i)`
120			`);`
121
122
123
124			`r32_reg pc_nxt`
125			`(`
126			`.clk(clk),`
127			`.r32_i(BUS2446),`
128			`.r32_o(BUS2332)`
129			`);`
130
131
132
133			`r32_reg_cls spc`
134			`(`
135			`.clk(clk),`
136			`.cls(spc_cls_i),`
137			`.r32_i(pc_i),`
138			`.r32_o(zz_spc_o)`
139			`);`
140
141			`endmodule`
142
143			`module big_alu(clk,rst,a,b,c,ctl);`
144			`input clk,rst ;`
145			`input [31:0] a,b ;`
146			`output [31:0] c ;`
147			`input [4:0]ctl ;`
148
149			`wire [31:0] mul_div_c;`
150			`wire [31:0] alu_c;`
151			`wire [31:0] shift_c;`
152
153			`assign c =mul_div_c \| alu_c \| shift_c ;//save the pc to register`
154
155			`muldiv_ff muldiv_ff(`
156			`.clk_i(clk),`
157			`.rst_i(rst),//sys signal`
158			`.op_type(ctl),`
159			`.op1(a),`
160			`.op2(b),`
161			`// .busy_o(busy),`
162			`.res(mul_div_c)`
163			`);`
164
165			`/*`
166			`muldiv mips_muldiv(`
167			`.ready(busy),`
168			`.rst(rst),`
169			`.op1(a),`
170			`.op2(b),`
171			`.clk(clk),`
172			`.dout(mul_div_c),`
173			`.func(ctl)`
174			`);`
175			`*/`
176			`alu mips_alu(`
177			`.a(a),`
178			`.b(b),`
179			`.alu_out(alu_c),`
180			`.alu_func(ctl)`
181
182			`);`
183
184			`shifter_tak mips_shifter(`
185			`.a(b),`
186			`.shift_out(shift_c),`
187			`.shift_func(ctl),`
188			`.shift_amount(a)`
189			`);`
190
191			`endmodule`
192
193			`module alu_muxa(`
194			`input [31:0]spc,`
195			`input [31:0]pc,`
196			`input [31:0]fw_mem,`
197			`input [31:0]rs,`
198			`input [31:0]fw_alu,`
199			`input [31:0]ext,`
200			`input [1:0] ctl,`
201			`input [2:0] fw_ctl,`
202			`output reg [31:0]a_o`
203			`);`
204
205			`always @(*)`
206			`begin`
207			`case (ctl)`
208			`MUXA_RS: a_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rs;
209			`MUXA_PC: a_o = pc;
210			`MUXA_EXT: a_o = ext;
211			`MUXA_SPC: a_o = spc;
212			`default : a_o = rs;`
213			`endcase`
214			`end`
215			`endmodule`
216
217			`module alu_muxb(`
218			`input [31:0] rt,`
219			`input [31:0]fw_alu,`
220			`input [31:0]fw_mem,`
221			`input [31:0]ext ,`
222			`input [1:0]ctl ,`
223			`input [2:0]fw_ctl ,`
224			`output reg [31:0] b_o`
225			`);`
226			`always@(*)`
227			`case (ctl)`
228			`MUXB_RT :b_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
229			`MUXB_EXT : b_o=ext;
230			`default b_o=rt;`
231			`endcase`
232			`endmodule`
233
234
235
236			`//This file is based on YACC ->alu.v and UCORE ->alu.v`
237
238			`module alu (a,b,alu_out,alu_func);`
239
240			`input [31:0] a,b;`
241			`output reg [31:0] alu_out;`
242			`input [4:0] alu_func;`
243			`reg [32:0] sum;`
244
245			`always @(*)`
246			`begin`
247			`case (alu_func)`
248
249			`ALU_PA : alu_out=a;
250			`ALU_PB : alu_out=b;
251			`ALU_ADD : alu_out=a+b;
252			`ALU_SUB ,
253			`ALU_SUBU : alu_out=a + (~b)+1;
254			`ALU_OR : alu_out=a \| b;
255			`ALU_AND : alu_out=a & b;
256			`ALU_XOR : alu_out=a ^ b;
257			`ALU_NOR : alu_out=~(a \| b);
258			`ALU_SLTU : alu_out=(a < b)?1:0;
259			`ALU_SLT :
260			`begin`
261			`sum={a[31],a}+~{b[31],b}+33'h0_0000_0001;`
262			`alu_out={31'h0000_0000,sum[32]};`
263			`end`
264			`default : alu_out=32'h0;`
265			`endcase`
266			`end`
267			`endmodule`
268
269			`module`
270			`shifter_tak(`
271			`input [31:0] a,`
272			`output reg [31:0] shift_out,`
273			`input [4:0] shift_func,//connect to alu_func_ctl`
274			`input [31:0] shift_amount//connect to b`
275			`);`
276
277			`always @ (*)`
278			`begin`
279			if( shift_func == `ALU_SLL )
280			`begin`
281			`case ( shift_amount[4:0] )`
282			`5'b00000: shift_out=a;`
283			`5'b00001: shift_out={a[30:0],1'b0};`
284			`5'b00010: shift_out={a[29:0],2'b0};`
285			`5'b00011: shift_out={a[28:0],3'b0};`
286			`5'b00100: shift_out={a[27:0],4'b0};`
287			`5'b00101: shift_out={a[26:0],5'b0};`
288			`5'b00110: shift_out={a[25:0],6'b0};`
289			`5'b00111: shift_out={a[24:0],7'b0};`
290			`5'b01000: shift_out={a[23:0],8'b0};`
291			`5'b01001: shift_out={a[22:0],9'b0};`
292			`5'b01010: shift_out={a[21:0],10'b0};`
293			`5'b01011: shift_out={a[20:0],11'b0};`
294			`5'b01100: shift_out={a[19:0],12'b0};`
295			`5'b01101: shift_out={a[18:0],13'b0};`
296			`5'b01110: shift_out={a[17:0],14'b0};`
297			`5'b01111: shift_out={a[16:0],15'b0};`
298			`5'b10000: shift_out={a[15:0],16'b0};`
299			`5'b10001: shift_out={a[14:0],17'b0};`
300			`5'b10010: shift_out={a[13:0],18'b0};`
301			`5'b10011: shift_out={a[12:0],19'b0};`
302			`5'b10100: shift_out={a[11:0],20'b0};`
303			`5'b10101: shift_out={a[10:0],21'b0};`
304			`5'b10110: shift_out={a[9:0],22'b0};`
305			`5'b10111: shift_out={a[8:0],23'b0};`
306			`5'b11000: shift_out={a[7:0],24'b0};`
307			`5'b11001: shift_out={a[6:0],25'b0};`
308			`5'b11010: shift_out={a[5:0],26'b0};`
309			`5'b11011: shift_out={a[4:0],27'b0};`
310			`5'b11100: shift_out={a[3:0],28'b0};`
311			`5'b11101: shift_out={a[2:0],29'b0};`
312			`5'b11110: shift_out={a[1:0],30'b0};`
313			`5'b11111: shift_out={a[0],31'b0};`
314			`default shift_out ='d0;`
315			`endcase`
316			end else if (shift_func== `ALU_SRL) begin
317			`case (shift_amount[4:0])`
318			`5'b00000: shift_out=a;`
319			`5'b00001: shift_out={1'b0,a[31:1]};`
320			`5'b00010: shift_out={2'b0,a[31:2]};`
321			`5'b00011: shift_out={3'b0,a[31:3]};`
322			`5'b00100: shift_out={4'b0,a[31:4]};`
323			`5'b00101: shift_out={5'b0,a[31:5]};`
324			`5'b00110: shift_out={6'b0,a[31:6]};`
325			`5'b00111: shift_out={7'b0,a[31:7]};`
326			`5'b01000: shift_out={8'b0,a[31:8]};`
327			`5'b01001: shift_out={9'b0,a[31:9]};`
328			`5'b01010: shift_out={10'b0,a[31:10]};`
329			`5'b01011: shift_out={11'b0,a[31:11]};`
330			`5'b01100: shift_out={12'b0,a[31:12]};`
331			`5'b01101: shift_out={13'b0,a[31:13]};`
332			`5'b01110: shift_out={14'b0,a[31:14]};`
333			`5'b01111: shift_out={15'b0,a[31:15]};`
334			`5'b10000: shift_out={16'b0,a[31:16]};`
335			`5'b10001: shift_out={17'b0,a[31:17]};`
336			`5'b10010: shift_out={18'b0,a[31:18]};`
337			`5'b10011: shift_out={19'b0,a[31:19]};`
338			`5'b10100: shift_out={20'b0,a[31:20]};`
339			`5'b10101: shift_out={21'b0,a[31:21]};`
340			`5'b10110: shift_out={22'b0,a[31:22]};`
341			`5'b10111: shift_out={23'b0,a[31:23]};`
342			`5'b11000: shift_out={24'b0,a[31:24]};`
343			`5'b11001: shift_out={25'b0,a[31:25]};`
344			`5'b11010: shift_out={26'b0,a[31:26]};`
345			`5'b11011: shift_out={27'b0,a[31:27]};`
346			`5'b11100: shift_out={28'b0,a[31:28]};`
347			`5'b11101: shift_out={29'b0,a[31:29]};`
348			`5'b11110: shift_out={30'b0,a[31:30]};`
349			`5'b11111: shift_out={31'b0,a[31:31]};`
350			`default : shift_out = 0;`
351			`endcase`
352			`end else`
353			if (shift_func==`ALU_SRA)
354			`begin// SHIFT_RIGHT_SIGNED`
355			`case ( shift_amount[4:0])`
356			`5'b00000: shift_out=a;`
357			`5'b00001: shift_out={a[31],a[31:1]};`
358			`5'b00010: shift_out={{2{a[31]}},a[31:2]};`
359			`5'b00011: shift_out={{3{a[31]}},a[31:3]};`
360			`5'b00100: shift_out={{4{a[31]}},a[31:4]};`
361			`5'b00101: shift_out={{5{a[31]}},a[31:5]};`
362			`5'b00110: shift_out={{6{a[31]}},a[31:6]};`
363			`5'b00111: shift_out={{7{a[31]}},a[31:7]};`
364			`5'b01000: shift_out={{8{a[31]}},a[31:8]};`
365			`5'b01001: shift_out={{9{a[31]}},a[31:9]};`
366			`5'b01010: shift_out={{10{a[31]}},a[31:10]};`
367			`5'b01011: shift_out={{11{a[31]}},a[31:11]};`
368			`5'b01100: shift_out={{12{a[31]}},a[31:12]};`
369			`5'b01101: shift_out={{13{a[31]}},a[31:13]};`
370			`5'b01110: shift_out={{14{a[31]}},a[31:14]};`
371			`5'b01111: shift_out={{15{a[31]}},a[31:15]};`
372			`5'b10000: shift_out={{16{a[31]}},a[31:16]};`
373			`5'b10001: shift_out={{17{a[31]}},a[31:17]};`
374			`5'b10010: shift_out={{18{a[31]}},a[31:18]};`
375			`5'b10011: shift_out={{19{a[31]}},a[31:19]};`
376			`5'b10100: shift_out={{20{a[31]}},a[31:20]};`
377			`5'b10101: shift_out={{21{a[31]}},a[31:21]};`
378			`5'b10110: shift_out={{22{a[31]}},a[31:22]};`
379			`5'b10111: shift_out={{23{a[31]}},a[31:23]};`
380			`5'b11000: shift_out={{24{a[31]}},a[31:24]};`
381			`5'b11001: shift_out={{25{a[31]}},a[31:25]};`
382			`5'b11010: shift_out={{26{a[31]}},a[31:26]};`
383			`5'b11011: shift_out={{27{a[31]}},a[31:27]};`
384			`5'b11100: shift_out={{28{a[31]}},a[31:28]};`
385			`5'b11101: shift_out={{29{a[31]}},a[31:29]};`
386			`5'b11110: shift_out={{30{a[31]}},a[31:30]};`
387			`5'b11111: shift_out={{31{a[31]}},a[31:31]};`
388			`default shift_out='d0;`
389			`endcase`
390			`end`
391			`else shift_out='d0;`
392			`end`
393			`endmodule`
394
395			`module muldiv(ready,rst,op1,op2,clk,dout,func);`
396			`input clk,rst;`
397			`wire sign;`
398			`input [4:0] func ;`
399			`input [31:0] op2, op1;`
400			`output [31:0] dout;`
401			`output ready;`
402			`reg [31:0] quotient, quotient_temp;`
403			`reg [63:0] dividend_copy, divider_copy, diff;`
404			`reg negative_output;`
405
406			`reg [63:0] product, product_temp;`
407
408			`reg [31:0] multiplier_copy;`
409			`reg [63:0] multiplicand_copy;`
410
411			`reg [6:0] mul_bit,div_bit;`
412			`wire ready = ((mul_bit==0)&&(div_bit==0));`
413
414			`wire [31:0] dividend, divider;`
415
416			`wire [31:0] remainder;`
417			`wire [31:0] multiplier,multiplicand;`
418
419			`reg [31:0] hi,lo;`
420
421			assign dout = (func==`ALU_MFHI)?hi:(func==`ALU_MFLO)?lo:0;
422
423			`assign remainder = (!negative_output) ?`
424			`dividend_copy[31:0] :`
425			`~dividend_copy[31:0] + 1'b1;`
426
427			`assign multiplier=op2;`
428			`assign multiplicand=op1;`
429			`assign dividend=op1;`
430			`assign divider = op2;`
431			assign sign = ((func==`ALU_MULT)\|\|(func==`ALU_DIV));
432
433	35	mcupro	`initial`
434			`begin`
435			`hi=0;`
436			`lo=0;`
437			`end`
438	10	mcupro	`always @( posedge clk /or negedge rst /)`
439			`if (~rst)`
440			`begin`
441			`mul_bit=0;`
442			`div_bit=0;`
443	35	mcupro	`/*`
444			`hi=0;`
445			`lo=0;`
446			`*/`
447	10	mcupro	`negative_output = 0;`
448			`end`
449			`else`
450			`begin`
451			if((ready)&&((func==`ALU_MULT)\|\|(func==`ALU_MULTTU)))
452			`begin`
453			`mul_bit = 33;`
454			`product = 0;`
455			`product_temp = 0;`
456			`multiplicand_copy = (!sign \|\| !multiplicand[31]) ?`
457			`{ 32'd0, multiplicand } :`
458			`{ 32'd0, ~multiplicand + 1'b1};`
459			`multiplier_copy = (!sign \|\| !multiplier[31]) ?multiplier :~multiplier + 1'b1;`
460
461			`negative_output = sign &&`
462			`((multiplier[31] && !multiplicand[31])`
463			`\|\|(!multiplier[31] && multiplicand[31]));`
464			`end`
465			`if ( mul_bit > 1 )`
466			`begin`
467
468			`if( multiplier_copy[0] == 1'b1 )`
469			`product_temp = product_temp +multiplicand_copy;`
470
471
472			`product = (!negative_output) ?`
473			`product_temp :`
474			`~product_temp + 1'b1;`
475
476			`multiplier_copy = multiplier_copy >> 1;`
477			`multiplicand_copy = multiplicand_copy << 1;`
478			`mul_bit = mul_bit - 1'b1;`
479			`end`
480			`else if (mul_bit == 1)`
481			`begin`
482			`hi = product[63:32];`
483			`lo = product[31:0];`
484			`mul_bit=0;`
485			`end`
486
487			if((ready)&&((func==`ALU_DIV)\|\|(func==`ALU_DIVU)))
488			`begin`
489			`div_bit = 33;`
490			`quotient = 0;`
491			`quotient_temp = 0;`
492			`dividend_copy = (!sign \|\| !dividend[31]) ?`
493			`{32'd0,dividend} :`
494			`{32'd0,~dividend + 1'b1};`
495
496			`divider_copy = (!sign \|\| !divider[31]) ?`
497			`{1'b0,divider,31'd0} :`
498			`{1'b0,~divider + 1'b1,31'd0};`
499
500			`negative_output = sign &&`
501			`((divider[31] && !dividend[31])`
502			`\|\|(!divider[31] && dividend[31]));`
503			`end`
504			`else if (div_bit > 1)`
505			`begin`
506			`diff = dividend_copy - divider_copy;`
507			`quotient_temp = quotient_temp << 1;`
508			`if( !diff[63] )`
509			`begin`
510			`dividend_copy = diff;`
511			`quotient_temp[0] = 1'd1;`
512			`end`
513			`quotient = (!negative_output) ?quotient_temp :~quotient_temp + 1'b1;`
514			`divider_copy = divider_copy >> 1;`
515			`div_bit = div_bit - 1'b1;`
516			`end`
517			`else if (div_bit == 1)`
518			`begin`
519			`lo = quotient;`
520			`hi = remainder;`
521			`div_bit=0;`
522			`end`
523			`end`
524
525			`endmodule`
526
527			`//creatied by Zhangfeifei`
528	35	mcupro	`//modified by Liwei`
529	10	mcupro	`module muldiv_ff`
530			`(`
531			`clk_i,rst_i,`
532			`op_type,op1,op2,`
533			`rdy,res`
534			`);`
535
536			parameter OP_MULT = `ALU_MULT;
537			parameter OP_MULTU = `ALU_MULTU;
538			parameter OP_DIV = `ALU_DIV;
539			parameter OP_DIVU = `ALU_DIVU;
540			parameter OP_MFHI = `ALU_MFHI;
541			parameter OP_MFLO = `ALU_MFLO;
542
543			parameter OP_MTHI = `ALU_MTHI;
544			parameter OP_MTLO = `ALU_MTLO;
545
546			parameter OP_NONE = `ALU_NOP;
547
548			`input clk_i;`
549			`input rst_i;`
550			`input [4:0] op_type;`
551			`input [31:0] op1;`
552			`input [31:0] op2;`
553			`output [31:0] res;`
554			`output rdy;`
555
556			`reg rdy;`
557
558			`reg [64:0] hilo;`
559			`reg [32:0] op2_reged;`
560			`reg [5:0] count;`
561			`reg op1_sign_reged;`
562			`reg op2_sign_reged;`
563			`reg sub_or_yn;`
564
565			`wire [32:0] nop2_reged;`
566			`assign nop2_reged = ~op2_reged +1;`
567
568			`reg sign;`
569			`reg mul;`
570			`reg start;`
571
572			`assign res = (op_type == OP_MFLO )?hilo[31:0]:((op_type == OP_MFHI))?hilo[63:32]:0;//op_type == OP_MFHI or other`
573
574			`reg overflow;`
575			`reg finish;`
576			`reg add1; //if the quotient will add 1 at the end of the divide operation`
577			`reg addop2; //if the remainder will add op2 at the end of the divide operation`
578			`reg addnop2;//if the remainder will add ~op2+1 at the end of the divide operation`
579
580	35	mcupro
581	10	mcupro	`always @( posedge clk_i /or negedge rst_i/)`
582			`begin`
583			`if(~rst_i)`
584			`begin`
585			`count = 6'bx;`
586			`hilo = 65'b0;`
587			`op2_reged = 33'bx;`
588			`op1_sign_reged = 1'bx;`
589			`op2_sign_reged = 1'bx;`
590			`sub_or_yn = 1'bx;`
591			`rdy = 1'b1;`
592			`start = 1'bx;`
593			`sign = 1'bx;`
594			`mul = 1'bx;`
595
596			`finish = 1'bx;`
597			`add1 = 1'bx;`
598			`addop2 = 1'bx;`
599			`addnop2 = 1'bx;`
600			`end`
601			`else begin`
602
603			`if(op_type == OP_MTHI \|\| op_type == OP_MTLO)`
604			`begin`
605			`if(op_type == OP_MTHI) hilo[64:32] = {1'b0,op1};`
606			`if(op_type == OP_MTLO) hilo[31:0] = op1;`
607			`rdy = 1;`
608			`end`
609			`else if(rdy)`
610			`begin`
611			`start = (op_type == OP_MULT) \|\| (op_type == OP_MULTU) \|\| (op_type == OP_DIV) \|\| (op_type == OP_DIVU);`
612			`mul = (op_type == OP_MULT) \|\| (op_type == OP_MULTU);`
613			`sign = (op_type == OP_MULT) \|\| (op_type == OP_DIV);`
614
615			`if(start)`
616			`begin:START_SECTION`
617			`reg [32:0] over;`
618
619			`op2_reged = {sign ?op2[31] :1'b0 ,op2};`
620			`hilo = {~mul && sign?{33{op1[31]}}:33'b0,op1};`
621			`count = 6'b000000;`
622			`rdy = 0;`
623			`op1_sign_reged = sign?op1[31]:0;`
624			`op2_sign_reged = sign?op2[31]:0;`
625			`sub_or_yn = 0;`
626
627			`over = ~op2_reged + {op1[31],op1};`
628			`overflow = sign && ~mul ? op1_sign_reged && op2_sign_reged && ~over[32] : 0;`
629
630			`finish = 0;`
631			`end`
632			`end`
633			`else if(start)`
634			`begin`
635			`if(overflow)`
636			`begin`
637			`hilo[63:0] = {hilo[31:0],32'b0};`
638			`rdy = 1;`
639			`end`
640			`else if(!count[5])`
641			`begin`
642			`if(mul)`
643			`begin`
644			`if(sign)`
645			`begin`
646			`case({hilo[0],sub_or_yn})`
647			`2'b10:hilo[64:32] = hilo[64:32] + nop2_reged;`
648			`2'b01:hilo[64:32] = hilo[64:32] + op2_reged;`
649			`default:;`
650			`endcase`
651			`{hilo[63:0],sub_or_yn} = hilo[64:0];`
652			`end`
653			`else begin`
654			`if(hilo[0]) hilo[64:32] = hilo[64:32] + op2_reged;`
655			`hilo = {1'b0,hilo[64:1]};`
656			`end`
657			`end`
658			`else begin`
659			`sub_or_yn = hilo[64]== op2_sign_reged;`
660			`hilo[64:1] = hilo[63:0];`
661
662			`hilo[64:32] = sub_or_yn ? hilo[64:32] + nop2_reged : hilo[64:32] + op2_reged;`
663
664			`hilo[0] = hilo[64]== op2_sign_reged;`
665			`end`
666
667			`count = count + 1'b1;`
668			`end`
669			`else begin`
670			`if(finish)`
671			`begin`
672			`if(add1) hilo[31:0] = hilo[31:0] + 1;`
673			`case({addop2,addnop2})`
674			`2'b10: hilo[64:32] = hilo[64:32] + op2_reged;`
675			`2'b01: hilo[64:32] = hilo[64:32] + nop2_reged;`
676			`default: ;`
677			`endcase`
678			`rdy = 1;`
679			`end`
680			`else begin`
681			`{add1,addop2,addnop2} = 3'b000;`
682			`finish = 1;`
683
684			`if(~mul)`
685			`begin:LAST_CYCLE_DEAL_SECTION`
686			`reg eqz,eqop2,eqnop2;`
687			`eqz = hilo[64:32] == 0;`
688			`eqop2 = hilo[64:32] == op2_reged;`
689			`eqnop2 = hilo[64:32] == nop2_reged;`
690			`casex({op1_sign_reged,op2_sign_reged,eqz,eqop2,eqnop2})`
691			`5'b101xx : {add1,addop2,addnop2} = 3'b000;`
692			`5'b100x1 : {add1,addop2,addnop2} = 3'b010;`
693			`5'b111xx : {add1,addop2,addnop2} = 3'b100;`
694			`5'b1101x : {add1,addop2,addnop2} = 3'b101;`
695			`default :`
696			`begin:LAST_CYCLE_DEAL_SECTION_DEFAULT`
697
698			`reg op1s_eq_op2s,op1s_eq_h64;`
699			`op1s_eq_op2s = op1_sign_reged == op2_sign_reged;`
700			`op1s_eq_h64 = op1_sign_reged == hilo[64];`
701
702			`add1 = ~op1s_eq_op2s;`
703			`case({op1s_eq_op2s,op1s_eq_h64})//synthesis parallel_case`
704			`2'b00: {addop2,addnop2} = 2'b01;`
705			`2'b10: {addop2,addnop2} = 2'b10;`
706			`default: {addop2,addnop2} = 2'b00;`
707			`endcase`
708			`end`
709			`endcase`
710			`end`
711			`end`
712			`end`
713			`end`
714			`end`
715			`end`
716			`endmodule`
717
718