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[/] [mips789/] [tags/] [arelease/] [rtl/] [verilog/] [fifo.v] - Blame information for rev 56

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`include "include.h"
 
module fifo
    (
        clk_i,
        rst_i,
        clear_i,
        data_i,
        wen_i,
        ren_i,
        data_o,
        almost_full_o,
        full_o,
        almost_empty_o,
        empty_o,
        cnt_o
    );
 
    parameter DATA_WIDTH    = 8;
    parameter DEPTH         = 8;
    parameter CNT_WIDTH     = 4;
 
 
    input  clk_i;
    input  rst_i;
    input  clear_i;
 
    input  wen_i;
    input  [DATA_WIDTH-1:0] data_i;
 
    input  ren_i;
    output [DATA_WIDTH-1:0] data_o;
    output almost_full_o;
    output full_o;
    output almost_empty_o;
    output empty_o;
    output [CNT_WIDTH-1:0] cnt_o;
 
    reg    [DATA_WIDTH-1:0] mem[0:DEPTH-1];
 
    reg    [CNT_WIDTH-1:0] cnt;
    reg    [CNT_WIDTH-2:0] read_pointer;
    reg    [CNT_WIDTH-2:0] write_pointer;
    assign cnt_o = cnt;
 
    always @(posedge clk_i /*or posedge rst_i*/)
    begin
        if(~rst_i)
            cnt <=  0;
        else if(clear_i)
            cnt <=  {{(CNT_WIDTH-1){1'b0}},ren_i^wen_i};
        else if(ren_i ^ wen_i)
        begin
            if(ren_i & ~empty_o)
                cnt <= cnt - 1'b1;
            else if( wen_i & ~full_o)
                cnt <= cnt + 1'b1;
        end
    end
 
    always @(posedge clk_i/* or posedge rst_i*/)
    begin
        if(~rst_i)
            read_pointer <= 0;
        else if(clear_i)
            read_pointer <= { {(CNT_WIDTH-2){1'b0}}, ren_i};
        else if(ren_i & ~empty_o)
            read_pointer <= read_pointer + 1'b1;
    end
 
    always @ (posedge clk_i /*or posedge rst_i*/)
    begin
        if(~rst_i)
            write_pointer <= 0;
        else if(clear_i)
            write_pointer <= { {(CNT_WIDTH-2){1'b0}}, wen_i};
        else if(wen_i & ~full_o)
            write_pointer <= write_pointer + 1'b1;
    end
 
    assign empty_o = ~(|cnt);
    assign almost_empty_o = cnt == 1;
    assign full_o  = cnt == DEPTH;
    assign almost_full_o  = &cnt[CNT_WIDTH-2:0];
 
    always @ (posedge clk_i)
    begin
        if(wen_i & clear_i)
            mem[0] <= data_i;
        else if(wen_i & ~full_o)
            mem[write_pointer] <= data_i;
    end
 
    assign data_o = clear_i ? mem[0] : mem[read_pointer];
 
endmodule
 
 

Line No.	Rev	Author	Line
1	10	mcupro	`include "include.h"
2
3			`module fifo`
4			`(`
5			`clk_i,`
6			`rst_i,`
7			`clear_i,`
8			`data_i,`
9			`wen_i,`
10			`ren_i,`
11			`data_o,`
12			`almost_full_o,`
13			`full_o,`
14			`almost_empty_o,`
15			`empty_o,`
16			`cnt_o`
17			`);`
18
19			`parameter DATA_WIDTH = 8;`
20			`parameter DEPTH = 8;`
21			`parameter CNT_WIDTH = 4;`
22
23
24			`input clk_i;`
25			`input rst_i;`
26			`input clear_i;`
27
28			`input wen_i;`
29			`input [DATA_WIDTH-1:0] data_i;`
30
31			`input ren_i;`
32			`output [DATA_WIDTH-1:0] data_o;`
33			`output almost_full_o;`
34			`output full_o;`
35			`output almost_empty_o;`
36			`output empty_o;`
37			`output [CNT_WIDTH-1:0] cnt_o;`
38
39			`reg [DATA_WIDTH-1:0] mem[0:DEPTH-1];`
40
41			`reg [CNT_WIDTH-1:0] cnt;`
42			`reg [CNT_WIDTH-2:0] read_pointer;`
43			`reg [CNT_WIDTH-2:0] write_pointer;`
44			`assign cnt_o = cnt;`
45
46			`always @(posedge clk_i /or posedge rst_i/)`
47			`begin`
48	15	mcupro	`if(~rst_i)`
49	10	mcupro	`cnt <= 0;`
50			`else if(clear_i)`
51			`cnt <= {{(CNT_WIDTH-1){1'b0}},ren_i^wen_i};`
52			`else if(ren_i ^ wen_i)`
53			`begin`
54			`if(ren_i & ~empty_o)`
55			`cnt <= cnt - 1'b1;`
56			`else if( wen_i & ~full_o)`
57			`cnt <= cnt + 1'b1;`
58			`end`
59			`end`
60
61			`always @(posedge clk_i/* or posedge rst_i*/)`
62			`begin`
63	15	mcupro	`if(~rst_i)`
64	10	mcupro	`read_pointer <= 0;`
65			`else if(clear_i)`
66			`read_pointer <= { {(CNT_WIDTH-2){1'b0}}, ren_i};`
67			`else if(ren_i & ~empty_o)`
68			`read_pointer <= read_pointer + 1'b1;`
69			`end`
70
71			`always @ (posedge clk_i /or posedge rst_i/)`
72			`begin`
73	15	mcupro	`if(~rst_i)`
74	10	mcupro	`write_pointer <= 0;`
75			`else if(clear_i)`
76			`write_pointer <= { {(CNT_WIDTH-2){1'b0}}, wen_i};`
77			`else if(wen_i & ~full_o)`
78			`write_pointer <= write_pointer + 1'b1;`
79			`end`
80
81			`assign empty_o = ~(\|cnt);`
82			`assign almost_empty_o = cnt == 1;`
83			`assign full_o = cnt == DEPTH;`
84			`assign almost_full_o = &cnt[CNT_WIDTH-2:0];`
85
86			`always @ (posedge clk_i)`
87			`begin`
88			`if(wen_i & clear_i)`
89			`mem[0] <= data_i;`
90			`else if(wen_i & ~full_o)`
91			`mem[write_pointer] <= data_i;`
92			`end`
93
94			`assign data_o = clear_i ? mem[0] : mem[read_pointer];`
95
96			`endmodule`
97
98

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[/] [mips789/] [tags/] [arelease/] [rtl/] [verilog/] [fifo.v] - Blame information for rev 56