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[/] [mips789/] [tags/] [arelease/] [rtl/] [verilog/] [forward.v] - Blame information for rev 56

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1 35 mcupro 
/******************************************************************
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 *                                                                *
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 *    Author: Liwei                                               *
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 *                                                                *
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 *    This file is part of the "mips789" project.                 *
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 *    Downloaded from:                                            *
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 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
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 *                                                                *
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 *    If you encountered any problem, please contact me via       *
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 *    Email:mcupro@opencores.org  or mcupro@163.com               *
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 *                                                                *
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 ******************************************************************/
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14 35 mcupro 
`include "mips789_defs.v"
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module fw_latch5(input clk,input[4:0]d,output reg  [4:0]q);
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    always @ (posedge clk) q<=d;
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endmodule
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module fw_latch1(input clk,input d,output reg q);
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    always @ (posedge clk) q<=d;
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endmodule
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module forward_node (
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        input [4:0]rn,
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        input [4:0]alu_wr_rn,
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        input alu_we,
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        input [4:0]mem_wr_rn,
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        input mem_we,
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        output  wire[2:0]mux_fw
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    );
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    assign mux_fw = ((alu_we)&&(alu_wr_rn==rn)&&(alu_wr_rn!=0))?`FW_ALU:
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           ((mem_we)&&(mem_wr_rn==rn)&&(mem_wr_rn!=0))?`FW_MEM:
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           `FW_NOP;
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endmodule
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module fwd_mux(
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        input [31:0]din,
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        output reg [31:0]dout,
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        input [31:0]fw_alu       ,
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        input [2:0]fw_ctl,
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        input [31:0]fw_dmem
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    );
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    always@(*)
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    case (fw_ctl)
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        `FW_ALU :dout=fw_alu;
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        `FW_MEM :dout=fw_dmem;
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        `FW_NOP :dout=din;
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        default dout=din;
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    endcase
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endmodule
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module forward  (alu_we,clk,mem_We,fw_alu_rn,fw_mem_rn,rns_i,rnt_i,alu_rs_fw,alu_rt_fw,cmp_rs_fw,
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                     cmp_rt_fw,dmem_fw) ;
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    input alu_we;
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    wire alu_we;
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    input clk;
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    wire clk;
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    input mem_We;
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    wire mem_We;
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    input [4:0] fw_alu_rn;
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    wire [4:0] fw_alu_rn;
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    input [4:0] fw_mem_rn;
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    wire [4:0] fw_mem_rn;
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    input [4:0] rns_i;
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    wire [4:0] rns_i;
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    input [4:0] rnt_i;
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    wire [4:0] rnt_i;
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    output [2:0] alu_rs_fw;
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    wire [2:0] alu_rs_fw;
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    output [2:0] alu_rt_fw;
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    wire [2:0] alu_rt_fw;
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    output [2:0] cmp_rs_fw;
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    wire [2:0] cmp_rs_fw;
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    output [2:0] cmp_rt_fw;
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    wire [2:0] cmp_rt_fw;
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    output [2:0] dmem_fw;
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    wire [2:0] dmem_fw;
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    wire [2:0] BUS1345;
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    wire [4:0] BUS82;
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    wire [4:0] BUS937;
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    forward_node fw_alu_rs
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                 (
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                     .alu_we(alu_we),
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                     .alu_wr_rn(fw_alu_rn),
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                     .mem_we(mem_We),
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                     .mem_wr_rn(fw_mem_rn),
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                     .mux_fw(alu_rs_fw),
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                     .rn(BUS82)
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                 );
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    forward_node fw_alu_rt
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                 (
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                     .alu_we(alu_we),
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                     .alu_wr_rn(fw_alu_rn),
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                     .mem_we(mem_We),
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                     .mem_wr_rn(fw_mem_rn),
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                     .mux_fw(BUS1345),
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                     .rn(BUS937)
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                 );
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    forward_node fw_cmp_rs
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                 (
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                     .alu_we(alu_we),
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                     .alu_wr_rn(fw_alu_rn),
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                     .mem_we(mem_We),
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                     .mem_wr_rn(fw_mem_rn),
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                     .mux_fw(cmp_rs_fw),
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                     .rn(rns_i)
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                 );
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    forward_node fw_cmp_rt
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                 (
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                     .alu_we(alu_we),
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                     .alu_wr_rn(fw_alu_rn),
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                     .mem_we(mem_We),
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                     .mem_wr_rn(fw_mem_rn),
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                     .mux_fw(cmp_rt_fw),
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                     .rn(rnt_i)
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                 );
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    fw_latch5 fw_reg_rns
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              (
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                  .clk(clk),
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                  .d(rns_i),
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                  .q(BUS82)
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              );
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    fw_latch5 fw_reg_rnt
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              (
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                  .clk(clk),
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                  .d(rnt_i),
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                  .q(BUS937)
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              );
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    assign alu_rt_fw[2:0] = BUS1345[2:0];
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    assign dmem_fw[2:0] = BUS1345[2:0];
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endmodule
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