URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [tags/] [arelease/] [rtl/] [verilog/] [mips_dvc.v] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log


`include "include.h"
 
module mips_dvc (
 
        input [31:0]din,
        input clk,
        input rst,
        input [31:0]addr ,
        input [3:0]mem_ctl,
 
        output reg [31:0]dout ,
 
        output reg[7:0] lcd_data,
        output lcd_rs,
        output lcd_rw,
        output lcd_en,
 
        input  ser_rxd,
        output ser_txd,
 
        output [6:0]seg7led1,
        output [6:0]seg7led2     ,
        output led1,
        output led2               ,
        input key1,
        input key2 ,
 
        output reg[31:0]irq_addr_o,  //not registed
        output irq_req_o
    );
 
    reg r_key1;
    reg r_key2;
 
    reg rr_key1;
    reg rr_key2;
 
    always @(posedge clk)
    begin
        r_key1<=key1;
        r_key2<=key2;
    end
 
    always @(posedge clk)
    begin
        rr_key1<=r_key1;
        rr_key2<=r_key2;
    end
 
 
    wire sv_byte = (mem_ctl==`DMEM_SB);
    wire ld_byte = mem_ctl==`DMEM_LBS||mem_ctl==`DMEM_LBU;
 
    wire sv_wd = (mem_ctl==`DMEM_SW);
    wire ld_wd = (mem_ctl==`DMEM_LW);
 
 
    wire wr_uartdata   =          addr==`UART_DATA_ADDR         &&              sv_byte;
    wire wr_lcddata    =          addr==`LCD_DATA_ADDR          &&              sv_byte;
    wire rd_uartdata   =          addr==`UART_DATA_ADDR         &&              ld_byte;
    wire rd_status         =      addr==`STATUS_ADDR            &&              ld_wd;
    wire wr_cmd        =          addr==`CMD_ADDR                       &&              sv_wd;
    wire rd_cmd        =          addr==`CMD_ADDR                       &&              ld_wd;
    wire wr_seg7       =          addr==`SEG7LED_ADDR           &&              sv_byte  ;
 
    wire set_tmr_addr  = addr==`TMR_IRQ_ADDR    &&     sv_wd;
    wire set_key1_addr = addr==`KEY1_IRQ_ADDR   &&     sv_wd;
    wire set_key2_addr = addr==`KEY2_IRQ_ADDR   &&     sv_wd;
    wire wr_tmr_data   = addr==`TMR_DATA_ADDR   &&     sv_wd;
    wire rd_tmr_data   = addr==`TMR_DATA_ADDR   &&     ld_wd;
 
    wire w_tmr_req;
    wire [31:0]w_tmr_data;
 
    reg [31:0] tmr_addr;
    reg [31:0] key1_addr;
    reg [31:0] key2_addr;
 
    reg [31:0] cmd ;
 
    // wire w_txd_ld            =               cmd[0]  ;
    wire w_rxd_ft               =               cmd[1]  ;
 
    assign lcd_rs               =               cmd[2]  ;
    assign lcd_rw               =               cmd[3]  ;
    assign lcd_en               =               cmd[4]  ;
 
    assign led1                 =               cmd[5]  ;
    assign led2                 =               cmd[6]  ;
 
    wire  tmr_clr               =       cmd[7]  ;
    wire  tmr_en                =               cmd[8]  ;
 
    /*
 
    */
 
    reg [7:0] seg7data;
    wire [7:0] uart_dout;
    wire w_txd_busy;
    wire w_rx_rdy;
 
    always@(posedge clk )
        if (rst)
        begin
            dout<=0;
        end
        else
        begin
            if (rd_status) dout<={28'b0,/*added here*/w_rx_rdy,w_txd_busy,rr_key1,rr_key2};else
            if (rd_cmd)dout<=cmd;else
            if (rd_uartdata)dout<={24'b0,uart_dout};else
            if ( rd_tmr_data )dout<=w_tmr_data; else
            dout<=0;
        end
 
    always @(posedge clk)
        if (rst)
        begin
            cmd<=0;
            seg7data<=0;
            tmr_addr<=32'BX      ;
            key1_addr<=32'BX;
            key2_addr<=32'BX;
        end
        else
        begin
            /*
            casex({wr_uartdata,wr_cmd,wr_seg7,wr_lcddata,set_tmr_addr,set_key1_addr,set_key1_addr})      //synthesis parallel_case
                     7'b1xxxxxx:          uart_data<=din[7:0];
            7'bx1xxxxx:                    cmd<=din;
            7'bxx1xxxx:                                         seg7data<=din[7:0];
            7'bxxx1xxx:                          lcd_data<=din[7:0];
            7'bxxxx1xx:            tmr_addr<=din;
            7'bxxxxx1x:                 key1_addr<=din;
            7'bxxxxxx1:                 key2_addr<=din;
            endcase
            */
 
            //  if (wr_uartdata)  uart_data<=din[7:0];
            if (wr_cmd)   cmd<=din;
            if (wr_seg7) seg7data<=din[7:0];
            if (wr_lcddata)        lcd_data<=din[7:0];
 
            if (set_tmr_addr)tmr_addr<=din;
            if (set_key1_addr)key1_addr<=din;
            if (set_key2_addr)key2_addr<=din;
 
        end
 
    uart0 iuart0(
 
              .clk(clk),
              .rst(rst),
              .ser_rxd(ser_rxd),
              .ser_txd(ser_txd),
 
              .rxd_ft(w_rxd_ft),
              .txd_ld(wr_uartdata),
 
              .din(din[7:0]),
 
              .rxd_rdy(w_rx_rdy),
              .txd_busy(w_txd_busy),
 
              .dout(uart_dout)
          ) ;
 
    seg7led_cv iseg7_cv (
                   .data(seg7data),
                   .seg7led1(seg7led1),
                   .seg7led2(seg7led2)
               );
 
    tmr0 mips_tmr0(
             .clk(clk),
             .clr( tmr_clr),
             .din(din) ,
             .ld(wr_tmr_data),
             .tmr_en(tmr_en),
             .tmr_req(w_tmr_req),
             .cntr_o(w_tmr_data)
         );
 
 
    //interrupt control
    wire tmr_irq_bit  =       cmd[31] ;
    wire key1_irq_bit =       cmd[30] ;
    wire key2_irq_bit =       cmd[29] ;
 
    wire tmr_req_do =   w_tmr_req & tmr_irq_bit;
    wire key1_req_do = rr_key1 & key1_irq_bit;
    wire key2_req_do = rr_key2 & key2_irq_bit;
 
    assign irq_req_o = 0;//tmr_req_do;
 
    always @(*)
        if       (tmr_req_do)         irq_addr_o = tmr_addr;else
    if (key1_req_do)     irq_addr_o = key1_addr;else
    if (key2_req_do)      irq_addr_o = key2_addr ;
    else                      irq_addr_o = 0;
 
endmodule

Browse

Tools

Subversion Repositories mips789

[/] [mips789/] [tags/] [arelease/] [rtl/] [verilog/] [mips_dvc.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	10	mcupro	`include "include.h"
2
3			`module mips_dvc (`
4
5			`input [31:0]din,`
6			`input clk,`
7			`input rst,`
8			`input [31:0]addr ,`
9			`input [3:0]mem_ctl,`
10
11			`output reg [31:0]dout ,`
12
13			`output reg[7:0] lcd_data,`
14			`output lcd_rs,`
15			`output lcd_rw,`
16			`output lcd_en,`
17
18			`input ser_rxd,`
19			`output ser_txd,`
20
21			`output [6:0]seg7led1,`
22			`output [6:0]seg7led2 ,`
23			`output led1,`
24			`output led2 ,`
25			`input key1,`
26			`input key2 ,`
27
28			`output reg[31:0]irq_addr_o, //not registed`
29			`output irq_req_o`
30			`);`
31
32			`reg r_key1;`
33			`reg r_key2;`
34
35			`reg rr_key1;`
36			`reg rr_key2;`
37
38			`always @(posedge clk)`
39			`begin`
40			`r_key1<=key1;`
41			`r_key2<=key2;`
42			`end`
43
44			`always @(posedge clk)`
45			`begin`
46			`rr_key1<=r_key1;`
47			`rr_key2<=r_key2;`
48			`end`
49
50
51			wire sv_byte = (mem_ctl==`DMEM_SB);
52			wire ld_byte = mem_ctl==`DMEM_LBS\|\|mem_ctl==`DMEM_LBU;
53
54			wire sv_wd = (mem_ctl==`DMEM_SW);
55			wire ld_wd = (mem_ctl==`DMEM_LW);
56
57
58			wire wr_uartdata = addr==`UART_DATA_ADDR && sv_byte;
59			wire wr_lcddata = addr==`LCD_DATA_ADDR && sv_byte;
60			wire rd_uartdata = addr==`UART_DATA_ADDR && ld_byte;
61			wire rd_status = addr==`STATUS_ADDR && ld_wd;
62			wire wr_cmd = addr==`CMD_ADDR && sv_wd;
63			wire rd_cmd = addr==`CMD_ADDR && ld_wd;
64			wire wr_seg7 = addr==`SEG7LED_ADDR && sv_byte ;
65
66			wire set_tmr_addr = addr==`TMR_IRQ_ADDR && sv_wd;
67			wire set_key1_addr = addr==`KEY1_IRQ_ADDR && sv_wd;
68			wire set_key2_addr = addr==`KEY2_IRQ_ADDR && sv_wd;
69			wire wr_tmr_data = addr==`TMR_DATA_ADDR && sv_wd;
70			wire rd_tmr_data = addr==`TMR_DATA_ADDR && ld_wd;
71
72			`wire w_tmr_req;`
73			`wire [31:0]w_tmr_data;`
74
75			`reg [31:0] tmr_addr;`
76			`reg [31:0] key1_addr;`
77			`reg [31:0] key2_addr;`
78
79			`reg [31:0] cmd ;`
80
81			`// wire w_txd_ld = cmd[0] ;`
82			`wire w_rxd_ft = cmd[1] ;`
83
84			`assign lcd_rs = cmd[2] ;`
85			`assign lcd_rw = cmd[3] ;`
86			`assign lcd_en = cmd[4] ;`
87
88			`assign led1 = cmd[5] ;`
89			`assign led2 = cmd[6] ;`
90
91			`wire tmr_clr = cmd[7] ;`
92			`wire tmr_en = cmd[8] ;`
93
94			`/*`
95
96			`*/`
97
98			`reg [7:0] seg7data;`
99			`wire [7:0] uart_dout;`
100			`wire w_txd_busy;`
101			`wire w_rx_rdy;`
102
103			`always@(posedge clk )`
104			`if (rst)`
105			`begin`
106			`dout<=0;`
107			`end`
108			`else`
109			`begin`
110			`if (rd_status) dout<={28'b0,/added here/w_rx_rdy,w_txd_busy,rr_key1,rr_key2};else`
111			`if (rd_cmd)dout<=cmd;else`
112			`if (rd_uartdata)dout<={24'b0,uart_dout};else`
113			`if ( rd_tmr_data )dout<=w_tmr_data; else`
114			`dout<=0;`
115			`end`
116
117			`always @(posedge clk)`
118			`if (rst)`
119			`begin`
120			`cmd<=0;`
121			`seg7data<=0;`
122			`tmr_addr<=32'BX ;`
123			`key1_addr<=32'BX;`
124			`key2_addr<=32'BX;`
125			`end`
126			`else`
127			`begin`
128			`/*`
129			`casex({wr_uartdata,wr_cmd,wr_seg7,wr_lcddata,set_tmr_addr,set_key1_addr,set_key1_addr}) //synthesis parallel_case`
130			`7'b1xxxxxx: uart_data<=din[7:0];`
131			`7'bx1xxxxx: cmd<=din;`
132			`7'bxx1xxxx: seg7data<=din[7:0];`
133			`7'bxxx1xxx: lcd_data<=din[7:0];`
134			`7'bxxxx1xx: tmr_addr<=din;`
135			`7'bxxxxx1x: key1_addr<=din;`
136			`7'bxxxxxx1: key2_addr<=din;`
137			`endcase`
138			`*/`
139
140			`// if (wr_uartdata) uart_data<=din[7:0];`
141			`if (wr_cmd) cmd<=din;`
142			`if (wr_seg7) seg7data<=din[7:0];`
143			`if (wr_lcddata) lcd_data<=din[7:0];`
144
145			`if (set_tmr_addr)tmr_addr<=din;`
146			`if (set_key1_addr)key1_addr<=din;`
147			`if (set_key2_addr)key2_addr<=din;`
148
149			`end`
150
151			`uart0 iuart0(`
152
153			`.clk(clk),`
154			`.rst(rst),`
155			`.ser_rxd(ser_rxd),`
156			`.ser_txd(ser_txd),`
157
158			`.rxd_ft(w_rxd_ft),`
159			`.txd_ld(wr_uartdata),`
160
161			`.din(din[7:0]),`
162
163			`.rxd_rdy(w_rx_rdy),`
164			`.txd_busy(w_txd_busy),`
165
166			`.dout(uart_dout)`
167			`) ;`
168
169			`seg7led_cv iseg7_cv (`
170			`.data(seg7data),`
171			`.seg7led1(seg7led1),`
172			`.seg7led2(seg7led2)`
173			`);`
174
175			`tmr0 mips_tmr0(`
176			`.clk(clk),`
177			`.clr( tmr_clr),`
178			`.din(din) ,`
179			`.ld(wr_tmr_data),`
180			`.tmr_en(tmr_en),`
181			`.tmr_req(w_tmr_req),`
182			`.cntr_o(w_tmr_data)`
183			`);`
184
185
186			`//interrupt control`
187			`wire tmr_irq_bit = cmd[31] ;`
188			`wire key1_irq_bit = cmd[30] ;`
189			`wire key2_irq_bit = cmd[29] ;`
190
191			`wire tmr_req_do = w_tmr_req & tmr_irq_bit;`
192			`wire key1_req_do = rr_key1 & key1_irq_bit;`
193			`wire key2_req_do = rr_key2 & key2_irq_bit;`
194
195			`assign irq_req_o = 0;//tmr_req_do;`
196
197			`always @(*)`
198			`if (tmr_req_do) irq_addr_o = tmr_addr;else`
199			`if (key1_req_do) irq_addr_o = key1_addr;else`
200			`if (key2_req_do) irq_addr_o = key2_addr ;`
201			`else irq_addr_o = 0;`
202
203			`endmodule`