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/******************************************************************
 *                                                                *
 *    Author: Liwei                                               *
 *                                                                *
 *    This file is part of the "mips789" project.                 *
 *    Downloaded from:                                            *
 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
 *                                                                *
 *    If you encountered any problem, please contact me via       *
 *    Email:mcupro@opencores.org  or mcupro@163.com               *
 *                                                                *
 ******************************************************************/
 
`include "mips789_defs.v"
 
module rxd_d(input clr,input clk,input d,output reg q );
 
    always @(posedge clk)
 
        if      (clr) q<=0;
        else          q<=d|q;
 
endmodule
 
module uart0 (
        clk,rst,rxd_ft,ser_rxd,txd_ld,
        din,rxd_rdy,ser_txd,txd_busy,dout) ;
    input clk;
    wire clk;
    input rst;
    wire rst;
    input rxd_ft;
    wire rxd_ft;
    input ser_rxd;
    wire ser_rxd;
    input txd_ld;
    wire txd_ld;
    input [7:0] din;
    wire [7:0] din;
    output rxd_rdy;
    wire rxd_rdy;
    output ser_txd;
    wire ser_txd;
    output txd_busy;
    wire txd_busy;
    output [7:0] dout;
    wire [7:0] dout;
 
    wire clk_uart=clk;
    wire w_rxd_rdy;
 
    uart_read uart_rd_tak(
                  .sync_reset(rst),
                  .clk(clk),
                  .rxd(ser_rxd),
                  .buffer_reg(dout),
                  .int_req(w_rxd_rdy)
              );
 
    rxd_d rxd_rdy_hold_lw
          (
              .clk(clk_uart),
              .clr(rxd_ft),
              .d(w_rxd_rdy),
              .q(rxd_rdy)
          );
 
    uart_write uart_txd
               (
                   .sync_reset(rst),
                   .clk(clk),
                   .txd(ser_txd),
                   .data_in(din) ,
                   .write_request(txd_ld),
                   //.write_done(),
                   .write_busy(txd_busy)
               );
 
endmodule
 
//These modules below are modified slight by Liwei based on YACC,an CPU core in opencores.
//Thank you TAK
 
module  uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy);
    input sync_reset,clk;
    input [7:0] data_in;
    input write_request;
    output txd,write_done;
    output write_busy;
 
 
 
    wire                queue_full;
    wire        queing, read_request;
    wire [7:0] queue_data;
    reg read_request_ff;
 
 
    //________|--|___write_request (upper  module :     its period should be 1clock time.)
    //__________________________|-|______write_done    (Responds by this module posedge interrupt)
    //With 512Bytes FIFO.
    //No error handling is supported.
 
    reg         [15:0] clk_ctr;//liwei
    reg         [2:0] bit_ctr;
    reg         [2:0] ua_state;
    reg         [7:0] tx_sr;
    reg         txd;
 
    wire         clk_ctr_equ15, clk_ctr_equ31,  bit_ctr_equ7,
          clk_ctr_enable_state, bit_ctr_enable_state  ;
    wire    tx_state;
    wire empty;
    assign write_busy=queue_full;//Apr.2.2005
 
    always @ (posedge clk) begin
        if (~sync_reset)        read_request_ff<=1'b0;
        else                    read_request_ff<=read_request;
    end
 
    assign queing=      !empty;
    assign read_request  = queing && ua_state==3'b000;//Jul.14.2004
 
    assign write_done=ua_state==3'b101;
 
`ifdef ALTERA
    fifo512_cyclone  alt_fifo(
                         .data(data_in),
                         .wrreq(write_request),
                         .rdreq(read_request),
                         .clock(clk),
                         .q(queue_data),
                         .full(queue_full),
                         .empty(empty));
`else//debug model in simulations
 
    sim_fifo512_cyclone  sim_fifo(
                             .data(data_in),
                             .wrreq(write_request),
                             .rdreq(read_request),
                             .clock(clk),
                             .q(queue_data),
                             .full(queue_full),
                             .empty(empty),
                             .rst(sync_reset));
`endif
 
 
 
    // 7bit counter
    // I set the regerster lenth as 16 .Sufficent but not waste.Liwei
    always @(posedge clk ) begin
        if (~sync_reset)
            clk_ctr <= 0;
        else if (clk_ctr_enable_state && clk_ctr_equ31)  clk_ctr<=0;
        else if (clk_ctr_enable_state)                   clk_ctr <= clk_ctr + 1;
        else    clk_ctr <= 0;
    end
 
 
    assign      clk_ctr_equ15 = clk_ctr==`COUNTER_VALUE1;
    assign      clk_ctr_equ31 = clk_ctr==`COUNTER_VALUE2;
 
    // 3bit counter
    always @(posedge clk) begin
        if (~sync_reset)
            bit_ctr <= 0;
        else if (bit_ctr_enable_state) begin
            if (clk_ctr_equ15)
                bit_ctr <= bit_ctr + 1;
        end
        else
            bit_ctr <= 0;
    end
 
    assign      bit_ctr_equ7 = (bit_ctr==7);
 
    assign      clk_ctr_enable_state = bit_ctr_enable_state ||ua_state==3'b110 ||  ua_state==3'b001 ||  ua_state==3'b100||ua_state==3'b101;
    assign      bit_ctr_enable_state =  ua_state==3'b010 || ua_state==3'b011;
 
 
    always @(posedge clk ) begin
        if (~sync_reset) ua_state <= 3'b000;
        else begin
            case (ua_state)
                3'b000: if (queing)  ua_state <= 3'b001;        //wait write_request
                3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit
                3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011;           // start bit, bit0-7 data  send
                3'b011: if (clk_ctr_equ15) ua_state <= 3'b100;                                  // bit7 data send
                3'b100: if (clk_ctr_equ15) ua_state <= 3'b101;  // stop bit                             // stop bit send
                3'b101: if (clk_ctr_equ15) ua_state <= 3'b110;  //LIWEI                         // stop bit send
                3'b110: if (clk_ctr_equ15) ua_state <= 3'b111;            //LIWEI
                3'b111:  ua_state <= 3'h0;      // TAK                                  // byte read cycle end
                default: ua_state <= 3'h0;
            endcase
        end
    end
 
 
 
 
    // tx shift reg.
    always @(posedge clk ) begin
        if (~sync_reset) tx_sr<=0;
        else if (read_request_ff) tx_sr <= queue_data[7:0]; //data_in[7:0]; // load
        else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]};
    end
 
    assign  tx_state=(  ua_state==3'h2 || ua_state==3'h3)               &&      clk_ctr_equ15;
 
 
    // tx
    always @(posedge clk ) begin
        if (~sync_reset) txd <=1'b1;
        else if (~sync_reset)                     txd<=1'b1;
        else if (ua_state==3'h0)                  txd<=1'b1;
        else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0;    // start bit
        else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0];
        else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1;     // stop bit
    end
endmodule
 
 
module  uart_read( sync_reset, clk, rxd,buffer_reg, int_req);
    input sync_reset;
    input       clk, rxd;
    output      [7:0] buffer_reg;
    output      int_req;
 
 
    //________|-|______int_req (This module,, posedge interrupt)
    //
    //Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time...
    //
    //No error handling (overrun ) is supported.
 
    reg         rxq1;
    reg         [15:0] clk_ctr;
    reg         [2:0] bit_ctr;
    reg         [2:0] ua_state;
    reg         [7:0] rx_sr;             //.,tx_sr;
    reg         int_req;
    reg         [7:0] buffer_reg;
 
    wire         clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
          clk_ctr_enable_state, bit_ctr_enable_state  ;
    wire        clk_ctr_equ0;
 
    //sync_reset
 
    //synchronization
    always @(posedge clk ) begin
        rxq1 <=rxd ;
    end
 
    // 7bit counter
    always @(posedge clk ) begin
        if (~sync_reset)
            clk_ctr <= 0;
        else if (clk_ctr_enable_state && clk_ctr_equ31)  clk_ctr<=0;
        else if (clk_ctr_enable_state)                   clk_ctr <= clk_ctr + 1;
        else    clk_ctr <= 0;
    end
    assign      clk_ctr_equ15 =  (clk_ctr==`COUNTER_VALUE1)  ;//
    assign      clk_ctr_equ31 =  (clk_ctr==`COUNTER_VALUE2) ;//
    assign  clk_ctr_equ0=    (clk_ctr==`COUNTER_VALUE3);        //
 
 
    // 3bit counter
    always @(posedge clk) begin
        if (~sync_reset)
            bit_ctr <= 0;
        else if (bit_ctr_enable_state) begin
            if (clk_ctr_equ15)
                bit_ctr <= bit_ctr + 1;
        end
        else
            bit_ctr <= 0;
    end
 
    assign      bit_ctr_equ7 = (bit_ctr==7);
 
 
    assign      clk_ctr_enable_state =  ua_state !=3'b000  && ua_state<=3'b011;
    assign      bit_ctr_enable_state = ua_state==3'h2;
 
    always @(posedge clk ) begin
        if (~sync_reset) ua_state <= 3'h0;
        else begin
            case (ua_state)
                3'h0:   if (rxq1==0) ua_state <= 3'h1;  // if rxd==0 then goto next state and enable clock                                               // start bit search
                3'h1:   if (clk_ctr_equ15) ua_state <= 3'h2;                                    // start bit receive
                3'h2:   if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;
                3'h3:   if (clk_ctr_equ15)     ua_state <=3'h4;                                                                 // stop bit receive
                3'h4:   ua_state <= 3'b000;
                default: ua_state <= 3'b000;
            endcase
        end
    end
 
 
    //reg_we
    always @(posedge clk ) begin
        if (~sync_reset)                           buffer_reg<=8'h00;
        else if (ua_state==3'h3 && clk_ctr_equ0)  buffer_reg<=rx_sr;
    end
 
    //int_req
    always @(posedge clk ) begin
        if (~sync_reset)                            int_req<=1'b0;
        else if (ua_state==3'h4 )   int_req<=1'b1;
        else                                        int_req<=1'b0;
    end
 
 
    // rx shift reg.
    always @(posedge clk ) begin
        if (~sync_reset) rx_sr <= 0;
        else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
    end
 
endmodule

Line No.	Rev	Author	Line
1	35	mcupro	`/******************************************************************`
2			`* *`
3			`* Author: Liwei *`
4			`* *`
5			`* This file is part of the "mips789" project. *`
6			`* Downloaded from: *`
7			`* http://www.opencores.org/pdownloads.cgi/list/mips789 *`
8			`* *`
9			`* If you encountered any problem, please contact me via *`
10			`* Email:mcupro@opencores.org or mcupro@163.com *`
11			`* *`
12			`******************************************************************/`
13	10	mcupro
14	35	mcupro	`include "mips789_defs.v"
15
16	10	mcupro	`module rxd_d(input clr,input clk,input d,output reg q );`
17
18	35	mcupro	`always @(posedge clk)`
19	10	mcupro
20			`if (clr) q<=0;`
21			`else q<=d\|q;`
22
23			`endmodule`
24
25			`module uart0 (`
26			`clk,rst,rxd_ft,ser_rxd,txd_ld,`
27			`din,rxd_rdy,ser_txd,txd_busy,dout) ;`
28			`input clk;`
29			`wire clk;`
30			`input rst;`
31			`wire rst;`
32			`input rxd_ft;`
33			`wire rxd_ft;`
34			`input ser_rxd;`
35			`wire ser_rxd;`
36			`input txd_ld;`
37			`wire txd_ld;`
38			`input [7:0] din;`
39			`wire [7:0] din;`
40			`output rxd_rdy;`
41			`wire rxd_rdy;`
42			`output ser_txd;`
43			`wire ser_txd;`
44			`output txd_busy;`
45			`wire txd_busy;`
46			`output [7:0] dout;`
47			`wire [7:0] dout;`
48
49			`wire clk_uart=clk;`
50			`wire w_rxd_rdy;`
51
52			`uart_read uart_rd_tak(`
53			`.sync_reset(rst),`
54			`.clk(clk),`
55			`.rxd(ser_rxd),`
56			`.buffer_reg(dout),`
57			`.int_req(w_rxd_rdy)`
58			`);`
59
60			`rxd_d rxd_rdy_hold_lw`
61			`(`
62			`.clk(clk_uart),`
63			`.clr(rxd_ft),`
64			`.d(w_rxd_rdy),`
65			`.q(rxd_rdy)`
66			`);`
67
68			`uart_write uart_txd`
69			`(`
70			`.sync_reset(rst),`
71			`.clk(clk),`
72			`.txd(ser_txd),`
73			`.data_in(din) ,`
74			`.write_request(txd_ld),`
75			`//.write_done(),`
76			`.write_busy(txd_busy)`
77			`);`
78
79			`endmodule`
80
81	35	mcupro	`//These modules below are modified slight by Liwei based on YACC,an CPU core in opencores.`
82			`//Thank you TAK`
83	10	mcupro
84			`module uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy);`
85			`input sync_reset,clk;`
86			`input [7:0] data_in;`
87			`input write_request;`
88			`output txd,write_done;`
89			`output write_busy;`
90
91
92
93			`wire queue_full;`
94			`wire queing, read_request;`
95			`wire [7:0] queue_data;`
96			`reg read_request_ff;`
97
98
99			`//________\|--\|___write_request (upper module : its period should be 1clock time.)`
100			`//__________________________\|-\|______write_done (Responds by this module posedge interrupt)`
101			`//With 512Bytes FIFO.`
102			`//No error handling is supported.`
103
104	35	mcupro	`reg [15:0] clk_ctr;//liwei`
105	10	mcupro	`reg [2:0] bit_ctr;`
106			`reg [2:0] ua_state;`
107			`reg [7:0] tx_sr;`
108			`reg txd;`
109
110			`wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,`
111			`clk_ctr_enable_state, bit_ctr_enable_state ;`
112			`wire tx_state;`
113			`wire empty;`
114			`assign write_busy=queue_full;//Apr.2.2005`
115
116			`always @ (posedge clk) begin`
117	15	mcupro	`if (~sync_reset) read_request_ff<=1'b0;`
118	10	mcupro	`else read_request_ff<=read_request;`
119			`end`
120
121			`assign queing= !empty;`
122			`assign read_request = queing && ua_state==3'b000;//Jul.14.2004`
123
124			`assign write_done=ua_state==3'b101;`
125
126			`ifdef ALTERA
127	35	mcupro	`fifo512_cyclone alt_fifo(`
128	10	mcupro	`.data(data_in),`
129			`.wrreq(write_request),`
130			`.rdreq(read_request),`
131			`.clock(clk),`
132			`.q(queue_data),`
133			`.full(queue_full),`
134			`.empty(empty));`
135	35	mcupro	`else//debug model in simulations
136	10	mcupro
137	35	mcupro	`sim_fifo512_cyclone sim_fifo(`
138			`.data(data_in),`
139			`.wrreq(write_request),`
140			`.rdreq(read_request),`
141			`.clock(clk),`
142			`.q(queue_data),`
143			`.full(queue_full),`
144			`.empty(empty),`
145			`.rst(sync_reset));`
146	10	mcupro	`endif
147
148
149
150			`// 7bit counter`
151	35	mcupro	`// I set the regerster lenth as 16 .Sufficent but not waste.Liwei`
152	10	mcupro	`always @(posedge clk ) begin`
153	15	mcupro	`if (~sync_reset)`
154	10	mcupro	`clk_ctr <= 0;`
155			`else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;`
156			`else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;`
157			`else clk_ctr <= 0;`
158			`end`
159
160
161			assign clk_ctr_equ15 = clk_ctr==`COUNTER_VALUE1;
162			assign clk_ctr_equ31 = clk_ctr==`COUNTER_VALUE2;
163
164			`// 3bit counter`
165			`always @(posedge clk) begin`
166	15	mcupro	`if (~sync_reset)`
167	10	mcupro	`bit_ctr <= 0;`
168			`else if (bit_ctr_enable_state) begin`
169			`if (clk_ctr_equ15)`
170			`bit_ctr <= bit_ctr + 1;`
171			`end`
172			`else`
173			`bit_ctr <= 0;`
174			`end`
175
176			`assign bit_ctr_equ7 = (bit_ctr==7);`
177
178			`assign clk_ctr_enable_state = bit_ctr_enable_state \|\|ua_state==3'b110 \|\| ua_state==3'b001 \|\| ua_state==3'b100\|\|ua_state==3'b101;`
179			`assign bit_ctr_enable_state = ua_state==3'b010 \|\| ua_state==3'b011;`
180
181
182			`always @(posedge clk ) begin`
183	15	mcupro	`if (~sync_reset) ua_state <= 3'b000;`
184	10	mcupro	`else begin`
185			`case (ua_state)`
186			`3'b000: if (queing) ua_state <= 3'b001; //wait write_request`
187			`3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit`
188			`3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send`
189			`3'b011: if (clk_ctr_equ15) ua_state <= 3'b100; // bit7 data send`
190			`3'b100: if (clk_ctr_equ15) ua_state <= 3'b101; // stop bit // stop bit send`
191	35	mcupro	`3'b101: if (clk_ctr_equ15) ua_state <= 3'b110; //LIWEI // stop bit send`
192	10	mcupro	`3'b110: if (clk_ctr_equ15) ua_state <= 3'b111; //LIWEI`
193			`3'b111: ua_state <= 3'h0; // TAK // byte read cycle end`
194			`default: ua_state <= 3'h0;`
195			`endcase`
196			`end`
197			`end`
198
199
200
201
202			`// tx shift reg.`
203			`always @(posedge clk ) begin`
204	15	mcupro	`if (~sync_reset) tx_sr<=0;`
205	10	mcupro	`else if (read_request_ff) tx_sr <= queue_data[7:0]; //data_in[7:0]; // load`
206			`else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]};`
207			`end`
208
209			`assign tx_state=( ua_state==3'h2 \|\| ua_state==3'h3) && clk_ctr_equ15;`
210
211
212			`// tx`
213			`always @(posedge clk ) begin`
214	15	mcupro	`if (~sync_reset) txd <=1'b1;`
215			`else if (~sync_reset) txd<=1'b1;`
216	10	mcupro	`else if (ua_state==3'h0) txd<=1'b1;`
217			`else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0; // start bit`
218			`else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0];`
219			`else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1; // stop bit`
220			`end`
221			`endmodule`
222
223
224			`module uart_read( sync_reset, clk, rxd,buffer_reg, int_req);`
225			`input sync_reset;`
226			`input clk, rxd;`
227			`output [7:0] buffer_reg;`
228			`output int_req;`
229
230
231			`//________\|-\|______int_req (This module,, posedge interrupt)`
232			`//`
233			`//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time...`
234			`//`
235			`//No error handling (overrun ) is supported.`
236
237			`reg rxq1;`
238			`reg [15:0] clk_ctr;`
239			`reg [2:0] bit_ctr;`
240			`reg [2:0] ua_state;`
241			`reg [7:0] rx_sr; //.,tx_sr;`
242			`reg int_req;`
243			`reg [7:0] buffer_reg;`
244
245			`wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,`
246			`clk_ctr_enable_state, bit_ctr_enable_state ;`
247			`wire clk_ctr_equ0;`
248
249			`//sync_reset`
250
251			`//synchronization`
252			`always @(posedge clk ) begin`
253			`rxq1 <=rxd ;`
254			`end`
255
256			`// 7bit counter`
257			`always @(posedge clk ) begin`
258	15	mcupro	`if (~sync_reset)`
259	10	mcupro	`clk_ctr <= 0;`
260			`else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;`
261			`else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;`
262			`else clk_ctr <= 0;`
263			`end`
264			assign clk_ctr_equ15 = (clk_ctr==`COUNTER_VALUE1) ;//
265			assign clk_ctr_equ31 = (clk_ctr==`COUNTER_VALUE2) ;//
266			assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); //
267
268
269			`// 3bit counter`
270			`always @(posedge clk) begin`
271	15	mcupro	`if (~sync_reset)`
272	10	mcupro	`bit_ctr <= 0;`
273			`else if (bit_ctr_enable_state) begin`
274			`if (clk_ctr_equ15)`
275			`bit_ctr <= bit_ctr + 1;`
276			`end`
277			`else`
278			`bit_ctr <= 0;`
279			`end`
280
281			`assign bit_ctr_equ7 = (bit_ctr==7);`
282
283
284			`assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;`
285			`assign bit_ctr_enable_state = ua_state==3'h2;`
286
287			`always @(posedge clk ) begin`
288	15	mcupro	`if (~sync_reset) ua_state <= 3'h0;`
289	10	mcupro	`else begin`
290			`case (ua_state)`
291			`3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search`
292			`3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive`
293			`3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;`
294			`3'h3: if (clk_ctr_equ15) ua_state <=3'h4; // stop bit receive`
295			`3'h4: ua_state <= 3'b000;`
296			`default: ua_state <= 3'b000;`
297			`endcase`
298			`end`
299			`end`
300
301
302			`//reg_we`
303			`always @(posedge clk ) begin`
304	15	mcupro	`if (~sync_reset) buffer_reg<=8'h00;`
305	10	mcupro	`else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr;`
306			`end`
307
308			`//int_req`
309			`always @(posedge clk ) begin`
310	15	mcupro	`if (~sync_reset) int_req<=1'b0;`
311	35	mcupro	`else if (ua_state==3'h4 ) int_req<=1'b1;`
312	10	mcupro	`else int_req<=1'b0;`
313			`end`
314
315
316			`// rx shift reg.`
317			`always @(posedge clk ) begin`
318	15	mcupro	`if (~sync_reset) rx_sr <= 0;`
319	10	mcupro	`else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};`
320			`end`
321
322			`endmodule`

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