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mcupro |
#
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# Synplicity Verification Interface File
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# Generated using Synplify-pro
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#
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# Copyright (c) 1996-2005 Synplicity, Inc.
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# All rights reserved
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#
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# Set logfile options
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vif_set_result_file mips_core.vlf
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# Set technology for TCL script
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vif_set_technology -architecture FPGA -vendor Altera
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# RTL and technology files
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vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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vif_add_file -original -verilog ../../rtl/verilog/ctl_fsm.v
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| 18 |
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vif_add_file -original -verilog ../../rtl/verilog/decode_pipe.v
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| 19 |
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vif_add_file -original -verilog ../../rtl/verilog/dvc.v
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| 20 |
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vif_add_file -original -verilog ../../rtl/verilog/EXEC_stage.v
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| 21 |
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vif_add_file -original -verilog ../../rtl/verilog/fifo.v
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| 22 |
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vif_add_file -original -verilog ../../rtl/verilog/forward.v
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| 23 |
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vif_add_file -original -verilog ../../rtl/verilog/mem_module.v
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| 24 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_core.v
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vif_add_file -original -verilog ../../rtl/verilog/mips_dvc.v
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| 26 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_sys.v
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| 27 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_uart.v
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| 28 |
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vif_add_file -original -verilog ../../rtl/verilog/ram_module.v
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| 29 |
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vif_add_file -original -verilog ../../rtl/verilog/RF_components.v
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vif_add_file -original -verilog ../../rtl/verilog/RF_stage.v
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| 31 |
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vif_add_file -original -verilog ../../rtl/verilog/sim_ram.v
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vif_add_file -original -verilog ../../rtl/verilog/tools.v
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vif_add_file -original -verilog ../../rtl/verilog/fifo512_cyclone.v
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vif_set_top_module -original -top mips_core
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vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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vif_add_file -translated -verilog mips_core.vqm
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vif_set_top_module -translated -top mips_core
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# Read FSM encoding
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vif_set_fsm -fsm fsm_0
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vif_set_fsmreg -original -fsm fsm_0 iRF_stage/MIAN_FSM/CurrState_Sreg0[3:0]
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| 42 |
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vif_set_fsmreg -translated -fsm fsm_0 iRF_stage/MIAN_FSM/CurrState_Sreg0[8:0]
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| 43 |
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vif_set_state_map -fsm fsm_0 -original "0000" -translated "000000001"
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| 44 |
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vif_set_state_map -fsm fsm_0 -original "0001" -translated "000000010"
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| 45 |
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vif_set_state_map -fsm fsm_0 -original "0010" -translated "000000100"
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| 46 |
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vif_set_state_map -fsm fsm_0 -original "0011" -translated "000001000"
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| 47 |
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vif_set_state_map -fsm fsm_0 -original "0100" -translated "000010000"
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| 48 |
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vif_set_state_map -fsm fsm_0 -original "0101" -translated "000100000"
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| 49 |
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vif_set_state_map -fsm fsm_0 -original "0110" -translated "001000000"
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| 50 |
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vif_set_state_map -fsm fsm_0 -original "0111" -translated "010000000"
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| 51 |
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vif_set_state_map -fsm fsm_0 -original "1000" -translated "100000000"
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| 52 |
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| 53 |
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# Memory map points
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| 54 |
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| 55 |
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# SRL map points
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| 56 |
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| 57 |
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# Compiler constant registers
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| 58 |
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| 59 |
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# Compiler constant latches
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| 60 |
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| 61 |
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# Compiler RTL sequential redundancies
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| 62 |
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| 63 |
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# RTL sequential redundancies
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| 64 |
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vif_set_merge -original iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged iexec_stage/MIPS_alu/muldiv_ff/op2_reged[32]
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| 65 |
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vif_set_merge -original alu_pass0/r32_o[0] MEM_CTL/dmem_ctl_post/byte_addr_o[0]
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| 66 |
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vif_set_merge -original alu_pass0/r32_o[1] MEM_CTL/dmem_ctl_post/byte_addr_o[1]
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| 67 |
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| 68 |
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# Technology sequential redundancies
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| 69 |
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| 70 |
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# Inversion map points
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| 71 |
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vif_set_map_point -register -inverted -original iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z
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| 72 |
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| 73 |
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# Port mappping and directions
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| 74 |
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| 75 |
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# Black box mapping
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| 76 |
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vif_set_black_box synplicity_altsyncram4_r_w
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| 77 |
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| 78 |
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vif_set_map_point -blackbox -original iRF_stage/reg_bank/reg_bank/altsyncram -translated iRF_stage/reg_bank/reg_bank.I_1
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| 79 |
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vif_set_map_point -blackbox -original iRF_stage/reg_bank/reg_bank_1/altsyncram -translated iRF_stage/reg_bank/reg_bank_1.I_1
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| 80 |
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| 81 |
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# Other sequential cells, including multidimensional arrays
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| 82 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[7] -translated MEM_CTL/i_mem_dout_ctl/dout_1_7__Z
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| 83 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[6] -translated MEM_CTL/i_mem_dout_ctl/dout_1_6__Z
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| 84 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[5] -translated MEM_CTL/i_mem_dout_ctl/dout_1_5__Z
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| 85 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[4] -translated MEM_CTL/i_mem_dout_ctl/dout_1_4__Z
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| 86 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[3] -translated MEM_CTL/i_mem_dout_ctl/dout_1_3__Z
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| 87 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[2] -translated MEM_CTL/i_mem_dout_ctl/dout_1_2__Z
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| 88 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[1] -translated MEM_CTL/i_mem_dout_ctl/dout_1_1__Z
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| 89 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[0] -translated MEM_CTL/i_mem_dout_ctl/dout_1_0__Z
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| 90 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[15] -translated MEM_CTL/i_mem_dout_ctl/dout_1_15__Z
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| 91 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[14] -translated MEM_CTL/i_mem_dout_ctl/dout_1_14__Z
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| 92 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[13] -translated MEM_CTL/i_mem_dout_ctl/dout_1_13__Z
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| 93 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[12] -translated MEM_CTL/i_mem_dout_ctl/dout_1_12__Z
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| 94 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[11] -translated MEM_CTL/i_mem_dout_ctl/dout_1_11__Z
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| 95 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[10] -translated MEM_CTL/i_mem_dout_ctl/dout_1_10__Z
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| 96 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[9] -translated MEM_CTL/i_mem_dout_ctl/dout_1_9__Z
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| 97 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[8] -translated MEM_CTL/i_mem_dout_ctl/dout_1_8__Z
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| 98 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[31] -translated MEM_CTL/i_mem_dout_ctl/dout_1_31__Z
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| 99 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[30] -translated MEM_CTL/i_mem_dout_ctl/dout_1_30__Z
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| 100 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[29] -translated MEM_CTL/i_mem_dout_ctl/dout_1_29__Z
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| 101 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[28] -translated MEM_CTL/i_mem_dout_ctl/dout_1_28__Z
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| 102 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[27] -translated MEM_CTL/i_mem_dout_ctl/dout_1_27__Z
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| 103 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[26] -translated MEM_CTL/i_mem_dout_ctl/dout_1_26__Z
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| 104 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[25] -translated MEM_CTL/i_mem_dout_ctl/dout_1_25__Z
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| 105 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[24] -translated MEM_CTL/i_mem_dout_ctl/dout_1_24__Z
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| 106 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[23] -translated MEM_CTL/i_mem_dout_ctl/dout_1_23__Z
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| 107 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[22] -translated MEM_CTL/i_mem_dout_ctl/dout_1_22__Z
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| 108 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[21] -translated MEM_CTL/i_mem_dout_ctl/dout_1_21__Z
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| 109 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[20] -translated MEM_CTL/i_mem_dout_ctl/dout_1_20__Z
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| 110 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[19] -translated MEM_CTL/i_mem_dout_ctl/dout_1_19__Z
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| 111 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[18] -translated MEM_CTL/i_mem_dout_ctl/dout_1_18__Z
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| 112 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[17] -translated MEM_CTL/i_mem_dout_ctl/dout_1_17__Z
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| 113 |
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vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[16] -translated MEM_CTL/i_mem_dout_ctl/dout_1_16__Z
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| 114 |
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vif_set_map_point -latch -original decoder_pipe/idecoder/fsm_dly[2] -translated decoder_pipe/idecoder/fsm_dly_1_2__Z
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| 115 |
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vif_set_map_point -latch -original decoder_pipe/idecoder/fsm_dly[1] -translated decoder_pipe/idecoder/fsm_dly_1_1__Z
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| 116 |
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| 117 |
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# Constant Registers
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| 118 |
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| 119 |
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# Retimed Registers
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| 120 |
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vif_set_sequential_verify -retimed -register -original MEM_CTL/dmem_ctl_post/ctl_o[0] -translated MEM_CTL/dmem_ctl_post/ctl_o_0__Z
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| 121 |
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vif_set_sequential_verify -retimed -register -original MEM_CTL/dmem_ctl_post/ctl_o[1] -translated MEM_CTL/dmem_ctl_post/ctl_o_1__Z
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| 122 |
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vif_set_sequential_verify -retimed -register -original MEM_CTL/dmem_ctl_post/ctl_o[2] -translated MEM_CTL/dmem_ctl_post/ctl_o_2__Z
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| 123 |
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vif_set_sequential_verify -retimed -register -original MEM_CTL/dmem_ctl_post/ctl_o[3] -translated MEM_CTL/dmem_ctl_post/ctl_o_3__Z
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| 124 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/delay_counter_Sreg0[2] -translated iRF_stage/MIAN_FSM/delay_counter_Sreg0_2__Z
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| 125 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/delay_counter_Sreg0[3] -translated iRF_stage/MIAN_FSM/delay_counter_Sreg0_3__Z
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| 126 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/delay_counter_Sreg0[4] -translated iRF_stage/MIAN_FSM/delay_counter_Sreg0_4__Z
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| 127 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/delay_counter_Sreg0[5] -translated iRF_stage/MIAN_FSM/delay_counter_Sreg0_5__Z
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| 128 |
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# Retimed registers from FSM not handled in VIF
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| 129 |
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//vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z
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| 130 |
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# Retimed registers from FSM not handled in VIF
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| 131 |
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//vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/CurrState_Sreg0[6] -translated iRF_stage/MIAN_FSM/CurrState_Sreg0_6__Z
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| 132 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[24] -translated iRF_stage/ins_reg/r32_o_24__Z
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| 133 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[23] -translated iRF_stage/ins_reg/r32_o_23__Z
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| 134 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[20] -translated iRF_stage/ins_reg/r32_o_20__Z
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| 135 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[19] -translated iRF_stage/ins_reg/r32_o_19__Z
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| 136 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[16] -translated iRF_stage/ins_reg/r32_o_16__Z
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| 137 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[15] -translated iRF_stage/ins_reg/r32_o_15__Z
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| 138 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[12] -translated iRF_stage/ins_reg/r32_o_12__Z
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| 139 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[11] -translated iRF_stage/ins_reg/r32_o_11__Z
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| 140 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[8] -translated iRF_stage/ins_reg/r32_o_8__Z
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| 141 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[7] -translated iRF_stage/ins_reg/r32_o_7__Z
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| 142 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[4] -translated iRF_stage/ins_reg/r32_o_4__Z
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| 143 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[3] -translated iRF_stage/ins_reg/r32_o_3__Z
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| 144 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[0] -translated iRF_stage/ins_reg/r32_o_0__Z
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| 145 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[25] -translated iRF_stage/ins_reg/r32_o_25__Z
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| 146 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[22] -translated iRF_stage/ins_reg/r32_o_22__Z
|
| 147 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[21] -translated iRF_stage/ins_reg/r32_o_21__Z
|
| 148 |
|
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[18] -translated iRF_stage/ins_reg/r32_o_18__Z
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| 149 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[17] -translated iRF_stage/ins_reg/r32_o_17__Z
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| 150 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[14] -translated iRF_stage/ins_reg/r32_o_14__Z
|
| 151 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[13] -translated iRF_stage/ins_reg/r32_o_13__Z
|
| 152 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[10] -translated iRF_stage/ins_reg/r32_o_10__Z
|
| 153 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[9] -translated iRF_stage/ins_reg/r32_o_9__Z
|
| 154 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[6] -translated iRF_stage/ins_reg/r32_o_6__Z
|
| 155 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[5] -translated iRF_stage/ins_reg/r32_o_5__Z
|
| 156 |
|
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[2] -translated iRF_stage/ins_reg/r32_o_2__Z
|
| 157 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[1] -translated iRF_stage/ins_reg/r32_o_1__Z
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| 158 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wren -translated iRF_stage/reg_bank/r_wren_Z
|
| 159 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[0] -translated iRF_stage/reg_bank/r_rdaddress_a_0__Z
|
| 160 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[1] -translated iRF_stage/reg_bank/r_rdaddress_a_1__Z
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| 161 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[2] -translated iRF_stage/reg_bank/r_rdaddress_a_2__Z
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| 162 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[3] -translated iRF_stage/reg_bank/r_rdaddress_a_3__Z
|
| 163 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[4] -translated iRF_stage/reg_bank/r_rdaddress_a_4__Z
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| 164 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[0] -translated iRF_stage/reg_bank/r_rdaddress_b_0__Z
|
| 165 |
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vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[1] -translated iRF_stage/reg_bank/r_rdaddress_b_1__Z
|
| 166 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[2] -translated iRF_stage/reg_bank/r_rdaddress_b_2__Z
|
| 167 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[3] -translated iRF_stage/reg_bank/r_rdaddress_b_3__Z
|
| 168 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[4] -translated iRF_stage/reg_bank/r_rdaddress_b_4__Z
|
| 169 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[0] -translated iRF_stage/reg_bank/r_data_0__Z
|
| 170 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[1] -translated iRF_stage/reg_bank/r_data_1__Z
|
| 171 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[2] -translated iRF_stage/reg_bank/r_data_2__Z
|
| 172 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[3] -translated iRF_stage/reg_bank/r_data_3__Z
|
| 173 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[4] -translated iRF_stage/reg_bank/r_data_4__Z
|
| 174 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[5] -translated iRF_stage/reg_bank/r_data_5__Z
|
| 175 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[6] -translated iRF_stage/reg_bank/r_data_6__Z
|
| 176 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[7] -translated iRF_stage/reg_bank/r_data_7__Z
|
| 177 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[8] -translated iRF_stage/reg_bank/r_data_8__Z
|
| 178 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[9] -translated iRF_stage/reg_bank/r_data_9__Z
|
| 179 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[10] -translated iRF_stage/reg_bank/r_data_10__Z
|
| 180 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[11] -translated iRF_stage/reg_bank/r_data_11__Z
|
| 181 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[12] -translated iRF_stage/reg_bank/r_data_12__Z
|
| 182 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[13] -translated iRF_stage/reg_bank/r_data_13__Z
|
| 183 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[14] -translated iRF_stage/reg_bank/r_data_14__Z
|
| 184 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[15] -translated iRF_stage/reg_bank/r_data_15__Z
|
| 185 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[16] -translated iRF_stage/reg_bank/r_data_16__Z
|
| 186 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[17] -translated iRF_stage/reg_bank/r_data_17__Z
|
| 187 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[18] -translated iRF_stage/reg_bank/r_data_18__Z
|
| 188 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[19] -translated iRF_stage/reg_bank/r_data_19__Z
|
| 189 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[20] -translated iRF_stage/reg_bank/r_data_20__Z
|
| 190 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[21] -translated iRF_stage/reg_bank/r_data_21__Z
|
| 191 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[22] -translated iRF_stage/reg_bank/r_data_22__Z
|
| 192 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[23] -translated iRF_stage/reg_bank/r_data_23__Z
|
| 193 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[24] -translated iRF_stage/reg_bank/r_data_24__Z
|
| 194 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[25] -translated iRF_stage/reg_bank/r_data_25__Z
|
| 195 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[26] -translated iRF_stage/reg_bank/r_data_26__Z
|
| 196 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[27] -translated iRF_stage/reg_bank/r_data_27__Z
|
| 197 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[28] -translated iRF_stage/reg_bank/r_data_28__Z
|
| 198 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[29] -translated iRF_stage/reg_bank/r_data_29__Z
|
| 199 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[30] -translated iRF_stage/reg_bank/r_data_30__Z
|
| 200 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[31] -translated iRF_stage/reg_bank/r_data_31__Z
|
| 201 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[0] -translated iRF_stage/reg_bank/r_wraddress_0__Z
|
| 202 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[1] -translated iRF_stage/reg_bank/r_wraddress_1__Z
|
| 203 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[2] -translated iRF_stage/reg_bank/r_wraddress_2__Z
|
| 204 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[3] -translated iRF_stage/reg_bank/r_wraddress_3__Z
|
| 205 |
|
|
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[4] -translated iRF_stage/reg_bank/r_wraddress_4__Z
|
| 206 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/add1 -translated iexec_stage/MIPS_alu/muldiv_ff/add1_Z
|
| 207 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/addop2 -translated iexec_stage/MIPS_alu/muldiv_ff/addop2_Z
|
| 208 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/addnop2 -translated iexec_stage/MIPS_alu/muldiv_ff/addnop2_Z
|
| 209 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/overflow -translated iexec_stage/MIPS_alu/muldiv_ff/overflow_Z
|
| 210 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/sub_or_yn -translated iexec_stage/MIPS_alu/muldiv_ff/sub_or_yn_Z
|
| 211 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/finish -translated iexec_stage/MIPS_alu/muldiv_ff/finish_Z
|
| 212 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged -translated iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged_Z
|
| 213 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op1_sign_reged -translated iexec_stage/MIPS_alu/muldiv_ff/op1_sign_reged_Z
|
| 214 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/start -translated iexec_stage/MIPS_alu/muldiv_ff/start_Z
|
| 215 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/sign -translated iexec_stage/MIPS_alu/muldiv_ff/sign_Z
|
| 216 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/mul -translated iexec_stage/MIPS_alu/muldiv_ff/mul_Z
|
| 217 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/rdy -translated iexec_stage/MIPS_alu/muldiv_ff/rdy_Z
|
| 218 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[0] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_0__Z
|
| 219 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[1] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_1__Z
|
| 220 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[2] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_2__Z
|
| 221 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[3] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_3__Z
|
| 222 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[4] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_4__Z
|
| 223 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[5] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_5__Z
|
| 224 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[6] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_6__Z
|
| 225 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[7] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_7__Z
|
| 226 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[8] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_8__Z
|
| 227 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[9] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_9__Z
|
| 228 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[10] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_10__Z
|
| 229 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[11] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_11__Z
|
| 230 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[12] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_12__Z
|
| 231 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[13] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_13__Z
|
| 232 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[14] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_14__Z
|
| 233 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[15] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_15__Z
|
| 234 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[16] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_16__Z
|
| 235 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[17] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_17__Z
|
| 236 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[18] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_18__Z
|
| 237 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[19] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_19__Z
|
| 238 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[20] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_20__Z
|
| 239 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[21] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_21__Z
|
| 240 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[22] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_22__Z
|
| 241 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[23] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_23__Z
|
| 242 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[24] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_24__Z
|
| 243 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[25] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_25__Z
|
| 244 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[26] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_26__Z
|
| 245 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[27] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_27__Z
|
| 246 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[28] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_28__Z
|
| 247 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[29] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_29__Z
|
| 248 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[30] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_30__Z
|
| 249 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[31] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_31__Z
|
| 250 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[2] -translated iexec_stage/pc_nxt/r32_o_2__Z
|
| 251 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[3] -translated iexec_stage/pc_nxt/r32_o_3__Z
|
| 252 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[4] -translated iexec_stage/pc_nxt/r32_o_4__Z
|
| 253 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[5] -translated iexec_stage/pc_nxt/r32_o_5__Z
|
| 254 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[6] -translated iexec_stage/pc_nxt/r32_o_6__Z
|
| 255 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[7] -translated iexec_stage/pc_nxt/r32_o_7__Z
|
| 256 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[8] -translated iexec_stage/pc_nxt/r32_o_8__Z
|
| 257 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[9] -translated iexec_stage/pc_nxt/r32_o_9__Z
|
| 258 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[10] -translated iexec_stage/pc_nxt/r32_o_10__Z
|
| 259 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[11] -translated iexec_stage/pc_nxt/r32_o_11__Z
|
| 260 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[12] -translated iexec_stage/pc_nxt/r32_o_12__Z
|
| 261 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[13] -translated iexec_stage/pc_nxt/r32_o_13__Z
|
| 262 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[14] -translated iexec_stage/pc_nxt/r32_o_14__Z
|
| 263 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[15] -translated iexec_stage/pc_nxt/r32_o_15__Z
|
| 264 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[16] -translated iexec_stage/pc_nxt/r32_o_16__Z
|
| 265 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[17] -translated iexec_stage/pc_nxt/r32_o_17__Z
|
| 266 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[18] -translated iexec_stage/pc_nxt/r32_o_18__Z
|
| 267 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[19] -translated iexec_stage/pc_nxt/r32_o_19__Z
|
| 268 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[20] -translated iexec_stage/pc_nxt/r32_o_20__Z
|
| 269 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[21] -translated iexec_stage/pc_nxt/r32_o_21__Z
|
| 270 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[22] -translated iexec_stage/pc_nxt/r32_o_22__Z
|
| 271 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[23] -translated iexec_stage/pc_nxt/r32_o_23__Z
|
| 272 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[24] -translated iexec_stage/pc_nxt/r32_o_24__Z
|
| 273 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[25] -translated iexec_stage/pc_nxt/r32_o_25__Z
|
| 274 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[26] -translated iexec_stage/pc_nxt/r32_o_26__Z
|
| 275 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[27] -translated iexec_stage/pc_nxt/r32_o_27__Z
|
| 276 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[28] -translated iexec_stage/pc_nxt/r32_o_28__Z
|
| 277 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[29] -translated iexec_stage/pc_nxt/r32_o_29__Z
|
| 278 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[30] -translated iexec_stage/pc_nxt/r32_o_30__Z
|
| 279 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[31] -translated iexec_stage/pc_nxt/r32_o_31__Z
|
| 280 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[1] -translated iexec_stage/pc_nxt/r32_o_1__Z
|
| 281 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[0] -translated iexec_stage/pc_nxt/r32_o_0__Z
|
| 282 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[0] -translated iexec_stage/spc/r32_o_0__Z
|
| 283 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[1] -translated iexec_stage/spc/r32_o_1__Z
|
| 284 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[2] -translated iexec_stage/spc/r32_o_2__Z
|
| 285 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[3] -translated iexec_stage/spc/r32_o_3__Z
|
| 286 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[4] -translated iexec_stage/spc/r32_o_4__Z
|
| 287 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[5] -translated iexec_stage/spc/r32_o_5__Z
|
| 288 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[6] -translated iexec_stage/spc/r32_o_6__Z
|
| 289 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[7] -translated iexec_stage/spc/r32_o_7__Z
|
| 290 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[8] -translated iexec_stage/spc/r32_o_8__Z
|
| 291 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[9] -translated iexec_stage/spc/r32_o_9__Z
|
| 292 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[10] -translated iexec_stage/spc/r32_o_10__Z
|
| 293 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[11] -translated iexec_stage/spc/r32_o_11__Z
|
| 294 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[12] -translated iexec_stage/spc/r32_o_12__Z
|
| 295 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[13] -translated iexec_stage/spc/r32_o_13__Z
|
| 296 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[14] -translated iexec_stage/spc/r32_o_14__Z
|
| 297 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[15] -translated iexec_stage/spc/r32_o_15__Z
|
| 298 |
|
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vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[16] -translated iexec_stage/spc/r32_o_16__Z
|
| 299 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[17] -translated iexec_stage/spc/r32_o_17__Z
|
| 300 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[18] -translated iexec_stage/spc/r32_o_18__Z
|
| 301 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[19] -translated iexec_stage/spc/r32_o_19__Z
|
| 302 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[20] -translated iexec_stage/spc/r32_o_20__Z
|
| 303 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[21] -translated iexec_stage/spc/r32_o_21__Z
|
| 304 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[22] -translated iexec_stage/spc/r32_o_22__Z
|
| 305 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[23] -translated iexec_stage/spc/r32_o_23__Z
|
| 306 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[24] -translated iexec_stage/spc/r32_o_24__Z
|
| 307 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[25] -translated iexec_stage/spc/r32_o_25__Z
|
| 308 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[26] -translated iexec_stage/spc/r32_o_26__Z
|
| 309 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[27] -translated iexec_stage/spc/r32_o_27__Z
|
| 310 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[28] -translated iexec_stage/spc/r32_o_28__Z
|
| 311 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[29] -translated iexec_stage/spc/r32_o_29__Z
|
| 312 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[30] -translated iexec_stage/spc/r32_o_30__Z
|
| 313 |
|
|
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[31] -translated iexec_stage/spc/r32_o_31__Z
|
| 314 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[0] -translated alu_pass0/r32_o_0__Z
|
| 315 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[1] -translated alu_pass0/r32_o_1__Z
|
| 316 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[2] -translated alu_pass0/r32_o_2__Z
|
| 317 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[3] -translated alu_pass0/r32_o_3__Z
|
| 318 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[4] -translated alu_pass0/r32_o_4__Z
|
| 319 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[5] -translated alu_pass0/r32_o_5__Z
|
| 320 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[6] -translated alu_pass0/r32_o_6__Z
|
| 321 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[7] -translated alu_pass0/r32_o_7__Z
|
| 322 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[8] -translated alu_pass0/r32_o_8__Z
|
| 323 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[9] -translated alu_pass0/r32_o_9__Z
|
| 324 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[10] -translated alu_pass0/r32_o_10__Z
|
| 325 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[11] -translated alu_pass0/r32_o_11__Z
|
| 326 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[12] -translated alu_pass0/r32_o_12__Z
|
| 327 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[13] -translated alu_pass0/r32_o_13__Z
|
| 328 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[14] -translated alu_pass0/r32_o_14__Z
|
| 329 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[15] -translated alu_pass0/r32_o_15__Z
|
| 330 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[16] -translated alu_pass0/r32_o_16__Z
|
| 331 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[17] -translated alu_pass0/r32_o_17__Z
|
| 332 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[18] -translated alu_pass0/r32_o_18__Z
|
| 333 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[19] -translated alu_pass0/r32_o_19__Z
|
| 334 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[20] -translated alu_pass0/r32_o_20__Z
|
| 335 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[21] -translated alu_pass0/r32_o_21__Z
|
| 336 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[22] -translated alu_pass0/r32_o_22__Z
|
| 337 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[23] -translated alu_pass0/r32_o_23__Z
|
| 338 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[24] -translated alu_pass0/r32_o_24__Z
|
| 339 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[25] -translated alu_pass0/r32_o_25__Z
|
| 340 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[26] -translated alu_pass0/r32_o_26__Z
|
| 341 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[27] -translated alu_pass0/r32_o_27__Z
|
| 342 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[28] -translated alu_pass0/r32_o_28__Z
|
| 343 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[29] -translated alu_pass0/r32_o_29__Z
|
| 344 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[30] -translated alu_pass0/r32_o_30__Z
|
| 345 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[31] -translated alu_pass0/r32_o_31__Z
|
| 346 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[0] -translated alu_pass1/r32_o_0__Z
|
| 347 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[1] -translated alu_pass1/r32_o_1__Z
|
| 348 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[2] -translated alu_pass1/r32_o_2__Z
|
| 349 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[3] -translated alu_pass1/r32_o_3__Z
|
| 350 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[4] -translated alu_pass1/r32_o_4__Z
|
| 351 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[5] -translated alu_pass1/r32_o_5__Z
|
| 352 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[6] -translated alu_pass1/r32_o_6__Z
|
| 353 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[7] -translated alu_pass1/r32_o_7__Z
|
| 354 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[8] -translated alu_pass1/r32_o_8__Z
|
| 355 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[9] -translated alu_pass1/r32_o_9__Z
|
| 356 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[10] -translated alu_pass1/r32_o_10__Z
|
| 357 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[11] -translated alu_pass1/r32_o_11__Z
|
| 358 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[12] -translated alu_pass1/r32_o_12__Z
|
| 359 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[13] -translated alu_pass1/r32_o_13__Z
|
| 360 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[14] -translated alu_pass1/r32_o_14__Z
|
| 361 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[15] -translated alu_pass1/r32_o_15__Z
|
| 362 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[16] -translated alu_pass1/r32_o_16__Z
|
| 363 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[17] -translated alu_pass1/r32_o_17__Z
|
| 364 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[18] -translated alu_pass1/r32_o_18__Z
|
| 365 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[19] -translated alu_pass1/r32_o_19__Z
|
| 366 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[20] -translated alu_pass1/r32_o_20__Z
|
| 367 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[21] -translated alu_pass1/r32_o_21__Z
|
| 368 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[22] -translated alu_pass1/r32_o_22__Z
|
| 369 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[23] -translated alu_pass1/r32_o_23__Z
|
| 370 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[24] -translated alu_pass1/r32_o_24__Z
|
| 371 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[25] -translated alu_pass1/r32_o_25__Z
|
| 372 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[26] -translated alu_pass1/r32_o_26__Z
|
| 373 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[27] -translated alu_pass1/r32_o_27__Z
|
| 374 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[28] -translated alu_pass1/r32_o_28__Z
|
| 375 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[29] -translated alu_pass1/r32_o_29__Z
|
| 376 |
|
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vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[30] -translated alu_pass1/r32_o_30__Z
|
| 377 |
|
|
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[31] -translated alu_pass1/r32_o_31__Z
|
| 378 |
|
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vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[0] -translated cop_data_reg/r32_o_0__Z
|
| 379 |
|
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vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[1] -translated cop_data_reg/r32_o_1__Z
|
| 380 |
|
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vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[2] -translated cop_data_reg/r32_o_2__Z
|
| 381 |
|
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vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[3] -translated cop_data_reg/r32_o_3__Z
|
| 382 |
|
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vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[4] -translated cop_data_reg/r32_o_4__Z
|
| 383 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[5] -translated cop_data_reg/r32_o_5__Z
|
| 384 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[6] -translated cop_data_reg/r32_o_6__Z
|
| 385 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[7] -translated cop_data_reg/r32_o_7__Z
|
| 386 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[8] -translated cop_data_reg/r32_o_8__Z
|
| 387 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[9] -translated cop_data_reg/r32_o_9__Z
|
| 388 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[10] -translated cop_data_reg/r32_o_10__Z
|
| 389 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[11] -translated cop_data_reg/r32_o_11__Z
|
| 390 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[12] -translated cop_data_reg/r32_o_12__Z
|
| 391 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[13] -translated cop_data_reg/r32_o_13__Z
|
| 392 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[14] -translated cop_data_reg/r32_o_14__Z
|
| 393 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[15] -translated cop_data_reg/r32_o_15__Z
|
| 394 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[16] -translated cop_data_reg/r32_o_16__Z
|
| 395 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[17] -translated cop_data_reg/r32_o_17__Z
|
| 396 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[18] -translated cop_data_reg/r32_o_18__Z
|
| 397 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[19] -translated cop_data_reg/r32_o_19__Z
|
| 398 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[20] -translated cop_data_reg/r32_o_20__Z
|
| 399 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[21] -translated cop_data_reg/r32_o_21__Z
|
| 400 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[22] -translated cop_data_reg/r32_o_22__Z
|
| 401 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[23] -translated cop_data_reg/r32_o_23__Z
|
| 402 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[24] -translated cop_data_reg/r32_o_24__Z
|
| 403 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[25] -translated cop_data_reg/r32_o_25__Z
|
| 404 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[26] -translated cop_data_reg/r32_o_26__Z
|
| 405 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[27] -translated cop_data_reg/r32_o_27__Z
|
| 406 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[28] -translated cop_data_reg/r32_o_28__Z
|
| 407 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[29] -translated cop_data_reg/r32_o_29__Z
|
| 408 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[30] -translated cop_data_reg/r32_o_30__Z
|
| 409 |
|
|
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[31] -translated cop_data_reg/r32_o_31__Z
|
| 410 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[0] -translated cop_dout_reg/r32_o_0__Z
|
| 411 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[1] -translated cop_dout_reg/r32_o_1__Z
|
| 412 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[2] -translated cop_dout_reg/r32_o_2__Z
|
| 413 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[3] -translated cop_dout_reg/r32_o_3__Z
|
| 414 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[4] -translated cop_dout_reg/r32_o_4__Z
|
| 415 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[5] -translated cop_dout_reg/r32_o_5__Z
|
| 416 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[6] -translated cop_dout_reg/r32_o_6__Z
|
| 417 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[7] -translated cop_dout_reg/r32_o_7__Z
|
| 418 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[8] -translated cop_dout_reg/r32_o_8__Z
|
| 419 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[9] -translated cop_dout_reg/r32_o_9__Z
|
| 420 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[10] -translated cop_dout_reg/r32_o_10__Z
|
| 421 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[11] -translated cop_dout_reg/r32_o_11__Z
|
| 422 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[12] -translated cop_dout_reg/r32_o_12__Z
|
| 423 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[13] -translated cop_dout_reg/r32_o_13__Z
|
| 424 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[14] -translated cop_dout_reg/r32_o_14__Z
|
| 425 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[15] -translated cop_dout_reg/r32_o_15__Z
|
| 426 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[16] -translated cop_dout_reg/r32_o_16__Z
|
| 427 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[17] -translated cop_dout_reg/r32_o_17__Z
|
| 428 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[18] -translated cop_dout_reg/r32_o_18__Z
|
| 429 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[19] -translated cop_dout_reg/r32_o_19__Z
|
| 430 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[20] -translated cop_dout_reg/r32_o_20__Z
|
| 431 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[21] -translated cop_dout_reg/r32_o_21__Z
|
| 432 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[22] -translated cop_dout_reg/r32_o_22__Z
|
| 433 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[23] -translated cop_dout_reg/r32_o_23__Z
|
| 434 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[24] -translated cop_dout_reg/r32_o_24__Z
|
| 435 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[25] -translated cop_dout_reg/r32_o_25__Z
|
| 436 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[26] -translated cop_dout_reg/r32_o_26__Z
|
| 437 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[27] -translated cop_dout_reg/r32_o_27__Z
|
| 438 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[28] -translated cop_dout_reg/r32_o_28__Z
|
| 439 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[29] -translated cop_dout_reg/r32_o_29__Z
|
| 440 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[30] -translated cop_dout_reg/r32_o_30__Z
|
| 441 |
|
|
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[31] -translated cop_dout_reg/r32_o_31__Z
|
| 442 |
|
|
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U12/wb_we_o[0] -translated decoder_pipe/pipereg/U12/wb_we_o_0__Z
|
| 443 |
|
|
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U18/wb_mux_ctl_o[0] -translated decoder_pipe/pipereg/U18/wb_mux_ctl_o_0__Z
|
| 444 |
|
|
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U20/wb_we_o[0] -translated decoder_pipe/pipereg/U20/wb_we_o_0__Z
|
| 445 |
|
|
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U21/wb_mux_ctl_o[0] -translated decoder_pipe/pipereg/U21/wb_mux_ctl_o_0__Z
|
| 446 |
|
|
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U22/wb_we_o[0] -translated decoder_pipe/pipereg/U22/wb_we_o_0__Z
|
| 447 |
|
|
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U9/dmem_ctl_o[0] -translated decoder_pipe/pipereg/U9/dmem_ctl_o_0__Z
|
| 448 |
|
|
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U9/dmem_ctl_o[1] -translated decoder_pipe/pipereg/U9/dmem_ctl_o_1__Z
|
| 449 |
|
|
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U9/dmem_ctl_o[2] -translated decoder_pipe/pipereg/U9/dmem_ctl_o_2__Z
|
| 450 |
|
|
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U9/dmem_ctl_o[3] -translated decoder_pipe/pipereg/U9/dmem_ctl_o_3__Z
|
| 451 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[0] -translated ext_reg/r32_o_0__Z
|
| 452 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[1] -translated ext_reg/r32_o_1__Z
|
| 453 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[2] -translated ext_reg/r32_o_2__Z
|
| 454 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[3] -translated ext_reg/r32_o_3__Z
|
| 455 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[4] -translated ext_reg/r32_o_4__Z
|
| 456 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[5] -translated ext_reg/r32_o_5__Z
|
| 457 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[6] -translated ext_reg/r32_o_6__Z
|
| 458 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[7] -translated ext_reg/r32_o_7__Z
|
| 459 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[8] -translated ext_reg/r32_o_8__Z
|
| 460 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[9] -translated ext_reg/r32_o_9__Z
|
| 461 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[10] -translated ext_reg/r32_o_10__Z
|
| 462 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[11] -translated ext_reg/r32_o_11__Z
|
| 463 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[12] -translated ext_reg/r32_o_12__Z
|
| 464 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[13] -translated ext_reg/r32_o_13__Z
|
| 465 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[14] -translated ext_reg/r32_o_14__Z
|
| 466 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[15] -translated ext_reg/r32_o_15__Z
|
| 467 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[16] -translated ext_reg/r32_o_16__Z
|
| 468 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[17] -translated ext_reg/r32_o_17__Z
|
| 469 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[18] -translated ext_reg/r32_o_18__Z
|
| 470 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[19] -translated ext_reg/r32_o_19__Z
|
| 471 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[20] -translated ext_reg/r32_o_20__Z
|
| 472 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[21] -translated ext_reg/r32_o_21__Z
|
| 473 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[22] -translated ext_reg/r32_o_22__Z
|
| 474 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[23] -translated ext_reg/r32_o_23__Z
|
| 475 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[24] -translated ext_reg/r32_o_24__Z
|
| 476 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[25] -translated ext_reg/r32_o_25__Z
|
| 477 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[26] -translated ext_reg/r32_o_26__Z
|
| 478 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[27] -translated ext_reg/r32_o_27__Z
|
| 479 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[28] -translated ext_reg/r32_o_28__Z
|
| 480 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[29] -translated ext_reg/r32_o_29__Z
|
| 481 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[30] -translated ext_reg/r32_o_30__Z
|
| 482 |
|
|
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[31] -translated ext_reg/r32_o_31__Z
|
| 483 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[0] -translated iforward/fw_reg_rns/q_0__Z
|
| 484 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[1] -translated iforward/fw_reg_rns/q_1__Z
|
| 485 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[2] -translated iforward/fw_reg_rns/q_2__Z
|
| 486 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[3] -translated iforward/fw_reg_rns/q_3__Z
|
| 487 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[4] -translated iforward/fw_reg_rns/q_4__Z
|
| 488 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[0] -translated iforward/fw_reg_rnt/q_0__Z
|
| 489 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[1] -translated iforward/fw_reg_rnt/q_1__Z
|
| 490 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[2] -translated iforward/fw_reg_rnt/q_2__Z
|
| 491 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[3] -translated iforward/fw_reg_rnt/q_3__Z
|
| 492 |
|
|
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[4] -translated iforward/fw_reg_rnt/q_4__Z
|
| 493 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[0] -translated pc/r32_o_0__Z
|
| 494 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[1] -translated pc/r32_o_1__Z
|
| 495 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[2] -translated pc/r32_o_2__Z
|
| 496 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[3] -translated pc/r32_o_3__Z
|
| 497 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[4] -translated pc/r32_o_4__Z
|
| 498 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[5] -translated pc/r32_o_5__Z
|
| 499 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[6] -translated pc/r32_o_6__Z
|
| 500 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[7] -translated pc/r32_o_7__Z
|
| 501 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[8] -translated pc/r32_o_8__Z
|
| 502 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[9] -translated pc/r32_o_9__Z
|
| 503 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[10] -translated pc/r32_o_10__Z
|
| 504 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[11] -translated pc/r32_o_11__Z
|
| 505 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[12] -translated pc/r32_o_12__Z
|
| 506 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[13] -translated pc/r32_o_13__Z
|
| 507 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[14] -translated pc/r32_o_14__Z
|
| 508 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[15] -translated pc/r32_o_15__Z
|
| 509 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[16] -translated pc/r32_o_16__Z
|
| 510 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[17] -translated pc/r32_o_17__Z
|
| 511 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[18] -translated pc/r32_o_18__Z
|
| 512 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[19] -translated pc/r32_o_19__Z
|
| 513 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[20] -translated pc/r32_o_20__Z
|
| 514 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[21] -translated pc/r32_o_21__Z
|
| 515 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[22] -translated pc/r32_o_22__Z
|
| 516 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[23] -translated pc/r32_o_23__Z
|
| 517 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[24] -translated pc/r32_o_24__Z
|
| 518 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[25] -translated pc/r32_o_25__Z
|
| 519 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[26] -translated pc/r32_o_26__Z
|
| 520 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[27] -translated pc/r32_o_27__Z
|
| 521 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[28] -translated pc/r32_o_28__Z
|
| 522 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[29] -translated pc/r32_o_29__Z
|
| 523 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[30] -translated pc/r32_o_30__Z
|
| 524 |
|
|
vif_set_sequential_verify -retimed -register -original pc/r32_o[31] -translated pc/r32_o_31__Z
|
| 525 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[0] -translated rnd_pass0/r5_o_0__Z
|
| 526 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[1] -translated rnd_pass0/r5_o_1__Z
|
| 527 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[2] -translated rnd_pass0/r5_o_2__Z
|
| 528 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[3] -translated rnd_pass0/r5_o_3__Z
|
| 529 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[4] -translated rnd_pass0/r5_o_4__Z
|
| 530 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[0] -translated rnd_pass1/r5_o_0__Z
|
| 531 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[1] -translated rnd_pass1/r5_o_1__Z
|
| 532 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[2] -translated rnd_pass1/r5_o_2__Z
|
| 533 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[3] -translated rnd_pass1/r5_o_3__Z
|
| 534 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[4] -translated rnd_pass1/r5_o_4__Z
|
| 535 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[0] -translated rnd_pass2/r5_o_0__Z
|
| 536 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[1] -translated rnd_pass2/r5_o_1__Z
|
| 537 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[2] -translated rnd_pass2/r5_o_2__Z
|
| 538 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[3] -translated rnd_pass2/r5_o_3__Z
|
| 539 |
|
|
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[4] -translated rnd_pass2/r5_o_4__Z
|
| 540 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[0] -translated rs_reg/r32_o_0__Z
|
| 541 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[1] -translated rs_reg/r32_o_1__Z
|
| 542 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[2] -translated rs_reg/r32_o_2__Z
|
| 543 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[3] -translated rs_reg/r32_o_3__Z
|
| 544 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[4] -translated rs_reg/r32_o_4__Z
|
| 545 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[5] -translated rs_reg/r32_o_5__Z
|
| 546 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[6] -translated rs_reg/r32_o_6__Z
|
| 547 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[7] -translated rs_reg/r32_o_7__Z
|
| 548 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[8] -translated rs_reg/r32_o_8__Z
|
| 549 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[9] -translated rs_reg/r32_o_9__Z
|
| 550 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[10] -translated rs_reg/r32_o_10__Z
|
| 551 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[11] -translated rs_reg/r32_o_11__Z
|
| 552 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[12] -translated rs_reg/r32_o_12__Z
|
| 553 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[13] -translated rs_reg/r32_o_13__Z
|
| 554 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[14] -translated rs_reg/r32_o_14__Z
|
| 555 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[15] -translated rs_reg/r32_o_15__Z
|
| 556 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[16] -translated rs_reg/r32_o_16__Z
|
| 557 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[17] -translated rs_reg/r32_o_17__Z
|
| 558 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[18] -translated rs_reg/r32_o_18__Z
|
| 559 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[19] -translated rs_reg/r32_o_19__Z
|
| 560 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[20] -translated rs_reg/r32_o_20__Z
|
| 561 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[21] -translated rs_reg/r32_o_21__Z
|
| 562 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[22] -translated rs_reg/r32_o_22__Z
|
| 563 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[23] -translated rs_reg/r32_o_23__Z
|
| 564 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[24] -translated rs_reg/r32_o_24__Z
|
| 565 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[25] -translated rs_reg/r32_o_25__Z
|
| 566 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[26] -translated rs_reg/r32_o_26__Z
|
| 567 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[27] -translated rs_reg/r32_o_27__Z
|
| 568 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[28] -translated rs_reg/r32_o_28__Z
|
| 569 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[29] -translated rs_reg/r32_o_29__Z
|
| 570 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[30] -translated rs_reg/r32_o_30__Z
|
| 571 |
|
|
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[31] -translated rs_reg/r32_o_31__Z
|
| 572 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[0] -translated rt_reg/r32_o_0__Z
|
| 573 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[1] -translated rt_reg/r32_o_1__Z
|
| 574 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[2] -translated rt_reg/r32_o_2__Z
|
| 575 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[3] -translated rt_reg/r32_o_3__Z
|
| 576 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[4] -translated rt_reg/r32_o_4__Z
|
| 577 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[5] -translated rt_reg/r32_o_5__Z
|
| 578 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[6] -translated rt_reg/r32_o_6__Z
|
| 579 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[7] -translated rt_reg/r32_o_7__Z
|
| 580 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[8] -translated rt_reg/r32_o_8__Z
|
| 581 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[9] -translated rt_reg/r32_o_9__Z
|
| 582 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[10] -translated rt_reg/r32_o_10__Z
|
| 583 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[11] -translated rt_reg/r32_o_11__Z
|
| 584 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[12] -translated rt_reg/r32_o_12__Z
|
| 585 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[13] -translated rt_reg/r32_o_13__Z
|
| 586 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[14] -translated rt_reg/r32_o_14__Z
|
| 587 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[15] -translated rt_reg/r32_o_15__Z
|
| 588 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[16] -translated rt_reg/r32_o_16__Z
|
| 589 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[17] -translated rt_reg/r32_o_17__Z
|
| 590 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[18] -translated rt_reg/r32_o_18__Z
|
| 591 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[19] -translated rt_reg/r32_o_19__Z
|
| 592 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[20] -translated rt_reg/r32_o_20__Z
|
| 593 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[21] -translated rt_reg/r32_o_21__Z
|
| 594 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[22] -translated rt_reg/r32_o_22__Z
|
| 595 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[23] -translated rt_reg/r32_o_23__Z
|
| 596 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[24] -translated rt_reg/r32_o_24__Z
|
| 597 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[25] -translated rt_reg/r32_o_25__Z
|
| 598 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[26] -translated rt_reg/r32_o_26__Z
|
| 599 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[27] -translated rt_reg/r32_o_27__Z
|
| 600 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[28] -translated rt_reg/r32_o_28__Z
|
| 601 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[29] -translated rt_reg/r32_o_29__Z
|
| 602 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[30] -translated rt_reg/r32_o_30__Z
|
| 603 |
|
|
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[31] -translated rt_reg/r32_o_31__Z
|
| 604 |
|
|
|
| 605 |
|
|
# Altera MAC annotations
|
| 606 |
|
|
|
