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10 |
mcupro |
#
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# Synplicity Verification Interface File
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| 3 |
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# Generated using Synplify-pro
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#
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| 5 |
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# Copyright (c) 1996-2005 Synplicity, Inc.
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# All rights reserved
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| 7 |
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#
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| 8 |
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| 9 |
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# Set logfile options
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| 10 |
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vif_set_result_file mips_sys.vlf
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| 11 |
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| 12 |
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# Set technology for TCL script
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| 13 |
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vif_set_technology -architecture FPGA -vendor Altera
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| 14 |
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| 15 |
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# RTL and technology files
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| 16 |
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vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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| 17 |
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vif_add_file -original -verilog ../../rtl/verilog/ctl_fsm.v
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| 18 |
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vif_add_file -original -verilog ../../rtl/verilog/decode_pipe.v
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| 19 |
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vif_add_file -original -verilog ../../rtl/verilog/dvc.v
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| 20 |
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vif_add_file -original -verilog ../../rtl/verilog/EXEC_stage.v
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| 21 |
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vif_add_file -original -verilog ../../rtl/verilog/fifo.v
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| 22 |
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vif_add_file -original -verilog ../../rtl/verilog/forward.v
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| 23 |
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vif_add_file -original -verilog ../../rtl/verilog/mem_module.v
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| 24 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_core.v
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| 25 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_dvc.v
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| 26 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_sys.v
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| 27 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_uart.v
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| 28 |
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vif_add_file -original -verilog ../../rtl/verilog/ram_module.v
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| 29 |
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vif_add_file -original -verilog ../../rtl/verilog/RF_components.v
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| 30 |
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vif_add_file -original -verilog ../../rtl/verilog/RF_stage.v
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| 31 |
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vif_add_file -original -verilog ../../rtl/verilog/sim_ram.v
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| 32 |
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vif_add_file -original -verilog ../../rtl/verilog/tools.v
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| 33 |
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vif_add_file -original -verilog ../../rtl/verilog/fifo512_cyclone.v
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| 34 |
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vif_set_top_module -original -top mips_sys
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| 35 |
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| 36 |
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vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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| 37 |
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vif_add_file -translated -verilog mips_sys.vqm
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| 38 |
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vif_set_top_module -translated -top mips_sys
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| 39 |
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# Read FSM encoding
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| 40 |
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vif_set_fsm -fsm fsm_0
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| 41 |
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vif_set_fsmreg -original -fsm fsm_0 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[3:0]
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| 42 |
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vif_set_fsmreg -translated -fsm fsm_0 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[8:0]
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| 43 |
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vif_set_state_map -fsm fsm_0 -original "0000" -translated "000000001"
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| 44 |
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vif_set_state_map -fsm fsm_0 -original "0001" -translated "000000010"
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| 45 |
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vif_set_state_map -fsm fsm_0 -original "0010" -translated "000000100"
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| 46 |
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vif_set_state_map -fsm fsm_0 -original "0011" -translated "000001000"
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| 47 |
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vif_set_state_map -fsm fsm_0 -original "0100" -translated "000010000"
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| 48 |
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vif_set_state_map -fsm fsm_0 -original "0101" -translated "000100000"
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| 49 |
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vif_set_state_map -fsm fsm_0 -original "0110" -translated "001000000"
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| 50 |
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vif_set_state_map -fsm fsm_0 -original "0111" -translated "010000000"
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| 51 |
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vif_set_state_map -fsm fsm_0 -original "1000" -translated "100000000"
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| 52 |
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vif_set_fsm -fsm fsm_9
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| 53 |
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vif_set_fsmreg -original -fsm fsm_9 imips_dvc/iuart0/uart_rd_tak/ua_state[2:0]
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| 54 |
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vif_set_fsmreg -translated -fsm fsm_9 imips_dvc/iuart0/uart_rd_tak/ua_state[4:0]
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| 55 |
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vif_set_state_map -fsm fsm_9 -original "000" -translated "00001"
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| 56 |
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vif_set_state_map -fsm fsm_9 -original "001" -translated "00010"
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| 57 |
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vif_set_state_map -fsm fsm_9 -original "010" -translated "00100"
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| 58 |
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vif_set_state_map -fsm fsm_9 -original "011" -translated "01000"
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| 59 |
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vif_set_state_map -fsm fsm_9 -original "100" -translated "10000"
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| 60 |
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vif_set_fsm -fsm fsm_15
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| 61 |
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vif_set_fsmreg -original -fsm fsm_15 imips_dvc/iuart0/uart_txd/ua_state[2:0]
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| 62 |
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vif_set_fsmreg -translated -fsm fsm_15 imips_dvc/iuart0/uart_txd/ua_state[7:0]
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| 63 |
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vif_set_state_map -fsm fsm_15 -original "000" -translated "00000001"
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| 64 |
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vif_set_state_map -fsm fsm_15 -original "001" -translated "00000010"
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| 65 |
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vif_set_state_map -fsm fsm_15 -original "010" -translated "00000100"
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| 66 |
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vif_set_state_map -fsm fsm_15 -original "011" -translated "00001000"
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| 67 |
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vif_set_state_map -fsm fsm_15 -original "100" -translated "00010000"
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| 68 |
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vif_set_state_map -fsm fsm_15 -original "101" -translated "00100000"
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| 69 |
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vif_set_state_map -fsm fsm_15 -original "110" -translated "01000000"
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| 70 |
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vif_set_state_map -fsm fsm_15 -original "111" -translated "10000000"
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| 71 |
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| 72 |
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# Memory map points
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| 73 |
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| 74 |
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# SRL map points
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| 75 |
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| 76 |
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# Compiler constant registers
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| 77 |
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| 78 |
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# Compiler constant latches
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| 79 |
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| 80 |
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# Compiler RTL sequential redundancies
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| 81 |
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| 82 |
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# RTL sequential redundancies
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| 83 |
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vif_set_merge -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[0] mips_core/alu_pass0/r32_o[0]
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| 84 |
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vif_set_merge -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[1] mips_core/alu_pass0/r32_o[1]
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| 85 |
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vif_set_merge -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[32]
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| 86 |
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| 87 |
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# Technology sequential redundancies
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| 88 |
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| 89 |
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# Inversion map points
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| 90 |
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vif_set_map_point -register -inverted -original mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z
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| 91 |
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vif_set_map_point -register -inverted -original imips_dvc/iuart0/uart_rd_tak/ua_state[0] -translated imips_dvc/iuart0/uart_rd_tak/ua_state_i_0__Z
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| 92 |
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vif_set_map_point -register -inverted -original imips_dvc/iuart0/uart_txd/ua_state[0] -translated imips_dvc/iuart0/uart_txd/ua_state_i_0__Z
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| 93 |
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| 94 |
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# Port mappping and directions
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| 95 |
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| 96 |
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# Black box mapping
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| 97 |
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vif_set_black_box synplicity_altsyncram4_r_w
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| 98 |
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vif_set_black_box scfifo
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| 99 |
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| 100 |
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vif_set_map_point -blackbox -original mips_core/iRF_stage/reg_bank/reg_bank/altsyncram -translated mips_core/iRF_stage/reg_bank/reg_bank.I_1
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| 101 |
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vif_set_map_point -blackbox -original mips_core/iRF_stage/reg_bank/reg_bank_1/altsyncram -translated mips_core/iRF_stage/reg_bank/reg_bank_1.I_1
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| 102 |
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vif_set_map_point -blackbox -original imips_dvc/iuart0/uart_txd/fifo/scfifo_component -translated imips_dvc/iuart0/uart_txd/fifo/scfifo_component
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| 103 |
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| 104 |
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# Other sequential cells, including multidimensional arrays
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| 105 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[7] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_7__Z
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| 106 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[6] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_6__Z
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| 107 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[5] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_5__Z
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| 108 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[4] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_4__Z
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| 109 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[3] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_3__Z
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| 110 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[2] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_2__Z
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| 111 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[1] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_1__Z
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| 112 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[0] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_0__Z
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| 113 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[15] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_15__Z
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| 114 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[14] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_14__Z
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| 115 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[13] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_13__Z
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| 116 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[12] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_12__Z
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| 117 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[11] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_11__Z
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| 118 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[10] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_10__Z
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| 119 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[9] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_9__Z
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| 120 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[8] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_8__Z
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| 121 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[31] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_31__Z
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| 122 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[30] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_30__Z
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| 123 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[29] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_29__Z
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| 124 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[28] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_28__Z
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| 125 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[27] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_27__Z
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| 126 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[26] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_26__Z
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| 127 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[25] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_25__Z
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| 128 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[24] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_24__Z
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| 129 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[23] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_23__Z
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| 130 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[22] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_22__Z
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| 131 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[21] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_21__Z
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| 132 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[20] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_20__Z
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| 133 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[19] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_19__Z
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| 134 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[18] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_18__Z
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| 135 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[17] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_17__Z
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| 136 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[16] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_16__Z
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| 137 |
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vif_set_map_point -latch -original mips_core/decoder_pipe/idecoder/fsm_dly[2] -translated mips_core/decoder_pipe/idecoder/fsm_dly_1_2__Z
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| 138 |
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vif_set_map_point -latch -original mips_core/decoder_pipe/idecoder/fsm_dly[1] -translated mips_core/decoder_pipe/idecoder/fsm_dly_1_1__Z
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| 139 |
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|
| 140 |
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# Constant Registers
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| 141 |
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vif_set_constant -original -1 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[5]
|
| 142 |
|
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vif_set_transparent -original 1 mips_core/iRF_stage/MIAN_FSM/iack
|
| 143 |
|
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vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[31]
|
| 144 |
|
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vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[30]
|
| 145 |
|
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vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[29]
|
| 146 |
|
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vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[28]
|
| 147 |
|
|
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[27]
|
| 148 |
|
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vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[26]
|
| 149 |
|
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vif_set_constant -original -1 imips_dvc/mips_tmr0/itmr_d/q
|
| 150 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[31]
|
| 151 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[30]
|
| 152 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[29]
|
| 153 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[28]
|
| 154 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[27]
|
| 155 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[26]
|
| 156 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[25]
|
| 157 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[24]
|
| 158 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[23]
|
| 159 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[22]
|
| 160 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[21]
|
| 161 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[20]
|
| 162 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[19]
|
| 163 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[18]
|
| 164 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[17]
|
| 165 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[16]
|
| 166 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[15]
|
| 167 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[14]
|
| 168 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[13]
|
| 169 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[12]
|
| 170 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[11]
|
| 171 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[10]
|
| 172 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[9]
|
| 173 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[8]
|
| 174 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[7]
|
| 175 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[6]
|
| 176 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[5]
|
| 177 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[4]
|
| 178 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[3]
|
| 179 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[2]
|
| 180 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[1]
|
| 181 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[0]
|
| 182 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[31]
|
| 183 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[30]
|
| 184 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[29]
|
| 185 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[28]
|
| 186 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[27]
|
| 187 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[26]
|
| 188 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[25]
|
| 189 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[24]
|
| 190 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[23]
|
| 191 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[22]
|
| 192 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[21]
|
| 193 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[20]
|
| 194 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[19]
|
| 195 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[18]
|
| 196 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[17]
|
| 197 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[16]
|
| 198 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[15]
|
| 199 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[14]
|
| 200 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[13]
|
| 201 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[12]
|
| 202 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[11]
|
| 203 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[10]
|
| 204 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[9]
|
| 205 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[8]
|
| 206 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[7]
|
| 207 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[6]
|
| 208 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[5]
|
| 209 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[4]
|
| 210 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[3]
|
| 211 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[2]
|
| 212 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[1]
|
| 213 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[0]
|
| 214 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[31]
|
| 215 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[30]
|
| 216 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[29]
|
| 217 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[28]
|
| 218 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[27]
|
| 219 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[26]
|
| 220 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[25]
|
| 221 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[24]
|
| 222 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[23]
|
| 223 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[22]
|
| 224 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[21]
|
| 225 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[20]
|
| 226 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[19]
|
| 227 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[18]
|
| 228 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[17]
|
| 229 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[16]
|
| 230 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[15]
|
| 231 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[14]
|
| 232 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[13]
|
| 233 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[12]
|
| 234 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[11]
|
| 235 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[10]
|
| 236 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[9]
|
| 237 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[8]
|
| 238 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[7]
|
| 239 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[6]
|
| 240 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[5]
|
| 241 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[4]
|
| 242 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[3]
|
| 243 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[2]
|
| 244 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[1]
|
| 245 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[0]
|
| 246 |
|
|
|
| 247 |
|
|
# Retimed Registers
|
| 248 |
|
|
|
| 249 |
|
|
# Altera MAC annotations
|
| 250 |
|
|
|
