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15 |
mcupro |
vendor_name = Synplicity
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| 2 |
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source_file = 0, noname, synplify
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| 3 |
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source_file = 1, c:\program files\synplicity\fpga_81\lib\altera\altera.v, synplify
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| 4 |
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source_file = 2, c:\program files\synplicity\fpga_81\lib\altera\cyclone.v, synplify
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| 5 |
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source_file = 3, c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v, synplify
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| 6 |
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source_file = 4, c:\program files\synplicity\fpga_81\lib\altera\altera_lpm.v, synplify
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| 7 |
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source_file = 5, e:\mips789\mips789\rtl\verilog\exec_stage.v, synplify
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| 8 |
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source_file = 6, e:\mips789\mips789\rtl\verilog\include.h, synplify
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| 9 |
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source_file = 7, e:\mips789\mips789\rtl\verilog\rf_components.v, synplify
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| 10 |
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source_file = 8, e:\mips789\mips789\rtl\verilog\rf_stage.v, synplify
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| 11 |
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source_file = 9, e:\mips789\mips789\rtl\verilog\ctl_fsm.v, synplify
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| 12 |
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source_file = 10, e:\mips789\mips789\rtl\verilog\decode_pipe.v, synplify
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| 13 |
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source_file = 11, e:\mips789\mips789\rtl\verilog\dvc.v, synplify
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| 14 |
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source_file = 12, e:\mips789\mips789\rtl\verilog\fifo.v, synplify
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| 15 |
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source_file = 13, e:\mips789\mips789\rtl\verilog\forward.v, synplify
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| 16 |
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source_file = 14, e:\mips789\mips789\rtl\verilog\mem_module.v, synplify
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| 17 |
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source_file = 15, e:\mips789\mips789\rtl\verilog\mips_core.v, synplify
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| 18 |
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source_file = 16, e:\mips789\mips789\rtl\verilog\mips_dvc.v, synplify
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| 19 |
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source_file = 17, e:\mips789\mips789\rtl\verilog\mips_sys.v, synplify
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| 20 |
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source_file = 18, e:\mips789\mips789\rtl\verilog\mips_uart.v, synplify
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| 21 |
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source_file = 19, e:\mips789\mips789\rtl\verilog\ram_module.v, synplify
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| 22 |
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source_file = 20, e:\mips789\mips789\rtl\verilog\sim_ram.v, synplify
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| 23 |
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source_file = 21, e:\mips789\mips789\rtl\verilog\ulit.v, synplify
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| 24 |
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source_file = 22, e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v, synplify
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| 25 |
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design_name=r5_reg_cls
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instance = port, r5_i[4:0], , r5_reg_cls, 21, 172:37:172:40
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instance = port, r5_o[4:0], , r5_reg_cls, 21, 172:66:172:69
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| 28 |
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instance = port, clk, , r5_reg_cls, 21, 172:77:172:79
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| 29 |
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instance = port, cls, , r5_reg_cls, 21, 172:87:172:89
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| 30 |
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instance = comp, r5_o_4__Z, , r5_reg_cls, 21, 172:92:172:97
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| 31 |
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instance = comp, r5_o_3__Z, , r5_reg_cls, 21, 172:92:172:97
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| 32 |
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instance = comp, r5_o_2__Z, , r5_reg_cls, 21, 172:92:172:97
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| 33 |
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instance = comp, r5_o_1__Z, , r5_reg_cls, 21, 172:92:172:97
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| 34 |
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instance = comp, r5_o_0__Z, , r5_reg_cls, 21, 172:92:172:97
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| 35 |
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instance = comp, cls_in, , r5_reg_cls, 21, 172:87:172:89
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| 36 |
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instance = comp, clk_in, , r5_reg_cls, 21, 172:77:172:79
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| 37 |
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instance = comp, r5_i_in_4_, , r5_reg_cls, 21, 172:37:172:40
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| 38 |
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instance = comp, r5_i_in_3_, , r5_reg_cls, 21, 172:37:172:40
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| 39 |
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instance = comp, r5_i_in_2_, , r5_reg_cls, 21, 172:37:172:40
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| 40 |
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instance = comp, r5_i_in_1_, , r5_reg_cls, 21, 172:37:172:40
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| 41 |
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instance = comp, r5_i_in_0_, , r5_reg_cls, 21, 172:37:172:40
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| 42 |
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instance = comp, r5_o_out_4_, , r5_reg_cls, 21, 172:66:172:69
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| 43 |
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instance = comp, r5_o_out_3_, , r5_reg_cls, 21, 172:66:172:69
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| 44 |
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instance = comp, r5_o_out_2_, , r5_reg_cls, 21, 172:66:172:69
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| 45 |
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instance = comp, r5_o_out_1_, , r5_reg_cls, 21, 172:66:172:69
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| 46 |
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instance = comp, r5_o_out_0_, , r5_reg_cls, 21, 172:66:172:69
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