OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [tags/] [arelease/] [synplify_prj/] [rev_1/] [mips_sys.tlg] - Blame information for rev 51

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mcupro 
Selecting top level module mips_sys
2 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":78:7:78:25|Synthesizing module infile_dmem_ctl_reg
3 
 
4 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <30> of dmem_addr_i[31:0] is unused
5 
 
6 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <29> of dmem_addr_i[31:0] is unused
7 
 
8 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <28> of dmem_addr_i[31:0] is unused
9 
 
10 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <27> of dmem_addr_i[31:0] is unused
11 
 
12 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <26> of dmem_addr_i[31:0] is unused
13 
 
14 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <25> of dmem_addr_i[31:0] is unused
15 
 
16 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <24> of dmem_addr_i[31:0] is unused
17 
 
18 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <23> of dmem_addr_i[31:0] is unused
19 
 
20 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <22> of dmem_addr_i[31:0] is unused
21 
 
22 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <21> of dmem_addr_i[31:0] is unused
23 
 
24 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <20> of dmem_addr_i[31:0] is unused
25 
 
26 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <19> of dmem_addr_i[31:0] is unused
27 
 
28 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <18> of dmem_addr_i[31:0] is unused
29 
 
30 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <17> of dmem_addr_i[31:0] is unused
31 
 
32 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <16> of dmem_addr_i[31:0] is unused
33 
 
34 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <15> of dmem_addr_i[31:0] is unused
35 
 
36 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <14> of dmem_addr_i[31:0] is unused
37 
 
38 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <13> of dmem_addr_i[31:0] is unused
39 
 
40 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <12> of dmem_addr_i[31:0] is unused
41 
 
42 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <11> of dmem_addr_i[31:0] is unused
43 
 
44 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <10> of dmem_addr_i[31:0] is unused
45 
 
46 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <9> of dmem_addr_i[31:0] is unused
47 
 
48 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <8> of dmem_addr_i[31:0] is unused
49 
 
50 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <7> of dmem_addr_i[31:0] is unused
51 
 
52 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <6> of dmem_addr_i[31:0] is unused
53 
 
54 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <5> of dmem_addr_i[31:0] is unused
55 
 
56 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <4> of dmem_addr_i[31:0] is unused
57 
 
58 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <3> of dmem_addr_i[31:0] is unused
59 
 
60 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <2> of dmem_addr_i[31:0] is unused
61 
 
62 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":96:7:96:18|Synthesizing module mem_addr_ctl
63 
 
64 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":102:4:102:7|Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt
65 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <31> of addr_i[31:0] is unused
66 
 
67 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <30> of addr_i[31:0] is unused
68 
 
69 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <29> of addr_i[31:0] is unused
70 
 
71 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <28> of addr_i[31:0] is unused
72 
 
73 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <27> of addr_i[31:0] is unused
74 
 
75 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <26> of addr_i[31:0] is unused
76 
 
77 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <25> of addr_i[31:0] is unused
78 
 
79 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <24> of addr_i[31:0] is unused
80 
 
81 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <23> of addr_i[31:0] is unused
82 
 
83 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <22> of addr_i[31:0] is unused
84 
 
85 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <21> of addr_i[31:0] is unused
86 
 
87 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <20> of addr_i[31:0] is unused
88 
 
89 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <19> of addr_i[31:0] is unused
90 
 
91 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <18> of addr_i[31:0] is unused
92 
 
93 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <17> of addr_i[31:0] is unused
94 
 
95 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <16> of addr_i[31:0] is unused
96 
 
97 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <15> of addr_i[31:0] is unused
98 
 
99 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <14> of addr_i[31:0] is unused
100 
 
101 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <13> of addr_i[31:0] is unused
102 
 
103 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <12> of addr_i[31:0] is unused
104 
 
105 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <11> of addr_i[31:0] is unused
106 
 
107 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <10> of addr_i[31:0] is unused
108 
 
109 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <9> of addr_i[31:0] is unused
110 
 
111 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <8> of addr_i[31:0] is unused
112 
 
113 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <7> of addr_i[31:0] is unused
114 
 
115 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <6> of addr_i[31:0] is unused
116 
 
117 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <5> of addr_i[31:0] is unused
118 
 
119 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <4> of addr_i[31:0] is unused
120 
 
121 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <3> of addr_i[31:0] is unused
122 
 
123 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <2> of addr_i[31:0] is unused
124 
 
125 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":199:7:199:17|Synthesizing module mem_din_ctl
126 
 
127 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":130:7:130:18|Synthesizing module mem_dout_ctl
128 
 
129 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt
130 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":4:7:4:16|Synthesizing module mem_module
131 
 
132 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":3:7:3:13|Synthesizing module cal_cpi
133 
 
134 
@N:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":2:7:2:13|Synthesizing module ctl_FSM
135 
 
136 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt
137 
@W: CL113 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Feedback mux created for signal iack.
138 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt
139 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt
140 
@N: CL201 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":255:4:255:9|Trying to extract state machine for register CurrState_Sreg0
141 
Extracted state machine for register CurrState_Sreg0
142 
State machine has 9 reachable states with original encodings of:
143 
   0000
144 
   0001
145 
   0010
146 
   0011
147 
   0100
148 
   0101
149 
   0110
150 
   0111
151 
   1000
152 
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":49:7:49:12|Synthesizing module pc_gen
153 
 
154 
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":30:7:30:13|Synthesizing module compare
155 
 
156 
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":2:7:2:9|Synthesizing module ext
157 
 
158 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <31> of ins_i[31:0] is unused
159 
 
160 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <30> of ins_i[31:0] is unused
161 
 
162 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <29> of ins_i[31:0] is unused
163 
 
164 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <28> of ins_i[31:0] is unused
165 
 
166 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <27> of ins_i[31:0] is unused
167 
 
168 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <26> of ins_i[31:0] is unused
169 
 
170 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":103:7:103:21|Synthesizing module r32_reg_clr_cls
171 
 
172 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":103:167:103:171|Removing redundant assignment
173 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":30:7:30:10|Synthesizing module jack
174 
 
175 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <31> of ins_i[31:0] is unused
176 
 
177 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <30> of ins_i[31:0] is unused
178 
 
179 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <29> of ins_i[31:0] is unused
180 
 
181 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <28> of ins_i[31:0] is unused
182 
 
183 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <27> of ins_i[31:0] is unused
184 
 
185 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <26> of ins_i[31:0] is unused
186 
 
187 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <10> of ins_i[31:0] is unused
188 
 
189 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <9> of ins_i[31:0] is unused
190 
 
191 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <8> of ins_i[31:0] is unused
192 
 
193 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <7> of ins_i[31:0] is unused
194 
 
195 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <6> of ins_i[31:0] is unused
196 
 
197 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <5> of ins_i[31:0] is unused
198 
 
199 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <4> of ins_i[31:0] is unused
200 
 
201 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <3> of ins_i[31:0] is unused
202 
 
203 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <2> of ins_i[31:0] is unused
204 
 
205 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <1> of ins_i[31:0] is unused
206 
 
207 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <0> of ins_i[31:0] is unused
208 
 
209 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":64:7:64:12|Synthesizing module rd_sel
210 
 
211 
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":89:7:89:15|Synthesizing module reg_array
212 
 
213 
@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":139:4:139:9|Found RAM reg_bank, depth=32, width=32
214 
@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":139:4:139:9|Found RAM reg_bank, depth=32, width=32
215 
@N:"E:\mips789\mips789\rtl\verilog\forward.v":25:7:25:13|Synthesizing module fwd_mux
216 
 
217 
@N:"E:\mips789\mips789\rtl\verilog\RF_stage.v":3:7:3:14|Synthesizing module rf_stage
218 
 
219 
@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":91:24:91:29|Port width mismatch for port ins_no.  Formal has width 101, Actual 1
220 
@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":90:24:90:29|Port width mismatch for port clk_no.  Formal has width 101, Actual 1
221 
@W: CL168 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":87:12:87:18|Pruning instance CAL_CPI - not in use ...
222 
 
223 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":512:7:512:15|Synthesizing module muldiv_ff
224 
 
225 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2
226 
 
227 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2
228 
 
229 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s
230 
 
231 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register START_SECTION.over[32:0]
232 
 
233 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64
234 
 
235 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":563:4:563:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqz
236 
 
237 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":227:7:227:9|Synthesizing module alu
238 
 
239 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":259:4:259:14|Synthesizing module shifter_tak
240 
 
241 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <31> of shift_amount[31:0] is unused
242 
 
243 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <30> of shift_amount[31:0] is unused
244 
 
245 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <29> of shift_amount[31:0] is unused
246 
 
247 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <28> of shift_amount[31:0] is unused
248 
 
249 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <27> of shift_amount[31:0] is unused
250 
 
251 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <26> of shift_amount[31:0] is unused
252 
 
253 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <25> of shift_amount[31:0] is unused
254 
 
255 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <24> of shift_amount[31:0] is unused
256 
 
257 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <23> of shift_amount[31:0] is unused
258 
 
259 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <22> of shift_amount[31:0] is unused
260 
 
261 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <21> of shift_amount[31:0] is unused
262 
 
263 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <20> of shift_amount[31:0] is unused
264 
 
265 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <19> of shift_amount[31:0] is unused
266 
 
267 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <18> of shift_amount[31:0] is unused
268 
 
269 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <17> of shift_amount[31:0] is unused
270 
 
271 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <16> of shift_amount[31:0] is unused
272 
 
273 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <15> of shift_amount[31:0] is unused
274 
 
275 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <14> of shift_amount[31:0] is unused
276 
 
277 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <13> of shift_amount[31:0] is unused
278 
 
279 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <12> of shift_amount[31:0] is unused
280 
 
281 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <11> of shift_amount[31:0] is unused
282 
 
283 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <10> of shift_amount[31:0] is unused
284 
 
285 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <9> of shift_amount[31:0] is unused
286 
 
287 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <8> of shift_amount[31:0] is unused
288 
 
289 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <7> of shift_amount[31:0] is unused
290 
 
291 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <6> of shift_amount[31:0] is unused
292 
 
293 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":263:25:263:50|Input port bit <5> of shift_amount[31:0] is unused
294 
 
295 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":132:7:132:13|Synthesizing module big_alu
296 
 
297 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":22:7:22:11|Synthesizing module add32
298 
 
299 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":182:7:182:14|Synthesizing module alu_muxa
300 
 
301 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":206:7:206:14|Synthesizing module alu_muxb
302 
 
303 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":149:7:149:13|Synthesizing module r32_reg
304 
 
305 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":172:7:172:17|Synthesizing module r32_reg_cls
306 
 
307 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":172:132:172:136|Removing redundant assignment
308 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":3:7:3:16|Synthesizing module exec_stage
309 
 
310 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":54:7:54:10|Synthesizing module or32
311 
 
312 
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":2:7:2:13|Synthesizing module decoder
313 
 
314 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt
315 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt
316 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt
317 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt
318 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt
319 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt
320 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt
321 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt
322 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt
323 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt
324 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt
325 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt
326 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <15> of ins_i[31:0] is unused
327 
 
328 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <14> of ins_i[31:0] is unused
329 
 
330 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <13> of ins_i[31:0] is unused
331 
 
332 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <12> of ins_i[31:0] is unused
333 
 
334 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <11> of ins_i[31:0] is unused
335 
 
336 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <10> of ins_i[31:0] is unused
337 
 
338 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <9> of ins_i[31:0] is unused
339 
 
340 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <8> of ins_i[31:0] is unused
341 
 
342 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <7> of ins_i[31:0] is unused
343 
 
344 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <6> of ins_i[31:0] is unused
345 
 
346 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":89:7:89:26|Synthesizing module muxb_ctl_reg_clr_cls
347 
 
348 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":89:202:89:211|Removing redundant assignment
349 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":93:7:93:28|Synthesizing module wb_mux_ctl_reg_clr_cls
350 
 
351 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":93:216:93:227|Removing redundant assignment
352 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":94:7:94:23|Synthesizing module wb_we_reg_clr_cls
353 
 
354 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":94:181:94:187|Removing redundant assignment
355 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":140:7:140:15|Synthesizing module wb_we_reg
356 
 
357 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":116:7:116:24|Synthesizing module wb_mux_ctl_reg_clr
358 
 
359 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":112:7:112:22|Synthesizing module muxb_ctl_reg_clr
360 
 
361 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":115:7:115:22|Synthesizing module dmem_ctl_reg_clr
362 
 
363 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":113:7:113:22|Synthesizing module alu_func_reg_clr
364 
 
365 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":111:7:111:22|Synthesizing module muxa_ctl_reg_clr
366 
 
367 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":139:7:139:20|Synthesizing module wb_mux_ctl_reg
368 
 
369 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":117:7:117:19|Synthesizing module wb_we_reg_clr
370 
 
371 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":85:7:85:25|Synthesizing module cmp_ctl_reg_clr_cls
372 
 
373 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":85:195:85:203|Removing redundant assignment
374 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":114:7:114:20|Synthesizing module alu_we_reg_clr
375 
 
376 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":90:7:90:26|Synthesizing module alu_func_reg_clr_cls
377 
 
378 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":90:202:90:211|Removing redundant assignment
379 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":92:7:92:26|Synthesizing module dmem_ctl_reg_clr_cls
380 
 
381 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":92:202:92:211|Removing redundant assignment
382 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":83:7:83:25|Synthesizing module ext_ctl_reg_clr_cls
383 
 
384 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":83:195:83:203|Removing redundant assignment
385 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":84:7:84:24|Synthesizing module rd_sel_reg_clr_cls
386 
 
387 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":84:188:84:195|Removing redundant assignment
388 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":91:7:91:24|Synthesizing module alu_we_reg_clr_cls
389 
 
390 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":91:188:91:195|Removing redundant assignment
391 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":88:7:88:26|Synthesizing module muxa_ctl_reg_clr_cls
392 
 
393 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":88:202:88:211|Removing redundant assignment
394 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":86:7:86:28|Synthesizing module pc_gen_ctl_reg_clr_cls
395 
 
396 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":86:216:86:227|Removing redundant assignment
397 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":138:7:138:18|Synthesizing module dmem_ctl_reg
398 
 
399 
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1090:7:1090:19|Synthesizing module pipelinedregs
400 
 
401 
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1419:7:1419:17|Synthesizing module decode_pipe
402 
 
403 
@N:"E:\mips789\mips789\rtl\verilog\forward.v":12:7:12:18|Synthesizing module forward_node
404 
 
405 
@N:"E:\mips789\mips789\rtl\verilog\forward.v":4:7:4:15|Synthesizing module fw_latch5
406 
 
407 
@N:"E:\mips789\mips789\rtl\verilog\forward.v":41:7:41:13|Synthesizing module forward
408 
 
409 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":148:7:148:12|Synthesizing module r5_reg
410 
 
411 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":43:7:43:12|Synthesizing module wb_mux
412 
 
413 
@N:"E:\mips789\mips789\rtl\verilog\mips_core.v":3:7:3:15|Synthesizing module mips_core
414 
 
415 
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":210:7:210:15|Synthesizing module uart_read
416 
 
417 
@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":274:4:274:9|Trying to extract state machine for register ua_state
418 
Extracted state machine for register ua_state
419 
State machine has 5 reachable states with original encodings of:
420 
   000
421 
   001
422 
   010
423 
   011
424 
   100
425 
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":3:7:3:11|Synthesizing module rxd_d
426 
 
427 
@N:"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v":3709:7:3709:12|Synthesizing module scfifo
428 
 
429 
        lpm_width=32'b00000000000000000000000000001000
430 
        lpm_widthu=32'b00000000000000000000000000001001
431 
        lpm_numwords=32'b00000000000000000000001000000000
432 
        lpm_showahead=24'b010011110100011001000110
433 
        intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
434 
        almost_full_value=32'b00000000000000000000000000000000
435 
        almost_empty_value=32'b00000000000000000000000000000000
436 
        underflow_checking=16'b0100111101001110
437 
        overflow_checking=16'b0100111101001110
438 
        allow_rwcycle_when_full=24'b010011110100011001000110
439 
        lpm_hint=152'b01010010010000010100110101011111010000100100110001001111010000110100101101011111010101000101100101010000010001010011110101000001010101010101010001001111
440 
        use_eab=16'b0100111101001110
441 
        add_ram_output_register=24'b010011110100011001000110
442 
        maximum_depth=32'b00000000000000000000000000000000
443 
        lpm_type=48'b011100110110001101100110011010010110011001101111
444 
   Generated name = scfifo_Z1
445 
@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":42:7:42:21|Synthesizing module fifo512_cyclone
446 
 
447 
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":70:7:70:16|Synthesizing module uart_write
448 
 
449 
@W: CG133 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":94:9:94:20|No assignment to write_done_n
450 
@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":168:4:168:9|Trying to extract state machine for register ua_state
451 
Extracted state machine for register ua_state
452 
State machine has 8 reachable states with original encodings of:
453 
   000
454 
   001
455 
   010
456 
   011
457 
   100
458 
   101
459 
   110
460 
   111
461 
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":12:7:12:11|Synthesizing module uart0
462 
 
463 
@W:"E:\mips789\mips789\rtl\verilog\mips_uart.v":38:9:38:17|No assignment to wire w_rxd_clr
464 
 
465 
@N:"E:\mips789\mips789\rtl\verilog\dvc.v":52:7:52:16|Synthesizing module seg7led_cv
466 
 
467 
@N:"E:\mips789\mips789\rtl\verilog\dvc.v":43:7:43:11|Synthesizing module tmr_d
468 
 
469 
@N:"E:\mips789\mips789\rtl\verilog\dvc.v":3:7:3:10|Synthesizing module tmr0
470 
 
471 
@N:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":3:7:3:14|Synthesizing module mips_dvc
472 
 
473 
@N:"E:\mips789\mips789\rtl\verilog\mips_sys.v":4:7:4:14|Synthesizing module mips_sys
474 
 
475 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":78:16:78:24|No assignment to wire data2core
476 
 
477 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":79:16:79:23|No assignment to wire data2mem
478 
 
479 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":80:16:80:23|No assignment to wire ins2core
480 
 
481 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":81:16:81:23|No assignment to wire mem_Addr
482 
 
483 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":82:16:82:17|No assignment to wire pc
484 
 
485 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":83:15:83:19|No assignment to wire wr_en
486 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.