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[/] [mips789/] [tags/] [arelease/] [synplify_prj/] [rev_1/] [syntmp/] [fifo512_cyclone_srr.htm] - Blame information for rev 51

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1 15 mcupro 
<html>
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<body><samp><pre>
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<!@TC:1223605606>
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#Program: Synplify Pro 8.1
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#OS: Windows_NT
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<a name=compilerReport24>$ Start of Compile
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#Fri Oct 10 10:26:44 2008
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Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
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Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
12 
 
13 
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v"
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@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v"
15 
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v"
16 
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v"
17 
@I::"E:\mips789\mips789\rtl\verilog\EXEC_stage.v"
18 
@I:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
19 
@I:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
20 
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:694:80:694:93:@N::@XP_MSG">exec_stage.v(694)</a><!@TM:1223605606> | Read parallel_case directive
21 
@I::"E:\mips789\mips789\rtl\verilog\RF_components.v"
22 
@I:"E:\mips789\mips789\rtl\verilog\RF_components.v":"E:\mips789\mips789\rtl\verilog\include.h"
23 
@I::"E:\mips789\mips789\rtl\verilog\RF_stage.v"
24 
@I:"E:\mips789\mips789\rtl\verilog\RF_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"
25 
@I::"E:\mips789\mips789\rtl\verilog\ctl_fsm.v"
26 
@I:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":"E:\mips789\mips789\rtl\verilog\include.h"
27 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:43:58:56:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605606> | Read parallel_case directive
28 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:57:58:66:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605606> | Read full_case directive
29 
<font color=#A52A2A>@W:<a href="@W:CG286:@XP_HELP">CG286</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CG286:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605606> | Case statement has both a full_case directive and a default clause.  The full_case directive is ignored.</font>
30 
@I::"E:\mips789\mips789\rtl\verilog\decode_pipe.v"
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@I:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":"E:\mips789\mips789\rtl\verilog\include.h"
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@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:34:31:47:@N::@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605606> | Read parallel_case directive
33 
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:34:45:34:58:@N::@XP_MSG">decode_pipe.v(34)</a><!@TM:1223605606> | Read parallel_case directive
34 
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:533:47:533:60:@N::@XP_MSG">decode_pipe.v(533)</a><!@TM:1223605606> | Read parallel_case directive
35 
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:835:49:835:62:@N::@XP_MSG">decode_pipe.v(835)</a><!@TM:1223605606> | Read parallel_case directive
36 
@I::"E:\mips789\mips789\rtl\verilog\dvc.v"
37 
@I:"E:\mips789\mips789\rtl\verilog\dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"
38 
@I::"E:\mips789\mips789\rtl\verilog\fifo.v"
39 
@I:"E:\mips789\mips789\rtl\verilog\fifo.v":"E:\mips789\mips789\rtl\verilog\include.h"
40 
@I::"E:\mips789\mips789\rtl\verilog\forward.v"
41 
@I:"E:\mips789\mips789\rtl\verilog\forward.v":"E:\mips789\mips789\rtl\verilog\include.h"
42 
@I::"E:\mips789\mips789\rtl\verilog\mem_module.v"
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@I:"E:\mips789\mips789\rtl\verilog\mem_module.v":"E:\mips789\mips789\rtl\verilog\include.h"
44 
@I::"E:\mips789\mips789\rtl\verilog\mips_core.v"
45 
@I:"E:\mips789\mips789\rtl\verilog\mips_core.v":"E:\mips789\mips789\rtl\verilog\include.h"
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@I::"E:\mips789\mips789\rtl\verilog\mips_dvc.v"
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@I:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"
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@I::"E:\mips789\mips789\rtl\verilog\mips_sys.v"
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@I:"E:\mips789\mips789\rtl\verilog\mips_sys.v":"E:\mips789\mips789\rtl\verilog\include.h"
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@I::"E:\mips789\mips789\rtl\verilog\mips_uart.v"
51 
@I:"E:\mips789\mips789\rtl\verilog\mips_uart.v":"E:\mips789\mips789\rtl\verilog\include.h"
52 
@I::"E:\mips789\mips789\rtl\verilog\ram_module.v"
53 
@I:"E:\mips789\mips789\rtl\verilog\ram_module.v":"E:\mips789\mips789\rtl\verilog\include.h"
54 
@I::"E:\mips789\mips789\rtl\verilog\sim_ram.v"
55 
@I::"E:\mips789\mips789\rtl\verilog\ulit.v"
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@I:"E:\mips789\mips789\rtl\verilog\ulit.v":"E:\mips789\mips789\rtl\verilog\include.h"
57 
@I::"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v"
58 
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:39:12:39:25:@N::@XP_MSG">fifo512_cyclone.v(39)</a><!@TM:1223605606> | Read directive translate_off
59 
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:41:12:41:24:@N::@XP_MSG">fifo512_cyclone.v(41)</a><!@TM:1223605606> | Read directive translate_on
60 
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:74:16:74:29:@N::@XP_MSG">fifo512_cyclone.v(74)</a><!@TM:1223605606> | Read directive translate_off
61 
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:81:16:81:28:@N::@XP_MSG">fifo512_cyclone.v(81)</a><!@TM:1223605606> | Read directive translate_on
62 
Verilog syntax check successful!
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Options changed - recompiling
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Selecting top level module mips_sys
65 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:78:7:78:26:@N::@XP_MSG">mem_module.v(78)</a><!@TM:1223605618> | Synthesizing module infile_dmem_ctl_reg
66 
 
67 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <30> of dmem_addr_i[31:0] is unused</font>
68 
 
69 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <29> of dmem_addr_i[31:0] is unused</font>
70 
 
71 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <28> of dmem_addr_i[31:0] is unused</font>
72 
 
73 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <27> of dmem_addr_i[31:0] is unused</font>
74 
 
75 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <26> of dmem_addr_i[31:0] is unused</font>
76 
 
77 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <25> of dmem_addr_i[31:0] is unused</font>
78 
 
79 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <24> of dmem_addr_i[31:0] is unused</font>
80 
 
81 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <23> of dmem_addr_i[31:0] is unused</font>
82 
 
83 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <22> of dmem_addr_i[31:0] is unused</font>
84 
 
85 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <21> of dmem_addr_i[31:0] is unused</font>
86 
 
87 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <20> of dmem_addr_i[31:0] is unused</font>
88 
 
89 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <19> of dmem_addr_i[31:0] is unused</font>
90 
 
91 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <18> of dmem_addr_i[31:0] is unused</font>
92 
 
93 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <17> of dmem_addr_i[31:0] is unused</font>
94 
 
95 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <16> of dmem_addr_i[31:0] is unused</font>
96 
 
97 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <15> of dmem_addr_i[31:0] is unused</font>
98 
 
99 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <14> of dmem_addr_i[31:0] is unused</font>
100 
 
101 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <13> of dmem_addr_i[31:0] is unused</font>
102 
 
103 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <12> of dmem_addr_i[31:0] is unused</font>
104 
 
105 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <11> of dmem_addr_i[31:0] is unused</font>
106 
 
107 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <10> of dmem_addr_i[31:0] is unused</font>
108 
 
109 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <9> of dmem_addr_i[31:0] is unused</font>
110 
 
111 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <8> of dmem_addr_i[31:0] is unused</font>
112 
 
113 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <7> of dmem_addr_i[31:0] is unused</font>
114 
 
115 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <6> of dmem_addr_i[31:0] is unused</font>
116 
 
117 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <5> of dmem_addr_i[31:0] is unused</font>
118 
 
119 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <4> of dmem_addr_i[31:0] is unused</font>
120 
 
121 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <3> of dmem_addr_i[31:0] is unused</font>
122 
 
123 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1223605618> | Input port bit <2> of dmem_addr_i[31:0] is unused</font>
124 
 
125 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:96:7:96:19:@N::@XP_MSG">mem_module.v(96)</a><!@TM:1223605618> | Synthesizing module mem_addr_ctl
126 
 
127 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:102:4:102:8:@W:CL118:@XP_MSG">mem_module.v(102)</a><!@TM:1223605618> | Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt</font>
128 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <31> of addr_i[31:0] is unused</font>
129 
 
130 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <30> of addr_i[31:0] is unused</font>
131 
 
132 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <29> of addr_i[31:0] is unused</font>
133 
 
134 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <28> of addr_i[31:0] is unused</font>
135 
 
136 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <27> of addr_i[31:0] is unused</font>
137 
 
138 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <26> of addr_i[31:0] is unused</font>
139 
 
140 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <25> of addr_i[31:0] is unused</font>
141 
 
142 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <24> of addr_i[31:0] is unused</font>
143 
 
144 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <23> of addr_i[31:0] is unused</font>
145 
 
146 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <22> of addr_i[31:0] is unused</font>
147 
 
148 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <21> of addr_i[31:0] is unused</font>
149 
 
150 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <20> of addr_i[31:0] is unused</font>
151 
 
152 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <19> of addr_i[31:0] is unused</font>
153 
 
154 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <18> of addr_i[31:0] is unused</font>
155 
 
156 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <17> of addr_i[31:0] is unused</font>
157 
 
158 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <16> of addr_i[31:0] is unused</font>
159 
 
160 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <15> of addr_i[31:0] is unused</font>
161 
 
162 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <14> of addr_i[31:0] is unused</font>
163 
 
164 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <13> of addr_i[31:0] is unused</font>
165 
 
166 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <12> of addr_i[31:0] is unused</font>
167 
 
168 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <11> of addr_i[31:0] is unused</font>
169 
 
170 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <10> of addr_i[31:0] is unused</font>
171 
 
172 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <9> of addr_i[31:0] is unused</font>
173 
 
174 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <8> of addr_i[31:0] is unused</font>
175 
 
176 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <7> of addr_i[31:0] is unused</font>
177 
 
178 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <6> of addr_i[31:0] is unused</font>
179 
 
180 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <5> of addr_i[31:0] is unused</font>
181 
 
182 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <4> of addr_i[31:0] is unused</font>
183 
 
184 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <3> of addr_i[31:0] is unused</font>
185 
 
186 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1223605618> | Input port bit <2> of addr_i[31:0] is unused</font>
187 
 
188 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:199:7:199:18:@N::@XP_MSG">mem_module.v(199)</a><!@TM:1223605618> | Synthesizing module mem_din_ctl
189 
 
190 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:130:7:130:19:@N::@XP_MSG">mem_module.v(130)</a><!@TM:1223605618> | Synthesizing module mem_dout_ctl
191 
 
192 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:161:4:161:8:@W:CL118:@XP_MSG">mem_module.v(161)</a><!@TM:1223605618> | Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt</font>
193 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mem_module.v:4:7:4:17:@N::@XP_MSG">mem_module.v(4)</a><!@TM:1223605618> | Synthesizing module mem_module
194 
 
195 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:3:7:3:14:@N::@XP_MSG">ulit.v(3)</a><!@TM:1223605618> | Synthesizing module cal_cpi
196 
 
197 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:2:7:2:14:@N::@XP_MSG">ctl_fsm.v(2)</a><!@TM:1223605618> | Synthesizing module ctl_FSM
198 
 
199 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605618> | Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt</font>
200 
<font color=#A52A2A>@W:<a href="@W:CL113:@XP_HELP">CL113</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL113:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605618> | Feedback mux created for signal iack.</font>
201 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605618> | Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt</font>
202 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1223605618> | Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt</font>
203 
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:224:4:224:10:@N:CL201:@XP_MSG">ctl_fsm.v(224)</a><!@TM:1223605618> | Trying to extract state machine for register CurrState_Sreg0
204 
Extracted state machine for register CurrState_Sreg0
205 
State machine has 9 reachable states with original encodings of:
206 
   0000
207 
   0001
208 
   0010
209 
   0011
210 
   0100
211 
   0101
212 
   0110
213 
   0111
214 
   1000
215 
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:50:7:50:13:@N::@XP_MSG">rf_components.v(50)</a><!@TM:1223605618> | Synthesizing module pc_gen
216 
 
217 
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:30:7:30:14:@N::@XP_MSG">rf_components.v(30)</a><!@TM:1223605618> | Synthesizing module compare
218 
 
219 
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:36:14:36:17:@W:CG133:@XP_MSG">rf_components.v(36)</a><!@TM:1223605618> | No assignment to sum</font>
220 
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:2:7:2:10:@N::@XP_MSG">rf_components.v(2)</a><!@TM:1223605618> | Synthesizing module ext
221 
 
222 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <31> of ins_i[31:0] is unused</font>
223 
 
224 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <30> of ins_i[31:0] is unused</font>
225 
 
226 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <29> of ins_i[31:0] is unused</font>
227 
 
228 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <28> of ins_i[31:0] is unused</font>
229 
 
230 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <27> of ins_i[31:0] is unused</font>
231 
 
232 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1223605618> | Input port bit <26> of ins_i[31:0] is unused</font>
233 
 
234 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:7:104:22:@N::@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Synthesizing module r32_reg_clr_cls
235 
 
236 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:167:104:172:@N:CG179:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing redundant assignment
237 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:30:7:30:11:@N::@XP_MSG">ulit.v(30)</a><!@TM:1223605618> | Synthesizing module jack
238 
 
239 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <31> of ins_i[31:0] is unused</font>
240 
 
241 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <30> of ins_i[31:0] is unused</font>
242 
 
243 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <29> of ins_i[31:0] is unused</font>
244 
 
245 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <28> of ins_i[31:0] is unused</font>
246 
 
247 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <27> of ins_i[31:0] is unused</font>
248 
 
249 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <26> of ins_i[31:0] is unused</font>
250 
 
251 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <10> of ins_i[31:0] is unused</font>
252 
 
253 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <9> of ins_i[31:0] is unused</font>
254 
 
255 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <8> of ins_i[31:0] is unused</font>
256 
 
257 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <7> of ins_i[31:0] is unused</font>
258 
 
259 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <6> of ins_i[31:0] is unused</font>
260 
 
261 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <5> of ins_i[31:0] is unused</font>
262 
 
263 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <4> of ins_i[31:0] is unused</font>
264 
 
265 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <3> of ins_i[31:0] is unused</font>
266 
 
267 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <2> of ins_i[31:0] is unused</font>
268 
 
269 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <1> of ins_i[31:0] is unused</font>
270 
 
271 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:31:21:31:26:@W::@XP_MSG">ulit.v(31)</a><!@TM:1223605618> | Input port bit <0> of ins_i[31:0] is unused</font>
272 
 
273 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:64:7:64:13:@N::@XP_MSG">ulit.v(64)</a><!@TM:1223605618> | Synthesizing module rd_sel
274 
 
275 
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:90:7:90:16:@N::@XP_MSG">rf_components.v(90)</a><!@TM:1223605618> | Synthesizing module reg_array
276 
 
277 
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1223605618> | Found RAM reg_bank, depth=32, width=32
278 
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1223605618> | Found RAM reg_bank, depth=32, width=32
279 
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:25:7:25:14:@N::@XP_MSG">forward.v(25)</a><!@TM:1223605618> | Synthesizing module fwd_mux
280 
 
281 
@N: : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:3:7:3:15:@N::@XP_MSG">rf_stage.v(3)</a><!@TM:1223605618> | Synthesizing module rf_stage
282 
 
283 
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:91:24:91:30:@W:CS149:@XP_MSG">rf_stage.v(91)</a><!@TM:1223605618> | Port width mismatch for port ins_no.  Formal has width 101, Actual 1</font>
284 
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:90:24:90:30:@W:CS149:@XP_MSG">rf_stage.v(90)</a><!@TM:1223605618> | Port width mismatch for port clk_no.  Formal has width 101, Actual 1</font>
285 
<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="e:\mips789\mips789\rtl\verilog\rf_stage.v:87:12:87:19:@W:CL168:@XP_MSG">rf_stage.v(87)</a><!@TM:1223605618> | Pruning instance CAL_CPI - not in use ...</font>
286 
 
287 
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:521:7:521:16:@N::@XP_MSG">exec_stage.v(521)</a><!@TM:1223605618> | Synthesizing module muldiv_ff
288 
 
289 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqz </font>
290 
 
291 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64 </font>
292 
 
293 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2 </font>
294 
 
295 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2 </font>
296 
 
297 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s </font>
298 
 
299 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Pruning Register START_SECTION.over[32:0] </font>
300 
 
301 
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:233:7:233:10:@N::@XP_MSG">exec_stage.v(233)</a><!@TM:1223605618> | Synthesizing module alu
302 
 
303 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:238:16:238:17:@W::@XP_MSG">exec_stage.v(238)</a><!@TM:1223605618> | No assignment to wire c</font>
304 
 
305 
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:266:4:266:15:@N::@XP_MSG">exec_stage.v(266)</a><!@TM:1223605618> | Synthesizing module shifter_tak
306 
 
307 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <31> of shift_amount[31:0] is unused</font>
308 
 
309 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <30> of shift_amount[31:0] is unused</font>
310 
 
311 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <29> of shift_amount[31:0] is unused</font>
312 
 
313 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <28> of shift_amount[31:0] is unused</font>
314 
 
315 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <27> of shift_amount[31:0] is unused</font>
316 
 
317 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <26> of shift_amount[31:0] is unused</font>
318 
 
319 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <25> of shift_amount[31:0] is unused</font>
320 
 
321 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <24> of shift_amount[31:0] is unused</font>
322 
 
323 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <23> of shift_amount[31:0] is unused</font>
324 
 
325 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <22> of shift_amount[31:0] is unused</font>
326 
 
327 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <21> of shift_amount[31:0] is unused</font>
328 
 
329 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <20> of shift_amount[31:0] is unused</font>
330 
 
331 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <19> of shift_amount[31:0] is unused</font>
332 
 
333 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <18> of shift_amount[31:0] is unused</font>
334 
 
335 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <17> of shift_amount[31:0] is unused</font>
336 
 
337 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <16> of shift_amount[31:0] is unused</font>
338 
 
339 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <15> of shift_amount[31:0] is unused</font>
340 
 
341 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <14> of shift_amount[31:0] is unused</font>
342 
 
343 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <13> of shift_amount[31:0] is unused</font>
344 
 
345 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <12> of shift_amount[31:0] is unused</font>
346 
 
347 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <11> of shift_amount[31:0] is unused</font>
348 
 
349 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <10> of shift_amount[31:0] is unused</font>
350 
 
351 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <9> of shift_amount[31:0] is unused</font>
352 
 
353 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <8> of shift_amount[31:0] is unused</font>
354 
 
355 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <7> of shift_amount[31:0] is unused</font>
356 
 
357 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <6> of shift_amount[31:0] is unused</font>
358 
 
359 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:270:25:270:51:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1223605618> | Input port bit <5> of shift_amount[31:0] is unused</font>
360 
 
361 
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:138:7:138:14:@N::@XP_MSG">exec_stage.v(138)</a><!@TM:1223605618> | Synthesizing module big_alu
362 
 
363 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:22:7:22:12:@N::@XP_MSG">ulit.v(22)</a><!@TM:1223605618> | Synthesizing module add32
364 
 
365 
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:188:7:188:15:@N::@XP_MSG">exec_stage.v(188)</a><!@TM:1223605618> | Synthesizing module alu_muxa
366 
 
367 
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:212:7:212:15:@N::@XP_MSG">exec_stage.v(212)</a><!@TM:1223605618> | Synthesizing module alu_muxb
368 
 
369 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:150:7:150:14:@N::@XP_MSG">ulit.v(150)</a><!@TM:1223605618> | Synthesizing module r32_reg
370 
 
371 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:173:7:173:18:@N::@XP_MSG">ulit.v(173)</a><!@TM:1223605618> | Synthesizing module r32_reg_cls
372 
 
373 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:173:132:173:137:@N:CG179:@XP_MSG">ulit.v(173)</a><!@TM:1223605618> | Removing redundant assignment
374 
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:3:7:3:17:@N::@XP_MSG">exec_stage.v(3)</a><!@TM:1223605618> | Synthesizing module exec_stage
375 
 
376 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:54:7:54:11:@N::@XP_MSG">ulit.v(54)</a><!@TM:1223605618> | Synthesizing module or32
377 
 
378 
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:2:7:2:14:@N::@XP_MSG">decode_pipe.v(2)</a><!@TM:1223605618> | Synthesizing module decoder
379 
 
380 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt</font>
381 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
382 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt</font>
383 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
384 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt</font>
385 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
386 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
387 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt</font>
388 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt</font>
389 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
390 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt</font>
391 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt</font>
392 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <15> of ins_i[31:0] is unused</font>
393 
 
394 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <14> of ins_i[31:0] is unused</font>
395 
 
396 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <13> of ins_i[31:0] is unused</font>
397 
 
398 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <12> of ins_i[31:0] is unused</font>
399 
 
400 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <11> of ins_i[31:0] is unused</font>
401 
 
402 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <10> of ins_i[31:0] is unused</font>
403 
 
404 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <9> of ins_i[31:0] is unused</font>
405 
 
406 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <8> of ins_i[31:0] is unused</font>
407 
 
408 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <7> of ins_i[31:0] is unused</font>
409 
 
410 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1223605618> | Input port bit <6> of ins_i[31:0] is unused</font>
411 
 
412 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:90:7:90:27:@N::@XP_MSG">ulit.v(90)</a><!@TM:1223605618> | Synthesizing module muxb_ctl_reg_clr_cls
413 
 
414 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:90:202:90:212:@N:CG179:@XP_MSG">ulit.v(90)</a><!@TM:1223605618> | Removing redundant assignment
415 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:94:7:94:29:@N::@XP_MSG">ulit.v(94)</a><!@TM:1223605618> | Synthesizing module wb_mux_ctl_reg_clr_cls
416 
 
417 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:94:216:94:228:@N:CG179:@XP_MSG">ulit.v(94)</a><!@TM:1223605618> | Removing redundant assignment
418 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:95:7:95:24:@N::@XP_MSG">ulit.v(95)</a><!@TM:1223605618> | Synthesizing module wb_we_reg_clr_cls
419 
 
420 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:95:181:95:188:@N:CG179:@XP_MSG">ulit.v(95)</a><!@TM:1223605618> | Removing redundant assignment
421 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:141:7:141:16:@N::@XP_MSG">ulit.v(141)</a><!@TM:1223605618> | Synthesizing module wb_we_reg
422 
 
423 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:117:7:117:25:@N::@XP_MSG">ulit.v(117)</a><!@TM:1223605618> | Synthesizing module wb_mux_ctl_reg_clr
424 
 
425 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:113:7:113:23:@N::@XP_MSG">ulit.v(113)</a><!@TM:1223605618> | Synthesizing module muxb_ctl_reg_clr
426 
 
427 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:116:7:116:23:@N::@XP_MSG">ulit.v(116)</a><!@TM:1223605618> | Synthesizing module dmem_ctl_reg_clr
428 
 
429 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:114:7:114:23:@N::@XP_MSG">ulit.v(114)</a><!@TM:1223605618> | Synthesizing module alu_func_reg_clr
430 
 
431 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:112:7:112:23:@N::@XP_MSG">ulit.v(112)</a><!@TM:1223605618> | Synthesizing module muxa_ctl_reg_clr
432 
 
433 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:140:7:140:21:@N::@XP_MSG">ulit.v(140)</a><!@TM:1223605618> | Synthesizing module wb_mux_ctl_reg
434 
 
435 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:118:7:118:20:@N::@XP_MSG">ulit.v(118)</a><!@TM:1223605618> | Synthesizing module wb_we_reg_clr
436 
 
437 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:86:7:86:26:@N::@XP_MSG">ulit.v(86)</a><!@TM:1223605618> | Synthesizing module cmp_ctl_reg_clr_cls
438 
 
439 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:86:195:86:204:@N:CG179:@XP_MSG">ulit.v(86)</a><!@TM:1223605618> | Removing redundant assignment
440 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:115:7:115:21:@N::@XP_MSG">ulit.v(115)</a><!@TM:1223605618> | Synthesizing module alu_we_reg_clr
441 
 
442 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:91:7:91:27:@N::@XP_MSG">ulit.v(91)</a><!@TM:1223605618> | Synthesizing module alu_func_reg_clr_cls
443 
 
444 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:91:202:91:212:@N:CG179:@XP_MSG">ulit.v(91)</a><!@TM:1223605618> | Removing redundant assignment
445 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:93:7:93:27:@N::@XP_MSG">ulit.v(93)</a><!@TM:1223605618> | Synthesizing module dmem_ctl_reg_clr_cls
446 
 
447 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:93:202:93:212:@N:CG179:@XP_MSG">ulit.v(93)</a><!@TM:1223605618> | Removing redundant assignment
448 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:84:7:84:26:@N::@XP_MSG">ulit.v(84)</a><!@TM:1223605618> | Synthesizing module ext_ctl_reg_clr_cls
449 
 
450 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:84:195:84:204:@N:CG179:@XP_MSG">ulit.v(84)</a><!@TM:1223605618> | Removing redundant assignment
451 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:85:7:85:25:@N::@XP_MSG">ulit.v(85)</a><!@TM:1223605618> | Synthesizing module rd_sel_reg_clr_cls
452 
 
453 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:85:188:85:196:@N:CG179:@XP_MSG">ulit.v(85)</a><!@TM:1223605618> | Removing redundant assignment
454 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:92:7:92:25:@N::@XP_MSG">ulit.v(92)</a><!@TM:1223605618> | Synthesizing module alu_we_reg_clr_cls
455 
 
456 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:92:188:92:196:@N:CG179:@XP_MSG">ulit.v(92)</a><!@TM:1223605618> | Removing redundant assignment
457 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:89:7:89:27:@N::@XP_MSG">ulit.v(89)</a><!@TM:1223605618> | Synthesizing module muxa_ctl_reg_clr_cls
458 
 
459 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:89:202:89:212:@N:CG179:@XP_MSG">ulit.v(89)</a><!@TM:1223605618> | Removing redundant assignment
460 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:87:7:87:29:@N::@XP_MSG">ulit.v(87)</a><!@TM:1223605618> | Synthesizing module pc_gen_ctl_reg_clr_cls
461 
 
462 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:87:216:87:228:@N:CG179:@XP_MSG">ulit.v(87)</a><!@TM:1223605618> | Removing redundant assignment
463 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:139:7:139:19:@N::@XP_MSG">ulit.v(139)</a><!@TM:1223605618> | Synthesizing module dmem_ctl_reg
464 
 
465 
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:1090:7:1090:20:@N::@XP_MSG">decode_pipe.v(1090)</a><!@TM:1223605618> | Synthesizing module pipelinedregs
466 
 
467 
@N: : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:1419:7:1419:18:@N::@XP_MSG">decode_pipe.v(1419)</a><!@TM:1223605618> | Synthesizing module decode_pipe
468 
 
469 
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:12:7:12:19:@N::@XP_MSG">forward.v(12)</a><!@TM:1223605618> | Synthesizing module forward_node
470 
 
471 
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:4:7:4:16:@N::@XP_MSG">forward.v(4)</a><!@TM:1223605618> | Synthesizing module fw_latch5
472 
 
473 
@N: : <a href="e:\mips789\mips789\rtl\verilog\forward.v:41:7:41:14:@N::@XP_MSG">forward.v(41)</a><!@TM:1223605618> | Synthesizing module forward
474 
 
475 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:149:7:149:13:@N::@XP_MSG">ulit.v(149)</a><!@TM:1223605618> | Synthesizing module r5_reg
476 
 
477 
@N: : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:43:7:43:13:@N::@XP_MSG">ulit.v(43)</a><!@TM:1223605618> | Synthesizing module wb_mux
478 
 
479 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_core.v:3:7:3:16:@N::@XP_MSG">mips_core.v(3)</a><!@TM:1223605618> | Synthesizing module mips_core
480 
 
481 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:210:7:210:16:@N::@XP_MSG">mips_uart.v(210)</a><!@TM:1223605618> | Synthesizing module uart_read
482 
 
483 
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:274:4:274:10:@N:CL201:@XP_MSG">mips_uart.v(274)</a><!@TM:1223605618> | Trying to extract state machine for register ua_state
484 
Extracted state machine for register ua_state
485 
State machine has 5 reachable states with original encodings of:
486 
   000
487 
   001
488 
   010
489 
   011
490 
   100
491 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:3:7:3:12:@N::@XP_MSG">mips_uart.v(3)</a><!@TM:1223605618> | Synthesizing module rxd_d
492 
 
493 
@N: : <a href="c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v:3709:7:3709:13:@N::@XP_MSG">altera_mf.v(3709)</a><!@TM:1223605618> | Synthesizing module scfifo
494 
 
495 
        lpm_width=32'b00000000000000000000000000001000
496 
        lpm_widthu=32'b00000000000000000000000000001001
497 
        lpm_numwords=32'b00000000000000000000001000000000
498 
        lpm_showahead=24'b010011110100011001000110
499 
        intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
500 
        almost_full_value=32'b00000000000000000000000000000000
501 
        almost_empty_value=32'b00000000000000000000000000000000
502 
        underflow_checking=16'b0100111101001110
503 
        overflow_checking=16'b0100111101001110
504 
        allow_rwcycle_when_full=24'b010011110100011001000110
505 
        lpm_hint=152'b01010010010000010100110101011111010000100100110001001111010000110100101101011111010101000101100101010000010001010011110101000001010101010101010001001111
506 
        use_eab=16'b0100111101001110
507 
        add_ram_output_register=24'b010011110100011001000110
508 
        maximum_depth=32'b00000000000000000000000000000000
509 
        lpm_type=48'b011100110110001101100110011010010110011001101111
510 
   Generated name = scfifo_Z1
511 
@N: : <a href="e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v:42:7:42:22:@N::@XP_MSG">fifo512_cyclone.v(42)</a><!@TM:1223605618> | Synthesizing module fifo512_cyclone
512 
 
513 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:70:7:70:17:@N::@XP_MSG">mips_uart.v(70)</a><!@TM:1223605618> | Synthesizing module uart_write
514 
 
515 
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:94:9:94:21:@W:CG133:@XP_MSG">mips_uart.v(94)</a><!@TM:1223605618> | No assignment to write_done_n</font>
516 
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:168:4:168:10:@N:CL201:@XP_MSG">mips_uart.v(168)</a><!@TM:1223605618> | Trying to extract state machine for register ua_state
517 
Extracted state machine for register ua_state
518 
State machine has 8 reachable states with original encodings of:
519 
   000
520 
   001
521 
   010
522 
   011
523 
   100
524 
   101
525 
   110
526 
   111
527 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:12:7:12:12:@N::@XP_MSG">mips_uart.v(12)</a><!@TM:1223605618> | Synthesizing module uart0
528 
 
529 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:38:9:38:18:@W::@XP_MSG">mips_uart.v(38)</a><!@TM:1223605618> | No assignment to wire w_rxd_clr</font>
530 
 
531 
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:52:7:52:17:@N::@XP_MSG">dvc.v(52)</a><!@TM:1223605618> | Synthesizing module seg7led_cv
532 
 
533 
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:43:7:43:12:@N::@XP_MSG">dvc.v(43)</a><!@TM:1223605618> | Synthesizing module tmr_d
534 
 
535 
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:3:7:3:11:@N::@XP_MSG">dvc.v(3)</a><!@TM:1223605618> | Synthesizing module tmr0
536 
 
537 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_dvc.v:3:7:3:15:@N::@XP_MSG">mips_dvc.v(3)</a><!@TM:1223605618> | Synthesizing module mips_dvc
538 
 
539 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:4:7:4:15:@N::@XP_MSG">mips_sys.v(4)</a><!@TM:1223605618> | Synthesizing module mips_sys
540 
 
541 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:78:16:78:25:@W::@XP_MSG">mips_sys.v(78)</a><!@TM:1223605618> | No assignment to wire data2core</font>
542 
 
543 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:79:16:79:24:@W::@XP_MSG">mips_sys.v(79)</a><!@TM:1223605618> | No assignment to wire data2mem</font>
544 
 
545 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:80:16:80:24:@W::@XP_MSG">mips_sys.v(80)</a><!@TM:1223605618> | No assignment to wire ins2core</font>
546 
 
547 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:81:16:81:24:@W::@XP_MSG">mips_sys.v(81)</a><!@TM:1223605618> | No assignment to wire mem_Addr</font>
548 
 
549 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:82:16:82:18:@W::@XP_MSG">mips_sys.v(82)</a><!@TM:1223605618> | No assignment to wire pc</font>
550 
 
551 
<font color=#A52A2A>@W: : <a href="e:\mips789\mips789\rtl\verilog\mips_sys.v:83:15:83:20:@W::@XP_MSG">mips_sys.v(83)</a><!@TM:1223605618> | No assignment to wire wr_en</font>
552 
 
553 
@END
554 
Process took 0h:00m:11s realtime, 0h:00m:11s cputime
555 
# Fri Oct 10 10:26:56 2008
556 
 
557 
###########################################################[
558 
Version 8.1
559 
<a name=mapperReport25>Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
560 
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
561 
 
562 
 
563 
 
564 
Running FSM Explorer ...
565 
 
566 
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_din_ctl(mem_din_ctl)
567 
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_addr_ctl(mem_addr_ctl)
568 
Automatic dissolve at startup in view:work.mem_module(verilog) of dmem_ctl_post(infile_dmem_ctl_reg)
569 
Automatic dissolve at startup in view:work.rf_stage(verilog) of rs_fwd_rs(fwd_mux)
570 
Automatic dissolve at startup in view:work.rf_stage(verilog) of rf_fwd_rt(fwd_mux)
571 
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack2(jack)
572 
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack1(jack)
573 
Automatic dissolve at startup in view:work.rf_stage(verilog) of ins_reg(r32_reg_clr_cls)
574 
Automatic dissolve at startup in view:work.rf_stage(verilog) of i_pc_gen(pc_gen)
575 
Automatic dissolve at startup in view:work.exec_stage(verilog) of spc(r32_reg_cls)
576 
Automatic dissolve at startup in view:work.exec_stage(verilog) of pc_nxt(r32_reg)
577 
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxb(alu_muxb)
578 
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxa(alu_muxa)
579 
Automatic dissolve at startup in view:work.exec_stage(verilog) of dmem_fw_mux(fwd_mux)
580 
Automatic dissolve at startup in view:work.exec_stage(verilog) of add4(add32)
581 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U9(dmem_ctl_reg)
582 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U8(pc_gen_ctl_reg_clr_cls)
583 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U7(muxa_ctl_reg_clr_cls)
584 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U6(alu_we_reg_clr_cls)
585 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U5(rd_sel_reg_clr_cls)
586 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U4(ext_ctl_reg_clr_cls)
587 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U3(dmem_ctl_reg_clr_cls)
588 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U26(alu_func_reg_clr_cls)
589 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U24(alu_we_reg_clr)
590 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U22(wb_we_reg)
591 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U21(wb_mux_ctl_reg)
592 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U20(wb_we_reg)
593 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U2(cmp_ctl_reg_clr_cls)
594 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U19(wb_we_reg_clr)
595 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U18(wb_mux_ctl_reg)
596 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U17(muxa_ctl_reg_clr)
597 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U16(alu_func_reg_clr)
598 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U15(dmem_ctl_reg_clr)
599 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U14(muxb_ctl_reg_clr)
600 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U13(wb_mux_ctl_reg_clr)
601 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U12(wb_we_reg)
602 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U11(wb_we_reg_clr_cls)
603 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U10(wb_mux_ctl_reg_clr_cls)
604 
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U1(muxb_ctl_reg_clr_cls)
605 
Automatic dissolve at startup in view:work.decode_pipe(verilog) of pipereg(pipelinedregs)
606 
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rnt(fw_latch5)
607 
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rns(fw_latch5)
608 
Automatic dissolve at startup in view:work.mips_core(verilog) of wb_mux(wb_mux)
609 
Automatic dissolve at startup in view:work.mips_core(verilog) of rt_reg(r32_reg)
610 
Automatic dissolve at startup in view:work.mips_core(verilog) of rs_reg(r32_reg)
611 
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass2(r5_reg)
612 
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass1(r5_reg)
613 
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass0(r5_reg)
614 
Automatic dissolve at startup in view:work.mips_core(verilog) of pc(r32_reg)
615 
Automatic dissolve at startup in view:work.mips_core(verilog) of ext_reg(r32_reg)
616 
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_dout_reg(r32_reg)
617 
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_reg(r32_reg)
618 
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_or(or32)
619 
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass1(r32_reg)
620 
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass0(r32_reg)
621 
Automatic dissolve at startup in view:work.mips_core(verilog) of iexec_stage(exec_stage)
622 
Automatic dissolve at startup in view:work.mips_core(verilog) of iRF_stage(rf_stage)
623 
Automatic dissolve at startup in view:work.mips_core(verilog) of MEM_CTL(mem_module)
624 
Automatic dissolve at startup in view:work.uart_write(verilog) of fifo(fifo512_cyclone)
625 
Automatic dissolve at startup in view:work.uart0(verilog) of rxd_rdy_hold_lw(rxd_d)
626 
Automatic dissolve at startup in view:work.tmr0(verilog) of itmr_d(tmr_d)
627 
Warning: Found 30 combinational loops!
628 
         Each loop is reported with an instance in the loop
629 
         and nets connected to that instance.
630 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
631 
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
632 
    input nets to instance:
633 
        net "fsm_dly_2[0]" in work.decoder(verilog)
634 
        net "un1_fsm_dly370" in work.decoder(verilog)
635 
        net "un1_ins_i_21" in work.decoder(verilog)
636 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
637 
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
638 
    input nets to instance:
639 
        net "fsm_dly_2[1]" in work.decoder(verilog)
640 
        net "fsm_dly_2[2]" in work.decoder(verilog)
641 
        net "un1_fsm_dly370" in work.decoder(verilog)
642 
        net "un1_ins_i_21" in work.decoder(verilog)
643 
        net "GND" in work.decoder(verilog)
644 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
645 
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
646 
    input nets to instance:
647 
        net "fsm_dly_2[1]" in work.decoder(verilog)
648 
        net "fsm_dly_2[2]" in work.decoder(verilog)
649 
        net "un1_fsm_dly370" in work.decoder(verilog)
650 
        net "un1_ins_i_21" in work.decoder(verilog)
651 
        net "GND" in work.decoder(verilog)
652 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_1[0]</font>
653 
4) instance work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
654 
    input nets to instance:
655 
        net "ext_ctl_2[0]" in work.decoder(verilog)
656 
        net "un1_fsm_dly370" in work.decoder(verilog)
657 
        net "un1_ins_i_23" in work.decoder(verilog)
658 
        net "un1_ins_i_20" in work.decoder(verilog)
659 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_1[1]</font>
660 
5) instance work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
661 
    input nets to instance:
662 
        net "ext_ctl_2[1]" in work.decoder(verilog)
663 
        net "un1_fsm_dly370" in work.decoder(verilog)
664 
        net "un1_ins_i_21" in work.decoder(verilog)
665 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_1[2]</font>
666 
6) instance work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
667 
    input nets to instance:
668 
        net "ext_ctl_2[2]" in work.decoder(verilog)
669 
        net "un1_fsm_dly370" in work.decoder(verilog)
670 
        net "un1_ins_i_21" in work.decoder(verilog)
671 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net rd_sel_1[0]</font>
672 
7) instance work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
673 
    input nets to instance:
674 
        net "rd_sel_2[0]" in work.decoder(verilog)
675 
        net "un1_fsm_dly370" in work.decoder(verilog)
676 
        net "un1_ins_i_21" in work.decoder(verilog)
677 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net rd_sel_1[1]</font>
678 
8) instance work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
679 
    input nets to instance:
680 
        net "rd_sel_2[1]" in work.decoder(verilog)
681 
        net "un1_fsm_dly370" in work.decoder(verilog)
682 
        net "un1_ins_i_22" in work.decoder(verilog)
683 
        net "fsm_dly373" in work.decoder(verilog)
684 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_1[0]</font>
685 
9) instance work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
686 
    input nets to instance:
687 
        net "cmp_ctl_2[0]" in work.decoder(verilog)
688 
        net "un1_fsm_dly370" in work.decoder(verilog)
689 
        net "un1_ins_i_21" in work.decoder(verilog)
690 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_1[1]</font>
691 
10) instance work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
692 
    input nets to instance:
693 
        net "cmp_ctl_2[1]" in work.decoder(verilog)
694 
        net "un1_fsm_dly370" in work.decoder(verilog)
695 
        net "un1_ins_i_21" in work.decoder(verilog)
696 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_1[2]</font>
697 
11) instance work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
698 
    input nets to instance:
699 
        net "cmp_ctl_2[2]" in work.decoder(verilog)
700 
        net "un1_fsm_dly370" in work.decoder(verilog)
701 
        net "un1_ins_i_21" in work.decoder(verilog)
702 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_1[0]</font>
703 
12) instance work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
704 
    input nets to instance:
705 
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
706 
        net "un1_fsm_dly370" in work.decoder(verilog)
707 
        net "un1_ins_i_23" in work.decoder(verilog)
708 
        net "un1_ins_i_20" in work.decoder(verilog)
709 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_1[1]</font>
710 
13) instance work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
711 
    input nets to instance:
712 
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
713 
        net "un1_fsm_dly370" in work.decoder(verilog)
714 
        net "un1_ins_i_21" in work.decoder(verilog)
715 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_1[2]</font>
716 
14) instance work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
717 
    input nets to instance:
718 
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
719 
        net "un1_fsm_dly370" in work.decoder(verilog)
720 
        net "un1_ins_i_23" in work.decoder(verilog)
721 
        net "un1_ins_i_20" in work.decoder(verilog)
722 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxa_ctl_1[0]</font>
723 
15) instance work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
724 
    input nets to instance:
725 
        net "muxa_ctl_2[0]" in work.decoder(verilog)
726 
        net "un1_fsm_dly370" in work.decoder(verilog)
727 
        net "un1_ins_i_21" in work.decoder(verilog)
728 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxa_ctl_1[1]</font>
729 
16) instance work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
730 
    input nets to instance:
731 
        net "muxa_ctl_2[1]" in work.decoder(verilog)
732 
        net "un1_fsm_dly370" in work.decoder(verilog)
733 
        net "un1_ins_i_23" in work.decoder(verilog)
734 
        net "un1_ins_i_20" in work.decoder(verilog)
735 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxb_ctl_1[0]</font>
736 
17) instance work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
737 
    input nets to instance:
738 
        net "muxb_ctl_2[0]" in work.decoder(verilog)
739 
        net "un1_fsm_dly370" in work.decoder(verilog)
740 
        net "un1_ins_i_21" in work.decoder(verilog)
741 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxb_ctl_1[1]</font>
742 
18) instance work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
743 
    input nets to instance:
744 
        net "muxb_ctl_2[1]" in work.decoder(verilog)
745 
        net "un1_fsm_dly370" in work.decoder(verilog)
746 
        net "un1_ins_i_23" in work.decoder(verilog)
747 
        net "un1_ins_i_20" in work.decoder(verilog)
748 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[0]</font>
749 
19) instance work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
750 
    input nets to instance:
751 
        net "alu_func_2[0]" in work.decoder(verilog)
752 
        net "un1_fsm_dly370" in work.decoder(verilog)
753 
        net "un1_ins_i_21" in work.decoder(verilog)
754 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[1]</font>
755 
20) instance work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
756 
    input nets to instance:
757 
        net "alu_func_2[1]" in work.decoder(verilog)
758 
        net "un1_fsm_dly370" in work.decoder(verilog)
759 
        net "un1_ins_i_21" in work.decoder(verilog)
760 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[2]</font>
761 
21) instance work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
762 
    input nets to instance:
763 
        net "alu_func_2[2]" in work.decoder(verilog)
764 
        net "un1_fsm_dly370" in work.decoder(verilog)
765 
        net "un1_ins_i_23" in work.decoder(verilog)
766 
        net "un1_ins_i_20" in work.decoder(verilog)
767 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[3]</font>
768 
22) instance work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
769 
    input nets to instance:
770 
        net "alu_func_2[3]" in work.decoder(verilog)
771 
        net "un1_fsm_dly370" in work.decoder(verilog)
772 
        net "un1_ins_i_23" in work.decoder(verilog)
773 
        net "un1_ins_i_20" in work.decoder(verilog)
774 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_1[4]</font>
775 
23) instance work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
776 
    input nets to instance:
777 
        net "alu_func_2[4]" in work.decoder(verilog)
778 
        net "un1_fsm_dly370" in work.decoder(verilog)
779 
        net "un1_ins_i_21" in work.decoder(verilog)
780 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_1[0]</font>
781 
24) instance work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
782 
    input nets to instance:
783 
        net "dmem_ctl_2[0]" in work.decoder(verilog)
784 
        net "un1_fsm_dly370" in work.decoder(verilog)
785 
        net "un1_ins_i_23" in work.decoder(verilog)
786 
        net "un1_ins_i_20" in work.decoder(verilog)
787 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_1[1]</font>
788 
25) instance work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
789 
    input nets to instance:
790 
        net "dmem_ctl_2[1]" in work.decoder(verilog)
791 
        net "un1_fsm_dly370" in work.decoder(verilog)
792 
        net "un1_ins_i_22" in work.decoder(verilog)
793 
        net "fsm_dly373" in work.decoder(verilog)
794 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_1[2]</font>
795 
26) instance work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
796 
    input nets to instance:
797 
        net "dmem_ctl_2[2]" in work.decoder(verilog)
798 
        net "un1_fsm_dly370" in work.decoder(verilog)
799 
        net "un1_ins_i_24" in work.decoder(verilog)
800 
        net "un1_ins_i_15" in work.decoder(verilog)
801 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_1[3]</font>
802 
27) instance work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
803 
    input nets to instance:
804 
        net "dmem_ctl_2[3]" in work.decoder(verilog)
805 
        net "un1_fsm_dly370" in work.decoder(verilog)
806 
        net "un1_ins_i_21" in work.decoder(verilog)
807 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_we[0]</font>
808 
28) instance work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
809 
    input nets to instance:
810 
        net "alu_we_1[0]" in work.decoder(verilog)
811 
        net "un1_fsm_dly370" in work.decoder(verilog)
812 
        net "un1_ins_i_21" in work.decoder(verilog)
813 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net wb_mux[0]</font>
814 
29) instance work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
815 
    input nets to instance:
816 
        net "wb_mux_1[0]" in work.decoder(verilog)
817 
        net "un1_fsm_dly370" in work.decoder(verilog)
818 
        net "un1_ins_i_21" in work.decoder(verilog)
819 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net wb_we[0]</font>
820 
30) instance work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
821 
    input nets to instance:
822 
        net "wb_we_1[0]" in work.decoder(verilog)
823 
        net "un1_fsm_dly370" in work.decoder(verilog)
824 
        net "un1_ins_i_21" in work.decoder(verilog)
825 
End of loops
826 
RTL optimization done.
827 
Warning: Found 30 combinational loops!
828 
         Each loop is reported with an instance in the loop
829 
         and nets connected to that instance.
830 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
831 
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
832 
    input nets to instance:
833 
        net "fsm_dly_2[0]" in work.decoder(verilog)
834 
        net "un1_fsm_dly370" in work.decoder(verilog)
835 
        net "un1_ins_i_21" in work.decoder(verilog)
836 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
837 
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
838 
    input nets to instance:
839 
        net "fsm_dly_2[1]" in work.decoder(verilog)
840 
        net "fsm_dly_2[2]" in work.decoder(verilog)
841 
        net "un1_fsm_dly370" in work.decoder(verilog)
842 
        net "un1_ins_i_21" in work.decoder(verilog)
843 
        net "GND" in work.decoder(verilog)
844 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
845 
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
846 
    input nets to instance:
847 
        net "fsm_dly_2[1]" in work.decoder(verilog)
848 
        net "fsm_dly_2[2]" in work.decoder(verilog)
849 
        net "un1_fsm_dly370" in work.decoder(verilog)
850 
        net "un1_ins_i_21" in work.decoder(verilog)
851 
        net "GND" in work.decoder(verilog)
852 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net wb_mux_1[0]</font>
853 
4) instance work.decoder(verilog)-wb_mux_1[0], output net "wb_mux_1[0]" in work.decoder(verilog)
854 
    input nets to instance:
855 
        net "un1_alu_we_3_sqmuxa_4" in work.decoder(verilog)
856 
        net "GND" in work.decoder(verilog)
857 
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
858 
        net "wb_mux[0]" in work.decoder(verilog)
859 
        net "un1_fsm_dly365" in work.decoder(verilog)
860 
        net "VCC" in work.decoder(verilog)
861 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net wb_we_1[0]</font>
862 
5) instance work.decoder(verilog)-wb_we_1[0], output net "wb_we_1[0]" in work.decoder(verilog)
863 
    input nets to instance:
864 
        net "un1_alu_we_3_sqmuxa_3" in work.decoder(verilog)
865 
        net "GND" in work.decoder(verilog)
866 
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
867 
        net "wb_we[0]" in work.decoder(verilog)
868 
        net "un1_fsm_dly362" in work.decoder(verilog)
869 
        net "VCC" in work.decoder(verilog)
870 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[0]</font>
871 
6) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[0]" in work.decoder(verilog)
872 
    input nets to instance:
873 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
874 
        net "GND" in work.decoder(verilog)
875 
        net "VCC" in work.decoder(verilog)
876 
        net "GND" in work.decoder(verilog)
877 
        net "GND" in work.decoder(verilog)
878 
        net "GND" in work.decoder(verilog)
879 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
880 
        net "VCC" in work.decoder(verilog)
881 
        net "GND" in work.decoder(verilog)
882 
        net "GND" in work.decoder(verilog)
883 
        net "GND" in work.decoder(verilog)
884 
        net "GND" in work.decoder(verilog)
885 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
886 
        net "GND" in work.decoder(verilog)
887 
        net "GND" in work.decoder(verilog)
888 
        net "VCC" in work.decoder(verilog)
889 
        net "GND" in work.decoder(verilog)
890 
        net "GND" in work.decoder(verilog)
891 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
892 
        net "GND" in work.decoder(verilog)
893 
        net "GND" in work.decoder(verilog)
894 
        net "GND" in work.decoder(verilog)
895 
        net "GND" in work.decoder(verilog)
896 
        net "GND" in work.decoder(verilog)
897 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
898 
        net "GND" in work.decoder(verilog)
899 
        net "GND" in work.decoder(verilog)
900 
        net "GND" in work.decoder(verilog)
901 
        net "GND" in work.decoder(verilog)
902 
        net "GND" in work.decoder(verilog)
903 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
904 
        net "GND" in work.decoder(verilog)
905 
        net "GND" in work.decoder(verilog)
906 
        net "GND" in work.decoder(verilog)
907 
        net "GND" in work.decoder(verilog)
908 
        net "GND" in work.decoder(verilog)
909 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
910 
        net "GND" in work.decoder(verilog)
911 
        net "GND" in work.decoder(verilog)
912 
        net "GND" in work.decoder(verilog)
913 
        net "GND" in work.decoder(verilog)
914 
        net "GND" in work.decoder(verilog)
915 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
916 
        net "GND" in work.decoder(verilog)
917 
        net "GND" in work.decoder(verilog)
918 
        net "GND" in work.decoder(verilog)
919 
        net "GND" in work.decoder(verilog)
920 
        net "GND" in work.decoder(verilog)
921 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
922 
        net "GND" in work.decoder(verilog)
923 
        net "GND" in work.decoder(verilog)
924 
        net "GND" in work.decoder(verilog)
925 
        net "GND" in work.decoder(verilog)
926 
        net "GND" in work.decoder(verilog)
927 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
928 
        net "GND" in work.decoder(verilog)
929 
        net "GND" in work.decoder(verilog)
930 
        net "GND" in work.decoder(verilog)
931 
        net "GND" in work.decoder(verilog)
932 
        net "GND" in work.decoder(verilog)
933 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
934 
        net "GND" in work.decoder(verilog)
935 
        net "VCC" in work.decoder(verilog)
936 
        net "VCC" in work.decoder(verilog)
937 
        net "GND" in work.decoder(verilog)
938 
        net "GND" in work.decoder(verilog)
939 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
940 
        net "VCC" in work.decoder(verilog)
941 
        net "VCC" in work.decoder(verilog)
942 
        net "VCC" in work.decoder(verilog)
943 
        net "VCC" in work.decoder(verilog)
944 
        net "VCC" in work.decoder(verilog)
945 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
946 
        net "VCC" in work.decoder(verilog)
947 
        net "VCC" in work.decoder(verilog)
948 
        net "VCC" in work.decoder(verilog)
949 
        net "GND" in work.decoder(verilog)
950 
        net "GND" in work.decoder(verilog)
951 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
952 
        net "VCC" in work.decoder(verilog)
953 
        net "VCC" in work.decoder(verilog)
954 
        net "VCC" in work.decoder(verilog)
955 
        net "GND" in work.decoder(verilog)
956 
        net "GND" in work.decoder(verilog)
957 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
958 
        net "VCC" in work.decoder(verilog)
959 
        net "GND" in work.decoder(verilog)
960 
        net "GND" in work.decoder(verilog)
961 
        net "VCC" in work.decoder(verilog)
962 
        net "GND" in work.decoder(verilog)
963 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
964 
        net "GND" in work.decoder(verilog)
965 
        net "GND" in work.decoder(verilog)
966 
        net "GND" in work.decoder(verilog)
967 
        net "VCC" in work.decoder(verilog)
968 
        net "GND" in work.decoder(verilog)
969 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
970 
        net "VCC" in work.decoder(verilog)
971 
        net "VCC" in work.decoder(verilog)
972 
        net "GND" in work.decoder(verilog)
973 
        net "VCC" in work.decoder(verilog)
974 
        net "GND" in work.decoder(verilog)
975 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
976 
        net "GND" in work.decoder(verilog)
977 
        net "VCC" in work.decoder(verilog)
978 
        net "GND" in work.decoder(verilog)
979 
        net "VCC" in work.decoder(verilog)
980 
        net "GND" in work.decoder(verilog)
981 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
982 
        net "GND" in work.decoder(verilog)
983 
        net "GND" in work.decoder(verilog)
984 
        net "VCC" in work.decoder(verilog)
985 
        net "VCC" in work.decoder(verilog)
986 
        net "GND" in work.decoder(verilog)
987 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
988 
        net "GND" in work.decoder(verilog)
989 
        net "GND" in work.decoder(verilog)
990 
        net "VCC" in work.decoder(verilog)
991 
        net "VCC" in work.decoder(verilog)
992 
        net "GND" in work.decoder(verilog)
993 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
994 
        net "GND" in work.decoder(verilog)
995 
        net "VCC" in work.decoder(verilog)
996 
        net "VCC" in work.decoder(verilog)
997 
        net "VCC" in work.decoder(verilog)
998 
        net "GND" in work.decoder(verilog)
999 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
1000 
        net "VCC" in work.decoder(verilog)
1001 
        net "VCC" in work.decoder(verilog)
1002 
        net "VCC" in work.decoder(verilog)
1003 
        net "VCC" in work.decoder(verilog)
1004 
        net "GND" in work.decoder(verilog)
1005 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
1006 
        net "VCC" in work.decoder(verilog)
1007 
        net "VCC" in work.decoder(verilog)
1008 
        net "GND" in work.decoder(verilog)
1009 
        net "GND" in work.decoder(verilog)
1010 
        net "VCC" in work.decoder(verilog)
1011 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
1012 
        net "GND" in work.decoder(verilog)
1013 
        net "VCC" in work.decoder(verilog)
1014 
        net "GND" in work.decoder(verilog)
1015 
        net "GND" in work.decoder(verilog)
1016 
        net "VCC" in work.decoder(verilog)
1017 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
1018 
        net "GND" in work.decoder(verilog)
1019 
        net "GND" in work.decoder(verilog)
1020 
        net "VCC" in work.decoder(verilog)
1021 
        net "GND" in work.decoder(verilog)
1022 
        net "VCC" in work.decoder(verilog)
1023 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
1024 
        net "VCC" in work.decoder(verilog)
1025 
        net "GND" in work.decoder(verilog)
1026 
        net "VCC" in work.decoder(verilog)
1027 
        net "GND" in work.decoder(verilog)
1028 
        net "VCC" in work.decoder(verilog)
1029 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
1030 
        net "VCC" in work.decoder(verilog)
1031 
        net "GND" in work.decoder(verilog)
1032 
        net "GND" in work.decoder(verilog)
1033 
        net "GND" in work.decoder(verilog)
1034 
        net "VCC" in work.decoder(verilog)
1035 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
1036 
        net "GND" in work.decoder(verilog)
1037 
        net "GND" in work.decoder(verilog)
1038 
        net "GND" in work.decoder(verilog)
1039 
        net "GND" in work.decoder(verilog)
1040 
        net "VCC" in work.decoder(verilog)
1041 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
1042 
        net "GND" in work.decoder(verilog)
1043 
        net "GND" in work.decoder(verilog)
1044 
        net "GND" in work.decoder(verilog)
1045 
        net "GND" in work.decoder(verilog)
1046 
        net "GND" in work.decoder(verilog)
1047 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
1048 
        net "GND" in work.decoder(verilog)
1049 
        net "GND" in work.decoder(verilog)
1050 
        net "GND" in work.decoder(verilog)
1051 
        net "GND" in work.decoder(verilog)
1052 
        net "GND" in work.decoder(verilog)
1053 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
1054 
        net "GND" in work.decoder(verilog)
1055 
        net "GND" in work.decoder(verilog)
1056 
        net "GND" in work.decoder(verilog)
1057 
        net "GND" in work.decoder(verilog)
1058 
        net "GND" in work.decoder(verilog)
1059 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
1060 
        net "GND" in work.decoder(verilog)
1061 
        net "GND" in work.decoder(verilog)
1062 
        net "GND" in work.decoder(verilog)
1063 
        net "GND" in work.decoder(verilog)
1064 
        net "GND" in work.decoder(verilog)
1065 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
1066 
        net "alu_func_1[0]" in work.decoder(verilog)
1067 
        net "alu_func_1[1]" in work.decoder(verilog)
1068 
        net "alu_func_1[2]" in work.decoder(verilog)
1069 
        net "alu_func_1[3]" in work.decoder(verilog)
1070 
        net "alu_func_1[4]" in work.decoder(verilog)
1071 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
1072 
        net "alu_func_1[0]" in work.decoder(verilog)
1073 
        net "alu_func_1[1]" in work.decoder(verilog)
1074 
        net "alu_func_1[2]" in work.decoder(verilog)
1075 
        net "alu_func_1[3]" in work.decoder(verilog)
1076 
        net "alu_func_1[4]" in work.decoder(verilog)
1077 
        net "fsm_dly350" in work.decoder(verilog)
1078 
        net "GND" in work.decoder(verilog)
1079 
        net "GND" in work.decoder(verilog)
1080 
        net "GND" in work.decoder(verilog)
1081 
        net "GND" in work.decoder(verilog)
1082 
        net "GND" in work.decoder(verilog)
1083 
        net "fsm_dly351" in work.decoder(verilog)
1084 
        net "GND" in work.decoder(verilog)
1085 
        net "VCC" in work.decoder(verilog)
1086 
        net "VCC" in work.decoder(verilog)
1087 
        net "GND" in work.decoder(verilog)
1088 
        net "VCC" in work.decoder(verilog)
1089 
        net "fsm_dly352" in work.decoder(verilog)
1090 
        net "GND" in work.decoder(verilog)
1091 
        net "GND" in work.decoder(verilog)
1092 
        net "GND" in work.decoder(verilog)
1093 
        net "GND" in work.decoder(verilog)
1094 
        net "GND" in work.decoder(verilog)
1095 
        net "fsm_dly353" in work.decoder(verilog)
1096 
        net "GND" in work.decoder(verilog)
1097 
        net "GND" in work.decoder(verilog)
1098 
        net "GND" in work.decoder(verilog)
1099 
        net "GND" in work.decoder(verilog)
1100 
        net "GND" in work.decoder(verilog)
1101 
        net "fsm_dly354" in work.decoder(verilog)
1102 
        net "GND" in work.decoder(verilog)
1103 
        net "GND" in work.decoder(verilog)
1104 
        net "GND" in work.decoder(verilog)
1105 
        net "GND" in work.decoder(verilog)
1106 
        net "GND" in work.decoder(verilog)
1107 
        net "fsm_dly355" in work.decoder(verilog)
1108 
        net "GND" in work.decoder(verilog)
1109 
        net "GND" in work.decoder(verilog)
1110 
        net "GND" in work.decoder(verilog)
1111 
        net "GND" in work.decoder(verilog)
1112 
        net "GND" in work.decoder(verilog)
1113 
        net "fsm_dly356" in work.decoder(verilog)
1114 
        net "GND" in work.decoder(verilog)
1115 
        net "GND" in work.decoder(verilog)
1116 
        net "VCC" in work.decoder(verilog)
1117 
        net "VCC" in work.decoder(verilog)
1118 
        net "GND" in work.decoder(verilog)
1119 
        net "fsm_dly357" in work.decoder(verilog)
1120 
        net "GND" in work.decoder(verilog)
1121 
        net "GND" in work.decoder(verilog)
1122 
        net "VCC" in work.decoder(verilog)
1123 
        net "VCC" in work.decoder(verilog)
1124 
        net "GND" in work.decoder(verilog)
1125 
        net "fsm_dly358" in work.decoder(verilog)
1126 
        net "VCC" in work.decoder(verilog)
1127 
        net "GND" in work.decoder(verilog)
1128 
        net "GND" in work.decoder(verilog)
1129 
        net "GND" in work.decoder(verilog)
1130 
        net "VCC" in work.decoder(verilog)
1131 
        net "fsm_dly359" in work.decoder(verilog)
1132 
        net "GND" in work.decoder(verilog)
1133 
        net "GND" in work.decoder(verilog)
1134 
        net "GND" in work.decoder(verilog)
1135 
        net "GND" in work.decoder(verilog)
1136 
        net "VCC" in work.decoder(verilog)
1137 
        net "fsm_dly360" in work.decoder(verilog)
1138 
        net "VCC" in work.decoder(verilog)
1139 
        net "VCC" in work.decoder(verilog)
1140 
        net "GND" in work.decoder(verilog)
1141 
        net "GND" in work.decoder(verilog)
1142 
        net "VCC" in work.decoder(verilog)
1143 
        net "fsm_dly361" in work.decoder(verilog)
1144 
        net "GND" in work.decoder(verilog)
1145 
        net "VCC" in work.decoder(verilog)
1146 
        net "GND" in work.decoder(verilog)
1147 
        net "GND" in work.decoder(verilog)
1148 
        net "VCC" in work.decoder(verilog)
1149 
        net "fsm_dly362" in work.decoder(verilog)
1150 
        net "GND" in work.decoder(verilog)
1151 
        net "GND" in work.decoder(verilog)
1152 
        net "VCC" in work.decoder(verilog)
1153 
        net "GND" in work.decoder(verilog)
1154 
        net "VCC" in work.decoder(verilog)
1155 
        net "fsm_dly363" in work.decoder(verilog)
1156 
        net "VCC" in work.decoder(verilog)
1157 
        net "VCC" in work.decoder(verilog)
1158 
        net "VCC" in work.decoder(verilog)
1159 
        net "GND" in work.decoder(verilog)
1160 
        net "VCC" in work.decoder(verilog)
1161 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
1162 
        net "GND" in work.decoder(verilog)
1163 
        net "VCC" in work.decoder(verilog)
1164 
        net "VCC" in work.decoder(verilog)
1165 
        net "GND" in work.decoder(verilog)
1166 
        net "VCC" in work.decoder(verilog)
1167 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
1168 
        net "GND" in work.decoder(verilog)
1169 
        net "GND" in work.decoder(verilog)
1170 
        net "GND" in work.decoder(verilog)
1171 
        net "GND" in work.decoder(verilog)
1172 
        net "GND" in work.decoder(verilog)
1173 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
1174 
        net "alu_func_1[0]" in work.decoder(verilog)
1175 
        net "alu_func_1[1]" in work.decoder(verilog)
1176 
        net "alu_func_1[2]" in work.decoder(verilog)
1177 
        net "alu_func_1[3]" in work.decoder(verilog)
1178 
        net "alu_func_1[4]" in work.decoder(verilog)
1179 
        net "fsm_dly365" in work.decoder(verilog)
1180 
        net "GND" in work.decoder(verilog)
1181 
        net "GND" in work.decoder(verilog)
1182 
        net "VCC" in work.decoder(verilog)
1183 
        net "VCC" in work.decoder(verilog)
1184 
        net "GND" in work.decoder(verilog)
1185 
        net "fsm_dly366" in work.decoder(verilog)
1186 
        net "GND" in work.decoder(verilog)
1187 
        net "GND" in work.decoder(verilog)
1188 
        net "VCC" in work.decoder(verilog)
1189 
        net "VCC" in work.decoder(verilog)
1190 
        net "GND" in work.decoder(verilog)
1191 
        net "fsm_dly367" in work.decoder(verilog)
1192 
        net "GND" in work.decoder(verilog)
1193 
        net "GND" in work.decoder(verilog)
1194 
        net "GND" in work.decoder(verilog)
1195 
        net "GND" in work.decoder(verilog)
1196 
        net "GND" in work.decoder(verilog)
1197 
        net "fsm_dly368" in work.decoder(verilog)
1198 
        net "GND" in work.decoder(verilog)
1199 
        net "GND" in work.decoder(verilog)
1200 
        net "VCC" in work.decoder(verilog)
1201 
        net "VCC" in work.decoder(verilog)
1202 
        net "GND" in work.decoder(verilog)
1203 
        net "fsm_dly369" in work.decoder(verilog)
1204 
        net "GND" in work.decoder(verilog)
1205 
        net "GND" in work.decoder(verilog)
1206 
        net "VCC" in work.decoder(verilog)
1207 
        net "VCC" in work.decoder(verilog)
1208 
        net "GND" in work.decoder(verilog)
1209 
        net "fsm_dly370" in work.decoder(verilog)
1210 
        net "GND" in work.decoder(verilog)
1211 
        net "GND" in work.decoder(verilog)
1212 
        net "VCC" in work.decoder(verilog)
1213 
        net "VCC" in work.decoder(verilog)
1214 
        net "GND" in work.decoder(verilog)
1215 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[1]</font>
1216 
7) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[1]" in work.decoder(verilog)
1217 
    input nets to instance:
1218 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
1219 
        net "GND" in work.decoder(verilog)
1220 
        net "VCC" in work.decoder(verilog)
1221 
        net "GND" in work.decoder(verilog)
1222 
        net "GND" in work.decoder(verilog)
1223 
        net "GND" in work.decoder(verilog)
1224 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
1225 
        net "VCC" in work.decoder(verilog)
1226 
        net "GND" in work.decoder(verilog)
1227 
        net "GND" in work.decoder(verilog)
1228 
        net "GND" in work.decoder(verilog)
1229 
        net "GND" in work.decoder(verilog)
1230 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
1231 
        net "GND" in work.decoder(verilog)
1232 
        net "GND" in work.decoder(verilog)
1233 
        net "VCC" in work.decoder(verilog)
1234 
        net "GND" in work.decoder(verilog)
1235 
        net "GND" in work.decoder(verilog)
1236 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
1237 
        net "GND" in work.decoder(verilog)
1238 
        net "GND" in work.decoder(verilog)
1239 
        net "GND" in work.decoder(verilog)
1240 
        net "GND" in work.decoder(verilog)
1241 
        net "GND" in work.decoder(verilog)
1242 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
1243 
        net "GND" in work.decoder(verilog)
1244 
        net "GND" in work.decoder(verilog)
1245 
        net "GND" in work.decoder(verilog)
1246 
        net "GND" in work.decoder(verilog)
1247 
        net "GND" in work.decoder(verilog)
1248 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
1249 
        net "GND" in work.decoder(verilog)
1250 
        net "GND" in work.decoder(verilog)
1251 
        net "GND" in work.decoder(verilog)
1252 
        net "GND" in work.decoder(verilog)
1253 
        net "GND" in work.decoder(verilog)
1254 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
1255 
        net "GND" in work.decoder(verilog)
1256 
        net "GND" in work.decoder(verilog)
1257 
        net "GND" in work.decoder(verilog)
1258 
        net "GND" in work.decoder(verilog)
1259 
        net "GND" in work.decoder(verilog)
1260 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
1261 
        net "GND" in work.decoder(verilog)
1262 
        net "GND" in work.decoder(verilog)
1263 
        net "GND" in work.decoder(verilog)
1264 
        net "GND" in work.decoder(verilog)
1265 
        net "GND" in work.decoder(verilog)
1266 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
1267 
        net "GND" in work.decoder(verilog)
1268 
        net "GND" in work.decoder(verilog)
1269 
        net "GND" in work.decoder(verilog)
1270 
        net "GND" in work.decoder(verilog)
1271 
        net "GND" in work.decoder(verilog)
1272 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
1273 
        net "GND" in work.decoder(verilog)
1274 
        net "GND" in work.decoder(verilog)
1275 
        net "GND" in work.decoder(verilog)
1276 
        net "GND" in work.decoder(verilog)
1277 
        net "GND" in work.decoder(verilog)
1278 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
1279 
        net "GND" in work.decoder(verilog)
1280 
        net "VCC" in work.decoder(verilog)
1281 
        net "VCC" in work.decoder(verilog)
1282 
        net "GND" in work.decoder(verilog)
1283 
        net "GND" in work.decoder(verilog)
1284 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
1285 
        net "VCC" in work.decoder(verilog)
1286 
        net "VCC" in work.decoder(verilog)
1287 
        net "VCC" in work.decoder(verilog)
1288 
        net "VCC" in work.decoder(verilog)
1289 
        net "VCC" in work.decoder(verilog)
1290 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
1291 
        net "VCC" in work.decoder(verilog)
1292 
        net "VCC" in work.decoder(verilog)
1293 
        net "VCC" in work.decoder(verilog)
1294 
        net "GND" in work.decoder(verilog)
1295 
        net "GND" in work.decoder(verilog)
1296 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
1297 
        net "VCC" in work.decoder(verilog)
1298 
        net "VCC" in work.decoder(verilog)
1299 
        net "VCC" in work.decoder(verilog)
1300 
        net "GND" in work.decoder(verilog)
1301 
        net "GND" in work.decoder(verilog)
1302 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
1303 
        net "VCC" in work.decoder(verilog)
1304 
        net "GND" in work.decoder(verilog)
1305 
        net "GND" in work.decoder(verilog)
1306 
        net "VCC" in work.decoder(verilog)
1307 
        net "GND" in work.decoder(verilog)
1308 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
1309 
        net "GND" in work.decoder(verilog)
1310 
        net "GND" in work.decoder(verilog)
1311 
        net "GND" in work.decoder(verilog)
1312 
        net "VCC" in work.decoder(verilog)
1313 
        net "GND" in work.decoder(verilog)
1314 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
1315 
        net "VCC" in work.decoder(verilog)
1316 
        net "VCC" in work.decoder(verilog)
1317 
        net "GND" in work.decoder(verilog)
1318 
        net "VCC" in work.decoder(verilog)
1319 
        net "GND" in work.decoder(verilog)
1320 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
1321 
        net "GND" in work.decoder(verilog)
1322 
        net "VCC" in work.decoder(verilog)
1323 
        net "GND" in work.decoder(verilog)
1324 
        net "VCC" in work.decoder(verilog)
1325 
        net "GND" in work.decoder(verilog)
1326 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
1327 
        net "GND" in work.decoder(verilog)
1328 
        net "GND" in work.decoder(verilog)
1329 
        net "VCC" in work.decoder(verilog)
1330 
        net "VCC" in work.decoder(verilog)
1331 
        net "GND" in work.decoder(verilog)
1332 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
1333 
        net "GND" in work.decoder(verilog)
1334 
        net "GND" in work.decoder(verilog)
1335 
        net "VCC" in work.decoder(verilog)
1336 
        net "VCC" in work.decoder(verilog)
1337 
        net "GND" in work.decoder(verilog)
1338 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
1339 
        net "GND" in work.decoder(verilog)
1340 
        net "VCC" in work.decoder(verilog)
1341 
        net "VCC" in work.decoder(verilog)
1342 
        net "VCC" in work.decoder(verilog)
1343 
        net "GND" in work.decoder(verilog)
1344 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
1345 
        net "VCC" in work.decoder(verilog)
1346 
        net "VCC" in work.decoder(verilog)
1347 
        net "VCC" in work.decoder(verilog)
1348 
        net "VCC" in work.decoder(verilog)
1349 
        net "GND" in work.decoder(verilog)
1350 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
1351 
        net "VCC" in work.decoder(verilog)
1352 
        net "VCC" in work.decoder(verilog)
1353 
        net "GND" in work.decoder(verilog)
1354 
        net "GND" in work.decoder(verilog)
1355 
        net "VCC" in work.decoder(verilog)
1356 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
1357 
        net "GND" in work.decoder(verilog)
1358 
        net "VCC" in work.decoder(verilog)
1359 
        net "GND" in work.decoder(verilog)
1360 
        net "GND" in work.decoder(verilog)
1361 
        net "VCC" in work.decoder(verilog)
1362 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
1363 
        net "GND" in work.decoder(verilog)
1364 
        net "GND" in work.decoder(verilog)
1365 
        net "VCC" in work.decoder(verilog)
1366 
        net "GND" in work.decoder(verilog)
1367 
        net "VCC" in work.decoder(verilog)
1368 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
1369 
        net "VCC" in work.decoder(verilog)
1370 
        net "GND" in work.decoder(verilog)
1371 
        net "VCC" in work.decoder(verilog)
1372 
        net "GND" in work.decoder(verilog)
1373 
        net "VCC" in work.decoder(verilog)
1374 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
1375 
        net "VCC" in work.decoder(verilog)
1376 
        net "GND" in work.decoder(verilog)
1377 
        net "GND" in work.decoder(verilog)
1378 
        net "GND" in work.decoder(verilog)
1379 
        net "VCC" in work.decoder(verilog)
1380 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
1381 
        net "GND" in work.decoder(verilog)
1382 
        net "GND" in work.decoder(verilog)
1383 
        net "GND" in work.decoder(verilog)
1384 
        net "GND" in work.decoder(verilog)
1385 
        net "VCC" in work.decoder(verilog)
1386 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
1387 
        net "GND" in work.decoder(verilog)
1388 
        net "GND" in work.decoder(verilog)
1389 
        net "GND" in work.decoder(verilog)
1390 
        net "GND" in work.decoder(verilog)
1391 
        net "GND" in work.decoder(verilog)
1392 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
1393 
        net "GND" in work.decoder(verilog)
1394 
        net "GND" in work.decoder(verilog)
1395 
        net "GND" in work.decoder(verilog)
1396 
        net "GND" in work.decoder(verilog)
1397 
        net "GND" in work.decoder(verilog)
1398 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
1399 
        net "GND" in work.decoder(verilog)
1400 
        net "GND" in work.decoder(verilog)
1401 
        net "GND" in work.decoder(verilog)
1402 
        net "GND" in work.decoder(verilog)
1403 
        net "GND" in work.decoder(verilog)
1404 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
1405 
        net "GND" in work.decoder(verilog)
1406 
        net "GND" in work.decoder(verilog)
1407 
        net "GND" in work.decoder(verilog)
1408 
        net "GND" in work.decoder(verilog)
1409 
        net "GND" in work.decoder(verilog)
1410 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
1411 
        net "alu_func_1[0]" in work.decoder(verilog)
1412 
        net "alu_func_1[1]" in work.decoder(verilog)
1413 
        net "alu_func_1[2]" in work.decoder(verilog)
1414 
        net "alu_func_1[3]" in work.decoder(verilog)
1415 
        net "alu_func_1[4]" in work.decoder(verilog)
1416 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
1417 
        net "alu_func_1[0]" in work.decoder(verilog)
1418 
        net "alu_func_1[1]" in work.decoder(verilog)
1419 
        net "alu_func_1[2]" in work.decoder(verilog)
1420 
        net "alu_func_1[3]" in work.decoder(verilog)
1421 
        net "alu_func_1[4]" in work.decoder(verilog)
1422 
        net "fsm_dly350" in work.decoder(verilog)
1423 
        net "GND" in work.decoder(verilog)
1424 
        net "GND" in work.decoder(verilog)
1425 
        net "GND" in work.decoder(verilog)
1426 
        net "GND" in work.decoder(verilog)
1427 
        net "GND" in work.decoder(verilog)
1428 
        net "fsm_dly351" in work.decoder(verilog)
1429 
        net "GND" in work.decoder(verilog)
1430 
        net "VCC" in work.decoder(verilog)
1431 
        net "VCC" in work.decoder(verilog)
1432 
        net "GND" in work.decoder(verilog)
1433 
        net "VCC" in work.decoder(verilog)
1434 
        net "fsm_dly352" in work.decoder(verilog)
1435 
        net "GND" in work.decoder(verilog)
1436 
        net "GND" in work.decoder(verilog)
1437 
        net "GND" in work.decoder(verilog)
1438 
        net "GND" in work.decoder(verilog)
1439 
        net "GND" in work.decoder(verilog)
1440 
        net "fsm_dly353" in work.decoder(verilog)
1441 
        net "GND" in work.decoder(verilog)
1442 
        net "GND" in work.decoder(verilog)
1443 
        net "GND" in work.decoder(verilog)
1444 
        net "GND" in work.decoder(verilog)
1445 
        net "GND" in work.decoder(verilog)
1446 
        net "fsm_dly354" in work.decoder(verilog)
1447 
        net "GND" in work.decoder(verilog)
1448 
        net "GND" in work.decoder(verilog)
1449 
        net "GND" in work.decoder(verilog)
1450 
        net "GND" in work.decoder(verilog)
1451 
        net "GND" in work.decoder(verilog)
1452 
        net "fsm_dly355" in work.decoder(verilog)
1453 
        net "GND" in work.decoder(verilog)
1454 
        net "GND" in work.decoder(verilog)
1455 
        net "GND" in work.decoder(verilog)
1456 
        net "GND" in work.decoder(verilog)
1457 
        net "GND" in work.decoder(verilog)
1458 
        net "fsm_dly356" in work.decoder(verilog)
1459 
        net "GND" in work.decoder(verilog)
1460 
        net "GND" in work.decoder(verilog)
1461 
        net "VCC" in work.decoder(verilog)
1462 
        net "VCC" in work.decoder(verilog)
1463 
        net "GND" in work.decoder(verilog)
1464 
        net "fsm_dly357" in work.decoder(verilog)
1465 
        net "GND" in work.decoder(verilog)
1466 
        net "GND" in work.decoder(verilog)
1467 
        net "VCC" in work.decoder(verilog)
1468 
        net "VCC" in work.decoder(verilog)
1469 
        net "GND" in work.decoder(verilog)
1470 
        net "fsm_dly358" in work.decoder(verilog)
1471 
        net "VCC" in work.decoder(verilog)
1472 
        net "GND" in work.decoder(verilog)
1473 
        net "GND" in work.decoder(verilog)
1474 
        net "GND" in work.decoder(verilog)
1475 
        net "VCC" in work.decoder(verilog)
1476 
        net "fsm_dly359" in work.decoder(verilog)
1477 
        net "GND" in work.decoder(verilog)
1478 
        net "GND" in work.decoder(verilog)
1479 
        net "GND" in work.decoder(verilog)
1480 
        net "GND" in work.decoder(verilog)
1481 
        net "VCC" in work.decoder(verilog)
1482 
        net "fsm_dly360" in work.decoder(verilog)
1483 
        net "VCC" in work.decoder(verilog)
1484 
        net "VCC" in work.decoder(verilog)
1485 
        net "GND" in work.decoder(verilog)
1486 
        net "GND" in work.decoder(verilog)
1487 
        net "VCC" in work.decoder(verilog)
1488 
        net "fsm_dly361" in work.decoder(verilog)
1489 
        net "GND" in work.decoder(verilog)
1490 
        net "VCC" in work.decoder(verilog)
1491 
        net "GND" in work.decoder(verilog)
1492 
        net "GND" in work.decoder(verilog)
1493 
        net "VCC" in work.decoder(verilog)
1494 
        net "fsm_dly362" in work.decoder(verilog)
1495 
        net "GND" in work.decoder(verilog)
1496 
        net "GND" in work.decoder(verilog)
1497 
        net "VCC" in work.decoder(verilog)
1498 
        net "GND" in work.decoder(verilog)
1499 
        net "VCC" in work.decoder(verilog)
1500 
        net "fsm_dly363" in work.decoder(verilog)
1501 
        net "VCC" in work.decoder(verilog)
1502 
        net "VCC" in work.decoder(verilog)
1503 
        net "VCC" in work.decoder(verilog)
1504 
        net "GND" in work.decoder(verilog)
1505 
        net "VCC" in work.decoder(verilog)
1506 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
1507 
        net "GND" in work.decoder(verilog)
1508 
        net "VCC" in work.decoder(verilog)
1509 
        net "VCC" in work.decoder(verilog)
1510 
        net "GND" in work.decoder(verilog)
1511 
        net "VCC" in work.decoder(verilog)
1512 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
1513 
        net "GND" in work.decoder(verilog)
1514 
        net "GND" in work.decoder(verilog)
1515 
        net "GND" in work.decoder(verilog)
1516 
        net "GND" in work.decoder(verilog)
1517 
        net "GND" in work.decoder(verilog)
1518 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
1519 
        net "alu_func_1[0]" in work.decoder(verilog)
1520 
        net "alu_func_1[1]" in work.decoder(verilog)
1521 
        net "alu_func_1[2]" in work.decoder(verilog)
1522 
        net "alu_func_1[3]" in work.decoder(verilog)
1523 
        net "alu_func_1[4]" in work.decoder(verilog)
1524 
        net "fsm_dly365" in work.decoder(verilog)
1525 
        net "GND" in work.decoder(verilog)
1526 
        net "GND" in work.decoder(verilog)
1527 
        net "VCC" in work.decoder(verilog)
1528 
        net "VCC" in work.decoder(verilog)
1529 
        net "GND" in work.decoder(verilog)
1530 
        net "fsm_dly366" in work.decoder(verilog)
1531 
        net "GND" in work.decoder(verilog)
1532 
        net "GND" in work.decoder(verilog)
1533 
        net "VCC" in work.decoder(verilog)
1534 
        net "VCC" in work.decoder(verilog)
1535 
        net "GND" in work.decoder(verilog)
1536 
        net "fsm_dly367" in work.decoder(verilog)
1537 
        net "GND" in work.decoder(verilog)
1538 
        net "GND" in work.decoder(verilog)
1539 
        net "GND" in work.decoder(verilog)
1540 
        net "GND" in work.decoder(verilog)
1541 
        net "GND" in work.decoder(verilog)
1542 
        net "fsm_dly368" in work.decoder(verilog)
1543 
        net "GND" in work.decoder(verilog)
1544 
        net "GND" in work.decoder(verilog)
1545 
        net "VCC" in work.decoder(verilog)
1546 
        net "VCC" in work.decoder(verilog)
1547 
        net "GND" in work.decoder(verilog)
1548 
        net "fsm_dly369" in work.decoder(verilog)
1549 
        net "GND" in work.decoder(verilog)
1550 
        net "GND" in work.decoder(verilog)
1551 
        net "VCC" in work.decoder(verilog)
1552 
        net "VCC" in work.decoder(verilog)
1553 
        net "GND" in work.decoder(verilog)
1554 
        net "fsm_dly370" in work.decoder(verilog)
1555 
        net "GND" in work.decoder(verilog)
1556 
        net "GND" in work.decoder(verilog)
1557 
        net "VCC" in work.decoder(verilog)
1558 
        net "VCC" in work.decoder(verilog)
1559 
        net "GND" in work.decoder(verilog)
1560 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[2]</font>
1561 
8) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[2]" in work.decoder(verilog)
1562 
    input nets to instance:
1563 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
1564 
        net "GND" in work.decoder(verilog)
1565 
        net "VCC" in work.decoder(verilog)
1566 
        net "GND" in work.decoder(verilog)
1567 
        net "GND" in work.decoder(verilog)
1568 
        net "GND" in work.decoder(verilog)
1569 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
1570 
        net "VCC" in work.decoder(verilog)
1571 
        net "GND" in work.decoder(verilog)
1572 
        net "GND" in work.decoder(verilog)
1573 
        net "GND" in work.decoder(verilog)
1574 
        net "GND" in work.decoder(verilog)
1575 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
1576 
        net "GND" in work.decoder(verilog)
1577 
        net "GND" in work.decoder(verilog)
1578 
        net "VCC" in work.decoder(verilog)
1579 
        net "GND" in work.decoder(verilog)
1580 
        net "GND" in work.decoder(verilog)
1581 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
1582 
        net "GND" in work.decoder(verilog)
1583 
        net "GND" in work.decoder(verilog)
1584 
        net "GND" in work.decoder(verilog)
1585 
        net "GND" in work.decoder(verilog)
1586 
        net "GND" in work.decoder(verilog)
1587 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
1588 
        net "GND" in work.decoder(verilog)
1589 
        net "GND" in work.decoder(verilog)
1590 
        net "GND" in work.decoder(verilog)
1591 
        net "GND" in work.decoder(verilog)
1592 
        net "GND" in work.decoder(verilog)
1593 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
1594 
        net "GND" in work.decoder(verilog)
1595 
        net "GND" in work.decoder(verilog)
1596 
        net "GND" in work.decoder(verilog)
1597 
        net "GND" in work.decoder(verilog)
1598 
        net "GND" in work.decoder(verilog)
1599 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
1600 
        net "GND" in work.decoder(verilog)
1601 
        net "GND" in work.decoder(verilog)
1602 
        net "GND" in work.decoder(verilog)
1603 
        net "GND" in work.decoder(verilog)
1604 
        net "GND" in work.decoder(verilog)
1605 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
1606 
        net "GND" in work.decoder(verilog)
1607 
        net "GND" in work.decoder(verilog)
1608 
        net "GND" in work.decoder(verilog)
1609 
        net "GND" in work.decoder(verilog)
1610 
        net "GND" in work.decoder(verilog)
1611 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
1612 
        net "GND" in work.decoder(verilog)
1613 
        net "GND" in work.decoder(verilog)
1614 
        net "GND" in work.decoder(verilog)
1615 
        net "GND" in work.decoder(verilog)
1616 
        net "GND" in work.decoder(verilog)
1617 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
1618 
        net "GND" in work.decoder(verilog)
1619 
        net "GND" in work.decoder(verilog)
1620 
        net "GND" in work.decoder(verilog)
1621 
        net "GND" in work.decoder(verilog)
1622 
        net "GND" in work.decoder(verilog)
1623 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
1624 
        net "GND" in work.decoder(verilog)
1625 
        net "VCC" in work.decoder(verilog)
1626 
        net "VCC" in work.decoder(verilog)
1627 
        net "GND" in work.decoder(verilog)
1628 
        net "GND" in work.decoder(verilog)
1629 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
1630 
        net "VCC" in work.decoder(verilog)
1631 
        net "VCC" in work.decoder(verilog)
1632 
        net "VCC" in work.decoder(verilog)
1633 
        net "VCC" in work.decoder(verilog)
1634 
        net "VCC" in work.decoder(verilog)
1635 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
1636 
        net "VCC" in work.decoder(verilog)
1637 
        net "VCC" in work.decoder(verilog)
1638 
        net "VCC" in work.decoder(verilog)
1639 
        net "GND" in work.decoder(verilog)
1640 
        net "GND" in work.decoder(verilog)
1641 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
1642 
        net "VCC" in work.decoder(verilog)
1643 
        net "VCC" in work.decoder(verilog)
1644 
        net "VCC" in work.decoder(verilog)
1645 
        net "GND" in work.decoder(verilog)
1646 
        net "GND" in work.decoder(verilog)
1647 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
1648 
        net "VCC" in work.decoder(verilog)
1649 
        net "GND" in work.decoder(verilog)
1650 
        net "GND" in work.decoder(verilog)
1651 
        net "VCC" in work.decoder(verilog)
1652 
        net "GND" in work.decoder(verilog)
1653 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
1654 
        net "GND" in work.decoder(verilog)
1655 
        net "GND" in work.decoder(verilog)
1656 
        net "GND" in work.decoder(verilog)
1657 
        net "VCC" in work.decoder(verilog)
1658 
        net "GND" in work.decoder(verilog)
1659 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
1660 
        net "VCC" in work.decoder(verilog)
1661 
        net "VCC" in work.decoder(verilog)
1662 
        net "GND" in work.decoder(verilog)
1663 
        net "VCC" in work.decoder(verilog)
1664 
        net "GND" in work.decoder(verilog)
1665 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
1666 
        net "GND" in work.decoder(verilog)
1667 
        net "VCC" in work.decoder(verilog)
1668 
        net "GND" in work.decoder(verilog)
1669 
        net "VCC" in work.decoder(verilog)
1670 
        net "GND" in work.decoder(verilog)
1671 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
1672 
        net "GND" in work.decoder(verilog)
1673 
        net "GND" in work.decoder(verilog)
1674 
        net "VCC" in work.decoder(verilog)
1675 
        net "VCC" in work.decoder(verilog)
1676 
        net "GND" in work.decoder(verilog)
1677 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
1678 
        net "GND" in work.decoder(verilog)
1679 
        net "GND" in work.decoder(verilog)
1680 
        net "VCC" in work.decoder(verilog)
1681 
        net "VCC" in work.decoder(verilog)
1682 
        net "GND" in work.decoder(verilog)
1683 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
1684 
        net "GND" in work.decoder(verilog)
1685 
        net "VCC" in work.decoder(verilog)
1686 
        net "VCC" in work.decoder(verilog)
1687 
        net "VCC" in work.decoder(verilog)
1688 
        net "GND" in work.decoder(verilog)
1689 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
1690 
        net "VCC" in work.decoder(verilog)
1691 
        net "VCC" in work.decoder(verilog)
1692 
        net "VCC" in work.decoder(verilog)
1693 
        net "VCC" in work.decoder(verilog)
1694 
        net "GND" in work.decoder(verilog)
1695 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
1696 
        net "VCC" in work.decoder(verilog)
1697 
        net "VCC" in work.decoder(verilog)
1698 
        net "GND" in work.decoder(verilog)
1699 
        net "GND" in work.decoder(verilog)
1700 
        net "VCC" in work.decoder(verilog)
1701 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
1702 
        net "GND" in work.decoder(verilog)
1703 
        net "VCC" in work.decoder(verilog)
1704 
        net "GND" in work.decoder(verilog)
1705 
        net "GND" in work.decoder(verilog)
1706 
        net "VCC" in work.decoder(verilog)
1707 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
1708 
        net "GND" in work.decoder(verilog)
1709 
        net "GND" in work.decoder(verilog)
1710 
        net "VCC" in work.decoder(verilog)
1711 
        net "GND" in work.decoder(verilog)
1712 
        net "VCC" in work.decoder(verilog)
1713 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
1714 
        net "VCC" in work.decoder(verilog)
1715 
        net "GND" in work.decoder(verilog)
1716 
        net "VCC" in work.decoder(verilog)
1717 
        net "GND" in work.decoder(verilog)
1718 
        net "VCC" in work.decoder(verilog)
1719 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
1720 
        net "VCC" in work.decoder(verilog)
1721 
        net "GND" in work.decoder(verilog)
1722 
        net "GND" in work.decoder(verilog)
1723 
        net "GND" in work.decoder(verilog)
1724 
        net "VCC" in work.decoder(verilog)
1725 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
1726 
        net "GND" in work.decoder(verilog)
1727 
        net "GND" in work.decoder(verilog)
1728 
        net "GND" in work.decoder(verilog)
1729 
        net "GND" in work.decoder(verilog)
1730 
        net "VCC" in work.decoder(verilog)
1731 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
1732 
        net "GND" in work.decoder(verilog)
1733 
        net "GND" in work.decoder(verilog)
1734 
        net "GND" in work.decoder(verilog)
1735 
        net "GND" in work.decoder(verilog)
1736 
        net "GND" in work.decoder(verilog)
1737 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
1738 
        net "GND" in work.decoder(verilog)
1739 
        net "GND" in work.decoder(verilog)
1740 
        net "GND" in work.decoder(verilog)
1741 
        net "GND" in work.decoder(verilog)
1742 
        net "GND" in work.decoder(verilog)
1743 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
1744 
        net "GND" in work.decoder(verilog)
1745 
        net "GND" in work.decoder(verilog)
1746 
        net "GND" in work.decoder(verilog)
1747 
        net "GND" in work.decoder(verilog)
1748 
        net "GND" in work.decoder(verilog)
1749 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
1750 
        net "GND" in work.decoder(verilog)
1751 
        net "GND" in work.decoder(verilog)
1752 
        net "GND" in work.decoder(verilog)
1753 
        net "GND" in work.decoder(verilog)
1754 
        net "GND" in work.decoder(verilog)
1755 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
1756 
        net "alu_func_1[0]" in work.decoder(verilog)
1757 
        net "alu_func_1[1]" in work.decoder(verilog)
1758 
        net "alu_func_1[2]" in work.decoder(verilog)
1759 
        net "alu_func_1[3]" in work.decoder(verilog)
1760 
        net "alu_func_1[4]" in work.decoder(verilog)
1761 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
1762 
        net "alu_func_1[0]" in work.decoder(verilog)
1763 
        net "alu_func_1[1]" in work.decoder(verilog)
1764 
        net "alu_func_1[2]" in work.decoder(verilog)
1765 
        net "alu_func_1[3]" in work.decoder(verilog)
1766 
        net "alu_func_1[4]" in work.decoder(verilog)
1767 
        net "fsm_dly350" in work.decoder(verilog)
1768 
        net "GND" in work.decoder(verilog)
1769 
        net "GND" in work.decoder(verilog)
1770 
        net "GND" in work.decoder(verilog)
1771 
        net "GND" in work.decoder(verilog)
1772 
        net "GND" in work.decoder(verilog)
1773 
        net "fsm_dly351" in work.decoder(verilog)
1774 
        net "GND" in work.decoder(verilog)
1775 
        net "VCC" in work.decoder(verilog)
1776 
        net "VCC" in work.decoder(verilog)
1777 
        net "GND" in work.decoder(verilog)
1778 
        net "VCC" in work.decoder(verilog)
1779 
        net "fsm_dly352" in work.decoder(verilog)
1780 
        net "GND" in work.decoder(verilog)
1781 
        net "GND" in work.decoder(verilog)
1782 
        net "GND" in work.decoder(verilog)
1783 
        net "GND" in work.decoder(verilog)
1784 
        net "GND" in work.decoder(verilog)
1785 
        net "fsm_dly353" in work.decoder(verilog)
1786 
        net "GND" in work.decoder(verilog)
1787 
        net "GND" in work.decoder(verilog)
1788 
        net "GND" in work.decoder(verilog)
1789 
        net "GND" in work.decoder(verilog)
1790 
        net "GND" in work.decoder(verilog)
1791 
        net "fsm_dly354" in work.decoder(verilog)
1792 
        net "GND" in work.decoder(verilog)
1793 
        net "GND" in work.decoder(verilog)
1794 
        net "GND" in work.decoder(verilog)
1795 
        net "GND" in work.decoder(verilog)
1796 
        net "GND" in work.decoder(verilog)
1797 
        net "fsm_dly355" in work.decoder(verilog)
1798 
        net "GND" in work.decoder(verilog)
1799 
        net "GND" in work.decoder(verilog)
1800 
        net "GND" in work.decoder(verilog)
1801 
        net "GND" in work.decoder(verilog)
1802 
        net "GND" in work.decoder(verilog)
1803 
        net "fsm_dly356" in work.decoder(verilog)
1804 
        net "GND" in work.decoder(verilog)
1805 
        net "GND" in work.decoder(verilog)
1806 
        net "VCC" in work.decoder(verilog)
1807 
        net "VCC" in work.decoder(verilog)
1808 
        net "GND" in work.decoder(verilog)
1809 
        net "fsm_dly357" in work.decoder(verilog)
1810 
        net "GND" in work.decoder(verilog)
1811 
        net "GND" in work.decoder(verilog)
1812 
        net "VCC" in work.decoder(verilog)
1813 
        net "VCC" in work.decoder(verilog)
1814 
        net "GND" in work.decoder(verilog)
1815 
        net "fsm_dly358" in work.decoder(verilog)
1816 
        net "VCC" in work.decoder(verilog)
1817 
        net "GND" in work.decoder(verilog)
1818 
        net "GND" in work.decoder(verilog)
1819 
        net "GND" in work.decoder(verilog)
1820 
        net "VCC" in work.decoder(verilog)
1821 
        net "fsm_dly359" in work.decoder(verilog)
1822 
        net "GND" in work.decoder(verilog)
1823 
        net "GND" in work.decoder(verilog)
1824 
        net "GND" in work.decoder(verilog)
1825 
        net "GND" in work.decoder(verilog)
1826 
        net "VCC" in work.decoder(verilog)
1827 
        net "fsm_dly360" in work.decoder(verilog)
1828 
        net "VCC" in work.decoder(verilog)
1829 
        net "VCC" in work.decoder(verilog)
1830 
        net "GND" in work.decoder(verilog)
1831 
        net "GND" in work.decoder(verilog)
1832 
        net "VCC" in work.decoder(verilog)
1833 
        net "fsm_dly361" in work.decoder(verilog)
1834 
        net "GND" in work.decoder(verilog)
1835 
        net "VCC" in work.decoder(verilog)
1836 
        net "GND" in work.decoder(verilog)
1837 
        net "GND" in work.decoder(verilog)
1838 
        net "VCC" in work.decoder(verilog)
1839 
        net "fsm_dly362" in work.decoder(verilog)
1840 
        net "GND" in work.decoder(verilog)
1841 
        net "GND" in work.decoder(verilog)
1842 
        net "VCC" in work.decoder(verilog)
1843 
        net "GND" in work.decoder(verilog)
1844 
        net "VCC" in work.decoder(verilog)
1845 
        net "fsm_dly363" in work.decoder(verilog)
1846 
        net "VCC" in work.decoder(verilog)
1847 
        net "VCC" in work.decoder(verilog)
1848 
        net "VCC" in work.decoder(verilog)
1849 
        net "GND" in work.decoder(verilog)
1850 
        net "VCC" in work.decoder(verilog)
1851 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
1852 
        net "GND" in work.decoder(verilog)
1853 
        net "VCC" in work.decoder(verilog)
1854 
        net "VCC" in work.decoder(verilog)
1855 
        net "GND" in work.decoder(verilog)
1856 
        net "VCC" in work.decoder(verilog)
1857 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
1858 
        net "GND" in work.decoder(verilog)
1859 
        net "GND" in work.decoder(verilog)
1860 
        net "GND" in work.decoder(verilog)
1861 
        net "GND" in work.decoder(verilog)
1862 
        net "GND" in work.decoder(verilog)
1863 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
1864 
        net "alu_func_1[0]" in work.decoder(verilog)
1865 
        net "alu_func_1[1]" in work.decoder(verilog)
1866 
        net "alu_func_1[2]" in work.decoder(verilog)
1867 
        net "alu_func_1[3]" in work.decoder(verilog)
1868 
        net "alu_func_1[4]" in work.decoder(verilog)
1869 
        net "fsm_dly365" in work.decoder(verilog)
1870 
        net "GND" in work.decoder(verilog)
1871 
        net "GND" in work.decoder(verilog)
1872 
        net "VCC" in work.decoder(verilog)
1873 
        net "VCC" in work.decoder(verilog)
1874 
        net "GND" in work.decoder(verilog)
1875 
        net "fsm_dly366" in work.decoder(verilog)
1876 
        net "GND" in work.decoder(verilog)
1877 
        net "GND" in work.decoder(verilog)
1878 
        net "VCC" in work.decoder(verilog)
1879 
        net "VCC" in work.decoder(verilog)
1880 
        net "GND" in work.decoder(verilog)
1881 
        net "fsm_dly367" in work.decoder(verilog)
1882 
        net "GND" in work.decoder(verilog)
1883 
        net "GND" in work.decoder(verilog)
1884 
        net "GND" in work.decoder(verilog)
1885 
        net "GND" in work.decoder(verilog)
1886 
        net "GND" in work.decoder(verilog)
1887 
        net "fsm_dly368" in work.decoder(verilog)
1888 
        net "GND" in work.decoder(verilog)
1889 
        net "GND" in work.decoder(verilog)
1890 
        net "VCC" in work.decoder(verilog)
1891 
        net "VCC" in work.decoder(verilog)
1892 
        net "GND" in work.decoder(verilog)
1893 
        net "fsm_dly369" in work.decoder(verilog)
1894 
        net "GND" in work.decoder(verilog)
1895 
        net "GND" in work.decoder(verilog)
1896 
        net "VCC" in work.decoder(verilog)
1897 
        net "VCC" in work.decoder(verilog)
1898 
        net "GND" in work.decoder(verilog)
1899 
        net "fsm_dly370" in work.decoder(verilog)
1900 
        net "GND" in work.decoder(verilog)
1901 
        net "GND" in work.decoder(verilog)
1902 
        net "VCC" in work.decoder(verilog)
1903 
        net "VCC" in work.decoder(verilog)
1904 
        net "GND" in work.decoder(verilog)
1905 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[3]</font>
1906 
9) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[3]" in work.decoder(verilog)
1907 
    input nets to instance:
1908 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
1909 
        net "GND" in work.decoder(verilog)
1910 
        net "VCC" in work.decoder(verilog)
1911 
        net "GND" in work.decoder(verilog)
1912 
        net "GND" in work.decoder(verilog)
1913 
        net "GND" in work.decoder(verilog)
1914 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
1915 
        net "VCC" in work.decoder(verilog)
1916 
        net "GND" in work.decoder(verilog)
1917 
        net "GND" in work.decoder(verilog)
1918 
        net "GND" in work.decoder(verilog)
1919 
        net "GND" in work.decoder(verilog)
1920 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
1921 
        net "GND" in work.decoder(verilog)
1922 
        net "GND" in work.decoder(verilog)
1923 
        net "VCC" in work.decoder(verilog)
1924 
        net "GND" in work.decoder(verilog)
1925 
        net "GND" in work.decoder(verilog)
1926 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
1927 
        net "GND" in work.decoder(verilog)
1928 
        net "GND" in work.decoder(verilog)
1929 
        net "GND" in work.decoder(verilog)
1930 
        net "GND" in work.decoder(verilog)
1931 
        net "GND" in work.decoder(verilog)
1932 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
1933 
        net "GND" in work.decoder(verilog)
1934 
        net "GND" in work.decoder(verilog)
1935 
        net "GND" in work.decoder(verilog)
1936 
        net "GND" in work.decoder(verilog)
1937 
        net "GND" in work.decoder(verilog)
1938 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
1939 
        net "GND" in work.decoder(verilog)
1940 
        net "GND" in work.decoder(verilog)
1941 
        net "GND" in work.decoder(verilog)
1942 
        net "GND" in work.decoder(verilog)
1943 
        net "GND" in work.decoder(verilog)
1944 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
1945 
        net "GND" in work.decoder(verilog)
1946 
        net "GND" in work.decoder(verilog)
1947 
        net "GND" in work.decoder(verilog)
1948 
        net "GND" in work.decoder(verilog)
1949 
        net "GND" in work.decoder(verilog)
1950 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
1951 
        net "GND" in work.decoder(verilog)
1952 
        net "GND" in work.decoder(verilog)
1953 
        net "GND" in work.decoder(verilog)
1954 
        net "GND" in work.decoder(verilog)
1955 
        net "GND" in work.decoder(verilog)
1956 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
1957 
        net "GND" in work.decoder(verilog)
1958 
        net "GND" in work.decoder(verilog)
1959 
        net "GND" in work.decoder(verilog)
1960 
        net "GND" in work.decoder(verilog)
1961 
        net "GND" in work.decoder(verilog)
1962 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
1963 
        net "GND" in work.decoder(verilog)
1964 
        net "GND" in work.decoder(verilog)
1965 
        net "GND" in work.decoder(verilog)
1966 
        net "GND" in work.decoder(verilog)
1967 
        net "GND" in work.decoder(verilog)
1968 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
1969 
        net "GND" in work.decoder(verilog)
1970 
        net "VCC" in work.decoder(verilog)
1971 
        net "VCC" in work.decoder(verilog)
1972 
        net "GND" in work.decoder(verilog)
1973 
        net "GND" in work.decoder(verilog)
1974 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
1975 
        net "VCC" in work.decoder(verilog)
1976 
        net "VCC" in work.decoder(verilog)
1977 
        net "VCC" in work.decoder(verilog)
1978 
        net "VCC" in work.decoder(verilog)
1979 
        net "VCC" in work.decoder(verilog)
1980 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
1981 
        net "VCC" in work.decoder(verilog)
1982 
        net "VCC" in work.decoder(verilog)
1983 
        net "VCC" in work.decoder(verilog)
1984 
        net "GND" in work.decoder(verilog)
1985 
        net "GND" in work.decoder(verilog)
1986 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
1987 
        net "VCC" in work.decoder(verilog)
1988 
        net "VCC" in work.decoder(verilog)
1989 
        net "VCC" in work.decoder(verilog)
1990 
        net "GND" in work.decoder(verilog)
1991 
        net "GND" in work.decoder(verilog)
1992 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
1993 
        net "VCC" in work.decoder(verilog)
1994 
        net "GND" in work.decoder(verilog)
1995 
        net "GND" in work.decoder(verilog)
1996 
        net "VCC" in work.decoder(verilog)
1997 
        net "GND" in work.decoder(verilog)
1998 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
1999 
        net "GND" in work.decoder(verilog)
2000 
        net "GND" in work.decoder(verilog)
2001 
        net "GND" in work.decoder(verilog)
2002 
        net "VCC" in work.decoder(verilog)
2003 
        net "GND" in work.decoder(verilog)
2004 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
2005 
        net "VCC" in work.decoder(verilog)
2006 
        net "VCC" in work.decoder(verilog)
2007 
        net "GND" in work.decoder(verilog)
2008 
        net "VCC" in work.decoder(verilog)
2009 
        net "GND" in work.decoder(verilog)
2010 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
2011 
        net "GND" in work.decoder(verilog)
2012 
        net "VCC" in work.decoder(verilog)
2013 
        net "GND" in work.decoder(verilog)
2014 
        net "VCC" in work.decoder(verilog)
2015 
        net "GND" in work.decoder(verilog)
2016 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
2017 
        net "GND" in work.decoder(verilog)
2018 
        net "GND" in work.decoder(verilog)
2019 
        net "VCC" in work.decoder(verilog)
2020 
        net "VCC" in work.decoder(verilog)
2021 
        net "GND" in work.decoder(verilog)
2022 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
2023 
        net "GND" in work.decoder(verilog)
2024 
        net "GND" in work.decoder(verilog)
2025 
        net "VCC" in work.decoder(verilog)
2026 
        net "VCC" in work.decoder(verilog)
2027 
        net "GND" in work.decoder(verilog)
2028 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
2029 
        net "GND" in work.decoder(verilog)
2030 
        net "VCC" in work.decoder(verilog)
2031 
        net "VCC" in work.decoder(verilog)
2032 
        net "VCC" in work.decoder(verilog)
2033 
        net "GND" in work.decoder(verilog)
2034 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
2035 
        net "VCC" in work.decoder(verilog)
2036 
        net "VCC" in work.decoder(verilog)
2037 
        net "VCC" in work.decoder(verilog)
2038 
        net "VCC" in work.decoder(verilog)
2039 
        net "GND" in work.decoder(verilog)
2040 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
2041 
        net "VCC" in work.decoder(verilog)
2042 
        net "VCC" in work.decoder(verilog)
2043 
        net "GND" in work.decoder(verilog)
2044 
        net "GND" in work.decoder(verilog)
2045 
        net "VCC" in work.decoder(verilog)
2046 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
2047 
        net "GND" in work.decoder(verilog)
2048 
        net "VCC" in work.decoder(verilog)
2049 
        net "GND" in work.decoder(verilog)
2050 
        net "GND" in work.decoder(verilog)
2051 
        net "VCC" in work.decoder(verilog)
2052 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
2053 
        net "GND" in work.decoder(verilog)
2054 
        net "GND" in work.decoder(verilog)
2055 
        net "VCC" in work.decoder(verilog)
2056 
        net "GND" in work.decoder(verilog)
2057 
        net "VCC" in work.decoder(verilog)
2058 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
2059 
        net "VCC" in work.decoder(verilog)
2060 
        net "GND" in work.decoder(verilog)
2061 
        net "VCC" in work.decoder(verilog)
2062 
        net "GND" in work.decoder(verilog)
2063 
        net "VCC" in work.decoder(verilog)
2064 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
2065 
        net "VCC" in work.decoder(verilog)
2066 
        net "GND" in work.decoder(verilog)
2067 
        net "GND" in work.decoder(verilog)
2068 
        net "GND" in work.decoder(verilog)
2069 
        net "VCC" in work.decoder(verilog)
2070 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
2071 
        net "GND" in work.decoder(verilog)
2072 
        net "GND" in work.decoder(verilog)
2073 
        net "GND" in work.decoder(verilog)
2074 
        net "GND" in work.decoder(verilog)
2075 
        net "VCC" in work.decoder(verilog)
2076 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
2077 
        net "GND" in work.decoder(verilog)
2078 
        net "GND" in work.decoder(verilog)
2079 
        net "GND" in work.decoder(verilog)
2080 
        net "GND" in work.decoder(verilog)
2081 
        net "GND" in work.decoder(verilog)
2082 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
2083 
        net "GND" in work.decoder(verilog)
2084 
        net "GND" in work.decoder(verilog)
2085 
        net "GND" in work.decoder(verilog)
2086 
        net "GND" in work.decoder(verilog)
2087 
        net "GND" in work.decoder(verilog)
2088 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
2089 
        net "GND" in work.decoder(verilog)
2090 
        net "GND" in work.decoder(verilog)
2091 
        net "GND" in work.decoder(verilog)
2092 
        net "GND" in work.decoder(verilog)
2093 
        net "GND" in work.decoder(verilog)
2094 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
2095 
        net "GND" in work.decoder(verilog)
2096 
        net "GND" in work.decoder(verilog)
2097 
        net "GND" in work.decoder(verilog)
2098 
        net "GND" in work.decoder(verilog)
2099 
        net "GND" in work.decoder(verilog)
2100 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
2101 
        net "alu_func_1[0]" in work.decoder(verilog)
2102 
        net "alu_func_1[1]" in work.decoder(verilog)
2103 
        net "alu_func_1[2]" in work.decoder(verilog)
2104 
        net "alu_func_1[3]" in work.decoder(verilog)
2105 
        net "alu_func_1[4]" in work.decoder(verilog)
2106 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
2107 
        net "alu_func_1[0]" in work.decoder(verilog)
2108 
        net "alu_func_1[1]" in work.decoder(verilog)
2109 
        net "alu_func_1[2]" in work.decoder(verilog)
2110 
        net "alu_func_1[3]" in work.decoder(verilog)
2111 
        net "alu_func_1[4]" in work.decoder(verilog)
2112 
        net "fsm_dly350" in work.decoder(verilog)
2113 
        net "GND" in work.decoder(verilog)
2114 
        net "GND" in work.decoder(verilog)
2115 
        net "GND" in work.decoder(verilog)
2116 
        net "GND" in work.decoder(verilog)
2117 
        net "GND" in work.decoder(verilog)
2118 
        net "fsm_dly351" in work.decoder(verilog)
2119 
        net "GND" in work.decoder(verilog)
2120 
        net "VCC" in work.decoder(verilog)
2121 
        net "VCC" in work.decoder(verilog)
2122 
        net "GND" in work.decoder(verilog)
2123 
        net "VCC" in work.decoder(verilog)
2124 
        net "fsm_dly352" in work.decoder(verilog)
2125 
        net "GND" in work.decoder(verilog)
2126 
        net "GND" in work.decoder(verilog)
2127 
        net "GND" in work.decoder(verilog)
2128 
        net "GND" in work.decoder(verilog)
2129 
        net "GND" in work.decoder(verilog)
2130 
        net "fsm_dly353" in work.decoder(verilog)
2131 
        net "GND" in work.decoder(verilog)
2132 
        net "GND" in work.decoder(verilog)
2133 
        net "GND" in work.decoder(verilog)
2134 
        net "GND" in work.decoder(verilog)
2135 
        net "GND" in work.decoder(verilog)
2136 
        net "fsm_dly354" in work.decoder(verilog)
2137 
        net "GND" in work.decoder(verilog)
2138 
        net "GND" in work.decoder(verilog)
2139 
        net "GND" in work.decoder(verilog)
2140 
        net "GND" in work.decoder(verilog)
2141 
        net "GND" in work.decoder(verilog)
2142 
        net "fsm_dly355" in work.decoder(verilog)
2143 
        net "GND" in work.decoder(verilog)
2144 
        net "GND" in work.decoder(verilog)
2145 
        net "GND" in work.decoder(verilog)
2146 
        net "GND" in work.decoder(verilog)
2147 
        net "GND" in work.decoder(verilog)
2148 
        net "fsm_dly356" in work.decoder(verilog)
2149 
        net "GND" in work.decoder(verilog)
2150 
        net "GND" in work.decoder(verilog)
2151 
        net "VCC" in work.decoder(verilog)
2152 
        net "VCC" in work.decoder(verilog)
2153 
        net "GND" in work.decoder(verilog)
2154 
        net "fsm_dly357" in work.decoder(verilog)
2155 
        net "GND" in work.decoder(verilog)
2156 
        net "GND" in work.decoder(verilog)
2157 
        net "VCC" in work.decoder(verilog)
2158 
        net "VCC" in work.decoder(verilog)
2159 
        net "GND" in work.decoder(verilog)
2160 
        net "fsm_dly358" in work.decoder(verilog)
2161 
        net "VCC" in work.decoder(verilog)
2162 
        net "GND" in work.decoder(verilog)
2163 
        net "GND" in work.decoder(verilog)
2164 
        net "GND" in work.decoder(verilog)
2165 
        net "VCC" in work.decoder(verilog)
2166 
        net "fsm_dly359" in work.decoder(verilog)
2167 
        net "GND" in work.decoder(verilog)
2168 
        net "GND" in work.decoder(verilog)
2169 
        net "GND" in work.decoder(verilog)
2170 
        net "GND" in work.decoder(verilog)
2171 
        net "VCC" in work.decoder(verilog)
2172 
        net "fsm_dly360" in work.decoder(verilog)
2173 
        net "VCC" in work.decoder(verilog)
2174 
        net "VCC" in work.decoder(verilog)
2175 
        net "GND" in work.decoder(verilog)
2176 
        net "GND" in work.decoder(verilog)
2177 
        net "VCC" in work.decoder(verilog)
2178 
        net "fsm_dly361" in work.decoder(verilog)
2179 
        net "GND" in work.decoder(verilog)
2180 
        net "VCC" in work.decoder(verilog)
2181 
        net "GND" in work.decoder(verilog)
2182 
        net "GND" in work.decoder(verilog)
2183 
        net "VCC" in work.decoder(verilog)
2184 
        net "fsm_dly362" in work.decoder(verilog)
2185 
        net "GND" in work.decoder(verilog)
2186 
        net "GND" in work.decoder(verilog)
2187 
        net "VCC" in work.decoder(verilog)
2188 
        net "GND" in work.decoder(verilog)
2189 
        net "VCC" in work.decoder(verilog)
2190 
        net "fsm_dly363" in work.decoder(verilog)
2191 
        net "VCC" in work.decoder(verilog)
2192 
        net "VCC" in work.decoder(verilog)
2193 
        net "VCC" in work.decoder(verilog)
2194 
        net "GND" in work.decoder(verilog)
2195 
        net "VCC" in work.decoder(verilog)
2196 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
2197 
        net "GND" in work.decoder(verilog)
2198 
        net "VCC" in work.decoder(verilog)
2199 
        net "VCC" in work.decoder(verilog)
2200 
        net "GND" in work.decoder(verilog)
2201 
        net "VCC" in work.decoder(verilog)
2202 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
2203 
        net "GND" in work.decoder(verilog)
2204 
        net "GND" in work.decoder(verilog)
2205 
        net "GND" in work.decoder(verilog)
2206 
        net "GND" in work.decoder(verilog)
2207 
        net "GND" in work.decoder(verilog)
2208 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
2209 
        net "alu_func_1[0]" in work.decoder(verilog)
2210 
        net "alu_func_1[1]" in work.decoder(verilog)
2211 
        net "alu_func_1[2]" in work.decoder(verilog)
2212 
        net "alu_func_1[3]" in work.decoder(verilog)
2213 
        net "alu_func_1[4]" in work.decoder(verilog)
2214 
        net "fsm_dly365" in work.decoder(verilog)
2215 
        net "GND" in work.decoder(verilog)
2216 
        net "GND" in work.decoder(verilog)
2217 
        net "VCC" in work.decoder(verilog)
2218 
        net "VCC" in work.decoder(verilog)
2219 
        net "GND" in work.decoder(verilog)
2220 
        net "fsm_dly366" in work.decoder(verilog)
2221 
        net "GND" in work.decoder(verilog)
2222 
        net "GND" in work.decoder(verilog)
2223 
        net "VCC" in work.decoder(verilog)
2224 
        net "VCC" in work.decoder(verilog)
2225 
        net "GND" in work.decoder(verilog)
2226 
        net "fsm_dly367" in work.decoder(verilog)
2227 
        net "GND" in work.decoder(verilog)
2228 
        net "GND" in work.decoder(verilog)
2229 
        net "GND" in work.decoder(verilog)
2230 
        net "GND" in work.decoder(verilog)
2231 
        net "GND" in work.decoder(verilog)
2232 
        net "fsm_dly368" in work.decoder(verilog)
2233 
        net "GND" in work.decoder(verilog)
2234 
        net "GND" in work.decoder(verilog)
2235 
        net "VCC" in work.decoder(verilog)
2236 
        net "VCC" in work.decoder(verilog)
2237 
        net "GND" in work.decoder(verilog)
2238 
        net "fsm_dly369" in work.decoder(verilog)
2239 
        net "GND" in work.decoder(verilog)
2240 
        net "GND" in work.decoder(verilog)
2241 
        net "VCC" in work.decoder(verilog)
2242 
        net "VCC" in work.decoder(verilog)
2243 
        net "GND" in work.decoder(verilog)
2244 
        net "fsm_dly370" in work.decoder(verilog)
2245 
        net "GND" in work.decoder(verilog)
2246 
        net "GND" in work.decoder(verilog)
2247 
        net "VCC" in work.decoder(verilog)
2248 
        net "VCC" in work.decoder(verilog)
2249 
        net "GND" in work.decoder(verilog)
2250 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_func_2[4]</font>
2251 
10) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[4]" in work.decoder(verilog)
2252 
    input nets to instance:
2253 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
2254 
        net "GND" in work.decoder(verilog)
2255 
        net "VCC" in work.decoder(verilog)
2256 
        net "GND" in work.decoder(verilog)
2257 
        net "GND" in work.decoder(verilog)
2258 
        net "GND" in work.decoder(verilog)
2259 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
2260 
        net "VCC" in work.decoder(verilog)
2261 
        net "GND" in work.decoder(verilog)
2262 
        net "GND" in work.decoder(verilog)
2263 
        net "GND" in work.decoder(verilog)
2264 
        net "GND" in work.decoder(verilog)
2265 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
2266 
        net "GND" in work.decoder(verilog)
2267 
        net "GND" in work.decoder(verilog)
2268 
        net "VCC" in work.decoder(verilog)
2269 
        net "GND" in work.decoder(verilog)
2270 
        net "GND" in work.decoder(verilog)
2271 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
2272 
        net "GND" in work.decoder(verilog)
2273 
        net "GND" in work.decoder(verilog)
2274 
        net "GND" in work.decoder(verilog)
2275 
        net "GND" in work.decoder(verilog)
2276 
        net "GND" in work.decoder(verilog)
2277 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
2278 
        net "GND" in work.decoder(verilog)
2279 
        net "GND" in work.decoder(verilog)
2280 
        net "GND" in work.decoder(verilog)
2281 
        net "GND" in work.decoder(verilog)
2282 
        net "GND" in work.decoder(verilog)
2283 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
2284 
        net "GND" in work.decoder(verilog)
2285 
        net "GND" in work.decoder(verilog)
2286 
        net "GND" in work.decoder(verilog)
2287 
        net "GND" in work.decoder(verilog)
2288 
        net "GND" in work.decoder(verilog)
2289 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
2290 
        net "GND" in work.decoder(verilog)
2291 
        net "GND" in work.decoder(verilog)
2292 
        net "GND" in work.decoder(verilog)
2293 
        net "GND" in work.decoder(verilog)
2294 
        net "GND" in work.decoder(verilog)
2295 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
2296 
        net "GND" in work.decoder(verilog)
2297 
        net "GND" in work.decoder(verilog)
2298 
        net "GND" in work.decoder(verilog)
2299 
        net "GND" in work.decoder(verilog)
2300 
        net "GND" in work.decoder(verilog)
2301 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
2302 
        net "GND" in work.decoder(verilog)
2303 
        net "GND" in work.decoder(verilog)
2304 
        net "GND" in work.decoder(verilog)
2305 
        net "GND" in work.decoder(verilog)
2306 
        net "GND" in work.decoder(verilog)
2307 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
2308 
        net "GND" in work.decoder(verilog)
2309 
        net "GND" in work.decoder(verilog)
2310 
        net "GND" in work.decoder(verilog)
2311 
        net "GND" in work.decoder(verilog)
2312 
        net "GND" in work.decoder(verilog)
2313 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
2314 
        net "GND" in work.decoder(verilog)
2315 
        net "VCC" in work.decoder(verilog)
2316 
        net "VCC" in work.decoder(verilog)
2317 
        net "GND" in work.decoder(verilog)
2318 
        net "GND" in work.decoder(verilog)
2319 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
2320 
        net "VCC" in work.decoder(verilog)
2321 
        net "VCC" in work.decoder(verilog)
2322 
        net "VCC" in work.decoder(verilog)
2323 
        net "VCC" in work.decoder(verilog)
2324 
        net "VCC" in work.decoder(verilog)
2325 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
2326 
        net "VCC" in work.decoder(verilog)
2327 
        net "VCC" in work.decoder(verilog)
2328 
        net "VCC" in work.decoder(verilog)
2329 
        net "GND" in work.decoder(verilog)
2330 
        net "GND" in work.decoder(verilog)
2331 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
2332 
        net "VCC" in work.decoder(verilog)
2333 
        net "VCC" in work.decoder(verilog)
2334 
        net "VCC" in work.decoder(verilog)
2335 
        net "GND" in work.decoder(verilog)
2336 
        net "GND" in work.decoder(verilog)
2337 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
2338 
        net "VCC" in work.decoder(verilog)
2339 
        net "GND" in work.decoder(verilog)
2340 
        net "GND" in work.decoder(verilog)
2341 
        net "VCC" in work.decoder(verilog)
2342 
        net "GND" in work.decoder(verilog)
2343 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
2344 
        net "GND" in work.decoder(verilog)
2345 
        net "GND" in work.decoder(verilog)
2346 
        net "GND" in work.decoder(verilog)
2347 
        net "VCC" in work.decoder(verilog)
2348 
        net "GND" in work.decoder(verilog)
2349 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
2350 
        net "VCC" in work.decoder(verilog)
2351 
        net "VCC" in work.decoder(verilog)
2352 
        net "GND" in work.decoder(verilog)
2353 
        net "VCC" in work.decoder(verilog)
2354 
        net "GND" in work.decoder(verilog)
2355 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
2356 
        net "GND" in work.decoder(verilog)
2357 
        net "VCC" in work.decoder(verilog)
2358 
        net "GND" in work.decoder(verilog)
2359 
        net "VCC" in work.decoder(verilog)
2360 
        net "GND" in work.decoder(verilog)
2361 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
2362 
        net "GND" in work.decoder(verilog)
2363 
        net "GND" in work.decoder(verilog)
2364 
        net "VCC" in work.decoder(verilog)
2365 
        net "VCC" in work.decoder(verilog)
2366 
        net "GND" in work.decoder(verilog)
2367 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
2368 
        net "GND" in work.decoder(verilog)
2369 
        net "GND" in work.decoder(verilog)
2370 
        net "VCC" in work.decoder(verilog)
2371 
        net "VCC" in work.decoder(verilog)
2372 
        net "GND" in work.decoder(verilog)
2373 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
2374 
        net "GND" in work.decoder(verilog)
2375 
        net "VCC" in work.decoder(verilog)
2376 
        net "VCC" in work.decoder(verilog)
2377 
        net "VCC" in work.decoder(verilog)
2378 
        net "GND" in work.decoder(verilog)
2379 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
2380 
        net "VCC" in work.decoder(verilog)
2381 
        net "VCC" in work.decoder(verilog)
2382 
        net "VCC" in work.decoder(verilog)
2383 
        net "VCC" in work.decoder(verilog)
2384 
        net "GND" in work.decoder(verilog)
2385 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
2386 
        net "VCC" in work.decoder(verilog)
2387 
        net "VCC" in work.decoder(verilog)
2388 
        net "GND" in work.decoder(verilog)
2389 
        net "GND" in work.decoder(verilog)
2390 
        net "VCC" in work.decoder(verilog)
2391 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
2392 
        net "GND" in work.decoder(verilog)
2393 
        net "VCC" in work.decoder(verilog)
2394 
        net "GND" in work.decoder(verilog)
2395 
        net "GND" in work.decoder(verilog)
2396 
        net "VCC" in work.decoder(verilog)
2397 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
2398 
        net "GND" in work.decoder(verilog)
2399 
        net "GND" in work.decoder(verilog)
2400 
        net "VCC" in work.decoder(verilog)
2401 
        net "GND" in work.decoder(verilog)
2402 
        net "VCC" in work.decoder(verilog)
2403 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
2404 
        net "VCC" in work.decoder(verilog)
2405 
        net "GND" in work.decoder(verilog)
2406 
        net "VCC" in work.decoder(verilog)
2407 
        net "GND" in work.decoder(verilog)
2408 
        net "VCC" in work.decoder(verilog)
2409 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
2410 
        net "VCC" in work.decoder(verilog)
2411 
        net "GND" in work.decoder(verilog)
2412 
        net "GND" in work.decoder(verilog)
2413 
        net "GND" in work.decoder(verilog)
2414 
        net "VCC" in work.decoder(verilog)
2415 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
2416 
        net "GND" in work.decoder(verilog)
2417 
        net "GND" in work.decoder(verilog)
2418 
        net "GND" in work.decoder(verilog)
2419 
        net "GND" in work.decoder(verilog)
2420 
        net "VCC" in work.decoder(verilog)
2421 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
2422 
        net "GND" in work.decoder(verilog)
2423 
        net "GND" in work.decoder(verilog)
2424 
        net "GND" in work.decoder(verilog)
2425 
        net "GND" in work.decoder(verilog)
2426 
        net "GND" in work.decoder(verilog)
2427 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
2428 
        net "GND" in work.decoder(verilog)
2429 
        net "GND" in work.decoder(verilog)
2430 
        net "GND" in work.decoder(verilog)
2431 
        net "GND" in work.decoder(verilog)
2432 
        net "GND" in work.decoder(verilog)
2433 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
2434 
        net "GND" in work.decoder(verilog)
2435 
        net "GND" in work.decoder(verilog)
2436 
        net "GND" in work.decoder(verilog)
2437 
        net "GND" in work.decoder(verilog)
2438 
        net "GND" in work.decoder(verilog)
2439 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
2440 
        net "GND" in work.decoder(verilog)
2441 
        net "GND" in work.decoder(verilog)
2442 
        net "GND" in work.decoder(verilog)
2443 
        net "GND" in work.decoder(verilog)
2444 
        net "GND" in work.decoder(verilog)
2445 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
2446 
        net "alu_func_1[0]" in work.decoder(verilog)
2447 
        net "alu_func_1[1]" in work.decoder(verilog)
2448 
        net "alu_func_1[2]" in work.decoder(verilog)
2449 
        net "alu_func_1[3]" in work.decoder(verilog)
2450 
        net "alu_func_1[4]" in work.decoder(verilog)
2451 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
2452 
        net "alu_func_1[0]" in work.decoder(verilog)
2453 
        net "alu_func_1[1]" in work.decoder(verilog)
2454 
        net "alu_func_1[2]" in work.decoder(verilog)
2455 
        net "alu_func_1[3]" in work.decoder(verilog)
2456 
        net "alu_func_1[4]" in work.decoder(verilog)
2457 
        net "fsm_dly350" in work.decoder(verilog)
2458 
        net "GND" in work.decoder(verilog)
2459 
        net "GND" in work.decoder(verilog)
2460 
        net "GND" in work.decoder(verilog)
2461 
        net "GND" in work.decoder(verilog)
2462 
        net "GND" in work.decoder(verilog)
2463 
        net "fsm_dly351" in work.decoder(verilog)
2464 
        net "GND" in work.decoder(verilog)
2465 
        net "VCC" in work.decoder(verilog)
2466 
        net "VCC" in work.decoder(verilog)
2467 
        net "GND" in work.decoder(verilog)
2468 
        net "VCC" in work.decoder(verilog)
2469 
        net "fsm_dly352" in work.decoder(verilog)
2470 
        net "GND" in work.decoder(verilog)
2471 
        net "GND" in work.decoder(verilog)
2472 
        net "GND" in work.decoder(verilog)
2473 
        net "GND" in work.decoder(verilog)
2474 
        net "GND" in work.decoder(verilog)
2475 
        net "fsm_dly353" in work.decoder(verilog)
2476 
        net "GND" in work.decoder(verilog)
2477 
        net "GND" in work.decoder(verilog)
2478 
        net "GND" in work.decoder(verilog)
2479 
        net "GND" in work.decoder(verilog)
2480 
        net "GND" in work.decoder(verilog)
2481 
        net "fsm_dly354" in work.decoder(verilog)
2482 
        net "GND" in work.decoder(verilog)
2483 
        net "GND" in work.decoder(verilog)
2484 
        net "GND" in work.decoder(verilog)
2485 
        net "GND" in work.decoder(verilog)
2486 
        net "GND" in work.decoder(verilog)
2487 
        net "fsm_dly355" in work.decoder(verilog)
2488 
        net "GND" in work.decoder(verilog)
2489 
        net "GND" in work.decoder(verilog)
2490 
        net "GND" in work.decoder(verilog)
2491 
        net "GND" in work.decoder(verilog)
2492 
        net "GND" in work.decoder(verilog)
2493 
        net "fsm_dly356" in work.decoder(verilog)
2494 
        net "GND" in work.decoder(verilog)
2495 
        net "GND" in work.decoder(verilog)
2496 
        net "VCC" in work.decoder(verilog)
2497 
        net "VCC" in work.decoder(verilog)
2498 
        net "GND" in work.decoder(verilog)
2499 
        net "fsm_dly357" in work.decoder(verilog)
2500 
        net "GND" in work.decoder(verilog)
2501 
        net "GND" in work.decoder(verilog)
2502 
        net "VCC" in work.decoder(verilog)
2503 
        net "VCC" in work.decoder(verilog)
2504 
        net "GND" in work.decoder(verilog)
2505 
        net "fsm_dly358" in work.decoder(verilog)
2506 
        net "VCC" in work.decoder(verilog)
2507 
        net "GND" in work.decoder(verilog)
2508 
        net "GND" in work.decoder(verilog)
2509 
        net "GND" in work.decoder(verilog)
2510 
        net "VCC" in work.decoder(verilog)
2511 
        net "fsm_dly359" in work.decoder(verilog)
2512 
        net "GND" in work.decoder(verilog)
2513 
        net "GND" in work.decoder(verilog)
2514 
        net "GND" in work.decoder(verilog)
2515 
        net "GND" in work.decoder(verilog)
2516 
        net "VCC" in work.decoder(verilog)
2517 
        net "fsm_dly360" in work.decoder(verilog)
2518 
        net "VCC" in work.decoder(verilog)
2519 
        net "VCC" in work.decoder(verilog)
2520 
        net "GND" in work.decoder(verilog)
2521 
        net "GND" in work.decoder(verilog)
2522 
        net "VCC" in work.decoder(verilog)
2523 
        net "fsm_dly361" in work.decoder(verilog)
2524 
        net "GND" in work.decoder(verilog)
2525 
        net "VCC" in work.decoder(verilog)
2526 
        net "GND" in work.decoder(verilog)
2527 
        net "GND" in work.decoder(verilog)
2528 
        net "VCC" in work.decoder(verilog)
2529 
        net "fsm_dly362" in work.decoder(verilog)
2530 
        net "GND" in work.decoder(verilog)
2531 
        net "GND" in work.decoder(verilog)
2532 
        net "VCC" in work.decoder(verilog)
2533 
        net "GND" in work.decoder(verilog)
2534 
        net "VCC" in work.decoder(verilog)
2535 
        net "fsm_dly363" in work.decoder(verilog)
2536 
        net "VCC" in work.decoder(verilog)
2537 
        net "VCC" in work.decoder(verilog)
2538 
        net "VCC" in work.decoder(verilog)
2539 
        net "GND" in work.decoder(verilog)
2540 
        net "VCC" in work.decoder(verilog)
2541 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
2542 
        net "GND" in work.decoder(verilog)
2543 
        net "VCC" in work.decoder(verilog)
2544 
        net "VCC" in work.decoder(verilog)
2545 
        net "GND" in work.decoder(verilog)
2546 
        net "VCC" in work.decoder(verilog)
2547 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
2548 
        net "GND" in work.decoder(verilog)
2549 
        net "GND" in work.decoder(verilog)
2550 
        net "GND" in work.decoder(verilog)
2551 
        net "GND" in work.decoder(verilog)
2552 
        net "GND" in work.decoder(verilog)
2553 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
2554 
        net "alu_func_1[0]" in work.decoder(verilog)
2555 
        net "alu_func_1[1]" in work.decoder(verilog)
2556 
        net "alu_func_1[2]" in work.decoder(verilog)
2557 
        net "alu_func_1[3]" in work.decoder(verilog)
2558 
        net "alu_func_1[4]" in work.decoder(verilog)
2559 
        net "fsm_dly365" in work.decoder(verilog)
2560 
        net "GND" in work.decoder(verilog)
2561 
        net "GND" in work.decoder(verilog)
2562 
        net "VCC" in work.decoder(verilog)
2563 
        net "VCC" in work.decoder(verilog)
2564 
        net "GND" in work.decoder(verilog)
2565 
        net "fsm_dly366" in work.decoder(verilog)
2566 
        net "GND" in work.decoder(verilog)
2567 
        net "GND" in work.decoder(verilog)
2568 
        net "VCC" in work.decoder(verilog)
2569 
        net "VCC" in work.decoder(verilog)
2570 
        net "GND" in work.decoder(verilog)
2571 
        net "fsm_dly367" in work.decoder(verilog)
2572 
        net "GND" in work.decoder(verilog)
2573 
        net "GND" in work.decoder(verilog)
2574 
        net "GND" in work.decoder(verilog)
2575 
        net "GND" in work.decoder(verilog)
2576 
        net "GND" in work.decoder(verilog)
2577 
        net "fsm_dly368" in work.decoder(verilog)
2578 
        net "GND" in work.decoder(verilog)
2579 
        net "GND" in work.decoder(verilog)
2580 
        net "VCC" in work.decoder(verilog)
2581 
        net "VCC" in work.decoder(verilog)
2582 
        net "GND" in work.decoder(verilog)
2583 
        net "fsm_dly369" in work.decoder(verilog)
2584 
        net "GND" in work.decoder(verilog)
2585 
        net "GND" in work.decoder(verilog)
2586 
        net "VCC" in work.decoder(verilog)
2587 
        net "VCC" in work.decoder(verilog)
2588 
        net "GND" in work.decoder(verilog)
2589 
        net "fsm_dly370" in work.decoder(verilog)
2590 
        net "GND" in work.decoder(verilog)
2591 
        net "GND" in work.decoder(verilog)
2592 
        net "VCC" in work.decoder(verilog)
2593 
        net "VCC" in work.decoder(verilog)
2594 
        net "GND" in work.decoder(verilog)
2595 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net alu_we_1[0]</font>
2596 
11) instance work.decoder(verilog)-alu_we_1[0], output net "alu_we_1[0]" in work.decoder(verilog)
2597 
    input nets to instance:
2598 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
2599 
        net "VCC" in work.decoder(verilog)
2600 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
2601 
        net "VCC" in work.decoder(verilog)
2602 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
2603 
        net "VCC" in work.decoder(verilog)
2604 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
2605 
        net "GND" in work.decoder(verilog)
2606 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
2607 
        net "GND" in work.decoder(verilog)
2608 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
2609 
        net "GND" in work.decoder(verilog)
2610 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
2611 
        net "GND" in work.decoder(verilog)
2612 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
2613 
        net "GND" in work.decoder(verilog)
2614 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
2615 
        net "GND" in work.decoder(verilog)
2616 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
2617 
        net "GND" in work.decoder(verilog)
2618 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
2619 
        net "VCC" in work.decoder(verilog)
2620 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
2621 
        net "GND" in work.decoder(verilog)
2622 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
2623 
        net "VCC" in work.decoder(verilog)
2624 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
2625 
        net "GND" in work.decoder(verilog)
2626 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
2627 
        net "GND" in work.decoder(verilog)
2628 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
2629 
        net "GND" in work.decoder(verilog)
2630 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
2631 
        net "GND" in work.decoder(verilog)
2632 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
2633 
        net "GND" in work.decoder(verilog)
2634 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
2635 
        net "VCC" in work.decoder(verilog)
2636 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
2637 
        net "VCC" in work.decoder(verilog)
2638 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
2639 
        net "VCC" in work.decoder(verilog)
2640 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
2641 
        net "VCC" in work.decoder(verilog)
2642 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
2643 
        net "VCC" in work.decoder(verilog)
2644 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
2645 
        net "VCC" in work.decoder(verilog)
2646 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
2647 
        net "VCC" in work.decoder(verilog)
2648 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
2649 
        net "VCC" in work.decoder(verilog)
2650 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
2651 
        net "VCC" in work.decoder(verilog)
2652 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
2653 
        net "VCC" in work.decoder(verilog)
2654 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
2655 
        net "GND" in work.decoder(verilog)
2656 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
2657 
        net "GND" in work.decoder(verilog)
2658 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
2659 
        net "GND" in work.decoder(verilog)
2660 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
2661 
        net "GND" in work.decoder(verilog)
2662 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
2663 
        net "alu_we[0]" in work.decoder(verilog)
2664 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
2665 
        net "alu_we[0]" in work.decoder(verilog)
2666 
        net "fsm_dly350" in work.decoder(verilog)
2667 
        net "GND" in work.decoder(verilog)
2668 
        net "fsm_dly351" in work.decoder(verilog)
2669 
        net "VCC" in work.decoder(verilog)
2670 
        net "fsm_dly352" in work.decoder(verilog)
2671 
        net "GND" in work.decoder(verilog)
2672 
        net "fsm_dly353" in work.decoder(verilog)
2673 
        net "GND" in work.decoder(verilog)
2674 
        net "fsm_dly354" in work.decoder(verilog)
2675 
        net "GND" in work.decoder(verilog)
2676 
        net "fsm_dly355" in work.decoder(verilog)
2677 
        net "GND" in work.decoder(verilog)
2678 
        net "fsm_dly356" in work.decoder(verilog)
2679 
        net "VCC" in work.decoder(verilog)
2680 
        net "fsm_dly357" in work.decoder(verilog)
2681 
        net "VCC" in work.decoder(verilog)
2682 
        net "fsm_dly358" in work.decoder(verilog)
2683 
        net "VCC" in work.decoder(verilog)
2684 
        net "fsm_dly359" in work.decoder(verilog)
2685 
        net "VCC" in work.decoder(verilog)
2686 
        net "fsm_dly360" in work.decoder(verilog)
2687 
        net "VCC" in work.decoder(verilog)
2688 
        net "fsm_dly361" in work.decoder(verilog)
2689 
        net "VCC" in work.decoder(verilog)
2690 
        net "fsm_dly362" in work.decoder(verilog)
2691 
        net "VCC" in work.decoder(verilog)
2692 
        net "fsm_dly363" in work.decoder(verilog)
2693 
        net "VCC" in work.decoder(verilog)
2694 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
2695 
        net "VCC" in work.decoder(verilog)
2696 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
2697 
        net "GND" in work.decoder(verilog)
2698 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
2699 
        net "alu_we[0]" in work.decoder(verilog)
2700 
        net "fsm_dly365" in work.decoder(verilog)
2701 
        net "GND" in work.decoder(verilog)
2702 
        net "fsm_dly366" in work.decoder(verilog)
2703 
        net "GND" in work.decoder(verilog)
2704 
        net "fsm_dly367" in work.decoder(verilog)
2705 
        net "GND" in work.decoder(verilog)
2706 
        net "fsm_dly368" in work.decoder(verilog)
2707 
        net "GND" in work.decoder(verilog)
2708 
        net "fsm_dly369" in work.decoder(verilog)
2709 
        net "GND" in work.decoder(verilog)
2710 
        net "fsm_dly370" in work.decoder(verilog)
2711 
        net "GND" in work.decoder(verilog)
2712 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_2[0]</font>
2713 
12) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[0]" in work.decoder(verilog)
2714 
    input nets to instance:
2715 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
2716 
        net "VCC" in work.decoder(verilog)
2717 
        net "GND" in work.decoder(verilog)
2718 
        net "VCC" in work.decoder(verilog)
2719 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
2720 
        net "VCC" in work.decoder(verilog)
2721 
        net "GND" in work.decoder(verilog)
2722 
        net "VCC" in work.decoder(verilog)
2723 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
2724 
        net "VCC" in work.decoder(verilog)
2725 
        net "GND" in work.decoder(verilog)
2726 
        net "VCC" in work.decoder(verilog)
2727 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
2728 
        net "GND" in work.decoder(verilog)
2729 
        net "GND" in work.decoder(verilog)
2730 
        net "GND" in work.decoder(verilog)
2731 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
2732 
        net "GND" in work.decoder(verilog)
2733 
        net "GND" in work.decoder(verilog)
2734 
        net "GND" in work.decoder(verilog)
2735 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
2736 
        net "GND" in work.decoder(verilog)
2737 
        net "GND" in work.decoder(verilog)
2738 
        net "GND" in work.decoder(verilog)
2739 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
2740 
        net "GND" in work.decoder(verilog)
2741 
        net "GND" in work.decoder(verilog)
2742 
        net "GND" in work.decoder(verilog)
2743 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
2744 
        net "GND" in work.decoder(verilog)
2745 
        net "GND" in work.decoder(verilog)
2746 
        net "GND" in work.decoder(verilog)
2747 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
2748 
        net "GND" in work.decoder(verilog)
2749 
        net "GND" in work.decoder(verilog)
2750 
        net "GND" in work.decoder(verilog)
2751 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
2752 
        net "GND" in work.decoder(verilog)
2753 
        net "GND" in work.decoder(verilog)
2754 
        net "GND" in work.decoder(verilog)
2755 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
2756 
        net "GND" in work.decoder(verilog)
2757 
        net "GND" in work.decoder(verilog)
2758 
        net "GND" in work.decoder(verilog)
2759 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
2760 
        net "GND" in work.decoder(verilog)
2761 
        net "GND" in work.decoder(verilog)
2762 
        net "GND" in work.decoder(verilog)
2763 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
2764 
        net "GND" in work.decoder(verilog)
2765 
        net "GND" in work.decoder(verilog)
2766 
        net "GND" in work.decoder(verilog)
2767 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
2768 
        net "GND" in work.decoder(verilog)
2769 
        net "GND" in work.decoder(verilog)
2770 
        net "GND" in work.decoder(verilog)
2771 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
2772 
        net "GND" in work.decoder(verilog)
2773 
        net "GND" in work.decoder(verilog)
2774 
        net "GND" in work.decoder(verilog)
2775 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
2776 
        net "GND" in work.decoder(verilog)
2777 
        net "GND" in work.decoder(verilog)
2778 
        net "GND" in work.decoder(verilog)
2779 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
2780 
        net "GND" in work.decoder(verilog)
2781 
        net "GND" in work.decoder(verilog)
2782 
        net "GND" in work.decoder(verilog)
2783 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
2784 
        net "GND" in work.decoder(verilog)
2785 
        net "GND" in work.decoder(verilog)
2786 
        net "GND" in work.decoder(verilog)
2787 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
2788 
        net "GND" in work.decoder(verilog)
2789 
        net "GND" in work.decoder(verilog)
2790 
        net "GND" in work.decoder(verilog)
2791 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
2792 
        net "GND" in work.decoder(verilog)
2793 
        net "GND" in work.decoder(verilog)
2794 
        net "GND" in work.decoder(verilog)
2795 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
2796 
        net "GND" in work.decoder(verilog)
2797 
        net "GND" in work.decoder(verilog)
2798 
        net "GND" in work.decoder(verilog)
2799 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
2800 
        net "GND" in work.decoder(verilog)
2801 
        net "GND" in work.decoder(verilog)
2802 
        net "GND" in work.decoder(verilog)
2803 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
2804 
        net "GND" in work.decoder(verilog)
2805 
        net "GND" in work.decoder(verilog)
2806 
        net "GND" in work.decoder(verilog)
2807 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
2808 
        net "GND" in work.decoder(verilog)
2809 
        net "GND" in work.decoder(verilog)
2810 
        net "GND" in work.decoder(verilog)
2811 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
2812 
        net "GND" in work.decoder(verilog)
2813 
        net "GND" in work.decoder(verilog)
2814 
        net "GND" in work.decoder(verilog)
2815 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
2816 
        net "GND" in work.decoder(verilog)
2817 
        net "GND" in work.decoder(verilog)
2818 
        net "GND" in work.decoder(verilog)
2819 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
2820 
        net "VCC" in work.decoder(verilog)
2821 
        net "GND" in work.decoder(verilog)
2822 
        net "GND" in work.decoder(verilog)
2823 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
2824 
        net "GND" in work.decoder(verilog)
2825 
        net "GND" in work.decoder(verilog)
2826 
        net "GND" in work.decoder(verilog)
2827 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
2828 
        net "GND" in work.decoder(verilog)
2829 
        net "GND" in work.decoder(verilog)
2830 
        net "GND" in work.decoder(verilog)
2831 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
2832 
        net "GND" in work.decoder(verilog)
2833 
        net "GND" in work.decoder(verilog)
2834 
        net "VCC" in work.decoder(verilog)
2835 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
2836 
        net "GND" in work.decoder(verilog)
2837 
        net "GND" in work.decoder(verilog)
2838 
        net "VCC" in work.decoder(verilog)
2839 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
2840 
        net "GND" in work.decoder(verilog)
2841 
        net "GND" in work.decoder(verilog)
2842 
        net "GND" in work.decoder(verilog)
2843 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
2844 
        net "ext_ctl_1[0]" in work.decoder(verilog)
2845 
        net "ext_ctl_1[1]" in work.decoder(verilog)
2846 
        net "ext_ctl_1[2]" in work.decoder(verilog)
2847 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
2848 
        net "ext_ctl_1[0]" in work.decoder(verilog)
2849 
        net "ext_ctl_1[1]" in work.decoder(verilog)
2850 
        net "ext_ctl_1[2]" in work.decoder(verilog)
2851 
        net "fsm_dly350" in work.decoder(verilog)
2852 
        net "VCC" in work.decoder(verilog)
2853 
        net "VCC" in work.decoder(verilog)
2854 
        net "GND" in work.decoder(verilog)
2855 
        net "fsm_dly351" in work.decoder(verilog)
2856 
        net "VCC" in work.decoder(verilog)
2857 
        net "VCC" in work.decoder(verilog)
2858 
        net "GND" in work.decoder(verilog)
2859 
        net "fsm_dly352" in work.decoder(verilog)
2860 
        net "GND" in work.decoder(verilog)
2861 
        net "GND" in work.decoder(verilog)
2862 
        net "VCC" in work.decoder(verilog)
2863 
        net "fsm_dly353" in work.decoder(verilog)
2864 
        net "GND" in work.decoder(verilog)
2865 
        net "GND" in work.decoder(verilog)
2866 
        net "VCC" in work.decoder(verilog)
2867 
        net "fsm_dly354" in work.decoder(verilog)
2868 
        net "GND" in work.decoder(verilog)
2869 
        net "GND" in work.decoder(verilog)
2870 
        net "VCC" in work.decoder(verilog)
2871 
        net "fsm_dly355" in work.decoder(verilog)
2872 
        net "GND" in work.decoder(verilog)
2873 
        net "GND" in work.decoder(verilog)
2874 
        net "VCC" in work.decoder(verilog)
2875 
        net "fsm_dly356" in work.decoder(verilog)
2876 
        net "VCC" in work.decoder(verilog)
2877 
        net "GND" in work.decoder(verilog)
2878 
        net "GND" in work.decoder(verilog)
2879 
        net "fsm_dly357" in work.decoder(verilog)
2880 
        net "VCC" in work.decoder(verilog)
2881 
        net "GND" in work.decoder(verilog)
2882 
        net "GND" in work.decoder(verilog)
2883 
        net "fsm_dly358" in work.decoder(verilog)
2884 
        net "VCC" in work.decoder(verilog)
2885 
        net "GND" in work.decoder(verilog)
2886 
        net "GND" in work.decoder(verilog)
2887 
        net "fsm_dly359" in work.decoder(verilog)
2888 
        net "GND" in work.decoder(verilog)
2889 
        net "VCC" in work.decoder(verilog)
2890 
        net "GND" in work.decoder(verilog)
2891 
        net "fsm_dly360" in work.decoder(verilog)
2892 
        net "GND" in work.decoder(verilog)
2893 
        net "VCC" in work.decoder(verilog)
2894 
        net "GND" in work.decoder(verilog)
2895 
        net "fsm_dly361" in work.decoder(verilog)
2896 
        net "GND" in work.decoder(verilog)
2897 
        net "VCC" in work.decoder(verilog)
2898 
        net "GND" in work.decoder(verilog)
2899 
        net "fsm_dly362" in work.decoder(verilog)
2900 
        net "GND" in work.decoder(verilog)
2901 
        net "VCC" in work.decoder(verilog)
2902 
        net "GND" in work.decoder(verilog)
2903 
        net "fsm_dly363" in work.decoder(verilog)
2904 
        net "GND" in work.decoder(verilog)
2905 
        net "VCC" in work.decoder(verilog)
2906 
        net "VCC" in work.decoder(verilog)
2907 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
2908 
        net "GND" in work.decoder(verilog)
2909 
        net "GND" in work.decoder(verilog)
2910 
        net "GND" in work.decoder(verilog)
2911 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
2912 
        net "GND" in work.decoder(verilog)
2913 
        net "GND" in work.decoder(verilog)
2914 
        net "GND" in work.decoder(verilog)
2915 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
2916 
        net "ext_ctl_1[0]" in work.decoder(verilog)
2917 
        net "ext_ctl_1[1]" in work.decoder(verilog)
2918 
        net "ext_ctl_1[2]" in work.decoder(verilog)
2919 
        net "fsm_dly365" in work.decoder(verilog)
2920 
        net "VCC" in work.decoder(verilog)
2921 
        net "GND" in work.decoder(verilog)
2922 
        net "GND" in work.decoder(verilog)
2923 
        net "fsm_dly366" in work.decoder(verilog)
2924 
        net "VCC" in work.decoder(verilog)
2925 
        net "GND" in work.decoder(verilog)
2926 
        net "GND" in work.decoder(verilog)
2927 
        net "fsm_dly367" in work.decoder(verilog)
2928 
        net "GND" in work.decoder(verilog)
2929 
        net "GND" in work.decoder(verilog)
2930 
        net "GND" in work.decoder(verilog)
2931 
        net "fsm_dly368" in work.decoder(verilog)
2932 
        net "VCC" in work.decoder(verilog)
2933 
        net "GND" in work.decoder(verilog)
2934 
        net "GND" in work.decoder(verilog)
2935 
        net "fsm_dly369" in work.decoder(verilog)
2936 
        net "VCC" in work.decoder(verilog)
2937 
        net "GND" in work.decoder(verilog)
2938 
        net "GND" in work.decoder(verilog)
2939 
        net "fsm_dly370" in work.decoder(verilog)
2940 
        net "VCC" in work.decoder(verilog)
2941 
        net "GND" in work.decoder(verilog)
2942 
        net "GND" in work.decoder(verilog)
2943 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_2[1]</font>
2944 
13) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[1]" in work.decoder(verilog)
2945 
    input nets to instance:
2946 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
2947 
        net "VCC" in work.decoder(verilog)
2948 
        net "GND" in work.decoder(verilog)
2949 
        net "VCC" in work.decoder(verilog)
2950 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
2951 
        net "VCC" in work.decoder(verilog)
2952 
        net "GND" in work.decoder(verilog)
2953 
        net "VCC" in work.decoder(verilog)
2954 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
2955 
        net "VCC" in work.decoder(verilog)
2956 
        net "GND" in work.decoder(verilog)
2957 
        net "VCC" in work.decoder(verilog)
2958 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
2959 
        net "GND" in work.decoder(verilog)
2960 
        net "GND" in work.decoder(verilog)
2961 
        net "GND" in work.decoder(verilog)
2962 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
2963 
        net "GND" in work.decoder(verilog)
2964 
        net "GND" in work.decoder(verilog)
2965 
        net "GND" in work.decoder(verilog)
2966 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
2967 
        net "GND" in work.decoder(verilog)
2968 
        net "GND" in work.decoder(verilog)
2969 
        net "GND" in work.decoder(verilog)
2970 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
2971 
        net "GND" in work.decoder(verilog)
2972 
        net "GND" in work.decoder(verilog)
2973 
        net "GND" in work.decoder(verilog)
2974 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
2975 
        net "GND" in work.decoder(verilog)
2976 
        net "GND" in work.decoder(verilog)
2977 
        net "GND" in work.decoder(verilog)
2978 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
2979 
        net "GND" in work.decoder(verilog)
2980 
        net "GND" in work.decoder(verilog)
2981 
        net "GND" in work.decoder(verilog)
2982 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
2983 
        net "GND" in work.decoder(verilog)
2984 
        net "GND" in work.decoder(verilog)
2985 
        net "GND" in work.decoder(verilog)
2986 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
2987 
        net "GND" in work.decoder(verilog)
2988 
        net "GND" in work.decoder(verilog)
2989 
        net "GND" in work.decoder(verilog)
2990 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
2991 
        net "GND" in work.decoder(verilog)
2992 
        net "GND" in work.decoder(verilog)
2993 
        net "GND" in work.decoder(verilog)
2994 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
2995 
        net "GND" in work.decoder(verilog)
2996 
        net "GND" in work.decoder(verilog)
2997 
        net "GND" in work.decoder(verilog)
2998 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
2999 
        net "GND" in work.decoder(verilog)
3000 
        net "GND" in work.decoder(verilog)
3001 
        net "GND" in work.decoder(verilog)
3002 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
3003 
        net "GND" in work.decoder(verilog)
3004 
        net "GND" in work.decoder(verilog)
3005 
        net "GND" in work.decoder(verilog)
3006 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
3007 
        net "GND" in work.decoder(verilog)
3008 
        net "GND" in work.decoder(verilog)
3009 
        net "GND" in work.decoder(verilog)
3010 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
3011 
        net "GND" in work.decoder(verilog)
3012 
        net "GND" in work.decoder(verilog)
3013 
        net "GND" in work.decoder(verilog)
3014 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
3015 
        net "GND" in work.decoder(verilog)
3016 
        net "GND" in work.decoder(verilog)
3017 
        net "GND" in work.decoder(verilog)
3018 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
3019 
        net "GND" in work.decoder(verilog)
3020 
        net "GND" in work.decoder(verilog)
3021 
        net "GND" in work.decoder(verilog)
3022 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
3023 
        net "GND" in work.decoder(verilog)
3024 
        net "GND" in work.decoder(verilog)
3025 
        net "GND" in work.decoder(verilog)
3026 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
3027 
        net "GND" in work.decoder(verilog)
3028 
        net "GND" in work.decoder(verilog)
3029 
        net "GND" in work.decoder(verilog)
3030 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
3031 
        net "GND" in work.decoder(verilog)
3032 
        net "GND" in work.decoder(verilog)
3033 
        net "GND" in work.decoder(verilog)
3034 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
3035 
        net "GND" in work.decoder(verilog)
3036 
        net "GND" in work.decoder(verilog)
3037 
        net "GND" in work.decoder(verilog)
3038 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
3039 
        net "GND" in work.decoder(verilog)
3040 
        net "GND" in work.decoder(verilog)
3041 
        net "GND" in work.decoder(verilog)
3042 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
3043 
        net "GND" in work.decoder(verilog)
3044 
        net "GND" in work.decoder(verilog)
3045 
        net "GND" in work.decoder(verilog)
3046 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
3047 
        net "GND" in work.decoder(verilog)
3048 
        net "GND" in work.decoder(verilog)
3049 
        net "GND" in work.decoder(verilog)
3050 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
3051 
        net "VCC" in work.decoder(verilog)
3052 
        net "GND" in work.decoder(verilog)
3053 
        net "GND" in work.decoder(verilog)
3054 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
3055 
        net "GND" in work.decoder(verilog)
3056 
        net "GND" in work.decoder(verilog)
3057 
        net "GND" in work.decoder(verilog)
3058 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
3059 
        net "GND" in work.decoder(verilog)
3060 
        net "GND" in work.decoder(verilog)
3061 
        net "GND" in work.decoder(verilog)
3062 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
3063 
        net "GND" in work.decoder(verilog)
3064 
        net "GND" in work.decoder(verilog)
3065 
        net "VCC" in work.decoder(verilog)
3066 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
3067 
        net "GND" in work.decoder(verilog)
3068 
        net "GND" in work.decoder(verilog)
3069 
        net "VCC" in work.decoder(verilog)
3070 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
3071 
        net "GND" in work.decoder(verilog)
3072 
        net "GND" in work.decoder(verilog)
3073 
        net "GND" in work.decoder(verilog)
3074 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
3075 
        net "ext_ctl_1[0]" in work.decoder(verilog)
3076 
        net "ext_ctl_1[1]" in work.decoder(verilog)
3077 
        net "ext_ctl_1[2]" in work.decoder(verilog)
3078 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
3079 
        net "ext_ctl_1[0]" in work.decoder(verilog)
3080 
        net "ext_ctl_1[1]" in work.decoder(verilog)
3081 
        net "ext_ctl_1[2]" in work.decoder(verilog)
3082 
        net "fsm_dly350" in work.decoder(verilog)
3083 
        net "VCC" in work.decoder(verilog)
3084 
        net "VCC" in work.decoder(verilog)
3085 
        net "GND" in work.decoder(verilog)
3086 
        net "fsm_dly351" in work.decoder(verilog)
3087 
        net "VCC" in work.decoder(verilog)
3088 
        net "VCC" in work.decoder(verilog)
3089 
        net "GND" in work.decoder(verilog)
3090 
        net "fsm_dly352" in work.decoder(verilog)
3091 
        net "GND" in work.decoder(verilog)
3092 
        net "GND" in work.decoder(verilog)
3093 
        net "VCC" in work.decoder(verilog)
3094 
        net "fsm_dly353" in work.decoder(verilog)
3095 
        net "GND" in work.decoder(verilog)
3096 
        net "GND" in work.decoder(verilog)
3097 
        net "VCC" in work.decoder(verilog)
3098 
        net "fsm_dly354" in work.decoder(verilog)
3099 
        net "GND" in work.decoder(verilog)
3100 
        net "GND" in work.decoder(verilog)
3101 
        net "VCC" in work.decoder(verilog)
3102 
        net "fsm_dly355" in work.decoder(verilog)
3103 
        net "GND" in work.decoder(verilog)
3104 
        net "GND" in work.decoder(verilog)
3105 
        net "VCC" in work.decoder(verilog)
3106 
        net "fsm_dly356" in work.decoder(verilog)
3107 
        net "VCC" in work.decoder(verilog)
3108 
        net "GND" in work.decoder(verilog)
3109 
        net "GND" in work.decoder(verilog)
3110 
        net "fsm_dly357" in work.decoder(verilog)
3111 
        net "VCC" in work.decoder(verilog)
3112 
        net "GND" in work.decoder(verilog)
3113 
        net "GND" in work.decoder(verilog)
3114 
        net "fsm_dly358" in work.decoder(verilog)
3115 
        net "VCC" in work.decoder(verilog)
3116 
        net "GND" in work.decoder(verilog)
3117 
        net "GND" in work.decoder(verilog)
3118 
        net "fsm_dly359" in work.decoder(verilog)
3119 
        net "GND" in work.decoder(verilog)
3120 
        net "VCC" in work.decoder(verilog)
3121 
        net "GND" in work.decoder(verilog)
3122 
        net "fsm_dly360" in work.decoder(verilog)
3123 
        net "GND" in work.decoder(verilog)
3124 
        net "VCC" in work.decoder(verilog)
3125 
        net "GND" in work.decoder(verilog)
3126 
        net "fsm_dly361" in work.decoder(verilog)
3127 
        net "GND" in work.decoder(verilog)
3128 
        net "VCC" in work.decoder(verilog)
3129 
        net "GND" in work.decoder(verilog)
3130 
        net "fsm_dly362" in work.decoder(verilog)
3131 
        net "GND" in work.decoder(verilog)
3132 
        net "VCC" in work.decoder(verilog)
3133 
        net "GND" in work.decoder(verilog)
3134 
        net "fsm_dly363" in work.decoder(verilog)
3135 
        net "GND" in work.decoder(verilog)
3136 
        net "VCC" in work.decoder(verilog)
3137 
        net "VCC" in work.decoder(verilog)
3138 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
3139 
        net "GND" in work.decoder(verilog)
3140 
        net "GND" in work.decoder(verilog)
3141 
        net "GND" in work.decoder(verilog)
3142 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
3143 
        net "GND" in work.decoder(verilog)
3144 
        net "GND" in work.decoder(verilog)
3145 
        net "GND" in work.decoder(verilog)
3146 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
3147 
        net "ext_ctl_1[0]" in work.decoder(verilog)
3148 
        net "ext_ctl_1[1]" in work.decoder(verilog)
3149 
        net "ext_ctl_1[2]" in work.decoder(verilog)
3150 
        net "fsm_dly365" in work.decoder(verilog)
3151 
        net "VCC" in work.decoder(verilog)
3152 
        net "GND" in work.decoder(verilog)
3153 
        net "GND" in work.decoder(verilog)
3154 
        net "fsm_dly366" in work.decoder(verilog)
3155 
        net "VCC" in work.decoder(verilog)
3156 
        net "GND" in work.decoder(verilog)
3157 
        net "GND" in work.decoder(verilog)
3158 
        net "fsm_dly367" in work.decoder(verilog)
3159 
        net "GND" in work.decoder(verilog)
3160 
        net "GND" in work.decoder(verilog)
3161 
        net "GND" in work.decoder(verilog)
3162 
        net "fsm_dly368" in work.decoder(verilog)
3163 
        net "VCC" in work.decoder(verilog)
3164 
        net "GND" in work.decoder(verilog)
3165 
        net "GND" in work.decoder(verilog)
3166 
        net "fsm_dly369" in work.decoder(verilog)
3167 
        net "VCC" in work.decoder(verilog)
3168 
        net "GND" in work.decoder(verilog)
3169 
        net "GND" in work.decoder(verilog)
3170 
        net "fsm_dly370" in work.decoder(verilog)
3171 
        net "VCC" in work.decoder(verilog)
3172 
        net "GND" in work.decoder(verilog)
3173 
        net "GND" in work.decoder(verilog)
3174 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net ext_ctl_2[2]</font>
3175 
14) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[2]" in work.decoder(verilog)
3176 
    input nets to instance:
3177 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
3178 
        net "VCC" in work.decoder(verilog)
3179 
        net "GND" in work.decoder(verilog)
3180 
        net "VCC" in work.decoder(verilog)
3181 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
3182 
        net "VCC" in work.decoder(verilog)
3183 
        net "GND" in work.decoder(verilog)
3184 
        net "VCC" in work.decoder(verilog)
3185 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
3186 
        net "VCC" in work.decoder(verilog)
3187 
        net "GND" in work.decoder(verilog)
3188 
        net "VCC" in work.decoder(verilog)
3189 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
3190 
        net "GND" in work.decoder(verilog)
3191 
        net "GND" in work.decoder(verilog)
3192 
        net "GND" in work.decoder(verilog)
3193 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
3194 
        net "GND" in work.decoder(verilog)
3195 
        net "GND" in work.decoder(verilog)
3196 
        net "GND" in work.decoder(verilog)
3197 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
3198 
        net "GND" in work.decoder(verilog)
3199 
        net "GND" in work.decoder(verilog)
3200 
        net "GND" in work.decoder(verilog)
3201 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
3202 
        net "GND" in work.decoder(verilog)
3203 
        net "GND" in work.decoder(verilog)
3204 
        net "GND" in work.decoder(verilog)
3205 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
3206 
        net "GND" in work.decoder(verilog)
3207 
        net "GND" in work.decoder(verilog)
3208 
        net "GND" in work.decoder(verilog)
3209 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
3210 
        net "GND" in work.decoder(verilog)
3211 
        net "GND" in work.decoder(verilog)
3212 
        net "GND" in work.decoder(verilog)
3213 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
3214 
        net "GND" in work.decoder(verilog)
3215 
        net "GND" in work.decoder(verilog)
3216 
        net "GND" in work.decoder(verilog)
3217 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
3218 
        net "GND" in work.decoder(verilog)
3219 
        net "GND" in work.decoder(verilog)
3220 
        net "GND" in work.decoder(verilog)
3221 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
3222 
        net "GND" in work.decoder(verilog)
3223 
        net "GND" in work.decoder(verilog)
3224 
        net "GND" in work.decoder(verilog)
3225 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
3226 
        net "GND" in work.decoder(verilog)
3227 
        net "GND" in work.decoder(verilog)
3228 
        net "GND" in work.decoder(verilog)
3229 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
3230 
        net "GND" in work.decoder(verilog)
3231 
        net "GND" in work.decoder(verilog)
3232 
        net "GND" in work.decoder(verilog)
3233 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
3234 
        net "GND" in work.decoder(verilog)
3235 
        net "GND" in work.decoder(verilog)
3236 
        net "GND" in work.decoder(verilog)
3237 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
3238 
        net "GND" in work.decoder(verilog)
3239 
        net "GND" in work.decoder(verilog)
3240 
        net "GND" in work.decoder(verilog)
3241 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
3242 
        net "GND" in work.decoder(verilog)
3243 
        net "GND" in work.decoder(verilog)
3244 
        net "GND" in work.decoder(verilog)
3245 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
3246 
        net "GND" in work.decoder(verilog)
3247 
        net "GND" in work.decoder(verilog)
3248 
        net "GND" in work.decoder(verilog)
3249 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
3250 
        net "GND" in work.decoder(verilog)
3251 
        net "GND" in work.decoder(verilog)
3252 
        net "GND" in work.decoder(verilog)
3253 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
3254 
        net "GND" in work.decoder(verilog)
3255 
        net "GND" in work.decoder(verilog)
3256 
        net "GND" in work.decoder(verilog)
3257 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
3258 
        net "GND" in work.decoder(verilog)
3259 
        net "GND" in work.decoder(verilog)
3260 
        net "GND" in work.decoder(verilog)
3261 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
3262 
        net "GND" in work.decoder(verilog)
3263 
        net "GND" in work.decoder(verilog)
3264 
        net "GND" in work.decoder(verilog)
3265 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
3266 
        net "GND" in work.decoder(verilog)
3267 
        net "GND" in work.decoder(verilog)
3268 
        net "GND" in work.decoder(verilog)
3269 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
3270 
        net "GND" in work.decoder(verilog)
3271 
        net "GND" in work.decoder(verilog)
3272 
        net "GND" in work.decoder(verilog)
3273 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
3274 
        net "GND" in work.decoder(verilog)
3275 
        net "GND" in work.decoder(verilog)
3276 
        net "GND" in work.decoder(verilog)
3277 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
3278 
        net "GND" in work.decoder(verilog)
3279 
        net "GND" in work.decoder(verilog)
3280 
        net "GND" in work.decoder(verilog)
3281 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
3282 
        net "VCC" in work.decoder(verilog)
3283 
        net "GND" in work.decoder(verilog)
3284 
        net "GND" in work.decoder(verilog)
3285 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
3286 
        net "GND" in work.decoder(verilog)
3287 
        net "GND" in work.decoder(verilog)
3288 
        net "GND" in work.decoder(verilog)
3289 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
3290 
        net "GND" in work.decoder(verilog)
3291 
        net "GND" in work.decoder(verilog)
3292 
        net "GND" in work.decoder(verilog)
3293 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
3294 
        net "GND" in work.decoder(verilog)
3295 
        net "GND" in work.decoder(verilog)
3296 
        net "VCC" in work.decoder(verilog)
3297 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
3298 
        net "GND" in work.decoder(verilog)
3299 
        net "GND" in work.decoder(verilog)
3300 
        net "VCC" in work.decoder(verilog)
3301 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
3302 
        net "GND" in work.decoder(verilog)
3303 
        net "GND" in work.decoder(verilog)
3304 
        net "GND" in work.decoder(verilog)
3305 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
3306 
        net "ext_ctl_1[0]" in work.decoder(verilog)
3307 
        net "ext_ctl_1[1]" in work.decoder(verilog)
3308 
        net "ext_ctl_1[2]" in work.decoder(verilog)
3309 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
3310 
        net "ext_ctl_1[0]" in work.decoder(verilog)
3311 
        net "ext_ctl_1[1]" in work.decoder(verilog)
3312 
        net "ext_ctl_1[2]" in work.decoder(verilog)
3313 
        net "fsm_dly350" in work.decoder(verilog)
3314 
        net "VCC" in work.decoder(verilog)
3315 
        net "VCC" in work.decoder(verilog)
3316 
        net "GND" in work.decoder(verilog)
3317 
        net "fsm_dly351" in work.decoder(verilog)
3318 
        net "VCC" in work.decoder(verilog)
3319 
        net "VCC" in work.decoder(verilog)
3320 
        net "GND" in work.decoder(verilog)
3321 
        net "fsm_dly352" in work.decoder(verilog)
3322 
        net "GND" in work.decoder(verilog)
3323 
        net "GND" in work.decoder(verilog)
3324 
        net "VCC" in work.decoder(verilog)
3325 
        net "fsm_dly353" in work.decoder(verilog)
3326 
        net "GND" in work.decoder(verilog)
3327 
        net "GND" in work.decoder(verilog)
3328 
        net "VCC" in work.decoder(verilog)
3329 
        net "fsm_dly354" in work.decoder(verilog)
3330 
        net "GND" in work.decoder(verilog)
3331 
        net "GND" in work.decoder(verilog)
3332 
        net "VCC" in work.decoder(verilog)
3333 
        net "fsm_dly355" in work.decoder(verilog)
3334 
        net "GND" in work.decoder(verilog)
3335 
        net "GND" in work.decoder(verilog)
3336 
        net "VCC" in work.decoder(verilog)
3337 
        net "fsm_dly356" in work.decoder(verilog)
3338 
        net "VCC" in work.decoder(verilog)
3339 
        net "GND" in work.decoder(verilog)
3340 
        net "GND" in work.decoder(verilog)
3341 
        net "fsm_dly357" in work.decoder(verilog)
3342 
        net "VCC" in work.decoder(verilog)
3343 
        net "GND" in work.decoder(verilog)
3344 
        net "GND" in work.decoder(verilog)
3345 
        net "fsm_dly358" in work.decoder(verilog)
3346 
        net "VCC" in work.decoder(verilog)
3347 
        net "GND" in work.decoder(verilog)
3348 
        net "GND" in work.decoder(verilog)
3349 
        net "fsm_dly359" in work.decoder(verilog)
3350 
        net "GND" in work.decoder(verilog)
3351 
        net "VCC" in work.decoder(verilog)
3352 
        net "GND" in work.decoder(verilog)
3353 
        net "fsm_dly360" in work.decoder(verilog)
3354 
        net "GND" in work.decoder(verilog)
3355 
        net "VCC" in work.decoder(verilog)
3356 
        net "GND" in work.decoder(verilog)
3357 
        net "fsm_dly361" in work.decoder(verilog)
3358 
        net "GND" in work.decoder(verilog)
3359 
        net "VCC" in work.decoder(verilog)
3360 
        net "GND" in work.decoder(verilog)
3361 
        net "fsm_dly362" in work.decoder(verilog)
3362 
        net "GND" in work.decoder(verilog)
3363 
        net "VCC" in work.decoder(verilog)
3364 
        net "GND" in work.decoder(verilog)
3365 
        net "fsm_dly363" in work.decoder(verilog)
3366 
        net "GND" in work.decoder(verilog)
3367 
        net "VCC" in work.decoder(verilog)
3368 
        net "VCC" in work.decoder(verilog)
3369 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
3370 
        net "GND" in work.decoder(verilog)
3371 
        net "GND" in work.decoder(verilog)
3372 
        net "GND" in work.decoder(verilog)
3373 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
3374 
        net "GND" in work.decoder(verilog)
3375 
        net "GND" in work.decoder(verilog)
3376 
        net "GND" in work.decoder(verilog)
3377 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
3378 
        net "ext_ctl_1[0]" in work.decoder(verilog)
3379 
        net "ext_ctl_1[1]" in work.decoder(verilog)
3380 
        net "ext_ctl_1[2]" in work.decoder(verilog)
3381 
        net "fsm_dly365" in work.decoder(verilog)
3382 
        net "VCC" in work.decoder(verilog)
3383 
        net "GND" in work.decoder(verilog)
3384 
        net "GND" in work.decoder(verilog)
3385 
        net "fsm_dly366" in work.decoder(verilog)
3386 
        net "VCC" in work.decoder(verilog)
3387 
        net "GND" in work.decoder(verilog)
3388 
        net "GND" in work.decoder(verilog)
3389 
        net "fsm_dly367" in work.decoder(verilog)
3390 
        net "GND" in work.decoder(verilog)
3391 
        net "GND" in work.decoder(verilog)
3392 
        net "GND" in work.decoder(verilog)
3393 
        net "fsm_dly368" in work.decoder(verilog)
3394 
        net "VCC" in work.decoder(verilog)
3395 
        net "GND" in work.decoder(verilog)
3396 
        net "GND" in work.decoder(verilog)
3397 
        net "fsm_dly369" in work.decoder(verilog)
3398 
        net "VCC" in work.decoder(verilog)
3399 
        net "GND" in work.decoder(verilog)
3400 
        net "GND" in work.decoder(verilog)
3401 
        net "fsm_dly370" in work.decoder(verilog)
3402 
        net "VCC" in work.decoder(verilog)
3403 
        net "GND" in work.decoder(verilog)
3404 
        net "GND" in work.decoder(verilog)
3405 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxa_ctl_2[0]</font>
3406 
15) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[0]" in work.decoder(verilog)
3407 
    input nets to instance:
3408 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
3409 
        net "VCC" in work.decoder(verilog)
3410 
        net "VCC" in work.decoder(verilog)
3411 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
3412 
        net "VCC" in work.decoder(verilog)
3413 
        net "VCC" in work.decoder(verilog)
3414 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
3415 
        net "VCC" in work.decoder(verilog)
3416 
        net "VCC" in work.decoder(verilog)
3417 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
3418 
        net "GND" in work.decoder(verilog)
3419 
        net "GND" in work.decoder(verilog)
3420 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
3421 
        net "GND" in work.decoder(verilog)
3422 
        net "GND" in work.decoder(verilog)
3423 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
3424 
        net "GND" in work.decoder(verilog)
3425 
        net "GND" in work.decoder(verilog)
3426 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
3427 
        net "GND" in work.decoder(verilog)
3428 
        net "GND" in work.decoder(verilog)
3429 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
3430 
        net "GND" in work.decoder(verilog)
3431 
        net "GND" in work.decoder(verilog)
3432 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
3433 
        net "GND" in work.decoder(verilog)
3434 
        net "GND" in work.decoder(verilog)
3435 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
3436 
        net "GND" in work.decoder(verilog)
3437 
        net "GND" in work.decoder(verilog)
3438 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
3439 
        net "GND" in work.decoder(verilog)
3440 
        net "GND" in work.decoder(verilog)
3441 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
3442 
        net "GND" in work.decoder(verilog)
3443 
        net "VCC" in work.decoder(verilog)
3444 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
3445 
        net "GND" in work.decoder(verilog)
3446 
        net "GND" in work.decoder(verilog)
3447 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
3448 
        net "GND" in work.decoder(verilog)
3449 
        net "GND" in work.decoder(verilog)
3450 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
3451 
        net "GND" in work.decoder(verilog)
3452 
        net "VCC" in work.decoder(verilog)
3453 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
3454 
        net "GND" in work.decoder(verilog)
3455 
        net "VCC" in work.decoder(verilog)
3456 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
3457 
        net "GND" in work.decoder(verilog)
3458 
        net "VCC" in work.decoder(verilog)
3459 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
3460 
        net "GND" in work.decoder(verilog)
3461 
        net "VCC" in work.decoder(verilog)
3462 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
3463 
        net "GND" in work.decoder(verilog)
3464 
        net "VCC" in work.decoder(verilog)
3465 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
3466 
        net "GND" in work.decoder(verilog)
3467 
        net "VCC" in work.decoder(verilog)
3468 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
3469 
        net "GND" in work.decoder(verilog)
3470 
        net "VCC" in work.decoder(verilog)
3471 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
3472 
        net "GND" in work.decoder(verilog)
3473 
        net "VCC" in work.decoder(verilog)
3474 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
3475 
        net "GND" in work.decoder(verilog)
3476 
        net "VCC" in work.decoder(verilog)
3477 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
3478 
        net "GND" in work.decoder(verilog)
3479 
        net "VCC" in work.decoder(verilog)
3480 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
3481 
        net "GND" in work.decoder(verilog)
3482 
        net "VCC" in work.decoder(verilog)
3483 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
3484 
        net "GND" in work.decoder(verilog)
3485 
        net "VCC" in work.decoder(verilog)
3486 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
3487 
        net "GND" in work.decoder(verilog)
3488 
        net "VCC" in work.decoder(verilog)
3489 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
3490 
        net "GND" in work.decoder(verilog)
3491 
        net "VCC" in work.decoder(verilog)
3492 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
3493 
        net "GND" in work.decoder(verilog)
3494 
        net "GND" in work.decoder(verilog)
3495 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
3496 
        net "GND" in work.decoder(verilog)
3497 
        net "GND" in work.decoder(verilog)
3498 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
3499 
        net "GND" in work.decoder(verilog)
3500 
        net "GND" in work.decoder(verilog)
3501 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
3502 
        net "GND" in work.decoder(verilog)
3503 
        net "GND" in work.decoder(verilog)
3504 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
3505 
        net "muxa_ctl_1[0]" in work.decoder(verilog)
3506 
        net "muxa_ctl_1[1]" in work.decoder(verilog)
3507 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
3508 
        net "muxa_ctl_1[0]" in work.decoder(verilog)
3509 
        net "muxa_ctl_1[1]" in work.decoder(verilog)
3510 
        net "fsm_dly350" in work.decoder(verilog)
3511 
        net "GND" in work.decoder(verilog)
3512 
        net "GND" in work.decoder(verilog)
3513 
        net "fsm_dly351" in work.decoder(verilog)
3514 
        net "VCC" in work.decoder(verilog)
3515 
        net "GND" in work.decoder(verilog)
3516 
        net "fsm_dly352" in work.decoder(verilog)
3517 
        net "GND" in work.decoder(verilog)
3518 
        net "GND" in work.decoder(verilog)
3519 
        net "fsm_dly353" in work.decoder(verilog)
3520 
        net "GND" in work.decoder(verilog)
3521 
        net "GND" in work.decoder(verilog)
3522 
        net "fsm_dly354" in work.decoder(verilog)
3523 
        net "GND" in work.decoder(verilog)
3524 
        net "GND" in work.decoder(verilog)
3525 
        net "fsm_dly355" in work.decoder(verilog)
3526 
        net "GND" in work.decoder(verilog)
3527 
        net "GND" in work.decoder(verilog)
3528 
        net "fsm_dly356" in work.decoder(verilog)
3529 
        net "GND" in work.decoder(verilog)
3530 
        net "VCC" in work.decoder(verilog)
3531 
        net "fsm_dly357" in work.decoder(verilog)
3532 
        net "GND" in work.decoder(verilog)
3533 
        net "VCC" in work.decoder(verilog)
3534 
        net "fsm_dly358" in work.decoder(verilog)
3535 
        net "GND" in work.decoder(verilog)
3536 
        net "VCC" in work.decoder(verilog)
3537 
        net "fsm_dly359" in work.decoder(verilog)
3538 
        net "GND" in work.decoder(verilog)
3539 
        net "VCC" in work.decoder(verilog)
3540 
        net "fsm_dly360" in work.decoder(verilog)
3541 
        net "GND" in work.decoder(verilog)
3542 
        net "VCC" in work.decoder(verilog)
3543 
        net "fsm_dly361" in work.decoder(verilog)
3544 
        net "GND" in work.decoder(verilog)
3545 
        net "VCC" in work.decoder(verilog)
3546 
        net "fsm_dly362" in work.decoder(verilog)
3547 
        net "GND" in work.decoder(verilog)
3548 
        net "VCC" in work.decoder(verilog)
3549 
        net "fsm_dly363" in work.decoder(verilog)
3550 
        net "GND" in work.decoder(verilog)
3551 
        net "VCC" in work.decoder(verilog)
3552 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
3553 
        net "GND" in work.decoder(verilog)
3554 
        net "GND" in work.decoder(verilog)
3555 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
3556 
        net "GND" in work.decoder(verilog)
3557 
        net "GND" in work.decoder(verilog)
3558 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
3559 
        net "muxa_ctl_1[0]" in work.decoder(verilog)
3560 
        net "muxa_ctl_1[1]" in work.decoder(verilog)
3561 
        net "fsm_dly365" in work.decoder(verilog)
3562 
        net "GND" in work.decoder(verilog)
3563 
        net "VCC" in work.decoder(verilog)
3564 
        net "fsm_dly366" in work.decoder(verilog)
3565 
        net "GND" in work.decoder(verilog)
3566 
        net "VCC" in work.decoder(verilog)
3567 
        net "fsm_dly367" in work.decoder(verilog)
3568 
        net "GND" in work.decoder(verilog)
3569 
        net "GND" in work.decoder(verilog)
3570 
        net "fsm_dly368" in work.decoder(verilog)
3571 
        net "GND" in work.decoder(verilog)
3572 
        net "VCC" in work.decoder(verilog)
3573 
        net "fsm_dly369" in work.decoder(verilog)
3574 
        net "GND" in work.decoder(verilog)
3575 
        net "VCC" in work.decoder(verilog)
3576 
        net "fsm_dly370" in work.decoder(verilog)
3577 
        net "GND" in work.decoder(verilog)
3578 
        net "VCC" in work.decoder(verilog)
3579 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxa_ctl_2[1]</font>
3580 
16) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[1]" in work.decoder(verilog)
3581 
    input nets to instance:
3582 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
3583 
        net "VCC" in work.decoder(verilog)
3584 
        net "VCC" in work.decoder(verilog)
3585 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
3586 
        net "VCC" in work.decoder(verilog)
3587 
        net "VCC" in work.decoder(verilog)
3588 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
3589 
        net "VCC" in work.decoder(verilog)
3590 
        net "VCC" in work.decoder(verilog)
3591 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
3592 
        net "GND" in work.decoder(verilog)
3593 
        net "GND" in work.decoder(verilog)
3594 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
3595 
        net "GND" in work.decoder(verilog)
3596 
        net "GND" in work.decoder(verilog)
3597 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
3598 
        net "GND" in work.decoder(verilog)
3599 
        net "GND" in work.decoder(verilog)
3600 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
3601 
        net "GND" in work.decoder(verilog)
3602 
        net "GND" in work.decoder(verilog)
3603 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
3604 
        net "GND" in work.decoder(verilog)
3605 
        net "GND" in work.decoder(verilog)
3606 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
3607 
        net "GND" in work.decoder(verilog)
3608 
        net "GND" in work.decoder(verilog)
3609 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
3610 
        net "GND" in work.decoder(verilog)
3611 
        net "GND" in work.decoder(verilog)
3612 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
3613 
        net "GND" in work.decoder(verilog)
3614 
        net "GND" in work.decoder(verilog)
3615 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
3616 
        net "GND" in work.decoder(verilog)
3617 
        net "VCC" in work.decoder(verilog)
3618 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
3619 
        net "GND" in work.decoder(verilog)
3620 
        net "GND" in work.decoder(verilog)
3621 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
3622 
        net "GND" in work.decoder(verilog)
3623 
        net "GND" in work.decoder(verilog)
3624 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
3625 
        net "GND" in work.decoder(verilog)
3626 
        net "VCC" in work.decoder(verilog)
3627 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
3628 
        net "GND" in work.decoder(verilog)
3629 
        net "VCC" in work.decoder(verilog)
3630 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
3631 
        net "GND" in work.decoder(verilog)
3632 
        net "VCC" in work.decoder(verilog)
3633 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
3634 
        net "GND" in work.decoder(verilog)
3635 
        net "VCC" in work.decoder(verilog)
3636 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
3637 
        net "GND" in work.decoder(verilog)
3638 
        net "VCC" in work.decoder(verilog)
3639 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
3640 
        net "GND" in work.decoder(verilog)
3641 
        net "VCC" in work.decoder(verilog)
3642 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
3643 
        net "GND" in work.decoder(verilog)
3644 
        net "VCC" in work.decoder(verilog)
3645 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
3646 
        net "GND" in work.decoder(verilog)
3647 
        net "VCC" in work.decoder(verilog)
3648 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
3649 
        net "GND" in work.decoder(verilog)
3650 
        net "VCC" in work.decoder(verilog)
3651 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
3652 
        net "GND" in work.decoder(verilog)
3653 
        net "VCC" in work.decoder(verilog)
3654 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
3655 
        net "GND" in work.decoder(verilog)
3656 
        net "VCC" in work.decoder(verilog)
3657 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
3658 
        net "GND" in work.decoder(verilog)
3659 
        net "VCC" in work.decoder(verilog)
3660 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
3661 
        net "GND" in work.decoder(verilog)
3662 
        net "VCC" in work.decoder(verilog)
3663 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
3664 
        net "GND" in work.decoder(verilog)
3665 
        net "VCC" in work.decoder(verilog)
3666 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
3667 
        net "GND" in work.decoder(verilog)
3668 
        net "GND" in work.decoder(verilog)
3669 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
3670 
        net "GND" in work.decoder(verilog)
3671 
        net "GND" in work.decoder(verilog)
3672 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
3673 
        net "GND" in work.decoder(verilog)
3674 
        net "GND" in work.decoder(verilog)
3675 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
3676 
        net "GND" in work.decoder(verilog)
3677 
        net "GND" in work.decoder(verilog)
3678 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
3679 
        net "muxa_ctl_1[0]" in work.decoder(verilog)
3680 
        net "muxa_ctl_1[1]" in work.decoder(verilog)
3681 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
3682 
        net "muxa_ctl_1[0]" in work.decoder(verilog)
3683 
        net "muxa_ctl_1[1]" in work.decoder(verilog)
3684 
        net "fsm_dly350" in work.decoder(verilog)
3685 
        net "GND" in work.decoder(verilog)
3686 
        net "GND" in work.decoder(verilog)
3687 
        net "fsm_dly351" in work.decoder(verilog)
3688 
        net "VCC" in work.decoder(verilog)
3689 
        net "GND" in work.decoder(verilog)
3690 
        net "fsm_dly352" in work.decoder(verilog)
3691 
        net "GND" in work.decoder(verilog)
3692 
        net "GND" in work.decoder(verilog)
3693 
        net "fsm_dly353" in work.decoder(verilog)
3694 
        net "GND" in work.decoder(verilog)
3695 
        net "GND" in work.decoder(verilog)
3696 
        net "fsm_dly354" in work.decoder(verilog)
3697 
        net "GND" in work.decoder(verilog)
3698 
        net "GND" in work.decoder(verilog)
3699 
        net "fsm_dly355" in work.decoder(verilog)
3700 
        net "GND" in work.decoder(verilog)
3701 
        net "GND" in work.decoder(verilog)
3702 
        net "fsm_dly356" in work.decoder(verilog)
3703 
        net "GND" in work.decoder(verilog)
3704 
        net "VCC" in work.decoder(verilog)
3705 
        net "fsm_dly357" in work.decoder(verilog)
3706 
        net "GND" in work.decoder(verilog)
3707 
        net "VCC" in work.decoder(verilog)
3708 
        net "fsm_dly358" in work.decoder(verilog)
3709 
        net "GND" in work.decoder(verilog)
3710 
        net "VCC" in work.decoder(verilog)
3711 
        net "fsm_dly359" in work.decoder(verilog)
3712 
        net "GND" in work.decoder(verilog)
3713 
        net "VCC" in work.decoder(verilog)
3714 
        net "fsm_dly360" in work.decoder(verilog)
3715 
        net "GND" in work.decoder(verilog)
3716 
        net "VCC" in work.decoder(verilog)
3717 
        net "fsm_dly361" in work.decoder(verilog)
3718 
        net "GND" in work.decoder(verilog)
3719 
        net "VCC" in work.decoder(verilog)
3720 
        net "fsm_dly362" in work.decoder(verilog)
3721 
        net "GND" in work.decoder(verilog)
3722 
        net "VCC" in work.decoder(verilog)
3723 
        net "fsm_dly363" in work.decoder(verilog)
3724 
        net "GND" in work.decoder(verilog)
3725 
        net "VCC" in work.decoder(verilog)
3726 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
3727 
        net "GND" in work.decoder(verilog)
3728 
        net "GND" in work.decoder(verilog)
3729 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
3730 
        net "GND" in work.decoder(verilog)
3731 
        net "GND" in work.decoder(verilog)
3732 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
3733 
        net "muxa_ctl_1[0]" in work.decoder(verilog)
3734 
        net "muxa_ctl_1[1]" in work.decoder(verilog)
3735 
        net "fsm_dly365" in work.decoder(verilog)
3736 
        net "GND" in work.decoder(verilog)
3737 
        net "VCC" in work.decoder(verilog)
3738 
        net "fsm_dly366" in work.decoder(verilog)
3739 
        net "GND" in work.decoder(verilog)
3740 
        net "VCC" in work.decoder(verilog)
3741 
        net "fsm_dly367" in work.decoder(verilog)
3742 
        net "GND" in work.decoder(verilog)
3743 
        net "GND" in work.decoder(verilog)
3744 
        net "fsm_dly368" in work.decoder(verilog)
3745 
        net "GND" in work.decoder(verilog)
3746 
        net "VCC" in work.decoder(verilog)
3747 
        net "fsm_dly369" in work.decoder(verilog)
3748 
        net "GND" in work.decoder(verilog)
3749 
        net "VCC" in work.decoder(verilog)
3750 
        net "fsm_dly370" in work.decoder(verilog)
3751 
        net "GND" in work.decoder(verilog)
3752 
        net "VCC" in work.decoder(verilog)
3753 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxb_ctl_2[0]</font>
3754 
17) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[0]" in work.decoder(verilog)
3755 
    input nets to instance:
3756 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
3757 
        net "VCC" in work.decoder(verilog)
3758 
        net "GND" in work.decoder(verilog)
3759 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
3760 
        net "VCC" in work.decoder(verilog)
3761 
        net "GND" in work.decoder(verilog)
3762 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
3763 
        net "VCC" in work.decoder(verilog)
3764 
        net "GND" in work.decoder(verilog)
3765 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
3766 
        net "GND" in work.decoder(verilog)
3767 
        net "GND" in work.decoder(verilog)
3768 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
3769 
        net "GND" in work.decoder(verilog)
3770 
        net "GND" in work.decoder(verilog)
3771 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
3772 
        net "GND" in work.decoder(verilog)
3773 
        net "GND" in work.decoder(verilog)
3774 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
3775 
        net "GND" in work.decoder(verilog)
3776 
        net "GND" in work.decoder(verilog)
3777 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
3778 
        net "GND" in work.decoder(verilog)
3779 
        net "GND" in work.decoder(verilog)
3780 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
3781 
        net "GND" in work.decoder(verilog)
3782 
        net "GND" in work.decoder(verilog)
3783 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
3784 
        net "GND" in work.decoder(verilog)
3785 
        net "GND" in work.decoder(verilog)
3786 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
3787 
        net "GND" in work.decoder(verilog)
3788 
        net "GND" in work.decoder(verilog)
3789 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
3790 
        net "GND" in work.decoder(verilog)
3791 
        net "GND" in work.decoder(verilog)
3792 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
3793 
        net "GND" in work.decoder(verilog)
3794 
        net "GND" in work.decoder(verilog)
3795 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
3796 
        net "GND" in work.decoder(verilog)
3797 
        net "GND" in work.decoder(verilog)
3798 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
3799 
        net "VCC" in work.decoder(verilog)
3800 
        net "GND" in work.decoder(verilog)
3801 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
3802 
        net "VCC" in work.decoder(verilog)
3803 
        net "GND" in work.decoder(verilog)
3804 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
3805 
        net "VCC" in work.decoder(verilog)
3806 
        net "GND" in work.decoder(verilog)
3807 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
3808 
        net "VCC" in work.decoder(verilog)
3809 
        net "GND" in work.decoder(verilog)
3810 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
3811 
        net "VCC" in work.decoder(verilog)
3812 
        net "GND" in work.decoder(verilog)
3813 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
3814 
        net "VCC" in work.decoder(verilog)
3815 
        net "GND" in work.decoder(verilog)
3816 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
3817 
        net "VCC" in work.decoder(verilog)
3818 
        net "GND" in work.decoder(verilog)
3819 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
3820 
        net "VCC" in work.decoder(verilog)
3821 
        net "GND" in work.decoder(verilog)
3822 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
3823 
        net "VCC" in work.decoder(verilog)
3824 
        net "GND" in work.decoder(verilog)
3825 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
3826 
        net "VCC" in work.decoder(verilog)
3827 
        net "GND" in work.decoder(verilog)
3828 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
3829 
        net "VCC" in work.decoder(verilog)
3830 
        net "GND" in work.decoder(verilog)
3831 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
3832 
        net "VCC" in work.decoder(verilog)
3833 
        net "GND" in work.decoder(verilog)
3834 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
3835 
        net "VCC" in work.decoder(verilog)
3836 
        net "GND" in work.decoder(verilog)
3837 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
3838 
        net "VCC" in work.decoder(verilog)
3839 
        net "GND" in work.decoder(verilog)
3840 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
3841 
        net "GND" in work.decoder(verilog)
3842 
        net "GND" in work.decoder(verilog)
3843 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
3844 
        net "GND" in work.decoder(verilog)
3845 
        net "GND" in work.decoder(verilog)
3846 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
3847 
        net "GND" in work.decoder(verilog)
3848 
        net "GND" in work.decoder(verilog)
3849 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
3850 
        net "GND" in work.decoder(verilog)
3851 
        net "GND" in work.decoder(verilog)
3852 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
3853 
        net "muxb_ctl_1[0]" in work.decoder(verilog)
3854 
        net "muxb_ctl_1[1]" in work.decoder(verilog)
3855 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
3856 
        net "muxb_ctl_1[0]" in work.decoder(verilog)
3857 
        net "muxb_ctl_1[1]" in work.decoder(verilog)
3858 
        net "fsm_dly350" in work.decoder(verilog)
3859 
        net "GND" in work.decoder(verilog)
3860 
        net "GND" in work.decoder(verilog)
3861 
        net "fsm_dly351" in work.decoder(verilog)
3862 
        net "VCC" in work.decoder(verilog)
3863 
        net "GND" in work.decoder(verilog)
3864 
        net "fsm_dly352" in work.decoder(verilog)
3865 
        net "GND" in work.decoder(verilog)
3866 
        net "GND" in work.decoder(verilog)
3867 
        net "fsm_dly353" in work.decoder(verilog)
3868 
        net "GND" in work.decoder(verilog)
3869 
        net "GND" in work.decoder(verilog)
3870 
        net "fsm_dly354" in work.decoder(verilog)
3871 
        net "GND" in work.decoder(verilog)
3872 
        net "GND" in work.decoder(verilog)
3873 
        net "fsm_dly355" in work.decoder(verilog)
3874 
        net "GND" in work.decoder(verilog)
3875 
        net "GND" in work.decoder(verilog)
3876 
        net "fsm_dly356" in work.decoder(verilog)
3877 
        net "GND" in work.decoder(verilog)
3878 
        net "VCC" in work.decoder(verilog)
3879 
        net "fsm_dly357" in work.decoder(verilog)
3880 
        net "GND" in work.decoder(verilog)
3881 
        net "VCC" in work.decoder(verilog)
3882 
        net "fsm_dly358" in work.decoder(verilog)
3883 
        net "GND" in work.decoder(verilog)
3884 
        net "VCC" in work.decoder(verilog)
3885 
        net "fsm_dly359" in work.decoder(verilog)
3886 
        net "GND" in work.decoder(verilog)
3887 
        net "VCC" in work.decoder(verilog)
3888 
        net "fsm_dly360" in work.decoder(verilog)
3889 
        net "GND" in work.decoder(verilog)
3890 
        net "VCC" in work.decoder(verilog)
3891 
        net "fsm_dly361" in work.decoder(verilog)
3892 
        net "GND" in work.decoder(verilog)
3893 
        net "VCC" in work.decoder(verilog)
3894 
        net "fsm_dly362" in work.decoder(verilog)
3895 
        net "GND" in work.decoder(verilog)
3896 
        net "VCC" in work.decoder(verilog)
3897 
        net "fsm_dly363" in work.decoder(verilog)
3898 
        net "GND" in work.decoder(verilog)
3899 
        net "VCC" in work.decoder(verilog)
3900 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
3901 
        net "GND" in work.decoder(verilog)
3902 
        net "VCC" in work.decoder(verilog)
3903 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
3904 
        net "GND" in work.decoder(verilog)
3905 
        net "GND" in work.decoder(verilog)
3906 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
3907 
        net "muxb_ctl_1[0]" in work.decoder(verilog)
3908 
        net "muxb_ctl_1[1]" in work.decoder(verilog)
3909 
        net "fsm_dly365" in work.decoder(verilog)
3910 
        net "GND" in work.decoder(verilog)
3911 
        net "VCC" in work.decoder(verilog)
3912 
        net "fsm_dly366" in work.decoder(verilog)
3913 
        net "GND" in work.decoder(verilog)
3914 
        net "VCC" in work.decoder(verilog)
3915 
        net "fsm_dly367" in work.decoder(verilog)
3916 
        net "GND" in work.decoder(verilog)
3917 
        net "GND" in work.decoder(verilog)
3918 
        net "fsm_dly368" in work.decoder(verilog)
3919 
        net "GND" in work.decoder(verilog)
3920 
        net "VCC" in work.decoder(verilog)
3921 
        net "fsm_dly369" in work.decoder(verilog)
3922 
        net "GND" in work.decoder(verilog)
3923 
        net "VCC" in work.decoder(verilog)
3924 
        net "fsm_dly370" in work.decoder(verilog)
3925 
        net "GND" in work.decoder(verilog)
3926 
        net "VCC" in work.decoder(verilog)
3927 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net muxb_ctl_2[1]</font>
3928 
18) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[1]" in work.decoder(verilog)
3929 
    input nets to instance:
3930 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
3931 
        net "VCC" in work.decoder(verilog)
3932 
        net "GND" in work.decoder(verilog)
3933 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
3934 
        net "VCC" in work.decoder(verilog)
3935 
        net "GND" in work.decoder(verilog)
3936 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
3937 
        net "VCC" in work.decoder(verilog)
3938 
        net "GND" in work.decoder(verilog)
3939 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
3940 
        net "GND" in work.decoder(verilog)
3941 
        net "GND" in work.decoder(verilog)
3942 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
3943 
        net "GND" in work.decoder(verilog)
3944 
        net "GND" in work.decoder(verilog)
3945 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
3946 
        net "GND" in work.decoder(verilog)
3947 
        net "GND" in work.decoder(verilog)
3948 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
3949 
        net "GND" in work.decoder(verilog)
3950 
        net "GND" in work.decoder(verilog)
3951 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
3952 
        net "GND" in work.decoder(verilog)
3953 
        net "GND" in work.decoder(verilog)
3954 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
3955 
        net "GND" in work.decoder(verilog)
3956 
        net "GND" in work.decoder(verilog)
3957 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
3958 
        net "GND" in work.decoder(verilog)
3959 
        net "GND" in work.decoder(verilog)
3960 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
3961 
        net "GND" in work.decoder(verilog)
3962 
        net "GND" in work.decoder(verilog)
3963 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
3964 
        net "GND" in work.decoder(verilog)
3965 
        net "GND" in work.decoder(verilog)
3966 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
3967 
        net "GND" in work.decoder(verilog)
3968 
        net "GND" in work.decoder(verilog)
3969 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
3970 
        net "GND" in work.decoder(verilog)
3971 
        net "GND" in work.decoder(verilog)
3972 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
3973 
        net "VCC" in work.decoder(verilog)
3974 
        net "GND" in work.decoder(verilog)
3975 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
3976 
        net "VCC" in work.decoder(verilog)
3977 
        net "GND" in work.decoder(verilog)
3978 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
3979 
        net "VCC" in work.decoder(verilog)
3980 
        net "GND" in work.decoder(verilog)
3981 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
3982 
        net "VCC" in work.decoder(verilog)
3983 
        net "GND" in work.decoder(verilog)
3984 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
3985 
        net "VCC" in work.decoder(verilog)
3986 
        net "GND" in work.decoder(verilog)
3987 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
3988 
        net "VCC" in work.decoder(verilog)
3989 
        net "GND" in work.decoder(verilog)
3990 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
3991 
        net "VCC" in work.decoder(verilog)
3992 
        net "GND" in work.decoder(verilog)
3993 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
3994 
        net "VCC" in work.decoder(verilog)
3995 
        net "GND" in work.decoder(verilog)
3996 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
3997 
        net "VCC" in work.decoder(verilog)
3998 
        net "GND" in work.decoder(verilog)
3999 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
4000 
        net "VCC" in work.decoder(verilog)
4001 
        net "GND" in work.decoder(verilog)
4002 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
4003 
        net "VCC" in work.decoder(verilog)
4004 
        net "GND" in work.decoder(verilog)
4005 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
4006 
        net "VCC" in work.decoder(verilog)
4007 
        net "GND" in work.decoder(verilog)
4008 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
4009 
        net "VCC" in work.decoder(verilog)
4010 
        net "GND" in work.decoder(verilog)
4011 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
4012 
        net "VCC" in work.decoder(verilog)
4013 
        net "GND" in work.decoder(verilog)
4014 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
4015 
        net "GND" in work.decoder(verilog)
4016 
        net "GND" in work.decoder(verilog)
4017 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
4018 
        net "GND" in work.decoder(verilog)
4019 
        net "GND" in work.decoder(verilog)
4020 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
4021 
        net "GND" in work.decoder(verilog)
4022 
        net "GND" in work.decoder(verilog)
4023 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
4024 
        net "GND" in work.decoder(verilog)
4025 
        net "GND" in work.decoder(verilog)
4026 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
4027 
        net "muxb_ctl_1[0]" in work.decoder(verilog)
4028 
        net "muxb_ctl_1[1]" in work.decoder(verilog)
4029 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
4030 
        net "muxb_ctl_1[0]" in work.decoder(verilog)
4031 
        net "muxb_ctl_1[1]" in work.decoder(verilog)
4032 
        net "fsm_dly350" in work.decoder(verilog)
4033 
        net "GND" in work.decoder(verilog)
4034 
        net "GND" in work.decoder(verilog)
4035 
        net "fsm_dly351" in work.decoder(verilog)
4036 
        net "VCC" in work.decoder(verilog)
4037 
        net "GND" in work.decoder(verilog)
4038 
        net "fsm_dly352" in work.decoder(verilog)
4039 
        net "GND" in work.decoder(verilog)
4040 
        net "GND" in work.decoder(verilog)
4041 
        net "fsm_dly353" in work.decoder(verilog)
4042 
        net "GND" in work.decoder(verilog)
4043 
        net "GND" in work.decoder(verilog)
4044 
        net "fsm_dly354" in work.decoder(verilog)
4045 
        net "GND" in work.decoder(verilog)
4046 
        net "GND" in work.decoder(verilog)
4047 
        net "fsm_dly355" in work.decoder(verilog)
4048 
        net "GND" in work.decoder(verilog)
4049 
        net "GND" in work.decoder(verilog)
4050 
        net "fsm_dly356" in work.decoder(verilog)
4051 
        net "GND" in work.decoder(verilog)
4052 
        net "VCC" in work.decoder(verilog)
4053 
        net "fsm_dly357" in work.decoder(verilog)
4054 
        net "GND" in work.decoder(verilog)
4055 
        net "VCC" in work.decoder(verilog)
4056 
        net "fsm_dly358" in work.decoder(verilog)
4057 
        net "GND" in work.decoder(verilog)
4058 
        net "VCC" in work.decoder(verilog)
4059 
        net "fsm_dly359" in work.decoder(verilog)
4060 
        net "GND" in work.decoder(verilog)
4061 
        net "VCC" in work.decoder(verilog)
4062 
        net "fsm_dly360" in work.decoder(verilog)
4063 
        net "GND" in work.decoder(verilog)
4064 
        net "VCC" in work.decoder(verilog)
4065 
        net "fsm_dly361" in work.decoder(verilog)
4066 
        net "GND" in work.decoder(verilog)
4067 
        net "VCC" in work.decoder(verilog)
4068 
        net "fsm_dly362" in work.decoder(verilog)
4069 
        net "GND" in work.decoder(verilog)
4070 
        net "VCC" in work.decoder(verilog)
4071 
        net "fsm_dly363" in work.decoder(verilog)
4072 
        net "GND" in work.decoder(verilog)
4073 
        net "VCC" in work.decoder(verilog)
4074 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
4075 
        net "GND" in work.decoder(verilog)
4076 
        net "VCC" in work.decoder(verilog)
4077 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
4078 
        net "GND" in work.decoder(verilog)
4079 
        net "GND" in work.decoder(verilog)
4080 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
4081 
        net "muxb_ctl_1[0]" in work.decoder(verilog)
4082 
        net "muxb_ctl_1[1]" in work.decoder(verilog)
4083 
        net "fsm_dly365" in work.decoder(verilog)
4084 
        net "GND" in work.decoder(verilog)
4085 
        net "VCC" in work.decoder(verilog)
4086 
        net "fsm_dly366" in work.decoder(verilog)
4087 
        net "GND" in work.decoder(verilog)
4088 
        net "VCC" in work.decoder(verilog)
4089 
        net "fsm_dly367" in work.decoder(verilog)
4090 
        net "GND" in work.decoder(verilog)
4091 
        net "GND" in work.decoder(verilog)
4092 
        net "fsm_dly368" in work.decoder(verilog)
4093 
        net "GND" in work.decoder(verilog)
4094 
        net "VCC" in work.decoder(verilog)
4095 
        net "fsm_dly369" in work.decoder(verilog)
4096 
        net "GND" in work.decoder(verilog)
4097 
        net "VCC" in work.decoder(verilog)
4098 
        net "fsm_dly370" in work.decoder(verilog)
4099 
        net "GND" in work.decoder(verilog)
4100 
        net "VCC" in work.decoder(verilog)
4101 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_2[0]</font>
4102 
19) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[0]" in work.decoder(verilog)
4103 
    input nets to instance:
4104 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
4105 
        net "VCC" in work.decoder(verilog)
4106 
        net "GND" in work.decoder(verilog)
4107 
        net "VCC" in work.decoder(verilog)
4108 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
4109 
        net "VCC" in work.decoder(verilog)
4110 
        net "GND" in work.decoder(verilog)
4111 
        net "VCC" in work.decoder(verilog)
4112 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
4113 
        net "VCC" in work.decoder(verilog)
4114 
        net "GND" in work.decoder(verilog)
4115 
        net "VCC" in work.decoder(verilog)
4116 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
4117 
        net "GND" in work.decoder(verilog)
4118 
        net "GND" in work.decoder(verilog)
4119 
        net "GND" in work.decoder(verilog)
4120 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
4121 
        net "GND" in work.decoder(verilog)
4122 
        net "GND" in work.decoder(verilog)
4123 
        net "GND" in work.decoder(verilog)
4124 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
4125 
        net "GND" in work.decoder(verilog)
4126 
        net "GND" in work.decoder(verilog)
4127 
        net "GND" in work.decoder(verilog)
4128 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
4129 
        net "GND" in work.decoder(verilog)
4130 
        net "VCC" in work.decoder(verilog)
4131 
        net "GND" in work.decoder(verilog)
4132 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
4133 
        net "GND" in work.decoder(verilog)
4134 
        net "GND" in work.decoder(verilog)
4135 
        net "GND" in work.decoder(verilog)
4136 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
4137 
        net "GND" in work.decoder(verilog)
4138 
        net "GND" in work.decoder(verilog)
4139 
        net "GND" in work.decoder(verilog)
4140 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
4141 
        net "GND" in work.decoder(verilog)
4142 
        net "GND" in work.decoder(verilog)
4143 
        net "GND" in work.decoder(verilog)
4144 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
4145 
        net "VCC" in work.decoder(verilog)
4146 
        net "GND" in work.decoder(verilog)
4147 
        net "VCC" in work.decoder(verilog)
4148 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
4149 
        net "VCC" in work.decoder(verilog)
4150 
        net "GND" in work.decoder(verilog)
4151 
        net "VCC" in work.decoder(verilog)
4152 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
4153 
        net "VCC" in work.decoder(verilog)
4154 
        net "GND" in work.decoder(verilog)
4155 
        net "VCC" in work.decoder(verilog)
4156 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
4157 
        net "VCC" in work.decoder(verilog)
4158 
        net "GND" in work.decoder(verilog)
4159 
        net "VCC" in work.decoder(verilog)
4160 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
4161 
        net "VCC" in work.decoder(verilog)
4162 
        net "GND" in work.decoder(verilog)
4163 
        net "VCC" in work.decoder(verilog)
4164 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
4165 
        net "VCC" in work.decoder(verilog)
4166 
        net "GND" in work.decoder(verilog)
4167 
        net "VCC" in work.decoder(verilog)
4168 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
4169 
        net "VCC" in work.decoder(verilog)
4170 
        net "GND" in work.decoder(verilog)
4171 
        net "VCC" in work.decoder(verilog)
4172 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
4173 
        net "VCC" in work.decoder(verilog)
4174 
        net "GND" in work.decoder(verilog)
4175 
        net "VCC" in work.decoder(verilog)
4176 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
4177 
        net "VCC" in work.decoder(verilog)
4178 
        net "GND" in work.decoder(verilog)
4179 
        net "VCC" in work.decoder(verilog)
4180 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
4181 
        net "VCC" in work.decoder(verilog)
4182 
        net "GND" in work.decoder(verilog)
4183 
        net "VCC" in work.decoder(verilog)
4184 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
4185 
        net "VCC" in work.decoder(verilog)
4186 
        net "GND" in work.decoder(verilog)
4187 
        net "VCC" in work.decoder(verilog)
4188 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
4189 
        net "VCC" in work.decoder(verilog)
4190 
        net "GND" in work.decoder(verilog)
4191 
        net "VCC" in work.decoder(verilog)
4192 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
4193 
        net "VCC" in work.decoder(verilog)
4194 
        net "GND" in work.decoder(verilog)
4195 
        net "VCC" in work.decoder(verilog)
4196 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
4197 
        net "VCC" in work.decoder(verilog)
4198 
        net "GND" in work.decoder(verilog)
4199 
        net "VCC" in work.decoder(verilog)
4200 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
4201 
        net "VCC" in work.decoder(verilog)
4202 
        net "GND" in work.decoder(verilog)
4203 
        net "VCC" in work.decoder(verilog)
4204 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
4205 
        net "VCC" in work.decoder(verilog)
4206 
        net "GND" in work.decoder(verilog)
4207 
        net "VCC" in work.decoder(verilog)
4208 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
4209 
        net "VCC" in work.decoder(verilog)
4210 
        net "GND" in work.decoder(verilog)
4211 
        net "VCC" in work.decoder(verilog)
4212 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
4213 
        net "VCC" in work.decoder(verilog)
4214 
        net "GND" in work.decoder(verilog)
4215 
        net "VCC" in work.decoder(verilog)
4216 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
4217 
        net "GND" in work.decoder(verilog)
4218 
        net "GND" in work.decoder(verilog)
4219 
        net "GND" in work.decoder(verilog)
4220 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
4221 
        net "GND" in work.decoder(verilog)
4222 
        net "GND" in work.decoder(verilog)
4223 
        net "VCC" in work.decoder(verilog)
4224 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
4225 
        net "GND" in work.decoder(verilog)
4226 
        net "GND" in work.decoder(verilog)
4227 
        net "VCC" in work.decoder(verilog)
4228 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
4229 
        net "GND" in work.decoder(verilog)
4230 
        net "GND" in work.decoder(verilog)
4231 
        net "GND" in work.decoder(verilog)
4232 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
4233 
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
4234 
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
4235 
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
4236 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
4237 
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
4238 
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
4239 
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
4240 
        net "fsm_dly350" in work.decoder(verilog)
4241 
        net "VCC" in work.decoder(verilog)
4242 
        net "GND" in work.decoder(verilog)
4243 
        net "GND" in work.decoder(verilog)
4244 
        net "fsm_dly351" in work.decoder(verilog)
4245 
        net "VCC" in work.decoder(verilog)
4246 
        net "GND" in work.decoder(verilog)
4247 
        net "GND" in work.decoder(verilog)
4248 
        net "fsm_dly352" in work.decoder(verilog)
4249 
        net "GND" in work.decoder(verilog)
4250 
        net "GND" in work.decoder(verilog)
4251 
        net "VCC" in work.decoder(verilog)
4252 
        net "fsm_dly353" in work.decoder(verilog)
4253 
        net "GND" in work.decoder(verilog)
4254 
        net "GND" in work.decoder(verilog)
4255 
        net "VCC" in work.decoder(verilog)
4256 
        net "fsm_dly354" in work.decoder(verilog)
4257 
        net "GND" in work.decoder(verilog)
4258 
        net "GND" in work.decoder(verilog)
4259 
        net "VCC" in work.decoder(verilog)
4260 
        net "fsm_dly355" in work.decoder(verilog)
4261 
        net "GND" in work.decoder(verilog)
4262 
        net "GND" in work.decoder(verilog)
4263 
        net "VCC" in work.decoder(verilog)
4264 
        net "fsm_dly356" in work.decoder(verilog)
4265 
        net "VCC" in work.decoder(verilog)
4266 
        net "GND" in work.decoder(verilog)
4267 
        net "VCC" in work.decoder(verilog)
4268 
        net "fsm_dly357" in work.decoder(verilog)
4269 
        net "VCC" in work.decoder(verilog)
4270 
        net "GND" in work.decoder(verilog)
4271 
        net "VCC" in work.decoder(verilog)
4272 
        net "fsm_dly358" in work.decoder(verilog)
4273 
        net "VCC" in work.decoder(verilog)
4274 
        net "GND" in work.decoder(verilog)
4275 
        net "VCC" in work.decoder(verilog)
4276 
        net "fsm_dly359" in work.decoder(verilog)
4277 
        net "VCC" in work.decoder(verilog)
4278 
        net "GND" in work.decoder(verilog)
4279 
        net "VCC" in work.decoder(verilog)
4280 
        net "fsm_dly360" in work.decoder(verilog)
4281 
        net "VCC" in work.decoder(verilog)
4282 
        net "GND" in work.decoder(verilog)
4283 
        net "VCC" in work.decoder(verilog)
4284 
        net "fsm_dly361" in work.decoder(verilog)
4285 
        net "VCC" in work.decoder(verilog)
4286 
        net "GND" in work.decoder(verilog)
4287 
        net "VCC" in work.decoder(verilog)
4288 
        net "fsm_dly362" in work.decoder(verilog)
4289 
        net "VCC" in work.decoder(verilog)
4290 
        net "GND" in work.decoder(verilog)
4291 
        net "VCC" in work.decoder(verilog)
4292 
        net "fsm_dly363" in work.decoder(verilog)
4293 
        net "VCC" in work.decoder(verilog)
4294 
        net "GND" in work.decoder(verilog)
4295 
        net "VCC" in work.decoder(verilog)
4296 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
4297 
        net "VCC" in work.decoder(verilog)
4298 
        net "GND" in work.decoder(verilog)
4299 
        net "VCC" in work.decoder(verilog)
4300 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
4301 
        net "GND" in work.decoder(verilog)
4302 
        net "VCC" in work.decoder(verilog)
4303 
        net "VCC" in work.decoder(verilog)
4304 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
4305 
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
4306 
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
4307 
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
4308 
        net "fsm_dly365" in work.decoder(verilog)
4309 
        net "VCC" in work.decoder(verilog)
4310 
        net "GND" in work.decoder(verilog)
4311 
        net "VCC" in work.decoder(verilog)
4312 
        net "fsm_dly366" in work.decoder(verilog)
4313 
        net "VCC" in work.decoder(verilog)
4314 
        net "GND" in work.decoder(verilog)
4315 
        net "VCC" in work.decoder(verilog)
4316 
        net "fsm_dly367" in work.decoder(verilog)
4317 
        net "GND" in work.decoder(verilog)
4318 
        net "GND" in work.decoder(verilog)
4319 
        net "GND" in work.decoder(verilog)
4320 
        net "fsm_dly368" in work.decoder(verilog)
4321 
        net "VCC" in work.decoder(verilog)
4322 
        net "GND" in work.decoder(verilog)
4323 
        net "VCC" in work.decoder(verilog)
4324 
        net "fsm_dly369" in work.decoder(verilog)
4325 
        net "VCC" in work.decoder(verilog)
4326 
        net "GND" in work.decoder(verilog)
4327 
        net "VCC" in work.decoder(verilog)
4328 
        net "fsm_dly370" in work.decoder(verilog)
4329 
        net "VCC" in work.decoder(verilog)
4330 
        net "GND" in work.decoder(verilog)
4331 
        net "VCC" in work.decoder(verilog)
4332 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_2[1]</font>
4333 
20) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[1]" in work.decoder(verilog)
4334 
    input nets to instance:
4335 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
4336 
        net "VCC" in work.decoder(verilog)
4337 
        net "GND" in work.decoder(verilog)
4338 
        net "VCC" in work.decoder(verilog)
4339 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
4340 
        net "VCC" in work.decoder(verilog)
4341 
        net "GND" in work.decoder(verilog)
4342 
        net "VCC" in work.decoder(verilog)
4343 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
4344 
        net "VCC" in work.decoder(verilog)
4345 
        net "GND" in work.decoder(verilog)
4346 
        net "VCC" in work.decoder(verilog)
4347 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
4348 
        net "GND" in work.decoder(verilog)
4349 
        net "GND" in work.decoder(verilog)
4350 
        net "GND" in work.decoder(verilog)
4351 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
4352 
        net "GND" in work.decoder(verilog)
4353 
        net "GND" in work.decoder(verilog)
4354 
        net "GND" in work.decoder(verilog)
4355 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
4356 
        net "GND" in work.decoder(verilog)
4357 
        net "GND" in work.decoder(verilog)
4358 
        net "GND" in work.decoder(verilog)
4359 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
4360 
        net "GND" in work.decoder(verilog)
4361 
        net "VCC" in work.decoder(verilog)
4362 
        net "GND" in work.decoder(verilog)
4363 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
4364 
        net "GND" in work.decoder(verilog)
4365 
        net "GND" in work.decoder(verilog)
4366 
        net "GND" in work.decoder(verilog)
4367 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
4368 
        net "GND" in work.decoder(verilog)
4369 
        net "GND" in work.decoder(verilog)
4370 
        net "GND" in work.decoder(verilog)
4371 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
4372 
        net "GND" in work.decoder(verilog)
4373 
        net "GND" in work.decoder(verilog)
4374 
        net "GND" in work.decoder(verilog)
4375 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
4376 
        net "VCC" in work.decoder(verilog)
4377 
        net "GND" in work.decoder(verilog)
4378 
        net "VCC" in work.decoder(verilog)
4379 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
4380 
        net "VCC" in work.decoder(verilog)
4381 
        net "GND" in work.decoder(verilog)
4382 
        net "VCC" in work.decoder(verilog)
4383 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
4384 
        net "VCC" in work.decoder(verilog)
4385 
        net "GND" in work.decoder(verilog)
4386 
        net "VCC" in work.decoder(verilog)
4387 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
4388 
        net "VCC" in work.decoder(verilog)
4389 
        net "GND" in work.decoder(verilog)
4390 
        net "VCC" in work.decoder(verilog)
4391 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
4392 
        net "VCC" in work.decoder(verilog)
4393 
        net "GND" in work.decoder(verilog)
4394 
        net "VCC" in work.decoder(verilog)
4395 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
4396 
        net "VCC" in work.decoder(verilog)
4397 
        net "GND" in work.decoder(verilog)
4398 
        net "VCC" in work.decoder(verilog)
4399 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
4400 
        net "VCC" in work.decoder(verilog)
4401 
        net "GND" in work.decoder(verilog)
4402 
        net "VCC" in work.decoder(verilog)
4403 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
4404 
        net "VCC" in work.decoder(verilog)
4405 
        net "GND" in work.decoder(verilog)
4406 
        net "VCC" in work.decoder(verilog)
4407 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
4408 
        net "VCC" in work.decoder(verilog)
4409 
        net "GND" in work.decoder(verilog)
4410 
        net "VCC" in work.decoder(verilog)
4411 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
4412 
        net "VCC" in work.decoder(verilog)
4413 
        net "GND" in work.decoder(verilog)
4414 
        net "VCC" in work.decoder(verilog)
4415 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
4416 
        net "VCC" in work.decoder(verilog)
4417 
        net "GND" in work.decoder(verilog)
4418 
        net "VCC" in work.decoder(verilog)
4419 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
4420 
        net "VCC" in work.decoder(verilog)
4421 
        net "GND" in work.decoder(verilog)
4422 
        net "VCC" in work.decoder(verilog)
4423 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
4424 
        net "VCC" in work.decoder(verilog)
4425 
        net "GND" in work.decoder(verilog)
4426 
        net "VCC" in work.decoder(verilog)
4427 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
4428 
        net "VCC" in work.decoder(verilog)
4429 
        net "GND" in work.decoder(verilog)
4430 
        net "VCC" in work.decoder(verilog)
4431 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
4432 
        net "VCC" in work.decoder(verilog)
4433 
        net "GND" in work.decoder(verilog)
4434 
        net "VCC" in work.decoder(verilog)
4435 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
4436 
        net "VCC" in work.decoder(verilog)
4437 
        net "GND" in work.decoder(verilog)
4438 
        net "VCC" in work.decoder(verilog)
4439 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
4440 
        net "VCC" in work.decoder(verilog)
4441 
        net "GND" in work.decoder(verilog)
4442 
        net "VCC" in work.decoder(verilog)
4443 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
4444 
        net "VCC" in work.decoder(verilog)
4445 
        net "GND" in work.decoder(verilog)
4446 
        net "VCC" in work.decoder(verilog)
4447 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
4448 
        net "GND" in work.decoder(verilog)
4449 
        net "GND" in work.decoder(verilog)
4450 
        net "GND" in work.decoder(verilog)
4451 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
4452 
        net "GND" in work.decoder(verilog)
4453 
        net "GND" in work.decoder(verilog)
4454 
        net "VCC" in work.decoder(verilog)
4455 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
4456 
        net "GND" in work.decoder(verilog)
4457 
        net "GND" in work.decoder(verilog)
4458 
        net "VCC" in work.decoder(verilog)
4459 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
4460 
        net "GND" in work.decoder(verilog)
4461 
        net "GND" in work.decoder(verilog)
4462 
        net "GND" in work.decoder(verilog)
4463 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
4464 
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
4465 
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
4466 
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
4467 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
4468 
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
4469 
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
4470 
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
4471 
        net "fsm_dly350" in work.decoder(verilog)
4472 
        net "VCC" in work.decoder(verilog)
4473 
        net "GND" in work.decoder(verilog)
4474 
        net "GND" in work.decoder(verilog)
4475 
        net "fsm_dly351" in work.decoder(verilog)
4476 
        net "VCC" in work.decoder(verilog)
4477 
        net "GND" in work.decoder(verilog)
4478 
        net "GND" in work.decoder(verilog)
4479 
        net "fsm_dly352" in work.decoder(verilog)
4480 
        net "GND" in work.decoder(verilog)
4481 
        net "GND" in work.decoder(verilog)
4482 
        net "VCC" in work.decoder(verilog)
4483 
        net "fsm_dly353" in work.decoder(verilog)
4484 
        net "GND" in work.decoder(verilog)
4485 
        net "GND" in work.decoder(verilog)
4486 
        net "VCC" in work.decoder(verilog)
4487 
        net "fsm_dly354" in work.decoder(verilog)
4488 
        net "GND" in work.decoder(verilog)
4489 
        net "GND" in work.decoder(verilog)
4490 
        net "VCC" in work.decoder(verilog)
4491 
        net "fsm_dly355" in work.decoder(verilog)
4492 
        net "GND" in work.decoder(verilog)
4493 
        net "GND" in work.decoder(verilog)
4494 
        net "VCC" in work.decoder(verilog)
4495 
        net "fsm_dly356" in work.decoder(verilog)
4496 
        net "VCC" in work.decoder(verilog)
4497 
        net "GND" in work.decoder(verilog)
4498 
        net "VCC" in work.decoder(verilog)
4499 
        net "fsm_dly357" in work.decoder(verilog)
4500 
        net "VCC" in work.decoder(verilog)
4501 
        net "GND" in work.decoder(verilog)
4502 
        net "VCC" in work.decoder(verilog)
4503 
        net "fsm_dly358" in work.decoder(verilog)
4504 
        net "VCC" in work.decoder(verilog)
4505 
        net "GND" in work.decoder(verilog)
4506 
        net "VCC" in work.decoder(verilog)
4507 
        net "fsm_dly359" in work.decoder(verilog)
4508 
        net "VCC" in work.decoder(verilog)
4509 
        net "GND" in work.decoder(verilog)
4510 
        net "VCC" in work.decoder(verilog)
4511 
        net "fsm_dly360" in work.decoder(verilog)
4512 
        net "VCC" in work.decoder(verilog)
4513 
        net "GND" in work.decoder(verilog)
4514 
        net "VCC" in work.decoder(verilog)
4515 
        net "fsm_dly361" in work.decoder(verilog)
4516 
        net "VCC" in work.decoder(verilog)
4517 
        net "GND" in work.decoder(verilog)
4518 
        net "VCC" in work.decoder(verilog)
4519 
        net "fsm_dly362" in work.decoder(verilog)
4520 
        net "VCC" in work.decoder(verilog)
4521 
        net "GND" in work.decoder(verilog)
4522 
        net "VCC" in work.decoder(verilog)
4523 
        net "fsm_dly363" in work.decoder(verilog)
4524 
        net "VCC" in work.decoder(verilog)
4525 
        net "GND" in work.decoder(verilog)
4526 
        net "VCC" in work.decoder(verilog)
4527 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
4528 
        net "VCC" in work.decoder(verilog)
4529 
        net "GND" in work.decoder(verilog)
4530 
        net "VCC" in work.decoder(verilog)
4531 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
4532 
        net "GND" in work.decoder(verilog)
4533 
        net "VCC" in work.decoder(verilog)
4534 
        net "VCC" in work.decoder(verilog)
4535 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
4536 
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
4537 
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
4538 
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
4539 
        net "fsm_dly365" in work.decoder(verilog)
4540 
        net "VCC" in work.decoder(verilog)
4541 
        net "GND" in work.decoder(verilog)
4542 
        net "VCC" in work.decoder(verilog)
4543 
        net "fsm_dly366" in work.decoder(verilog)
4544 
        net "VCC" in work.decoder(verilog)
4545 
        net "GND" in work.decoder(verilog)
4546 
        net "VCC" in work.decoder(verilog)
4547 
        net "fsm_dly367" in work.decoder(verilog)
4548 
        net "GND" in work.decoder(verilog)
4549 
        net "GND" in work.decoder(verilog)
4550 
        net "GND" in work.decoder(verilog)
4551 
        net "fsm_dly368" in work.decoder(verilog)
4552 
        net "VCC" in work.decoder(verilog)
4553 
        net "GND" in work.decoder(verilog)
4554 
        net "VCC" in work.decoder(verilog)
4555 
        net "fsm_dly369" in work.decoder(verilog)
4556 
        net "VCC" in work.decoder(verilog)
4557 
        net "GND" in work.decoder(verilog)
4558 
        net "VCC" in work.decoder(verilog)
4559 
        net "fsm_dly370" in work.decoder(verilog)
4560 
        net "VCC" in work.decoder(verilog)
4561 
        net "GND" in work.decoder(verilog)
4562 
        net "VCC" in work.decoder(verilog)
4563 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net pc_gen_ctl_2[2]</font>
4564 
21) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[2]" in work.decoder(verilog)
4565 
    input nets to instance:
4566 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
4567 
        net "VCC" in work.decoder(verilog)
4568 
        net "GND" in work.decoder(verilog)
4569 
        net "VCC" in work.decoder(verilog)
4570 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
4571 
        net "VCC" in work.decoder(verilog)
4572 
        net "GND" in work.decoder(verilog)
4573 
        net "VCC" in work.decoder(verilog)
4574 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
4575 
        net "VCC" in work.decoder(verilog)
4576 
        net "GND" in work.decoder(verilog)
4577 
        net "VCC" in work.decoder(verilog)
4578 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
4579 
        net "GND" in work.decoder(verilog)
4580 
        net "GND" in work.decoder(verilog)
4581 
        net "GND" in work.decoder(verilog)
4582 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
4583 
        net "GND" in work.decoder(verilog)
4584 
        net "GND" in work.decoder(verilog)
4585 
        net "GND" in work.decoder(verilog)
4586 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
4587 
        net "GND" in work.decoder(verilog)
4588 
        net "GND" in work.decoder(verilog)
4589 
        net "GND" in work.decoder(verilog)
4590 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
4591 
        net "GND" in work.decoder(verilog)
4592 
        net "VCC" in work.decoder(verilog)
4593 
        net "GND" in work.decoder(verilog)
4594 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
4595 
        net "GND" in work.decoder(verilog)
4596 
        net "GND" in work.decoder(verilog)
4597 
        net "GND" in work.decoder(verilog)
4598 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
4599 
        net "GND" in work.decoder(verilog)
4600 
        net "GND" in work.decoder(verilog)
4601 
        net "GND" in work.decoder(verilog)
4602 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
4603 
        net "GND" in work.decoder(verilog)
4604 
        net "GND" in work.decoder(verilog)
4605 
        net "GND" in work.decoder(verilog)
4606 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
4607 
        net "VCC" in work.decoder(verilog)
4608 
        net "GND" in work.decoder(verilog)
4609 
        net "VCC" in work.decoder(verilog)
4610 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
4611 
        net "VCC" in work.decoder(verilog)
4612 
        net "GND" in work.decoder(verilog)
4613 
        net "VCC" in work.decoder(verilog)
4614 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
4615 
        net "VCC" in work.decoder(verilog)
4616 
        net "GND" in work.decoder(verilog)
4617 
        net "VCC" in work.decoder(verilog)
4618 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
4619 
        net "VCC" in work.decoder(verilog)
4620 
        net "GND" in work.decoder(verilog)
4621 
        net "VCC" in work.decoder(verilog)
4622 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
4623 
        net "VCC" in work.decoder(verilog)
4624 
        net "GND" in work.decoder(verilog)
4625 
        net "VCC" in work.decoder(verilog)
4626 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
4627 
        net "VCC" in work.decoder(verilog)
4628 
        net "GND" in work.decoder(verilog)
4629 
        net "VCC" in work.decoder(verilog)
4630 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
4631 
        net "VCC" in work.decoder(verilog)
4632 
        net "GND" in work.decoder(verilog)
4633 
        net "VCC" in work.decoder(verilog)
4634 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
4635 
        net "VCC" in work.decoder(verilog)
4636 
        net "GND" in work.decoder(verilog)
4637 
        net "VCC" in work.decoder(verilog)
4638 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
4639 
        net "VCC" in work.decoder(verilog)
4640 
        net "GND" in work.decoder(verilog)
4641 
        net "VCC" in work.decoder(verilog)
4642 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
4643 
        net "VCC" in work.decoder(verilog)
4644 
        net "GND" in work.decoder(verilog)
4645 
        net "VCC" in work.decoder(verilog)
4646 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
4647 
        net "VCC" in work.decoder(verilog)
4648 
        net "GND" in work.decoder(verilog)
4649 
        net "VCC" in work.decoder(verilog)
4650 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
4651 
        net "VCC" in work.decoder(verilog)
4652 
        net "GND" in work.decoder(verilog)
4653 
        net "VCC" in work.decoder(verilog)
4654 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
4655 
        net "VCC" in work.decoder(verilog)
4656 
        net "GND" in work.decoder(verilog)
4657 
        net "VCC" in work.decoder(verilog)
4658 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
4659 
        net "VCC" in work.decoder(verilog)
4660 
        net "GND" in work.decoder(verilog)
4661 
        net "VCC" in work.decoder(verilog)
4662 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
4663 
        net "VCC" in work.decoder(verilog)
4664 
        net "GND" in work.decoder(verilog)
4665 
        net "VCC" in work.decoder(verilog)
4666 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
4667 
        net "VCC" in work.decoder(verilog)
4668 
        net "GND" in work.decoder(verilog)
4669 
        net "VCC" in work.decoder(verilog)
4670 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
4671 
        net "VCC" in work.decoder(verilog)
4672 
        net "GND" in work.decoder(verilog)
4673 
        net "VCC" in work.decoder(verilog)
4674 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
4675 
        net "VCC" in work.decoder(verilog)
4676 
        net "GND" in work.decoder(verilog)
4677 
        net "VCC" in work.decoder(verilog)
4678 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
4679 
        net "GND" in work.decoder(verilog)
4680 
        net "GND" in work.decoder(verilog)
4681 
        net "GND" in work.decoder(verilog)
4682 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
4683 
        net "GND" in work.decoder(verilog)
4684 
        net "GND" in work.decoder(verilog)
4685 
        net "VCC" in work.decoder(verilog)
4686 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
4687 
        net "GND" in work.decoder(verilog)
4688 
        net "GND" in work.decoder(verilog)
4689 
        net "VCC" in work.decoder(verilog)
4690 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
4691 
        net "GND" in work.decoder(verilog)
4692 
        net "GND" in work.decoder(verilog)
4693 
        net "GND" in work.decoder(verilog)
4694 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
4695 
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
4696 
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
4697 
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
4698 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
4699 
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
4700 
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
4701 
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
4702 
        net "fsm_dly350" in work.decoder(verilog)
4703 
        net "VCC" in work.decoder(verilog)
4704 
        net "GND" in work.decoder(verilog)
4705 
        net "GND" in work.decoder(verilog)
4706 
        net "fsm_dly351" in work.decoder(verilog)
4707 
        net "VCC" in work.decoder(verilog)
4708 
        net "GND" in work.decoder(verilog)
4709 
        net "GND" in work.decoder(verilog)
4710 
        net "fsm_dly352" in work.decoder(verilog)
4711 
        net "GND" in work.decoder(verilog)
4712 
        net "GND" in work.decoder(verilog)
4713 
        net "VCC" in work.decoder(verilog)
4714 
        net "fsm_dly353" in work.decoder(verilog)
4715 
        net "GND" in work.decoder(verilog)
4716 
        net "GND" in work.decoder(verilog)
4717 
        net "VCC" in work.decoder(verilog)
4718 
        net "fsm_dly354" in work.decoder(verilog)
4719 
        net "GND" in work.decoder(verilog)
4720 
        net "GND" in work.decoder(verilog)
4721 
        net "VCC" in work.decoder(verilog)
4722 
        net "fsm_dly355" in work.decoder(verilog)
4723 
        net "GND" in work.decoder(verilog)
4724 
        net "GND" in work.decoder(verilog)
4725 
        net "VCC" in work.decoder(verilog)
4726 
        net "fsm_dly356" in work.decoder(verilog)
4727 
        net "VCC" in work.decoder(verilog)
4728 
        net "GND" in work.decoder(verilog)
4729 
        net "VCC" in work.decoder(verilog)
4730 
        net "fsm_dly357" in work.decoder(verilog)
4731 
        net "VCC" in work.decoder(verilog)
4732 
        net "GND" in work.decoder(verilog)
4733 
        net "VCC" in work.decoder(verilog)
4734 
        net "fsm_dly358" in work.decoder(verilog)
4735 
        net "VCC" in work.decoder(verilog)
4736 
        net "GND" in work.decoder(verilog)
4737 
        net "VCC" in work.decoder(verilog)
4738 
        net "fsm_dly359" in work.decoder(verilog)
4739 
        net "VCC" in work.decoder(verilog)
4740 
        net "GND" in work.decoder(verilog)
4741 
        net "VCC" in work.decoder(verilog)
4742 
        net "fsm_dly360" in work.decoder(verilog)
4743 
        net "VCC" in work.decoder(verilog)
4744 
        net "GND" in work.decoder(verilog)
4745 
        net "VCC" in work.decoder(verilog)
4746 
        net "fsm_dly361" in work.decoder(verilog)
4747 
        net "VCC" in work.decoder(verilog)
4748 
        net "GND" in work.decoder(verilog)
4749 
        net "VCC" in work.decoder(verilog)
4750 
        net "fsm_dly362" in work.decoder(verilog)
4751 
        net "VCC" in work.decoder(verilog)
4752 
        net "GND" in work.decoder(verilog)
4753 
        net "VCC" in work.decoder(verilog)
4754 
        net "fsm_dly363" in work.decoder(verilog)
4755 
        net "VCC" in work.decoder(verilog)
4756 
        net "GND" in work.decoder(verilog)
4757 
        net "VCC" in work.decoder(verilog)
4758 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
4759 
        net "VCC" in work.decoder(verilog)
4760 
        net "GND" in work.decoder(verilog)
4761 
        net "VCC" in work.decoder(verilog)
4762 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
4763 
        net "GND" in work.decoder(verilog)
4764 
        net "VCC" in work.decoder(verilog)
4765 
        net "VCC" in work.decoder(verilog)
4766 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
4767 
        net "pc_gen_ctl_1[0]" in work.decoder(verilog)
4768 
        net "pc_gen_ctl_1[1]" in work.decoder(verilog)
4769 
        net "pc_gen_ctl_1[2]" in work.decoder(verilog)
4770 
        net "fsm_dly365" in work.decoder(verilog)
4771 
        net "VCC" in work.decoder(verilog)
4772 
        net "GND" in work.decoder(verilog)
4773 
        net "VCC" in work.decoder(verilog)
4774 
        net "fsm_dly366" in work.decoder(verilog)
4775 
        net "VCC" in work.decoder(verilog)
4776 
        net "GND" in work.decoder(verilog)
4777 
        net "VCC" in work.decoder(verilog)
4778 
        net "fsm_dly367" in work.decoder(verilog)
4779 
        net "GND" in work.decoder(verilog)
4780 
        net "GND" in work.decoder(verilog)
4781 
        net "GND" in work.decoder(verilog)
4782 
        net "fsm_dly368" in work.decoder(verilog)
4783 
        net "VCC" in work.decoder(verilog)
4784 
        net "GND" in work.decoder(verilog)
4785 
        net "VCC" in work.decoder(verilog)
4786 
        net "fsm_dly369" in work.decoder(verilog)
4787 
        net "VCC" in work.decoder(verilog)
4788 
        net "GND" in work.decoder(verilog)
4789 
        net "VCC" in work.decoder(verilog)
4790 
        net "fsm_dly370" in work.decoder(verilog)
4791 
        net "VCC" in work.decoder(verilog)
4792 
        net "GND" in work.decoder(verilog)
4793 
        net "VCC" in work.decoder(verilog)
4794 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net rd_sel_2[0]</font>
4795 
22) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[0]" in work.decoder(verilog)
4796 
    input nets to instance:
4797 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
4798 
        net "VCC" in work.decoder(verilog)
4799 
        net "GND" in work.decoder(verilog)
4800 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
4801 
        net "VCC" in work.decoder(verilog)
4802 
        net "GND" in work.decoder(verilog)
4803 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
4804 
        net "VCC" in work.decoder(verilog)
4805 
        net "GND" in work.decoder(verilog)
4806 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
4807 
        net "GND" in work.decoder(verilog)
4808 
        net "GND" in work.decoder(verilog)
4809 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
4810 
        net "GND" in work.decoder(verilog)
4811 
        net "GND" in work.decoder(verilog)
4812 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
4813 
        net "GND" in work.decoder(verilog)
4814 
        net "GND" in work.decoder(verilog)
4815 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
4816 
        net "GND" in work.decoder(verilog)
4817 
        net "GND" in work.decoder(verilog)
4818 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
4819 
        net "GND" in work.decoder(verilog)
4820 
        net "GND" in work.decoder(verilog)
4821 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
4822 
        net "GND" in work.decoder(verilog)
4823 
        net "GND" in work.decoder(verilog)
4824 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
4825 
        net "GND" in work.decoder(verilog)
4826 
        net "GND" in work.decoder(verilog)
4827 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
4828 
        net "VCC" in work.decoder(verilog)
4829 
        net "GND" in work.decoder(verilog)
4830 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
4831 
        net "GND" in work.decoder(verilog)
4832 
        net "GND" in work.decoder(verilog)
4833 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
4834 
        net "VCC" in work.decoder(verilog)
4835 
        net "GND" in work.decoder(verilog)
4836 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
4837 
        net "GND" in work.decoder(verilog)
4838 
        net "GND" in work.decoder(verilog)
4839 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
4840 
        net "GND" in work.decoder(verilog)
4841 
        net "GND" in work.decoder(verilog)
4842 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
4843 
        net "GND" in work.decoder(verilog)
4844 
        net "GND" in work.decoder(verilog)
4845 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
4846 
        net "GND" in work.decoder(verilog)
4847 
        net "GND" in work.decoder(verilog)
4848 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
4849 
        net "GND" in work.decoder(verilog)
4850 
        net "GND" in work.decoder(verilog)
4851 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
4852 
        net "VCC" in work.decoder(verilog)
4853 
        net "GND" in work.decoder(verilog)
4854 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
4855 
        net "VCC" in work.decoder(verilog)
4856 
        net "GND" in work.decoder(verilog)
4857 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
4858 
        net "VCC" in work.decoder(verilog)
4859 
        net "GND" in work.decoder(verilog)
4860 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
4861 
        net "VCC" in work.decoder(verilog)
4862 
        net "GND" in work.decoder(verilog)
4863 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
4864 
        net "VCC" in work.decoder(verilog)
4865 
        net "GND" in work.decoder(verilog)
4866 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
4867 
        net "VCC" in work.decoder(verilog)
4868 
        net "GND" in work.decoder(verilog)
4869 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
4870 
        net "VCC" in work.decoder(verilog)
4871 
        net "GND" in work.decoder(verilog)
4872 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
4873 
        net "VCC" in work.decoder(verilog)
4874 
        net "GND" in work.decoder(verilog)
4875 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
4876 
        net "VCC" in work.decoder(verilog)
4877 
        net "GND" in work.decoder(verilog)
4878 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
4879 
        net "VCC" in work.decoder(verilog)
4880 
        net "GND" in work.decoder(verilog)
4881 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
4882 
        net "GND" in work.decoder(verilog)
4883 
        net "GND" in work.decoder(verilog)
4884 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
4885 
        net "GND" in work.decoder(verilog)
4886 
        net "GND" in work.decoder(verilog)
4887 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
4888 
        net "GND" in work.decoder(verilog)
4889 
        net "GND" in work.decoder(verilog)
4890 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
4891 
        net "GND" in work.decoder(verilog)
4892 
        net "GND" in work.decoder(verilog)
4893 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
4894 
        net "rd_sel_1[0]" in work.decoder(verilog)
4895 
        net "rd_sel_1[1]" in work.decoder(verilog)
4896 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
4897 
        net "rd_sel_1[0]" in work.decoder(verilog)
4898 
        net "rd_sel_1[1]" in work.decoder(verilog)
4899 
        net "fsm_dly350" in work.decoder(verilog)
4900 
        net "GND" in work.decoder(verilog)
4901 
        net "GND" in work.decoder(verilog)
4902 
        net "fsm_dly351" in work.decoder(verilog)
4903 
        net "VCC" in work.decoder(verilog)
4904 
        net "VCC" in work.decoder(verilog)
4905 
        net "fsm_dly352" in work.decoder(verilog)
4906 
        net "GND" in work.decoder(verilog)
4907 
        net "GND" in work.decoder(verilog)
4908 
        net "fsm_dly353" in work.decoder(verilog)
4909 
        net "GND" in work.decoder(verilog)
4910 
        net "GND" in work.decoder(verilog)
4911 
        net "fsm_dly354" in work.decoder(verilog)
4912 
        net "GND" in work.decoder(verilog)
4913 
        net "GND" in work.decoder(verilog)
4914 
        net "fsm_dly355" in work.decoder(verilog)
4915 
        net "GND" in work.decoder(verilog)
4916 
        net "GND" in work.decoder(verilog)
4917 
        net "fsm_dly356" in work.decoder(verilog)
4918 
        net "GND" in work.decoder(verilog)
4919 
        net "VCC" in work.decoder(verilog)
4920 
        net "fsm_dly357" in work.decoder(verilog)
4921 
        net "GND" in work.decoder(verilog)
4922 
        net "VCC" in work.decoder(verilog)
4923 
        net "fsm_dly358" in work.decoder(verilog)
4924 
        net "GND" in work.decoder(verilog)
4925 
        net "VCC" in work.decoder(verilog)
4926 
        net "fsm_dly359" in work.decoder(verilog)
4927 
        net "GND" in work.decoder(verilog)
4928 
        net "VCC" in work.decoder(verilog)
4929 
        net "fsm_dly360" in work.decoder(verilog)
4930 
        net "GND" in work.decoder(verilog)
4931 
        net "VCC" in work.decoder(verilog)
4932 
        net "fsm_dly361" in work.decoder(verilog)
4933 
        net "GND" in work.decoder(verilog)
4934 
        net "VCC" in work.decoder(verilog)
4935 
        net "fsm_dly362" in work.decoder(verilog)
4936 
        net "GND" in work.decoder(verilog)
4937 
        net "VCC" in work.decoder(verilog)
4938 
        net "fsm_dly363" in work.decoder(verilog)
4939 
        net "GND" in work.decoder(verilog)
4940 
        net "VCC" in work.decoder(verilog)
4941 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
4942 
        net "VCC" in work.decoder(verilog)
4943 
        net "GND" in work.decoder(verilog)
4944 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
4945 
        net "GND" in work.decoder(verilog)
4946 
        net "GND" in work.decoder(verilog)
4947 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
4948 
        net "rd_sel_1[0]" in work.decoder(verilog)
4949 
        net "rd_sel_1[1]" in work.decoder(verilog)
4950 
        net "fsm_dly365" in work.decoder(verilog)
4951 
        net "GND" in work.decoder(verilog)
4952 
        net "VCC" in work.decoder(verilog)
4953 
        net "fsm_dly366" in work.decoder(verilog)
4954 
        net "GND" in work.decoder(verilog)
4955 
        net "VCC" in work.decoder(verilog)
4956 
        net "fsm_dly367" in work.decoder(verilog)
4957 
        net "GND" in work.decoder(verilog)
4958 
        net "GND" in work.decoder(verilog)
4959 
        net "fsm_dly368" in work.decoder(verilog)
4960 
        net "GND" in work.decoder(verilog)
4961 
        net "VCC" in work.decoder(verilog)
4962 
        net "fsm_dly369" in work.decoder(verilog)
4963 
        net "GND" in work.decoder(verilog)
4964 
        net "VCC" in work.decoder(verilog)
4965 
        net "fsm_dly370" in work.decoder(verilog)
4966 
        net "GND" in work.decoder(verilog)
4967 
        net "VCC" in work.decoder(verilog)
4968 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net rd_sel_2[1]</font>
4969 
23) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[1]" in work.decoder(verilog)
4970 
    input nets to instance:
4971 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
4972 
        net "VCC" in work.decoder(verilog)
4973 
        net "GND" in work.decoder(verilog)
4974 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
4975 
        net "VCC" in work.decoder(verilog)
4976 
        net "GND" in work.decoder(verilog)
4977 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
4978 
        net "VCC" in work.decoder(verilog)
4979 
        net "GND" in work.decoder(verilog)
4980 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
4981 
        net "GND" in work.decoder(verilog)
4982 
        net "GND" in work.decoder(verilog)
4983 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
4984 
        net "GND" in work.decoder(verilog)
4985 
        net "GND" in work.decoder(verilog)
4986 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
4987 
        net "GND" in work.decoder(verilog)
4988 
        net "GND" in work.decoder(verilog)
4989 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
4990 
        net "GND" in work.decoder(verilog)
4991 
        net "GND" in work.decoder(verilog)
4992 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
4993 
        net "GND" in work.decoder(verilog)
4994 
        net "GND" in work.decoder(verilog)
4995 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
4996 
        net "GND" in work.decoder(verilog)
4997 
        net "GND" in work.decoder(verilog)
4998 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
4999 
        net "GND" in work.decoder(verilog)
5000 
        net "GND" in work.decoder(verilog)
5001 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
5002 
        net "VCC" in work.decoder(verilog)
5003 
        net "GND" in work.decoder(verilog)
5004 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
5005 
        net "GND" in work.decoder(verilog)
5006 
        net "GND" in work.decoder(verilog)
5007 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
5008 
        net "VCC" in work.decoder(verilog)
5009 
        net "GND" in work.decoder(verilog)
5010 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
5011 
        net "GND" in work.decoder(verilog)
5012 
        net "GND" in work.decoder(verilog)
5013 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
5014 
        net "GND" in work.decoder(verilog)
5015 
        net "GND" in work.decoder(verilog)
5016 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
5017 
        net "GND" in work.decoder(verilog)
5018 
        net "GND" in work.decoder(verilog)
5019 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
5020 
        net "GND" in work.decoder(verilog)
5021 
        net "GND" in work.decoder(verilog)
5022 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
5023 
        net "GND" in work.decoder(verilog)
5024 
        net "GND" in work.decoder(verilog)
5025 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
5026 
        net "VCC" in work.decoder(verilog)
5027 
        net "GND" in work.decoder(verilog)
5028 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
5029 
        net "VCC" in work.decoder(verilog)
5030 
        net "GND" in work.decoder(verilog)
5031 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
5032 
        net "VCC" in work.decoder(verilog)
5033 
        net "GND" in work.decoder(verilog)
5034 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
5035 
        net "VCC" in work.decoder(verilog)
5036 
        net "GND" in work.decoder(verilog)
5037 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
5038 
        net "VCC" in work.decoder(verilog)
5039 
        net "GND" in work.decoder(verilog)
5040 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
5041 
        net "VCC" in work.decoder(verilog)
5042 
        net "GND" in work.decoder(verilog)
5043 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
5044 
        net "VCC" in work.decoder(verilog)
5045 
        net "GND" in work.decoder(verilog)
5046 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
5047 
        net "VCC" in work.decoder(verilog)
5048 
        net "GND" in work.decoder(verilog)
5049 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
5050 
        net "VCC" in work.decoder(verilog)
5051 
        net "GND" in work.decoder(verilog)
5052 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
5053 
        net "VCC" in work.decoder(verilog)
5054 
        net "GND" in work.decoder(verilog)
5055 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
5056 
        net "GND" in work.decoder(verilog)
5057 
        net "GND" in work.decoder(verilog)
5058 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
5059 
        net "GND" in work.decoder(verilog)
5060 
        net "GND" in work.decoder(verilog)
5061 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
5062 
        net "GND" in work.decoder(verilog)
5063 
        net "GND" in work.decoder(verilog)
5064 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
5065 
        net "GND" in work.decoder(verilog)
5066 
        net "GND" in work.decoder(verilog)
5067 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
5068 
        net "rd_sel_1[0]" in work.decoder(verilog)
5069 
        net "rd_sel_1[1]" in work.decoder(verilog)
5070 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
5071 
        net "rd_sel_1[0]" in work.decoder(verilog)
5072 
        net "rd_sel_1[1]" in work.decoder(verilog)
5073 
        net "fsm_dly350" in work.decoder(verilog)
5074 
        net "GND" in work.decoder(verilog)
5075 
        net "GND" in work.decoder(verilog)
5076 
        net "fsm_dly351" in work.decoder(verilog)
5077 
        net "VCC" in work.decoder(verilog)
5078 
        net "VCC" in work.decoder(verilog)
5079 
        net "fsm_dly352" in work.decoder(verilog)
5080 
        net "GND" in work.decoder(verilog)
5081 
        net "GND" in work.decoder(verilog)
5082 
        net "fsm_dly353" in work.decoder(verilog)
5083 
        net "GND" in work.decoder(verilog)
5084 
        net "GND" in work.decoder(verilog)
5085 
        net "fsm_dly354" in work.decoder(verilog)
5086 
        net "GND" in work.decoder(verilog)
5087 
        net "GND" in work.decoder(verilog)
5088 
        net "fsm_dly355" in work.decoder(verilog)
5089 
        net "GND" in work.decoder(verilog)
5090 
        net "GND" in work.decoder(verilog)
5091 
        net "fsm_dly356" in work.decoder(verilog)
5092 
        net "GND" in work.decoder(verilog)
5093 
        net "VCC" in work.decoder(verilog)
5094 
        net "fsm_dly357" in work.decoder(verilog)
5095 
        net "GND" in work.decoder(verilog)
5096 
        net "VCC" in work.decoder(verilog)
5097 
        net "fsm_dly358" in work.decoder(verilog)
5098 
        net "GND" in work.decoder(verilog)
5099 
        net "VCC" in work.decoder(verilog)
5100 
        net "fsm_dly359" in work.decoder(verilog)
5101 
        net "GND" in work.decoder(verilog)
5102 
        net "VCC" in work.decoder(verilog)
5103 
        net "fsm_dly360" in work.decoder(verilog)
5104 
        net "GND" in work.decoder(verilog)
5105 
        net "VCC" in work.decoder(verilog)
5106 
        net "fsm_dly361" in work.decoder(verilog)
5107 
        net "GND" in work.decoder(verilog)
5108 
        net "VCC" in work.decoder(verilog)
5109 
        net "fsm_dly362" in work.decoder(verilog)
5110 
        net "GND" in work.decoder(verilog)
5111 
        net "VCC" in work.decoder(verilog)
5112 
        net "fsm_dly363" in work.decoder(verilog)
5113 
        net "GND" in work.decoder(verilog)
5114 
        net "VCC" in work.decoder(verilog)
5115 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
5116 
        net "VCC" in work.decoder(verilog)
5117 
        net "GND" in work.decoder(verilog)
5118 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
5119 
        net "GND" in work.decoder(verilog)
5120 
        net "GND" in work.decoder(verilog)
5121 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
5122 
        net "rd_sel_1[0]" in work.decoder(verilog)
5123 
        net "rd_sel_1[1]" in work.decoder(verilog)
5124 
        net "fsm_dly365" in work.decoder(verilog)
5125 
        net "GND" in work.decoder(verilog)
5126 
        net "VCC" in work.decoder(verilog)
5127 
        net "fsm_dly366" in work.decoder(verilog)
5128 
        net "GND" in work.decoder(verilog)
5129 
        net "VCC" in work.decoder(verilog)
5130 
        net "fsm_dly367" in work.decoder(verilog)
5131 
        net "GND" in work.decoder(verilog)
5132 
        net "GND" in work.decoder(verilog)
5133 
        net "fsm_dly368" in work.decoder(verilog)
5134 
        net "GND" in work.decoder(verilog)
5135 
        net "VCC" in work.decoder(verilog)
5136 
        net "fsm_dly369" in work.decoder(verilog)
5137 
        net "GND" in work.decoder(verilog)
5138 
        net "VCC" in work.decoder(verilog)
5139 
        net "fsm_dly370" in work.decoder(verilog)
5140 
        net "GND" in work.decoder(verilog)
5141 
        net "VCC" in work.decoder(verilog)
5142 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_2[0]</font>
5143 
24) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[0]" in work.decoder(verilog)
5144 
    input nets to instance:
5145 
        net "un1_fsm_dly352_1" in work.decoder(verilog)
5146 
        net "GND" in work.decoder(verilog)
5147 
        net "GND" in work.decoder(verilog)
5148 
        net "GND" in work.decoder(verilog)
5149 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
5150 
        net "GND" in work.decoder(verilog)
5151 
        net "VCC" in work.decoder(verilog)
5152 
        net "VCC" in work.decoder(verilog)
5153 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
5154 
        net "GND" in work.decoder(verilog)
5155 
        net "GND" in work.decoder(verilog)
5156 
        net "VCC" in work.decoder(verilog)
5157 
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
5158 
        net "cmp_ctl_1[0]" in work.decoder(verilog)
5159 
        net "cmp_ctl_1[1]" in work.decoder(verilog)
5160 
        net "cmp_ctl_1[2]" in work.decoder(verilog)
5161 
        net "fsm_dly352" in work.decoder(verilog)
5162 
        net "VCC" in work.decoder(verilog)
5163 
        net "GND" in work.decoder(verilog)
5164 
        net "GND" in work.decoder(verilog)
5165 
        net "fsm_dly353" in work.decoder(verilog)
5166 
        net "GND" in work.decoder(verilog)
5167 
        net "VCC" in work.decoder(verilog)
5168 
        net "GND" in work.decoder(verilog)
5169 
        net "fsm_dly354" in work.decoder(verilog)
5170 
        net "VCC" in work.decoder(verilog)
5171 
        net "VCC" in work.decoder(verilog)
5172 
        net "GND" in work.decoder(verilog)
5173 
        net "fsm_dly355" in work.decoder(verilog)
5174 
        net "VCC" in work.decoder(verilog)
5175 
        net "GND" in work.decoder(verilog)
5176 
        net "VCC" in work.decoder(verilog)
5177 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_2[1]</font>
5178 
25) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[1]" in work.decoder(verilog)
5179 
    input nets to instance:
5180 
        net "un1_fsm_dly352_1" in work.decoder(verilog)
5181 
        net "GND" in work.decoder(verilog)
5182 
        net "GND" in work.decoder(verilog)
5183 
        net "GND" in work.decoder(verilog)
5184 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
5185 
        net "GND" in work.decoder(verilog)
5186 
        net "VCC" in work.decoder(verilog)
5187 
        net "VCC" in work.decoder(verilog)
5188 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
5189 
        net "GND" in work.decoder(verilog)
5190 
        net "GND" in work.decoder(verilog)
5191 
        net "VCC" in work.decoder(verilog)
5192 
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
5193 
        net "cmp_ctl_1[0]" in work.decoder(verilog)
5194 
        net "cmp_ctl_1[1]" in work.decoder(verilog)
5195 
        net "cmp_ctl_1[2]" in work.decoder(verilog)
5196 
        net "fsm_dly352" in work.decoder(verilog)
5197 
        net "VCC" in work.decoder(verilog)
5198 
        net "GND" in work.decoder(verilog)
5199 
        net "GND" in work.decoder(verilog)
5200 
        net "fsm_dly353" in work.decoder(verilog)
5201 
        net "GND" in work.decoder(verilog)
5202 
        net "VCC" in work.decoder(verilog)
5203 
        net "GND" in work.decoder(verilog)
5204 
        net "fsm_dly354" in work.decoder(verilog)
5205 
        net "VCC" in work.decoder(verilog)
5206 
        net "VCC" in work.decoder(verilog)
5207 
        net "GND" in work.decoder(verilog)
5208 
        net "fsm_dly355" in work.decoder(verilog)
5209 
        net "VCC" in work.decoder(verilog)
5210 
        net "GND" in work.decoder(verilog)
5211 
        net "VCC" in work.decoder(verilog)
5212 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net cmp_ctl_2[2]</font>
5213 
26) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[2]" in work.decoder(verilog)
5214 
    input nets to instance:
5215 
        net "un1_fsm_dly352_1" in work.decoder(verilog)
5216 
        net "GND" in work.decoder(verilog)
5217 
        net "GND" in work.decoder(verilog)
5218 
        net "GND" in work.decoder(verilog)
5219 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
5220 
        net "GND" in work.decoder(verilog)
5221 
        net "VCC" in work.decoder(verilog)
5222 
        net "VCC" in work.decoder(verilog)
5223 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
5224 
        net "GND" in work.decoder(verilog)
5225 
        net "GND" in work.decoder(verilog)
5226 
        net "VCC" in work.decoder(verilog)
5227 
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
5228 
        net "cmp_ctl_1[0]" in work.decoder(verilog)
5229 
        net "cmp_ctl_1[1]" in work.decoder(verilog)
5230 
        net "cmp_ctl_1[2]" in work.decoder(verilog)
5231 
        net "fsm_dly352" in work.decoder(verilog)
5232 
        net "VCC" in work.decoder(verilog)
5233 
        net "GND" in work.decoder(verilog)
5234 
        net "GND" in work.decoder(verilog)
5235 
        net "fsm_dly353" in work.decoder(verilog)
5236 
        net "GND" in work.decoder(verilog)
5237 
        net "VCC" in work.decoder(verilog)
5238 
        net "GND" in work.decoder(verilog)
5239 
        net "fsm_dly354" in work.decoder(verilog)
5240 
        net "VCC" in work.decoder(verilog)
5241 
        net "VCC" in work.decoder(verilog)
5242 
        net "GND" in work.decoder(verilog)
5243 
        net "fsm_dly355" in work.decoder(verilog)
5244 
        net "VCC" in work.decoder(verilog)
5245 
        net "GND" in work.decoder(verilog)
5246 
        net "VCC" in work.decoder(verilog)
5247 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_2[0]</font>
5248 
27) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[0]" in work.decoder(verilog)
5249 
    input nets to instance:
5250 
        net "un1_fsm_dly365_2" in work.decoder(verilog)
5251 
        net "GND" in work.decoder(verilog)
5252 
        net "GND" in work.decoder(verilog)
5253 
        net "GND" in work.decoder(verilog)
5254 
        net "GND" in work.decoder(verilog)
5255 
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
5256 
        net "dmem_ctl_1[0]" in work.decoder(verilog)
5257 
        net "dmem_ctl_1[1]" in work.decoder(verilog)
5258 
        net "dmem_ctl_1[2]" in work.decoder(verilog)
5259 
        net "dmem_ctl_1[3]" in work.decoder(verilog)
5260 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
5261 
        net "VCC" in work.decoder(verilog)
5262 
        net "VCC" in work.decoder(verilog)
5263 
        net "GND" in work.decoder(verilog)
5264 
        net "GND" in work.decoder(verilog)
5265 
        net "fsm_dly365" in work.decoder(verilog)
5266 
        net "GND" in work.decoder(verilog)
5267 
        net "VCC" in work.decoder(verilog)
5268 
        net "GND" in work.decoder(verilog)
5269 
        net "GND" in work.decoder(verilog)
5270 
        net "fsm_dly366" in work.decoder(verilog)
5271 
        net "GND" in work.decoder(verilog)
5272 
        net "GND" in work.decoder(verilog)
5273 
        net "GND" in work.decoder(verilog)
5274 
        net "VCC" in work.decoder(verilog)
5275 
        net "fsm_dly368" in work.decoder(verilog)
5276 
        net "GND" in work.decoder(verilog)
5277 
        net "VCC" in work.decoder(verilog)
5278 
        net "VCC" in work.decoder(verilog)
5279 
        net "GND" in work.decoder(verilog)
5280 
        net "fsm_dly369" in work.decoder(verilog)
5281 
        net "GND" in work.decoder(verilog)
5282 
        net "GND" in work.decoder(verilog)
5283 
        net "VCC" in work.decoder(verilog)
5284 
        net "GND" in work.decoder(verilog)
5285 
        net "fsm_dly370" in work.decoder(verilog)
5286 
        net "GND" in work.decoder(verilog)
5287 
        net "VCC" in work.decoder(verilog)
5288 
        net "GND" in work.decoder(verilog)
5289 
        net "VCC" in work.decoder(verilog)
5290 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_2[1]</font>
5291 
28) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[1]" in work.decoder(verilog)
5292 
    input nets to instance:
5293 
        net "un1_fsm_dly365_2" in work.decoder(verilog)
5294 
        net "GND" in work.decoder(verilog)
5295 
        net "GND" in work.decoder(verilog)
5296 
        net "GND" in work.decoder(verilog)
5297 
        net "GND" in work.decoder(verilog)
5298 
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
5299 
        net "dmem_ctl_1[0]" in work.decoder(verilog)
5300 
        net "dmem_ctl_1[1]" in work.decoder(verilog)
5301 
        net "dmem_ctl_1[2]" in work.decoder(verilog)
5302 
        net "dmem_ctl_1[3]" in work.decoder(verilog)
5303 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
5304 
        net "VCC" in work.decoder(verilog)
5305 
        net "VCC" in work.decoder(verilog)
5306 
        net "GND" in work.decoder(verilog)
5307 
        net "GND" in work.decoder(verilog)
5308 
        net "fsm_dly365" in work.decoder(verilog)
5309 
        net "GND" in work.decoder(verilog)
5310 
        net "VCC" in work.decoder(verilog)
5311 
        net "GND" in work.decoder(verilog)
5312 
        net "GND" in work.decoder(verilog)
5313 
        net "fsm_dly366" in work.decoder(verilog)
5314 
        net "GND" in work.decoder(verilog)
5315 
        net "GND" in work.decoder(verilog)
5316 
        net "GND" in work.decoder(verilog)
5317 
        net "VCC" in work.decoder(verilog)
5318 
        net "fsm_dly368" in work.decoder(verilog)
5319 
        net "GND" in work.decoder(verilog)
5320 
        net "VCC" in work.decoder(verilog)
5321 
        net "VCC" in work.decoder(verilog)
5322 
        net "GND" in work.decoder(verilog)
5323 
        net "fsm_dly369" in work.decoder(verilog)
5324 
        net "GND" in work.decoder(verilog)
5325 
        net "GND" in work.decoder(verilog)
5326 
        net "VCC" in work.decoder(verilog)
5327 
        net "GND" in work.decoder(verilog)
5328 
        net "fsm_dly370" in work.decoder(verilog)
5329 
        net "GND" in work.decoder(verilog)
5330 
        net "VCC" in work.decoder(verilog)
5331 
        net "GND" in work.decoder(verilog)
5332 
        net "VCC" in work.decoder(verilog)
5333 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_2[2]</font>
5334 
29) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[2]" in work.decoder(verilog)
5335 
    input nets to instance:
5336 
        net "un1_fsm_dly365_2" in work.decoder(verilog)
5337 
        net "GND" in work.decoder(verilog)
5338 
        net "GND" in work.decoder(verilog)
5339 
        net "GND" in work.decoder(verilog)
5340 
        net "GND" in work.decoder(verilog)
5341 
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
5342 
        net "dmem_ctl_1[0]" in work.decoder(verilog)
5343 
        net "dmem_ctl_1[1]" in work.decoder(verilog)
5344 
        net "dmem_ctl_1[2]" in work.decoder(verilog)
5345 
        net "dmem_ctl_1[3]" in work.decoder(verilog)
5346 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
5347 
        net "VCC" in work.decoder(verilog)
5348 
        net "VCC" in work.decoder(verilog)
5349 
        net "GND" in work.decoder(verilog)
5350 
        net "GND" in work.decoder(verilog)
5351 
        net "fsm_dly365" in work.decoder(verilog)
5352 
        net "GND" in work.decoder(verilog)
5353 
        net "VCC" in work.decoder(verilog)
5354 
        net "GND" in work.decoder(verilog)
5355 
        net "GND" in work.decoder(verilog)
5356 
        net "fsm_dly366" in work.decoder(verilog)
5357 
        net "GND" in work.decoder(verilog)
5358 
        net "GND" in work.decoder(verilog)
5359 
        net "GND" in work.decoder(verilog)
5360 
        net "VCC" in work.decoder(verilog)
5361 
        net "fsm_dly368" in work.decoder(verilog)
5362 
        net "GND" in work.decoder(verilog)
5363 
        net "VCC" in work.decoder(verilog)
5364 
        net "VCC" in work.decoder(verilog)
5365 
        net "GND" in work.decoder(verilog)
5366 
        net "fsm_dly369" in work.decoder(verilog)
5367 
        net "GND" in work.decoder(verilog)
5368 
        net "GND" in work.decoder(verilog)
5369 
        net "VCC" in work.decoder(verilog)
5370 
        net "GND" in work.decoder(verilog)
5371 
        net "fsm_dly370" in work.decoder(verilog)
5372 
        net "GND" in work.decoder(verilog)
5373 
        net "VCC" in work.decoder(verilog)
5374 
        net "GND" in work.decoder(verilog)
5375 
        net "VCC" in work.decoder(verilog)
5376 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net dmem_ctl_2[3]</font>
5377 
30) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[3]" in work.decoder(verilog)
5378 
    input nets to instance:
5379 
        net "un1_fsm_dly365_2" in work.decoder(verilog)
5380 
        net "GND" in work.decoder(verilog)
5381 
        net "GND" in work.decoder(verilog)
5382 
        net "GND" in work.decoder(verilog)
5383 
        net "GND" in work.decoder(verilog)
5384 
        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
5385 
        net "dmem_ctl_1[0]" in work.decoder(verilog)
5386 
        net "dmem_ctl_1[1]" in work.decoder(verilog)
5387 
        net "dmem_ctl_1[2]" in work.decoder(verilog)
5388 
        net "dmem_ctl_1[3]" in work.decoder(verilog)
5389 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
5390 
        net "VCC" in work.decoder(verilog)
5391 
        net "VCC" in work.decoder(verilog)
5392 
        net "GND" in work.decoder(verilog)
5393 
        net "GND" in work.decoder(verilog)
5394 
        net "fsm_dly365" in work.decoder(verilog)
5395 
        net "GND" in work.decoder(verilog)
5396 
        net "VCC" in work.decoder(verilog)
5397 
        net "GND" in work.decoder(verilog)
5398 
        net "GND" in work.decoder(verilog)
5399 
        net "fsm_dly366" in work.decoder(verilog)
5400 
        net "GND" in work.decoder(verilog)
5401 
        net "GND" in work.decoder(verilog)
5402 
        net "GND" in work.decoder(verilog)
5403 
        net "VCC" in work.decoder(verilog)
5404 
        net "fsm_dly368" in work.decoder(verilog)
5405 
        net "GND" in work.decoder(verilog)
5406 
        net "VCC" in work.decoder(verilog)
5407 
        net "VCC" in work.decoder(verilog)
5408 
        net "GND" in work.decoder(verilog)
5409 
        net "fsm_dly369" in work.decoder(verilog)
5410 
        net "GND" in work.decoder(verilog)
5411 
        net "GND" in work.decoder(verilog)
5412 
        net "VCC" in work.decoder(verilog)
5413 
        net "GND" in work.decoder(verilog)
5414 
        net "fsm_dly370" in work.decoder(verilog)
5415 
        net "GND" in work.decoder(verilog)
5416 
        net "VCC" in work.decoder(verilog)
5417 
        net "GND" in work.decoder(verilog)
5418 
        net "VCC" in work.decoder(verilog)
5419 
End of loops
5420 
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:150:83:150:89:@W:BN132:@XP_MSG">ulit.v(150)</a><!@TM:1223605618> | Removing sequential instance mips_core.alu_pass0.r32_o[0],  because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[0]</font>
5421 
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:150:83:150:89:@W:BN132:@XP_MSG">ulit.v(150)</a><!@TM:1223605618> | Removing sequential instance mips_core.alu_pass0.r32_o[1],  because it is equivalent to instance mips_core.MEM_CTL.dmem_ctl_post.byte_addr_o[1]</font>
5422 
@N: : <a href="e:\mips789\mips789\rtl\verilog\exec_stage.v:572:4:572:10:@N::@XP_MSG">exec_stage.v(572)</a><!@TM:1223605618> | Found counter in view:work.muldiv_ff(verilog) inst count[5:0]
5423 
Warning: Found 30 combinational loops!
5424 
         Each loop is reported with an instance in the loop
5425 
         and nets connected to that instance.
5426 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5427 
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
5428 
    input nets to instance:
5429 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
5430 
        net "GND" in work.decoder(verilog)
5431 
        net "GND" in work.decoder(verilog)
5432 
        net "GND" in work.decoder(verilog)
5433 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
5434 
        net "GND" in work.decoder(verilog)
5435 
        net "GND" in work.decoder(verilog)
5436 
        net "GND" in work.decoder(verilog)
5437 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
5438 
        net "GND" in work.decoder(verilog)
5439 
        net "GND" in work.decoder(verilog)
5440 
        net "GND" in work.decoder(verilog)
5441 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
5442 
        net "GND" in work.decoder(verilog)
5443 
        net "GND" in work.decoder(verilog)
5444 
        net "GND" in work.decoder(verilog)
5445 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
5446 
        net "GND" in work.decoder(verilog)
5447 
        net "GND" in work.decoder(verilog)
5448 
        net "GND" in work.decoder(verilog)
5449 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
5450 
        net "GND" in work.decoder(verilog)
5451 
        net "GND" in work.decoder(verilog)
5452 
        net "GND" in work.decoder(verilog)
5453 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
5454 
        net "VCC" in work.decoder(verilog)
5455 
        net "GND" in work.decoder(verilog)
5456 
        net "GND" in work.decoder(verilog)
5457 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
5458 
        net "GND" in work.decoder(verilog)
5459 
        net "GND" in work.decoder(verilog)
5460 
        net "GND" in work.decoder(verilog)
5461 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
5462 
        net "GND" in work.decoder(verilog)
5463 
        net "GND" in work.decoder(verilog)
5464 
        net "GND" in work.decoder(verilog)
5465 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
5466 
        net "GND" in work.decoder(verilog)
5467 
        net "GND" in work.decoder(verilog)
5468 
        net "GND" in work.decoder(verilog)
5469 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
5470 
        net "GND" in work.decoder(verilog)
5471 
        net "GND" in work.decoder(verilog)
5472 
        net "GND" in work.decoder(verilog)
5473 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
5474 
        net "GND" in work.decoder(verilog)
5475 
        net "GND" in work.decoder(verilog)
5476 
        net "GND" in work.decoder(verilog)
5477 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
5478 
        net "GND" in work.decoder(verilog)
5479 
        net "GND" in work.decoder(verilog)
5480 
        net "GND" in work.decoder(verilog)
5481 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
5482 
        net "GND" in work.decoder(verilog)
5483 
        net "GND" in work.decoder(verilog)
5484 
        net "GND" in work.decoder(verilog)
5485 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
5486 
        net "GND" in work.decoder(verilog)
5487 
        net "VCC" in work.decoder(verilog)
5488 
        net "GND" in work.decoder(verilog)
5489 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
5490 
        net "GND" in work.decoder(verilog)
5491 
        net "VCC" in work.decoder(verilog)
5492 
        net "GND" in work.decoder(verilog)
5493 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
5494 
        net "GND" in work.decoder(verilog)
5495 
        net "VCC" in work.decoder(verilog)
5496 
        net "GND" in work.decoder(verilog)
5497 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
5498 
        net "GND" in work.decoder(verilog)
5499 
        net "VCC" in work.decoder(verilog)
5500 
        net "GND" in work.decoder(verilog)
5501 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
5502 
        net "GND" in work.decoder(verilog)
5503 
        net "GND" in work.decoder(verilog)
5504 
        net "GND" in work.decoder(verilog)
5505 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
5506 
        net "GND" in work.decoder(verilog)
5507 
        net "GND" in work.decoder(verilog)
5508 
        net "GND" in work.decoder(verilog)
5509 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
5510 
        net "GND" in work.decoder(verilog)
5511 
        net "GND" in work.decoder(verilog)
5512 
        net "GND" in work.decoder(verilog)
5513 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
5514 
        net "GND" in work.decoder(verilog)
5515 
        net "GND" in work.decoder(verilog)
5516 
        net "GND" in work.decoder(verilog)
5517 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
5518 
        net "GND" in work.decoder(verilog)
5519 
        net "GND" in work.decoder(verilog)
5520 
        net "GND" in work.decoder(verilog)
5521 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
5522 
        net "GND" in work.decoder(verilog)
5523 
        net "GND" in work.decoder(verilog)
5524 
        net "GND" in work.decoder(verilog)
5525 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
5526 
        net "GND" in work.decoder(verilog)
5527 
        net "GND" in work.decoder(verilog)
5528 
        net "GND" in work.decoder(verilog)
5529 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
5530 
        net "GND" in work.decoder(verilog)
5531 
        net "GND" in work.decoder(verilog)
5532 
        net "GND" in work.decoder(verilog)
5533 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
5534 
        net "GND" in work.decoder(verilog)
5535 
        net "GND" in work.decoder(verilog)
5536 
        net "GND" in work.decoder(verilog)
5537 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
5538 
        net "GND" in work.decoder(verilog)
5539 
        net "GND" in work.decoder(verilog)
5540 
        net "GND" in work.decoder(verilog)
5541 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
5542 
        net "GND" in work.decoder(verilog)
5543 
        net "GND" in work.decoder(verilog)
5544 
        net "GND" in work.decoder(verilog)
5545 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
5546 
        net "VCC" in work.decoder(verilog)
5547 
        net "GND" in work.decoder(verilog)
5548 
        net "GND" in work.decoder(verilog)
5549 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
5550 
        net "VCC" in work.decoder(verilog)
5551 
        net "GND" in work.decoder(verilog)
5552 
        net "GND" in work.decoder(verilog)
5553 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
5554 
        net "GND" in work.decoder(verilog)
5555 
        net "GND" in work.decoder(verilog)
5556 
        net "GND" in work.decoder(verilog)
5557 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
5558 
        net "fsm_dly_1[0]" in work.decoder(verilog)
5559 
        net "fsm_dly_1[1]" in work.decoder(verilog)
5560 
        net "fsm_dly_1[2]" in work.decoder(verilog)
5561 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
5562 
        net "fsm_dly_1[0]" in work.decoder(verilog)
5563 
        net "fsm_dly_1[1]" in work.decoder(verilog)
5564 
        net "fsm_dly_1[2]" in work.decoder(verilog)
5565 
        net "fsm_dly350" in work.decoder(verilog)
5566 
        net "GND" in work.decoder(verilog)
5567 
        net "VCC" in work.decoder(verilog)
5568 
        net "VCC" in work.decoder(verilog)
5569 
        net "fsm_dly351" in work.decoder(verilog)
5570 
        net "GND" in work.decoder(verilog)
5571 
        net "VCC" in work.decoder(verilog)
5572 
        net "VCC" in work.decoder(verilog)
5573 
        net "fsm_dly352" in work.decoder(verilog)
5574 
        net "VCC" in work.decoder(verilog)
5575 
        net "GND" in work.decoder(verilog)
5576 
        net "GND" in work.decoder(verilog)
5577 
        net "fsm_dly353" in work.decoder(verilog)
5578 
        net "VCC" in work.decoder(verilog)
5579 
        net "GND" in work.decoder(verilog)
5580 
        net "GND" in work.decoder(verilog)
5581 
        net "fsm_dly354" in work.decoder(verilog)
5582 
        net "VCC" in work.decoder(verilog)
5583 
        net "GND" in work.decoder(verilog)
5584 
        net "GND" in work.decoder(verilog)
5585 
        net "fsm_dly355" in work.decoder(verilog)
5586 
        net "VCC" in work.decoder(verilog)
5587 
        net "GND" in work.decoder(verilog)
5588 
        net "GND" in work.decoder(verilog)
5589 
        net "fsm_dly356" in work.decoder(verilog)
5590 
        net "GND" in work.decoder(verilog)
5591 
        net "GND" in work.decoder(verilog)
5592 
        net "GND" in work.decoder(verilog)
5593 
        net "fsm_dly357" in work.decoder(verilog)
5594 
        net "GND" in work.decoder(verilog)
5595 
        net "GND" in work.decoder(verilog)
5596 
        net "GND" in work.decoder(verilog)
5597 
        net "fsm_dly358" in work.decoder(verilog)
5598 
        net "GND" in work.decoder(verilog)
5599 
        net "GND" in work.decoder(verilog)
5600 
        net "GND" in work.decoder(verilog)
5601 
        net "fsm_dly359" in work.decoder(verilog)
5602 
        net "GND" in work.decoder(verilog)
5603 
        net "GND" in work.decoder(verilog)
5604 
        net "GND" in work.decoder(verilog)
5605 
        net "fsm_dly360" in work.decoder(verilog)
5606 
        net "GND" in work.decoder(verilog)
5607 
        net "GND" in work.decoder(verilog)
5608 
        net "GND" in work.decoder(verilog)
5609 
        net "fsm_dly361" in work.decoder(verilog)
5610 
        net "GND" in work.decoder(verilog)
5611 
        net "GND" in work.decoder(verilog)
5612 
        net "GND" in work.decoder(verilog)
5613 
        net "fsm_dly362" in work.decoder(verilog)
5614 
        net "GND" in work.decoder(verilog)
5615 
        net "GND" in work.decoder(verilog)
5616 
        net "GND" in work.decoder(verilog)
5617 
        net "fsm_dly363" in work.decoder(verilog)
5618 
        net "GND" in work.decoder(verilog)
5619 
        net "GND" in work.decoder(verilog)
5620 
        net "GND" in work.decoder(verilog)
5621 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
5622 
        net "GND" in work.decoder(verilog)
5623 
        net "GND" in work.decoder(verilog)
5624 
        net "GND" in work.decoder(verilog)
5625 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
5626 
        net "GND" in work.decoder(verilog)
5627 
        net "GND" in work.decoder(verilog)
5628 
        net "VCC" in work.decoder(verilog)
5629 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
5630 
        net "fsm_dly_1[0]" in work.decoder(verilog)
5631 
        net "fsm_dly_1[1]" in work.decoder(verilog)
5632 
        net "fsm_dly_1[2]" in work.decoder(verilog)
5633 
        net "fsm_dly365" in work.decoder(verilog)
5634 
        net "GND" in work.decoder(verilog)
5635 
        net "GND" in work.decoder(verilog)
5636 
        net "GND" in work.decoder(verilog)
5637 
        net "fsm_dly366" in work.decoder(verilog)
5638 
        net "GND" in work.decoder(verilog)
5639 
        net "GND" in work.decoder(verilog)
5640 
        net "GND" in work.decoder(verilog)
5641 
        net "fsm_dly367" in work.decoder(verilog)
5642 
        net "GND" in work.decoder(verilog)
5643 
        net "GND" in work.decoder(verilog)
5644 
        net "GND" in work.decoder(verilog)
5645 
        net "fsm_dly368" in work.decoder(verilog)
5646 
        net "GND" in work.decoder(verilog)
5647 
        net "GND" in work.decoder(verilog)
5648 
        net "GND" in work.decoder(verilog)
5649 
        net "fsm_dly369" in work.decoder(verilog)
5650 
        net "GND" in work.decoder(verilog)
5651 
        net "GND" in work.decoder(verilog)
5652 
        net "GND" in work.decoder(verilog)
5653 
        net "fsm_dly370" in work.decoder(verilog)
5654 
        net "GND" in work.decoder(verilog)
5655 
        net "GND" in work.decoder(verilog)
5656 
        net "GND" in work.decoder(verilog)
5657 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5658 
2) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[1]" in work.decoder(verilog)
5659 
    input nets to instance:
5660 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
5661 
        net "GND" in work.decoder(verilog)
5662 
        net "GND" in work.decoder(verilog)
5663 
        net "GND" in work.decoder(verilog)
5664 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
5665 
        net "GND" in work.decoder(verilog)
5666 
        net "GND" in work.decoder(verilog)
5667 
        net "GND" in work.decoder(verilog)
5668 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
5669 
        net "GND" in work.decoder(verilog)
5670 
        net "GND" in work.decoder(verilog)
5671 
        net "GND" in work.decoder(verilog)
5672 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
5673 
        net "GND" in work.decoder(verilog)
5674 
        net "GND" in work.decoder(verilog)
5675 
        net "GND" in work.decoder(verilog)
5676 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
5677 
        net "GND" in work.decoder(verilog)
5678 
        net "GND" in work.decoder(verilog)
5679 
        net "GND" in work.decoder(verilog)
5680 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
5681 
        net "GND" in work.decoder(verilog)
5682 
        net "GND" in work.decoder(verilog)
5683 
        net "GND" in work.decoder(verilog)
5684 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
5685 
        net "VCC" in work.decoder(verilog)
5686 
        net "GND" in work.decoder(verilog)
5687 
        net "GND" in work.decoder(verilog)
5688 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
5689 
        net "GND" in work.decoder(verilog)
5690 
        net "GND" in work.decoder(verilog)
5691 
        net "GND" in work.decoder(verilog)
5692 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
5693 
        net "GND" in work.decoder(verilog)
5694 
        net "GND" in work.decoder(verilog)
5695 
        net "GND" in work.decoder(verilog)
5696 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
5697 
        net "GND" in work.decoder(verilog)
5698 
        net "GND" in work.decoder(verilog)
5699 
        net "GND" in work.decoder(verilog)
5700 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
5701 
        net "GND" in work.decoder(verilog)
5702 
        net "GND" in work.decoder(verilog)
5703 
        net "GND" in work.decoder(verilog)
5704 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
5705 
        net "GND" in work.decoder(verilog)
5706 
        net "GND" in work.decoder(verilog)
5707 
        net "GND" in work.decoder(verilog)
5708 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
5709 
        net "GND" in work.decoder(verilog)
5710 
        net "GND" in work.decoder(verilog)
5711 
        net "GND" in work.decoder(verilog)
5712 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
5713 
        net "GND" in work.decoder(verilog)
5714 
        net "GND" in work.decoder(verilog)
5715 
        net "GND" in work.decoder(verilog)
5716 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
5717 
        net "GND" in work.decoder(verilog)
5718 
        net "VCC" in work.decoder(verilog)
5719 
        net "GND" in work.decoder(verilog)
5720 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
5721 
        net "GND" in work.decoder(verilog)
5722 
        net "VCC" in work.decoder(verilog)
5723 
        net "GND" in work.decoder(verilog)
5724 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
5725 
        net "GND" in work.decoder(verilog)
5726 
        net "VCC" in work.decoder(verilog)
5727 
        net "GND" in work.decoder(verilog)
5728 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
5729 
        net "GND" in work.decoder(verilog)
5730 
        net "VCC" in work.decoder(verilog)
5731 
        net "GND" in work.decoder(verilog)
5732 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
5733 
        net "GND" in work.decoder(verilog)
5734 
        net "GND" in work.decoder(verilog)
5735 
        net "GND" in work.decoder(verilog)
5736 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
5737 
        net "GND" in work.decoder(verilog)
5738 
        net "GND" in work.decoder(verilog)
5739 
        net "GND" in work.decoder(verilog)
5740 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
5741 
        net "GND" in work.decoder(verilog)
5742 
        net "GND" in work.decoder(verilog)
5743 
        net "GND" in work.decoder(verilog)
5744 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
5745 
        net "GND" in work.decoder(verilog)
5746 
        net "GND" in work.decoder(verilog)
5747 
        net "GND" in work.decoder(verilog)
5748 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
5749 
        net "GND" in work.decoder(verilog)
5750 
        net "GND" in work.decoder(verilog)
5751 
        net "GND" in work.decoder(verilog)
5752 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
5753 
        net "GND" in work.decoder(verilog)
5754 
        net "GND" in work.decoder(verilog)
5755 
        net "GND" in work.decoder(verilog)
5756 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
5757 
        net "GND" in work.decoder(verilog)
5758 
        net "GND" in work.decoder(verilog)
5759 
        net "GND" in work.decoder(verilog)
5760 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
5761 
        net "GND" in work.decoder(verilog)
5762 
        net "GND" in work.decoder(verilog)
5763 
        net "GND" in work.decoder(verilog)
5764 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
5765 
        net "GND" in work.decoder(verilog)
5766 
        net "GND" in work.decoder(verilog)
5767 
        net "GND" in work.decoder(verilog)
5768 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
5769 
        net "GND" in work.decoder(verilog)
5770 
        net "GND" in work.decoder(verilog)
5771 
        net "GND" in work.decoder(verilog)
5772 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
5773 
        net "GND" in work.decoder(verilog)
5774 
        net "GND" in work.decoder(verilog)
5775 
        net "GND" in work.decoder(verilog)
5776 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
5777 
        net "VCC" in work.decoder(verilog)
5778 
        net "GND" in work.decoder(verilog)
5779 
        net "GND" in work.decoder(verilog)
5780 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
5781 
        net "VCC" in work.decoder(verilog)
5782 
        net "GND" in work.decoder(verilog)
5783 
        net "GND" in work.decoder(verilog)
5784 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
5785 
        net "GND" in work.decoder(verilog)
5786 
        net "GND" in work.decoder(verilog)
5787 
        net "GND" in work.decoder(verilog)
5788 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
5789 
        net "fsm_dly_1[0]" in work.decoder(verilog)
5790 
        net "fsm_dly_1[1]" in work.decoder(verilog)
5791 
        net "fsm_dly_1[2]" in work.decoder(verilog)
5792 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
5793 
        net "fsm_dly_1[0]" in work.decoder(verilog)
5794 
        net "fsm_dly_1[1]" in work.decoder(verilog)
5795 
        net "fsm_dly_1[2]" in work.decoder(verilog)
5796 
        net "fsm_dly350" in work.decoder(verilog)
5797 
        net "GND" in work.decoder(verilog)
5798 
        net "VCC" in work.decoder(verilog)
5799 
        net "VCC" in work.decoder(verilog)
5800 
        net "fsm_dly351" in work.decoder(verilog)
5801 
        net "GND" in work.decoder(verilog)
5802 
        net "VCC" in work.decoder(verilog)
5803 
        net "VCC" in work.decoder(verilog)
5804 
        net "fsm_dly352" in work.decoder(verilog)
5805 
        net "VCC" in work.decoder(verilog)
5806 
        net "GND" in work.decoder(verilog)
5807 
        net "GND" in work.decoder(verilog)
5808 
        net "fsm_dly353" in work.decoder(verilog)
5809 
        net "VCC" in work.decoder(verilog)
5810 
        net "GND" in work.decoder(verilog)
5811 
        net "GND" in work.decoder(verilog)
5812 
        net "fsm_dly354" in work.decoder(verilog)
5813 
        net "VCC" in work.decoder(verilog)
5814 
        net "GND" in work.decoder(verilog)
5815 
        net "GND" in work.decoder(verilog)
5816 
        net "fsm_dly355" in work.decoder(verilog)
5817 
        net "VCC" in work.decoder(verilog)
5818 
        net "GND" in work.decoder(verilog)
5819 
        net "GND" in work.decoder(verilog)
5820 
        net "fsm_dly356" in work.decoder(verilog)
5821 
        net "GND" in work.decoder(verilog)
5822 
        net "GND" in work.decoder(verilog)
5823 
        net "GND" in work.decoder(verilog)
5824 
        net "fsm_dly357" in work.decoder(verilog)
5825 
        net "GND" in work.decoder(verilog)
5826 
        net "GND" in work.decoder(verilog)
5827 
        net "GND" in work.decoder(verilog)
5828 
        net "fsm_dly358" in work.decoder(verilog)
5829 
        net "GND" in work.decoder(verilog)
5830 
        net "GND" in work.decoder(verilog)
5831 
        net "GND" in work.decoder(verilog)
5832 
        net "fsm_dly359" in work.decoder(verilog)
5833 
        net "GND" in work.decoder(verilog)
5834 
        net "GND" in work.decoder(verilog)
5835 
        net "GND" in work.decoder(verilog)
5836 
        net "fsm_dly360" in work.decoder(verilog)
5837 
        net "GND" in work.decoder(verilog)
5838 
        net "GND" in work.decoder(verilog)
5839 
        net "GND" in work.decoder(verilog)
5840 
        net "fsm_dly361" in work.decoder(verilog)
5841 
        net "GND" in work.decoder(verilog)
5842 
        net "GND" in work.decoder(verilog)
5843 
        net "GND" in work.decoder(verilog)
5844 
        net "fsm_dly362" in work.decoder(verilog)
5845 
        net "GND" in work.decoder(verilog)
5846 
        net "GND" in work.decoder(verilog)
5847 
        net "GND" in work.decoder(verilog)
5848 
        net "fsm_dly363" in work.decoder(verilog)
5849 
        net "GND" in work.decoder(verilog)
5850 
        net "GND" in work.decoder(verilog)
5851 
        net "GND" in work.decoder(verilog)
5852 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
5853 
        net "GND" in work.decoder(verilog)
5854 
        net "GND" in work.decoder(verilog)
5855 
        net "GND" in work.decoder(verilog)
5856 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
5857 
        net "GND" in work.decoder(verilog)
5858 
        net "GND" in work.decoder(verilog)
5859 
        net "VCC" in work.decoder(verilog)
5860 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
5861 
        net "fsm_dly_1[0]" in work.decoder(verilog)
5862 
        net "fsm_dly_1[1]" in work.decoder(verilog)
5863 
        net "fsm_dly_1[2]" in work.decoder(verilog)
5864 
        net "fsm_dly365" in work.decoder(verilog)
5865 
        net "GND" in work.decoder(verilog)
5866 
        net "GND" in work.decoder(verilog)
5867 
        net "GND" in work.decoder(verilog)
5868 
        net "fsm_dly366" in work.decoder(verilog)
5869 
        net "GND" in work.decoder(verilog)
5870 
        net "GND" in work.decoder(verilog)
5871 
        net "GND" in work.decoder(verilog)
5872 
        net "fsm_dly367" in work.decoder(verilog)
5873 
        net "GND" in work.decoder(verilog)
5874 
        net "GND" in work.decoder(verilog)
5875 
        net "GND" in work.decoder(verilog)
5876 
        net "fsm_dly368" in work.decoder(verilog)
5877 
        net "GND" in work.decoder(verilog)
5878 
        net "GND" in work.decoder(verilog)
5879 
        net "GND" in work.decoder(verilog)
5880 
        net "fsm_dly369" in work.decoder(verilog)
5881 
        net "GND" in work.decoder(verilog)
5882 
        net "GND" in work.decoder(verilog)
5883 
        net "GND" in work.decoder(verilog)
5884 
        net "fsm_dly370" in work.decoder(verilog)
5885 
        net "GND" in work.decoder(verilog)
5886 
        net "GND" in work.decoder(verilog)
5887 
        net "GND" in work.decoder(verilog)
5888 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
5889 
3) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[2]" in work.decoder(verilog)
5890 
    input nets to instance:
5891 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
5892 
        net "GND" in work.decoder(verilog)
5893 
        net "GND" in work.decoder(verilog)
5894 
        net "GND" in work.decoder(verilog)
5895 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
5896 
        net "GND" in work.decoder(verilog)
5897 
        net "GND" in work.decoder(verilog)
5898 
        net "GND" in work.decoder(verilog)
5899 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
5900 
        net "GND" in work.decoder(verilog)
5901 
        net "GND" in work.decoder(verilog)
5902 
        net "GND" in work.decoder(verilog)
5903 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
5904 
        net "GND" in work.decoder(verilog)
5905 
        net "GND" in work.decoder(verilog)
5906 
        net "GND" in work.decoder(verilog)
5907 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
5908 
        net "GND" in work.decoder(verilog)
5909 
        net "GND" in work.decoder(verilog)
5910 
        net "GND" in work.decoder(verilog)
5911 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
5912 
        net "GND" in work.decoder(verilog)
5913 
        net "GND" in work.decoder(verilog)
5914 
        net "GND" in work.decoder(verilog)
5915 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
5916 
        net "VCC" in work.decoder(verilog)
5917 
        net "GND" in work.decoder(verilog)
5918 
        net "GND" in work.decoder(verilog)
5919 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
5920 
        net "GND" in work.decoder(verilog)
5921 
        net "GND" in work.decoder(verilog)
5922 
        net "GND" in work.decoder(verilog)
5923 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
5924 
        net "GND" in work.decoder(verilog)
5925 
        net "GND" in work.decoder(verilog)
5926 
        net "GND" in work.decoder(verilog)
5927 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
5928 
        net "GND" in work.decoder(verilog)
5929 
        net "GND" in work.decoder(verilog)
5930 
        net "GND" in work.decoder(verilog)
5931 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
5932 
        net "GND" in work.decoder(verilog)
5933 
        net "GND" in work.decoder(verilog)
5934 
        net "GND" in work.decoder(verilog)
5935 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
5936 
        net "GND" in work.decoder(verilog)
5937 
        net "GND" in work.decoder(verilog)
5938 
        net "GND" in work.decoder(verilog)
5939 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
5940 
        net "GND" in work.decoder(verilog)
5941 
        net "GND" in work.decoder(verilog)
5942 
        net "GND" in work.decoder(verilog)
5943 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
5944 
        net "GND" in work.decoder(verilog)
5945 
        net "GND" in work.decoder(verilog)
5946 
        net "GND" in work.decoder(verilog)
5947 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
5948 
        net "GND" in work.decoder(verilog)
5949 
        net "VCC" in work.decoder(verilog)
5950 
        net "GND" in work.decoder(verilog)
5951 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
5952 
        net "GND" in work.decoder(verilog)
5953 
        net "VCC" in work.decoder(verilog)
5954 
        net "GND" in work.decoder(verilog)
5955 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
5956 
        net "GND" in work.decoder(verilog)
5957 
        net "VCC" in work.decoder(verilog)
5958 
        net "GND" in work.decoder(verilog)
5959 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
5960 
        net "GND" in work.decoder(verilog)
5961 
        net "VCC" in work.decoder(verilog)
5962 
        net "GND" in work.decoder(verilog)
5963 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
5964 
        net "GND" in work.decoder(verilog)
5965 
        net "GND" in work.decoder(verilog)
5966 
        net "GND" in work.decoder(verilog)
5967 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
5968 
        net "GND" in work.decoder(verilog)
5969 
        net "GND" in work.decoder(verilog)
5970 
        net "GND" in work.decoder(verilog)
5971 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
5972 
        net "GND" in work.decoder(verilog)
5973 
        net "GND" in work.decoder(verilog)
5974 
        net "GND" in work.decoder(verilog)
5975 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
5976 
        net "GND" in work.decoder(verilog)
5977 
        net "GND" in work.decoder(verilog)
5978 
        net "GND" in work.decoder(verilog)
5979 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
5980 
        net "GND" in work.decoder(verilog)
5981 
        net "GND" in work.decoder(verilog)
5982 
        net "GND" in work.decoder(verilog)
5983 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
5984 
        net "GND" in work.decoder(verilog)
5985 
        net "GND" in work.decoder(verilog)
5986 
        net "GND" in work.decoder(verilog)
5987 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
5988 
        net "GND" in work.decoder(verilog)
5989 
        net "GND" in work.decoder(verilog)
5990 
        net "GND" in work.decoder(verilog)
5991 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
5992 
        net "GND" in work.decoder(verilog)
5993 
        net "GND" in work.decoder(verilog)
5994 
        net "GND" in work.decoder(verilog)
5995 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
5996 
        net "GND" in work.decoder(verilog)
5997 
        net "GND" in work.decoder(verilog)
5998 
        net "GND" in work.decoder(verilog)
5999 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
6000 
        net "GND" in work.decoder(verilog)
6001 
        net "GND" in work.decoder(verilog)
6002 
        net "GND" in work.decoder(verilog)
6003 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
6004 
        net "GND" in work.decoder(verilog)
6005 
        net "GND" in work.decoder(verilog)
6006 
        net "GND" in work.decoder(verilog)
6007 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
6008 
        net "VCC" in work.decoder(verilog)
6009 
        net "GND" in work.decoder(verilog)
6010 
        net "GND" in work.decoder(verilog)
6011 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
6012 
        net "VCC" in work.decoder(verilog)
6013 
        net "GND" in work.decoder(verilog)
6014 
        net "GND" in work.decoder(verilog)
6015 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
6016 
        net "GND" in work.decoder(verilog)
6017 
        net "GND" in work.decoder(verilog)
6018 
        net "GND" in work.decoder(verilog)
6019 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
6020 
        net "fsm_dly_1[0]" in work.decoder(verilog)
6021 
        net "fsm_dly_1[1]" in work.decoder(verilog)
6022 
        net "fsm_dly_1[2]" in work.decoder(verilog)
6023 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
6024 
        net "fsm_dly_1[0]" in work.decoder(verilog)
6025 
        net "fsm_dly_1[1]" in work.decoder(verilog)
6026 
        net "fsm_dly_1[2]" in work.decoder(verilog)
6027 
        net "fsm_dly350" in work.decoder(verilog)
6028 
        net "GND" in work.decoder(verilog)
6029 
        net "VCC" in work.decoder(verilog)
6030 
        net "VCC" in work.decoder(verilog)
6031 
        net "fsm_dly351" in work.decoder(verilog)
6032 
        net "GND" in work.decoder(verilog)
6033 
        net "VCC" in work.decoder(verilog)
6034 
        net "VCC" in work.decoder(verilog)
6035 
        net "fsm_dly352" in work.decoder(verilog)
6036 
        net "VCC" in work.decoder(verilog)
6037 
        net "GND" in work.decoder(verilog)
6038 
        net "GND" in work.decoder(verilog)
6039 
        net "fsm_dly353" in work.decoder(verilog)
6040 
        net "VCC" in work.decoder(verilog)
6041 
        net "GND" in work.decoder(verilog)
6042 
        net "GND" in work.decoder(verilog)
6043 
        net "fsm_dly354" in work.decoder(verilog)
6044 
        net "VCC" in work.decoder(verilog)
6045 
        net "GND" in work.decoder(verilog)
6046 
        net "GND" in work.decoder(verilog)
6047 
        net "fsm_dly355" in work.decoder(verilog)
6048 
        net "VCC" in work.decoder(verilog)
6049 
        net "GND" in work.decoder(verilog)
6050 
        net "GND" in work.decoder(verilog)
6051 
        net "fsm_dly356" in work.decoder(verilog)
6052 
        net "GND" in work.decoder(verilog)
6053 
        net "GND" in work.decoder(verilog)
6054 
        net "GND" in work.decoder(verilog)
6055 
        net "fsm_dly357" in work.decoder(verilog)
6056 
        net "GND" in work.decoder(verilog)
6057 
        net "GND" in work.decoder(verilog)
6058 
        net "GND" in work.decoder(verilog)
6059 
        net "fsm_dly358" in work.decoder(verilog)
6060 
        net "GND" in work.decoder(verilog)
6061 
        net "GND" in work.decoder(verilog)
6062 
        net "GND" in work.decoder(verilog)
6063 
        net "fsm_dly359" in work.decoder(verilog)
6064 
        net "GND" in work.decoder(verilog)
6065 
        net "GND" in work.decoder(verilog)
6066 
        net "GND" in work.decoder(verilog)
6067 
        net "fsm_dly360" in work.decoder(verilog)
6068 
        net "GND" in work.decoder(verilog)
6069 
        net "GND" in work.decoder(verilog)
6070 
        net "GND" in work.decoder(verilog)
6071 
        net "fsm_dly361" in work.decoder(verilog)
6072 
        net "GND" in work.decoder(verilog)
6073 
        net "GND" in work.decoder(verilog)
6074 
        net "GND" in work.decoder(verilog)
6075 
        net "fsm_dly362" in work.decoder(verilog)
6076 
        net "GND" in work.decoder(verilog)
6077 
        net "GND" in work.decoder(verilog)
6078 
        net "GND" in work.decoder(verilog)
6079 
        net "fsm_dly363" in work.decoder(verilog)
6080 
        net "GND" in work.decoder(verilog)
6081 
        net "GND" in work.decoder(verilog)
6082 
        net "GND" in work.decoder(verilog)
6083 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
6084 
        net "GND" in work.decoder(verilog)
6085 
        net "GND" in work.decoder(verilog)
6086 
        net "GND" in work.decoder(verilog)
6087 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
6088 
        net "GND" in work.decoder(verilog)
6089 
        net "GND" in work.decoder(verilog)
6090 
        net "VCC" in work.decoder(verilog)
6091 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
6092 
        net "fsm_dly_1[0]" in work.decoder(verilog)
6093 
        net "fsm_dly_1[1]" in work.decoder(verilog)
6094 
        net "fsm_dly_1[2]" in work.decoder(verilog)
6095 
        net "fsm_dly365" in work.decoder(verilog)
6096 
        net "GND" in work.decoder(verilog)
6097 
        net "GND" in work.decoder(verilog)
6098 
        net "GND" in work.decoder(verilog)
6099 
        net "fsm_dly366" in work.decoder(verilog)
6100 
        net "GND" in work.decoder(verilog)
6101 
        net "GND" in work.decoder(verilog)
6102 
        net "GND" in work.decoder(verilog)
6103 
        net "fsm_dly367" in work.decoder(verilog)
6104 
        net "GND" in work.decoder(verilog)
6105 
        net "GND" in work.decoder(verilog)
6106 
        net "GND" in work.decoder(verilog)
6107 
        net "fsm_dly368" in work.decoder(verilog)
6108 
        net "GND" in work.decoder(verilog)
6109 
        net "GND" in work.decoder(verilog)
6110 
        net "GND" in work.decoder(verilog)
6111 
        net "fsm_dly369" in work.decoder(verilog)
6112 
        net "GND" in work.decoder(verilog)
6113 
        net "GND" in work.decoder(verilog)
6114 
        net "GND" in work.decoder(verilog)
6115 
        net "fsm_dly370" in work.decoder(verilog)
6116 
        net "GND" in work.decoder(verilog)
6117 
        net "GND" in work.decoder(verilog)
6118 
        net "GND" in work.decoder(verilog)
6119 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6120 
4) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
6121 
    input nets to instance:
6122 
        net "ext_ctl_2[0]" in work.decoder(verilog)
6123 
        net "un1_fsm_dly370" in work.decoder(verilog)
6124 
        net "un1_ins_i_23" in work.decoder(verilog)
6125 
        net "un1_ins_i_20" in work.decoder(verilog)
6126 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6127 
5) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
6128 
    input nets to instance:
6129 
        net "ext_ctl_2[1]" in work.decoder(verilog)
6130 
        net "un1_fsm_dly370" in work.decoder(verilog)
6131 
        net "un1_ins_i_21" in work.decoder(verilog)
6132 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6133 
6) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
6134 
    input nets to instance:
6135 
        net "ext_ctl_2[2]" in work.decoder(verilog)
6136 
        net "un1_fsm_dly370" in work.decoder(verilog)
6137 
        net "un1_ins_i_21" in work.decoder(verilog)
6138 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6139 
7) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
6140 
    input nets to instance:
6141 
        net "rd_sel_2[0]" in work.decoder(verilog)
6142 
        net "un1_fsm_dly370" in work.decoder(verilog)
6143 
        net "un1_ins_i_21" in work.decoder(verilog)
6144 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6145 
8) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
6146 
    input nets to instance:
6147 
        net "rd_sel_2[1]" in work.decoder(verilog)
6148 
        net "un1_fsm_dly370" in work.decoder(verilog)
6149 
        net "un1_ins_i_22" in work.decoder(verilog)
6150 
        net "fsm_dly373" in work.decoder(verilog)
6151 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6152 
9) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
6153 
    input nets to instance:
6154 
        net "cmp_ctl_2[0]" in work.decoder(verilog)
6155 
        net "un1_fsm_dly370" in work.decoder(verilog)
6156 
        net "un1_ins_i_21" in work.decoder(verilog)
6157 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6158 
10) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
6159 
    input nets to instance:
6160 
        net "cmp_ctl_2[1]" in work.decoder(verilog)
6161 
        net "un1_fsm_dly370" in work.decoder(verilog)
6162 
        net "un1_ins_i_21" in work.decoder(verilog)
6163 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6164 
11) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
6165 
    input nets to instance:
6166 
        net "cmp_ctl_2[2]" in work.decoder(verilog)
6167 
        net "un1_fsm_dly370" in work.decoder(verilog)
6168 
        net "un1_ins_i_21" in work.decoder(verilog)
6169 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6170 
12) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
6171 
    input nets to instance:
6172 
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
6173 
        net "un1_fsm_dly370" in work.decoder(verilog)
6174 
        net "un1_ins_i_23" in work.decoder(verilog)
6175 
        net "un1_ins_i_20" in work.decoder(verilog)
6176 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6177 
13) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
6178 
    input nets to instance:
6179 
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
6180 
        net "un1_fsm_dly370" in work.decoder(verilog)
6181 
        net "un1_ins_i_21" in work.decoder(verilog)
6182 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6183 
14) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
6184 
    input nets to instance:
6185 
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
6186 
        net "un1_fsm_dly370" in work.decoder(verilog)
6187 
        net "un1_ins_i_23" in work.decoder(verilog)
6188 
        net "un1_ins_i_20" in work.decoder(verilog)
6189 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6190 
15) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
6191 
    input nets to instance:
6192 
        net "muxa_ctl_2[0]" in work.decoder(verilog)
6193 
        net "un1_fsm_dly370" in work.decoder(verilog)
6194 
        net "un1_ins_i_21" in work.decoder(verilog)
6195 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6196 
16) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
6197 
    input nets to instance:
6198 
        net "muxa_ctl_2[1]" in work.decoder(verilog)
6199 
        net "un1_fsm_dly370" in work.decoder(verilog)
6200 
        net "un1_ins_i_23" in work.decoder(verilog)
6201 
        net "un1_ins_i_20" in work.decoder(verilog)
6202 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6203 
17) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
6204 
    input nets to instance:
6205 
        net "muxb_ctl_2[0]" in work.decoder(verilog)
6206 
        net "un1_fsm_dly370" in work.decoder(verilog)
6207 
        net "un1_ins_i_21" in work.decoder(verilog)
6208 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6209 
18) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
6210 
    input nets to instance:
6211 
        net "muxb_ctl_2[1]" in work.decoder(verilog)
6212 
        net "un1_fsm_dly370" in work.decoder(verilog)
6213 
        net "un1_ins_i_23" in work.decoder(verilog)
6214 
        net "un1_ins_i_20" in work.decoder(verilog)
6215 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6216 
19) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
6217 
    input nets to instance:
6218 
        net "alu_func_2[0]" in work.decoder(verilog)
6219 
        net "un1_fsm_dly370" in work.decoder(verilog)
6220 
        net "un1_ins_i_21" in work.decoder(verilog)
6221 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6222 
20) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
6223 
    input nets to instance:
6224 
        net "alu_func_2[1]" in work.decoder(verilog)
6225 
        net "un1_fsm_dly370" in work.decoder(verilog)
6226 
        net "un1_ins_i_21" in work.decoder(verilog)
6227 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6228 
21) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
6229 
    input nets to instance:
6230 
        net "alu_func_2[2]" in work.decoder(verilog)
6231 
        net "un1_fsm_dly370" in work.decoder(verilog)
6232 
        net "un1_ins_i_23" in work.decoder(verilog)
6233 
        net "un1_ins_i_20" in work.decoder(verilog)
6234 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6235 
22) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
6236 
    input nets to instance:
6237 
        net "alu_func_2[3]" in work.decoder(verilog)
6238 
        net "un1_fsm_dly370" in work.decoder(verilog)
6239 
        net "un1_ins_i_23" in work.decoder(verilog)
6240 
        net "un1_ins_i_20" in work.decoder(verilog)
6241 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6242 
23) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
6243 
    input nets to instance:
6244 
        net "alu_func_2[4]" in work.decoder(verilog)
6245 
        net "un1_fsm_dly370" in work.decoder(verilog)
6246 
        net "un1_ins_i_21" in work.decoder(verilog)
6247 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6248 
24) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
6249 
    input nets to instance:
6250 
        net "dmem_ctl_2[0]" in work.decoder(verilog)
6251 
        net "un1_fsm_dly370" in work.decoder(verilog)
6252 
        net "un1_ins_i_23" in work.decoder(verilog)
6253 
        net "un1_ins_i_20" in work.decoder(verilog)
6254 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6255 
25) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
6256 
    input nets to instance:
6257 
        net "dmem_ctl_2[1]" in work.decoder(verilog)
6258 
        net "un1_fsm_dly370" in work.decoder(verilog)
6259 
        net "un1_ins_i_22" in work.decoder(verilog)
6260 
        net "fsm_dly373" in work.decoder(verilog)
6261 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6262 
26) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
6263 
    input nets to instance:
6264 
        net "dmem_ctl_2[2]" in work.decoder(verilog)
6265 
        net "un1_fsm_dly370" in work.decoder(verilog)
6266 
        net "un1_ins_i_24" in work.decoder(verilog)
6267 
        net "un1_ins_i_15" in work.decoder(verilog)
6268 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6269 
27) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
6270 
    input nets to instance:
6271 
        net "dmem_ctl_2[3]" in work.decoder(verilog)
6272 
        net "un1_fsm_dly370" in work.decoder(verilog)
6273 
        net "un1_ins_i_21" in work.decoder(verilog)
6274 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6275 
28) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
6276 
    input nets to instance:
6277 
        net "alu_we_1[0]" in work.decoder(verilog)
6278 
        net "un1_fsm_dly370" in work.decoder(verilog)
6279 
        net "un1_ins_i_21" in work.decoder(verilog)
6280 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6281 
29) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
6282 
    input nets to instance:
6283 
        net "wb_mux_1[0]" in work.decoder(verilog)
6284 
        net "un1_fsm_dly370" in work.decoder(verilog)
6285 
        net "un1_ins_i_21" in work.decoder(verilog)
6286 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6287 
30) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
6288 
    input nets to instance:
6289 
        net "wb_we_1[0]" in work.decoder(verilog)
6290 
        net "un1_fsm_dly370" in work.decoder(verilog)
6291 
        net "un1_ins_i_21" in work.decoder(verilog)
6292 
End of loops
6293 
Warning: Found 28 combinational loops!
6294 
         Each loop is reported with an instance in the loop
6295 
         and nets connected to that instance.
6296 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6297 
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
6298 
    input nets to instance:
6299 
        net "alu_func_0_sqmuxa" in work.decoder(verilog)
6300 
        net "GND" in work.decoder(verilog)
6301 
        net "GND" in work.decoder(verilog)
6302 
        net "GND" in work.decoder(verilog)
6303 
        net "alu_func_1_sqmuxa" in work.decoder(verilog)
6304 
        net "GND" in work.decoder(verilog)
6305 
        net "GND" in work.decoder(verilog)
6306 
        net "GND" in work.decoder(verilog)
6307 
        net "alu_func_2_sqmuxa" in work.decoder(verilog)
6308 
        net "GND" in work.decoder(verilog)
6309 
        net "GND" in work.decoder(verilog)
6310 
        net "GND" in work.decoder(verilog)
6311 
        net "alu_func_3_sqmuxa" in work.decoder(verilog)
6312 
        net "GND" in work.decoder(verilog)
6313 
        net "GND" in work.decoder(verilog)
6314 
        net "GND" in work.decoder(verilog)
6315 
        net "alu_func_4_sqmuxa" in work.decoder(verilog)
6316 
        net "GND" in work.decoder(verilog)
6317 
        net "GND" in work.decoder(verilog)
6318 
        net "GND" in work.decoder(verilog)
6319 
        net "alu_func_5_sqmuxa" in work.decoder(verilog)
6320 
        net "GND" in work.decoder(verilog)
6321 
        net "GND" in work.decoder(verilog)
6322 
        net "GND" in work.decoder(verilog)
6323 
        net "alu_func_6_sqmuxa" in work.decoder(verilog)
6324 
        net "VCC" in work.decoder(verilog)
6325 
        net "GND" in work.decoder(verilog)
6326 
        net "GND" in work.decoder(verilog)
6327 
        net "alu_func_7_sqmuxa" in work.decoder(verilog)
6328 
        net "GND" in work.decoder(verilog)
6329 
        net "GND" in work.decoder(verilog)
6330 
        net "GND" in work.decoder(verilog)
6331 
        net "alu_func_8_sqmuxa" in work.decoder(verilog)
6332 
        net "GND" in work.decoder(verilog)
6333 
        net "GND" in work.decoder(verilog)
6334 
        net "GND" in work.decoder(verilog)
6335 
        net "alu_func_9_sqmuxa" in work.decoder(verilog)
6336 
        net "GND" in work.decoder(verilog)
6337 
        net "GND" in work.decoder(verilog)
6338 
        net "GND" in work.decoder(verilog)
6339 
        net "alu_func_10_sqmuxa" in work.decoder(verilog)
6340 
        net "GND" in work.decoder(verilog)
6341 
        net "GND" in work.decoder(verilog)
6342 
        net "GND" in work.decoder(verilog)
6343 
        net "alu_func_11_sqmuxa" in work.decoder(verilog)
6344 
        net "GND" in work.decoder(verilog)
6345 
        net "GND" in work.decoder(verilog)
6346 
        net "GND" in work.decoder(verilog)
6347 
        net "alu_func_12_sqmuxa" in work.decoder(verilog)
6348 
        net "GND" in work.decoder(verilog)
6349 
        net "GND" in work.decoder(verilog)
6350 
        net "GND" in work.decoder(verilog)
6351 
        net "alu_func_13_sqmuxa" in work.decoder(verilog)
6352 
        net "GND" in work.decoder(verilog)
6353 
        net "GND" in work.decoder(verilog)
6354 
        net "GND" in work.decoder(verilog)
6355 
        net "alu_func_14_sqmuxa" in work.decoder(verilog)
6356 
        net "GND" in work.decoder(verilog)
6357 
        net "VCC" in work.decoder(verilog)
6358 
        net "GND" in work.decoder(verilog)
6359 
        net "alu_func_15_sqmuxa" in work.decoder(verilog)
6360 
        net "GND" in work.decoder(verilog)
6361 
        net "VCC" in work.decoder(verilog)
6362 
        net "GND" in work.decoder(verilog)
6363 
        net "alu_func_16_sqmuxa" in work.decoder(verilog)
6364 
        net "GND" in work.decoder(verilog)
6365 
        net "VCC" in work.decoder(verilog)
6366 
        net "GND" in work.decoder(verilog)
6367 
        net "alu_func_17_sqmuxa" in work.decoder(verilog)
6368 
        net "GND" in work.decoder(verilog)
6369 
        net "VCC" in work.decoder(verilog)
6370 
        net "GND" in work.decoder(verilog)
6371 
        net "alu_func_18_sqmuxa" in work.decoder(verilog)
6372 
        net "GND" in work.decoder(verilog)
6373 
        net "GND" in work.decoder(verilog)
6374 
        net "GND" in work.decoder(verilog)
6375 
        net "alu_func_19_sqmuxa" in work.decoder(verilog)
6376 
        net "GND" in work.decoder(verilog)
6377 
        net "GND" in work.decoder(verilog)
6378 
        net "GND" in work.decoder(verilog)
6379 
        net "alu_func_20_sqmuxa" in work.decoder(verilog)
6380 
        net "GND" in work.decoder(verilog)
6381 
        net "GND" in work.decoder(verilog)
6382 
        net "GND" in work.decoder(verilog)
6383 
        net "alu_func_21_sqmuxa" in work.decoder(verilog)
6384 
        net "GND" in work.decoder(verilog)
6385 
        net "GND" in work.decoder(verilog)
6386 
        net "GND" in work.decoder(verilog)
6387 
        net "alu_func_22_sqmuxa" in work.decoder(verilog)
6388 
        net "GND" in work.decoder(verilog)
6389 
        net "GND" in work.decoder(verilog)
6390 
        net "GND" in work.decoder(verilog)
6391 
        net "alu_func_23_sqmuxa" in work.decoder(verilog)
6392 
        net "GND" in work.decoder(verilog)
6393 
        net "GND" in work.decoder(verilog)
6394 
        net "GND" in work.decoder(verilog)
6395 
        net "alu_func_24_sqmuxa" in work.decoder(verilog)
6396 
        net "GND" in work.decoder(verilog)
6397 
        net "GND" in work.decoder(verilog)
6398 
        net "GND" in work.decoder(verilog)
6399 
        net "alu_func_25_sqmuxa" in work.decoder(verilog)
6400 
        net "GND" in work.decoder(verilog)
6401 
        net "GND" in work.decoder(verilog)
6402 
        net "GND" in work.decoder(verilog)
6403 
        net "alu_func_26_sqmuxa" in work.decoder(verilog)
6404 
        net "GND" in work.decoder(verilog)
6405 
        net "GND" in work.decoder(verilog)
6406 
        net "GND" in work.decoder(verilog)
6407 
        net "alu_func_27_sqmuxa" in work.decoder(verilog)
6408 
        net "GND" in work.decoder(verilog)
6409 
        net "GND" in work.decoder(verilog)
6410 
        net "GND" in work.decoder(verilog)
6411 
        net "alu_func_28_sqmuxa" in work.decoder(verilog)
6412 
        net "GND" in work.decoder(verilog)
6413 
        net "GND" in work.decoder(verilog)
6414 
        net "GND" in work.decoder(verilog)
6415 
        net "alu_we_0_sqmuxa" in work.decoder(verilog)
6416 
        net "VCC" in work.decoder(verilog)
6417 
        net "GND" in work.decoder(verilog)
6418 
        net "GND" in work.decoder(verilog)
6419 
        net "alu_we_1_sqmuxa" in work.decoder(verilog)
6420 
        net "VCC" in work.decoder(verilog)
6421 
        net "GND" in work.decoder(verilog)
6422 
        net "GND" in work.decoder(verilog)
6423 
        net "alu_we_2_sqmuxa" in work.decoder(verilog)
6424 
        net "GND" in work.decoder(verilog)
6425 
        net "GND" in work.decoder(verilog)
6426 
        net "GND" in work.decoder(verilog)
6427 
        net "alu_we_3_sqmuxa" in work.decoder(verilog)
6428 
        net "fsm_dly_1[0]" in work.decoder(verilog)
6429 
        net "fsm_dly_1[1]" in work.decoder(verilog)
6430 
        net "fsm_dly_1[2]" in work.decoder(verilog)
6431 
        net "alu_we_4_sqmuxa" in work.decoder(verilog)
6432 
        net "fsm_dly_1[0]" in work.decoder(verilog)
6433 
        net "fsm_dly_1[1]" in work.decoder(verilog)
6434 
        net "fsm_dly_1[2]" in work.decoder(verilog)
6435 
        net "fsm_dly350" in work.decoder(verilog)
6436 
        net "GND" in work.decoder(verilog)
6437 
        net "VCC" in work.decoder(verilog)
6438 
        net "VCC" in work.decoder(verilog)
6439 
        net "fsm_dly351" in work.decoder(verilog)
6440 
        net "GND" in work.decoder(verilog)
6441 
        net "VCC" in work.decoder(verilog)
6442 
        net "VCC" in work.decoder(verilog)
6443 
        net "fsm_dly352" in work.decoder(verilog)
6444 
        net "VCC" in work.decoder(verilog)
6445 
        net "GND" in work.decoder(verilog)
6446 
        net "GND" in work.decoder(verilog)
6447 
        net "fsm_dly353" in work.decoder(verilog)
6448 
        net "VCC" in work.decoder(verilog)
6449 
        net "GND" in work.decoder(verilog)
6450 
        net "GND" in work.decoder(verilog)
6451 
        net "fsm_dly354" in work.decoder(verilog)
6452 
        net "VCC" in work.decoder(verilog)
6453 
        net "GND" in work.decoder(verilog)
6454 
        net "GND" in work.decoder(verilog)
6455 
        net "fsm_dly355" in work.decoder(verilog)
6456 
        net "VCC" in work.decoder(verilog)
6457 
        net "GND" in work.decoder(verilog)
6458 
        net "GND" in work.decoder(verilog)
6459 
        net "fsm_dly356" in work.decoder(verilog)
6460 
        net "GND" in work.decoder(verilog)
6461 
        net "GND" in work.decoder(verilog)
6462 
        net "GND" in work.decoder(verilog)
6463 
        net "fsm_dly357" in work.decoder(verilog)
6464 
        net "GND" in work.decoder(verilog)
6465 
        net "GND" in work.decoder(verilog)
6466 
        net "GND" in work.decoder(verilog)
6467 
        net "fsm_dly358" in work.decoder(verilog)
6468 
        net "GND" in work.decoder(verilog)
6469 
        net "GND" in work.decoder(verilog)
6470 
        net "GND" in work.decoder(verilog)
6471 
        net "fsm_dly359" in work.decoder(verilog)
6472 
        net "GND" in work.decoder(verilog)
6473 
        net "GND" in work.decoder(verilog)
6474 
        net "GND" in work.decoder(verilog)
6475 
        net "fsm_dly360" in work.decoder(verilog)
6476 
        net "GND" in work.decoder(verilog)
6477 
        net "GND" in work.decoder(verilog)
6478 
        net "GND" in work.decoder(verilog)
6479 
        net "fsm_dly361" in work.decoder(verilog)
6480 
        net "GND" in work.decoder(verilog)
6481 
        net "GND" in work.decoder(verilog)
6482 
        net "GND" in work.decoder(verilog)
6483 
        net "fsm_dly362" in work.decoder(verilog)
6484 
        net "GND" in work.decoder(verilog)
6485 
        net "GND" in work.decoder(verilog)
6486 
        net "GND" in work.decoder(verilog)
6487 
        net "fsm_dly363" in work.decoder(verilog)
6488 
        net "GND" in work.decoder(verilog)
6489 
        net "GND" in work.decoder(verilog)
6490 
        net "GND" in work.decoder(verilog)
6491 
        net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
6492 
        net "GND" in work.decoder(verilog)
6493 
        net "GND" in work.decoder(verilog)
6494 
        net "GND" in work.decoder(verilog)
6495 
        net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
6496 
        net "GND" in work.decoder(verilog)
6497 
        net "GND" in work.decoder(verilog)
6498 
        net "VCC" in work.decoder(verilog)
6499 
        net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
6500 
        net "fsm_dly_1[0]" in work.decoder(verilog)
6501 
        net "fsm_dly_1[1]" in work.decoder(verilog)
6502 
        net "fsm_dly_1[2]" in work.decoder(verilog)
6503 
        net "fsm_dly365" in work.decoder(verilog)
6504 
        net "GND" in work.decoder(verilog)
6505 
        net "GND" in work.decoder(verilog)
6506 
        net "GND" in work.decoder(verilog)
6507 
        net "fsm_dly366" in work.decoder(verilog)
6508 
        net "GND" in work.decoder(verilog)
6509 
        net "GND" in work.decoder(verilog)
6510 
        net "GND" in work.decoder(verilog)
6511 
        net "fsm_dly367" in work.decoder(verilog)
6512 
        net "GND" in work.decoder(verilog)
6513 
        net "GND" in work.decoder(verilog)
6514 
        net "GND" in work.decoder(verilog)
6515 
        net "fsm_dly368" in work.decoder(verilog)
6516 
        net "GND" in work.decoder(verilog)
6517 
        net "GND" in work.decoder(verilog)
6518 
        net "GND" in work.decoder(verilog)
6519 
        net "fsm_dly369" in work.decoder(verilog)
6520 
        net "GND" in work.decoder(verilog)
6521 
        net "GND" in work.decoder(verilog)
6522 
        net "GND" in work.decoder(verilog)
6523 
        net "fsm_dly370" in work.decoder(verilog)
6524 
        net "GND" in work.decoder(verilog)
6525 
        net "GND" in work.decoder(verilog)
6526 
        net "GND" in work.decoder(verilog)
6527 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6528 
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
6529 
    input nets to instance:
6530 
        net "ext_ctl_2[0]" in work.decoder(verilog)
6531 
        net "un1_fsm_dly370" in work.decoder(verilog)
6532 
        net "un1_ins_i_23" in work.decoder(verilog)
6533 
        net "un1_ins_i_20" in work.decoder(verilog)
6534 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6535 
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
6536 
    input nets to instance:
6537 
        net "ext_ctl_2[1]" in work.decoder(verilog)
6538 
        net "un1_fsm_dly370" in work.decoder(verilog)
6539 
        net "un1_ins_i_21" in work.decoder(verilog)
6540 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6541 
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
6542 
    input nets to instance:
6543 
        net "ext_ctl_2[2]" in work.decoder(verilog)
6544 
        net "un1_fsm_dly370" in work.decoder(verilog)
6545 
        net "un1_ins_i_21" in work.decoder(verilog)
6546 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6547 
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
6548 
    input nets to instance:
6549 
        net "rd_sel_2[0]" in work.decoder(verilog)
6550 
        net "un1_fsm_dly370" in work.decoder(verilog)
6551 
        net "un1_ins_i_21" in work.decoder(verilog)
6552 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6553 
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
6554 
    input nets to instance:
6555 
        net "rd_sel_2[1]" in work.decoder(verilog)
6556 
        net "un1_fsm_dly370" in work.decoder(verilog)
6557 
        net "un1_ins_i_22" in work.decoder(verilog)
6558 
        net "fsm_dly373" in work.decoder(verilog)
6559 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6560 
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
6561 
    input nets to instance:
6562 
        net "cmp_ctl_2[0]" in work.decoder(verilog)
6563 
        net "un1_fsm_dly370" in work.decoder(verilog)
6564 
        net "un1_ins_i_21" in work.decoder(verilog)
6565 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6566 
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
6567 
    input nets to instance:
6568 
        net "cmp_ctl_2[1]" in work.decoder(verilog)
6569 
        net "un1_fsm_dly370" in work.decoder(verilog)
6570 
        net "un1_ins_i_21" in work.decoder(verilog)
6571 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6572 
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
6573 
    input nets to instance:
6574 
        net "cmp_ctl_2[2]" in work.decoder(verilog)
6575 
        net "un1_fsm_dly370" in work.decoder(verilog)
6576 
        net "un1_ins_i_21" in work.decoder(verilog)
6577 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6578 
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
6579 
    input nets to instance:
6580 
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
6581 
        net "un1_fsm_dly370" in work.decoder(verilog)
6582 
        net "un1_ins_i_23" in work.decoder(verilog)
6583 
        net "un1_ins_i_20" in work.decoder(verilog)
6584 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6585 
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
6586 
    input nets to instance:
6587 
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
6588 
        net "un1_fsm_dly370" in work.decoder(verilog)
6589 
        net "un1_ins_i_21" in work.decoder(verilog)
6590 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6591 
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
6592 
    input nets to instance:
6593 
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
6594 
        net "un1_fsm_dly370" in work.decoder(verilog)
6595 
        net "un1_ins_i_23" in work.decoder(verilog)
6596 
        net "un1_ins_i_20" in work.decoder(verilog)
6597 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6598 
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
6599 
    input nets to instance:
6600 
        net "muxa_ctl_2[0]" in work.decoder(verilog)
6601 
        net "un1_fsm_dly370" in work.decoder(verilog)
6602 
        net "un1_ins_i_21" in work.decoder(verilog)
6603 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6604 
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
6605 
    input nets to instance:
6606 
        net "muxa_ctl_2[1]" in work.decoder(verilog)
6607 
        net "un1_fsm_dly370" in work.decoder(verilog)
6608 
        net "un1_ins_i_23" in work.decoder(verilog)
6609 
        net "un1_ins_i_20" in work.decoder(verilog)
6610 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6611 
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
6612 
    input nets to instance:
6613 
        net "muxb_ctl_2[0]" in work.decoder(verilog)
6614 
        net "un1_fsm_dly370" in work.decoder(verilog)
6615 
        net "un1_ins_i_21" in work.decoder(verilog)
6616 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6617 
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
6618 
    input nets to instance:
6619 
        net "muxb_ctl_2[1]" in work.decoder(verilog)
6620 
        net "un1_fsm_dly370" in work.decoder(verilog)
6621 
        net "un1_ins_i_23" in work.decoder(verilog)
6622 
        net "un1_ins_i_20" in work.decoder(verilog)
6623 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6624 
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
6625 
    input nets to instance:
6626 
        net "alu_func_2[0]" in work.decoder(verilog)
6627 
        net "un1_fsm_dly370" in work.decoder(verilog)
6628 
        net "un1_ins_i_21" in work.decoder(verilog)
6629 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6630 
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
6631 
    input nets to instance:
6632 
        net "alu_func_2[1]" in work.decoder(verilog)
6633 
        net "un1_fsm_dly370" in work.decoder(verilog)
6634 
        net "un1_ins_i_21" in work.decoder(verilog)
6635 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6636 
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
6637 
    input nets to instance:
6638 
        net "alu_func_2[2]" in work.decoder(verilog)
6639 
        net "un1_fsm_dly370" in work.decoder(verilog)
6640 
        net "un1_ins_i_23" in work.decoder(verilog)
6641 
        net "un1_ins_i_20" in work.decoder(verilog)
6642 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6643 
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
6644 
    input nets to instance:
6645 
        net "alu_func_2[3]" in work.decoder(verilog)
6646 
        net "un1_fsm_dly370" in work.decoder(verilog)
6647 
        net "un1_ins_i_23" in work.decoder(verilog)
6648 
        net "un1_ins_i_20" in work.decoder(verilog)
6649 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6650 
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
6651 
    input nets to instance:
6652 
        net "alu_func_2[4]" in work.decoder(verilog)
6653 
        net "un1_fsm_dly370" in work.decoder(verilog)
6654 
        net "un1_ins_i_21" in work.decoder(verilog)
6655 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6656 
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
6657 
    input nets to instance:
6658 
        net "dmem_ctl_2[0]" in work.decoder(verilog)
6659 
        net "un1_fsm_dly370" in work.decoder(verilog)
6660 
        net "un1_ins_i_23" in work.decoder(verilog)
6661 
        net "un1_ins_i_20" in work.decoder(verilog)
6662 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6663 
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
6664 
    input nets to instance:
6665 
        net "dmem_ctl_2[1]" in work.decoder(verilog)
6666 
        net "un1_fsm_dly370" in work.decoder(verilog)
6667 
        net "un1_ins_i_22" in work.decoder(verilog)
6668 
        net "fsm_dly373" in work.decoder(verilog)
6669 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6670 
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
6671 
    input nets to instance:
6672 
        net "dmem_ctl_2[2]" in work.decoder(verilog)
6673 
        net "un1_fsm_dly370" in work.decoder(verilog)
6674 
        net "un1_ins_i_24" in work.decoder(verilog)
6675 
        net "un1_ins_i_15" in work.decoder(verilog)
6676 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6677 
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
6678 
    input nets to instance:
6679 
        net "dmem_ctl_2[3]" in work.decoder(verilog)
6680 
        net "un1_fsm_dly370" in work.decoder(verilog)
6681 
        net "un1_ins_i_21" in work.decoder(verilog)
6682 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6683 
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
6684 
    input nets to instance:
6685 
        net "alu_we_1[0]" in work.decoder(verilog)
6686 
        net "un1_fsm_dly370" in work.decoder(verilog)
6687 
        net "un1_ins_i_21" in work.decoder(verilog)
6688 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6689 
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
6690 
    input nets to instance:
6691 
        net "wb_mux_1[0]" in work.decoder(verilog)
6692 
        net "un1_fsm_dly370" in work.decoder(verilog)
6693 
        net "un1_ins_i_21" in work.decoder(verilog)
6694 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6695 
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
6696 
    input nets to instance:
6697 
        net "wb_we_1[0]" in work.decoder(verilog)
6698 
        net "un1_fsm_dly370" in work.decoder(verilog)
6699 
        net "un1_ins_i_21" in work.decoder(verilog)
6700 
End of loops
6701 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:243:4:243:10:@N::@XP_MSG">mips_uart.v(243)</a><!@TM:1223605618> | Found counter in view:work.uart_read(verilog) inst clk_ctr[15:0]
6702 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:256:4:256:10:@N::@XP_MSG">mips_uart.v(256)</a><!@TM:1223605618> | Found counter in view:work.uart_read(verilog) inst bit_ctr[2:0]
6703 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:138:4:138:10:@N::@XP_MSG">mips_uart.v(138)</a><!@TM:1223605618> | Found counter in view:work.uart_write(verilog) inst clk_ctr[15:0]
6704 
@N: : <a href="e:\mips789\mips789\rtl\verilog\mips_uart.v:151:4:151:10:@N::@XP_MSG">mips_uart.v(151)</a><!@TM:1223605618> | Found counter in view:work.uart_write(verilog) inst bit_ctr[2:0]
6705 
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:67:12:67:16:@N:MO106:@XP_MSG">dvc.v(67)</a><!@TM:1223605618> | Found ROM, 'seg_20[6:0]', 16 words by 7 bits
6706 
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:67:12:67:16:@N:MO106:@XP_MSG">dvc.v(67)</a><!@TM:1223605618> | Found ROM, 'seg[6:0]', 16 words by 7 bits
6707 
@N: : <a href="e:\mips789\mips789\rtl\verilog\dvc.v:23:4:23:10:@N::@XP_MSG">dvc.v(23)</a><!@TM:1223605618> | Found counter in view:work.tmr0(verilog) inst cntr[31:0]
6708 
Warning: Found 28 combinational loops!
6709 
         Each loop is reported with an instance in the loop
6710 
         and nets connected to that instance.
6711 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6712 
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
6713 
    input nets to instance:
6714 
        net "N_172" in work.decoder(verilog)
6715 
        net "fsm_dly_1[0]" in work.decoder(verilog)
6716 
        net "N_415" in work.decoder(verilog)
6717 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6718 
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
6719 
    input nets to instance:
6720 
        net "ext_ctl_2[0]" in work.decoder(verilog)
6721 
        net "un1_fsm_dly370" in work.decoder(verilog)
6722 
        net "un1_ins_i_23" in work.decoder(verilog)
6723 
        net "un1_ins_i_20" in work.decoder(verilog)
6724 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6725 
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
6726 
    input nets to instance:
6727 
        net "ext_ctl_2[1]" in work.decoder(verilog)
6728 
        net "un1_fsm_dly370" in work.decoder(verilog)
6729 
        net "N_436" in work.decoder(verilog)
6730 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6731 
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
6732 
    input nets to instance:
6733 
        net "ext_ctl_2[2]" in work.decoder(verilog)
6734 
        net "un1_fsm_dly370" in work.decoder(verilog)
6735 
        net "N_436" in work.decoder(verilog)
6736 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6737 
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
6738 
    input nets to instance:
6739 
        net "rd_sel_2[0]" in work.decoder(verilog)
6740 
        net "un1_fsm_dly370" in work.decoder(verilog)
6741 
        net "N_436" in work.decoder(verilog)
6742 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6743 
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
6744 
    input nets to instance:
6745 
        net "rd_sel_2[1]" in work.decoder(verilog)
6746 
        net "un1_fsm_dly370" in work.decoder(verilog)
6747 
        net "N_438" in work.decoder(verilog)
6748 
        net "fsm_dly373" in work.decoder(verilog)
6749 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6750 
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
6751 
    input nets to instance:
6752 
        net "cmp_ctl_2[0]" in work.decoder(verilog)
6753 
        net "un1_fsm_dly370" in work.decoder(verilog)
6754 
        net "N_436" in work.decoder(verilog)
6755 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6756 
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
6757 
    input nets to instance:
6758 
        net "cmp_ctl_2[1]" in work.decoder(verilog)
6759 
        net "un1_fsm_dly370" in work.decoder(verilog)
6760 
        net "N_436" in work.decoder(verilog)
6761 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6762 
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
6763 
    input nets to instance:
6764 
        net "cmp_ctl_2[2]" in work.decoder(verilog)
6765 
        net "un1_fsm_dly370" in work.decoder(verilog)
6766 
        net "N_436" in work.decoder(verilog)
6767 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6768 
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
6769 
    input nets to instance:
6770 
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
6771 
        net "un1_fsm_dly370" in work.decoder(verilog)
6772 
        net "un1_ins_i_23" in work.decoder(verilog)
6773 
        net "un1_ins_i_20" in work.decoder(verilog)
6774 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6775 
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
6776 
    input nets to instance:
6777 
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
6778 
        net "un1_fsm_dly370" in work.decoder(verilog)
6779 
        net "N_436" in work.decoder(verilog)
6780 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6781 
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
6782 
    input nets to instance:
6783 
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
6784 
        net "un1_fsm_dly370" in work.decoder(verilog)
6785 
        net "un1_ins_i_23" in work.decoder(verilog)
6786 
        net "un1_ins_i_20" in work.decoder(verilog)
6787 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6788 
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
6789 
    input nets to instance:
6790 
        net "muxa_ctl_2[0]" in work.decoder(verilog)
6791 
        net "un1_fsm_dly370" in work.decoder(verilog)
6792 
        net "N_436" in work.decoder(verilog)
6793 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6794 
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
6795 
    input nets to instance:
6796 
        net "muxa_ctl_2[1]" in work.decoder(verilog)
6797 
        net "un1_fsm_dly370" in work.decoder(verilog)
6798 
        net "un1_ins_i_23" in work.decoder(verilog)
6799 
        net "un1_ins_i_20" in work.decoder(verilog)
6800 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6801 
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
6802 
    input nets to instance:
6803 
        net "muxb_ctl_2[0]" in work.decoder(verilog)
6804 
        net "un1_fsm_dly370" in work.decoder(verilog)
6805 
        net "N_436" in work.decoder(verilog)
6806 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6807 
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
6808 
    input nets to instance:
6809 
        net "muxb_ctl_2[1]" in work.decoder(verilog)
6810 
        net "un1_fsm_dly370" in work.decoder(verilog)
6811 
        net "un1_ins_i_23" in work.decoder(verilog)
6812 
        net "un1_ins_i_20" in work.decoder(verilog)
6813 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6814 
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
6815 
    input nets to instance:
6816 
        net "alu_func_2[0]" in work.decoder(verilog)
6817 
        net "un1_fsm_dly370" in work.decoder(verilog)
6818 
        net "N_436" in work.decoder(verilog)
6819 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6820 
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
6821 
    input nets to instance:
6822 
        net "alu_func_2[1]" in work.decoder(verilog)
6823 
        net "un1_fsm_dly370" in work.decoder(verilog)
6824 
        net "N_436" in work.decoder(verilog)
6825 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6826 
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
6827 
    input nets to instance:
6828 
        net "alu_func_2[2]" in work.decoder(verilog)
6829 
        net "un1_fsm_dly370" in work.decoder(verilog)
6830 
        net "un1_ins_i_23" in work.decoder(verilog)
6831 
        net "un1_ins_i_20" in work.decoder(verilog)
6832 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6833 
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
6834 
    input nets to instance:
6835 
        net "alu_func_2[3]" in work.decoder(verilog)
6836 
        net "un1_fsm_dly370" in work.decoder(verilog)
6837 
        net "un1_ins_i_23" in work.decoder(verilog)
6838 
        net "un1_ins_i_20" in work.decoder(verilog)
6839 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6840 
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
6841 
    input nets to instance:
6842 
        net "alu_func_2[4]" in work.decoder(verilog)
6843 
        net "un1_fsm_dly370" in work.decoder(verilog)
6844 
        net "N_436" in work.decoder(verilog)
6845 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6846 
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
6847 
    input nets to instance:
6848 
        net "dmem_ctl_2[0]" in work.decoder(verilog)
6849 
        net "un1_fsm_dly370" in work.decoder(verilog)
6850 
        net "un1_ins_i_23" in work.decoder(verilog)
6851 
        net "un1_ins_i_20" in work.decoder(verilog)
6852 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6853 
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
6854 
    input nets to instance:
6855 
        net "dmem_ctl_2[1]" in work.decoder(verilog)
6856 
        net "un1_fsm_dly370" in work.decoder(verilog)
6857 
        net "N_438" in work.decoder(verilog)
6858 
        net "fsm_dly373" in work.decoder(verilog)
6859 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6860 
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
6861 
    input nets to instance:
6862 
        net "dmem_ctl_2[2]" in work.decoder(verilog)
6863 
        net "un1_fsm_dly370" in work.decoder(verilog)
6864 
        net "un1_ins_i_24" in work.decoder(verilog)
6865 
        net "un1_ins_i_15" in work.decoder(verilog)
6866 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6867 
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
6868 
    input nets to instance:
6869 
        net "dmem_ctl_2[3]" in work.decoder(verilog)
6870 
        net "un1_fsm_dly370" in work.decoder(verilog)
6871 
        net "N_436" in work.decoder(verilog)
6872 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6873 
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
6874 
    input nets to instance:
6875 
        net "alu_we_1[0]" in work.decoder(verilog)
6876 
        net "un1_fsm_dly370" in work.decoder(verilog)
6877 
        net "N_436" in work.decoder(verilog)
6878 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6879 
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
6880 
    input nets to instance:
6881 
        net "wb_mux_1[0]" in work.decoder(verilog)
6882 
        net "un1_fsm_dly370" in work.decoder(verilog)
6883 
        net "N_436" in work.decoder(verilog)
6884 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6885 
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
6886 
    input nets to instance:
6887 
        net "wb_we_1[0]" in work.decoder(verilog)
6888 
        net "un1_fsm_dly370" in work.decoder(verilog)
6889 
        net "N_436" in work.decoder(verilog)
6890 
End of loops
6891 
Warning: Found 28 combinational loops!
6892 
         Each loop is reported with an instance in the loop
6893 
         and nets connected to that instance.
6894 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6895 
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
6896 
    input nets to instance:
6897 
        net "N_172" in work.decoder(verilog)
6898 
        net "fsm_dly_1[0]" in work.decoder(verilog)
6899 
        net "N_415" in work.decoder(verilog)
6900 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6901 
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
6902 
    input nets to instance:
6903 
        net "ext_ctl_2[0]" in work.decoder(verilog)
6904 
        net "un1_fsm_dly370" in work.decoder(verilog)
6905 
        net "un1_ins_i_23" in work.decoder(verilog)
6906 
        net "un1_ins_i_20" in work.decoder(verilog)
6907 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6908 
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
6909 
    input nets to instance:
6910 
        net "ext_ctl_2[1]" in work.decoder(verilog)
6911 
        net "un1_fsm_dly370" in work.decoder(verilog)
6912 
        net "N_436" in work.decoder(verilog)
6913 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6914 
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
6915 
    input nets to instance:
6916 
        net "ext_ctl_2[2]" in work.decoder(verilog)
6917 
        net "un1_fsm_dly370" in work.decoder(verilog)
6918 
        net "N_436" in work.decoder(verilog)
6919 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6920 
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
6921 
    input nets to instance:
6922 
        net "rd_sel_2[0]" in work.decoder(verilog)
6923 
        net "un1_fsm_dly370" in work.decoder(verilog)
6924 
        net "N_436" in work.decoder(verilog)
6925 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6926 
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
6927 
    input nets to instance:
6928 
        net "rd_sel_2[1]" in work.decoder(verilog)
6929 
        net "un1_fsm_dly370" in work.decoder(verilog)
6930 
        net "N_438" in work.decoder(verilog)
6931 
        net "fsm_dly373" in work.decoder(verilog)
6932 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6933 
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
6934 
    input nets to instance:
6935 
        net "cmp_ctl_2[0]" in work.decoder(verilog)
6936 
        net "un1_fsm_dly370" in work.decoder(verilog)
6937 
        net "N_436" in work.decoder(verilog)
6938 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6939 
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
6940 
    input nets to instance:
6941 
        net "cmp_ctl_2[1]" in work.decoder(verilog)
6942 
        net "un1_fsm_dly370" in work.decoder(verilog)
6943 
        net "N_436" in work.decoder(verilog)
6944 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6945 
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
6946 
    input nets to instance:
6947 
        net "cmp_ctl_2[2]" in work.decoder(verilog)
6948 
        net "un1_fsm_dly370" in work.decoder(verilog)
6949 
        net "N_436" in work.decoder(verilog)
6950 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6951 
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
6952 
    input nets to instance:
6953 
        net "pc_gen_ctl_2[0]" in work.decoder(verilog)
6954 
        net "un1_fsm_dly370" in work.decoder(verilog)
6955 
        net "un1_ins_i_23" in work.decoder(verilog)
6956 
        net "un1_ins_i_20" in work.decoder(verilog)
6957 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6958 
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
6959 
    input nets to instance:
6960 
        net "pc_gen_ctl_2[1]" in work.decoder(verilog)
6961 
        net "un1_fsm_dly370" in work.decoder(verilog)
6962 
        net "N_436" in work.decoder(verilog)
6963 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6964 
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
6965 
    input nets to instance:
6966 
        net "pc_gen_ctl_2[2]" in work.decoder(verilog)
6967 
        net "un1_fsm_dly370" in work.decoder(verilog)
6968 
        net "un1_ins_i_23" in work.decoder(verilog)
6969 
        net "un1_ins_i_20" in work.decoder(verilog)
6970 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6971 
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
6972 
    input nets to instance:
6973 
        net "muxa_ctl_2[0]" in work.decoder(verilog)
6974 
        net "un1_fsm_dly370" in work.decoder(verilog)
6975 
        net "N_436" in work.decoder(verilog)
6976 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6977 
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
6978 
    input nets to instance:
6979 
        net "muxa_ctl_2[1]" in work.decoder(verilog)
6980 
        net "un1_fsm_dly370" in work.decoder(verilog)
6981 
        net "un1_ins_i_23" in work.decoder(verilog)
6982 
        net "un1_ins_i_20" in work.decoder(verilog)
6983 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6984 
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
6985 
    input nets to instance:
6986 
        net "muxb_ctl_2[0]" in work.decoder(verilog)
6987 
        net "un1_fsm_dly370" in work.decoder(verilog)
6988 
        net "N_436" in work.decoder(verilog)
6989 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6990 
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
6991 
    input nets to instance:
6992 
        net "muxb_ctl_2[1]" in work.decoder(verilog)
6993 
        net "un1_fsm_dly370" in work.decoder(verilog)
6994 
        net "un1_ins_i_23" in work.decoder(verilog)
6995 
        net "un1_ins_i_20" in work.decoder(verilog)
6996 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
6997 
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
6998 
    input nets to instance:
6999 
        net "alu_func_2[0]" in work.decoder(verilog)
7000 
        net "un1_fsm_dly370" in work.decoder(verilog)
7001 
        net "N_436" in work.decoder(verilog)
7002 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7003 
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
7004 
    input nets to instance:
7005 
        net "alu_func_2[1]" in work.decoder(verilog)
7006 
        net "un1_fsm_dly370" in work.decoder(verilog)
7007 
        net "N_436" in work.decoder(verilog)
7008 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7009 
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
7010 
    input nets to instance:
7011 
        net "alu_func_2[2]" in work.decoder(verilog)
7012 
        net "un1_fsm_dly370" in work.decoder(verilog)
7013 
        net "un1_ins_i_23" in work.decoder(verilog)
7014 
        net "un1_ins_i_20" in work.decoder(verilog)
7015 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7016 
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
7017 
    input nets to instance:
7018 
        net "alu_func_2[3]" in work.decoder(verilog)
7019 
        net "un1_fsm_dly370" in work.decoder(verilog)
7020 
        net "un1_ins_i_23" in work.decoder(verilog)
7021 
        net "un1_ins_i_20" in work.decoder(verilog)
7022 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7023 
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
7024 
    input nets to instance:
7025 
        net "alu_func_2[4]" in work.decoder(verilog)
7026 
        net "un1_fsm_dly370" in work.decoder(verilog)
7027 
        net "N_436" in work.decoder(verilog)
7028 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7029 
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
7030 
    input nets to instance:
7031 
        net "dmem_ctl_2[0]" in work.decoder(verilog)
7032 
        net "un1_fsm_dly370" in work.decoder(verilog)
7033 
        net "un1_ins_i_23" in work.decoder(verilog)
7034 
        net "un1_ins_i_20" in work.decoder(verilog)
7035 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7036 
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
7037 
    input nets to instance:
7038 
        net "dmem_ctl_2[1]" in work.decoder(verilog)
7039 
        net "un1_fsm_dly370" in work.decoder(verilog)
7040 
        net "N_438" in work.decoder(verilog)
7041 
        net "fsm_dly373" in work.decoder(verilog)
7042 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7043 
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
7044 
    input nets to instance:
7045 
        net "dmem_ctl_2[2]" in work.decoder(verilog)
7046 
        net "un1_fsm_dly370" in work.decoder(verilog)
7047 
        net "un1_ins_i_24" in work.decoder(verilog)
7048 
        net "un1_ins_i_15" in work.decoder(verilog)
7049 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7050 
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
7051 
    input nets to instance:
7052 
        net "dmem_ctl_2[3]" in work.decoder(verilog)
7053 
        net "un1_fsm_dly370" in work.decoder(verilog)
7054 
        net "N_436" in work.decoder(verilog)
7055 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7056 
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
7057 
    input nets to instance:
7058 
        net "alu_we_1[0]" in work.decoder(verilog)
7059 
        net "un1_fsm_dly370" in work.decoder(verilog)
7060 
        net "N_436" in work.decoder(verilog)
7061 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7062 
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
7063 
    input nets to instance:
7064 
        net "wb_mux_1[0]" in work.decoder(verilog)
7065 
        net "un1_fsm_dly370" in work.decoder(verilog)
7066 
        net "N_436" in work.decoder(verilog)
7067 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7068 
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
7069 
    input nets to instance:
7070 
        net "wb_we_1[0]" in work.decoder(verilog)
7071 
        net "un1_fsm_dly370" in work.decoder(verilog)
7072 
        net "N_436" in work.decoder(verilog)
7073 
End of loops
7074 
Automatic dissolve during optimization of view:work.mips_core(verilog) of iRF_stage.reg_bank(reg_array)
7075 
Auto Dissolve of decoder_pipe (inst of view:work.decode_pipe(verilog))
7076 
Auto Dissolve of iRF_stage.i_cmp (inst of view:work.compare(verilog))
7077 
Auto Dissolve of mips_tmr0 (inst of view:work.tmr0(verilog))
7078 
Warning: Found 28 combinational loops!
7079 
         Each loop is reported with an instance in the loop
7080 
         and nets connected to that instance.
7081 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7082 
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
7083 
    input nets to instance:
7084 
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
7085 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7086 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7087 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7088 
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
7089 
    input nets to instance:
7090 
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
7091 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7092 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7093 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7094 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7095 
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
7096 
    input nets to instance:
7097 
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
7098 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7099 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7100 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7101 
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
7102 
    input nets to instance:
7103 
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
7104 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7105 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7106 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7107 
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
7108 
    input nets to instance:
7109 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
7110 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7111 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7112 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7113 
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
7114 
    input nets to instance:
7115 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
7116 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7117 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7118 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7119 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7120 
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
7121 
    input nets to instance:
7122 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
7123 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7124 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7125 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7126 
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
7127 
    input nets to instance:
7128 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
7129 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7130 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7131 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7132 
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
7133 
    input nets to instance:
7134 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
7135 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7136 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7137 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7138 
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
7139 
    input nets to instance:
7140 
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
7141 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7142 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7143 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7144 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7145 
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
7146 
    input nets to instance:
7147 
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
7148 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7149 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7150 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7151 
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
7152 
    input nets to instance:
7153 
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
7154 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7155 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7156 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7157 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7158 
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
7159 
    input nets to instance:
7160 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
7161 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7162 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7163 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7164 
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
7165 
    input nets to instance:
7166 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
7167 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7168 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7169 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7170 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7171 
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
7172 
    input nets to instance:
7173 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
7174 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7175 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7176 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7177 
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
7178 
    input nets to instance:
7179 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
7180 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7181 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7182 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7183 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7184 
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
7185 
    input nets to instance:
7186 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
7187 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7188 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7189 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7190 
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
7191 
    input nets to instance:
7192 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
7193 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7194 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7195 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7196 
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
7197 
    input nets to instance:
7198 
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
7199 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7200 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7201 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7202 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7203 
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
7204 
    input nets to instance:
7205 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
7206 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7207 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7208 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7209 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7210 
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
7211 
    input nets to instance:
7212 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
7213 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7214 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7215 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7216 
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
7217 
    input nets to instance:
7218 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
7219 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7220 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7221 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7222 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7223 
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
7224 
    input nets to instance:
7225 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
7226 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7227 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7228 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7229 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7230 
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
7231 
    input nets to instance:
7232 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
7233 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7234 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_24" in work.mips_sys(verilog)
7235 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
7236 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7237 
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
7238 
    input nets to instance:
7239 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
7240 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7241 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7242 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7243 
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
7244 
    input nets to instance:
7245 
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
7246 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7247 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7248 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7249 
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
7250 
    input nets to instance:
7251 
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
7252 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7253 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7254 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7255 
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
7256 
    input nets to instance:
7257 
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
7258 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7259 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7260 
End of loops
7261 
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
7262 
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
7263 
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
7264 
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
7265 
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
7266 
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ulit.v:104:111:104:117:@W:BN116:@XP_MSG">ulit.v(104)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.ins_reg.r32_o[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
7267 
Warning: Found 28 combinational loops!
7268 
         Each loop is reported with an instance in the loop
7269 
         and nets connected to that instance.
7270 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7271 
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
7272 
    input nets to instance:
7273 
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
7274 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7275 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7276 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7277 
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
7278 
    input nets to instance:
7279 
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
7280 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7281 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7282 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7283 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7284 
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
7285 
    input nets to instance:
7286 
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
7287 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7288 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7289 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7290 
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
7291 
    input nets to instance:
7292 
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
7293 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7294 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7295 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7296 
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
7297 
    input nets to instance:
7298 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
7299 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7300 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7301 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7302 
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
7303 
    input nets to instance:
7304 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
7305 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7306 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7307 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7308 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7309 
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
7310 
    input nets to instance:
7311 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
7312 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7313 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7314 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7315 
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
7316 
    input nets to instance:
7317 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
7318 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7319 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7320 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7321 
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
7322 
    input nets to instance:
7323 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
7324 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7325 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7326 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7327 
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
7328 
    input nets to instance:
7329 
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
7330 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7331 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7332 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7333 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7334 
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
7335 
    input nets to instance:
7336 
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
7337 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7338 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7339 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7340 
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
7341 
    input nets to instance:
7342 
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
7343 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7344 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7345 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7346 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7347 
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
7348 
    input nets to instance:
7349 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
7350 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7351 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7352 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7353 
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
7354 
    input nets to instance:
7355 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
7356 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7357 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7358 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7359 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7360 
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
7361 
    input nets to instance:
7362 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
7363 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7364 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7365 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7366 
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
7367 
    input nets to instance:
7368 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
7369 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7370 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7371 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7372 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7373 
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
7374 
    input nets to instance:
7375 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
7376 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7377 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7378 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7379 
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
7380 
    input nets to instance:
7381 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
7382 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7383 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7384 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7385 
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
7386 
    input nets to instance:
7387 
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
7388 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7389 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7390 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7391 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7392 
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
7393 
    input nets to instance:
7394 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
7395 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7396 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7397 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7398 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7399 
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
7400 
    input nets to instance:
7401 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
7402 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7403 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7404 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7405 
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
7406 
    input nets to instance:
7407 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
7408 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7409 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7410 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7411 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7412 
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
7413 
    input nets to instance:
7414 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
7415 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7416 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7417 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7418 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7419 
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
7420 
    input nets to instance:
7421 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
7422 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7423 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
7424 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
7425 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7426 
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
7427 
    input nets to instance:
7428 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
7429 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7430 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7431 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7432 
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
7433 
    input nets to instance:
7434 
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
7435 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7436 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7437 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7438 
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
7439 
    input nets to instance:
7440 
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
7441 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7442 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7443 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7444 
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
7445 
    input nets to instance:
7446 
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
7447 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7448 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7449 
End of loops
7450 
Warning: Found 28 combinational loops!
7451 
         Each loop is reported with an instance in the loop
7452 
         and nets connected to that instance.
7453 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7454 
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
7455 
    input nets to instance:
7456 
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
7457 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7458 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7459 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7460 
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
7461 
    input nets to instance:
7462 
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
7463 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7464 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7465 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7466 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7467 
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
7468 
    input nets to instance:
7469 
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
7470 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7471 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7472 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7473 
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
7474 
    input nets to instance:
7475 
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
7476 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7477 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7478 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7479 
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
7480 
    input nets to instance:
7481 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
7482 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7483 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7484 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7485 
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
7486 
    input nets to instance:
7487 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
7488 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7489 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7490 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7491 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7492 
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
7493 
    input nets to instance:
7494 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
7495 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7496 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7497 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7498 
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
7499 
    input nets to instance:
7500 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
7501 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7502 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7503 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7504 
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
7505 
    input nets to instance:
7506 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
7507 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7508 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7509 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7510 
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
7511 
    input nets to instance:
7512 
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
7513 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7514 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7515 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7516 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7517 
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
7518 
    input nets to instance:
7519 
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
7520 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7521 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7522 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7523 
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
7524 
    input nets to instance:
7525 
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
7526 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7527 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7528 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7529 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7530 
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
7531 
    input nets to instance:
7532 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
7533 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7534 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7535 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7536 
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
7537 
    input nets to instance:
7538 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
7539 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7540 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7541 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7542 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7543 
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
7544 
    input nets to instance:
7545 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
7546 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7547 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7548 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7549 
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
7550 
    input nets to instance:
7551 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
7552 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7553 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7554 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7555 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7556 
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
7557 
    input nets to instance:
7558 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
7559 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7560 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7561 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7562 
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
7563 
    input nets to instance:
7564 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
7565 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7566 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7567 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7568 
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
7569 
    input nets to instance:
7570 
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
7571 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7572 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7573 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7574 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7575 
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
7576 
    input nets to instance:
7577 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
7578 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7579 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7580 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7581 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7582 
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
7583 
    input nets to instance:
7584 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
7585 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7586 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7587 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7588 
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
7589 
    input nets to instance:
7590 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
7591 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7592 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7593 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7594 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7595 
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
7596 
    input nets to instance:
7597 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
7598 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7599 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7600 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7601 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7602 
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
7603 
    input nets to instance:
7604 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
7605 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7606 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
7607 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
7608 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7609 
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
7610 
    input nets to instance:
7611 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
7612 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7613 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7614 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7615 
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
7616 
    input nets to instance:
7617 
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
7618 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7619 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7620 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7621 
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
7622 
    input nets to instance:
7623 
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
7624 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7625 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7626 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7627 
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
7628 
    input nets to instance:
7629 
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
7630 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7631 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7632 
End of loops
7633 
Warning: Found 28 combinational loops!
7634 
         Each loop is reported with an instance in the loop
7635 
         and nets connected to that instance.
7636 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7637 
1) instance mips_core.decoder_pipe.idecoder.fsm_dly_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
7638 
    input nets to instance:
7639 
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
7640 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7641 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7642 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7643 
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
7644 
    input nets to instance:
7645 
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
7646 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7647 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7648 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7649 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7650 
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
7651 
    input nets to instance:
7652 
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
7653 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7654 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7655 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7656 
4) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
7657 
    input nets to instance:
7658 
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
7659 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7660 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7661 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7662 
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
7663 
    input nets to instance:
7664 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
7665 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7666 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7667 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7668 
6) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
7669 
    input nets to instance:
7670 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
7671 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7672 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7673 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7674 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7675 
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
7676 
    input nets to instance:
7677 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
7678 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7679 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7680 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7681 
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
7682 
    input nets to instance:
7683 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
7684 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7685 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7686 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7687 
9) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
7688 
    input nets to instance:
7689 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
7690 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7691 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7692 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7693 
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
7694 
    input nets to instance:
7695 
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
7696 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7697 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7698 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7699 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7700 
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
7701 
    input nets to instance:
7702 
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
7703 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7704 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7705 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7706 
12) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
7707 
    input nets to instance:
7708 
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
7709 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7710 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7711 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7712 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7713 
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
7714 
    input nets to instance:
7715 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
7716 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7717 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7718 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7719 
14) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
7720 
    input nets to instance:
7721 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
7722 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7723 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7724 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7725 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7726 
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
7727 
    input nets to instance:
7728 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
7729 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7730 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7731 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7732 
16) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
7733 
    input nets to instance:
7734 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
7735 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7736 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7737 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7738 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7739 
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
7740 
    input nets to instance:
7741 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
7742 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7743 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7744 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7745 
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
7746 
    input nets to instance:
7747 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
7748 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7749 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7750 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7751 
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
7752 
    input nets to instance:
7753 
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
7754 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7755 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7756 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7757 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7758 
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
7759 
    input nets to instance:
7760 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
7761 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7762 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7763 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7764 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7765 
21) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
7766 
    input nets to instance:
7767 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
7768 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7769 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7770 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7771 
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
7772 
    input nets to instance:
7773 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
7774 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7775 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7776 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7777 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7778 
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
7779 
    input nets to instance:
7780 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
7781 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7782 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7783 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7784 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7785 
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
7786 
    input nets to instance:
7787 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
7788 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7789 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
7790 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
7791 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7792 
25) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
7793 
    input nets to instance:
7794 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
7795 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7796 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7797 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7798 
26) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
7799 
    input nets to instance:
7800 
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
7801 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7802 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7803 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7804 
27) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
7805 
    input nets to instance:
7806 
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
7807 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7808 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7809 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7810 
28) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
7811 
    input nets to instance:
7812 
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
7813 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7814 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7815 
End of loops
7816 
Encoding state machine ScratchLib.imips_dvc.iuart0.uart_txd.ua_state_7_0c(gate_dflt)-imips_dvc.iuart0.uart_txd.ua_state[7:0]
7817 
original code -> new code
7818 
   000 -> 00000000
7819 
   001 -> 00000011
7820 
   010 -> 00000101
7821 
   011 -> 00001001
7822 
   100 -> 00010001
7823 
   101 -> 00100001
7824 
   110 -> 01000001
7825 
   111 -> 10000001
7826 
Encoding state machine ScratchLib.imips_dvc.iuart0.uart_rd_tak.ua_state_4_0c(gate_dflt)-imips_dvc.iuart0.uart_rd_tak.ua_state[4:0]
7827 
original code -> new code
7828 
   000 -> 00000
7829 
   001 -> 00011
7830 
   010 -> 00101
7831 
   011 -> 01001
7832 
   100 -> 10001
7833 
Encoding state machine ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)-mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[8:0]
7834 
original code -> new code
7835 
   0000 -> 000000000
7836 
   0001 -> 000000011
7837 
   0010 -> 000000101
7838 
   0011 -> 000001001
7839 
   0100 -> 000010001
7840 
   0101 -> 000100001
7841 
   0110 -> 001000001
7842 
   0111 -> 010000001
7843 
   1000 -> 100000001
7844 
<font color=#A52A2A>@W:<a href="@W:FA140:@XP_HELP">FA140</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:126:16:126:17:@W:FA140:@XP_MSG">ctl_fsm.v(126)</a><!@TM:1223605618> | DFF ScratchLib.mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0_8_0c(gate_dflt)-mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[5] is stuck at '0', removing ... </font>
7845 
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="e:\mips789\mips789\rtl\verilog\ctl_fsm.v:126:16:126:17:@W:BN116:@XP_MSG">ctl_fsm.v(126)</a><!@TM:1223605618> | Removing sequential instance mips_core.iRF_stage.MIAN_FSM.CurrState_Sreg0[5] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
7846 
Warning: Found 27 combinational loops!
7847 
         Each loop is reported with an instance in the loop
7848 
         and nets connected to that instance.
7849 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7850 
1) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
7851 
    input nets to instance:
7852 
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
7853 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7854 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7855 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7856 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7857 
2) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
7858 
    input nets to instance:
7859 
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
7860 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7861 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7862 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7863 
3) instance mips_core.decoder_pipe.idecoder.ext_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
7864 
    input nets to instance:
7865 
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
7866 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7867 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7868 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7869 
4) instance mips_core.decoder_pipe.idecoder.rd_sel_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
7870 
    input nets to instance:
7871 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
7872 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7873 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7874 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7875 
5) instance mips_core.decoder_pipe.idecoder.rd_sel_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
7876 
    input nets to instance:
7877 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
7878 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7879 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7880 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7881 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7882 
6) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
7883 
    input nets to instance:
7884 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
7885 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7886 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7887 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7888 
7) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
7889 
    input nets to instance:
7890 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
7891 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7892 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7893 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7894 
8) instance mips_core.decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
7895 
    input nets to instance:
7896 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
7897 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7898 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7899 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7900 
9) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
7901 
    input nets to instance:
7902 
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
7903 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7904 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7905 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7906 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7907 
10) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
7908 
    input nets to instance:
7909 
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
7910 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7911 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7912 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7913 
11) instance mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
7914 
    input nets to instance:
7915 
        net "mips_core.decoder_pipe.idecoder.N_1232_i" in work.mips_sys(verilog)
7916 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7917 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7918 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7919 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7920 
12) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
7921 
    input nets to instance:
7922 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
7923 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7924 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7925 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7926 
13) instance mips_core.decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
7927 
    input nets to instance:
7928 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
7929 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7930 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7931 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7932 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7933 
14) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
7934 
    input nets to instance:
7935 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
7936 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7937 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7938 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7939 
15) instance mips_core.decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
7940 
    input nets to instance:
7941 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
7942 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7943 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7944 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7945 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7946 
16) instance mips_core.decoder_pipe.idecoder.alu_func_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
7947 
    input nets to instance:
7948 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
7949 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7950 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7951 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7952 
17) instance mips_core.decoder_pipe.idecoder.alu_func_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
7953 
    input nets to instance:
7954 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
7955 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7956 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7957 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7958 
18) instance mips_core.decoder_pipe.idecoder.alu_func_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
7959 
    input nets to instance:
7960 
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
7961 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7962 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7963 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7964 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7965 
19) instance mips_core.decoder_pipe.idecoder.alu_func_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
7966 
    input nets to instance:
7967 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
7968 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7969 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7970 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7971 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7972 
20) instance mips_core.decoder_pipe.idecoder.alu_func_1[4] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
7973 
    input nets to instance:
7974 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
7975 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7976 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
7977 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7978 
21) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
7979 
    input nets to instance:
7980 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
7981 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7982 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
7983 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
7984 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7985 
22) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
7986 
    input nets to instance:
7987 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
7988 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7989 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
7990 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
7991 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7992 
23) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
7993 
    input nets to instance:
7994 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
7995 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
7996 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
7997 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
7998 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
7999 
24) instance mips_core.decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
8000 
    input nets to instance:
8001 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
8002 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8003 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8004 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8005 
25) instance mips_core.decoder_pipe.idecoder.alu_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
8006 
    input nets to instance:
8007 
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
8008 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8009 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8010 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8011 
26) instance mips_core.decoder_pipe.idecoder.wb_mux[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
8012 
    input nets to instance:
8013 
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
8014 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8015 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8016 
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping</font>
8017 
27) instance mips_core.decoder_pipe.idecoder.wb_we[0] work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
8018 
    input nets to instance:
8019 
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
8020 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8021 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8022 
End of loops
8023 
Warning: Found 28 combinational loops!
8024 
         Each loop is reported with an instance in the loop
8025 
         and nets connected to that instance.
8026 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.BUS197[0]</font>
8027 
1) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.fsm_dly_1[0], output net "mips_core.BUS197[0]" in work.mips_sys(verilog)
8028 
    input nets to instance:
8029 
        net "mips_core.decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_sys(verilog)
8030 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8031 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8032 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[0]</font>
8033 
2) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[0], output net "mips_core.decoder_pipe.BUS2072[0]" in work.mips_sys(verilog)
8034 
    input nets to instance:
8035 
        net "mips_core.decoder_pipe.idecoder.N_1345" in work.mips_sys(verilog)
8036 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8037 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
8038 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
8039 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[1]</font>
8040 
3) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[1], output net "mips_core.decoder_pipe.BUS2072[1]" in work.mips_sys(verilog)
8041 
    input nets to instance:
8042 
        net "mips_core.decoder_pipe.idecoder.N_1346" in work.mips_sys(verilog)
8043 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8044 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8045 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2072[2]</font>
8046 
4) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.ext_ctl_1[2], output net "mips_core.decoder_pipe.BUS2072[2]" in work.mips_sys(verilog)
8047 
    input nets to instance:
8048 
        net "mips_core.decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_sys(verilog)
8049 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8050 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8051 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[0]</font>
8052 
5) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[0], output net "mips_core.decoder_pipe.BUS2110[0]" in work.mips_sys(verilog)
8053 
    input nets to instance:
8054 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_sys(verilog)
8055 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8056 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8057 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2110[1]</font>
8058 
6) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.rd_sel_1[1], output net "mips_core.decoder_pipe.BUS2110[1]" in work.mips_sys(verilog)
8059 
    input nets to instance:
8060 
        net "mips_core.decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_sys(verilog)
8061 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8062 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
8063 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
8064 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[0]</font>
8065 
7) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[0], output net "mips_core.decoder_pipe.BUS2056[0]" in work.mips_sys(verilog)
8066 
    input nets to instance:
8067 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_sys(verilog)
8068 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8069 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8070 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[1]</font>
8071 
8) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[1], output net "mips_core.decoder_pipe.BUS2056[1]" in work.mips_sys(verilog)
8072 
    input nets to instance:
8073 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_sys(verilog)
8074 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8075 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8076 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2056[2]</font>
8077 
9) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.cmp_ctl_1[2], output net "mips_core.decoder_pipe.BUS2056[2]" in work.mips_sys(verilog)
8078 
    input nets to instance:
8079 
        net "mips_core.decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_sys(verilog)
8080 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8081 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8082 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[0]</font>
8083 
10) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "mips_core.decoder_pipe.BUS2102[0]" in work.mips_sys(verilog)
8084 
    input nets to instance:
8085 
        net "mips_core.decoder_pipe.idecoder.N_1348" in work.mips_sys(verilog)
8086 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8087 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
8088 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
8089 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[1]</font>
8090 
11) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "mips_core.decoder_pipe.BUS2102[1]" in work.mips_sys(verilog)
8091 
    input nets to instance:
8092 
        net "mips_core.decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_sys(verilog)
8093 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8094 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8095 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2102[2]</font>
8096 
12) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "mips_core.decoder_pipe.BUS2102[2]" in work.mips_sys(verilog)
8097 
    input nets to instance:
8098 
        net "mips_core.decoder_pipe.idecoder.N_1232_i_0" in work.mips_sys(verilog)
8099 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8100 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
8101 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
8102 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[0]</font>
8103 
13) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[0], output net "mips_core.decoder_pipe.BUS2086[0]" in work.mips_sys(verilog)
8104 
    input nets to instance:
8105 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_sys(verilog)
8106 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8107 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8108 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2086[1]</font>
8109 
14) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxa_ctl_1[1], output net "mips_core.decoder_pipe.BUS2086[1]" in work.mips_sys(verilog)
8110 
    input nets to instance:
8111 
        net "mips_core.decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_sys(verilog)
8112 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8113 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
8114 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
8115 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[0]</font>
8116 
15) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[0], output net "mips_core.decoder_pipe.BUS2094[0]" in work.mips_sys(verilog)
8117 
    input nets to instance:
8118 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_sys(verilog)
8119 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8120 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8121 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2094[1]</font>
8122 
16) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.muxb_ctl_1[1], output net "mips_core.decoder_pipe.BUS2094[1]" in work.mips_sys(verilog)
8123 
    input nets to instance:
8124 
        net "mips_core.decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_sys(verilog)
8125 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8126 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
8127 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
8128 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[0]</font>
8129 
17) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[0], output net "mips_core.decoder_pipe.BUS2040[0]" in work.mips_sys(verilog)
8130 
    input nets to instance:
8131 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[0]" in work.mips_sys(verilog)
8132 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8133 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8134 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[1]</font>
8135 
18) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[1], output net "mips_core.decoder_pipe.BUS2040[1]" in work.mips_sys(verilog)
8136 
    input nets to instance:
8137 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[1]" in work.mips_sys(verilog)
8138 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8139 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8140 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[2]</font>
8141 
19) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[2], output net "mips_core.decoder_pipe.BUS2040[2]" in work.mips_sys(verilog)
8142 
    input nets to instance:
8143 
        net "mips_core.decoder_pipe.idecoder.N_1344" in work.mips_sys(verilog)
8144 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8145 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
8146 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
8147 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[3]</font>
8148 
20) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[3], output net "mips_core.decoder_pipe.BUS2040[3]" in work.mips_sys(verilog)
8149 
    input nets to instance:
8150 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[3]" in work.mips_sys(verilog)
8151 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8152 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
8153 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
8154 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2040[4]</font>
8155 
21) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_func_1[4], output net "mips_core.decoder_pipe.BUS2040[4]" in work.mips_sys(verilog)
8156 
    input nets to instance:
8157 
        net "mips_core.decoder_pipe.idecoder.alu_func_2[4]" in work.mips_sys(verilog)
8158 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8159 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8160 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[0]</font>
8161 
22) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[0], output net "mips_core.decoder_pipe.BUS2064[0]" in work.mips_sys(verilog)
8162 
    input nets to instance:
8163 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_sys(verilog)
8164 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8165 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_23" in work.mips_sys(verilog)
8166 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_20" in work.mips_sys(verilog)
8167 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[1]</font>
8168 
23) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[1], output net "mips_core.decoder_pipe.BUS2064[1]" in work.mips_sys(verilog)
8169 
    input nets to instance:
8170 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_sys(verilog)
8171 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8172 
        net "mips_core.decoder_pipe.idecoder.N_438" in work.mips_sys(verilog)
8173 
        net "mips_core.decoder_pipe.idecoder.fsm_dly373" in work.mips_sys(verilog)
8174 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[2]</font>
8175 
24) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[2], output net "mips_core.decoder_pipe.BUS2064[2]" in work.mips_sys(verilog)
8176 
    input nets to instance:
8177 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_sys(verilog)
8178 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8179 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_sys(verilog)
8180 
        net "mips_core.decoder_pipe.idecoder.un1_ins_i_15" in work.mips_sys(verilog)
8181 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2064[3]</font>
8182 
25) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.dmem_ctl_1[3], output net "mips_core.decoder_pipe.BUS2064[3]" in work.mips_sys(verilog)
8183 
    input nets to instance:
8184 
        net "mips_core.decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_sys(verilog)
8185 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8186 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8187 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2048[0]</font>
8188 
26) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.alu_we[0], output net "mips_core.decoder_pipe.BUS2048[0]" in work.mips_sys(verilog)
8189 
    input nets to instance:
8190 
        net "mips_core.decoder_pipe.idecoder.alu_we_1[0]" in work.mips_sys(verilog)
8191 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8192 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8193 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2118[0]</font>
8194 
27) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_mux[0], output net "mips_core.decoder_pipe.BUS2118[0]" in work.mips_sys(verilog)
8195 
    input nets to instance:
8196 
        net "mips_core.decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_sys(verilog)
8197 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8198 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8199 
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="e:\mips789\mips789\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1223605618> | Found combinational loop during mapping at net mips_core.decoder_pipe.BUS2126[0]</font>
8200 
28) instance work.mips_sys(verilog)-mips_core.decoder_pipe.idecoder.wb_we[0], output net "mips_core.decoder_pipe.BUS2126[0]" in work.mips_sys(verilog)
8201 
    input nets to instance:
8202 
        net "mips_core.decoder_pipe.idecoder.wb_we_1[0]" in work.mips_sys(verilog)
8203 
        net "mips_core.decoder_pipe.idecoder.un1_fsm_dly370" in work.mips_sys(verilog)
8204 
        net "mips_core.decoder_pipe.idecoder.N_436" in work.mips_sys(verilog)
8205 
End of loops

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