| 1 |
15 |
mcupro |
#
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| 2 |
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# Synplicity Verification Interface File
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| 3 |
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# Generated using Synplify-pro
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| 4 |
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#
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| 5 |
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# Copyright (c) 1996-2005 Synplicity, Inc.
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| 6 |
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# All rights reserved
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| 7 |
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#
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| 8 |
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| 9 |
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# Set logfile options
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| 10 |
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vif_set_result_file mips_sys.vlf
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| 11 |
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| 12 |
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# Set technology for TCL script
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| 13 |
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vif_set_technology -architecture FPGA -vendor Altera
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| 14 |
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| 15 |
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# RTL and technology files
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| 16 |
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vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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| 17 |
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vif_add_file -original -verilog ../../rtl/verilog/EXEC_stage.v
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| 18 |
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vif_add_file -original -verilog ../../rtl/verilog/RF_components.v
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| 19 |
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vif_add_file -original -verilog ../../rtl/verilog/RF_stage.v
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| 20 |
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vif_add_file -original -verilog ../../rtl/verilog/ctl_fsm.v
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| 21 |
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vif_add_file -original -verilog ../../rtl/verilog/decode_pipe.v
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| 22 |
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vif_add_file -original -verilog ../../rtl/verilog/dvc.v
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| 23 |
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vif_add_file -original -verilog ../../rtl/verilog/fifo.v
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| 24 |
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vif_add_file -original -verilog ../../rtl/verilog/forward.v
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| 25 |
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vif_add_file -original -verilog ../../rtl/verilog/mem_module.v
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| 26 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_core.v
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| 27 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_dvc.v
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| 28 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_sys.v
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| 29 |
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vif_add_file -original -verilog ../../rtl/verilog/mips_uart.v
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| 30 |
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vif_add_file -original -verilog ../../rtl/verilog/ram_module.v
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| 31 |
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vif_add_file -original -verilog ../../rtl/verilog/sim_ram.v
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| 32 |
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vif_add_file -original -verilog ../../rtl/verilog/ulit.v
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| 33 |
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vif_add_file -original -verilog ../../rtl/verilog/altera/fifo512_cyclone.v
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| 34 |
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vif_set_top_module -original -top mips_sys
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| 35 |
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| 36 |
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vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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| 37 |
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vif_add_file -translated -verilog mips_sys.vqm
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| 38 |
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vif_set_top_module -translated -top mips_sys
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| 39 |
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# Read FSM encoding
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| 40 |
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vif_set_fsm -fsm fsm_0
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| 41 |
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vif_set_fsmreg -original -fsm fsm_0 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[3:0]
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| 42 |
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vif_set_fsmreg -translated -fsm fsm_0 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[8:0]
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| 43 |
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vif_set_state_map -fsm fsm_0 -original "0000" -translated "000000001"
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| 44 |
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vif_set_state_map -fsm fsm_0 -original "0001" -translated "000000010"
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| 45 |
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vif_set_state_map -fsm fsm_0 -original "0010" -translated "000000100"
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| 46 |
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vif_set_state_map -fsm fsm_0 -original "0011" -translated "000001000"
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| 47 |
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vif_set_state_map -fsm fsm_0 -original "0100" -translated "000010000"
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| 48 |
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vif_set_state_map -fsm fsm_0 -original "0101" -translated "000100000"
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| 49 |
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vif_set_state_map -fsm fsm_0 -original "0110" -translated "001000000"
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| 50 |
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vif_set_state_map -fsm fsm_0 -original "0111" -translated "010000000"
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| 51 |
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vif_set_state_map -fsm fsm_0 -original "1000" -translated "100000000"
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| 52 |
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vif_set_fsm -fsm fsm_9
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| 53 |
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vif_set_fsmreg -original -fsm fsm_9 imips_dvc/iuart0/uart_rd_tak/ua_state[2:0]
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| 54 |
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vif_set_fsmreg -translated -fsm fsm_9 imips_dvc/iuart0/uart_rd_tak/ua_state[4:0]
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| 55 |
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vif_set_state_map -fsm fsm_9 -original "000" -translated "00001"
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| 56 |
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vif_set_state_map -fsm fsm_9 -original "001" -translated "00010"
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| 57 |
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vif_set_state_map -fsm fsm_9 -original "010" -translated "00100"
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| 58 |
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vif_set_state_map -fsm fsm_9 -original "011" -translated "01000"
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| 59 |
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vif_set_state_map -fsm fsm_9 -original "100" -translated "10000"
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| 60 |
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vif_set_fsm -fsm fsm_15
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| 61 |
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vif_set_fsmreg -original -fsm fsm_15 imips_dvc/iuart0/uart_txd/ua_state[2:0]
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| 62 |
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vif_set_fsmreg -translated -fsm fsm_15 imips_dvc/iuart0/uart_txd/ua_state[7:0]
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| 63 |
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vif_set_state_map -fsm fsm_15 -original "000" -translated "00000001"
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| 64 |
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vif_set_state_map -fsm fsm_15 -original "001" -translated "00000010"
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| 65 |
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vif_set_state_map -fsm fsm_15 -original "010" -translated "00000100"
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| 66 |
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vif_set_state_map -fsm fsm_15 -original "011" -translated "00001000"
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| 67 |
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vif_set_state_map -fsm fsm_15 -original "100" -translated "00010000"
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| 68 |
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vif_set_state_map -fsm fsm_15 -original "101" -translated "00100000"
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| 69 |
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vif_set_state_map -fsm fsm_15 -original "110" -translated "01000000"
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| 70 |
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vif_set_state_map -fsm fsm_15 -original "111" -translated "10000000"
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| 71 |
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| 72 |
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# Memory map points
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| 73 |
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| 74 |
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# SRL map points
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| 75 |
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| 76 |
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# Compiler constant registers
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| 77 |
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| 78 |
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# Compiler constant latches
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| 79 |
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| 80 |
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# Compiler RTL sequential redundancies
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| 81 |
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| 82 |
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# RTL sequential redundancies
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| 83 |
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vif_set_merge -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[0] mips_core/alu_pass0/r32_o[0]
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| 84 |
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vif_set_merge -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[1] mips_core/alu_pass0/r32_o[1]
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| 85 |
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vif_set_merge -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[32]
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| 86 |
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| 87 |
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# Technology sequential redundancies
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| 88 |
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| 89 |
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# Inversion map points
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| 90 |
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vif_set_map_point -register -inverted -original mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z
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| 91 |
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vif_set_map_point -register -inverted -original imips_dvc/iuart0/uart_rd_tak/ua_state[0] -translated imips_dvc/iuart0/uart_rd_tak/ua_state_i_0__Z
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| 92 |
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vif_set_map_point -register -inverted -original imips_dvc/iuart0/uart_txd/ua_state[0] -translated imips_dvc/iuart0/uart_txd/ua_state_i_0__Z
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| 93 |
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| 94 |
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# Port mappping and directions
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| 95 |
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| 96 |
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# Black box mapping
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| 97 |
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vif_set_black_box synplicity_altsyncram4_r_w
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| 98 |
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vif_set_black_box scfifo
|
| 99 |
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| 100 |
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vif_set_map_point -blackbox -original mips_core/iRF_stage/reg_bank/reg_bank/altsyncram -translated mips_core/iRF_stage/reg_bank/reg_bank.I_1
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| 101 |
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vif_set_map_point -blackbox -original mips_core/iRF_stage/reg_bank/reg_bank_1/altsyncram -translated mips_core/iRF_stage/reg_bank/reg_bank_1.I_1
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| 102 |
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vif_set_map_point -blackbox -original imips_dvc/iuart0/uart_txd/fifo/scfifo_component -translated imips_dvc/iuart0/uart_txd/fifo/scfifo_component
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| 103 |
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| 104 |
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# Other sequential cells, including multidimensional arrays
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| 105 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[7] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_7__Z
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| 106 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[6] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_6__Z
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| 107 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[5] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_5__Z
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| 108 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[4] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_4__Z
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| 109 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[3] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_3__Z
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| 110 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[2] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_2__Z
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| 111 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[1] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_1__Z
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| 112 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[0] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_0__Z
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| 113 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[15] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_15__Z
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| 114 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[14] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_14__Z
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| 115 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[13] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_13__Z
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| 116 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[12] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_12__Z
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| 117 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[11] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_11__Z
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| 118 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[10] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_10__Z
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| 119 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[9] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_9__Z
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| 120 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[8] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_8__Z
|
| 121 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[31] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_31__Z
|
| 122 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[30] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_30__Z
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| 123 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[29] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_29__Z
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| 124 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[28] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_28__Z
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| 125 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[27] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_27__Z
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| 126 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[26] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_26__Z
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| 127 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[25] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_25__Z
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| 128 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[24] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_24__Z
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| 129 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[23] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_23__Z
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| 130 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[22] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_22__Z
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| 131 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[21] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_21__Z
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| 132 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[20] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_20__Z
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| 133 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[19] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_19__Z
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| 134 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[18] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_18__Z
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| 135 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[17] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_17__Z
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| 136 |
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vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[16] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_16__Z
|
| 137 |
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vif_set_map_point -latch -original mips_core/decoder_pipe/idecoder/fsm_dly[2] -translated mips_core/decoder_pipe/idecoder/fsm_dly_1_2__Z
|
| 138 |
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vif_set_map_point -latch -original mips_core/decoder_pipe/idecoder/fsm_dly[1] -translated mips_core/decoder_pipe/idecoder/fsm_dly_1_1__Z
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| 139 |
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| 140 |
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# Constant Registers
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| 141 |
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vif_set_constant -original -1 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[5]
|
| 142 |
|
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vif_set_transparent -original 1 mips_core/iRF_stage/MIAN_FSM/iack
|
| 143 |
|
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vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[31]
|
| 144 |
|
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vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[30]
|
| 145 |
|
|
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[29]
|
| 146 |
|
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vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[28]
|
| 147 |
|
|
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[27]
|
| 148 |
|
|
vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[26]
|
| 149 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[31]
|
| 150 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[30]
|
| 151 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[29]
|
| 152 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[28]
|
| 153 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[27]
|
| 154 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[26]
|
| 155 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[25]
|
| 156 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[24]
|
| 157 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[23]
|
| 158 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[22]
|
| 159 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[21]
|
| 160 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[20]
|
| 161 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[19]
|
| 162 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[18]
|
| 163 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[17]
|
| 164 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[16]
|
| 165 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[15]
|
| 166 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[14]
|
| 167 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[13]
|
| 168 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[12]
|
| 169 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[11]
|
| 170 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[10]
|
| 171 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[9]
|
| 172 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[8]
|
| 173 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[7]
|
| 174 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[6]
|
| 175 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[5]
|
| 176 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[4]
|
| 177 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[3]
|
| 178 |
|
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vif_set_constant -original -1 imips_dvc/key2_addr[2]
|
| 179 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[1]
|
| 180 |
|
|
vif_set_constant -original -1 imips_dvc/key2_addr[0]
|
| 181 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[31]
|
| 182 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[30]
|
| 183 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[29]
|
| 184 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[28]
|
| 185 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[27]
|
| 186 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[26]
|
| 187 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[25]
|
| 188 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[24]
|
| 189 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[23]
|
| 190 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[22]
|
| 191 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[21]
|
| 192 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[20]
|
| 193 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[19]
|
| 194 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[18]
|
| 195 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[17]
|
| 196 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[16]
|
| 197 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[15]
|
| 198 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[14]
|
| 199 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[13]
|
| 200 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[12]
|
| 201 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[11]
|
| 202 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[10]
|
| 203 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[9]
|
| 204 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[8]
|
| 205 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[7]
|
| 206 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[6]
|
| 207 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[5]
|
| 208 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[4]
|
| 209 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[3]
|
| 210 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[2]
|
| 211 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[1]
|
| 212 |
|
|
vif_set_constant -original -1 imips_dvc/key1_addr[0]
|
| 213 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[31]
|
| 214 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[30]
|
| 215 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[29]
|
| 216 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[28]
|
| 217 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[27]
|
| 218 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[26]
|
| 219 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[25]
|
| 220 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[24]
|
| 221 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[23]
|
| 222 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[22]
|
| 223 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[21]
|
| 224 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[20]
|
| 225 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[19]
|
| 226 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[18]
|
| 227 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[17]
|
| 228 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[16]
|
| 229 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[15]
|
| 230 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[14]
|
| 231 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[13]
|
| 232 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[12]
|
| 233 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[11]
|
| 234 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[10]
|
| 235 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[9]
|
| 236 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[8]
|
| 237 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[7]
|
| 238 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[6]
|
| 239 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[5]
|
| 240 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[4]
|
| 241 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[3]
|
| 242 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[2]
|
| 243 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[1]
|
| 244 |
|
|
vif_set_constant -original -1 imips_dvc/tmr_addr[0]
|
| 245 |
|
|
|
| 246 |
|
|
# Retimed Registers
|
| 247 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/ctl_o[0] -translated mips_core/MEM_CTL/dmem_ctl_post/ctl_o_0__Z
|
| 248 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/ctl_o[1] -translated mips_core/MEM_CTL/dmem_ctl_post/ctl_o_1__Z
|
| 249 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/ctl_o[2] -translated mips_core/MEM_CTL/dmem_ctl_post/ctl_o_2__Z
|
| 250 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/ctl_o[3] -translated mips_core/MEM_CTL/dmem_ctl_post/ctl_o_3__Z
|
| 251 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[0] -translated mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o_0__Z
|
| 252 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[1] -translated mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o_1__Z
|
| 253 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/MIAN_FSM/delay_counter_Sreg0[3] -translated mips_core/iRF_stage/MIAN_FSM/delay_counter_Sreg0_3__Z
|
| 254 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/MIAN_FSM/delay_counter_Sreg0[5] -translated mips_core/iRF_stage/MIAN_FSM/delay_counter_Sreg0_5__Z
|
| 255 |
|
|
# Retimed registers from FSM not handled in VIF
|
| 256 |
|
|
//vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z
|
| 257 |
|
|
# Retimed registers from FSM not handled in VIF
|
| 258 |
|
|
//vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[6] -translated mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0_6__Z
|
| 259 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wren -translated mips_core/iRF_stage/reg_bank/r_wren_Z
|
| 260 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[0] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_0__Z
|
| 261 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[1] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_1__Z
|
| 262 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[2] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_2__Z
|
| 263 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[3] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_3__Z
|
| 264 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_a[4] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_a_4__Z
|
| 265 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[0] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_0__Z
|
| 266 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[1] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_1__Z
|
| 267 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[2] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_2__Z
|
| 268 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[3] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_3__Z
|
| 269 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_rdaddress_b[4] -translated mips_core/iRF_stage/reg_bank/r_rdaddress_b_4__Z
|
| 270 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[0] -translated mips_core/iRF_stage/reg_bank/r_data_0__Z
|
| 271 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[1] -translated mips_core/iRF_stage/reg_bank/r_data_1__Z
|
| 272 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[2] -translated mips_core/iRF_stage/reg_bank/r_data_2__Z
|
| 273 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[3] -translated mips_core/iRF_stage/reg_bank/r_data_3__Z
|
| 274 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[4] -translated mips_core/iRF_stage/reg_bank/r_data_4__Z
|
| 275 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[5] -translated mips_core/iRF_stage/reg_bank/r_data_5__Z
|
| 276 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[6] -translated mips_core/iRF_stage/reg_bank/r_data_6__Z
|
| 277 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[7] -translated mips_core/iRF_stage/reg_bank/r_data_7__Z
|
| 278 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[8] -translated mips_core/iRF_stage/reg_bank/r_data_8__Z
|
| 279 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[9] -translated mips_core/iRF_stage/reg_bank/r_data_9__Z
|
| 280 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[10] -translated mips_core/iRF_stage/reg_bank/r_data_10__Z
|
| 281 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[11] -translated mips_core/iRF_stage/reg_bank/r_data_11__Z
|
| 282 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[12] -translated mips_core/iRF_stage/reg_bank/r_data_12__Z
|
| 283 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[13] -translated mips_core/iRF_stage/reg_bank/r_data_13__Z
|
| 284 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[14] -translated mips_core/iRF_stage/reg_bank/r_data_14__Z
|
| 285 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[15] -translated mips_core/iRF_stage/reg_bank/r_data_15__Z
|
| 286 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[16] -translated mips_core/iRF_stage/reg_bank/r_data_16__Z
|
| 287 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[17] -translated mips_core/iRF_stage/reg_bank/r_data_17__Z
|
| 288 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[18] -translated mips_core/iRF_stage/reg_bank/r_data_18__Z
|
| 289 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[19] -translated mips_core/iRF_stage/reg_bank/r_data_19__Z
|
| 290 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[20] -translated mips_core/iRF_stage/reg_bank/r_data_20__Z
|
| 291 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[21] -translated mips_core/iRF_stage/reg_bank/r_data_21__Z
|
| 292 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[22] -translated mips_core/iRF_stage/reg_bank/r_data_22__Z
|
| 293 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[23] -translated mips_core/iRF_stage/reg_bank/r_data_23__Z
|
| 294 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[24] -translated mips_core/iRF_stage/reg_bank/r_data_24__Z
|
| 295 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[25] -translated mips_core/iRF_stage/reg_bank/r_data_25__Z
|
| 296 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[26] -translated mips_core/iRF_stage/reg_bank/r_data_26__Z
|
| 297 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[27] -translated mips_core/iRF_stage/reg_bank/r_data_27__Z
|
| 298 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[28] -translated mips_core/iRF_stage/reg_bank/r_data_28__Z
|
| 299 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[29] -translated mips_core/iRF_stage/reg_bank/r_data_29__Z
|
| 300 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[30] -translated mips_core/iRF_stage/reg_bank/r_data_30__Z
|
| 301 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_data[31] -translated mips_core/iRF_stage/reg_bank/r_data_31__Z
|
| 302 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[0] -translated mips_core/iRF_stage/reg_bank/r_wraddress_0__Z
|
| 303 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[1] -translated mips_core/iRF_stage/reg_bank/r_wraddress_1__Z
|
| 304 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[2] -translated mips_core/iRF_stage/reg_bank/r_wraddress_2__Z
|
| 305 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[3] -translated mips_core/iRF_stage/reg_bank/r_wraddress_3__Z
|
| 306 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iRF_stage/reg_bank/r_wraddress[4] -translated mips_core/iRF_stage/reg_bank/r_wraddress_4__Z
|
| 307 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/add1 -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/add1_Z
|
| 308 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/addop2 -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/addop2_Z
|
| 309 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/addnop2 -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/addnop2_Z
|
| 310 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/overflow -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/overflow_Z
|
| 311 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/sub_or_yn -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/sub_or_yn_Z
|
| 312 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged_Z
|
| 313 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op1_sign_reged -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op1_sign_reged_Z
|
| 314 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/start -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/start_Z
|
| 315 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/sign -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/sign_Z
|
| 316 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/mul -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/mul_Z
|
| 317 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/rdy -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/rdy_Z
|
| 318 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[0] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_0__Z
|
| 319 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[1] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_1__Z
|
| 320 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[2] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_2__Z
|
| 321 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[3] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_3__Z
|
| 322 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[4] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_4__Z
|
| 323 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[5] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_5__Z
|
| 324 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[6] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_6__Z
|
| 325 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[7] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_7__Z
|
| 326 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[8] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_8__Z
|
| 327 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[9] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_9__Z
|
| 328 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[10] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_10__Z
|
| 329 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[11] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_11__Z
|
| 330 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[12] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_12__Z
|
| 331 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[13] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_13__Z
|
| 332 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[14] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_14__Z
|
| 333 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[15] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_15__Z
|
| 334 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[16] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_16__Z
|
| 335 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[17] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_17__Z
|
| 336 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[18] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_18__Z
|
| 337 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[19] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_19__Z
|
| 338 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[20] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_20__Z
|
| 339 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[21] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_21__Z
|
| 340 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[22] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_22__Z
|
| 341 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[23] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_23__Z
|
| 342 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[24] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_24__Z
|
| 343 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[25] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_25__Z
|
| 344 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[26] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_26__Z
|
| 345 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[27] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_27__Z
|
| 346 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[28] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_28__Z
|
| 347 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[29] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_29__Z
|
| 348 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[30] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_30__Z
|
| 349 |
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[31] -translated mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged_31__Z
|
| 350 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[2] -translated mips_core/iexec_stage/pc_nxt/r32_o_2__Z
|
| 351 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[3] -translated mips_core/iexec_stage/pc_nxt/r32_o_3__Z
|
| 352 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[4] -translated mips_core/iexec_stage/pc_nxt/r32_o_4__Z
|
| 353 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[5] -translated mips_core/iexec_stage/pc_nxt/r32_o_5__Z
|
| 354 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[6] -translated mips_core/iexec_stage/pc_nxt/r32_o_6__Z
|
| 355 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[7] -translated mips_core/iexec_stage/pc_nxt/r32_o_7__Z
|
| 356 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[8] -translated mips_core/iexec_stage/pc_nxt/r32_o_8__Z
|
| 357 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[9] -translated mips_core/iexec_stage/pc_nxt/r32_o_9__Z
|
| 358 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[10] -translated mips_core/iexec_stage/pc_nxt/r32_o_10__Z
|
| 359 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[11] -translated mips_core/iexec_stage/pc_nxt/r32_o_11__Z
|
| 360 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[12] -translated mips_core/iexec_stage/pc_nxt/r32_o_12__Z
|
| 361 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[13] -translated mips_core/iexec_stage/pc_nxt/r32_o_13__Z
|
| 362 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[14] -translated mips_core/iexec_stage/pc_nxt/r32_o_14__Z
|
| 363 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[15] -translated mips_core/iexec_stage/pc_nxt/r32_o_15__Z
|
| 364 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[16] -translated mips_core/iexec_stage/pc_nxt/r32_o_16__Z
|
| 365 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[17] -translated mips_core/iexec_stage/pc_nxt/r32_o_17__Z
|
| 366 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[18] -translated mips_core/iexec_stage/pc_nxt/r32_o_18__Z
|
| 367 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[19] -translated mips_core/iexec_stage/pc_nxt/r32_o_19__Z
|
| 368 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[20] -translated mips_core/iexec_stage/pc_nxt/r32_o_20__Z
|
| 369 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[21] -translated mips_core/iexec_stage/pc_nxt/r32_o_21__Z
|
| 370 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[22] -translated mips_core/iexec_stage/pc_nxt/r32_o_22__Z
|
| 371 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[23] -translated mips_core/iexec_stage/pc_nxt/r32_o_23__Z
|
| 372 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[24] -translated mips_core/iexec_stage/pc_nxt/r32_o_24__Z
|
| 373 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[25] -translated mips_core/iexec_stage/pc_nxt/r32_o_25__Z
|
| 374 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[26] -translated mips_core/iexec_stage/pc_nxt/r32_o_26__Z
|
| 375 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[27] -translated mips_core/iexec_stage/pc_nxt/r32_o_27__Z
|
| 376 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[28] -translated mips_core/iexec_stage/pc_nxt/r32_o_28__Z
|
| 377 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[29] -translated mips_core/iexec_stage/pc_nxt/r32_o_29__Z
|
| 378 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[30] -translated mips_core/iexec_stage/pc_nxt/r32_o_30__Z
|
| 379 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[31] -translated mips_core/iexec_stage/pc_nxt/r32_o_31__Z
|
| 380 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[1] -translated mips_core/iexec_stage/pc_nxt/r32_o_1__Z
|
| 381 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/pc_nxt/r32_o[0] -translated mips_core/iexec_stage/pc_nxt/r32_o_0__Z
|
| 382 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[0] -translated mips_core/iexec_stage/spc/r32_o_0__Z
|
| 383 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[1] -translated mips_core/iexec_stage/spc/r32_o_1__Z
|
| 384 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[2] -translated mips_core/iexec_stage/spc/r32_o_2__Z
|
| 385 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[3] -translated mips_core/iexec_stage/spc/r32_o_3__Z
|
| 386 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[4] -translated mips_core/iexec_stage/spc/r32_o_4__Z
|
| 387 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[5] -translated mips_core/iexec_stage/spc/r32_o_5__Z
|
| 388 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[6] -translated mips_core/iexec_stage/spc/r32_o_6__Z
|
| 389 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[7] -translated mips_core/iexec_stage/spc/r32_o_7__Z
|
| 390 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[8] -translated mips_core/iexec_stage/spc/r32_o_8__Z
|
| 391 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[9] -translated mips_core/iexec_stage/spc/r32_o_9__Z
|
| 392 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[10] -translated mips_core/iexec_stage/spc/r32_o_10__Z
|
| 393 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[11] -translated mips_core/iexec_stage/spc/r32_o_11__Z
|
| 394 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[12] -translated mips_core/iexec_stage/spc/r32_o_12__Z
|
| 395 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[13] -translated mips_core/iexec_stage/spc/r32_o_13__Z
|
| 396 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[14] -translated mips_core/iexec_stage/spc/r32_o_14__Z
|
| 397 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[15] -translated mips_core/iexec_stage/spc/r32_o_15__Z
|
| 398 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[16] -translated mips_core/iexec_stage/spc/r32_o_16__Z
|
| 399 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[17] -translated mips_core/iexec_stage/spc/r32_o_17__Z
|
| 400 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[18] -translated mips_core/iexec_stage/spc/r32_o_18__Z
|
| 401 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[19] -translated mips_core/iexec_stage/spc/r32_o_19__Z
|
| 402 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[20] -translated mips_core/iexec_stage/spc/r32_o_20__Z
|
| 403 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[21] -translated mips_core/iexec_stage/spc/r32_o_21__Z
|
| 404 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[22] -translated mips_core/iexec_stage/spc/r32_o_22__Z
|
| 405 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[23] -translated mips_core/iexec_stage/spc/r32_o_23__Z
|
| 406 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[24] -translated mips_core/iexec_stage/spc/r32_o_24__Z
|
| 407 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[25] -translated mips_core/iexec_stage/spc/r32_o_25__Z
|
| 408 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[26] -translated mips_core/iexec_stage/spc/r32_o_26__Z
|
| 409 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[27] -translated mips_core/iexec_stage/spc/r32_o_27__Z
|
| 410 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[28] -translated mips_core/iexec_stage/spc/r32_o_28__Z
|
| 411 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[29] -translated mips_core/iexec_stage/spc/r32_o_29__Z
|
| 412 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[30] -translated mips_core/iexec_stage/spc/r32_o_30__Z
|
| 413 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/iexec_stage/spc/r32_o[31] -translated mips_core/iexec_stage/spc/r32_o_31__Z
|
| 414 |
|
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[2] -translated mips_core/alu_pass0/r32_o_2__Z
|
| 415 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[3] -translated mips_core/alu_pass0/r32_o_3__Z
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| 416 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[4] -translated mips_core/alu_pass0/r32_o_4__Z
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| 417 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[5] -translated mips_core/alu_pass0/r32_o_5__Z
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| 418 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[6] -translated mips_core/alu_pass0/r32_o_6__Z
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| 419 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[7] -translated mips_core/alu_pass0/r32_o_7__Z
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| 420 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[8] -translated mips_core/alu_pass0/r32_o_8__Z
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| 421 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[9] -translated mips_core/alu_pass0/r32_o_9__Z
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| 422 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[10] -translated mips_core/alu_pass0/r32_o_10__Z
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| 423 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[11] -translated mips_core/alu_pass0/r32_o_11__Z
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| 424 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[12] -translated mips_core/alu_pass0/r32_o_12__Z
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| 425 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[13] -translated mips_core/alu_pass0/r32_o_13__Z
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| 426 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[14] -translated mips_core/alu_pass0/r32_o_14__Z
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| 427 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[15] -translated mips_core/alu_pass0/r32_o_15__Z
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| 428 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[16] -translated mips_core/alu_pass0/r32_o_16__Z
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| 429 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[17] -translated mips_core/alu_pass0/r32_o_17__Z
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| 430 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[18] -translated mips_core/alu_pass0/r32_o_18__Z
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| 431 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[19] -translated mips_core/alu_pass0/r32_o_19__Z
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| 432 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[20] -translated mips_core/alu_pass0/r32_o_20__Z
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| 433 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[21] -translated mips_core/alu_pass0/r32_o_21__Z
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| 434 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[22] -translated mips_core/alu_pass0/r32_o_22__Z
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| 435 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[23] -translated mips_core/alu_pass0/r32_o_23__Z
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| 436 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[24] -translated mips_core/alu_pass0/r32_o_24__Z
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| 437 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[25] -translated mips_core/alu_pass0/r32_o_25__Z
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| 438 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[26] -translated mips_core/alu_pass0/r32_o_26__Z
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| 439 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[27] -translated mips_core/alu_pass0/r32_o_27__Z
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| 440 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[28] -translated mips_core/alu_pass0/r32_o_28__Z
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| 441 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[29] -translated mips_core/alu_pass0/r32_o_29__Z
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| 442 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[30] -translated mips_core/alu_pass0/r32_o_30__Z
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| 443 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass0/r32_o[31] -translated mips_core/alu_pass0/r32_o_31__Z
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| 444 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[0] -translated mips_core/alu_pass1/r32_o_0__Z
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| 445 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[1] -translated mips_core/alu_pass1/r32_o_1__Z
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| 446 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[2] -translated mips_core/alu_pass1/r32_o_2__Z
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| 447 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[3] -translated mips_core/alu_pass1/r32_o_3__Z
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| 448 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[4] -translated mips_core/alu_pass1/r32_o_4__Z
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| 449 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[5] -translated mips_core/alu_pass1/r32_o_5__Z
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| 450 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[6] -translated mips_core/alu_pass1/r32_o_6__Z
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| 451 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[7] -translated mips_core/alu_pass1/r32_o_7__Z
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| 452 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[8] -translated mips_core/alu_pass1/r32_o_8__Z
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| 453 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[9] -translated mips_core/alu_pass1/r32_o_9__Z
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| 454 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[10] -translated mips_core/alu_pass1/r32_o_10__Z
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| 455 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[11] -translated mips_core/alu_pass1/r32_o_11__Z
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| 456 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[12] -translated mips_core/alu_pass1/r32_o_12__Z
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| 457 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[13] -translated mips_core/alu_pass1/r32_o_13__Z
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| 458 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[14] -translated mips_core/alu_pass1/r32_o_14__Z
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| 459 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[15] -translated mips_core/alu_pass1/r32_o_15__Z
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| 460 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[16] -translated mips_core/alu_pass1/r32_o_16__Z
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| 461 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[17] -translated mips_core/alu_pass1/r32_o_17__Z
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| 462 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[18] -translated mips_core/alu_pass1/r32_o_18__Z
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| 463 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[19] -translated mips_core/alu_pass1/r32_o_19__Z
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| 464 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[20] -translated mips_core/alu_pass1/r32_o_20__Z
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| 465 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[21] -translated mips_core/alu_pass1/r32_o_21__Z
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| 466 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[22] -translated mips_core/alu_pass1/r32_o_22__Z
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| 467 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[23] -translated mips_core/alu_pass1/r32_o_23__Z
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| 468 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[24] -translated mips_core/alu_pass1/r32_o_24__Z
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| 469 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[25] -translated mips_core/alu_pass1/r32_o_25__Z
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| 470 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[26] -translated mips_core/alu_pass1/r32_o_26__Z
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| 471 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[27] -translated mips_core/alu_pass1/r32_o_27__Z
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| 472 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[28] -translated mips_core/alu_pass1/r32_o_28__Z
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| 473 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[29] -translated mips_core/alu_pass1/r32_o_29__Z
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| 474 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[30] -translated mips_core/alu_pass1/r32_o_30__Z
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| 475 |
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vif_set_sequential_verify -retimed -register -original mips_core/alu_pass1/r32_o[31] -translated mips_core/alu_pass1/r32_o_31__Z
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| 476 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[0] -translated mips_core/cop_data_reg/r32_o_0__Z
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| 477 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[1] -translated mips_core/cop_data_reg/r32_o_1__Z
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| 478 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[2] -translated mips_core/cop_data_reg/r32_o_2__Z
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| 479 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[3] -translated mips_core/cop_data_reg/r32_o_3__Z
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| 480 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[4] -translated mips_core/cop_data_reg/r32_o_4__Z
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| 481 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[5] -translated mips_core/cop_data_reg/r32_o_5__Z
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| 482 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[6] -translated mips_core/cop_data_reg/r32_o_6__Z
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| 483 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[7] -translated mips_core/cop_data_reg/r32_o_7__Z
|
| 484 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[8] -translated mips_core/cop_data_reg/r32_o_8__Z
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| 485 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[9] -translated mips_core/cop_data_reg/r32_o_9__Z
|
| 486 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[10] -translated mips_core/cop_data_reg/r32_o_10__Z
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| 487 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[11] -translated mips_core/cop_data_reg/r32_o_11__Z
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| 488 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[12] -translated mips_core/cop_data_reg/r32_o_12__Z
|
| 489 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[13] -translated mips_core/cop_data_reg/r32_o_13__Z
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| 490 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[14] -translated mips_core/cop_data_reg/r32_o_14__Z
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| 491 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[15] -translated mips_core/cop_data_reg/r32_o_15__Z
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| 492 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[16] -translated mips_core/cop_data_reg/r32_o_16__Z
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| 493 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[17] -translated mips_core/cop_data_reg/r32_o_17__Z
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| 494 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[18] -translated mips_core/cop_data_reg/r32_o_18__Z
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| 495 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[19] -translated mips_core/cop_data_reg/r32_o_19__Z
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| 496 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[20] -translated mips_core/cop_data_reg/r32_o_20__Z
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| 497 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[21] -translated mips_core/cop_data_reg/r32_o_21__Z
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| 498 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[22] -translated mips_core/cop_data_reg/r32_o_22__Z
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| 499 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[23] -translated mips_core/cop_data_reg/r32_o_23__Z
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| 500 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[24] -translated mips_core/cop_data_reg/r32_o_24__Z
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| 501 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[25] -translated mips_core/cop_data_reg/r32_o_25__Z
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| 502 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[26] -translated mips_core/cop_data_reg/r32_o_26__Z
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| 503 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[27] -translated mips_core/cop_data_reg/r32_o_27__Z
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| 504 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[28] -translated mips_core/cop_data_reg/r32_o_28__Z
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| 505 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[29] -translated mips_core/cop_data_reg/r32_o_29__Z
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| 506 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[30] -translated mips_core/cop_data_reg/r32_o_30__Z
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| 507 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_data_reg/r32_o[31] -translated mips_core/cop_data_reg/r32_o_31__Z
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| 508 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[0] -translated mips_core/cop_dout_reg/r32_o_0__Z
|
| 509 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[1] -translated mips_core/cop_dout_reg/r32_o_1__Z
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| 510 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[2] -translated mips_core/cop_dout_reg/r32_o_2__Z
|
| 511 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[3] -translated mips_core/cop_dout_reg/r32_o_3__Z
|
| 512 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[4] -translated mips_core/cop_dout_reg/r32_o_4__Z
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| 513 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[5] -translated mips_core/cop_dout_reg/r32_o_5__Z
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| 514 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[6] -translated mips_core/cop_dout_reg/r32_o_6__Z
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| 515 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[7] -translated mips_core/cop_dout_reg/r32_o_7__Z
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| 516 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[8] -translated mips_core/cop_dout_reg/r32_o_8__Z
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| 517 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[9] -translated mips_core/cop_dout_reg/r32_o_9__Z
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| 518 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[10] -translated mips_core/cop_dout_reg/r32_o_10__Z
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| 519 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[11] -translated mips_core/cop_dout_reg/r32_o_11__Z
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| 520 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[12] -translated mips_core/cop_dout_reg/r32_o_12__Z
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| 521 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[13] -translated mips_core/cop_dout_reg/r32_o_13__Z
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| 522 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[14] -translated mips_core/cop_dout_reg/r32_o_14__Z
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| 523 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[15] -translated mips_core/cop_dout_reg/r32_o_15__Z
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| 524 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[16] -translated mips_core/cop_dout_reg/r32_o_16__Z
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| 525 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[17] -translated mips_core/cop_dout_reg/r32_o_17__Z
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| 526 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[18] -translated mips_core/cop_dout_reg/r32_o_18__Z
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| 527 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[19] -translated mips_core/cop_dout_reg/r32_o_19__Z
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| 528 |
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vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[20] -translated mips_core/cop_dout_reg/r32_o_20__Z
|
| 529 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[21] -translated mips_core/cop_dout_reg/r32_o_21__Z
|
| 530 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[22] -translated mips_core/cop_dout_reg/r32_o_22__Z
|
| 531 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[23] -translated mips_core/cop_dout_reg/r32_o_23__Z
|
| 532 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[24] -translated mips_core/cop_dout_reg/r32_o_24__Z
|
| 533 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[25] -translated mips_core/cop_dout_reg/r32_o_25__Z
|
| 534 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[26] -translated mips_core/cop_dout_reg/r32_o_26__Z
|
| 535 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[27] -translated mips_core/cop_dout_reg/r32_o_27__Z
|
| 536 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[28] -translated mips_core/cop_dout_reg/r32_o_28__Z
|
| 537 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[29] -translated mips_core/cop_dout_reg/r32_o_29__Z
|
| 538 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[30] -translated mips_core/cop_dout_reg/r32_o_30__Z
|
| 539 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/cop_dout_reg/r32_o[31] -translated mips_core/cop_dout_reg/r32_o_31__Z
|
| 540 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U12/wb_we_o[0] -translated mips_core/decoder_pipe/pipereg/U12/wb_we_o_0__Z
|
| 541 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U18/wb_mux_ctl_o[0] -translated mips_core/decoder_pipe/pipereg/U18/wb_mux_ctl_o_0__Z
|
| 542 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U20/wb_we_o[0] -translated mips_core/decoder_pipe/pipereg/U20/wb_we_o_0__Z
|
| 543 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U21/wb_mux_ctl_o[0] -translated mips_core/decoder_pipe/pipereg/U21/wb_mux_ctl_o_0__Z
|
| 544 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U22/wb_we_o[0] -translated mips_core/decoder_pipe/pipereg/U22/wb_we_o_0__Z
|
| 545 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o[0] -translated mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o_0__Z
|
| 546 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o[1] -translated mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o_1__Z
|
| 547 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o[2] -translated mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o_2__Z
|
| 548 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o[3] -translated mips_core/decoder_pipe/pipereg/U9/dmem_ctl_o_3__Z
|
| 549 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[0] -translated mips_core/ext_reg/r32_o_0__Z
|
| 550 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[1] -translated mips_core/ext_reg/r32_o_1__Z
|
| 551 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[2] -translated mips_core/ext_reg/r32_o_2__Z
|
| 552 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[3] -translated mips_core/ext_reg/r32_o_3__Z
|
| 553 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[4] -translated mips_core/ext_reg/r32_o_4__Z
|
| 554 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[5] -translated mips_core/ext_reg/r32_o_5__Z
|
| 555 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[6] -translated mips_core/ext_reg/r32_o_6__Z
|
| 556 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[7] -translated mips_core/ext_reg/r32_o_7__Z
|
| 557 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[8] -translated mips_core/ext_reg/r32_o_8__Z
|
| 558 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[9] -translated mips_core/ext_reg/r32_o_9__Z
|
| 559 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[10] -translated mips_core/ext_reg/r32_o_10__Z
|
| 560 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[11] -translated mips_core/ext_reg/r32_o_11__Z
|
| 561 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[12] -translated mips_core/ext_reg/r32_o_12__Z
|
| 562 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[13] -translated mips_core/ext_reg/r32_o_13__Z
|
| 563 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[14] -translated mips_core/ext_reg/r32_o_14__Z
|
| 564 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[15] -translated mips_core/ext_reg/r32_o_15__Z
|
| 565 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[16] -translated mips_core/ext_reg/r32_o_16__Z
|
| 566 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[17] -translated mips_core/ext_reg/r32_o_17__Z
|
| 567 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[18] -translated mips_core/ext_reg/r32_o_18__Z
|
| 568 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[19] -translated mips_core/ext_reg/r32_o_19__Z
|
| 569 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[20] -translated mips_core/ext_reg/r32_o_20__Z
|
| 570 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[21] -translated mips_core/ext_reg/r32_o_21__Z
|
| 571 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[22] -translated mips_core/ext_reg/r32_o_22__Z
|
| 572 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[23] -translated mips_core/ext_reg/r32_o_23__Z
|
| 573 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[24] -translated mips_core/ext_reg/r32_o_24__Z
|
| 574 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[25] -translated mips_core/ext_reg/r32_o_25__Z
|
| 575 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[26] -translated mips_core/ext_reg/r32_o_26__Z
|
| 576 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[27] -translated mips_core/ext_reg/r32_o_27__Z
|
| 577 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[28] -translated mips_core/ext_reg/r32_o_28__Z
|
| 578 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[29] -translated mips_core/ext_reg/r32_o_29__Z
|
| 579 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[30] -translated mips_core/ext_reg/r32_o_30__Z
|
| 580 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/ext_reg/r32_o[31] -translated mips_core/ext_reg/r32_o_31__Z
|
| 581 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[0] -translated mips_core/iforward/fw_reg_rns/q_0__Z
|
| 582 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[1] -translated mips_core/iforward/fw_reg_rns/q_1__Z
|
| 583 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[2] -translated mips_core/iforward/fw_reg_rns/q_2__Z
|
| 584 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[3] -translated mips_core/iforward/fw_reg_rns/q_3__Z
|
| 585 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rns/q[4] -translated mips_core/iforward/fw_reg_rns/q_4__Z
|
| 586 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[0] -translated mips_core/iforward/fw_reg_rnt/q_0__Z
|
| 587 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[1] -translated mips_core/iforward/fw_reg_rnt/q_1__Z
|
| 588 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[2] -translated mips_core/iforward/fw_reg_rnt/q_2__Z
|
| 589 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[3] -translated mips_core/iforward/fw_reg_rnt/q_3__Z
|
| 590 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/iforward/fw_reg_rnt/q[4] -translated mips_core/iforward/fw_reg_rnt/q_4__Z
|
| 591 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[0] -translated mips_core/pc/r32_o_0__Z
|
| 592 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[1] -translated mips_core/pc/r32_o_1__Z
|
| 593 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[2] -translated mips_core/pc/r32_o_2__Z
|
| 594 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[3] -translated mips_core/pc/r32_o_3__Z
|
| 595 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[4] -translated mips_core/pc/r32_o_4__Z
|
| 596 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[5] -translated mips_core/pc/r32_o_5__Z
|
| 597 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[6] -translated mips_core/pc/r32_o_6__Z
|
| 598 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[7] -translated mips_core/pc/r32_o_7__Z
|
| 599 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[8] -translated mips_core/pc/r32_o_8__Z
|
| 600 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[9] -translated mips_core/pc/r32_o_9__Z
|
| 601 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[10] -translated mips_core/pc/r32_o_10__Z
|
| 602 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[11] -translated mips_core/pc/r32_o_11__Z
|
| 603 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[12] -translated mips_core/pc/r32_o_12__Z
|
| 604 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[13] -translated mips_core/pc/r32_o_13__Z
|
| 605 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[14] -translated mips_core/pc/r32_o_14__Z
|
| 606 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[15] -translated mips_core/pc/r32_o_15__Z
|
| 607 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[16] -translated mips_core/pc/r32_o_16__Z
|
| 608 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[17] -translated mips_core/pc/r32_o_17__Z
|
| 609 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[18] -translated mips_core/pc/r32_o_18__Z
|
| 610 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[19] -translated mips_core/pc/r32_o_19__Z
|
| 611 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[20] -translated mips_core/pc/r32_o_20__Z
|
| 612 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[21] -translated mips_core/pc/r32_o_21__Z
|
| 613 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[22] -translated mips_core/pc/r32_o_22__Z
|
| 614 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[23] -translated mips_core/pc/r32_o_23__Z
|
| 615 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[24] -translated mips_core/pc/r32_o_24__Z
|
| 616 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[25] -translated mips_core/pc/r32_o_25__Z
|
| 617 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[26] -translated mips_core/pc/r32_o_26__Z
|
| 618 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[27] -translated mips_core/pc/r32_o_27__Z
|
| 619 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[28] -translated mips_core/pc/r32_o_28__Z
|
| 620 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[29] -translated mips_core/pc/r32_o_29__Z
|
| 621 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[30] -translated mips_core/pc/r32_o_30__Z
|
| 622 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/pc/r32_o[31] -translated mips_core/pc/r32_o_31__Z
|
| 623 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[0] -translated mips_core/rnd_pass0/r5_o_0__Z
|
| 624 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[1] -translated mips_core/rnd_pass0/r5_o_1__Z
|
| 625 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[2] -translated mips_core/rnd_pass0/r5_o_2__Z
|
| 626 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[3] -translated mips_core/rnd_pass0/r5_o_3__Z
|
| 627 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass0/r5_o[4] -translated mips_core/rnd_pass0/r5_o_4__Z
|
| 628 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[0] -translated mips_core/rnd_pass1/r5_o_0__Z
|
| 629 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[1] -translated mips_core/rnd_pass1/r5_o_1__Z
|
| 630 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[2] -translated mips_core/rnd_pass1/r5_o_2__Z
|
| 631 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[3] -translated mips_core/rnd_pass1/r5_o_3__Z
|
| 632 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass1/r5_o[4] -translated mips_core/rnd_pass1/r5_o_4__Z
|
| 633 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[0] -translated mips_core/rnd_pass2/r5_o_0__Z
|
| 634 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[1] -translated mips_core/rnd_pass2/r5_o_1__Z
|
| 635 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[2] -translated mips_core/rnd_pass2/r5_o_2__Z
|
| 636 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[3] -translated mips_core/rnd_pass2/r5_o_3__Z
|
| 637 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rnd_pass2/r5_o[4] -translated mips_core/rnd_pass2/r5_o_4__Z
|
| 638 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[0] -translated mips_core/rs_reg/r32_o_0__Z
|
| 639 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[1] -translated mips_core/rs_reg/r32_o_1__Z
|
| 640 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[2] -translated mips_core/rs_reg/r32_o_2__Z
|
| 641 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[3] -translated mips_core/rs_reg/r32_o_3__Z
|
| 642 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[4] -translated mips_core/rs_reg/r32_o_4__Z
|
| 643 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[5] -translated mips_core/rs_reg/r32_o_5__Z
|
| 644 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[6] -translated mips_core/rs_reg/r32_o_6__Z
|
| 645 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[7] -translated mips_core/rs_reg/r32_o_7__Z
|
| 646 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[8] -translated mips_core/rs_reg/r32_o_8__Z
|
| 647 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[9] -translated mips_core/rs_reg/r32_o_9__Z
|
| 648 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[10] -translated mips_core/rs_reg/r32_o_10__Z
|
| 649 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[11] -translated mips_core/rs_reg/r32_o_11__Z
|
| 650 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[12] -translated mips_core/rs_reg/r32_o_12__Z
|
| 651 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[13] -translated mips_core/rs_reg/r32_o_13__Z
|
| 652 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[14] -translated mips_core/rs_reg/r32_o_14__Z
|
| 653 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[15] -translated mips_core/rs_reg/r32_o_15__Z
|
| 654 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[16] -translated mips_core/rs_reg/r32_o_16__Z
|
| 655 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[17] -translated mips_core/rs_reg/r32_o_17__Z
|
| 656 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[18] -translated mips_core/rs_reg/r32_o_18__Z
|
| 657 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[19] -translated mips_core/rs_reg/r32_o_19__Z
|
| 658 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[20] -translated mips_core/rs_reg/r32_o_20__Z
|
| 659 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[21] -translated mips_core/rs_reg/r32_o_21__Z
|
| 660 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[22] -translated mips_core/rs_reg/r32_o_22__Z
|
| 661 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[23] -translated mips_core/rs_reg/r32_o_23__Z
|
| 662 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[24] -translated mips_core/rs_reg/r32_o_24__Z
|
| 663 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[25] -translated mips_core/rs_reg/r32_o_25__Z
|
| 664 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[26] -translated mips_core/rs_reg/r32_o_26__Z
|
| 665 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[27] -translated mips_core/rs_reg/r32_o_27__Z
|
| 666 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[28] -translated mips_core/rs_reg/r32_o_28__Z
|
| 667 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[29] -translated mips_core/rs_reg/r32_o_29__Z
|
| 668 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[30] -translated mips_core/rs_reg/r32_o_30__Z
|
| 669 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rs_reg/r32_o[31] -translated mips_core/rs_reg/r32_o_31__Z
|
| 670 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[0] -translated mips_core/rt_reg/r32_o_0__Z
|
| 671 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[1] -translated mips_core/rt_reg/r32_o_1__Z
|
| 672 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[2] -translated mips_core/rt_reg/r32_o_2__Z
|
| 673 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[3] -translated mips_core/rt_reg/r32_o_3__Z
|
| 674 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[4] -translated mips_core/rt_reg/r32_o_4__Z
|
| 675 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[5] -translated mips_core/rt_reg/r32_o_5__Z
|
| 676 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[6] -translated mips_core/rt_reg/r32_o_6__Z
|
| 677 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[7] -translated mips_core/rt_reg/r32_o_7__Z
|
| 678 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[8] -translated mips_core/rt_reg/r32_o_8__Z
|
| 679 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[9] -translated mips_core/rt_reg/r32_o_9__Z
|
| 680 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[10] -translated mips_core/rt_reg/r32_o_10__Z
|
| 681 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[11] -translated mips_core/rt_reg/r32_o_11__Z
|
| 682 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[12] -translated mips_core/rt_reg/r32_o_12__Z
|
| 683 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[13] -translated mips_core/rt_reg/r32_o_13__Z
|
| 684 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[14] -translated mips_core/rt_reg/r32_o_14__Z
|
| 685 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[15] -translated mips_core/rt_reg/r32_o_15__Z
|
| 686 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[16] -translated mips_core/rt_reg/r32_o_16__Z
|
| 687 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[17] -translated mips_core/rt_reg/r32_o_17__Z
|
| 688 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[18] -translated mips_core/rt_reg/r32_o_18__Z
|
| 689 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[19] -translated mips_core/rt_reg/r32_o_19__Z
|
| 690 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[20] -translated mips_core/rt_reg/r32_o_20__Z
|
| 691 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[21] -translated mips_core/rt_reg/r32_o_21__Z
|
| 692 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[22] -translated mips_core/rt_reg/r32_o_22__Z
|
| 693 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[23] -translated mips_core/rt_reg/r32_o_23__Z
|
| 694 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[24] -translated mips_core/rt_reg/r32_o_24__Z
|
| 695 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[25] -translated mips_core/rt_reg/r32_o_25__Z
|
| 696 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[26] -translated mips_core/rt_reg/r32_o_26__Z
|
| 697 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[27] -translated mips_core/rt_reg/r32_o_27__Z
|
| 698 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[28] -translated mips_core/rt_reg/r32_o_28__Z
|
| 699 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[29] -translated mips_core/rt_reg/r32_o_29__Z
|
| 700 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[30] -translated mips_core/rt_reg/r32_o_30__Z
|
| 701 |
|
|
vif_set_sequential_verify -retimed -register -original mips_core/rt_reg/r32_o[31] -translated mips_core/rt_reg/r32_o_31__Z
|
| 702 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/iuart0/uart_rd_tak/rxq1 -translated imips_dvc/iuart0/uart_rd_tak/rxq1_Z
|
| 703 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/iuart0/rxd_rdy_hold_lw/q -translated imips_dvc/iuart0/rxd_rdy_hold_lw/q_Z
|
| 704 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/iuart0/uart_txd/txd -translated imips_dvc/iuart0/uart_txd/txd_Z
|
| 705 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[31] -translated imips_dvc/mips_tmr0/s_cntr_31__Z
|
| 706 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[30] -translated imips_dvc/mips_tmr0/s_cntr_30__Z
|
| 707 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[29] -translated imips_dvc/mips_tmr0/s_cntr_29__Z
|
| 708 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[28] -translated imips_dvc/mips_tmr0/s_cntr_28__Z
|
| 709 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[27] -translated imips_dvc/mips_tmr0/s_cntr_27__Z
|
| 710 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[26] -translated imips_dvc/mips_tmr0/s_cntr_26__Z
|
| 711 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[25] -translated imips_dvc/mips_tmr0/s_cntr_25__Z
|
| 712 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[24] -translated imips_dvc/mips_tmr0/s_cntr_24__Z
|
| 713 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[23] -translated imips_dvc/mips_tmr0/s_cntr_23__Z
|
| 714 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[22] -translated imips_dvc/mips_tmr0/s_cntr_22__Z
|
| 715 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[21] -translated imips_dvc/mips_tmr0/s_cntr_21__Z
|
| 716 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[20] -translated imips_dvc/mips_tmr0/s_cntr_20__Z
|
| 717 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[19] -translated imips_dvc/mips_tmr0/s_cntr_19__Z
|
| 718 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[18] -translated imips_dvc/mips_tmr0/s_cntr_18__Z
|
| 719 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[17] -translated imips_dvc/mips_tmr0/s_cntr_17__Z
|
| 720 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[16] -translated imips_dvc/mips_tmr0/s_cntr_16__Z
|
| 721 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[15] -translated imips_dvc/mips_tmr0/s_cntr_15__Z
|
| 722 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[14] -translated imips_dvc/mips_tmr0/s_cntr_14__Z
|
| 723 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[13] -translated imips_dvc/mips_tmr0/s_cntr_13__Z
|
| 724 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[12] -translated imips_dvc/mips_tmr0/s_cntr_12__Z
|
| 725 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[11] -translated imips_dvc/mips_tmr0/s_cntr_11__Z
|
| 726 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[10] -translated imips_dvc/mips_tmr0/s_cntr_10__Z
|
| 727 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[9] -translated imips_dvc/mips_tmr0/s_cntr_9__Z
|
| 728 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[8] -translated imips_dvc/mips_tmr0/s_cntr_8__Z
|
| 729 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[7] -translated imips_dvc/mips_tmr0/s_cntr_7__Z
|
| 730 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[6] -translated imips_dvc/mips_tmr0/s_cntr_6__Z
|
| 731 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[5] -translated imips_dvc/mips_tmr0/s_cntr_5__Z
|
| 732 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[4] -translated imips_dvc/mips_tmr0/s_cntr_4__Z
|
| 733 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[3] -translated imips_dvc/mips_tmr0/s_cntr_3__Z
|
| 734 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[2] -translated imips_dvc/mips_tmr0/s_cntr_2__Z
|
| 735 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[1] -translated imips_dvc/mips_tmr0/s_cntr_1__Z
|
| 736 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/mips_tmr0/s_cntr[0] -translated imips_dvc/mips_tmr0/s_cntr_0__Z
|
| 737 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/r_key1 -translated imips_dvc/r_key1_Z
|
| 738 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/r_key2 -translated imips_dvc/r_key2_Z
|
| 739 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[0] -translated imips_dvc/dout_0__Z
|
| 740 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[1] -translated imips_dvc/dout_1__Z
|
| 741 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[2] -translated imips_dvc/dout_2__Z
|
| 742 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[3] -translated imips_dvc/dout_3__Z
|
| 743 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[4] -translated imips_dvc/dout_4__Z
|
| 744 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[5] -translated imips_dvc/dout_5__Z
|
| 745 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[6] -translated imips_dvc/dout_6__Z
|
| 746 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[7] -translated imips_dvc/dout_7__Z
|
| 747 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[8] -translated imips_dvc/dout_8__Z
|
| 748 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[9] -translated imips_dvc/dout_9__Z
|
| 749 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[10] -translated imips_dvc/dout_10__Z
|
| 750 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[11] -translated imips_dvc/dout_11__Z
|
| 751 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[12] -translated imips_dvc/dout_12__Z
|
| 752 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[13] -translated imips_dvc/dout_13__Z
|
| 753 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[14] -translated imips_dvc/dout_14__Z
|
| 754 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[15] -translated imips_dvc/dout_15__Z
|
| 755 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[16] -translated imips_dvc/dout_16__Z
|
| 756 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[17] -translated imips_dvc/dout_17__Z
|
| 757 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[18] -translated imips_dvc/dout_18__Z
|
| 758 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[19] -translated imips_dvc/dout_19__Z
|
| 759 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[20] -translated imips_dvc/dout_20__Z
|
| 760 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[21] -translated imips_dvc/dout_21__Z
|
| 761 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[22] -translated imips_dvc/dout_22__Z
|
| 762 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[23] -translated imips_dvc/dout_23__Z
|
| 763 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[24] -translated imips_dvc/dout_24__Z
|
| 764 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[25] -translated imips_dvc/dout_25__Z
|
| 765 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[26] -translated imips_dvc/dout_26__Z
|
| 766 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[27] -translated imips_dvc/dout_27__Z
|
| 767 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[28] -translated imips_dvc/dout_28__Z
|
| 768 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[29] -translated imips_dvc/dout_29__Z
|
| 769 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[30] -translated imips_dvc/dout_30__Z
|
| 770 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/dout[31] -translated imips_dvc/dout_31__Z
|
| 771 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[0] -translated imips_dvc/lcd_data_0__Z
|
| 772 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[1] -translated imips_dvc/lcd_data_1__Z
|
| 773 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[2] -translated imips_dvc/lcd_data_2__Z
|
| 774 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[3] -translated imips_dvc/lcd_data_3__Z
|
| 775 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[4] -translated imips_dvc/lcd_data_4__Z
|
| 776 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[5] -translated imips_dvc/lcd_data_5__Z
|
| 777 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[6] -translated imips_dvc/lcd_data_6__Z
|
| 778 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/lcd_data[7] -translated imips_dvc/lcd_data_7__Z
|
| 779 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/rr_key2 -translated imips_dvc/rr_key2_Z
|
| 780 |
|
|
vif_set_sequential_verify -retimed -register -original imips_dvc/rr_key1 -translated imips_dvc/rr_key1_Z
|
| 781 |
|
|
|
| 782 |
|
|
# Altera MAC annotations
|
| 783 |
|
|
|
