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mcupro |
#
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# Synplicity Verification Interface File
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# Generated using Synplify-pro
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#
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# Copyright (c) 1996-2005 Synplicity, Inc.
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# All rights reserved
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#
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# Set logfile options
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vif_set_result_file r5_reg_cls.vlf
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# Set technology for TCL script
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vif_set_technology -architecture FPGA -vendor Altera
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# RTL and technology files
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vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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vif_add_file -original -verilog ../../rtl/verilog/ctl_fsm.v
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vif_add_file -original -verilog ../../rtl/verilog/decode_pipe.v
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vif_add_file -original -verilog ../../rtl/verilog/dvc.v
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vif_add_file -original -verilog ../../rtl/verilog/EXEC_stage.v
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vif_add_file -original -verilog ../../rtl/verilog/fifo.v
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vif_add_file -original -verilog ../../rtl/verilog/forward.v
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vif_add_file -original -verilog ../../rtl/verilog/mem_module.v
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vif_add_file -original -verilog ../../rtl/verilog/mips_core.v
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vif_add_file -original -verilog ../../rtl/verilog/mips_dvc.v
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vif_add_file -original -verilog ../../rtl/verilog/mips_sys.v
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vif_add_file -original -verilog ../../rtl/verilog/mips_uart.v
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vif_add_file -original -verilog ../../rtl/verilog/ram_module.v
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vif_add_file -original -verilog ../../rtl/verilog/RF_components.v
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vif_add_file -original -verilog ../../rtl/verilog/RF_stage.v
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vif_add_file -original -verilog ../../rtl/verilog/sim_ram.v
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vif_add_file -original -verilog ../../rtl/verilog/tools.v
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vif_set_top_module -original -top r5_reg_cls
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vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
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vif_add_file -translated -verilog r5_reg_cls.vqm
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vif_set_top_module -translated -top r5_reg_cls
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# Read FSM encoding
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# Memory map points
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# SRL map points
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# Compiler constant registers
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# Compiler constant latches
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# Compiler RTL sequential redundancies
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# RTL sequential redundancies
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# Technology sequential redundancies
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# Inversion map points
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# Port mappping and directions
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# Black box mapping
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# Other sequential cells, including multidimensional arrays
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# Constant Registers
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# Retimed Registers
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# Altera MAC annotations
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