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[/] [mips789/] [tags/] [arelease/] [verilog/] [device/] [uart_ff.v] - Blame information for rev 36

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/////////////////////////////////////////////////////////////////////
////  Author: Zhangfeifei                                        ////
////                                                             ////
////  Advance Test Technology Laboratory,                        ////
////  Institute of Computing Technology,                         ////
////  Chinese Academy of Sciences                                ////
////                                                             ////
////  If you encountered any problem, please contact :           ////
////  Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org    ////
////  Tel: +86-10-6256 5533 ext. 5673                            ////
////                                                             ////
////  Downloaded from:                                           ////
////     http://www.opencores.org/pdownloads.cgi/list/ucore      ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2005-2006 Zhangfeifei                         ////
////                         zhangfeifei@ict.ac.cn               ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// Please let the author know if it is used                    ////
//// for commercial purpose.                                     //// 
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Date of Creation: 2005.12.3                                 ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
//// Description: tx module of the uart module,data format is    ////
////              8bits data,1 bits stop bit,and no parity check ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
module uart_rxd(
                clk_i,rst_i,//system signal
                rxd_i,//serial data in
                rdy_o,data_o //data ready and parallel data out signal
                );
  parameter // state difinition
     STA_IDDLE = 0,
     STA_CHECK_START_BIT = 1,
     STA_RECIVE = 2;
 
  input clk_i;
  input rst_i;
  input rxd_i;
 
  output rdy_o;
  output [7:0] data_o;
 
  reg rdy_o;
  reg [7:0] data_o;
 
  reg [7:0] rsr;//reciving shift register
  reg [3:0] num_of_rec;
 
  reg [1:0] reg_sta;
 
  //the counter to count the clk in
  reg [3:0] count;
  reg count_c;//the carry of count
 
  always @(posedge clk_i or negedge rst_i)
  begin
    if(~rst_i)
    begin
      data_o     <= 8'bx;
      rdy_o      <= 1'b0;
 
      rsr        <= 8'bx;
      num_of_rec <= 3'bx;
      count      <= 4'bx;
      count_c    <= 1'bx;
 
      reg_sta    <= STA_IDDLE;
    end
    else begin
      case (reg_sta)
        STA_IDDLE:
        begin
          num_of_rec <= 3'd0;
          count      <= 4'd0;
          rdy_o      <= 1'b0;
          if(!rxd_i)
            reg_sta  <= STA_CHECK_START_BIT;//recive a start bit
          else
            reg_sta  <= STA_IDDLE;
        end
        STA_CHECK_START_BIT:
        begin
          count      <= count +1;
 
          if(count[3])
          begin
            //has passed 8 clk and rxd_i is still zero,then start bit has been confirmed
            if(!rxd_i)
              reg_sta <= STA_RECIVE;
            else
              reg_sta <= STA_IDDLE;
          end
          else reg_sta <= STA_CHECK_START_BIT;
        end
        STA_RECIVE:
        begin
          {count_c,count} <= count +1;
          //has passed 16 clk after the last bit has been checked,sampling a bit
          if(count_c)
          begin
            if(num_of_rec <=3'd7)
            begin //sampling the reciveed bit
              rsr        <= {rxd_i,rsr[7:1]};
              num_of_rec <= num_of_rec +1;
              reg_sta    <= STA_RECIVE;
            end
            else begin//sampling the stop bit
              if(rxd_i)//if stop bit exist
              begin
                  data_o  <= rsr;
                  rdy_o   <= 1'b1;
              end
              reg_sta    <= STA_IDDLE;
            end
          end
        end
      endcase
    end
  end
endmodule
 
/////////////////////////////////////////////////////////////////////
////  Author: Zhangfeifei                                        ////
////                                                             ////
////  Advance Test Technology Laboratory,                        ////
////  Institute of Computing Technology,                         ////
////  Chinese Academy of Sciences                                ////
////                                                             ////
////  If you encountered any problem, please contact :           ////
////  Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org    ////
////  Tel: +86-10-6256 5533 ext. 5673                            ////
////                                                             ////
////  Downloaded from:                                           ////
////     http://www.opencores.org/pdownloads.cgi/list/ucore      ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2005-2006 Zhangfeifei                         ////
////                         zhangfeifei@ict.ac.cn               ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// Please let the author know if it is used                    ////
//// for commercial purpose.                                     //// 
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Date of Creation: 2005.12.3                                 ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
//// Description: tx module of the uart module,data format is    ////
////              8bits data,1 bits stop bit,and no parity check ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
 
module uart_txd(
                clk_i,rst_i,//system signal
                data_i,wen_i,//parallel data in and enable signal
                txd_o,//serial data out
                tre_o// ready to transmit flag
                );
 
  parameter // state difinition
     STA_IDDLE = 0,
     STA_TRANS = 1,
     STA_FINISH = 2;
 
  input clk_i;
  input rst_i;
  input [7:0] data_i;
  input wen_i;
 
  output txd_o;
  output tre_o;
 
  reg txd_o;
  reg tre_o;
 
  reg [7:0] tsr;//transmitting shift register
  reg [3:0] num_of_trans;
 
  reg [1:0] reg_sta;
 
  //the counter to count the clk in
  reg [3:0] count;
  reg count_c;//the carry of count
 
  always @(posedge clk_i or negedge rst_i)
  begin
    if(~rst_i)
    begin
 
      tsr          <= 8'b0;
      txd_o        <= 1'b1;
      tre_o        <= 1'b1;
      num_of_trans <= 3'bx;
      count_c      <= 1'bx;
      count        <= 4'bx;
 
      reg_sta      <= STA_IDDLE;
    end
    else begin
 
      case(reg_sta)
        STA_IDDLE:
        begin
          num_of_trans    <= 3'd0;
          count           <= 4'd0;
 
          if(wen_i)
          begin
            tsr           <= data_i;
            tre_o         <= 1'b0;
            txd_o         <= 1'b0;// transmit the start bit 
            reg_sta       <= STA_TRANS;
          end
          else
            reg_sta       <= STA_IDDLE;
        end
        STA_TRANS:
        begin
          {count_c,count} <= count + 1;
 
          if(count_c)
          begin
            if(num_of_trans <=3'd7)
            begin
              //note ,when num_of_trans==7 ,we transmit the stop bit
              tsr          <= {1'b1,tsr[7:1]};
              txd_o        <= tsr[0];
              num_of_trans <= num_of_trans+1;
              reg_sta      <= STA_TRANS;
            end
            else begin
              txd_o        <= 1'b1;
              tre_o        <= 1'b1;
              reg_sta      <= STA_IDDLE;
            end
          end
        end
      endcase
    end
  end
 
 
endmodule
 
/////////////////////////////////////////////////////////////////////
////  Author: Zhangfeifei                                        ////
////                                                             ////
////  Advance Test Technology Laboratory,                        ////
////  Institute of Computing Technology,                         ////
////  Chinese Academy of Sciences                                ////
////                                                             ////
////  If you encountered any problem, please contact :           ////
////  Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org    ////
////  Tel: +86-10-6256 5533 ext. 5673                            ////
////                                                             ////
////  Downloaded from:                                           ////
////     http://www.opencores.org/pdownloads.cgi/list/ucore      ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2005-2006 Zhangfeifei                         ////
////                         zhangfeifei@ict.ac.cn               ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// Please let the author know if it is used                    ////
//// for commercial purpose.                                     //// 
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Date of Creation: 2005.12.3                                 ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
//// Description: clk divider of the uart module, provide a clk  ////
////              16times quick than the bitrate                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
 
module clk_div(
               clk_i,//100 MHZ clk in
               rst_i,
               clk_o//sampling clk out
               );
 
  parameter
    CLK_RATE = 25,//clk rate in MHZ
    BIT_RATE = 9600,
    DIV_NUM = 651;//CLK_RATE*1_000_000/(BIT_RATE*16);//DIV_NUM = 100M/(9600*16)=651 
 
  input clk_i;
  input rst_i;
  //output clk16_o;
  output clk_o;
 
  reg clk_o;
 
  reg [11:0] count;//the minial value of BIT_RATE is 9600 ,
                   //so the maxminal DIV_NUM is 2604,a length of 12 bit is big enough
  //reg [3:0] count16;//a counter has cycle of 16
  //reg count1;
 
  //assign clk16_o = count16[3];
  //assign clk1_o = count1;
 
  always @(posedge clk_i or negedge rst_i)
  begin
    if(~rst_i)
    begin
      //$display("BIT_RATE=%d,DIV_NUM=%d",BIT_RATE,DIV_NUM);
      clk_o <= 1'b1;
      //count16 <= 4'b1000;
      count <= 0;
    end
    else begin
      count <= count +1;
      if(count==DIV_NUM/2) clk_o <= 1'b0;
      else if(count==DIV_NUM)
      begin
        clk_o <= 1'b1;
        //count16 <= count16+1;
        count <= 0;
      end
    end
  end
 
endmodule
 
/////////////////////////////////////////////////////////////////////
////  Author: Liwei                                              ////
////                                                             ////
////                                                             ////
////  If you encountered any problem, please contact :           ////
////  Email: mcupro@yahoo.com.hk or mcupro@opencores.org         ////
////                                                             ////
////  Downloaded from:                                           ////
////     http://www.opencores.org/pdownloads.cgi/list/mips789    ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2007 Liwei                               ////
////                         mcupro@yahoo.com.hk                 ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// Please let the author know if it is used                    ////
//// for commercial purpose.                                     ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Date of Creation: 2007.8.1                                  ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
//// Description:                                                ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
module uart0 (clk,rst,rxd_ft,ser_rxd,txd_ld,din,rxd_rdy,ser_txd,txd_ldok,dout) ;
input clk;
wire clk;
input rst;
wire rst;
input rxd_ft;
wire rxd_ft;
input ser_rxd;
wire ser_rxd;
input txd_ld;
wire txd_ld;
input [7:0] din;
wire [7:0] din;
output rxd_rdy;
wire rxd_rdy;
output ser_txd;
wire ser_txd;
output txd_ldok;
wire txd_ldok;
output [7:0] dout;
wire [7:0] dout;
 
wire clk_uart;
wire w_rxd_rdy;
wire w_rxd_clr;
 
 
assign w_rxd_clr = ~(rst) & rxd_ft;
 
 
clk_div clk_div_ff
(
        .clk_i(clk),
        .clk_o(clk_uart),
        .rst_i(rst)
);
 
 
 
uart_rxd rxd_ff
(
        .clk_i(clk_uart),
        .data_o(dout),
        .rdy_o(w_rxd_rdy),
        .rst_i(rst),
        .rxd_i(ser_rxd)
);
 
 
 
rxd_rdy_hold rxd_rdy_hold_lw
(
        .clk(clk_uart),
        .clr(w_rxd_clr),
        .d(w_rxd_rdy),
        .q(rxd_rdy)
);
 
 
 
uart_txd txd_ff
(
        .clk_i(clk_uart),
        .data_i(din),
        .rst_i(rst),
        .tre_o(txd_ldok),
        .txd_o(ser_txd),
        .wen_i(txd_ld)
);
 
endmodule

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Subversion Repositories mips789

[/] [mips789/] [tags/] [arelease/] [verilog/] [device/] [uart_ff.v] - Blame information for rev 36

Line No.	Rev	Author	Line
1	2	mcupro	`/////////////////////////////////////////////////////////////////////`
2			`//// Author: Zhangfeifei ////`
3			`//// ////`
4			`//// Advance Test Technology Laboratory, ////`
5			`//// Institute of Computing Technology, ////`
6			`//// Chinese Academy of Sciences ////`
7			`//// ////`
8			`//// If you encountered any problem, please contact : ////`
9			`//// Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org ////`
10			`//// Tel: +86-10-6256 5533 ext. 5673 ////`
11			`//// ////`
12			`//// Downloaded from: ////`
13			`//// http://www.opencores.org/pdownloads.cgi/list/ucore ////`
14			`/////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2005-2006 Zhangfeifei ////`
17			`//// zhangfeifei@ict.ac.cn ////`
18			`//// ////`
19			`//// ////`
20			`//// This source file may be used and distributed freely without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and any derivative work contains the ////`
23			`//// original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// Please let the author know if it is used ////`
26			`//// for commercial purpose. ////`
27			`//// ////`
28			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
29			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
30			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
31			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
32			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
33			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
34			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
35			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
36			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
37			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
38			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
39			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
40			`//// POSSIBILITY OF SUCH DAMAGE. ////`
41			`//// ////`
42			`/////////////////////////////////////////////////////////////////////`
43			`//// ////`
44			`//// ////`
45			`//// Date of Creation: 2005.12.3 ////`
46			`//// ////`
47			`//// Version: 0.0.1 ////`
48			`//// ////`
49			`//// Description: tx module of the uart module,data format is ////`
50			`//// 8bits data,1 bits stop bit,and no parity check ////`
51			`//// ////`
52			`/////////////////////////////////////////////////////////////////////`
53			`//// ////`
54			`//// Change log: ////`
55			`//// ////`
56			`/////////////////////////////////////////////////////////////////////`
57			`module uart_rxd(`
58			`clk_i,rst_i,//system signal`
59			`rxd_i,//serial data in`
60			`rdy_o,data_o //data ready and parallel data out signal`
61			`);`
62			`parameter // state difinition`
63			`STA_IDDLE = 0,`
64			`STA_CHECK_START_BIT = 1,`
65			`STA_RECIVE = 2;`
66
67			`input clk_i;`
68			`input rst_i;`
69			`input rxd_i;`
70
71			`output rdy_o;`
72			`output [7:0] data_o;`
73
74			`reg rdy_o;`
75			`reg [7:0] data_o;`
76
77			`reg [7:0] rsr;//reciving shift register`
78			`reg [3:0] num_of_rec;`
79
80			`reg [1:0] reg_sta;`
81
82			`//the counter to count the clk in`
83			`reg [3:0] count;`
84			`reg count_c;//the carry of count`
85
86			`always @(posedge clk_i or negedge rst_i)`
87			`begin`
88			`if(~rst_i)`
89			`begin`
90			`data_o <= 8'bx;`
91			`rdy_o <= 1'b0;`
92
93			`rsr <= 8'bx;`
94			`num_of_rec <= 3'bx;`
95			`count <= 4'bx;`
96			`count_c <= 1'bx;`
97
98			`reg_sta <= STA_IDDLE;`
99			`end`
100			`else begin`
101			`case (reg_sta)`
102			`STA_IDDLE:`
103			`begin`
104			`num_of_rec <= 3'd0;`
105			`count <= 4'd0;`
106			`rdy_o <= 1'b0;`
107			`if(!rxd_i)`
108			`reg_sta <= STA_CHECK_START_BIT;//recive a start bit`
109			`else`
110			`reg_sta <= STA_IDDLE;`
111			`end`
112			`STA_CHECK_START_BIT:`
113			`begin`
114			`count <= count +1;`
115
116			`if(count[3])`
117			`begin`
118			`//has passed 8 clk and rxd_i is still zero,then start bit has been confirmed`
119			`if(!rxd_i)`
120			`reg_sta <= STA_RECIVE;`
121			`else`
122			`reg_sta <= STA_IDDLE;`
123			`end`
124			`else reg_sta <= STA_CHECK_START_BIT;`
125			`end`
126			`STA_RECIVE:`
127			`begin`
128			`{count_c,count} <= count +1;`
129			`//has passed 16 clk after the last bit has been checked,sampling a bit`
130			`if(count_c)`
131			`begin`
132			`if(num_of_rec <=3'd7)`
133			`begin //sampling the reciveed bit`
134			`rsr <= {rxd_i,rsr[7:1]};`
135			`num_of_rec <= num_of_rec +1;`
136			`reg_sta <= STA_RECIVE;`
137			`end`
138			`else begin//sampling the stop bit`
139			`if(rxd_i)//if stop bit exist`
140			`begin`
141			`data_o <= rsr;`
142			`rdy_o <= 1'b1;`
143			`end`
144			`reg_sta <= STA_IDDLE;`
145			`end`
146			`end`
147			`end`
148			`endcase`
149			`end`
150			`end`
151			`endmodule`
152
153			`/////////////////////////////////////////////////////////////////////`
154			`//// Author: Zhangfeifei ////`
155			`//// ////`
156			`//// Advance Test Technology Laboratory, ////`
157			`//// Institute of Computing Technology, ////`
158			`//// Chinese Academy of Sciences ////`
159			`//// ////`
160			`//// If you encountered any problem, please contact : ////`
161			`//// Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org ////`
162			`//// Tel: +86-10-6256 5533 ext. 5673 ////`
163			`//// ////`
164			`//// Downloaded from: ////`
165			`//// http://www.opencores.org/pdownloads.cgi/list/ucore ////`
166			`/////////////////////////////////////////////////////////////////////`
167			`//// ////`
168			`//// Copyright (C) 2005-2006 Zhangfeifei ////`
169			`//// zhangfeifei@ict.ac.cn ////`
170			`//// ////`
171			`//// ////`
172			`//// This source file may be used and distributed freely without ////`
173			`//// restriction provided that this copyright statement is not ////`
174			`//// removed from the file and any derivative work contains the ////`
175			`//// original copyright notice and the associated disclaimer. ////`
176			`//// ////`
177			`//// Please let the author know if it is used ////`
178			`//// for commercial purpose. ////`
179			`//// ////`
180			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
181			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
182			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
183			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
184			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
185			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
186			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
187			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
188			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
189			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
190			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
191			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
192			`//// POSSIBILITY OF SUCH DAMAGE. ////`
193			`//// ////`
194			`/////////////////////////////////////////////////////////////////////`
195			`//// ////`
196			`//// ////`
197			`//// Date of Creation: 2005.12.3 ////`
198			`//// ////`
199			`//// Version: 0.0.1 ////`
200			`//// ////`
201			`//// Description: tx module of the uart module,data format is ////`
202			`//// 8bits data,1 bits stop bit,and no parity check ////`
203			`//// ////`
204			`/////////////////////////////////////////////////////////////////////`
205			`//// ////`
206			`//// Change log: ////`
207			`//// ////`
208			`/////////////////////////////////////////////////////////////////////`
209
210
211			`module uart_txd(`
212			`clk_i,rst_i,//system signal`
213			`data_i,wen_i,//parallel data in and enable signal`
214			`txd_o,//serial data out`
215			`tre_o// ready to transmit flag`
216			`);`
217
218			`parameter // state difinition`
219			`STA_IDDLE = 0,`
220			`STA_TRANS = 1,`
221			`STA_FINISH = 2;`
222
223			`input clk_i;`
224			`input rst_i;`
225			`input [7:0] data_i;`
226			`input wen_i;`
227
228			`output txd_o;`
229			`output tre_o;`
230
231			`reg txd_o;`
232			`reg tre_o;`
233
234			`reg [7:0] tsr;//transmitting shift register`
235			`reg [3:0] num_of_trans;`
236
237			`reg [1:0] reg_sta;`
238
239			`//the counter to count the clk in`
240			`reg [3:0] count;`
241			`reg count_c;//the carry of count`
242
243			`always @(posedge clk_i or negedge rst_i)`
244			`begin`
245			`if(~rst_i)`
246			`begin`
247
248			`tsr <= 8'b0;`
249			`txd_o <= 1'b1;`
250			`tre_o <= 1'b1;`
251			`num_of_trans <= 3'bx;`
252			`count_c <= 1'bx;`
253			`count <= 4'bx;`
254
255			`reg_sta <= STA_IDDLE;`
256			`end`
257			`else begin`
258
259			`case(reg_sta)`
260			`STA_IDDLE:`
261			`begin`
262			`num_of_trans <= 3'd0;`
263			`count <= 4'd0;`
264
265			`if(wen_i)`
266			`begin`
267			`tsr <= data_i;`
268			`tre_o <= 1'b0;`
269			`txd_o <= 1'b0;// transmit the start bit`
270			`reg_sta <= STA_TRANS;`
271			`end`
272			`else`
273			`reg_sta <= STA_IDDLE;`
274			`end`
275			`STA_TRANS:`
276			`begin`
277			`{count_c,count} <= count + 1;`
278
279			`if(count_c)`
280			`begin`
281			`if(num_of_trans <=3'd7)`
282			`begin`
283			`//note ,when num_of_trans==7 ,we transmit the stop bit`
284			`tsr <= {1'b1,tsr[7:1]};`
285			`txd_o <= tsr[0];`
286			`num_of_trans <= num_of_trans+1;`
287			`reg_sta <= STA_TRANS;`
288			`end`
289			`else begin`
290			`txd_o <= 1'b1;`
291			`tre_o <= 1'b1;`
292			`reg_sta <= STA_IDDLE;`
293			`end`
294			`end`
295			`end`
296			`endcase`
297			`end`
298			`end`
299
300
301			`endmodule`
302
303			`/////////////////////////////////////////////////////////////////////`
304			`//// Author: Zhangfeifei ////`
305			`//// ////`
306			`//// Advance Test Technology Laboratory, ////`
307			`//// Institute of Computing Technology, ////`
308			`//// Chinese Academy of Sciences ////`
309			`//// ////`
310			`//// If you encountered any problem, please contact : ////`
311			`//// Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org ////`
312			`//// Tel: +86-10-6256 5533 ext. 5673 ////`
313			`//// ////`
314			`//// Downloaded from: ////`
315			`//// http://www.opencores.org/pdownloads.cgi/list/ucore ////`
316			`/////////////////////////////////////////////////////////////////////`
317			`//// ////`
318			`//// Copyright (C) 2005-2006 Zhangfeifei ////`
319			`//// zhangfeifei@ict.ac.cn ////`
320			`//// ////`
321			`//// ////`
322			`//// This source file may be used and distributed freely without ////`
323			`//// restriction provided that this copyright statement is not ////`
324			`//// removed from the file and any derivative work contains the ////`
325			`//// original copyright notice and the associated disclaimer. ////`
326			`//// ////`
327			`//// Please let the author know if it is used ////`
328			`//// for commercial purpose. ////`
329			`//// ////`
330			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
331			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
332			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
333			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
334			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
335			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
336			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
337			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
338			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
339			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
340			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
341			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
342			`//// POSSIBILITY OF SUCH DAMAGE. ////`
343			`//// ////`
344			`/////////////////////////////////////////////////////////////////////`
345			`//// ////`
346			`//// ////`
347			`//// Date of Creation: 2005.12.3 ////`
348			`//// ////`
349			`//// Version: 0.0.1 ////`
350			`//// ////`
351			`//// Description: clk divider of the uart module, provide a clk ////`
352			`//// 16times quick than the bitrate ////`
353			`//// ////`
354			`/////////////////////////////////////////////////////////////////////`
355			`//// ////`
356			`//// Change log: ////`
357			`//// ////`
358			`/////////////////////////////////////////////////////////////////////`
359
360
361			`module clk_div(`
362			`clk_i,//100 MHZ clk in`
363			`rst_i,`
364			`clk_o//sampling clk out`
365			`);`
366
367			`parameter`
368			`CLK_RATE = 25,//clk rate in MHZ`
369			`BIT_RATE = 9600,`
370			`DIV_NUM = 651;//CLK_RATE1_000_000/(BIT_RATE16);//DIV_NUM = 100M/(9600*16)=651`
371
372			`input clk_i;`
373			`input rst_i;`
374			`//output clk16_o;`
375			`output clk_o;`
376
377			`reg clk_o;`
378
379			`reg [11:0] count;//the minial value of BIT_RATE is 9600 ,`
380			`//so the maxminal DIV_NUM is 2604,a length of 12 bit is big enough`
381			`//reg [3:0] count16;//a counter has cycle of 16`
382			`//reg count1;`
383
384			`//assign clk16_o = count16[3];`
385			`//assign clk1_o = count1;`
386
387			`always @(posedge clk_i or negedge rst_i)`
388			`begin`
389			`if(~rst_i)`
390			`begin`
391			`//$display("BIT_RATE=%d,DIV_NUM=%d",BIT_RATE,DIV_NUM);`
392			`clk_o <= 1'b1;`
393			`//count16 <= 4'b1000;`
394			`count <= 0;`
395			`end`
396			`else begin`
397			`count <= count +1;`
398			`if(count==DIV_NUM/2) clk_o <= 1'b0;`
399			`else if(count==DIV_NUM)`
400			`begin`
401			`clk_o <= 1'b1;`
402			`//count16 <= count16+1;`
403			`count <= 0;`
404			`end`
405			`end`
406			`end`
407
408			`endmodule`
409
410			`/////////////////////////////////////////////////////////////////////`
411			`//// Author: Liwei ////`
412			`//// ////`
413			`//// ////`
414			`//// If you encountered any problem, please contact : ////`
415			`//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////`
416			`//// ////`
417			`//// Downloaded from: ////`
418			`//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////`
419			`/////////////////////////////////////////////////////////////////////`
420			`//// ////`
421			`//// Copyright (C) 2006-2007 Liwei ////`
422			`//// mcupro@yahoo.com.hk ////`
423			`//// ////`
424			`//// ////`
425			`//// This source file may be used and distributed freely without ////`
426			`//// restriction provided that this copyright statement is not ////`
427			`//// removed from the file and any derivative work contains the ////`
428			`//// original copyright notice and the associated disclaimer. ////`
429			`//// ////`
430			`//// Please let the author know if it is used ////`
431			`//// for commercial purpose. ////`
432			`//// ////`
433			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
434			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
435			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
436			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
437			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
438			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
439			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
440			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
441			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
442			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
443			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
444			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
445			`//// POSSIBILITY OF SUCH DAMAGE. ////`
446			`//// ////`
447			`/////////////////////////////////////////////////////////////////////`
448			`//// ////`
449			`//// ////`
450			`//// Date of Creation: 2007.8.1 ////`
451			`//// ////`
452			`//// Version: 0.0.1 ////`
453			`//// ////`
454			`//// Description: ////`
455			`//// ////`
456			`//// ////`
457			`/////////////////////////////////////////////////////////////////////`
458			`//// ////`
459			`//// Change log: ////`
460			`//// ////`
461			`/////////////////////////////////////////////////////////////////////`
462
463			`module uart0 (clk,rst,rxd_ft,ser_rxd,txd_ld,din,rxd_rdy,ser_txd,txd_ldok,dout) ;`
464			`input clk;`
465			`wire clk;`
466			`input rst;`
467			`wire rst;`
468			`input rxd_ft;`
469			`wire rxd_ft;`
470			`input ser_rxd;`
471			`wire ser_rxd;`
472			`input txd_ld;`
473			`wire txd_ld;`
474			`input [7:0] din;`
475			`wire [7:0] din;`
476			`output rxd_rdy;`
477			`wire rxd_rdy;`
478			`output ser_txd;`
479			`wire ser_txd;`
480			`output txd_ldok;`
481			`wire txd_ldok;`
482			`output [7:0] dout;`
483			`wire [7:0] dout;`
484
485			`wire clk_uart;`
486			`wire w_rxd_rdy;`
487			`wire w_rxd_clr;`
488
489
490			`assign w_rxd_clr = ~(rst) & rxd_ft;`
491
492
493			`clk_div clk_div_ff`
494			`(`
495			`.clk_i(clk),`
496			`.clk_o(clk_uart),`
497			`.rst_i(rst)`
498			`);`
499
500
501
502			`uart_rxd rxd_ff`
503			`(`
504			`.clk_i(clk_uart),`
505			`.data_o(dout),`
506			`.rdy_o(w_rxd_rdy),`
507			`.rst_i(rst),`
508			`.rxd_i(ser_rxd)`
509			`);`
510
511
512
513			`rxd_rdy_hold rxd_rdy_hold_lw`
514			`(`
515			`.clk(clk_uart),`
516			`.clr(w_rxd_clr),`
517			`.d(w_rxd_rdy),`
518			`.q(rxd_rdy)`
519			`);`
520
521
522
523			`uart_txd txd_ff`
524			`(`
525			`.clk_i(clk_uart),`
526			`.data_i(din),`
527			`.rst_i(rst),`
528			`.tre_o(txd_ldok),`
529			`.txd_o(ser_txd),`
530			`.wen_i(txd_ld)`
531			`);`
532
533			`endmodule`