OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [tags/] [v001/] [dbe/] [MIPS_UART.bde] - Blame information for rev 53

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 mcupro 
SCHM0103
2 
 
3 
HEADER
4 
{
5 
 FREEID 726
6 
 VARIABLES
7 
 {
8 
  #BLOCKTABLE_FILE="#table.bde"
9 
  #BLOCKTABLE_INCLUDED="1"
10 
  #LANGUAGE="VERILOG"
11 
  #MODULE="MIPSUART"
12 
  AUTHOR="Unknown"
13 
  COMPANY="Unknown"
14 
  CREATIONDATE="8/16/2008"
15 
  TITLE="MIPS_UART"
16 
 }
17 
 SYMBOL "#default" "mem_array" "mem_array"
18 
 {
19 
  HEADER
20 
  {
21 
   VARIABLES
22 
   {
23 
    #DESCRIPTION=""
24 
    #LANGUAGE="VERILOG"
25 
    #MODIFIED="1218631627"
26 
   }
27 
  }
28 
  PAGE ""
29 
  {
30 
   PAGEHEADER
31 
   {
32 
    RECT (0,0,300,280)
33 
    FREEID 19
34 
   }
35 
 
36 
   BODY
37 
   {
38 
    RECT  1, -1, 0
39 
    {
40 
     VARIABLES
41 
     {
42 
      #OUTLINE_FILLING="1"
43 
     }
44 
     AREA (20,0,280,280)
45 
    }
46 
    TEXT  3, 0, 0
47 
    {
48 
     TEXT "$#NAME"
49 
     RECT (25,30,60,54)
50 
     ALIGN 4
51 
     MARGINS (1,1)
52 
     PARENT 2
53 
    }
54 
    TEXT  5, 0, 0
55 
    {
56 
     TEXT "$#NAME"
57 
     RECT (163,30,275,54)
58 
     ALIGN 6
59 
     MARGINS (1,1)
60 
     PARENT 4
61 
    }
62 
    TEXT  7, 0, 0
63 
    {
64 
     TEXT "$#NAME"
65 
     RECT (25,70,126,94)
66 
     ALIGN 4
67 
     MARGINS (1,1)
68 
     PARENT 6
69 
    }
70 
    TEXT  9, 0, 0
71 
    {
72 
     TEXT "$#NAME"
73 
     RECT (152,70,275,94)
74 
     ALIGN 6
75 
     MARGINS (1,1)
76 
     PARENT 8
77 
    }
78 
    TEXT  11, 0, 0
79 
    {
80 
     TEXT "$#NAME"
81 
     RECT (25,110,137,134)
82 
     ALIGN 4
83 
     MARGINS (1,1)
84 
     PARENT 10
85 
    }
86 
    TEXT  13, 0, 0
87 
    {
88 
     TEXT "$#NAME"
89 
     RECT (25,150,192,174)
90 
     ALIGN 4
91 
     MARGINS (1,1)
92 
     PARENT 12
93 
    }
94 
    TEXT  15, 0, 0
95 
    {
96 
     TEXT "$#NAME"
97 
     RECT (25,190,192,214)
98 
     ALIGN 4
99 
     MARGINS (1,1)
100 
     PARENT 14
101 
    }
102 
    TEXT  17, 0, 0
103 
    {
104 
     TEXT "$#NAME"
105 
     RECT (25,230,126,254)
106 
     ALIGN 4
107 
     MARGINS (1,1)
108 
     PARENT 16
109 
    }
110 
    PIN  2, 0, 0
111 
    {
112 
     COORD (0,40)
113 
     VARIABLES
114 
     {
115 
      #DIRECTION="IN"
116 
      #LENGTH="20"
117 
      #MDA_RECORD_TOKEN="OTHER"
118 
      #NAME="clk"
119 
      #NUMBER="0"
120 
      #VERILOG_TYPE="wire"
121 
     }
122 
     LINE  2, 0, 0
123 
     {
124 
      POINTS ( (0,0), (20,0) )
125 
     }
126 
    }
127 
    PIN  4, 0, 0
128 
    {
129 
     COORD (300,40)
130 
     VARIABLES
131 
     {
132 
      #DIRECTION="OUT"
133 
      #DOWNTO="1"
134 
      #LENGTH="20"
135 
      #MDA_RECORD_TOKEN="OTHER"
136 
      #NAME="dout(31:0)"
137 
      #NUMBER="0"
138 
      #VERILOG_TYPE="wire"
139 
     }
140 
     LINE  2, 0, 0
141 
     {
142 
      POINTS ( (-20,0), (0,0) )
143 
     }
144 
    }
145 
    PIN  6, 0, 0
146 
    {
147 
     COORD (0,80)
148 
     VARIABLES
149 
     {
150 
      #DIRECTION="IN"
151 
      #DOWNTO="1"
152 
      #LENGTH="20"
153 
      #MDA_RECORD_TOKEN="OTHER"
154 
      #NAME="din(31:0)"
155 
      #NUMBER="0"
156 
      #VERILOG_TYPE="wire"
157 
     }
158 
     LINE  2, 0, 0
159 
     {
160 
      POINTS ( (0,0), (20,0) )
161 
     }
162 
    }
163 
    PIN  8, 0, 0
164 
    {
165 
     COORD (300,80)
166 
     VARIABLES
167 
     {
168 
      #DIRECTION="OUT"
169 
      #DOWNTO="1"
170 
      #LENGTH="20"
171 
      #MDA_RECORD_TOKEN="OTHER"
172 
      #NAME="ins_o(31:0)"
173 
      #NUMBER="0"
174 
      #VERILOG_TYPE="wire"
175 
     }
176 
     LINE  2, 0, 0
177 
     {
178 
      POINTS ( (-20,0), (0,0) )
179 
     }
180 
    }
181 
    PIN  10, 0, 0
182 
    {
183 
     COORD (0,120)
184 
     VARIABLES
185 
     {
186 
      #DIRECTION="IN"
187 
      #DOWNTO="1"
188 
      #LENGTH="20"
189 
      #MDA_RECORD_TOKEN="OTHER"
190 
      #NAME="pc_i(31:0)"
191 
      #NUMBER="0"
192 
      #VERILOG_TYPE="wire"
193 
     }
194 
     LINE  2, 0, 0
195 
     {
196 
      POINTS ( (0,0), (20,0) )
197 
     }
198 
    }
199 
    PIN  12, 0, 0
200 
    {
201 
     COORD (0,160)
202 
     VARIABLES
203 
     {
204 
      #DIRECTION="IN"
205 
      #DOWNTO="1"
206 
      #LENGTH="20"
207 
      #MDA_RECORD_TOKEN="OTHER"
208 
      #NAME="rd_addr_i(31:0)"
209 
      #NUMBER="0"
210 
      #VERILOG_TYPE="wire"
211 
     }
212 
     LINE  2, 0, 0
213 
     {
214 
      POINTS ( (0,0), (20,0) )
215 
     }
216 
    }
217 
    PIN  14, 0, 0
218 
    {
219 
     COORD (0,200)
220 
     VARIABLES
221 
     {
222 
      #DIRECTION="IN"
223 
      #DOWNTO="1"
224 
      #LENGTH="20"
225 
      #MDA_RECORD_TOKEN="OTHER"
226 
      #NAME="wr_addr_i(31:0)"
227 
      #NUMBER="0"
228 
      #VERILOG_TYPE="wire"
229 
     }
230 
     LINE  2, 0, 0
231 
     {
232 
      POINTS ( (0,0), (20,0) )
233 
     }
234 
    }
235 
    PIN  16, 0, 0
236 
    {
237 
     COORD (0,240)
238 
     VARIABLES
239 
     {
240 
      #DIRECTION="IN"
241 
      #DOWNTO="1"
242 
      #LENGTH="20"
243 
      #MDA_RECORD_TOKEN="OTHER"
244 
      #NAME="wren(3:0)"
245 
      #NUMBER="0"
246 
      #VERILOG_TYPE="wire"
247 
     }
248 
     LINE  2, 0, 0
249 
     {
250 
      POINTS ( (0,0), (20,0) )
251 
     }
252 
    }
253 
   }
254 
  }
255 
 }
256 
 SYMBOL "#default" "mips_core1" "mips_core1"
257 
 {
258 
  HEADER
259 
  {
260 
   VARIABLES
261 
   {
262 
    #DESCRIPTION=""
263 
    #LANGUAGE="VERILOG"
264 
    #MODIFIED="1218631794"
265 
   }
266 
  }
267 
  PAGE ""
268 
  {
269 
   PAGEHEADER
270 
   {
271 
    RECT (0,0,440,360)
272 
    FREEID 33
273 
   }
274 
 
275 
   BODY
276 
   {
277 
    RECT  1, -1, 0
278 
    {
279 
     VARIABLES
280 
     {
281 
      #OUTLINE_FILLING="1"
282 
     }
283 
     AREA (20,0,420,360)
284 
    }
285 
    TEXT  3, 0, 0
286 
    {
287 
     TEXT "$#NAME"
288 
     RECT (25,30,60,54)
289 
     ALIGN 4
290 
     MARGINS (1,1)
291 
     PARENT 2
292 
    }
293 
    TEXT  5, 0, 0
294 
    {
295 
     TEXT "$#NAME"
296 
     RECT (237,30,415,54)
297 
     ALIGN 6
298 
     MARGINS (1,1)
299 
     PARENT 4
300 
    }
301 
    TEXT  7, 0, 0
302 
    {
303 
     TEXT "$#NAME"
304 
     RECT (25,70,181,94)
305 
     ALIGN 4
306 
     MARGINS (1,1)
307 
     PARENT 6
308 
    }
309 
    TEXT  9, 0, 0
310 
    {
311 
     TEXT "$#NAME"
312 
     RECT (237,70,415,94)
313 
     ALIGN 6
314 
     MARGINS (1,1)
315 
     PARENT 8
316 
    }
317 
    TEXT  11, 0, 0
318 
    {
319 
     TEXT "$#NAME"
320 
     RECT (25,110,181,134)
321 
     ALIGN 4
322 
     MARGINS (1,1)
323 
     PARENT 10
324 
    }
325 
    TEXT  13, 0, 0
326 
    {
327 
     TEXT "$#NAME"
328 
     RECT (215,110,415,134)
329 
     ALIGN 6
330 
     MARGINS (1,1)
331 
     PARENT 12
332 
    }
333 
    TEXT  15, 0, 0
334 
    {
335 
     TEXT "$#NAME"
336 
     RECT (25,150,82,174)
337 
     ALIGN 4
338 
     MARGINS (1,1)
339 
     PARENT 14
340 
    }
341 
    TEXT  17, 0, 0
342 
    {
343 
     TEXT "$#NAME"
344 
     RECT (347,150,415,174)
345 
     ALIGN 6
346 
     MARGINS (1,1)
347 
     PARENT 16
348 
    }
349 
    TEXT  19, 0, 0
350 
    {
351 
     TEXT "$#NAME"
352 
     RECT (25,190,60,214)
353 
     ALIGN 4
354 
     MARGINS (1,1)
355 
     PARENT 18
356 
    }
357 
    TEXT  21, 0, 0
358 
    {
359 
     TEXT "$#NAME"
360 
     RECT (248,190,415,214)
361 
     ALIGN 6
362 
     MARGINS (1,1)
363 
     PARENT 20
364 
    }
365 
    TEXT  23, 0, 0
366 
    {
367 
     TEXT "$#NAME"
368 
     RECT (25,230,159,254)
369 
     ALIGN 4
370 
     MARGINS (1,1)
371 
     PARENT 22
372 
    }
373 
    TEXT  25, 0, 0
374 
    {
375 
     TEXT "$#NAME"
376 
     RECT (270,230,415,254)
377 
     ALIGN 6
378 
     MARGINS (1,1)
379 
     PARENT 24
380 
    }
381 
    TEXT  27, 0, 0
382 
    {
383 
     TEXT "$#NAME"
384 
     RECT (25,270,181,294)
385 
     ALIGN 4
386 
     MARGINS (1,1)
387 
     PARENT 26
388 
    }
389 
    TEXT  29, 0, 0
390 
    {
391 
     TEXT "$#NAME"
392 
     RECT (270,270,415,294)
393 
     ALIGN 6
394 
     MARGINS (1,1)
395 
     PARENT 28
396 
    }
397 
    TEXT  31, 0, 0
398 
    {
399 
     TEXT "$#NAME"
400 
     RECT (248,310,415,334)
401 
     ALIGN 6
402 
     MARGINS (1,1)
403 
     PARENT 30
404 
    }
405 
    PIN  2, 0, 0
406 
    {
407 
     COORD (0,40)
408 
     VARIABLES
409 
     {
410 
      #DIRECTION="IN"
411 
      #LENGTH="20"
412 
      #MDA_RECORD_TOKEN="OTHER"
413 
      #NAME="clk"
414 
      #NUMBER="0"
415 
      #VERILOG_TYPE="wire"
416 
     }
417 
     LINE  2, 0, 0
418 
     {
419 
      POINTS ( (0,0), (20,0) )
420 
     }
421 
    }
422 
    PIN  4, 0, 0
423 
    {
424 
     COORD (440,40)
425 
     VARIABLES
426 
     {
427 
      #DIRECTION="OUT"
428 
      #DOWNTO="1"
429 
      #LENGTH="20"
430 
      #MDA_RECORD_TOKEN="OTHER"
431 
      #NAME="cop_addr_o(31:0)"
432 
      #NUMBER="0"
433 
      #VERILOG_TYPE="wire"
434 
     }
435 
     LINE  2, 0, 0
436 
     {
437 
      POINTS ( (-20,0), (0,0) )
438 
     }
439 
    }
440 
    PIN  6, 0, 0
441 
    {
442 
     COORD (0,80)
443 
     VARIABLES
444 
     {
445 
      #DIRECTION="IN"
446 
      #DOWNTO="1"
447 
      #LENGTH="20"
448 
      #MDA_RECORD_TOKEN="OTHER"
449 
      #NAME="cop_dout(31:0)"
450 
      #NUMBER="0"
451 
      #VERILOG_TYPE="wire"
452 
     }
453 
     LINE  2, 0, 0
454 
     {
455 
      POINTS ( (0,0), (20,0) )
456 
     }
457 
    }
458 
    PIN  8, 0, 0
459 
    {
460 
     COORD (440,80)
461 
     VARIABLES
462 
     {
463 
      #DIRECTION="OUT"
464 
      #DOWNTO="1"
465 
      #LENGTH="20"
466 
      #MDA_RECORD_TOKEN="OTHER"
467 
      #NAME="cop_data_o(31:0)"
468 
      #NUMBER="0"
469 
      #VERILOG_TYPE="wire"
470 
     }
471 
     LINE  2, 0, 0
472 
     {
473 
      POINTS ( (-20,0), (0,0) )
474 
     }
475 
    }
476 
    PIN  10, 0, 0
477 
    {
478 
     COORD (0,120)
479 
     VARIABLES
480 
     {
481 
      #DIRECTION="IN"
482 
      #DOWNTO="1"
483 
      #LENGTH="20"
484 
      #MDA_RECORD_TOKEN="OTHER"
485 
      #NAME="irq_addr(31:0)"
486 
      #NUMBER="0"
487 
      #VERILOG_TYPE="wire"
488 
     }
489 
     LINE  2, 0, 0
490 
     {
491 
      POINTS ( (0,0), (20,0) )
492 
     }
493 
    }
494 
    PIN  12, 0, 0
495 
    {
496 
     COORD (440,120)
497 
     VARIABLES
498 
     {
499 
      #DIRECTION="OUT"
500 
      #DOWNTO="1"
501 
      #LENGTH="20"
502 
      #MDA_RECORD_TOKEN="OTHER"
503 
      #NAME="cop_mem_ctl_o(3:0)"
504 
      #NUMBER="0"
505 
      #VERILOG_TYPE="wire"
506 
     }
507 
     LINE  2, 0, 0
508 
     {
509 
      POINTS ( (-20,0), (0,0) )
510 
     }
511 
    }
512 
    PIN  14, 0, 0
513 
    {
514 
     COORD (0,160)
515 
     VARIABLES
516 
     {
517 
      #DIRECTION="IN"
518 
      #LENGTH="20"
519 
      #MDA_RECORD_TOKEN="OTHER"
520 
      #NAME="irq_i"
521 
      #NUMBER="0"
522 
      #VERILOG_TYPE="wire"
523 
     }
524 
     LINE  2, 0, 0
525 
     {
526 
      POINTS ( (0,0), (20,0) )
527 
     }
528 
    }
529 
    PIN  16, 0, 0
530 
    {
531 
     COORD (440,160)
532 
     VARIABLES
533 
     {
534 
      #DIRECTION="OUT"
535 
      #LENGTH="20"
536 
      #MDA_RECORD_TOKEN="OTHER"
537 
      #NAME="iack_o"
538 
      #NUMBER="0"
539 
      #VERILOG_TYPE="wire"
540 
     }
541 
     LINE  2, 0, 0
542 
     {
543 
      POINTS ( (-20,0), (0,0) )
544 
     }
545 
    }
546 
    PIN  18, 0, 0
547 
    {
548 
     COORD (0,200)
549 
     VARIABLES
550 
     {
551 
      #DIRECTION="IN"
552 
      #LENGTH="20"
553 
      #MDA_RECORD_TOKEN="OTHER"
554 
      #NAME="rst"
555 
      #NUMBER="0"
556 
      #VERILOG_TYPE="wire"
557 
     }
558 
     LINE  2, 0, 0
559 
     {
560 
      POINTS ( (0,0), (20,0) )
561 
     }
562 
    }
563 
    PIN  20, 0, 0
564 
    {
565 
     COORD (440,200)
566 
     VARIABLES
567 
     {
568 
      #DIRECTION="OUT"
569 
      #DOWNTO="1"
570 
      #LENGTH="20"
571 
      #MDA_RECORD_TOKEN="OTHER"
572 
      #NAME="zz_addr_o(31:0)"
573 
      #NUMBER="0"
574 
      #VERILOG_TYPE="wire"
575 
     }
576 
     LINE  2, 0, 0
577 
     {
578 
      POINTS ( (-20,0), (0,0) )
579 
     }
580 
    }
581 
    PIN  22, 0, 0
582 
    {
583 
     COORD (0,240)
584 
     VARIABLES
585 
     {
586 
      #DIRECTION="IN"
587 
      #DOWNTO="1"
588 
      #LENGTH="20"
589 
      #MDA_RECORD_TOKEN="OTHER"
590 
      #NAME="zz_din(31:0)"
591 
      #NUMBER="0"
592 
      #VERILOG_TYPE="wire"
593 
     }
594 
     LINE  2, 0, 0
595 
     {
596 
      POINTS ( (0,0), (20,0) )
597 
     }
598 
    }
599 
    PIN  24, 0, 0
600 
    {
601 
     COORD (440,240)
602 
     VARIABLES
603 
     {
604 
      #DIRECTION="OUT"
605 
      #DOWNTO="1"
606 
      #LENGTH="20"
607 
      #MDA_RECORD_TOKEN="OTHER"
608 
      #NAME="zz_dout(31:0)"
609 
      #NUMBER="0"
610 
      #VERILOG_TYPE="wire"
611 
     }
612 
     LINE  2, 0, 0
613 
     {
614 
      POINTS ( (-20,0), (0,0) )
615 
     }
616 
    }
617 
    PIN  26, 0, 0
618 
    {
619 
     COORD (0,280)
620 
     VARIABLES
621 
     {
622 
      #DIRECTION="IN"
623 
      #DOWNTO="1"
624 
      #LENGTH="20"
625 
      #MDA_RECORD_TOKEN="OTHER"
626 
      #NAME="zz_ins_i(31:0)"
627 
      #NUMBER="0"
628 
      #VERILOG_TYPE="wire"
629 
     }
630 
     LINE  2, 0, 0
631 
     {
632 
      POINTS ( (0,0), (20,0) )
633 
     }
634 
    }
635 
    PIN  28, 0, 0
636 
    {
637 
     COORD (440,280)
638 
     VARIABLES
639 
     {
640 
      #DIRECTION="OUT"
641 
      #DOWNTO="1"
642 
      #LENGTH="20"
643 
      #MDA_RECORD_TOKEN="OTHER"
644 
      #NAME="zz_pc_o(31:0)"
645 
      #NUMBER="0"
646 
      #VERILOG_TYPE="wire"
647 
     }
648 
     LINE  2, 0, 0
649 
     {
650 
      POINTS ( (-20,0), (0,0) )
651 
     }
652 
    }
653 
    PIN  30, 0, 0
654 
    {
655 
     COORD (440,320)
656 
     VARIABLES
657 
     {
658 
      #DIRECTION="OUT"
659 
      #DOWNTO="1"
660 
      #LENGTH="20"
661 
      #MDA_RECORD_TOKEN="OTHER"
662 
      #NAME="zz_wr_en_o(3:0)"
663 
      #NUMBER="0"
664 
      #VERILOG_TYPE="wire"
665 
     }
666 
     LINE  2, 0, 0
667 
     {
668 
      POINTS ( (-20,0), (0,0) )
669 
     }
670 
    }
671 
   }
672 
  }
673 
 }
674 
 SYMBOL "#default" "mips_uart" "mips_uart"
675 
 {
676 
  HEADER
677 
  {
678 
   VARIABLES
679 
   {
680 
    #DESCRIPTION=""
681 
    #GENERIC0="FREQUENCE:integer:=25000000"
682 
    #GENERIC1="BANDRATE:integer:=9600"
683 
    #LANGUAGE="VERILOG"
684 
    #MODIFIED="1218827070"
685 
   }
686 
  }
687 
  PAGE ""
688 
  {
689 
   PAGEHEADER
690 
   {
691 
    RECT (0,0,320,280)
692 
    FREEID 19
693 
   }
694 
 
695 
   BODY
696 
   {
697 
    RECT  1, -1, 0
698 
    {
699 
     VARIABLES
700 
     {
701 
      #OUTLINE_FILLING="1"
702 
     }
703 
     AREA (20,0,300,280)
704 
    }
705 
    TEXT  3, 0, 0
706 
    {
707 
     TEXT "$#NAME"
708 
     RECT (25,30,159,54)
709 
     ALIGN 4
710 
     MARGINS (1,1)
711 
     PARENT 2
712 
    }
713 
    TEXT  5, 0, 0
714 
    {
715 
     TEXT "$#NAME"
716 
     RECT (183,30,295,54)
717 
     ALIGN 6
718 
     MARGINS (1,1)
719 
     PARENT 4
720 
    }
721 
    TEXT  7, 0, 0
722 
    {
723 
     TEXT "$#NAME"
724 
     RECT (25,70,60,94)
725 
     ALIGN 4
726 
     MARGINS (1,1)
727 
     PARENT 6
728 
    }
729 
    TEXT  9, 0, 0
730 
    {
731 
     TEXT "$#NAME"
732 
     RECT (238,70,295,94)
733 
     ALIGN 6
734 
     MARGINS (1,1)
735 
     PARENT 8
736 
    }
737 
    TEXT  11, 0, 0
738 
    {
739 
     TEXT "$#NAME"
740 
     RECT (25,110,126,134)
741 
     ALIGN 4
742 
     MARGINS (1,1)
743 
     PARENT 10
744 
    }
745 
    TEXT  13, 0, 0
746 
    {
747 
     TEXT "$#NAME"
748 
     RECT (25,150,192,174)
749 
     ALIGN 4
750 
     MARGINS (1,1)
751 
     PARENT 12
752 
    }
753 
    TEXT  15, 0, 0
754 
    {
755 
     TEXT "$#NAME"
756 
     RECT (25,190,60,214)
757 
     ALIGN 4
758 
     MARGINS (1,1)
759 
     PARENT 14
760 
    }
761 
    TEXT  17, 0, 0
762 
    {
763 
     TEXT "$#NAME"
764 
     RECT (25,230,82,254)
765 
     ALIGN 4
766 
     MARGINS (1,1)
767 
     PARENT 16
768 
    }
769 
    PIN  2, 0, 0
770 
    {
771 
     COORD (0,40)
772 
     VARIABLES
773 
     {
774 
      #DIRECTION="IN"
775 
      #DOWNTO="1"
776 
      #LENGTH="20"
777 
      #MDA_RECORD_TOKEN="OTHER"
778 
      #NAME="addr_i(31:0)"
779 
      #NUMBER="0"
780 
      #VERILOG_TYPE="wire"
781 
     }
782 
     LINE  2, 0, 0
783 
     {
784 
      POINTS ( (0,0), (20,0) )
785 
     }
786 
    }
787 
    PIN  4, 0, 0
788 
    {
789 
     COORD (320,40)
790 
     VARIABLES
791 
     {
792 
      #DIRECTION="OUT"
793 
      #DOWNTO="1"
794 
      #LENGTH="20"
795 
      #MDA_RECORD_TOKEN="OTHER"
796 
      #NAME="dout(31:0)"
797 
      #NUMBER="0"
798 
      #VERILOG_TYPE="reg"
799 
     }
800 
     LINE  2, 0, 0
801 
     {
802 
      POINTS ( (-20,0), (0,0) )
803 
     }
804 
    }
805 
    PIN  6, 0, 0
806 
    {
807 
     COORD (0,80)
808 
     VARIABLES
809 
     {
810 
      #DIRECTION="IN"
811 
      #LENGTH="20"
812 
      #MDA_RECORD_TOKEN="OTHER"
813 
      #NAME="clk"
814 
      #NUMBER="0"
815 
      #VERILOG_TYPE="wire"
816 
     }
817 
     LINE  2, 0, 0
818 
     {
819 
      POINTS ( (0,0), (20,0) )
820 
     }
821 
    }
822 
    PIN  8, 0, 0
823 
    {
824 
     COORD (320,80)
825 
     VARIABLES
826 
     {
827 
      #DIRECTION="OUT"
828 
      #LENGTH="20"
829 
      #MDA_RECORD_TOKEN="OTHER"
830 
      #NAME="ser_o"
831 
      #NUMBER="0"
832 
      #VERILOG_TYPE="wire"
833 
     }
834 
     LINE  2, 0, 0
835 
     {
836 
      POINTS ( (-20,0), (0,0) )
837 
     }
838 
    }
839 
    PIN  10, 0, 0
840 
    {
841 
     COORD (0,120)
842 
     VARIABLES
843 
     {
844 
      #DIRECTION="IN"
845 
      #DOWNTO="1"
846 
      #LENGTH="20"
847 
      #MDA_RECORD_TOKEN="OTHER"
848 
      #NAME="din(31:0)"
849 
      #NUMBER="0"
850 
      #VERILOG_TYPE="wire"
851 
     }
852 
     LINE  2, 0, 0
853 
     {
854 
      POINTS ( (0,0), (20,0) )
855 
     }
856 
    }
857 
    PIN  12, 0, 0
858 
    {
859 
     COORD (0,160)
860 
     VARIABLES
861 
     {
862 
      #DIRECTION="IN"
863 
      #DOWNTO="1"
864 
      #LENGTH="20"
865 
      #MDA_RECORD_TOKEN="OTHER"
866 
      #NAME="dmem_ctl_i(3:0)"
867 
      #NUMBER="0"
868 
      #VERILOG_TYPE="wire"
869 
     }
870 
     LINE  2, 0, 0
871 
     {
872 
      POINTS ( (0,0), (20,0) )
873 
     }
874 
    }
875 
    PIN  14, 0, 0
876 
    {
877 
     COORD (0,200)
878 
     VARIABLES
879 
     {
880 
      #DIRECTION="IN"
881 
      #LENGTH="20"
882 
      #MDA_RECORD_TOKEN="OTHER"
883 
      #NAME="rst"
884 
      #NUMBER="0"
885 
      #VERILOG_TYPE="wire"
886 
     }
887 
     LINE  2, 0, 0
888 
     {
889 
      POINTS ( (0,0), (20,0) )
890 
     }
891 
    }
892 
    PIN  16, 0, 0
893 
    {
894 
     COORD (0,240)
895 
     VARIABLES
896 
     {
897 
      #DIRECTION="IN"
898 
      #LENGTH="20"
899 
      #MDA_RECORD_TOKEN="OTHER"
900 
      #NAME="ser_i"
901 
      #NUMBER="0"
902 
      #VERILOG_TYPE="wire"
903 
     }
904 
     LINE  2, 0, 0
905 
     {
906 
      POINTS ( (0,0), (20,0) )
907 
     }
908 
    }
909 
   }
910 
  }
911 
 }
912 
}
913 
 
914 
PAGE ""
915 
{
916 
 PAGEHEADER
917 
 {
918 
  PAGESIZE (2200,1700)
919 
  MARGINS (200,200,200,200)
920 
  RECT (0,0,0,0)
921 
 }
922 
 
923 
 BODY
924 
 {
925 
  INSTANCE  1, 0, 0
926 
  {
927 
   VARIABLES
928 
   {
929 
    #COMPONENT="mem_array"
930 
    #LIBRARY="#default"
931 
    #REFERENCE="ram_4k"
932 
    #SYMBOL="mem_array"
933 
   }
934 
   COORD (1380,780)
935 
   VERTEXES ( (2,242), (12,252), (14,253), (16,257), (4,264), (8,256), (10,678), (6,691) )
936 
  }
937 
  TEXT  10, 0, 0
938 
  {
939 
   TEXT "$#REFERENCE"
940 
   RECT (1380,744,1484,779)
941 
   ALIGN 8
942 
   MARGINS (1,1)
943 
   PARENT 1
944 
  }
945 
  TEXT  11, 0, 0
946 
  {
947 
   TEXT "$#COMPONENT"
948 
   RECT (1380,1060,1535,1095)
949 
   MARGINS (1,1)
950 
   PARENT 1
951 
  }
952 
  INSTANCE  12, 0, 0
953 
  {
954 
   VARIABLES
955 
   {
956 
    #COMPONENT="Input"
957 
    #LIBRARY="#terminals"
958 
    #REFERENCE="clk"
959 
    #SYMBOL="Input"
960 
   }
961 
   COORD (520,660)
962 
   VERTEXES ( (2,245) )
963 
  }
964 
  TEXT  14, 0, 0
965 
  {
966 
   TEXT "$#REFERENCE"
967 
   RECT (416,643,469,678)
968 
   ALIGN 6
969 
   MARGINS (1,1)
970 
   PARENT 12
971 
  }
972 
  INSTANCE  15, 0, 0
973 
  {
974 
   VARIABLES
975 
   {
976 
    #COMPONENT="Input"
977 
    #LIBRARY="#terminals"
978 
    #REFERENCE="rst"
979 
    #SYMBOL="Input"
980 
   }
981 
   COORD (520,900)
982 
   VERTEXES ( (2,239) )
983 
  }
984 
  TEXT  17, 0, 0
985 
  {
986 
   TEXT "$#REFERENCE"
987 
   RECT (416,883,469,918)
988 
   ALIGN 6
989 
   MARGINS (1,1)
990 
   PARENT 15
991 
  }
992 
  INSTANCE  18, 0, 0
993 
  {
994 
   VARIABLES
995 
   {
996 
    #COMPONENT="Input"
997 
    #LIBRARY="#terminals"
998 
    #REFERENCE="key2"
999 
    #SYMBOL="Input"
1000 
   }
1001 
   COORD (520,860)
1002 
   VERTEXES ( (2,232) )
1003 
  }
1004 
  TEXT  20, 0, 0
1005 
  {
1006 
   TEXT "$#REFERENCE"
1007 
   RECT (399,843,469,878)
1008 
   ALIGN 6
1009 
   MARGINS (1,1)
1010 
   PARENT 18
1011 
  }
1012 
  NET WIRE  21, 0, 0
1013 
  NET WIRE  43, 0, 0
1014 
  NET WIRE  48, 0, 0
1015 
  INSTANCE  57, 0, 0
1016 
  {
1017 
   VARIABLES
1018 
   {
1019 
    #COMPONENT="mips_core1"
1020 
    #LIBRARY="#default"
1021 
    #REFERENCE="mips_core_"
1022 
    #SYMBOL="mips_core1"
1023 
   }
1024 
   COORD (620,700)
1025 
   VERTEXES ( (2,244), (10,249), (14,231), (18,237), (22,263), (26,255), (4,266), (8,268), (12,270), (30,258), (6,599), (28,679), (20,685), (24,692) )
1026 
  }
1027 
  TEXT  72, 0, 0
1028 
  {
1029 
   TEXT "$#REFERENCE"
1030 
   RECT (620,664,792,699)
1031 
   ALIGN 8
1032 
   MARGINS (1,1)
1033 
   PARENT 57
1034 
  }
1035 
  TEXT  73, 0, 0
1036 
  {
1037 
   TEXT "$#COMPONENT"
1038 
   RECT (660,1060,832,1095)
1039 
   MARGINS (1,1)
1040 
   PARENT 57
1041 
  }
1042 
  NET BUS  74, 0, 0
1043 
  NET BUS  76, 0, 0
1044 
  INSTANCE  81, 0, 0
1045 
  {
1046 
   VARIABLES
1047 
   {
1048 
    #COMPONENT="BusInput"
1049 
    #LIBRARY="#terminals"
1050 
    #REFERENCE="irq_addr(31:0)"
1051 
    #SYMBOL="BusInput"
1052 
   }
1053 
   COORD (520,820)
1054 
   VERTEXES ( (2,250) )
1055 
  }
1056 
  TEXT  83, 0, 0
1057 
  {
1058 
   TEXT "$#REFERENCE"
1059 
   RECT (229,803,469,838)
1060 
   ALIGN 6
1061 
   MARGINS (1,1)
1062 
   PARENT 81
1063 
  }
1064 
  NET BUS  86, 0, 0
1065 
  {
1066 
   VARIABLES
1067 
   {
1068 
    #MDA_RECORD_TOKEN="OTHER"
1069 
    #NAME="mem_Addr(31:0)"
1070 
    #VERILOG_TYPE="wire"
1071 
   }
1072 
  }
1073 
  NET BUS  92, 0, 0
1074 
  {
1075 
   VARIABLES
1076 
   {
1077 
    #MDA_RECORD_TOKEN="OTHER"
1078 
    #NAME="ins2core(31:0)"
1079 
    #VERILOG_TYPE="wire"
1080 
   }
1081 
  }
1082 
  NET BUS  98, 0, 0
1083 
  {
1084 
   VARIABLES
1085 
   {
1086 
    #MDA_RECORD_TOKEN="OTHER"
1087 
    #NAME="wr_en(3:0)"
1088 
    #VERILOG_TYPE="wire"
1089 
   }
1090 
  }
1091 
  NET BUS  100, 0, 0
1092 
  {
1093 
   VARIABLES
1094 
   {
1095 
    #MDA_RECORD_TOKEN="OTHER"
1096 
    #NAME="data2mem(31:0)"
1097 
    #VERILOG_TYPE="wire"
1098 
   }
1099 
  }
1100 
  NET BUS  103, 0, 0
1101 
  {
1102 
   VARIABLES
1103 
   {
1104 
    #MDA_RECORD_TOKEN="OTHER"
1105 
    #NAME="pc(31:0)"
1106 
    #VERILOG_TYPE="wire"
1107 
   }
1108 
  }
1109 
  TEXT  113, 0, 0
1110 
  {
1111 
   TEXT "$#NAME"
1112 
   RECT (1101,1051,1299,1080)
1113 
   ALIGN 9
1114 
   MARGINS (1,1)
1115 
   PARENT 306
1116 
  }
1117 
  TEXT  119, 0, 0
1118 
  {
1119 
   TEXT "$#NAME"
1120 
   RECT (1149,990,1291,1019)
1121 
   ALIGN 9
1122 
   MARGINS (1,1)
1123 
   PARENT 310
1124 
  }
1125 
  TEXT  122, 0, 0
1126 
  {
1127 
   TEXT "$#NAME"
1128 
   RECT (1239,830,1437,859)
1129 
   ALIGN 9
1130 
   MARGINS (1,1)
1131 
   PARENT 694
1132 
  }
1133 
  TEXT  127, 0, 0
1134 
  {
1135 
   TEXT "$#NAME"
1136 
   RECT (1122,950,1236,979)
1137 
   ALIGN 9
1138 
   MARGINS (1,1)
1139 
   PARENT 684
1140 
  }
1141 
  TEXT  131, 0, 0
1142 
  {
1143 
   TEXT "$#NAME"
1144 
   RECT (1031,870,1229,899)
1145 
   ALIGN 9
1146 
   MARGINS (1,1)
1147 
   PARENT 690
1148 
  }
1149 
  NET BUS  133, 0, 0
1150 
  {
1151 
   VARIABLES
1152 
   {
1153 
    #MDA_RECORD_TOKEN="OTHER"
1154 
    #NAME="data2core(31:0)"
1155 
    #VERILOG_TYPE="wire"
1156 
   }
1157 
  }
1158 
  TEXT  141, 0, 0
1159 
  {
1160 
   TEXT "$#NAME"
1161 
   RECT (954,1111,1166,1140)
1162 
   ALIGN 9
1163 
   MARGINS (1,1)
1164 
   PARENT 326
1165 
  }
1166 
  NET BUS  143, 0, 0
1167 
  {
1168 
   VARIABLES
1169 
   {
1170 
    #MDA_RECORD_TOKEN="OTHER"
1171 
    #NAME="cop_addr(31:0)"
1172 
    #VERILOG_TYPE="wire"
1173 
   }
1174 
  }
1175 
  TEXT  147, 0, 0
1176 
  {
1177 
   TEXT "$#NAME"
1178 
   RECT (980,366,1178,395)
1179 
   ALIGN 4
1180 
   MARGINS (1,1)
1181 
   PARENT 333
1182 
  }
1183 
  NET BUS  148, 0, 0
1184 
  {
1185 
   VARIABLES
1186 
   {
1187 
    #MDA_RECORD_TOKEN="OTHER"
1188 
    #NAME="data2cop(31:0)"
1189 
    #VERILOG_TYPE="wire"
1190 
   }
1191 
  }
1192 
  TEXT  152, 0, 0
1193 
  {
1194 
   TEXT "$#NAME"
1195 
   RECT (900,606,1098,635)
1196 
   ALIGN 4
1197 
   MARGINS (1,1)
1198 
   PARENT 338
1199 
  }
1200 
  NET BUS  153, 0, 0
1201 
  {
1202 
   VARIABLES
1203 
   {
1204 
    #MDA_RECORD_TOKEN="OTHER"
1205 
    #NAME="cop_mem_ctl(3:0)"
1206 
    #VERILOG_TYPE="wire"
1207 
   }
1208 
  }
1209 
  TEXT  157, 0, 0
1210 
  {
1211 
   TEXT "$#NAME"
1212 
   RECT (1167,731,1393,760)
1213 
   ALIGN 9
1214 
   MARGINS (1,1)
1215 
   PARENT 344
1216 
  }
1217 
  VTX  231, 0, 0
1218 
  {
1219 
   COORD (620,860)
1220 
  }
1221 
  VTX  232, 0, 0
1222 
  {
1223 
   COORD (520,860)
1224 
  }
1225 
  VTX  237, 0, 0
1226 
  {
1227 
   COORD (620,900)
1228 
  }
1229 
  VTX  238, 0, 0
1230 
  {
1231 
   COORD (600,900)
1232 
  }
1233 
  VTX  239, 0, 0
1234 
  {
1235 
   COORD (520,900)
1236 
  }
1237 
  VTX  240, 0, 0
1238 
  {
1239 
   COORD (1200,560)
1240 
  }
1241 
  VTX  241, 0, 0
1242 
  {
1243 
   COORD (640,660)
1244 
  }
1245 
  VTX  242, 0, 0
1246 
  {
1247 
   COORD (1380,820)
1248 
  }
1249 
  VTX  243, 0, 0
1250 
  {
1251 
   COORD (620,660)
1252 
  }
1253 
  VTX  244, 0, 0
1254 
  {
1255 
   COORD (620,740)
1256 
  }
1257 
  VTX  245, 0, 0
1258 
  {
1259 
   COORD (520,660)
1260 
  }
1261 
  VTX  246, 0, 0
1262 
  {
1263 
   COORD (1200,440)
1264 
  }
1265 
  VTX  249, 0, 0
1266 
  {
1267 
   COORD (620,820)
1268 
  }
1269 
  VTX  250, 0, 0
1270 
  {
1271 
   COORD (520,820)
1272 
  }
1273 
  VTX  251, 0, 0
1274 
  {
1275 
   COORD (1360,940)
1276 
  }
1277 
  VTX  252, 0, 0
1278 
  {
1279 
   COORD (1380,940)
1280 
  }
1281 
  VTX  253, 0, 0
1282 
  {
1283 
   COORD (1380,980)
1284 
  }
1285 
  VTX  255, 0, 0
1286 
  {
1287 
   COORD (620,980)
1288 
  }
1289 
  VTX  256, 0, 0
1290 
  {
1291 
   COORD (1680,860)
1292 
  }
1293 
  VTX  257, 0, 0
1294 
  {
1295 
   COORD (1380,1020)
1296 
  }
1297 
  VTX  258, 0, 0
1298 
  {
1299 
   COORD (1060,1020)
1300 
  }
1301 
  VTX  263, 0, 0
1302 
  {
1303 
   COORD (620,940)
1304 
  }
1305 
  VTX  264, 0, 0
1306 
  {
1307 
   COORD (1680,820)
1308 
  }
1309 
  VTX  265, 0, 0
1310 
  {
1311 
   COORD (1200,400)
1312 
  }
1313 
  VTX  266, 0, 0
1314 
  {
1315 
   COORD (1060,740)
1316 
  }
1317 
  VTX  267, 0, 0
1318 
  {
1319 
   COORD (1200,480)
1320 
  }
1321 
  VTX  268, 0, 0
1322 
  {
1323 
   COORD (1060,780)
1324 
  }
1325 
  VTX  269, 0, 0
1326 
  {
1327 
   COORD (1200,520)
1328 
  }
1329 
  VTX  270, 0, 0
1330 
  {
1331 
   COORD (1060,820)
1332 
  }
1333 
  WIRE  271, 0, 0
1334 
  {
1335 
   NET 21
1336 
   VTX 231, 232
1337 
  }
1338 
  WIRE  274, 0, 0
1339 
  {
1340 
   NET 43
1341 
   VTX 237, 238
1342 
  }
1343 
  WIRE  275, 0, 0
1344 
  {
1345 
   NET 43
1346 
   VTX 238, 239
1347 
  }
1348 
  VTX  276, 0, 0
1349 
  {
1350 
   COORD (600,560)
1351 
  }
1352 
  WIRE  277, 0, 0
1353 
  {
1354 
   NET 43
1355 
   VTX 238, 276
1356 
  }
1357 
  WIRE  278, 0, 0
1358 
  {
1359 
   NET 43
1360 
   VTX 276, 240
1361 
  }
1362 
  VTX  279, 0, 0
1363 
  {
1364 
   COORD (1340,660)
1365 
  }
1366 
  WIRE  280, 0, 0
1367 
  {
1368 
   NET 48
1369 
   VTX 241, 279
1370 
  }
1371 
  VTX  281, 0, 0
1372 
  {
1373 
   COORD (1340,820)
1374 
  }
1375 
  WIRE  282, 0, 0
1376 
  {
1377 
   NET 48
1378 
   VTX 279, 281
1379 
  }
1380 
  WIRE  283, 0, 0
1381 
  {
1382 
   NET 48
1383 
   VTX 281, 242
1384 
  }
1385 
  WIRE  284, 0, 0
1386 
  {
1387 
   NET 48
1388 
   VTX 243, 244
1389 
  }
1390 
  WIRE  285, 0, 0
1391 
  {
1392 
   NET 48
1393 
   VTX 245, 243
1394 
  }
1395 
  VTX  286, 0, 0
1396 
  {
1397 
   COORD (640,440)
1398 
  }
1399 
  WIRE  287, 0, 0
1400 
  {
1401 
   NET 48
1402 
   VTX 246, 286
1403 
  }
1404 
  WIRE  288, 0, 0
1405 
  {
1406 
   NET 48
1407 
   VTX 286, 241
1408 
  }
1409 
  WIRE  289, 0, 0
1410 
  {
1411 
   NET 48
1412 
   VTX 241, 243
1413 
  }
1414 
  BUS  291, 0, 0
1415 
  {
1416 
   NET 76
1417 
   VTX 249, 250
1418 
  }
1419 
  BUS  292, 0, 0
1420 
  {
1421 
   NET 86
1422 
   VTX 251, 252
1423 
  }
1424 
  VTX  293, 0, 0
1425 
  {
1426 
   COORD (1360,980)
1427 
  }
1428 
  BUS  294, 0, 0
1429 
  {
1430 
   NET 86
1431 
   VTX 251, 293
1432 
  }
1433 
  BUS  295, 0, 0
1434 
  {
1435 
   NET 86
1436 
   VTX 293, 253
1437 
  }
1438 
  VTX  301, 0, 0
1439 
  {
1440 
   COORD (610,980)
1441 
  }
1442 
  BUS  302, 0, 0
1443 
  {
1444 
   NET 92
1445 
   VTX 255, 301
1446 
  }
1447 
  VTX  303, 0, 0
1448 
  {
1449 
   COORD (610,1080)
1450 
  }
1451 
  BUS  304, 0, 0
1452 
  {
1453 
   NET 92
1454 
   VTX 301, 303
1455 
  }
1456 
  VTX  305, 0, 0
1457 
  {
1458 
   COORD (1700,1080)
1459 
  }
1460 
  BUS  306, 0, 0
1461 
  {
1462 
   NET 92
1463 
   VTX 303, 305
1464 
   VARIABLES
1465 
   {
1466 
    #NAMED="1"
1467 
   }
1468 
  }
1469 
  VTX  307, 0, 0
1470 
  {
1471 
   COORD (1700,860)
1472 
  }
1473 
  BUS  308, 0, 0
1474 
  {
1475 
   NET 92
1476 
   VTX 305, 307
1477 
  }
1478 
  BUS  309, 0, 0
1479 
  {
1480 
   NET 92
1481 
   VTX 307, 256
1482 
  }
1483 
  BUS  310, 0, 0
1484 
  {
1485 
   NET 98
1486 
   VTX 257, 258
1487 
   VARIABLES
1488 
   {
1489 
    #NAMED="1"
1490 
   }
1491 
  }
1492 
  VTX  321, 0, 0
1493 
  {
1494 
   COORD (580,940)
1495 
  }
1496 
  BUS  322, 0, 0
1497 
  {
1498 
   NET 133
1499 
   VTX 263, 321
1500 
  }
1501 
  VTX  323, 0, 0
1502 
  {
1503 
   COORD (580,1100)
1504 
  }
1505 
  BUS  324, 0, 0
1506 
  {
1507 
   NET 133
1508 
   VTX 321, 323
1509 
  }
1510 
  VTX  325, 0, 0
1511 
  {
1512 
   COORD (1720,1100)
1513 
  }
1514 
  BUS  326, 0, 0
1515 
  {
1516 
   NET 133
1517 
   VTX 323, 325
1518 
   VARIABLES
1519 
   {
1520 
    #NAMED="1"
1521 
   }
1522 
  }
1523 
  VTX  327, 0, 0
1524 
  {
1525 
   COORD (1720,820)
1526 
  }
1527 
  BUS  328, 0, 0
1528 
  {
1529 
   NET 133
1530 
   VTX 325, 327
1531 
  }
1532 
  BUS  329, 0, 0
1533 
  {
1534 
   NET 133
1535 
   VTX 327, 264
1536 
  }
1537 
  VTX  330, 0, 0
1538 
  {
1539 
   COORD (1120,400)
1540 
  }
1541 
  BUS  331, 0, 0
1542 
  {
1543 
   NET 143
1544 
   VTX 265, 330
1545 
  }
1546 
  VTX  332, 0, 0
1547 
  {
1548 
   COORD (1120,740)
1549 
  }
1550 
  BUS  333, 0, 0
1551 
  {
1552 
   NET 143
1553 
   VTX 330, 332
1554 
   VARIABLES
1555 
   {
1556 
    #NAMED="1"
1557 
   }
1558 
  }
1559 
  BUS  334, 0, 0
1560 
  {
1561 
   NET 143
1562 
   VTX 332, 266
1563 
  }
1564 
  VTX  335, 0, 0
1565 
  {
1566 
   COORD (1140,480)
1567 
  }
1568 
  BUS  336, 0, 0
1569 
  {
1570 
   NET 148
1571 
   VTX 267, 335
1572 
  }
1573 
  VTX  337, 0, 0
1574 
  {
1575 
   COORD (1140,780)
1576 
  }
1577 
  BUS  338, 0, 0
1578 
  {
1579 
   NET 148
1580 
   VTX 335, 337
1581 
   VARIABLES
1582 
   {
1583 
    #NAMED="1"
1584 
   }
1585 
  }
1586 
  BUS  339, 0, 0
1587 
  {
1588 
   NET 148
1589 
   VTX 337, 268
1590 
  }
1591 
  VTX  340, 0, 0
1592 
  {
1593 
   COORD (1160,520)
1594 
  }
1595 
  BUS  341, 0, 0
1596 
  {
1597 
   NET 153
1598 
   VTX 269, 340
1599 
  }
1600 
  VTX  342, 0, 0
1601 
  {
1602 
   COORD (1160,820)
1603 
  }
1604 
  BUS  343, 0, 0
1605 
  {
1606 
   NET 153
1607 
   VTX 340, 342
1608 
  }
1609 
  BUS  344, 0, 0
1610 
  {
1611 
   NET 153
1612 
   VTX 342, 270
1613 
   VARIABLES
1614 
   {
1615 
    #NAMED="1"
1616 
   }
1617 
  }
1618 
  INSTANCE  345, 0, 0
1619 
  {
1620 
   VARIABLES
1621 
   {
1622 
    #COMPONENT="mips_uart"
1623 
    #LIBRARY="#default"
1624 
    #REFERENCE="uart"
1625 
    #SYMBOL="mips_uart"
1626 
   }
1627 
   COORD (1200,360)
1628 
   VERTEXES ( (2,265), (6,246), (10,267), (12,269), (14,240), (16,409), (4,600), (8,647) )
1629 
  }
1630 
  TEXT  346, 0, 0
1631 
  {
1632 
   TEXT "$#REFERENCE"
1633 
   RECT (1200,324,1270,359)
1634 
   ALIGN 8
1635 
   MARGINS (1,1)
1636 
   PARENT 345
1637 
  }
1638 
  TEXT  350, 0, 0
1639 
  {
1640 
   TEXT "$#COMPONENT"
1641 
   RECT (1200,640,1355,675)
1642 
   MARGINS (1,1)
1643 
   PARENT 345
1644 
  }
1645 
  INSTANCE  388, 0, 0
1646 
  {
1647 
   VARIABLES
1648 
   {
1649 
    #COMPONENT="Input"
1650 
    #LIBRARY="#terminals"
1651 
    #REFERENCE="uart_rxd"
1652 
    #SYMBOL="Input"
1653 
   }
1654 
   COORD (520,600)
1655 
   VERTEXES ( (2,410) )
1656 
  }
1657 
  TEXT  389, 0, 0
1658 
  {
1659 
   TEXT "$#REFERENCE"
1660 
   RECT (331,583,469,618)
1661 
   ALIGN 6
1662 
   MARGINS (1,1)
1663 
   PARENT 388
1664 
  }
1665 
  INSTANCE  393, 0, 0
1666 
  {
1667 
   VARIABLES
1668 
   {
1669 
    #COMPONENT="Output"
1670 
    #LIBRARY="#terminals"
1671 
    #REFERENCE="uart_txd"
1672 
    #SYMBOL="Output"
1673 
   }
1674 
   COORD (1640,440)
1675 
   VERTEXES ( (2,648) )
1676 
  }
1677 
  TEXT  394, 0, 0
1678 
  {
1679 
   TEXT "$#REFERENCE"
1680 
   RECT (1692,423,1830,458)
1681 
   ALIGN 4
1682 
   MARGINS (1,1)
1683 
   PARENT 393
1684 
  }
1685 
  NET WIRE  398, 0, 0
1686 
  NET WIRE  405, 0, 0
1687 
  VTX  409, 0, 0
1688 
  {
1689 
   COORD (1200,600)
1690 
  }
1691 
  VTX  410, 0, 0
1692 
  {
1693 
   COORD (520,600)
1694 
  }
1695 
  WIRE  411, 0, 0
1696 
  {
1697 
   NET 405
1698 
   VTX 409, 410
1699 
  }
1700 
  VTX  599, 0, 0
1701 
  {
1702 
   COORD (620,780)
1703 
  }
1704 
  VTX  600, 0, 0
1705 
  {
1706 
   COORD (1520,400)
1707 
  }
1708 
  VTX  601, 0, 0
1709 
  {
1710 
   COORD (560,780)
1711 
  }
1712 
  BUS  602, 0, 0
1713 
  {
1714 
   NET 74
1715 
   VTX 599, 601
1716 
  }
1717 
  VTX  603, 0, 0
1718 
  {
1719 
   COORD (560,680)
1720 
  }
1721 
  BUS  604, 0, 0
1722 
  {
1723 
   NET 74
1724 
   VTX 601, 603
1725 
  }
1726 
  VTX  605, 0, 0
1727 
  {
1728 
   COORD (1530,680)
1729 
  }
1730 
  BUS  606, 0, 0
1731 
  {
1732 
   NET 74
1733 
   VTX 603, 605
1734 
  }
1735 
  VTX  607, 0, 0
1736 
  {
1737 
   COORD (1530,400)
1738 
  }
1739 
  BUS  608, 0, 0
1740 
  {
1741 
   NET 74
1742 
   VTX 605, 607
1743 
  }
1744 
  BUS  609, 0, 0
1745 
  {
1746 
   NET 74
1747 
   VTX 607, 600
1748 
  }
1749 
  VTX  647, 0, 0
1750 
  {
1751 
   COORD (1520,440)
1752 
  }
1753 
  VTX  648, 0, 0
1754 
  {
1755 
   COORD (1640,440)
1756 
  }
1757 
  WIRE  649, 0, 0
1758 
  {
1759 
   NET 398
1760 
   VTX 647, 648
1761 
  }
1762 
  VTX  678, 0, 0
1763 
  {
1764 
   COORD (1380,900)
1765 
  }
1766 
  VTX  679, 0, 0
1767 
  {
1768 
   COORD (1060,980)
1769 
  }
1770 
  VTX  680, 0, 0
1771 
  {
1772 
   COORD (1320,900)
1773 
  }
1774 
  BUS  681, 0, 0
1775 
  {
1776 
   NET 103
1777 
   VTX 678, 680
1778 
  }
1779 
  VTX  682, 0, 0
1780 
  {
1781 
   COORD (1320,980)
1782 
  }
1783 
  BUS  683, 0, 0
1784 
  {
1785 
   NET 103
1786 
   VTX 680, 682
1787 
  }
1788 
  BUS  684, 0, 0
1789 
  {
1790 
   NET 103
1791 
   VTX 682, 679
1792 
   VARIABLES
1793 
   {
1794 
    #NAMED="1"
1795 
   }
1796 
  }
1797 
  VTX  685, 0, 0
1798 
  {
1799 
   COORD (1060,900)
1800 
  }
1801 
  VTX  686, 0, 0
1802 
  {
1803 
   COORD (1280,940)
1804 
  }
1805 
  BUS  687, 0, 0
1806 
  {
1807 
   NET 86
1808 
   VTX 251, 686
1809 
  }
1810 
  VTX  688, 0, 0
1811 
  {
1812 
   COORD (1280,900)
1813 
  }
1814 
  BUS  689, 0, 0
1815 
  {
1816 
   NET 86
1817 
   VTX 686, 688
1818 
  }
1819 
  BUS  690, 0, 0
1820 
  {
1821 
   NET 86
1822 
   VTX 688, 685
1823 
   VARIABLES
1824 
   {
1825 
    #NAMED="1"
1826 
   }
1827 
  }
1828 
  VTX  691, 0, 0
1829 
  {
1830 
   COORD (1380,860)
1831 
  }
1832 
  VTX  692, 0, 0
1833 
  {
1834 
   COORD (1060,940)
1835 
  }
1836 
  VTX  693, 0, 0
1837 
  {
1838 
   COORD (1220,860)
1839 
  }
1840 
  BUS  694, 0, 0
1841 
  {
1842 
   NET 100
1843 
   VTX 691, 693
1844 
   VARIABLES
1845 
   {
1846 
    #NAMED="1"
1847 
   }
1848 
  }
1849 
  VTX  695, 0, 0
1850 
  {
1851 
   COORD (1220,940)
1852 
  }
1853 
  BUS  696, 0, 0
1854 
  {
1855 
   NET 100
1856 
   VTX 693, 695
1857 
  }
1858 
  BUS  697, 0, 0
1859 
  {
1860 
   NET 100
1861 
   VTX 695, 692
1862 
  }
1863 
 }
1864 
 
1865 
}
1866 
 
1867 
PAGE ""
1868 
{
1869 
 PAGEHEADER
1870 
 {
1871 
  PAGESIZE (2200,1700)
1872 
  MARGINS (200,200,200,200)
1873 
  RECT (0,0,0,0)
1874 
  VARIABLES
1875 
  {
1876 
   #ARCHITECTURE="\\#TABLE\\"
1877 
   #BLOCKTABLE_PAGE="1"
1878 
   #BLOCKTABLE_TEMPL="1"
1879 
   #BLOCKTABLE_VISIBLE="0"
1880 
   #ENTITY="\\#TABLE\\"
1881 
   #MODIFIED="1140746926"
1882 
  }
1883 
 }
1884 
 
1885 
 BODY
1886 
 {
1887 
  TEXT  698, 0, 0
1888 
  {
1889 
   PAGEALIGN 10
1890 
   OUTLINE 5,1, (0,0,0)
1891 
   TEXT "Created:"
1892 
   RECT (1140,1386,1257,1439)
1893 
   ALIGN 4
1894 
   MARGINS (1,10)
1895 
   COLOR (0,0,0)
1896 
   FONT (12,0,0,700,0,0,0,"Arial")
1897 
  }
1898 
  TEXT  699, 0, 0
1899 
  {
1900 
   PAGEALIGN 10
1901 
   TEXT "$CREATIONDATE"
1902 
   RECT (1310,1380,1980,1440)
1903 
   ALIGN 4
1904 
   MARGINS (1,1)
1905 
   COLOR (0,0,0)
1906 
   FONT (12,0,0,700,0,128,0,"Arial")
1907 
   UPDATE 0
1908 
  }
1909 
  TEXT  700, 0, 0
1910 
  {
1911 
   PAGEALIGN 10
1912 
   TEXT "Title:"
1913 
   RECT (1141,1444,1212,1497)
1914 
   ALIGN 4
1915 
   MARGINS (1,10)
1916 
   COLOR (0,0,0)
1917 
   FONT (12,0,0,700,0,0,0,"Arial")
1918 
  }
1919 
  TEXT  701, 0, 0
1920 
  {
1921 
   PAGEALIGN 10
1922 
   OUTLINE 5,1, (0,0,0)
1923 
   TEXT "$TITLE"
1924 
   RECT (1310,1440,1980,1500)
1925 
   ALIGN 4
1926 
   MARGINS (1,1)
1927 
   COLOR (0,0,0)
1928 
   FONT (12,0,0,700,0,128,0,"Arial")
1929 
   UPDATE 0
1930 
  }
1931 
  LINE  702, 0, 0
1932 
  {
1933 
   PAGEALIGN 10
1934 
   OUTLINE 0,1, (128,128,128)
1935 
   POINTS ( (1130,1380), (2000,1380) )
1936 
   FILL (1,(0,0,0),0)
1937 
  }
1938 
  LINE  703, 0, 0
1939 
  {
1940 
   PAGEALIGN 10
1941 
   OUTLINE 0,1, (128,128,128)
1942 
   POINTS ( (1130,1440), (2000,1440) )
1943 
   FILL (1,(0,0,0),0)
1944 
  }
1945 
  LINE  704, 0, 0
1946 
  {
1947 
   PAGEALIGN 10
1948 
   OUTLINE 0,1, (128,128,128)
1949 
   POINTS ( (1300,1380), (1300,1500) )
1950 
  }
1951 
  LINE  705, 0, 0
1952 
  {
1953 
   PAGEALIGN 10
1954 
   OUTLINE 0,1, (128,128,128)
1955 
   POINTS ( (2000,1500), (2000,1240), (1130,1240), (1130,1500), (2000,1500) )
1956 
   FILL (1,(0,0,0),0)
1957 
  }
1958 
  TEXT  706, 0, 0
1959 
  {
1960 
   PAGEALIGN 10
1961 
   TEXT
1962 
"(C)ALDEC. Inc\n"+
1963 
"2260 Corporate Circle\n"+
1964 
"Henderson, NV 89074"
1965 
   RECT (1140,1260,1435,1361)
1966 
   MARGINS (1,1)
1967 
   COLOR (0,0,0)
1968 
   FONT (12,0,0,700,0,0,0,"Arial")
1969 
   MULTILINE
1970 
  }
1971 
  LINE  707, 0, 0
1972 
  {
1973 
   PAGEALIGN 10
1974 
   OUTLINE 0,1, (128,128,128)
1975 
   POINTS ( (1440,1240), (1440,1380) )
1976 
  }
1977 
  LINE  708, 0, 0
1978 
  {
1979 
   PAGEALIGN 10
1980 
   OUTLINE 0,4, (0,4,255)
1981 
   POINTS ( (1616,1304), (1682,1304) )
1982 
   FILL (0,(0,4,255),0)
1983 
  }
1984 
  LINE  709, 0, 0
1985 
  {
1986 
   PAGEALIGN 10
1987 
   OUTLINE 0,1, (0,4,255)
1988 
   POINTS ( (1585,1300), (1585,1300) )
1989 
   FILL (0,(0,4,255),0)
1990 
  }
1991 
  LINE  710, 0, 0
1992 
  {
1993 
   PAGEALIGN 10
1994 
   OUTLINE 0,3, (0,4,255)
1995 
   POINTS ( (1634,1304), (1650,1264) )
1996 
   FILL (0,(0,4,255),0)
1997 
  }
1998 
  TEXT  711, -4, 0
1999 
  {
2000 
   PAGEALIGN 10
2001 
   OUTLINE 5,0, (49,101,255)
2002 
   TEXT "ALDEC"
2003 
   RECT (1663,1246,1961,1348)
2004 
   MARGINS (1,1)
2005 
   COLOR (0,4,255)
2006 
   FONT (36,0,0,700,0,0,0,"Arial")
2007 
  }
2008 
  LINE  712, 0, 0
2009 
  {
2010 
   PAGEALIGN 10
2011 
   OUTLINE 0,3, (0,4,255)
2012 
   POINTS ( (1576,1264), (1551,1327) )
2013 
   FILL (0,(0,4,255),0)
2014 
  }
2015 
  BEZIER  713, 0, 0
2016 
  {
2017 
   PAGEALIGN 10
2018 
   OUTLINE 0,3, (0,4,255)
2019 
   FILL (0,(0,4,255),0)
2020 
   ORIGINS ( (1583,1290), (1616,1304), (1583,1315), (1583,1290) )
2021 
   CONTROLS (( (1607,1290), (1615,1289)),( (1613,1315), (1610,1315)),( (1583,1307), (1583,1302)) )
2022 
  }
2023 
  LINE  714, 0, 0
2024 
  {
2025 
   PAGEALIGN 10
2026 
   OUTLINE 0,4, (0,4,255)
2027 
   POINTS ( (1495,1311), (1583,1311) )
2028 
   FILL (0,(0,4,255),0)
2029 
  }
2030 
  LINE  715, 0, 0
2031 
  {
2032 
   PAGEALIGN 10
2033 
   OUTLINE 0,4, (0,4,255)
2034 
   POINTS ( (1502,1294), (1583,1294) )
2035 
   FILL (0,(0,4,255),0)
2036 
  }
2037 
  LINE  716, 0, 0
2038 
  {
2039 
   PAGEALIGN 10
2040 
   OUTLINE 0,1, (0,4,255)
2041 
   POINTS ( (1688,1271), (1511,1271) )
2042 
   FILL (0,(0,4,255),0)
2043 
  }
2044 
  LINE  717, 0, 0
2045 
  {
2046 
   PAGEALIGN 10
2047 
   OUTLINE 0,1, (0,4,255)
2048 
   POINTS ( (1686,1278), (1508,1278) )
2049 
   FILL (0,(0,4,255),0)
2050 
  }
2051 
  LINE  718, 0, 0
2052 
  {
2053 
   PAGEALIGN 10
2054 
   OUTLINE 0,1, (0,4,255)
2055 
   POINTS ( (1700,1286), (1506,1286) )
2056 
   FILL (0,(0,4,255),0)
2057 
  }
2058 
  LINE  719, 0, 0
2059 
  {
2060 
   PAGEALIGN 10
2061 
   OUTLINE 0,1, (0,4,255)
2062 
   POINTS ( (1702,1294), (1510,1294) )
2063 
   FILL (0,(0,4,255),0)
2064 
  }
2065 
  LINE  720, 0, 0
2066 
  {
2067 
   PAGEALIGN 10
2068 
   OUTLINE 0,1, (0,4,255)
2069 
   POINTS ( (1615,1302), (1499,1302) )
2070 
   FILL (0,(0,4,255),0)
2071 
  }
2072 
  LINE  721, 0, 0
2073 
  {
2074 
   PAGEALIGN 10
2075 
   OUTLINE 0,1, (0,4,255)
2076 
   POINTS ( (1680,1311), (1495,1311) )
2077 
   FILL (0,(0,4,255),0)
2078 
  }
2079 
  LINE  722, 0, 0
2080 
  {
2081 
   PAGEALIGN 10
2082 
   OUTLINE 0,1, (0,4,255)
2083 
   POINTS ( (1673,1319), (1492,1319) )
2084 
   FILL (0,(0,4,255),0)
2085 
  }
2086 
  TEXT  723, 0, 0
2087 
  {
2088 
   PAGEALIGN 10
2089 
   TEXT "The Design Verification Company"
2090 
   RECT (1482,1336,1934,1370)
2091 
   MARGINS (1,1)
2092 
   COLOR (0,4,255)
2093 
   FONT (12,0,0,700,1,0,0,"Arial")
2094 
  }
2095 
  LINE  724, 0, 0
2096 
  {
2097 
   PAGEALIGN 10
2098 
   OUTLINE 0,1, (0,4,255)
2099 
   POINTS ( (1667,1327), (1489,1327) )
2100 
   FILL (0,(0,4,255),0)
2101 
  }
2102 
  LINE  725, 0, 0
2103 
  {
2104 
   PAGEALIGN 10
2105 
   OUTLINE 0,1, (0,4,255)
2106 
   POINTS ( (1690,1264), (1514,1264) )
2107 
   FILL (0,(0,4,255),0)
2108 
  }
2109 
 }
2110 
 
2111 
}
2112 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.