OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [tags/] [v001/] [dbe/] [mem_module.BDE] - Blame information for rev 51

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Line No. Rev Author Line
1 2 mcupro 
SCHM0103
2 
 
3 
HEADER
4 
{
5 
 FREEID 2735
6 
 VARIABLES
7 
 {
8 
  #BLOCKTABLE_FILE="#table.bde"
9 
  #BLOCKTABLE_INCLUDED="1"
10 
  #LANGUAGE="VERILOG"
11 
  #MODULE="mem_module1"
12 
  AUTHOR="liwei"
13 
  COMPANY="PKU"
14 
  CREATIONDATE="2007-8-4"
15 
  TITLE="No Title"
16 
 }
17 
 SYMBOL "#default" "mem_din_ctl" "mem_din_ctl"
18 
 {
19 
  HEADER
20 
  {
21 
   VARIABLES
22 
   {
23 
    #DESCRIPTION=""
24 
    #LANGUAGE="VERILOG"
25 
    #MODIFIED="1186222937"
26 
   }
27 
  }
28 
  PAGE ""
29 
  {
30 
   PAGEHEADER
31 
   {
32 
    RECT (0,0,540,120)
33 
    FREEID 9
34 
   }
35 
 
36 
   BODY
37 
   {
38 
    RECT  1, -1, 0
39 
    {
40 
     VARIABLES
41 
     {
42 
      #OUTLINE_FILLING="1"
43 
     }
44 
     AREA (20,0,520,120)
45 
    }
46 
    TEXT  3, 0, 0
47 
    {
48 
     TEXT "$#NAME"
49 
     RECT (25,70,115,94)
50 
     ALIGN 4
51 
     MARGINS (1,1)
52 
     PARENT 2
53 
    }
54 
    TEXT  5, 0, 0
55 
    {
56 
     TEXT "$#NAME"
57 
     RECT (403,30,515,54)
58 
     ALIGN 6
59 
     MARGINS (1,1)
60 
     PARENT 4
61 
    }
62 
    TEXT  7, 0, 0
63 
    {
64 
     TEXT "$#NAME"
65 
     RECT (20,28,121,52)
66 
     ALIGN 4
67 
     MARGINS (1,1)
68 
     PARENT 6
69 
    }
70 
    PIN  2, 0, 0
71 
    {
72 
     COORD (0,80)
73 
     VARIABLES
74 
     {
75 
      #DIRECTION="IN"
76 
      #DOWNTO="1"
77 
      #LENGTH="20"
78 
      #MDA_RECORD_TOKEN="OTHER"
79 
      #NAME="ctl(3:0)"
80 
      #NUMBER="0"
81 
      #SIDE="left"
82 
      #VERILOG_TYPE="wire"
83 
     }
84 
     LINE  2, 0, 0
85 
     {
86 
      POINTS ( (0,0), (20,0) )
87 
     }
88 
    }
89 
    PIN  4, 0, 0
90 
    {
91 
     COORD (540,40)
92 
     VARIABLES
93 
     {
94 
      #DIRECTION="OUT"
95 
      #DOWNTO="1"
96 
      #LENGTH="20"
97 
      #MDA_RECORD_TOKEN="OTHER"
98 
      #NAME="dout(31:0)"
99 
      #NUMBER="0"
100 
      #VERILOG_TYPE="reg"
101 
     }
102 
     LINE  2, 0, 0
103 
     {
104 
      POINTS ( (-20,0), (0,0) )
105 
     }
106 
    }
107 
    PIN  6, 0, 0
108 
    {
109 
     COORD (0,40)
110 
     VARIABLES
111 
     {
112 
      #DIRECTION="IN"
113 
      #DOWNTO="1"
114 
      #LENGTH="20"
115 
      #MDA_RECORD_TOKEN="OTHER"
116 
      #NAME="din(31:0)"
117 
      #NUMBER="0"
118 
      #SIDE="left"
119 
      #VERILOG_TYPE="wire"
120 
     }
121 
     LINE  2, 0, 0
122 
     {
123 
      POINTS ( (0,0), (20,0) )
124 
     }
125 
    }
126 
   }
127 
  }
128 
 }
129 
 SYMBOL "#default" "mem_addr_ctl" "mem_addr_ctl"
130 
 {
131 
  HEADER
132 
  {
133 
   VARIABLES
134 
   {
135 
    #DESCRIPTION=""
136 
    #LANGUAGE="VERILOG"
137 
    #MODIFIED="1186221485"
138 
   }
139 
  }
140 
  PAGE ""
141 
  {
142 
   PAGEHEADER
143 
   {
144 
    RECT (0,0,540,120)
145 
    FREEID 9
146 
   }
147 
 
148 
   BODY
149 
   {
150 
    RECT  1, -1, 0
151 
    {
152 
     VARIABLES
153 
     {
154 
      #OUTLINE_FILLING="1"
155 
     }
156 
     AREA (20,0,520,120)
157 
    }
158 
    TEXT  3, 0, 0
159 
    {
160 
     TEXT "$#NAME"
161 
     RECT (25,30,159,54)
162 
     ALIGN 4
163 
     MARGINS (1,1)
164 
     PARENT 2
165 
    }
166 
    TEXT  5, 0, 0
167 
    {
168 
     TEXT "$#NAME"
169 
     RECT (403,30,515,54)
170 
     ALIGN 6
171 
     MARGINS (1,1)
172 
     PARENT 4
173 
    }
174 
    TEXT  7, 0, 0
175 
    {
176 
     TEXT "$#NAME"
177 
     RECT (25,70,115,94)
178 
     ALIGN 4
179 
     MARGINS (1,1)
180 
     PARENT 6
181 
    }
182 
    PIN  2, 0, 0
183 
    {
184 
     COORD (0,40)
185 
     VARIABLES
186 
     {
187 
      #DIRECTION="IN"
188 
      #DOWNTO="1"
189 
      #LENGTH="20"
190 
      #MDA_RECORD_TOKEN="OTHER"
191 
      #NAME="addr_i(31:0)"
192 
      #NUMBER="0"
193 
      #VERILOG_TYPE="wire"
194 
     }
195 
     LINE  2, 0, 0
196 
     {
197 
      POINTS ( (0,0), (20,0) )
198 
     }
199 
    }
200 
    PIN  4, 0, 0
201 
    {
202 
     COORD (540,40)
203 
     VARIABLES
204 
     {
205 
      #DIRECTION="OUT"
206 
      #DOWNTO="1"
207 
      #LENGTH="20"
208 
      #MDA_RECORD_TOKEN="OTHER"
209 
      #NAME="wr_en(3:0)"
210 
      #NUMBER="0"
211 
      #VERILOG_TYPE="reg"
212 
     }
213 
     LINE  2, 0, 0
214 
     {
215 
      POINTS ( (-20,0), (0,0) )
216 
     }
217 
    }
218 
    PIN  6, 0, 0
219 
    {
220 
     COORD (0,80)
221 
     VARIABLES
222 
     {
223 
      #DIRECTION="IN"
224 
      #DOWNTO="1"
225 
      #LENGTH="20"
226 
      #MDA_RECORD_TOKEN="OTHER"
227 
      #NAME="ctl(3:0)"
228 
      #NUMBER="0"
229 
      #VERILOG_TYPE="wire"
230 
     }
231 
     LINE  2, 0, 0
232 
     {
233 
      POINTS ( (0,0), (20,0) )
234 
     }
235 
    }
236 
   }
237 
  }
238 
 }
239 
 SYMBOL "#default" "mem_dout_ctl" "mem_dout_ctl"
240 
 {
241 
  HEADER
242 
  {
243 
   VARIABLES
244 
   {
245 
    #DESCRIPTION=""
246 
    #LANGUAGE="VERILOG"
247 
    #MODIFIED="1186221520"
248 
   }
249 
  }
250 
  PAGE ""
251 
  {
252 
   PAGEHEADER
253 
   {
254 
    RECT (0,0,520,160)
255 
    FREEID 11
256 
   }
257 
 
258 
   BODY
259 
   {
260 
    RECT  1, -1, 0
261 
    {
262 
     VARIABLES
263 
     {
264 
      #OUTLINE_FILLING="1"
265 
     }
266 
     AREA (20,0,500,160)
267 
    }
268 
    TEXT  3, 0, 0
269 
    {
270 
     TEXT "$#NAME"
271 
     RECT (25,30,181,54)
272 
     ALIGN 4
273 
     MARGINS (1,1)
274 
     PARENT 2
275 
    }
276 
    TEXT  5, 0, 0
277 
    {
278 
     TEXT "$#NAME"
279 
     RECT (383,30,495,54)
280 
     ALIGN 6
281 
     MARGINS (1,1)
282 
     PARENT 4
283 
    }
284 
    TEXT  7, 0, 0
285 
    {
286 
     TEXT "$#NAME"
287 
     RECT (25,70,115,94)
288 
     ALIGN 4
289 
     MARGINS (1,1)
290 
     PARENT 6
291 
    }
292 
    TEXT  9, 0, 0
293 
    {
294 
     TEXT "$#NAME"
295 
     RECT (25,110,126,134)
296 
     ALIGN 4
297 
     MARGINS (1,1)
298 
     PARENT 8
299 
    }
300 
    PIN  2, 0, 0
301 
    {
302 
     COORD (0,40)
303 
     VARIABLES
304 
     {
305 
      #DIRECTION="IN"
306 
      #DOWNTO="1"
307 
      #LENGTH="20"
308 
      #MDA_RECORD_TOKEN="OTHER"
309 
      #NAME="byte_addr(1:0)"
310 
      #NUMBER="0"
311 
      #VERILOG_TYPE="wire"
312 
     }
313 
     LINE  2, 0, 0
314 
     {
315 
      POINTS ( (0,0), (20,0) )
316 
     }
317 
    }
318 
    PIN  4, 0, 0
319 
    {
320 
     COORD (520,40)
321 
     VARIABLES
322 
     {
323 
      #DIRECTION="OUT"
324 
      #DOWNTO="1"
325 
      #LENGTH="20"
326 
      #MDA_RECORD_TOKEN="OTHER"
327 
      #NAME="dout(31:0)"
328 
      #NUMBER="0"
329 
      #VERILOG_TYPE="reg"
330 
     }
331 
     LINE  2, 0, 0
332 
     {
333 
      POINTS ( (-20,0), (0,0) )
334 
     }
335 
    }
336 
    PIN  6, 0, 0
337 
    {
338 
     COORD (0,80)
339 
     VARIABLES
340 
     {
341 
      #DIRECTION="IN"
342 
      #DOWNTO="1"
343 
      #LENGTH="20"
344 
      #MDA_RECORD_TOKEN="OTHER"
345 
      #NAME="ctl(3:0)"
346 
      #NUMBER="0"
347 
      #VERILOG_TYPE="wire"
348 
     }
349 
     LINE  2, 0, 0
350 
     {
351 
      POINTS ( (0,0), (20,0) )
352 
     }
353 
    }
354 
    PIN  8, 0, 0
355 
    {
356 
     COORD (0,120)
357 
     VARIABLES
358 
     {
359 
      #DIRECTION="IN"
360 
      #DOWNTO="1"
361 
      #LENGTH="20"
362 
      #MDA_RECORD_TOKEN="OTHER"
363 
      #NAME="din(31:0)"
364 
      #NUMBER="0"
365 
      #VERILOG_TYPE="wire"
366 
     }
367 
     LINE  2, 0, 0
368 
     {
369 
      POINTS ( (0,0), (20,0) )
370 
     }
371 
    }
372 
   }
373 
  }
374 
 }
375 
 SYMBOL "#default" "infile_dmem_ctl_reg" "infile_dmem_ctl_reg"
376 
 {
377 
  HEADER
378 
  {
379 
   VARIABLES
380 
   {
381 
    #DESCRIPTION=""
382 
    #LANGUAGE="VERILOG"
383 
    #MODIFIED="1194388301"
384 
   }
385 
  }
386 
  PAGE ""
387 
  {
388 
   PAGEHEADER
389 
   {
390 
    RECT (0,0,520,160)
391 
    FREEID 13
392 
   }
393 
 
394 
   BODY
395 
   {
396 
    RECT  1, -1, 0
397 
    {
398 
     VARIABLES
399 
     {
400 
      #OUTLINE_FILLING="1"
401 
     }
402 
     AREA (20,0,500,160)
403 
    }
404 
    TEXT  3, 0, 0
405 
    {
406 
     TEXT "$#NAME"
407 
     RECT (25,30,60,54)
408 
     ALIGN 4
409 
     MARGINS (1,1)
410 
     PARENT 2
411 
    }
412 
    TEXT  5, 0, 0
413 
    {
414 
     TEXT "$#NAME"
415 
     RECT (317,30,495,54)
416 
     ALIGN 6
417 
     MARGINS (1,1)
418 
     PARENT 4
419 
    }
420 
    TEXT  7, 0, 0
421 
    {
422 
     TEXT "$#NAME"
423 
     RECT (25,70,137,94)
424 
     ALIGN 4
425 
     MARGINS (1,1)
426 
     PARENT 6
427 
    }
428 
    TEXT  9, 0, 0
429 
    {
430 
     TEXT "$#NAME"
431 
     RECT (383,70,495,94)
432 
     ALIGN 6
433 
     MARGINS (1,1)
434 
     PARENT 8
435 
    }
436 
    TEXT  11, 0, 0
437 
    {
438 
     TEXT "$#NAME"
439 
     RECT (25,110,214,134)
440 
     ALIGN 4
441 
     MARGINS (1,1)
442 
     PARENT 10
443 
    }
444 
    PIN  2, 0, 0
445 
    {
446 
     COORD (0,40)
447 
     VARIABLES
448 
     {
449 
      #DIRECTION="IN"
450 
      #LENGTH="20"
451 
      #MDA_RECORD_TOKEN="OTHER"
452 
      #NAME="clk"
453 
      #NUMBER="0"
454 
      #VERILOG_TYPE="wire"
455 
     }
456 
     LINE  2, 0, 0
457 
     {
458 
      POINTS ( (0,0), (20,0) )
459 
     }
460 
    }
461 
    PIN  4, 0, 0
462 
    {
463 
     COORD (520,40)
464 
     VARIABLES
465 
     {
466 
      #DIRECTION="OUT"
467 
      #DOWNTO="1"
468 
      #LENGTH="20"
469 
      #MDA_RECORD_TOKEN="OTHER"
470 
      #NAME="byte_addr_o(1:0)"
471 
      #NUMBER="0"
472 
      #VERILOG_TYPE="reg"
473 
     }
474 
     LINE  2, 0, 0
475 
     {
476 
      POINTS ( (-20,0), (0,0) )
477 
     }
478 
    }
479 
    PIN  6, 0, 0
480 
    {
481 
     COORD (0,80)
482 
     VARIABLES
483 
     {
484 
      #DIRECTION="IN"
485 
      #DOWNTO="1"
486 
      #LENGTH="20"
487 
      #MDA_RECORD_TOKEN="OTHER"
488 
      #NAME="ctl_i(3:0)"
489 
      #NUMBER="0"
490 
      #VERILOG_TYPE="wire"
491 
     }
492 
     LINE  2, 0, 0
493 
     {
494 
      POINTS ( (0,0), (20,0) )
495 
     }
496 
    }
497 
    PIN  8, 0, 0
498 
    {
499 
     COORD (520,80)
500 
     VARIABLES
501 
     {
502 
      #DIRECTION="OUT"
503 
      #DOWNTO="1"
504 
      #LENGTH="20"
505 
      #MDA_RECORD_TOKEN="OTHER"
506 
      #NAME="ctl_o(3:0)"
507 
      #NUMBER="0"
508 
      #VERILOG_TYPE="reg"
509 
     }
510 
     LINE  2, 0, 0
511 
     {
512 
      POINTS ( (-20,0), (0,0) )
513 
     }
514 
    }
515 
    PIN  10, 0, 0
516 
    {
517 
     COORD (0,120)
518 
     VARIABLES
519 
     {
520 
      #DIRECTION="IN"
521 
      #DOWNTO="1"
522 
      #LENGTH="20"
523 
      #MDA_RECORD_TOKEN="OTHER"
524 
      #NAME="dmem_addr_i(31:0)"
525 
      #NUMBER="0"
526 
      #VERILOG_TYPE="wire"
527 
     }
528 
     LINE  2, 0, 0
529 
     {
530 
      POINTS ( (0,0), (20,0) )
531 
     }
532 
    }
533 
   }
534 
  }
535 
 }
536 
}
537 
 
538 
PAGE ""
539 
{
540 
 PAGEHEADER
541 
 {
542 
  PAGESIZE (2787,1968)
543 
  MARGINS (200,200,200,200)
544 
  RECT (0,0,100,200)
545 
 }
546 
 
547 
 BODY
548 
 {
549 
  INSTANCE  29, 0, 0
550 
  {
551 
   VARIABLES
552 
   {
553 
    #COMPONENT="mem_din_ctl"
554 
    #LIBRARY="#default"
555 
    #REFERENCE="i_mem_din_ctl"
556 
    #SYMBOL="mem_din_ctl"
557 
   }
558 
   COORD (480,620)
559 
   VERTEXES ( (6,1866), (2,1854), (4,2423) )
560 
  }
561 
  TEXT  30, 0, 0
562 
  {
563 
   TEXT "$#REFERENCE"
564 
   RECT (480,584,703,619)
565 
   ALIGN 8
566 
   MARGINS (1,1)
567 
   PARENT 29
568 
  }
569 
  TEXT  34, 0, 0
570 
  {
571 
   TEXT "$#COMPONENT"
572 
   RECT (480,740,669,775)
573 
   MARGINS (1,1)
574 
   PARENT 29
575 
  }
576 
  INSTANCE  47, 0, 0
577 
  {
578 
   VARIABLES
579 
   {
580 
    #COMPONENT="mem_addr_ctl"
581 
    #LIBRARY="#default"
582 
    #REFERENCE="i_mem_addr_ctl"
583 
    #SYMBOL="mem_addr_ctl"
584 
   }
585 
   COORD (480,840)
586 
   VERTEXES ( (2,1847), (6,1842), (4,2428) )
587 
  }
588 
  TEXT  48, 0, 0
589 
  {
590 
   TEXT "$#REFERENCE"
591 
   RECT (480,804,720,839)
592 
   ALIGN 8
593 
   MARGINS (1,1)
594 
   PARENT 47
595 
  }
596 
  TEXT  52, 0, 0
597 
  {
598 
   TEXT "$#COMPONENT"
599 
   RECT (480,960,686,995)
600 
   MARGINS (1,1)
601 
   PARENT 47
602 
  }
603 
  INSTANCE  56, 0, 0
604 
  {
605 
   VARIABLES
606 
   {
607 
    #COMPONENT="mem_dout_ctl"
608 
    #LIBRARY="#default"
609 
    #REFERENCE="i_mem_dout_ctl"
610 
    #SYMBOL="mem_dout_ctl"
611 
   }
612 
   COORD (1900,660)
613 
   VERTEXES ( (2,2328), (6,2332), (8,2350), (4,2360) )
614 
  }
615 
  TEXT  57, 0, 0
616 
  {
617 
   TEXT "$#REFERENCE"
618 
   RECT (1900,624,2140,659)
619 
   ALIGN 8
620 
   MARGINS (1,1)
621 
   PARENT 56
622 
  }
623 
  TEXT  61, 0, 0
624 
  {
625 
   TEXT "$#COMPONENT"
626 
   RECT (1900,820,2106,855)
627 
   MARGINS (1,1)
628 
   PARENT 56
629 
  }
630 
  NET BUS  93, 0, 0
631 
  NET BUS  101, 0, 0
632 
  NET BUS  129, 0, 0
633 
  INSTANCE  232, 0, 0
634 
  {
635 
   VARIABLES
636 
   {
637 
    #COMPONENT="Input"
638 
    #LIBRARY="#terminals"
639 
    #REFERENCE="clk"
640 
    #SYMBOL="Input"
641 
   }
642 
   COORD (360,520)
643 
   VERTEXES ( (2,1864) )
644 
  }
645 
  TEXT  233, 0, 0
646 
  {
647 
   TEXT "$#REFERENCE"
648 
   RECT (256,503,309,538)
649 
   ALIGN 6
650 
   MARGINS (1,1)
651 
   PARENT 232
652 
  }
653 
  INSTANCE  237, 0, 0
654 
  {
655 
   VARIABLES
656 
   {
657 
    #COMPONENT="BusInput"
658 
    #LIBRARY="#terminals"
659 
    #REFERENCE="dmem_ctl(3:0)"
660 
    #SYMBOL="BusInput"
661 
    #VERILOG_TYPE="wire"
662 
   }
663 
   COORD (360,700)
664 
   VERTEXES ( (2,2199) )
665 
  }
666 
  TEXT  238, 0, 0
667 
  {
668 
   TEXT "$#REFERENCE"
669 
   RECT (86,683,309,718)
670 
   ALIGN 6
671 
   MARGINS (1,1)
672 
   PARENT 237
673 
  }
674 
  INSTANCE  242, 0, 0
675 
  {
676 
   VARIABLES
677 
   {
678 
    #COMPONENT="BusInput"
679 
    #LIBRARY="#terminals"
680 
    #REFERENCE="din(31:0)"
681 
    #SYMBOL="BusInput"
682 
   }
683 
   COORD (360,660)
684 
   VERTEXES ( (2,1867) )
685 
  }
686 
  TEXT  243, 0, 0
687 
  {
688 
   TEXT "$#REFERENCE"
689 
   RECT (154,643,309,678)
690 
   ALIGN 6
691 
   MARGINS (1,1)
692 
   PARENT 242
693 
  }
694 
  INSTANCE  247, 0, 0
695 
  {
696 
   VARIABLES
697 
   {
698 
    #COMPONENT="BusInput"
699 
    #LIBRARY="#terminals"
700 
    #REFERENCE="dmem_addr_i(31:0)"
701 
    #SYMBOL="BusInput"
702 
    #VERILOG_TYPE="wire"
703 
   }
704 
   COORD (360,780)
705 
   VERTEXES ( (2,2205) )
706 
  }
707 
  TEXT  248, 0, 0
708 
  {
709 
   TEXT "$#REFERENCE"
710 
   RECT (18,763,309,798)
711 
   ALIGN 6
712 
   MARGINS (1,1)
713 
   PARENT 247
714 
  }
715 
  INSTANCE  260, 0, 0
716 
  {
717 
   VARIABLES
718 
   {
719 
    #COMPONENT="BusOutput"
720 
    #LIBRARY="#terminals"
721 
    #REFERENCE="dout(31:0)"
722 
    #SYMBOL="BusOutput"
723 
   }
724 
   COORD (1760,620)
725 
   ORIENTATION 2
726 
   VERTEXES ( (2,2361) )
727 
  }
728 
  TEXT  261, 0, 0
729 
  {
730 
   TEXT "$#REFERENCE"
731 
   RECT (1536,603,1708,638)
732 
   ALIGN 6
733 
   MARGINS (1,1)
734 
   PARENT 260
735 
   ORIENTATION 2
736 
  }
737 
  NET BUS  307, 0, 0
738 
  NET BUS  366, 0, 0
739 
  NET BUS  512, 0, 0
740 
  NET WIRE  585, 0, 0
741 
  NET BUS  629, 0, 0
742 
  NET BUS  650, 0, 0
743 
  INSTANCE  1261, 0, 0
744 
  {
745 
   VARIABLES
746 
   {
747 
    #COMPONENT="infile_dmem_ctl_reg"
748 
    #LIBRARY="#default"
749 
    #REFERENCE="dmem_ctl_post"
750 
    #SYMBOL="infile_dmem_ctl_reg"
751 
   }
752 
   COORD (1180,1060)
753 
   VERTEXES ( (2,1857), (6,1860), (10,1962), (4,2327), (8,2331) )
754 
  }
755 
  TEXT  1262, 0, 0
756 
  {
757 
   TEXT "$#REFERENCE"
758 
   RECT (1180,1024,1403,1059)
759 
   ALIGN 8
760 
   MARGINS (1,1)
761 
   PARENT 1261
762 
  }
763 
  TEXT  1266, 0, 0
764 
  {
765 
   TEXT "$#COMPONENT"
766 
   RECT (1180,1220,1505,1255)
767 
   MARGINS (1,1)
768 
   PARENT 1261
769 
  }
770 
  VTX  1842, 0, 0
771 
  {
772 
   COORD (480,920)
773 
  }
774 
  VTX  1843, 0, 0
775 
  {
776 
   COORD (400,920)
777 
  }
778 
  VTX  1847, 0, 0
779 
  {
780 
   COORD (480,880)
781 
  }
782 
  VTX  1848, 0, 0
783 
  {
784 
   COORD (460,780)
785 
  }
786 
  VTX  1854, 0, 0
787 
  {
788 
   COORD (480,700)
789 
  }
790 
  VTX  1857, 0, 0
791 
  {
792 
   COORD (1180,1100)
793 
  }
794 
  VTX  1860, 0, 0
795 
  {
796 
   COORD (1180,1140)
797 
  }
798 
  VTX  1864, 0, 0
799 
  {
800 
   COORD (360,520)
801 
  }
802 
  VTX  1866, 0, 0
803 
  {
804 
   COORD (480,660)
805 
  }
806 
  VTX  1867, 0, 0
807 
  {
808 
   COORD (360,660)
809 
  }
810 
  BUS  1876, 0, 0
811 
  {
812 
   NET 2203
813 
   VTX 1842, 1843
814 
  }
815 
  VTX  1879, 0, 0
816 
  {
817 
   COORD (460,880)
818 
  }
819 
  BUS  1880, 0, 0
820 
  {
821 
   NET 650
822 
   VTX 1847, 1879
823 
  }
824 
  BUS  1881, 0, 0
825 
  {
826 
   NET 650
827 
   VTX 1879, 1848
828 
  }
829 
  BUS  1887, 0, 0
830 
  {
831 
   NET 650
832 
   VTX 1963, 1848
833 
  }
834 
  BUS  1894, 0, 0
835 
  {
836 
   NET 2203
837 
   VTX 2188, 1854
838 
  }
839 
  VTX  1900, 0, 0
840 
  {
841 
   COORD (1140,1100)
842 
  }
843 
  WIRE  1902, 0, 0
844 
  {
845 
   NET 585
846 
   VTX 1900, 1857
847 
  }
848 
  VTX  1908, 0, 0
849 
  {
850 
   COORD (400,1140)
851 
  }
852 
  BUS  1909, 0, 0
853 
  {
854 
   NET 2203
855 
   VTX 1843, 1908
856 
  }
857 
  BUS  1910, 0, 0
858 
  {
859 
   NET 2203
860 
   VTX 1908, 1860
861 
  }
862 
  VTX  1919, 0, 0
863 
  {
864 
   COORD (1140,520)
865 
  }
866 
  WIRE  1921, 0, 0
867 
  {
868 
   NET 585
869 
   VTX 1919, 1864
870 
  }
871 
  BUS  1923, 0, 0
872 
  {
873 
   NET 307
874 
   VTX 1866, 1867
875 
  }
876 
  VTX  1962, 0, 0
877 
  {
878 
   COORD (1180,1180)
879 
  }
880 
  VTX  1963, 0, 0
881 
  {
882 
   COORD (1060,780)
883 
  }
884 
  VTX  1965, 0, 0
885 
  {
886 
   COORD (1060,1180)
887 
  }
888 
  BUS  1966, 0, 0
889 
  {
890 
   NET 650
891 
   VTX 1963, 1965
892 
  }
893 
  BUS  1967, 0, 0
894 
  {
895 
   NET 650
896 
   VTX 1965, 1962
897 
  }
898 
  INSTANCE  2060, 0, 0
899 
  {
900 
   VARIABLES
901 
   {
902 
    #COMPONENT="BusInput"
903 
    #LIBRARY="#terminals"
904 
    #REFERENCE="zZ_din(31:0)"
905 
    #SYMBOL="BusInput"
906 
    #VERILOG_TYPE="wire"
907 
   }
908 
   COORD (1760,780)
909 
   VERTEXES ( (2,2351) )
910 
  }
911 
  TEXT  2061, 0, 0
912 
  {
913 
   TEXT "$#REFERENCE"
914 
   RECT (1503,763,1709,798)
915 
   ALIGN 6
916 
   MARGINS (1,1)
917 
   PARENT 2060
918 
  }
919 
  INSTANCE  2065, 0, 0
920 
  {
921 
   VARIABLES
922 
   {
923 
    #COMPONENT="BusOutput"
924 
    #LIBRARY="#terminals"
925 
    #REFERENCE="Zz_dout(31:0)"
926 
    #SYMBOL="BusOutput"
927 
    #VERILOG_TYPE="wire"
928 
   }
929 
   COORD (1160,660)
930 
   VERTEXES ( (2,2424) )
931 
  }
932 
  TEXT  2066, 0, 0
933 
  {
934 
   TEXT "$#REFERENCE"
935 
   RECT (1212,643,1435,678)
936 
   ALIGN 4
937 
   MARGINS (1,1)
938 
   PARENT 2065
939 
  }
940 
  INSTANCE  2075, 0, 0
941 
  {
942 
   VARIABLES
943 
   {
944 
    #COMPONENT="BusOutput"
945 
    #LIBRARY="#terminals"
946 
    #REFERENCE="Zz_addr(31:0)"
947 
    #SYMBOL="BusOutput"
948 
   }
949 
   COORD (1160,780)
950 
   VERTEXES ( (2,2426) )
951 
  }
952 
  TEXT  2076, 0, 0
953 
  {
954 
   TEXT "$#REFERENCE"
955 
   RECT (1212,763,1435,798)
956 
   ALIGN 4
957 
   MARGINS (1,1)
958 
   PARENT 2075
959 
  }
960 
  INSTANCE  2085, 0, 0
961 
  {
962 
   VARIABLES
963 
   {
964 
    #COMPONENT="BusOutput"
965 
    #LIBRARY="#terminals"
966 
    #REFERENCE="Zz_wr_en(3:0)"
967 
    #SYMBOL="BusOutput"
968 
   }
969 
   COORD (1160,880)
970 
   VERTEXES ( (2,2429) )
971 
  }
972 
  TEXT  2086, 0, 0
973 
  {
974 
   TEXT "$#REFERENCE"
975 
   RECT (1212,863,1435,898)
976 
   ALIGN 4
977 
   MARGINS (1,1)
978 
   PARENT 2085
979 
  }
980 
  WIRE  2118, 0, 0
981 
  {
982 
   NET 585
983 
   VTX 1900, 1919
984 
  }
985 
  VTX  2188, 0, 0
986 
  {
987 
   COORD (400,700)
988 
  }
989 
  BUS  2198, 0, 0
990 
  {
991 
   NET 2203
992 
   VTX 1843, 2188
993 
  }
994 
  VTX  2199, 0, 0
995 
  {
996 
   COORD (360,700)
997 
  }
998 
  NET BUS  2203, 0, 0
999 
  BUS  2204, 0, 0
1000 
  {
1001 
   NET 2203
1002 
   VTX 2199, 2188
1003 
  }
1004 
  VTX  2205, 0, 0
1005 
  {
1006 
   COORD (360,780)
1007 
  }
1008 
  BUS  2206, 0, 0
1009 
  {
1010 
   NET 650
1011 
   VTX 1848, 2205
1012 
  }
1013 
  VTX  2327, 0, 0
1014 
  {
1015 
   COORD (1700,1100)
1016 
  }
1017 
  VTX  2328, 0, 0
1018 
  {
1019 
   COORD (1900,700)
1020 
  }
1021 
  VTX  2331, 0, 0
1022 
  {
1023 
   COORD (1700,1140)
1024 
  }
1025 
  VTX  2332, 0, 0
1026 
  {
1027 
   COORD (1900,740)
1028 
  }
1029 
  VTX  2335, 0, 0
1030 
  {
1031 
   COORD (1780,1100)
1032 
  }
1033 
  BUS  2336, 0, 0
1034 
  {
1035 
   NET 629
1036 
   VTX 2327, 2335
1037 
  }
1038 
  VTX  2337, 0, 0
1039 
  {
1040 
   COORD (1780,700)
1041 
  }
1042 
  BUS  2338, 0, 0
1043 
  {
1044 
   NET 629
1045 
   VTX 2335, 2337
1046 
  }
1047 
  BUS  2339, 0, 0
1048 
  {
1049 
   NET 629
1050 
   VTX 2337, 2328
1051 
  }
1052 
  VTX  2341, 0, 0
1053 
  {
1054 
   COORD (1800,1140)
1055 
  }
1056 
  BUS  2342, 0, 0
1057 
  {
1058 
   NET 512
1059 
   VTX 2331, 2341
1060 
  }
1061 
  VTX  2343, 0, 0
1062 
  {
1063 
   COORD (1800,740)
1064 
  }
1065 
  BUS  2344, 0, 0
1066 
  {
1067 
   NET 512
1068 
   VTX 2341, 2343
1069 
  }
1070 
  BUS  2345, 0, 0
1071 
  {
1072 
   NET 512
1073 
   VTX 2343, 2332
1074 
  }
1075 
  VTX  2350, 0, 0
1076 
  {
1077 
   COORD (1900,780)
1078 
  }
1079 
  VTX  2351, 0, 0
1080 
  {
1081 
   COORD (1760,780)
1082 
  }
1083 
  BUS  2352, 0, 0
1084 
  {
1085 
   NET 129
1086 
   VTX 2350, 2351
1087 
  }
1088 
  VTX  2360, 0, 0
1089 
  {
1090 
   COORD (2420,700)
1091 
  }
1092 
  VTX  2361, 0, 0
1093 
  {
1094 
   COORD (1760,620)
1095 
  }
1096 
  VTX  2362, 0, 0
1097 
  {
1098 
   COORD (2440,700)
1099 
  }
1100 
  BUS  2363, 0, 0
1101 
  {
1102 
   NET 366
1103 
   VTX 2360, 2362
1104 
  }
1105 
  VTX  2364, 0, 0
1106 
  {
1107 
   COORD (2440,620)
1108 
  }
1109 
  BUS  2365, 0, 0
1110 
  {
1111 
   NET 366
1112 
   VTX 2362, 2364
1113 
  }
1114 
  BUS  2366, 0, 0
1115 
  {
1116 
   NET 366
1117 
   VTX 2364, 2361
1118 
  }
1119 
  VTX  2423, 0, 0
1120 
  {
1121 
   COORD (1020,660)
1122 
  }
1123 
  VTX  2424, 0, 0
1124 
  {
1125 
   COORD (1160,660)
1126 
  }
1127 
  BUS  2425, 0, 0
1128 
  {
1129 
   NET 101
1130 
   VTX 2423, 2424
1131 
  }
1132 
  VTX  2426, 0, 0
1133 
  {
1134 
   COORD (1160,780)
1135 
  }
1136 
  BUS  2427, 0, 0
1137 
  {
1138 
   NET 650
1139 
   VTX 1963, 2426
1140 
  }
1141 
  VTX  2428, 0, 0
1142 
  {
1143 
   COORD (1020,880)
1144 
  }
1145 
  VTX  2429, 0, 0
1146 
  {
1147 
   COORD (1160,880)
1148 
  }
1149 
  BUS  2430, 0, 0
1150 
  {
1151 
   NET 93
1152 
   VTX 2428, 2429
1153 
  }
1154 
 }
1155 
 
1156 
}
1157 
 
1158 
PAGE ""
1159 
{
1160 
 PAGEHEADER
1161 
 {
1162 
  PAGESIZE (2787,1968)
1163 
  MARGINS (200,200,200,200)
1164 
  RECT (0,0,0,0)
1165 
  VARIABLES
1166 
  {
1167 
   #ARCHITECTURE="\\#TABLE\\"
1168 
   #BLOCKTABLE_PAGE="1"
1169 
   #BLOCKTABLE_TEMPL="1"
1170 
   #BLOCKTABLE_VISIBLE="0"
1171 
   #ENTITY="\\#TABLE\\"
1172 
   #MODIFIED="1140746926"
1173 
  }
1174 
 }
1175 
 
1176 
 BODY
1177 
 {
1178 
  TEXT  2707, 0, 0
1179 
  {
1180 
   PAGEALIGN 10
1181 
   OUTLINE 5,1, (0,0,0)
1182 
   TEXT "Created:"
1183 
   RECT (1727,1654,1844,1707)
1184 
   ALIGN 4
1185 
   MARGINS (1,10)
1186 
   COLOR (0,0,0)
1187 
   FONT (12,0,0,700,0,0,0,"Arial")
1188 
  }
1189 
  TEXT  2708, 0, 0
1190 
  {
1191 
   PAGEALIGN 10
1192 
   TEXT "$CREATIONDATE"
1193 
   RECT (1897,1648,2567,1708)
1194 
   ALIGN 4
1195 
   MARGINS (1,1)
1196 
   COLOR (0,0,0)
1197 
   FONT (12,0,0,700,0,128,0,"Arial")
1198 
   UPDATE 0
1199 
  }
1200 
  TEXT  2709, 0, 0
1201 
  {
1202 
   PAGEALIGN 10
1203 
   TEXT "Title:"
1204 
   RECT (1728,1712,1799,1765)
1205 
   ALIGN 4
1206 
   MARGINS (1,10)
1207 
   COLOR (0,0,0)
1208 
   FONT (12,0,0,700,0,0,0,"Arial")
1209 
  }
1210 
  TEXT  2710, 0, 0
1211 
  {
1212 
   PAGEALIGN 10
1213 
   OUTLINE 5,1, (0,0,0)
1214 
   TEXT "$TITLE"
1215 
   RECT (1897,1708,2567,1768)
1216 
   ALIGN 4
1217 
   MARGINS (1,1)
1218 
   COLOR (0,0,0)
1219 
   FONT (12,0,0,700,0,128,0,"Arial")
1220 
   UPDATE 0
1221 
  }
1222 
  LINE  2711, 0, 0
1223 
  {
1224 
   PAGEALIGN 10
1225 
   OUTLINE 0,1, (128,128,128)
1226 
   POINTS ( (1717,1648), (2587,1648) )
1227 
   FILL (1,(0,0,0),0)
1228 
  }
1229 
  LINE  2712, 0, 0
1230 
  {
1231 
   PAGEALIGN 10
1232 
   OUTLINE 0,1, (128,128,128)
1233 
   POINTS ( (1717,1708), (2587,1708) )
1234 
   FILL (1,(0,0,0),0)
1235 
  }
1236 
  LINE  2713, 0, 0
1237 
  {
1238 
   PAGEALIGN 10
1239 
   OUTLINE 0,1, (128,128,128)
1240 
   POINTS ( (1887,1648), (1887,1768) )
1241 
  }
1242 
  LINE  2714, 0, 0
1243 
  {
1244 
   PAGEALIGN 10
1245 
   OUTLINE 0,1, (128,128,128)
1246 
   POINTS ( (2587,1768), (2587,1508), (1717,1508), (1717,1768), (2587,1768) )
1247 
   FILL (1,(0,0,0),0)
1248 
  }
1249 
  TEXT  2715, 0, 0
1250 
  {
1251 
   PAGEALIGN 10
1252 
   TEXT
1253 
"(C)ALDEC. Inc\n"+
1254 
"2260 Corporate Circle\n"+
1255 
"Henderson, NV 89074"
1256 
   RECT (1727,1528,2022,1629)
1257 
   MARGINS (1,1)
1258 
   COLOR (0,0,0)
1259 
   FONT (12,0,0,700,0,0,0,"Arial")
1260 
   MULTILINE
1261 
  }
1262 
  LINE  2716, 0, 0
1263 
  {
1264 
   PAGEALIGN 10
1265 
   OUTLINE 0,1, (128,128,128)
1266 
   POINTS ( (2027,1508), (2027,1648) )
1267 
  }
1268 
  LINE  2717, 0, 0
1269 
  {
1270 
   PAGEALIGN 10
1271 
   OUTLINE 0,4, (0,4,255)
1272 
   POINTS ( (2203,1572), (2269,1572) )
1273 
   FILL (0,(0,4,255),0)
1274 
  }
1275 
  LINE  2718, 0, 0
1276 
  {
1277 
   PAGEALIGN 10
1278 
   OUTLINE 0,1, (0,4,255)
1279 
   POINTS ( (2172,1568), (2172,1568) )
1280 
   FILL (0,(0,4,255),0)
1281 
  }
1282 
  LINE  2719, 0, 0
1283 
  {
1284 
   PAGEALIGN 10
1285 
   OUTLINE 0,3, (0,4,255)
1286 
   POINTS ( (2221,1572), (2237,1532) )
1287 
   FILL (0,(0,4,255),0)
1288 
  }
1289 
  TEXT  2720, -4, 0
1290 
  {
1291 
   PAGEALIGN 10
1292 
   OUTLINE 5,0, (49,101,255)
1293 
   TEXT "ALDEC"
1294 
   RECT (2250,1514,2548,1616)
1295 
   MARGINS (1,1)
1296 
   COLOR (0,4,255)
1297 
   FONT (36,0,0,700,0,0,0,"Arial")
1298 
  }
1299 
  LINE  2721, 0, 0
1300 
  {
1301 
   PAGEALIGN 10
1302 
   OUTLINE 0,3, (0,4,255)
1303 
   POINTS ( (2163,1532), (2138,1595) )
1304 
   FILL (0,(0,4,255),0)
1305 
  }
1306 
  BEZIER  2722, 0, 0
1307 
  {
1308 
   PAGEALIGN 10
1309 
   OUTLINE 0,3, (0,4,255)
1310 
   FILL (0,(0,4,255),0)
1311 
   ORIGINS ( (2170,1558), (2203,1572), (2170,1583), (2170,1558) )
1312 
   CONTROLS (( (2194,1558), (2202,1557)),( (2200,1583), (2197,1583)),( (2170,1575), (2170,1570)) )
1313 
  }
1314 
  LINE  2723, 0, 0
1315 
  {
1316 
   PAGEALIGN 10
1317 
   OUTLINE 0,4, (0,4,255)
1318 
   POINTS ( (2082,1579), (2170,1579) )
1319 
   FILL (0,(0,4,255),0)
1320 
  }
1321 
  LINE  2724, 0, 0
1322 
  {
1323 
   PAGEALIGN 10
1324 
   OUTLINE 0,4, (0,4,255)
1325 
   POINTS ( (2089,1562), (2170,1562) )
1326 
   FILL (0,(0,4,255),0)
1327 
  }
1328 
  LINE  2725, 0, 0
1329 
  {
1330 
   PAGEALIGN 10
1331 
   OUTLINE 0,1, (0,4,255)
1332 
   POINTS ( (2275,1539), (2098,1539) )
1333 
   FILL (0,(0,4,255),0)
1334 
  }
1335 
  LINE  2726, 0, 0
1336 
  {
1337 
   PAGEALIGN 10
1338 
   OUTLINE 0,1, (0,4,255)
1339 
   POINTS ( (2273,1546), (2095,1546) )
1340 
   FILL (0,(0,4,255),0)
1341 
  }
1342 
  LINE  2727, 0, 0
1343 
  {
1344 
   PAGEALIGN 10
1345 
   OUTLINE 0,1, (0,4,255)
1346 
   POINTS ( (2287,1554), (2093,1554) )
1347 
   FILL (0,(0,4,255),0)
1348 
  }
1349 
  LINE  2728, 0, 0
1350 
  {
1351 
   PAGEALIGN 10
1352 
   OUTLINE 0,1, (0,4,255)
1353 
   POINTS ( (2289,1562), (2097,1562) )
1354 
   FILL (0,(0,4,255),0)
1355 
  }
1356 
  LINE  2729, 0, 0
1357 
  {
1358 
   PAGEALIGN 10
1359 
   OUTLINE 0,1, (0,4,255)
1360 
   POINTS ( (2202,1570), (2086,1570) )
1361 
   FILL (0,(0,4,255),0)
1362 
  }
1363 
  LINE  2730, 0, 0
1364 
  {
1365 
   PAGEALIGN 10
1366 
   OUTLINE 0,1, (0,4,255)
1367 
   POINTS ( (2267,1579), (2082,1579) )
1368 
   FILL (0,(0,4,255),0)
1369 
  }
1370 
  LINE  2731, 0, 0
1371 
  {
1372 
   PAGEALIGN 10
1373 
   OUTLINE 0,1, (0,4,255)
1374 
   POINTS ( (2260,1587), (2079,1587) )
1375 
   FILL (0,(0,4,255),0)
1376 
  }
1377 
  TEXT  2732, 0, 0
1378 
  {
1379 
   PAGEALIGN 10
1380 
   TEXT "The Design Verification Company"
1381 
   RECT (2069,1604,2521,1638)
1382 
   MARGINS (1,1)
1383 
   COLOR (0,4,255)
1384 
   FONT (12,0,0,700,1,0,0,"Arial")
1385 
  }
1386 
  LINE  2733, 0, 0
1387 
  {
1388 
   PAGEALIGN 10
1389 
   OUTLINE 0,1, (0,4,255)
1390 
   POINTS ( (2254,1595), (2076,1595) )
1391 
   FILL (0,(0,4,255),0)
1392 
  }
1393 
  LINE  2734, 0, 0
1394 
  {
1395 
   PAGEALIGN 10
1396 
   OUTLINE 0,1, (0,4,255)
1397 
   POINTS ( (2277,1532), (2101,1532) )
1398 
   FILL (0,(0,4,255),0)
1399 
  }
1400 
 }
1401 
 
1402 
}
1403 
 

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