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1 2 mcupro 
/////////////////////////////////////////////////////////////////////
2 
////  Author: Liwei                                              ////
3 
////                                                             ////
4 
////                                                             ////
5 
////  If you encountered any problem, please contact :           ////
6 
////  Email: mcupro@yahoo.com.hk or mcupro@opencores.org         ////
7 
////                                                             ////
8 
////  Downloaded from:                                           ////
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////     http://www.opencores.org/pdownloads.cgi/list/mips789    ////
10 
/////////////////////////////////////////////////////////////////////
11 
////                                                             ////
12 
//// Copyright (C) 2006-2007 Liwei                               ////
13 
////                         mcupro@yahoo.com.hk                 ////
14 
////                                                             ////
15 
////                                                             ////
16 
//// This source file may be used and distributed freely without ////
17 
//// restriction provided that this copyright statement is not   ////
18 
//// removed from the file and any derivative work contains the  ////
19 
//// original copyright notice and the associated disclaimer.    ////
20 
////                                                             ////
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//// Please let the author know if it is used                    ////
22 
//// for commercial purpose.                                     ////
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////                                                             ////
24 
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
25 
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
26 
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
27 
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
28 
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
29 
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
39 
////                                                             ////
40 
////                                                             ////
41 
//// Date of Creation: 2007.8.1                                  ////
42 
////                                                             ////
43 
//// Version: 0.0.1                                              ////
44 
////                                                             ////
45 
//// Description:                                                ////
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////                                                             ////
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////                                                             ////
48 
/////////////////////////////////////////////////////////////////////
49 
////                                                             ////
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//// Change log:                                                 ////
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////                                                             ////
52 
/////////////////////////////////////////////////////////////////////
53 
 
54 
/*
55 
AT :
56 
we assume WB_EN as MEM_WE
57 
*/
58 
`define   ALU_NOP             0
59 
`define   ALU_SRL             1
60 
`define   ALU_SLL             2
61 
`define   ALU_SRA             4
62 
 
63 
 
64 
`define   ALU_MFHI            6
65 
`define   ALU_MFLO            7
66 
`define   ALU_MTLO            30
67 
`define   ALU_MTHI            31
68 
`define   ALU_MULTU           8
69 
`define   ALU_MULT            9
70 
`define   ALU_DIVU            10
71 
`define   ALU_DIV             11
72 
`define   ALU_ADD             12
73 
`define   ALU_ADDU            13
74 
`define   ALU_SUB             14
75 
`define   ALU_SUBU            15
76 
`define   ALU_SLTU            16
77 
`define   ALU_SLT             17
78 
`define   ALU_OR              18
79 
`define   ALU_AND             19
80 
`define   ALU_XOR             20
81 
`define   ALU_NOR             21
82 
`define   ALU_PA              22
83 
`define   ALU_PB              23
84 
 
85 
`define   PC_IGN              1
86 
`define   PC_KEP              2
87 
`define   PC_IRQ              4
88 
`define   PC_RST              8
89 
 
90 
`define   PC_J                1
91 
`define   PC_JR               2
92 
`define   PC_BC               4
93 
`define   PC_NEXT             5
94 
`define   PC_NOP              0
95 
`define PC_RET 6
96 
 `define PC_SPC 6
97 
 
98 
`define   RD_RD               1
99 
`define   RD_RT               2
100 
`define   RD_R31              3
101 
`define   RD_NOP              0
102 
`define RD_ZR 0
103 
 
104 
`define   RD_NOP              0
105 
 
106 
`define   RF                  13
107 
`define   EXEC                10
108 
`define   DMEM                4
109 
`define   WB                  2
110 
 
111 
`define   WB_ALU              0
112 
`define   WB_MEM              1
113 
`define   WB_NOP              0
114 
 
115 
`define   WB_NOP              0
116 
 
117 
`define   MUXA_PC             1
118 
`define   MUXA_RS             2
119 
`define   MUXA_EXT            3
120 
`define   MUXA_SPC            0
121 
`define   MUXA_NOP            0
122 
 
123 
`define   MUXB_RT             1
124 
`define   MUXB_EXT            2
125 
`define   MUXB_NOP            0
126 
 
127 
`define   MUXB_NOP            0
128 
`define   FW_ALU              3'b001
129 
`define   FW_MEM              3'b010
130 
`define   FW_NOP              3'b100
131 
 
132 
`define   CMP_BEQ             1
133 
`define   CMP_BNE             2
134 
`define   CMP_BLEZ            3
135 
`define   CMP_BGEZ            4
136 
`define   CMP_BGTZ            5
137 
`define   CMP_BLTZ            6
138 
`define   CMP_NOP             0
139 
 
140 
`define   FSM_CUR             1
141 
`define   FSM_MUL             2
142 
`define   FSM_RET             4
143 
`define   FSM_NOP             0
144 
`define   FSM_LD              5
145 
`define   FSM_NOI             6
146 
 
147 
`define   REG_NOP             0
148 
`define   REG_CLR             1
149 
`define   REG_KEP             2
150 
 
151 
`define   REG_KEP             2
152 
`define   EXT_SIGN            1
153 
`define   EXT_UNSIGN          2
154 
`define   EXT_J               3
155 
`define   EXT_B               4
156 
`define   EXT_SA              5
157 
`define   EXT_S2H             6
158 
`define   EXT_NOP             0
159 
/*
160 
`define   EXT_CTL_LEN         3
161 
`define   RD_SEL_LEN          1
162 
`define   CMP_CTL_LEN         3
163 
`define   PC_GEN_CTL_LEN      3
164 
`define   FSM_CTL_LEN         3
165 
`define   MUXA_CTL_LEN        2
166 
`define   MUXB_CTL_LEN        2
167 
`define   ALU_FUNC_LEN        5
168 
`define   ALU_WE_LEN          1
169 
`define   DMEM_CTL_LEN        4
170 
`define   WB_MUX_CTL_LEN      1
171 
`define   WB_WE_LEN           1
172 
*/
173 
`define   EN                  1
174 
`define   DIS                 0
175 
`define IGN 0
176 
 
177 
`define   DMEM_SB             1
178 
`define   DMEM_LBS            2
179 
`define   DMEM_LB             3
180 
`define   DMEM_LBU            4
181 
`define   DMEM_SW             5
182 
`define   DMEM_LW             6
183 
`define   DMEM_SH             7
184 
`define   DMEM_LHS            8
185 
`define   DMEM_LH             9
186 
`define   DMEM_LHU            10
187 
`define   DMEM_NOP            0
188 
 
189 
`define   DMEM_NOP            0
190 
 
191 
 
192 
`define   EXT_CTL_LEN         3
193 
`define   RD_SEL_LEN          2
194 
`define   CMP_CTL_LEN         3
195 
`define   PC_GEN_CTL_LEN      3
196 
`define   FSM_CTL_LEN         3
197 
`define   MUXA_CTL_LEN        2
198 
`define   MUXB_CTL_LEN        2
199 
`define   ALU_FUNC_LEN        5
200 
`define   ALU_WE_LEN          1
201 
`define   DMEM_CTL_LEN        4
202 
`define   WB_MUX_CTL_LEN      1
203 
`define   WB_WE_LEN           1
204 
 
205 
module decoder3(
206 
        input [31:0]ins_i,
207 
        output reg [`EXT_CTL_LEN-1:0] ext_ctl,
208 
        output reg [`RD_SEL_LEN-1:0] rd_sel,
209 
        output reg [`CMP_CTL_LEN-1:0]cmp_ctl,
210 
        output reg [`PC_GEN_CTL_LEN-1:0]pc_gen_ctl,
211 
        output reg [`FSM_CTL_LEN-1:0]fsm_dly,
212 
        output reg [`MUXA_CTL_LEN-1:0]muxa_ctl,
213 
        output reg [`MUXB_CTL_LEN-1:0]muxb_ctl,
214 
        output reg [`ALU_FUNC_LEN-1:0]alu_func,
215 
        output reg [`DMEM_CTL_LEN-1:0]dmem_ctl,
216 
        output reg [`ALU_WE_LEN-1:0] alu_we,
217 
        output reg [`WB_MUX_CTL_LEN-1:0]wb_mux,
218 
        output reg [`WB_WE_LEN-1:0]wb_we
219 
    );
220 
 
221 
    wire [5:0]  inst_op,inst_func;
222 
    wire [4:0]  inst_regimm;//,inst_rs,inst_rt,inst_rd,inst_sa;
223 
    wire [4:0]  inst_cop0_func;//cop0's function code filed
224 
    wire [25:0] inst_cop0_code;//cop0's code field
225 
 
226 
    assign inst_op        = ins_i[31:26];
227 
    assign inst_func      = ins_i[5:0];
228 
    assign inst_regimm    = ins_i[20:16];
229 
    assign inst_cop0_func = ins_i[25:21];
230 
    assign inst_cop0_code = ins_i[25:0];
231 
 
232 
    always @(*)
233 
    begin
234 
        case (inst_op)//synthesis parallel_case
235 
            'd0://special operation
236 
            begin
237 
                case (inst_func) //synthesis parallel_case
238 
                    'd0://SLL rd,rt,sa
239 
                    begin
240 
                        //replaceID  = `SLL ;
241 
                        ext_ctl = `EXT_SA;
242 
                        rd_sel = `RD_RD;
243 
                        cmp_ctl = `CMP_NOP;
244 
                        pc_gen_ctl = `PC_NEXT;
245 
                        fsm_dly = `FSM_NOP;
246 
                        muxa_ctl = `MUXA_EXT;
247 
                        muxb_ctl = `MUXB_RT;
248 
                        alu_func = `ALU_SLL;
249 
                        alu_we = `EN;
250 
                        dmem_ctl = `DMEM_NOP;
251 
                        wb_we =  `DIS;
252 
                        wb_mux = `WB_ALU;
253 
                        //end of `SLL ;
254 
                    end
255 
                    'd2://SRL rd,rt,sa
256 
                    begin
257 
                        //replaceID  = `SRL ;
258 
                        ext_ctl = `EXT_SA;
259 
                        rd_sel = `RD_RD;
260 
                        cmp_ctl = `CMP_NOP;
261 
                        pc_gen_ctl = `PC_NEXT;
262 
                        fsm_dly = `FSM_NOP;
263 
                        muxa_ctl = `MUXA_EXT;
264 
                        muxb_ctl = `MUXB_RT;
265 
                        alu_func = `ALU_SRL;
266 
                        alu_we = `EN;
267 
                        dmem_ctl = `DMEM_NOP;
268 
                        wb_we =  `DIS;
269 
                        wb_mux = `WB_ALU;
270 
                        //end of `SRL ;
271 
                    end
272 
                    'd3://SRA rd,rt,sa
273 
                    begin
274 
                        //replaceID  = `SRA ;
275 
                        ext_ctl = `EXT_SA;
276 
                        rd_sel = `RD_RD;
277 
                        cmp_ctl = `CMP_NOP;
278 
                        pc_gen_ctl = `PC_NEXT;
279 
                        fsm_dly = `FSM_NOP;
280 
                        muxa_ctl = `MUXA_EXT;
281 
                        muxb_ctl = `MUXB_RT;
282 
                        alu_func = `ALU_SRA;
283 
                        alu_we = `EN;
284 
                        dmem_ctl = `DMEM_NOP;
285 
                        wb_we =  `DIS;
286 
                        wb_mux = `WB_ALU;
287 
                        //end of `SRA ;
288 
                    end
289 
                    'd4://SLLV rd,rt,rs
290 
                    begin
291 
                        //replaceID  = `SLLV ;
292 
                        ext_ctl = `IGN;
293 
                        rd_sel = `IGN;
294 
                        cmp_ctl = `IGN;
295 
                        pc_gen_ctl = `IGN;
296 
                        fsm_dly = `IGN;
297 
                        muxa_ctl = `IGN;
298 
                        muxb_ctl = `IGN;
299 
                        alu_func = `IGN;
300 
                        alu_we = `IGN;
301 
                        dmem_ctl = `IGN;
302 
                        wb_we =  `IGN;
303 
                        wb_mux = `IGN;
304 
                        //end of `SLLV ;
305 
                    end
306 
                    'd6://SRLV rd,rt,rs
307 
                    begin
308 
                        //replaceID  = `SRLV ;
309 
                        ext_ctl = `IGN;
310 
                        rd_sel = `IGN;
311 
                        cmp_ctl = `IGN;
312 
                        pc_gen_ctl = `IGN;
313 
                        fsm_dly = `IGN;
314 
                        muxa_ctl = `IGN;
315 
                        muxb_ctl = `IGN;
316 
                        alu_func = `IGN;
317 
                        alu_we = `IGN;
318 
                        dmem_ctl = `IGN;
319 
                        wb_we =  `IGN;
320 
                        wb_mux = `IGN;
321 
                        //end of `SRLV ;
322 
                    end
323 
                    'd7://SRAV rd,rt,rs
324 
                    begin
325 
                        //replaceID  = `SRAV ;
326 
                        ext_ctl = `IGN;
327 
                        rd_sel = `IGN;
328 
                        cmp_ctl = `IGN;
329 
                        pc_gen_ctl = `IGN;
330 
                        fsm_dly = `IGN;
331 
                        muxa_ctl = `IGN;
332 
                        muxb_ctl = `IGN;
333 
                        alu_func = `IGN;
334 
                        alu_we = `IGN;
335 
                        dmem_ctl = `IGN;
336 
                        wb_we =  `IGN;
337 
                        wb_mux = `IGN;
338 
                        //end of `SRAV ;
339 
                    end
340 
                    'd8://JR rs
341 
                    begin
342 
                        //replaceID  = `JR ;
343 
                        ext_ctl = `EXT_NOP;
344 
                        rd_sel = `RD_NOP;
345 
                        cmp_ctl = `CMP_NOP;
346 
                        pc_gen_ctl = `PC_JR;
347 
                        fsm_dly = `FSM_CUR;
348 
                        muxa_ctl = `MUXA_NOP;
349 
                        muxb_ctl = `MUXB_NOP;
350 
                        alu_func = `ALU_NOP;
351 
                        alu_we = `DIS;
352 
                        dmem_ctl = `DMEM_NOP;
353 
                        wb_we =  `DIS;
354 
                        wb_mux = `WB_NOP;
355 
                        //end of `JR ;
356 
                    end
357 
                    'd9://JALR jalr rs(rd=31) or jalr rd,rs
358 
                    begin
359 
                        //replaceID  = `JALR ;
360 
                        ext_ctl = `IGN;
361 
                        rd_sel = `IGN;
362 
                        cmp_ctl = `IGN;
363 
                        pc_gen_ctl = `IGN;
364 
                        fsm_dly = `IGN;
365 
                        muxa_ctl = `IGN;
366 
                        muxb_ctl = `IGN;
367 
                        alu_func = `IGN;
368 
                        alu_we = `IGN;
369 
                        dmem_ctl = `IGN;
370 
                        wb_we =  `IGN;
371 
                        wb_mux = `IGN;
372 
                        //end of `JALR ;
373 
                    end
374 
                    'd12://SYSCALL
375 
                    begin
376 
                        //replaceID  = `SYSCALL ;
377 
                        ext_ctl = `IGN;
378 
                        rd_sel = `IGN;
379 
                        cmp_ctl = `IGN;
380 
                        pc_gen_ctl = `IGN;
381 
                        fsm_dly = `IGN;
382 
                        muxa_ctl = `IGN;
383 
                        muxb_ctl = `IGN;
384 
                        alu_func = `IGN;
385 
                        alu_we = `IGN;
386 
                        dmem_ctl = `IGN;
387 
                        wb_we =  `IGN;
388 
                        wb_mux = `IGN;
389 
                        //end of `SYSCALL ;
390 
                    end
391 
                    'd13://BREAK
392 
                    begin
393 
                        //replaceID  = `BREAK ;
394 
                        ext_ctl = `IGN;
395 
                        rd_sel = `IGN;
396 
                        cmp_ctl = `IGN;
397 
                        pc_gen_ctl = `IGN;
398 
                        fsm_dly = `IGN;
399 
                        muxa_ctl = `IGN;
400 
                        muxb_ctl = `IGN;
401 
                        alu_func = `IGN;
402 
                        alu_we = `IGN;
403 
                        dmem_ctl = `IGN;
404 
                        wb_we =  `IGN;
405 
                        wb_mux = `IGN;
406 
                        //end of `BREAK ;
407 
                    end
408 
                    'd16://MFHI rd
409 
                    begin
410 
                        //replaceID  = `MFHI ;
411 
                        ext_ctl = `EXT_NOP;
412 
                        rd_sel = `RD_RD;
413 
                        cmp_ctl = `CMP_NOP;
414 
                        pc_gen_ctl = `PC_NEXT;
415 
                        fsm_dly = `FSM_NOP;
416 
                        muxa_ctl = `MUXA_NOP;
417 
                        muxb_ctl = `MUXB_NOP;
418 
                        alu_func = `ALU_MFHI;
419 
                        alu_we = `EN;
420 
                        dmem_ctl = `DMEM_NOP;
421 
                        wb_we =  `DIS;
422 
                        wb_mux = `WB_ALU;
423 
                        //end of `MFHI ;
424 
                    end
425 
                    'd17://MTHI rs
426 
                    begin
427 
                        //replaceID  = `MTHI ;
428 
                        ext_ctl = `EXT_NOP      ;
429 
                        rd_sel = `RD_NOP;
430 
                        cmp_ctl = `CMP_NOP;
431 
                        pc_gen_ctl = `PC_NEXT;
432 
                        fsm_dly = `FSM_NOP;
433 
                        muxa_ctl = `MUXA_RS;
434 
                        muxb_ctl = `MUXB_NOP;
435 
                        alu_func = `ALU_MTHI;
436 
                        alu_we = `DIS;
437 
                        dmem_ctl = `DMEM_NOP;
438 
                        wb_we =  `DIS;
439 
                        wb_mux = `WB_NOP;
440 
                        //end of `MTHI ;
441 
                    end
442 
                    'd18://MFLO rd
443 
                    begin
444 
                        //replaceID  = `MFLO ;
445 
                        ext_ctl = `EXT_NOP      ;
446 
                        rd_sel = `RD_RD;
447 
                        cmp_ctl = `CMP_NOP;
448 
                        pc_gen_ctl = `PC_NEXT;
449 
                        fsm_dly = `FSM_NOP;
450 
                        muxa_ctl = `MUXA_NOP;
451 
                        muxb_ctl = `MUXB_NOP;
452 
                        alu_func = `ALU_MFLO;
453 
                        alu_we = `EN;
454 
                        dmem_ctl = `DMEM_NOP;
455 
                        wb_we =  `DIS;
456 
                        wb_mux = `WB_ALU;
457 
                        //end of `MFLO ;
458 
                    end
459 
                    'd19://MTLO rs
460 
                    begin
461 
                        //replaceID  = `MTLO ;
462 
                        ext_ctl = `EXT_NOP      ;
463 
                        rd_sel = `RD_NOP;
464 
                        cmp_ctl = `CMP_NOP;
465 
                        pc_gen_ctl = `PC_NEXT;
466 
                        fsm_dly = `FSM_NOP;
467 
                        muxa_ctl = `MUXA_NOP;
468 
                        muxb_ctl = `MUXB_NOP;
469 
                        alu_func = `ALU_MFLO;
470 
                        alu_we = `DIS;
471 
                        dmem_ctl = `DMEM_NOP;
472 
                        wb_we =  `DIS;
473 
                        wb_mux = `WB_NOP;
474 
 
475 
                        //end of `MTLO ;
476 
                    end
477 
                    'd24://MULT rs,rt
478 
                    begin
479 
                        //replaceID  = `MULT ;
480 
                        ext_ctl = `EXT_NOP;
481 
                        rd_sel = `RD_NOP;
482 
                        cmp_ctl = `CMP_NOP;
483 
                        pc_gen_ctl = `PC_NEXT;
484 
                        fsm_dly = `FSM_MUL;
485 
                        muxa_ctl = `MUXA_RS;
486 
                        muxb_ctl = `MUXB_RT;
487 
                        alu_func = `ALU_MULT;
488 
                        alu_we = `DIS;
489 
                        dmem_ctl = `DMEM_NOP;
490 
                        wb_we =  `DIS;
491 
                        wb_mux = `WB_NOP;
492 
                        //end of `MULT ;
493 
                    end
494 
                    'd25://MULTU rs,rt
495 
                    begin
496 
                        //replaceID  = `MULTU ;
497 
                        ext_ctl = `EXT_NOP;
498 
                        rd_sel = `RD_NOP;
499 
                        cmp_ctl = `CMP_NOP;
500 
                        pc_gen_ctl = `PC_NEXT;
501 
                        fsm_dly = `FSM_MUL;
502 
                        muxa_ctl = `MUXA_RS;
503 
                        muxb_ctl = `MUXB_RT;
504 
                        alu_func = `ALU_MULTU;
505 
                        alu_we = `DIS;
506 
                        dmem_ctl = `DMEM_NOP;
507 
                        wb_we =  `DIS;
508 
                        wb_mux = `WB_NOP;
509 
                        //end of `MULTU ;
510 
                    end
511 
                    'd26://DIV rs,rt
512 
                    begin
513 
                        //replaceID  = `DIV ;
514 
                        ext_ctl = `EXT_NOP;
515 
                        rd_sel = `RD_NOP;
516 
                        cmp_ctl = `CMP_NOP;
517 
                        pc_gen_ctl = `PC_NEXT;
518 
                        fsm_dly = `FSM_MUL;
519 
                        muxa_ctl = `MUXA_RS;
520 
                        muxb_ctl = `MUXB_RT;
521 
                        alu_func = `ALU_DIV;
522 
                        alu_we = `DIS;
523 
                        dmem_ctl = `DMEM_NOP;
524 
                        wb_we =  `DIS;
525 
                        wb_mux = `WB_NOP;
526 
                        //end of `DIV ;
527 
                    end
528 
                    'd27://DIVU rs,rt
529 
                    begin
530 
                        //replaceID  = `DIVU ;
531 
                        ext_ctl = `EXT_NOP;
532 
                        rd_sel = `RD_NOP;
533 
                        cmp_ctl = `CMP_NOP;
534 
                        pc_gen_ctl = `PC_NEXT;
535 
                        fsm_dly = `FSM_MUL;
536 
                        muxa_ctl = `MUXA_RS;
537 
                        muxb_ctl = `MUXB_RT;
538 
                        alu_func = `ALU_DIVU;
539 
                        alu_we = `DIS;
540 
                        dmem_ctl = `DMEM_NOP;
541 
                        wb_we =  `DIS;
542 
                        wb_mux = `WB_NOP;
543 
                        //end of `DIVU ;
544 
                    end
545 
                    'd32://ADD rd,rs,rt
546 
                    begin
547 
                        //replaceID  = `ADD ;
548 
                        ext_ctl = `EXT_NOP;
549 
                        rd_sel = `RD_RD;
550 
                        cmp_ctl = `CMP_NOP;
551 
                        pc_gen_ctl = `PC_NEXT;
552 
                        fsm_dly = `FSM_NOP;
553 
                        muxa_ctl = `MUXA_RS;
554 
                        muxb_ctl = `MUXB_RT;
555 
                        alu_func = `ALU_ADD;
556 
                        alu_we = `EN;
557 
                        dmem_ctl = `DMEM_NOP;
558 
                        wb_we =  `DIS;
559 
                        wb_mux = `WB_ALU;
560 
                        //end of `ADD ;
561 
                    end
562 
                    'd33://ADDU rd,rs,rt
563 
                    begin
564 
                        //replaceID  = `ADDU ;
565 
                        ext_ctl = `EXT_NOP;
566 
                        rd_sel = `RD_RD;
567 
                        cmp_ctl = `CMP_NOP;
568 
                        pc_gen_ctl = `PC_NEXT;
569 
                        fsm_dly = `FSM_NOP;
570 
                        muxa_ctl = `MUXA_RS;
571 
                        muxb_ctl = `MUXB_RT;
572 
                        alu_func = `ALU_ADD;
573 
                        alu_we = `EN;
574 
                        dmem_ctl = `DMEM_NOP;
575 
                        wb_we =  `DIS;
576 
                        wb_mux = `WB_ALU;
577 
                        //end of `ADDU ;
578 
                    end
579 
                    'd34://SUB rd,rs,rt
580 
                    begin
581 
                        //replaceID  = `SUB ;
582 
                        ext_ctl = `EXT_NOP;
583 
                        rd_sel = `RD_RD;
584 
                        cmp_ctl = `CMP_NOP;
585 
                        pc_gen_ctl = `PC_NEXT;
586 
                        fsm_dly = `FSM_NOP;
587 
                        muxa_ctl = `MUXA_RS;
588 
                        muxb_ctl = `MUXB_RT;
589 
                        alu_func = `ALU_SUB;
590 
                        alu_we = `EN;
591 
                        dmem_ctl = `DMEM_NOP;
592 
                        wb_we =  `DIS;
593 
                        wb_mux = `WB_ALU;
594 
                        //end of `SUB ;
595 
                    end
596 
                    'd35://SUBU rd,rs,rt
597 
                    begin
598 
                        //replaceID  = `SUBU ;
599 
                        ext_ctl = `EXT_NOP;
600 
                        rd_sel = `RD_RD;
601 
                        cmp_ctl = `CMP_NOP;
602 
                        pc_gen_ctl = `PC_NEXT;
603 
                        fsm_dly = `FSM_NOP;
604 
                        muxa_ctl = `MUXA_RS;
605 
                        muxb_ctl = `MUXB_RT;
606 
                        alu_func = `ALU_SUBU;
607 
                        alu_we = `EN;
608 
                        dmem_ctl = `DMEM_NOP;
609 
                        wb_we =  `DIS;
610 
                        wb_mux = `WB_ALU;
611 
                        //end of `SUBU ;
612 
                    end
613 
                    'd36://AND rd,rs,rt
614 
                    begin
615 
                        //replaceID  = `AND ;
616 
                        ext_ctl = `EXT_NOP;
617 
                        rd_sel = `RD_RD;
618 
                        cmp_ctl = `CMP_NOP;
619 
                        pc_gen_ctl = `PC_NEXT;
620 
                        fsm_dly = `FSM_NOP;
621 
                        muxa_ctl = `MUXA_RS;
622 
                        muxb_ctl = `MUXB_RT;
623 
                        alu_func = `ALU_AND;
624 
                        alu_we = `EN;
625 
                        dmem_ctl = `DMEM_NOP;
626 
                        wb_we =  `DIS;
627 
                        wb_mux = `WB_ALU;
628 
                        //end of `AND ;
629 
                    end
630 
                    'd37://OR rd,rs,rt
631 
                    begin
632 
                        //replaceID  = `OR ;
633 
                        ext_ctl = `EXT_NOP;
634 
                        rd_sel = `RD_RD;
635 
                        cmp_ctl = `CMP_NOP;
636 
                        pc_gen_ctl = `PC_NEXT;
637 
                        fsm_dly = `FSM_NOP;
638 
                        muxa_ctl = `MUXA_RS;
639 
                        muxb_ctl = `MUXB_RT;
640 
                        alu_func = `ALU_OR;
641 
                        alu_we = `EN;
642 
                        dmem_ctl = `DMEM_NOP;
643 
                        wb_we =  `DIS;
644 
                        wb_mux = `WB_ALU;
645 
                        //end of `OR ;
646 
                    end
647 
                    'd38://XOR rd,rs,rt
648 
                    begin
649 
                        //replaceID  = `XOR ;
650 
                        ext_ctl = `EXT_NOP;
651 
                        rd_sel = `RD_RD;
652 
                        cmp_ctl = `CMP_NOP;
653 
                        pc_gen_ctl = `PC_NEXT;
654 
                        fsm_dly = `FSM_NOP;
655 
                        muxa_ctl = `MUXA_RS;
656 
                        muxb_ctl = `MUXB_RT;
657 
                        alu_func = `ALU_XOR;
658 
                        alu_we = `EN;
659 
                        dmem_ctl = `DMEM_NOP;
660 
                        wb_we =  `DIS;
661 
                        wb_mux = `WB_ALU;
662 
                        //end of `XOR ;
663 
                    end
664 
                    'd39://NOR rd,rs,rt
665 
                    begin
666 
                        //replaceID  = `NOR ;
667 
                        ext_ctl = `EXT_NOP;
668 
                        rd_sel = `RD_RD;
669 
                        cmp_ctl = `CMP_NOP;
670 
                        pc_gen_ctl = `PC_NEXT;
671 
                        fsm_dly = `FSM_NOP;
672 
                        muxa_ctl = `MUXA_RS;
673 
                        muxb_ctl = `MUXB_RT;
674 
                        alu_func = `ALU_NOR;
675 
                        alu_we = `EN;
676 
                        dmem_ctl = `DMEM_NOP;
677 
                        wb_we =  `DIS;
678 
                        wb_mux = `WB_ALU;
679 
                        //end of `NOR ;
680 
                    end
681 
                    'd42://SLT rd,rs,rt
682 
                    begin
683 
                        //replaceID  = `SLT ;
684 
                        ext_ctl = `EXT_SIGN;
685 
                        rd_sel = `RD_RD;
686 
                        cmp_ctl = `CMP_NOP;
687 
                        pc_gen_ctl = `PC_NEXT;
688 
                        fsm_dly = `FSM_NOP;
689 
                        muxa_ctl = `MUXA_RS;
690 
                        muxb_ctl = `MUXB_RT;
691 
                        alu_func = `ALU_SLT;
692 
                        alu_we = `EN;
693 
                        dmem_ctl = `DMEM_NOP;
694 
                        wb_we =  `DIS;
695 
                        wb_mux = `WB_ALU;
696 
                        //end of `SLT ;
697 
                    end
698 
                    'd43://SLTU rd,rs,rt
699 
                    begin
700 
                        //replaceID  = `SLTU ;
701 
                        ext_ctl = `EXT_NOP;
702 
                        rd_sel = `RD_RD;
703 
                        cmp_ctl = `CMP_NOP;
704 
                        pc_gen_ctl = `PC_NEXT;
705 
                        fsm_dly = `FSM_NOP;
706 
                        muxa_ctl = `MUXA_RS;
707 
                        muxb_ctl = `MUXB_RT;
708 
                        alu_func = `ALU_SLTU;
709 
                        alu_we = `EN;
710 
                        dmem_ctl = `DMEM_NOP;
711 
                        wb_we =  `DIS;
712 
                        wb_mux = `WB_ALU;
713 
                        //end of `SLTU ;
714 
                    end
715 
                    default:
716 
                    begin
717 
                        //replaceID  = `INVALID ;
718 
                        ext_ctl = `IGN;
719 
                        rd_sel = `IGN;
720 
                        cmp_ctl = `IGN;
721 
                        pc_gen_ctl = `IGN;
722 
                        fsm_dly = `IGN;
723 
                        muxa_ctl = `IGN;
724 
                        muxb_ctl = `IGN;
725 
                        alu_func = `IGN;
726 
                        alu_we = `IGN;
727 
                        dmem_ctl = `IGN;
728 
                        wb_we =  `IGN;
729 
                        wb_mux = `IGN;
730 
                        //end of `INVALID ;
731 
                    end
732 
                endcase
733 
            end
734 
            'd1://regimm opreation
735 
            begin
736 
                case (inst_regimm) //synthesis parallel_case
737 
                    'd0://BLTZ rs,offset(signed)
738 
                    begin
739 
                        //replaceID  = `BLTZ ;
740 
                        ext_ctl = `EXT_B;
741 
                        rd_sel = `RD_NOP;
742 
                        cmp_ctl = `CMP_BLTZ;
743 
                        pc_gen_ctl = `PC_BC;
744 
                        fsm_dly = `FSM_CUR;
745 
                        muxa_ctl = `MUXA_NOP;
746 
                        muxb_ctl = `MUXB_NOP;
747 
                        alu_func = `ALU_NOP;
748 
                        alu_we = `DIS;
749 
                        dmem_ctl = `DMEM_NOP;
750 
                        wb_we =  `DIS;
751 
                        wb_mux = `WB_NOP;
752 
                        //end of `BLTZ ;
753 
                    end
754 
                    'd1://BGEZ rs,offset(signed)
755 
                    begin
756 
                        //replaceID  = `BGEZ ;
757 
                        ext_ctl = `EXT_B;
758 
                        rd_sel = `RD_NOP;
759 
                        cmp_ctl = `CMP_BGEZ;
760 
                        pc_gen_ctl = `PC_BC;
761 
                        fsm_dly = `FSM_CUR;
762 
                        muxa_ctl = `MUXA_NOP;
763 
                        muxb_ctl = `MUXB_NOP;
764 
                        alu_func = `ALU_NOP;
765 
                        alu_we = `DIS;
766 
                        dmem_ctl = `DMEM_NOP;
767 
                        wb_we =  `DIS;
768 
                        wb_mux = `WB_NOP;
769 
                        //end of `BGEZ ;
770 
                    end
771 
                    'd16://BLTZAL rs,offset(signed)
772 
                    begin
773 
                        //replaceID  = `BLTZAL ;
774 
                        ext_ctl = `IGN;
775 
                        rd_sel = `IGN;
776 
                        cmp_ctl = `IGN;
777 
                        pc_gen_ctl = `IGN;
778 
                        fsm_dly = `IGN;
779 
                        muxa_ctl = `IGN;
780 
                        muxb_ctl = `IGN;
781 
                        alu_func = `IGN;
782 
                        alu_we = `IGN;
783 
                        dmem_ctl = `IGN;
784 
                        wb_we =  `IGN;
785 
                        wb_mux = `IGN;
786 
                        //end of `BLTZAL ;
787 
                    end
788 
                    'd17://BGEZAL rs,offset(signed)
789 
                    begin
790 
                        //replaceID  = `BGEZAL ;
791 
                    end
792 
                    default:
793 
                    begin
794 
                        //replaceID   = `INVALID ;
795 
                    end
796 
                endcase
797 
            end
798 
            'd2://J imm26({pc[31:28],imm26,00})
799 
            begin
800 
                //replaceID  = `J ;
801 
                ext_ctl = `EXT_J;
802 
                rd_sel = `RD_NOP;
803 
                cmp_ctl = `CMP_NOP;
804 
                pc_gen_ctl = `PC_J;
805 
                fsm_dly = `FSM_NOI;
806 
                muxa_ctl = `MUXA_NOP;
807 
                muxb_ctl = `MUXB_NOP;
808 
                alu_func = `ALU_NOP;
809 
                alu_we = `DIS;
810 
                dmem_ctl = `DMEM_NOP;
811 
                wb_we =  `DIS;
812 
                wb_mux = `WB_NOP;
813 
                //end of `J ;
814 
            end
815 
            'd3://JAL imm26({pc[31:28],imm26,00})
816 
            begin
817 
                //replaceID  = `JAL ;
818 
                ext_ctl = `EXT_J;
819 
                rd_sel = `RD_R31;
820 
                cmp_ctl = `CMP_NOP;
821 
                pc_gen_ctl = `PC_J;
822 
                fsm_dly = `FSM_NOI;
823 
                muxa_ctl = `MUXA_PC;
824 
                muxb_ctl = `MUXB_RT;
825 
                alu_func = `ALU_PA;
826 
                alu_we = `EN;
827 
                dmem_ctl = `DMEM_NOP;
828 
                wb_we =  `DIS;
829 
                wb_mux = `WB_ALU;
830 
                //end of `JAL ;
831 
            end
832 
            'd4://BEQ rs,rt,offset(signed)
833 
            begin
834 
                //replaceID  = `BEQ ;
835 
                ext_ctl = `EXT_B;
836 
                rd_sel = `RD_NOP;
837 
                cmp_ctl = `CMP_BEQ;
838 
                pc_gen_ctl = `PC_BC;
839 
                fsm_dly = `FSM_CUR;
840 
                muxa_ctl = `MUXA_NOP;
841 
                muxb_ctl = `MUXB_NOP;
842 
                alu_func = `ALU_NOP;
843 
                alu_we = `DIS;
844 
                dmem_ctl = `DMEM_NOP;
845 
                wb_we =  `DIS;
846 
                wb_mux = `WB_NOP;
847 
                //end of `BEQ ;
848 
            end
849 
            'd5://BNE rs,rt,offset(signed)
850 
            begin
851 
                //replaceID  = `BNE ;
852 
                ext_ctl = `EXT_B;
853 
                rd_sel = `RD_NOP;
854 
                cmp_ctl = `CMP_BNE;
855 
                pc_gen_ctl = `PC_BC;
856 
                fsm_dly = `FSM_CUR;
857 
                muxa_ctl = `MUXA_NOP;
858 
                muxb_ctl = `MUXB_NOP;
859 
                alu_func = `ALU_NOP;
860 
                alu_we = `DIS;
861 
                dmem_ctl = `DMEM_NOP;
862 
                wb_we =  `DIS;
863 
                wb_mux = `WB_NOP;
864 
                //end of `BNE ;
865 
            end
866 
            'd6://BLEZ rs,offset(signed)
867 
            begin
868 
                //replaceID  = `BLEZ ;
869 
                ext_ctl = `EXT_B;
870 
                rd_sel = `RD_NOP;
871 
                cmp_ctl = `CMP_BLEZ;
872 
                pc_gen_ctl = `PC_BC;
873 
                fsm_dly = `FSM_CUR;
874 
                muxa_ctl = `MUXA_NOP;
875 
                muxb_ctl = `MUXB_NOP;
876 
                alu_func = `ALU_NOP;
877 
                alu_we = `DIS;
878 
                dmem_ctl = `DMEM_NOP;
879 
                wb_we =  `DIS;
880 
                wb_mux = `WB_NOP;
881 
                //end of `BLEZ ;
882 
            end
883 
            'd7://BGTZ rs,offset(signed)
884 
            begin
885 
                //replaceID  = `BGTZ ;
886 
                ext_ctl = `EXT_B;
887 
                rd_sel = `RD_NOP;
888 
                cmp_ctl = `CMP_BGTZ;
889 
                pc_gen_ctl = `PC_BC;
890 
                fsm_dly = `FSM_CUR;
891 
                muxa_ctl = `MUXA_NOP;
892 
                muxb_ctl = `MUXB_NOP;
893 
                alu_func = `ALU_NOP;
894 
                alu_we = `DIS;
895 
                dmem_ctl = `DMEM_NOP;
896 
                wb_we =  `DIS;
897 
                wb_mux = `WB_NOP;
898 
                //end of `BGTZ ;
899 
            end
900 
            'd8://ADDI rt,rs,imm16(singed)
901 
            begin
902 
                //replaceID  = `ADDI ;
903 
                ext_ctl = `EXT_SIGN;
904 
                rd_sel = `RD_RT;
905 
                cmp_ctl = `CMP_NOP;
906 
                pc_gen_ctl = `PC_NEXT;
907 
                fsm_dly = `FSM_NOP;
908 
                muxa_ctl = `MUXA_RS;
909 
                muxb_ctl = `MUXB_EXT;
910 
                alu_func = `ALU_ADD;
911 
                alu_we = `EN;
912 
                dmem_ctl = `DMEM_NOP;
913 
                wb_we =  `DIS;
914 
                wb_mux = `WB_ALU;
915 
                //end of `ADDI ;
916 
            end
917 
            'd9://ADDIU rt,rs,imm16(singed)
918 
            begin
919 
                //replaceID  = `ADDIU ;
920 
                ext_ctl = `EXT_SIGN;
921 
                rd_sel = `RD_RT;
922 
                cmp_ctl = `CMP_NOP;
923 
                pc_gen_ctl = `PC_NEXT;
924 
                fsm_dly = `FSM_NOP;
925 
                muxa_ctl = `MUXA_RS;
926 
                muxb_ctl = `MUXB_EXT;
927 
                alu_func = `ALU_ADD;
928 
                alu_we = `EN;
929 
                dmem_ctl = `DMEM_NOP;
930 
                wb_we =  `DIS;
931 
                wb_mux = `WB_ALU;
932 
                //end of `ADDIU ;
933 
            end
934 
            'd10://SLTI rt,rs,imm16(singed)
935 
            begin
936 
                //replaceID  = `SLTI ;
937 
                ext_ctl = `EXT_SIGN;
938 
                rd_sel = `RD_RT;
939 
                cmp_ctl = `CMP_NOP;
940 
                pc_gen_ctl = `PC_NEXT;
941 
                fsm_dly = `FSM_NOP;
942 
                muxa_ctl = `MUXA_RS;
943 
                muxb_ctl = `MUXB_EXT;
944 
                alu_func = `ALU_SLT;
945 
                alu_we = `EN;
946 
                dmem_ctl = `DMEM_NOP;
947 
                wb_we =  `DIS;
948 
                wb_mux = `WB_ALU;
949 
                //end of `SLTI ;
950 
            end
951 
            'd11://SLTIU rt,rs,imm16(singed)
952 
            begin
953 
                //replaceID  = `SLTIU ;
954 
                ext_ctl = `EXT_UNSIGN;
955 
                rd_sel = `RD_RT;
956 
                cmp_ctl = `CMP_NOP;
957 
                pc_gen_ctl = `PC_NEXT;
958 
                fsm_dly = `FSM_NOP;
959 
                muxa_ctl = `MUXA_RS;
960 
                muxb_ctl = `MUXB_EXT;
961 
                alu_func = `ALU_SLTU;
962 
                alu_we = `EN;
963 
                dmem_ctl = `DMEM_NOP;
964 
                wb_we =  `DIS;
965 
                wb_mux = `WB_ALU;
966 
                //end of `SLTIU ;
967 
            end
968 
            'd12://ANDI rt,rs,imm16(singed)
969 
            begin
970 
                //replaceID  = `ANDI ;
971 
                ext_ctl = `EXT_UNSIGN;
972 
                rd_sel = `RD_RT;
973 
                cmp_ctl = `CMP_NOP;
974 
                pc_gen_ctl = `PC_NEXT;
975 
                fsm_dly = `FSM_NOP;
976 
                muxa_ctl = `MUXA_RS;
977 
                muxb_ctl = `MUXB_EXT;
978 
                alu_func = `ALU_AND;
979 
                alu_we = `EN;
980 
                dmem_ctl = `DMEM_NOP;
981 
                wb_we =  `DIS;
982 
                wb_mux = `WB_ALU;
983 
                //end of `ANDI ;
984 
            end
985 
            'd13://ORI rt,rs,imm16(singed)
986 
            begin
987 
                //replaceID  = `ORI ;
988 
                ext_ctl = `EXT_UNSIGN;
989 
                rd_sel = `RD_RT;
990 
                cmp_ctl = `CMP_NOP;
991 
                pc_gen_ctl = `PC_NEXT;
992 
                fsm_dly = `FSM_NOP;
993 
                muxa_ctl = `MUXA_RS;
994 
                muxb_ctl = `MUXB_EXT;
995 
                alu_func = `ALU_OR;
996 
                alu_we = `EN;
997 
                dmem_ctl = `DMEM_NOP;
998 
                wb_we =  `DIS;
999 
                wb_mux = `WB_NOP;
1000 
                //end of `ORI ;
1001 
            end
1002 
            'd14://XORI rt,rs,imm16(singed)
1003 
            begin
1004 
                //replaceID  = `XORI ;
1005 
                ext_ctl = `EXT_UNSIGN;
1006 
                rd_sel = `RD_RT;
1007 
                cmp_ctl = `CMP_NOP;
1008 
                pc_gen_ctl = `PC_NEXT;
1009 
                fsm_dly = `FSM_NOP;
1010 
                muxa_ctl = `MUXA_RS;
1011 
                muxb_ctl = `MUXB_EXT;
1012 
                alu_func = `ALU_XOR;
1013 
                alu_we = `EN;
1014 
                dmem_ctl = `DMEM_NOP;
1015 
                wb_we =  `EN;
1016 
                wb_mux = `WB_ALU;
1017 
                //end of `XORI ;
1018 
            end
1019 
            'd15://LUI rt,imm16
1020 
            begin
1021 
                //replaceID  = `LUI ;
1022 
                ext_ctl = `EXT_S2H;
1023 
                rd_sel = `RD_RT;
1024 
                cmp_ctl = `CMP_NOP;
1025 
                pc_gen_ctl = `PC_NEXT;
1026 
                fsm_dly = `FSM_NOP;
1027 
                muxa_ctl = `MUXA_RS;
1028 
                muxb_ctl = `MUXB_EXT;
1029 
                alu_func = `ALU_PB;
1030 
                alu_we = `EN;
1031 
                dmem_ctl = `DMEM_NOP;
1032 
                wb_we =  `DIS;
1033 
                wb_mux = `WB_ALU;
1034 
                //end of `LUI ;
1035 
            end
1036 
            'd16://COP0 func
1037 
            begin
1038 
                case(inst_cop0_func) //synthesis parallel_case
1039 
                    'd0://mfc0 rt,rd // GPR[rd] = CPR[rt] //differ to mips32 definition
1040 
                        //read saved PC
1041 
                    begin
1042 
                        //replaceID  = `MFC0;
1043 
                        ext_ctl = `EXT_NOP;
1044 
                        rd_sel = `RD_RD;
1045 
                        cmp_ctl = `CMP_NOP;
1046 
                        pc_gen_ctl = `PC_NEXT;
1047 
                        fsm_dly = `FSM_NOP;
1048 
                        muxa_ctl = `MUXA_SPC;
1049 
                        muxb_ctl = `MUXB_EXT;
1050 
                        alu_func = `ALU_PA;
1051 
                        alu_we = `EN;
1052 
                        dmem_ctl = `DMEM_LB;
1053 
                        wb_we =  `DIS;
1054 
                        wb_mux = `WB_ALU;
1055 
                    end
1056 
 
1057 
                    'd4://mtc0 rt,rd // CPR[rd] = GPR[rt] //follow the mips32 definition
1058 
                    begin        //return from interrupt
1059 
                        //replaceID  = `MTC0;
1060 
                        ext_ctl = `EXT_NOP;
1061 
                        rd_sel = `RD_NOP;
1062 
                        cmp_ctl = `CMP_NOP;
1063 
                        pc_gen_ctl = `PC_SPC;
1064 
                        fsm_dly = `FSM_RET;
1065 
                        muxa_ctl = `MUXA_NOP;
1066 
                        muxb_ctl = `MUXB_NOP;
1067 
                        alu_func = `ALU_NOP;
1068 
                        alu_we = `DIS;
1069 
                        dmem_ctl = `DMEM_NOP;
1070 
                        wb_we =  `DIS;
1071 
                        wb_mux = `WB_NOP;
1072 
                    end
1073 
                    default:
1074 
                    begin
1075 
 
1076 
                    end
1077 
                endcase
1078 
            end
1079 
            'd32://LB rt,offset(base) (offset:signed;base:rs)
1080 
            begin
1081 
                //replaceID  = `LB ;
1082 
                ext_ctl = `EXT_SIGN;
1083 
                rd_sel = `RD_RT;
1084 
                cmp_ctl = `CMP_NOP;
1085 
                pc_gen_ctl = `PC_NEXT;
1086 
                fsm_dly = `FSM_NOP;
1087 
                muxa_ctl = `MUXA_RS;
1088 
                muxb_ctl = `MUXB_EXT;
1089 
                alu_func = `ALU_ADD;
1090 
                alu_we = `DIS;
1091 
                dmem_ctl = `DMEM_LB;
1092 
                wb_we =  `EN;
1093 
                wb_mux = `WB_MEM;
1094 
                //end of `LB ;
1095 
            end
1096 
            'd33://LH rt,offset(base) (offset:signed;base:rs)
1097 
            begin
1098 
                //replaceID  = `LH ;
1099 
                ext_ctl = `EXT_SIGN;
1100 
                rd_sel = `RD_RT;
1101 
                cmp_ctl = `CMP_NOP;
1102 
                pc_gen_ctl = `PC_NEXT;
1103 
                fsm_dly = `FSM_NOP;
1104 
                muxa_ctl = `MUXA_RS;
1105 
                muxb_ctl = `MUXB_EXT;
1106 
                alu_func = `ALU_ADD;
1107 
                alu_we = `DIS;
1108 
                dmem_ctl = `DMEM_LH;
1109 
                wb_we =  `EN;
1110 
                wb_mux = `WB_NOP;
1111 
                //end of `LH ;
1112 
            end
1113 
            'd34://LWL rt,offset(base) (offset:signed;base:rs)
1114 
            begin
1115 
                //replaceID  = `LWL ;
1116 
                ext_ctl = `IGN;
1117 
                rd_sel = `IGN;
1118 
                cmp_ctl = `IGN;
1119 
                pc_gen_ctl = `IGN;
1120 
                fsm_dly = `IGN;
1121 
                muxa_ctl = `IGN;
1122 
                muxb_ctl = `IGN;
1123 
                alu_func = `IGN;
1124 
                alu_we = `IGN;
1125 
                dmem_ctl = `IGN;
1126 
                wb_we =  `IGN;
1127 
                wb_mux = `IGN;
1128 
                //end of `LWL ;
1129 
            end
1130 
            'd35://LW rt,offset(base) (offset:signed;base:rs)
1131 
            begin
1132 
                //replaceID  = `LW ;
1133 
                ext_ctl = `EXT_SIGN;
1134 
                rd_sel = `RD_RT;
1135 
                cmp_ctl = `CMP_NOP;
1136 
                pc_gen_ctl = `PC_NEXT;
1137 
                fsm_dly = `FSM_NOP;
1138 
                muxa_ctl = `MUXA_RS;
1139 
                muxb_ctl = `MUXB_EXT;
1140 
                alu_func = `ALU_ADD;
1141 
                alu_we = `DIS;
1142 
                dmem_ctl = `DMEM_LW;
1143 
                wb_we =  `EN;
1144 
                wb_mux = `WB_MEM;
1145 
                //end of `LW ;
1146 
            end
1147 
            'd36://LBU rt,offset(base) (offset:signed;base:rs)
1148 
            begin
1149 
                //replaceID  = `LBU ;
1150 
                ext_ctl = `EXT_SIGN;
1151 
                rd_sel = `RD_RT;
1152 
                cmp_ctl = `CMP_NOP;
1153 
                pc_gen_ctl = `PC_NEXT;
1154 
                fsm_dly = `FSM_NOP;
1155 
                muxa_ctl = `MUXA_RS;
1156 
                muxb_ctl = `MUXB_EXT;
1157 
                alu_func = `ALU_ADD;
1158 
                alu_we = `DIS;
1159 
                dmem_ctl = `DMEM_LBU;
1160 
                wb_we =  `EN;
1161 
                wb_mux = `WB_MEM;
1162 
                //end of `LBU ;
1163 
            end
1164 
            'd37://LHU rt,offset(base) (offset:signed;base:rs)
1165 
            begin
1166 
                //replaceID  = `LHU ;
1167 
                ext_ctl = `EXT_SIGN;
1168 
                rd_sel = `RD_RT;
1169 
                cmp_ctl = `CMP_NOP;
1170 
                pc_gen_ctl = `PC_NEXT;
1171 
                fsm_dly = `FSM_NOP;
1172 
                muxa_ctl = `MUXA_RS;
1173 
                muxb_ctl = `MUXB_EXT;
1174 
                alu_func = `ALU_ADD;
1175 
                alu_we = `DIS;
1176 
                dmem_ctl = `DMEM_LHU;
1177 
                wb_we =  `EN;
1178 
                wb_mux = `WB_MEM;
1179 
                //end of `LHU ;
1180 
            end
1181 
            'd38://LWR rt,offset(base) (offset:signed;base:rs)
1182 
            begin
1183 
                //replaceID  = `LWR ;
1184 
                ext_ctl = `IGN;
1185 
                rd_sel = `IGN;
1186 
                cmp_ctl = `IGN;
1187 
                pc_gen_ctl = `IGN;
1188 
                fsm_dly = `IGN;
1189 
                muxa_ctl = `IGN;
1190 
                muxb_ctl = `IGN;
1191 
                alu_func = `IGN;
1192 
                alu_we = `IGN;
1193 
                dmem_ctl = `IGN;
1194 
                wb_we =  `IGN;
1195 
                wb_mux = `IGN;
1196 
                //end of `LWR ;
1197 
            end
1198 
            'd40://SB rt,offset(base) (offset:signed;base:rs)
1199 
            begin
1200 
                //replaceID  = `SB ;
1201 
                ext_ctl = `EXT_SIGN;
1202 
                rd_sel = `RD_NOP;
1203 
                cmp_ctl = `CMP_NOP;
1204 
                pc_gen_ctl = `PC_NEXT;
1205 
                fsm_dly = `FSM_NOP;
1206 
                muxa_ctl = `MUXA_RS;
1207 
                muxb_ctl = `MUXB_EXT;
1208 
                alu_func = `ALU_ADD;
1209 
                alu_we = `DIS;
1210 
                dmem_ctl = `DMEM_SB;
1211 
                wb_we =  `DIS;
1212 
                wb_mux = `WB_NOP;
1213 
                //end of `SB ;
1214 
            end
1215 
            'd41://SH rt,offset(base) (offset:signed;base:rs)
1216 
            begin
1217 
                //replaceID  = `SH ;
1218 
                ext_ctl = `EXT_SIGN;
1219 
                rd_sel = `RD_RT;
1220 
                cmp_ctl = `CMP_NOP;
1221 
                pc_gen_ctl = `PC_NEXT;
1222 
                fsm_dly = `FSM_NOP;
1223 
                muxa_ctl = `MUXA_RS;
1224 
                muxb_ctl = `MUXB_EXT;
1225 
                alu_func = `ALU_ADD;
1226 
                alu_we = `DIS;
1227 
                dmem_ctl = `DMEM_SH;
1228 
                wb_we =  `DIS;
1229 
                wb_mux = `WB_NOP;
1230 
                //end of `SH ;
1231 
            end
1232 
            'd42://SWL rt,offset(base) (offset:signed;base:rs)
1233 
            begin
1234 
                //replaceID  = `SWL ;
1235 
                ext_ctl = `IGN;
1236 
                rd_sel = `IGN;
1237 
                cmp_ctl = `IGN;
1238 
                pc_gen_ctl = `IGN;
1239 
                fsm_dly = `IGN;
1240 
                muxa_ctl = `IGN;
1241 
                muxb_ctl = `IGN;
1242 
                alu_func = `IGN;
1243 
                alu_we = `IGN;
1244 
                dmem_ctl = `IGN;
1245 
                wb_we =  `IGN;
1246 
                wb_mux = `IGN;
1247 
                //end of `SWL ;
1248 
            end
1249 
            'd43://SW rt,offset(base) (offset:signed;base:rs)
1250 
            begin
1251 
                //replaceID  = `SW ;
1252 
                ext_ctl = `EXT_SIGN;
1253 
                rd_sel = `RD_NOP;
1254 
                cmp_ctl = `CMP_NOP;
1255 
                pc_gen_ctl = `PC_NEXT;
1256 
                fsm_dly = `FSM_NOP;
1257 
                muxa_ctl = `MUXA_RS;
1258 
                muxb_ctl = `MUXB_EXT;
1259 
                alu_func = `ALU_ADD;
1260 
                alu_we = `DIS;
1261 
                dmem_ctl = `DMEM_SW;
1262 
                wb_we =  `DIS;
1263 
                wb_mux = `WB_NOP;
1264 
                //end of `SW ;
1265 
            end
1266 
            'd46://SWR rt,offset(base) (offset:signed;base:rs)
1267 
            begin
1268 
                //replaceID  = `SWR ;
1269 
                ext_ctl = `IGN;
1270 
                rd_sel = `IGN;
1271 
                cmp_ctl = `IGN;
1272 
                pc_gen_ctl = `IGN;
1273 
                fsm_dly = `IGN;
1274 
                muxa_ctl = `IGN;
1275 
                muxb_ctl = `IGN;
1276 
                alu_func = `IGN;
1277 
                alu_we = `IGN;
1278 
                dmem_ctl = `IGN;
1279 
                wb_we =  `IGN;
1280 
                wb_mux = `IGN;
1281 
                //end of `SWR ;
1282 
            end
1283 
            default:
1284 
            begin
1285 
                //replaceID   = `INVALID ;
1286 
            end
1287 
        endcase
1288 
    end
1289 
endmodule

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