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[/] [mips789/] [tags/] [v001/] [verilog/] [mips_core/] [mem_ctl.v] - Blame information for rev 62

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1 2 mcupro 
/////////////////////////////////////////////////////////////////////
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////  Author: Liwei                                              ////
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////                                                             ////
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////                                                             ////
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////  If you encountered any problem, please contact :           ////
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////  Email: mcupro@yahoo.com.hk or mcupro@opencores.org         ////
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////                                                             ////
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////  Downloaded from:                                           ////
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////     http://www.opencores.org/pdownloads.cgi/list/mips789    ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2006-2007 Liwei                               ////
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////                         mcupro@yahoo.com.hk                 ////
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////                                                             ////
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////                                                             ////
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//// This source file may be used and distributed freely without ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and any derivative work contains the  ////
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//// original copyright notice and the associated disclaimer.    ////
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////                                                             ////
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//// Please let the author know if it is used                    ////
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//// for commercial purpose.                                     ////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////                                                             ////
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//// Date of Creation: 2007.8.1                                  ////
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////                                                             ////
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//// Version: 0.0.1                                              ////
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////                                                             ////
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//// Description:                                                ////
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////                                                             ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Change log:                                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`define DMEM_SB    1
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`define DMEM_LBS   2
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`define DMEM_LB    3
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`define DMEM_LBU   4
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`define DMEM_SW    5
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`define DMEM_LW    6
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`define DMEM_SH    7
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`define DMEM_LHS   8
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`define DMEM_LH    9
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`define DMEM_LHU   10
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`define DMEM_NOP   0
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module infile_dmem_ctl_reg(
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        input clk,
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        input [3:0]ctl_i,
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        input [31:0]dmem_addr_i,
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        output reg [1:0]byte_addr_o,
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        output reg [3:0]ctl_o
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    );
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    wire   [1:0]byte_addr_i;
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    assign byte_addr_i = dmem_addr_i[1:0] ;
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    always @(posedge clk)
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    begin
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        ctl_o<=(dmem_addr_i[31]==0)?ctl_i:0;
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        byte_addr_o<=byte_addr_i;
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    end
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endmodule
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module mem_addr_ctl(
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        input [3:0]ctl,
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        input [31:0]addr_i,
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        output reg[3:0]wr_en
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    );
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    always@(*)
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    case (ctl)
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        `DMEM_SB:
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        begin
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            case(addr_i[1:0])
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                0:wr_en = 4'b1000;
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                1:wr_en = 4'b0100;
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                2:wr_en = 4'b0010;
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                3:wr_en = 4'b0001;
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            endcase
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        end
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        `DMEM_SH  :
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        begin
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            case(addr_i[1:0])
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                'd0:wr_en=4'b1100;
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                'd2:wr_en=4'b0011;
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            endcase
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        end
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        `DMEM_SW :
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        begin
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            wr_en=4'b1111;
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        end
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        default wr_en=4'b0000;
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    endcase
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endmodule
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module mem_dout_ctl(
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        input [1:0]byte_addr,
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        input [3:0]ctl,
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        input [31:0] din,
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        output reg [31:0] dout
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    );
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    always @(*)
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    case (ctl)
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        `DMEM_LBS :
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        case (byte_addr)
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            'd0:dout={{24{din[31]}},din[31:24]};
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            'd1:dout={{24{din[23]}},din[23:16]};
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            'd2:dout={{24{din[15]}},din[15:8]};
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            'd3:dout={{24{din[7]}},din[7:0] };
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            default :
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                dout=32'b0;
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        endcase//checked
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        `DMEM_LBU :
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        case (byte_addr)
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            'd3:dout={24'b0,din[7:0]};
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            'd2:dout={24'b0,din[15:8]};
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            'd1:dout={24'b0,din[23:16]};
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            'd0:dout={24'b0,din[31:24]};
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            default :
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                dout=32'b0;
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        endcase
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        `DMEM_LHU :
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        case (byte_addr)
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            'd0:dout={16'b0,din[23:16],din[31:24]};
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            'd2:dout={16'b0,din[7:0],din[15:8]};
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        endcase
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        `DMEM_LHS :
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        case (byte_addr)
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            'd0 :dout={{16{din[23]}},din[23:16],din[31:24]};
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            'd2 :dout={{16{din[7 ]}},din[7 :0],din[15:8]};
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            default:dout=0;
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        endcase
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        `DMEM_LW  :
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            dout=din;
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        default :
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            dout=32'b0;
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    endcase
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endmodule
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module mem_din_ctl(
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        input [3:0]ctl,
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        input [31:0]din,
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        output reg [31:0]dout
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    );
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    always @(*)
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    case (ctl)
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        `DMEM_SB   :
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            dout={din[7:0],din[7:0],din[7:0],din[7:0]};
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        `DMEM_SH   :
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            dout = {din[15:0],din[15:0]};
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        `DMEM_SW   :
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            dout =din;
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        default dout=din;
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    endcase
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endmodule
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/*
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ex. 1,
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unsigned short a[4]={0,1,2,3};
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00000001
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00020003
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ex. 2
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unsigned char a[4]={0,1,2,3};
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00010203
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ex.  3
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unsigned int b[3]={0x12345678,0,0x12345678};
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12345678
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00000000
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12345678
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*/

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