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[/] [mips789/] [tags/] [v001/] [verilog/] [mips_core/] [ram_module.v] - Blame information for rev 59

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/////////////////////////////////////////////////////////////////////
////  Author: Liwei                                              ////
////                                                             ////
////                                                             ////
////  If you encountered any problem, please contact :           ////
////  Email: mcupro@yahoo.com.hk or mcupro@opencores.org         ////
////                                                             ////
////  Downloaded from:                                           ////
////     http://www.opencores.org/pdownloads.cgi/list/mips789    ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2007 Liwei                               ////
////                         mcupro@yahoo.com.hk                 ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// Please let the author know if it is used                    ////
//// for commercial purpose.                                     ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Date of Creation: 2007.8.1                                  ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
//// Description:                                                ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
`define DEBUG
 
module mem_array
    (
        input clk,
        input [31:0] pc_i,
        output [31:0] ins_o,
        input [3:0] wren,
        input [31:0]din,
        input [31:0]wr_addr_i,
        input [31:0]rd_addr_i,
        output [31:0]dout
    );
    wire [31:0] rd_addr,pc,wr_addr;
    wire [31:0]dout_w;
    assign dout = dout_w;
    assign rd_addr=rd_addr_i[31:2];
    assign wr_addr=wr_addr_i[31:2];
    assign pc= pc_i[31:2];
 
`ifdef DEBUG
 
    sim_syn_ram3 ram3 (
                     .data(din[31:31-7]),
                     .wraddress(wr_addr),
                     .rdaddress_a(pc),
                     .rdaddress_b(rd_addr),
                     .wren(wren[3]),
                     .clock(clk),
                     .qa(ins_o[31:31-7]),
                     .qb(dout_w[31:31-7])
                 );
 
    sim_syn_ram2 ram2(
                     .data(din[31-8:31-8-7]),
                     .wraddress(wr_addr),
                     .rdaddress_a(pc),
                     .rdaddress_b(rd_addr),
                     .wren(wren[2]),
                     .clock(clk),
                     .qa(ins_o[31-8:31-8-7]),
                     .qb(dout_w[31-8:31-7-8])
                 );
 
    sim_syn_ram1 ram1(
                     .data(din[31-16:31-16-7]),
                     .wraddress(wr_addr),
                     .rdaddress_a(pc),
                     .rdaddress_b(rd_addr),
                     .wren(wren[1]),
                     .clock(clk),
                     .qa(ins_o[31-16:31-7-16]),
                     .qb(dout_w[31-16:31-7-16])
                 );
 
    sim_syn_ram0 ram0(
                     .data(din[31-24:31-7-24]),
                     .wraddress(wr_addr),
                     .rdaddress_a(pc),
                     .rdaddress_b(rd_addr),
                     .wren(wren[0]),
                     .clock(clk),
                     .qa(ins_o[31-24:31-7-24]),
                     .qb(dout_w[31-24:31-7-24])
                 );
 
 
`else
    ram4096x8_3 ram3(
                    .data_a(32'b0),
                    .wren_a(1'b0),
                    .address_a(32'b0),
                    .data_b(din[31:24]),
                    .address_b(wr_addr),
                    .wren_b(wren[3]),
                    .clock(clk),
                    .q_a(ins_o[31:24]),
                    .q_b(dout_w[31:24])
                );
 
    ram4096x8_2 ram2(
                    .data_a(32'b0),
                    .wren_a(1'b0),
                    .address_a(32'b0),
                    .data_b(din[23:16]),
                    .address_b(wr_addr),
                    .wren_b(wren[2]),
                    .clock(clk),
                    .q_a(ins_o[23:16]),
                    .q_b(dout_w[23:16])
                );
 
    ram4096x8_1 ram1(
                    .data_a(32'b0),
                    .wren_a(1'b0),
                    .address_a(32'b0),
                    .data_b(din[15:8]),
                    .address_b(wr_addr),
                    .wren_b(wren[1]),
                    .clock(clk),
                    .q_a(ins_o[15:8]),
                    .q_b(dout_w[15:8])
                );
 
    ram4096x8_0 ram0(
                    .data_a(32'b0),
                    .wren_a(1'b0),
                    .address_a(32'b0),
                    .data_b(din[7:0]),
                    .address_b(wr_addr),
                    .wren_b(wren[0]),
                    .clock(clk),
                    .q_a(ins_o[7:0]),
                    .q_b(dout_w[7:0])
                );
`endif
 
endmodule
 

Line No.	Rev	Author	Line
1	2	mcupro	`/////////////////////////////////////////////////////////////////////`
2			`//// Author: Liwei ////`
3			`//// ////`
4			`//// ////`
5			`//// If you encountered any problem, please contact : ////`
6			`//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////`
7			`//// ////`
8			`//// Downloaded from: ////`
9			`//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2006-2007 Liwei ////`
13			`//// mcupro@yahoo.com.hk ////`
14			`//// ////`
15			`//// ////`
16			`//// This source file may be used and distributed freely without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and any derivative work contains the ////`
19			`//// original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// Please let the author know if it is used ////`
22			`//// for commercial purpose. ////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39			`//// ////`
40			`//// ////`
41			`//// Date of Creation: 2007.8.1 ////`
42			`//// ////`
43			`//// Version: 0.0.1 ////`
44			`//// ////`
45			`//// Description: ////`
46			`//// ////`
47			`//// ////`
48			`/////////////////////////////////////////////////////////////////////`
49			`//// ////`
50			`//// Change log: ////`
51			`//// ////`
52			`/////////////////////////////////////////////////////////////////////`
53
54			`define DEBUG
55
56			`module mem_array`
57			`(`
58			`input clk,`
59			`input [31:0] pc_i,`
60			`output [31:0] ins_o,`
61			`input [3:0] wren,`
62			`input [31:0]din,`
63			`input [31:0]wr_addr_i,`
64			`input [31:0]rd_addr_i,`
65			`output [31:0]dout`
66			`);`
67			`wire [31:0] rd_addr,pc,wr_addr;`
68			`wire [31:0]dout_w;`
69			`assign dout = dout_w;`
70			`assign rd_addr=rd_addr_i[31:2];`
71			`assign wr_addr=wr_addr_i[31:2];`
72			`assign pc= pc_i[31:2];`
73
74			`ifdef DEBUG
75
76			`sim_syn_ram3 ram3 (`
77			`.data(din[31:31-7]),`
78			`.wraddress(wr_addr),`
79			`.rdaddress_a(pc),`
80			`.rdaddress_b(rd_addr),`
81			`.wren(wren[3]),`
82			`.clock(clk),`
83			`.qa(ins_o[31:31-7]),`
84			`.qb(dout_w[31:31-7])`
85			`);`
86
87			`sim_syn_ram2 ram2(`
88			`.data(din[31-8:31-8-7]),`
89			`.wraddress(wr_addr),`
90			`.rdaddress_a(pc),`
91			`.rdaddress_b(rd_addr),`
92			`.wren(wren[2]),`
93			`.clock(clk),`
94			`.qa(ins_o[31-8:31-8-7]),`
95			`.qb(dout_w[31-8:31-7-8])`
96			`);`
97
98			`sim_syn_ram1 ram1(`
99			`.data(din[31-16:31-16-7]),`
100			`.wraddress(wr_addr),`
101			`.rdaddress_a(pc),`
102			`.rdaddress_b(rd_addr),`
103			`.wren(wren[1]),`
104			`.clock(clk),`
105			`.qa(ins_o[31-16:31-7-16]),`
106			`.qb(dout_w[31-16:31-7-16])`
107			`);`
108
109			`sim_syn_ram0 ram0(`
110			`.data(din[31-24:31-7-24]),`
111			`.wraddress(wr_addr),`
112			`.rdaddress_a(pc),`
113			`.rdaddress_b(rd_addr),`
114			`.wren(wren[0]),`
115			`.clock(clk),`
116			`.qa(ins_o[31-24:31-7-24]),`
117			`.qb(dout_w[31-24:31-7-24])`
118			`);`
119
120
121			`else
122			`ram4096x8_3 ram3(`
123			`.data_a(32'b0),`
124			`.wren_a(1'b0),`
125			`.address_a(32'b0),`
126			`.data_b(din[31:24]),`
127			`.address_b(wr_addr),`
128			`.wren_b(wren[3]),`
129			`.clock(clk),`
130			`.q_a(ins_o[31:24]),`
131			`.q_b(dout_w[31:24])`
132			`);`
133
134			`ram4096x8_2 ram2(`
135			`.data_a(32'b0),`
136			`.wren_a(1'b0),`
137			`.address_a(32'b0),`
138			`.data_b(din[23:16]),`
139			`.address_b(wr_addr),`
140			`.wren_b(wren[2]),`
141			`.clock(clk),`
142			`.q_a(ins_o[23:16]),`
143			`.q_b(dout_w[23:16])`
144			`);`
145
146			`ram4096x8_1 ram1(`
147			`.data_a(32'b0),`
148			`.wren_a(1'b0),`
149			`.address_a(32'b0),`
150			`.data_b(din[15:8]),`
151			`.address_b(wr_addr),`
152			`.wren_b(wren[1]),`
153			`.clock(clk),`
154			`.q_a(ins_o[15:8]),`
155			`.q_b(dout_w[15:8])`
156			`);`
157
158			`ram4096x8_0 ram0(`
159			`.data_a(32'b0),`
160			`.wren_a(1'b0),`
161			`.address_a(32'b0),`
162			`.data_b(din[7:0]),`
163			`.address_b(wr_addr),`
164			`.wren_b(wren[0]),`
165			`.clock(clk),`
166			`.q_a(ins_o[7:0]),`
167			`.q_b(dout_w[7:0])`
168			`);`
169			`endif
170
171			`endmodule`
172

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[/] [mips789/] [tags/] [v001/] [verilog/] [mips_core/] [ram_module.v] - Blame information for rev 59