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[/] [mips789/] [trunk/] [core/] [decode_pipe.v] - Blame information for rev 64

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1 64 mcupro 
/******************************************************************
2 
 *                                                                *
3 
 *    Author: Liwei                                               *
4 
 *                                                                *
5 
 *    This file is part of the "mips789" project.                 *
6 
 *    Downloaded from:                                            *
7 
 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
8 
 *                                                                *
9 
 *    If you encountered any problem, please contact me via       *
10 
 *    Email:mcupro@opencores.org  or mcupro@163.com               *
11 
 *                                                                *
12 
 ******************************************************************/
13 
 
14 
`include "mips789_defs.v"
15 
module decoder(
16 
        input [31:0]ins_i,
17 
        output reg [`EXT_CTL_LEN-1:0] ext_ctl,
18 
        output reg [`RD_SEL_LEN-1:0] rd_sel,
19 
        output reg [`CMP_CTL_LEN-1:0]cmp_ctl,
20 
        output reg [`PC_GEN_CTL_LEN-1:0]pc_gen_ctl,
21 
        output reg [`FSM_CTL_LEN-1:0]fsm_dly,
22 
        output reg [`MUXA_CTL_LEN-1:0]muxa_ctl,
23 
        output reg [`MUXB_CTL_LEN-1:0]muxb_ctl,
24 
        output reg [`ALU_FUNC_LEN-1:0]alu_func,
25 
        output reg [`DMEM_CTL_LEN-1:0]dmem_ctl,
26 
        output reg [`ALU_WE_LEN-1:0] alu_we,
27 
        output reg [`WB_MUX_CTL_LEN-1:0]wb_mux,
28 
        output reg [`WB_WE_LEN-1:0]wb_we
29 
    );
30 
 
31 
    wire [5:0]  inst_op,inst_func;
32 
    wire [4:0]  inst_regimm;//,inst_rs,inst_rt,inst_rd,inst_sa;
33 
    wire [4:0]  inst_cop0_func;//cop0's function code filed
34 
    wire [25:0] inst_cop0_code;//cop0's code field
35 
 
36 
    assign inst_op        = ins_i[31:26];
37 
    assign inst_func      = ins_i[5:0];
38 
    assign inst_regimm    = ins_i[20:16];
39 
    assign inst_cop0_func = ins_i[25:21];
40 
    assign inst_cop0_code = ins_i[25:0];
41 
 
42 
    always @(*)
43 
    begin
44 
        case (inst_op)//synthesis parallel_case
45 
            'd0://special operation
46 
            begin
47 
                case (inst_func) //synthesis parallel_case
48 
                    'd0://SLL rd,rt,sa
49 
                    begin
50 
                        //replaceID  = `SLL ;
51 
                        ext_ctl = `EXT_SA;
52 
                        rd_sel = `RD_RD;
53 
                        cmp_ctl = `CMP_NOP;
54 
                        pc_gen_ctl = `PC_NEXT;
55 
                        fsm_dly = `FSM_NOP;
56 
                        muxa_ctl = `MUXA_EXT;
57 
                        muxb_ctl = `MUXB_RT;
58 
                        alu_func = `ALU_SLL;
59 
                        alu_we = `EN;
60 
                        dmem_ctl = `DMEM_NOP;
61 
                        wb_we =  `DIS;
62 
                        wb_mux = `WB_ALU;
63 
                        //end of `SLL ;
64 
                    end
65 
                    'd2://SRL rd,rt,sa
66 
                    begin
67 
                        //replaceID  = `SRL ;
68 
                        ext_ctl = `EXT_SA;
69 
                        rd_sel = `RD_RD;
70 
                        cmp_ctl = `CMP_NOP;
71 
                        pc_gen_ctl = `PC_NEXT;
72 
                        fsm_dly = `FSM_NOP;
73 
                        muxa_ctl = `MUXA_EXT;
74 
                        muxb_ctl = `MUXB_RT;
75 
                        alu_func = `ALU_SRL;
76 
                        alu_we = `EN;
77 
                        dmem_ctl = `DMEM_NOP;
78 
                        wb_we =  `DIS;
79 
                        wb_mux = `WB_ALU;
80 
                        //end of `SRL ;
81 
                    end
82 
                    'd3://SRA rd,rt,sa
83 
                    begin
84 
                        //replaceID  = `SRA ;
85 
                        ext_ctl = `EXT_SA;
86 
                        rd_sel = `RD_RD;
87 
                        cmp_ctl = `CMP_NOP;
88 
                        pc_gen_ctl = `PC_NEXT;
89 
                        fsm_dly = `FSM_NOP;
90 
                        muxa_ctl = `MUXA_EXT;
91 
                        muxb_ctl = `MUXB_RT;
92 
                        alu_func = `ALU_SRA;
93 
                        alu_we = `EN;
94 
                        dmem_ctl = `DMEM_NOP;
95 
                        wb_we =  `DIS;
96 
                        wb_mux = `WB_ALU;
97 
                        //end of `SRA ;
98 
                    end
99 
                    'd4://SLLV rd,rt,rs
100 
                    begin
101 
                        //replaceID  = `SLLV ;
102 
                        ext_ctl = `IGN;
103 
                        rd_sel = `IGN;
104 
                        cmp_ctl = `IGN;
105 
                        pc_gen_ctl = `IGN;
106 
                        fsm_dly = `IGN;
107 
                        muxa_ctl = `IGN;
108 
                        muxb_ctl = `IGN;
109 
                        alu_func = `IGN;
110 
                        alu_we = `IGN;
111 
                        dmem_ctl = `IGN;
112 
                        wb_we =  `IGN;
113 
                        wb_mux = 1'bx;//`IGN;
114 
                        //end of `SLLV ;
115 
                    end
116 
                    'd6://SRLV rd,rt,rs
117 
                    begin
118 
                        //replaceID  = `SRLV ;
119 
                        ext_ctl = `IGN;
120 
                        rd_sel = `IGN;
121 
                        cmp_ctl = `IGN;
122 
                        pc_gen_ctl = `IGN;
123 
                        fsm_dly = `IGN;
124 
                        muxa_ctl = `IGN;
125 
                        muxb_ctl = `IGN;
126 
                        alu_func = `IGN;
127 
                        alu_we = `IGN;
128 
                        dmem_ctl = `IGN;
129 
                        wb_we =  `IGN;
130 
                        wb_mux = `IGN;
131 
                        //end of `SRLV ;
132 
                    end
133 
                    'd7://SRAV rd,rt,rs
134 
                    begin
135 
                        //replaceID  = `SRAV ;
136 
                        ext_ctl = `IGN;
137 
                        rd_sel = `IGN;
138 
                        cmp_ctl = `IGN;
139 
                        pc_gen_ctl = `IGN;
140 
                        fsm_dly = `IGN;
141 
                        muxa_ctl = `IGN;
142 
                        muxb_ctl = `IGN;
143 
                        alu_func = `IGN;
144 
                        alu_we = `IGN;
145 
                        dmem_ctl = `IGN;
146 
                        wb_we =  `IGN;
147 
                        wb_mux = `IGN;
148 
                        //end of `SRAV ;
149 
                    end
150 
                    'd8://JR rs
151 
                    begin
152 
                        //replaceID  = `JR ;
153 
                        ext_ctl = `EXT_NOP;
154 
                        rd_sel = `RD_NOP;
155 
                        cmp_ctl = `CMP_NOP;
156 
                        pc_gen_ctl = `PC_JR;
157 
                        fsm_dly = `FSM_CUR;
158 
                        muxa_ctl = `MUXA_NOP;
159 
                        muxb_ctl = `MUXB_NOP;
160 
                        alu_func = `ALU_NOP;
161 
                        alu_we = `DIS;
162 
                        dmem_ctl = `DMEM_NOP;
163 
                        wb_we =  `DIS;
164 
                        wb_mux = `WB_NOP;
165 
                        //end of `JR ;
166 
                    end
167 
                    'd9://JALR jalr rs(rd=31) or jalr rd,rs
168 
                    begin
169 
                        //replaceID  = `JALR ;
170 
                        ext_ctl = `IGN;
171 
                        rd_sel = `IGN;
172 
                        cmp_ctl = `IGN;
173 
                        pc_gen_ctl = `IGN;
174 
                        fsm_dly = `IGN;
175 
                        muxa_ctl = `IGN;
176 
                        muxb_ctl = `IGN;
177 
                        alu_func = `IGN;
178 
                        alu_we = `IGN;
179 
                        dmem_ctl = `IGN;
180 
                        wb_we =  `IGN;
181 
                        wb_mux = `IGN;
182 
                        //end of `JALR ;
183 
                    end
184 
                    'd12://SYSCALL
185 
                    begin
186 
                        //replaceID  = `SYSCALL ;
187 
                        ext_ctl = `IGN;
188 
                        rd_sel = `IGN;
189 
                        cmp_ctl = `IGN;
190 
                        pc_gen_ctl = `IGN;
191 
                        fsm_dly = `IGN;
192 
                        muxa_ctl = `IGN;
193 
                        muxb_ctl = `IGN;
194 
                        alu_func = `IGN;
195 
                        alu_we = `IGN;
196 
                        dmem_ctl = `IGN;
197 
                        wb_we =  `IGN;
198 
                        wb_mux = `IGN;
199 
                        //end of `SYSCALL ;
200 
                    end
201 
                    'd13://BREAK
202 
                    begin
203 
                        //replaceID  = `BREAK ;
204 
                        ext_ctl = `IGN;
205 
                        rd_sel = `IGN;
206 
                        cmp_ctl = `IGN;
207 
                        pc_gen_ctl = `IGN;
208 
                        fsm_dly = `IGN;
209 
                        muxa_ctl = `IGN;
210 
                        muxb_ctl = `IGN;
211 
                        alu_func = `IGN;
212 
                        alu_we = `IGN;
213 
                        dmem_ctl = `IGN;
214 
                        wb_we =  `IGN;
215 
                        wb_mux = `IGN;
216 
                        //end of `BREAK ;
217 
                    end
218 
                    'd16://MFHI rd
219 
                    begin
220 
                        //replaceID  = `MFHI ;
221 
                        ext_ctl = `EXT_NOP;
222 
                        rd_sel = `RD_RD;
223 
                        cmp_ctl = `CMP_NOP;
224 
                        pc_gen_ctl = `PC_NEXT;
225 
                        fsm_dly = `FSM_NOP;
226 
                        muxa_ctl = `MUXA_NOP;
227 
                        muxb_ctl = `MUXB_NOP;
228 
                        alu_func = `ALU_MFHI;
229 
                        alu_we = `EN;
230 
                        dmem_ctl = `DMEM_NOP;
231 
                        wb_we =  `DIS;
232 
                        wb_mux = `WB_ALU;
233 
                        //end of `MFHI ;
234 
                    end
235 
                    'd17://MTHI rs
236 
                    begin
237 
                        //replaceID  = `MTHI ;
238 
                        ext_ctl = `EXT_NOP      ;
239 
                        rd_sel = `RD_NOP;
240 
                        cmp_ctl = `CMP_NOP;
241 
                        pc_gen_ctl = `PC_NEXT;
242 
                        fsm_dly = `FSM_NOP;
243 
                        muxa_ctl = `MUXA_RS;
244 
                        muxb_ctl = `MUXB_NOP;
245 
                        alu_func = `ALU_MTHI;
246 
                        alu_we = `DIS;
247 
                        dmem_ctl = `DMEM_NOP;
248 
                        wb_we =  `DIS;
249 
                        wb_mux = `WB_NOP;
250 
                        //end of `MTHI ;
251 
                    end
252 
                    'd18://MFLO rd
253 
                    begin
254 
                        //replaceID  = `MFLO ;
255 
                        ext_ctl = `EXT_NOP      ;
256 
                        rd_sel = `RD_RD;
257 
                        cmp_ctl = `CMP_NOP;
258 
                        pc_gen_ctl = `PC_NEXT;
259 
                        fsm_dly = `FSM_NOP;
260 
                        muxa_ctl = `MUXA_NOP;
261 
                        muxb_ctl = `MUXB_NOP;
262 
                        alu_func = `ALU_MFLO;
263 
                        alu_we = `EN;
264 
                        dmem_ctl = `DMEM_NOP;
265 
                        wb_we =  `DIS;
266 
                        wb_mux = `WB_ALU;
267 
                        //end of `MFLO ;
268 
                    end
269 
                    'd19://MTLO rs
270 
                    begin
271 
                        //replaceID  = `MTLO ;
272 
                        ext_ctl = `EXT_NOP      ;
273 
                        rd_sel = `RD_NOP;
274 
                        cmp_ctl = `CMP_NOP;
275 
                        pc_gen_ctl = `PC_NEXT;
276 
                        fsm_dly = `FSM_NOP;
277 
                        muxa_ctl = `MUXA_NOP;
278 
                        muxb_ctl = `MUXB_NOP;
279 
                        alu_func = `ALU_MFLO;
280 
                        alu_we = `DIS;
281 
                        dmem_ctl = `DMEM_NOP;
282 
                        wb_we =  `DIS;
283 
                        wb_mux = `WB_NOP;
284 
 
285 
                        //end of `MTLO ;
286 
                    end
287 
                    'd24://MULT rs,rt
288 
                    begin
289 
                        //replaceID  = `MULT ;
290 
                        ext_ctl = `EXT_NOP;
291 
                        rd_sel = `RD_NOP;
292 
                        cmp_ctl = `CMP_NOP;
293 
                        pc_gen_ctl = `PC_NEXT;
294 
                        fsm_dly = `FSM_MUL;
295 
                        muxa_ctl = `MUXA_RS;
296 
                        muxb_ctl = `MUXB_RT;
297 
                        alu_func = `ALU_MULT;
298 
                        alu_we = `DIS;
299 
                        dmem_ctl = `DMEM_NOP;
300 
                        wb_we =  `DIS;
301 
                        wb_mux = `WB_NOP;
302 
                        //end of `MULT ;
303 
                    end
304 
                    'd25://MULTU rs,rt
305 
                    begin
306 
                        //replaceID  = `MULTU ;
307 
                        ext_ctl = `EXT_NOP;
308 
                        rd_sel = `RD_NOP;
309 
                        cmp_ctl = `CMP_NOP;
310 
                        pc_gen_ctl = `PC_NEXT;
311 
                        fsm_dly = `FSM_MUL;
312 
                        muxa_ctl = `MUXA_RS;
313 
                        muxb_ctl = `MUXB_RT;
314 
                        alu_func = `ALU_MULTU;
315 
                        alu_we = `DIS;
316 
                        dmem_ctl = `DMEM_NOP;
317 
                        wb_we =  `DIS;
318 
                        wb_mux = `WB_NOP;
319 
                        //end of `MULTU ;
320 
                    end
321 
                    'd26://DIV rs,rt
322 
                    begin
323 
                        //replaceID  = `DIV ;
324 
                        ext_ctl = `EXT_NOP;
325 
                        rd_sel = `RD_NOP;
326 
                        cmp_ctl = `CMP_NOP;
327 
                        pc_gen_ctl = `PC_NEXT;
328 
                        fsm_dly = `FSM_MUL;
329 
                        muxa_ctl = `MUXA_RS;
330 
                        muxb_ctl = `MUXB_RT;
331 
                        alu_func = `ALU_DIV;
332 
                        alu_we = `DIS;
333 
                        dmem_ctl = `DMEM_NOP;
334 
                        wb_we =  `DIS;
335 
                        wb_mux = `WB_NOP;
336 
                        //end of `DIV ;
337 
                    end
338 
                    'd27://DIVU rs,rt
339 
                    begin
340 
                        //replaceID  = `DIVU ;
341 
                        ext_ctl = `EXT_NOP;
342 
                        rd_sel = `RD_NOP;
343 
                        cmp_ctl = `CMP_NOP;
344 
                        pc_gen_ctl = `PC_NEXT;
345 
                        fsm_dly = `FSM_MUL;
346 
                        muxa_ctl = `MUXA_RS;
347 
                        muxb_ctl = `MUXB_RT;
348 
                        alu_func = `ALU_DIVU;
349 
                        alu_we = `DIS;
350 
                        dmem_ctl = `DMEM_NOP;
351 
                        wb_we =  `DIS;
352 
                        wb_mux = `WB_NOP;
353 
                        //end of `DIVU ;
354 
                    end
355 
                    'd32://ADD rd,rs,rt
356 
                    begin
357 
                        //replaceID  = `ADD ;
358 
                        ext_ctl = `EXT_NOP;
359 
                        rd_sel = `RD_RD;
360 
                        cmp_ctl = `CMP_NOP;
361 
                        pc_gen_ctl = `PC_NEXT;
362 
                        fsm_dly = `FSM_NOP;
363 
                        muxa_ctl = `MUXA_RS;
364 
                        muxb_ctl = `MUXB_RT;
365 
                        alu_func = `ALU_ADD;
366 
                        alu_we = `EN;
367 
                        dmem_ctl = `DMEM_NOP;
368 
                        wb_we =  `DIS;
369 
                        wb_mux = `WB_ALU;
370 
                        //end of `ADD ;
371 
                    end
372 
                    'd33://ADDU rd,rs,rt
373 
                    begin
374 
                        //replaceID  = `ADDU ;
375 
                        ext_ctl = `EXT_NOP;
376 
                        rd_sel = `RD_RD;
377 
                        cmp_ctl = `CMP_NOP;
378 
                        pc_gen_ctl = `PC_NEXT;
379 
                        fsm_dly = `FSM_NOP;
380 
                        muxa_ctl = `MUXA_RS;
381 
                        muxb_ctl = `MUXB_RT;
382 
                        alu_func = `ALU_ADD;
383 
                        alu_we = `EN;
384 
                        dmem_ctl = `DMEM_NOP;
385 
                        wb_we =  `DIS;
386 
                        wb_mux = `WB_ALU;
387 
                        //end of `ADDU ;
388 
                    end
389 
                    'd34://SUB rd,rs,rt
390 
                    begin
391 
                        //replaceID  = `SUB ;
392 
                        ext_ctl = `EXT_NOP;
393 
                        rd_sel = `RD_RD;
394 
                        cmp_ctl = `CMP_NOP;
395 
                        pc_gen_ctl = `PC_NEXT;
396 
                        fsm_dly = `FSM_NOP;
397 
                        muxa_ctl = `MUXA_RS;
398 
                        muxb_ctl = `MUXB_RT;
399 
                        alu_func = `ALU_SUB;
400 
                        alu_we = `EN;
401 
                        dmem_ctl = `DMEM_NOP;
402 
                        wb_we =  `DIS;
403 
                        wb_mux = `WB_ALU;
404 
                        //end of `SUB ;
405 
                    end
406 
                    'd35://SUBU rd,rs,rt
407 
                    begin
408 
                        //replaceID  = `SUBU ;
409 
                        ext_ctl = `EXT_NOP;
410 
                        rd_sel = `RD_RD;
411 
                        cmp_ctl = `CMP_NOP;
412 
                        pc_gen_ctl = `PC_NEXT;
413 
                        fsm_dly = `FSM_NOP;
414 
                        muxa_ctl = `MUXA_RS;
415 
                        muxb_ctl = `MUXB_RT;
416 
                        alu_func = `ALU_SUBU;
417 
                        alu_we = `EN;
418 
                        dmem_ctl = `DMEM_NOP;
419 
                        wb_we =  `DIS;
420 
                        wb_mux = `WB_ALU;
421 
                        //end of `SUBU ;
422 
                    end
423 
                    'd36://AND rd,rs,rt
424 
                    begin
425 
                        //replaceID  = `AND ;
426 
                        ext_ctl = `EXT_NOP;
427 
                        rd_sel = `RD_RD;
428 
                        cmp_ctl = `CMP_NOP;
429 
                        pc_gen_ctl = `PC_NEXT;
430 
                        fsm_dly = `FSM_NOP;
431 
                        muxa_ctl = `MUXA_RS;
432 
                        muxb_ctl = `MUXB_RT;
433 
                        alu_func = `ALU_AND;
434 
                        alu_we = `EN;
435 
                        dmem_ctl = `DMEM_NOP;
436 
                        wb_we =  `DIS;
437 
                        wb_mux = `WB_ALU;
438 
                        //end of `AND ;
439 
                    end
440 
                    'd37://OR rd,rs,rt
441 
                    begin
442 
                        //replaceID  = `OR ;
443 
                        ext_ctl = `EXT_NOP;
444 
                        rd_sel = `RD_RD;
445 
                        cmp_ctl = `CMP_NOP;
446 
                        pc_gen_ctl = `PC_NEXT;
447 
                        fsm_dly = `FSM_NOP;
448 
                        muxa_ctl = `MUXA_RS;
449 
                        muxb_ctl = `MUXB_RT;
450 
                        alu_func = `ALU_OR;
451 
                        alu_we = `EN;
452 
                        dmem_ctl = `DMEM_NOP;
453 
                        wb_we =  `DIS;
454 
                        wb_mux = `WB_ALU;
455 
                        //end of `OR ;
456 
                    end
457 
                    'd38://XOR rd,rs,rt
458 
                    begin
459 
                        //replaceID  = `XOR ;
460 
                        ext_ctl = `EXT_NOP;
461 
                        rd_sel = `RD_RD;
462 
                        cmp_ctl = `CMP_NOP;
463 
                        pc_gen_ctl = `PC_NEXT;
464 
                        fsm_dly = `FSM_NOP;
465 
                        muxa_ctl = `MUXA_RS;
466 
                        muxb_ctl = `MUXB_RT;
467 
                        alu_func = `ALU_XOR;
468 
                        alu_we = `EN;
469 
                        dmem_ctl = `DMEM_NOP;
470 
                        wb_we =  `DIS;
471 
                        wb_mux = `WB_ALU;
472 
                        //end of `XOR ;
473 
                    end
474 
                    'd39://NOR rd,rs,rt
475 
                    begin
476 
                        //replaceID  = `NOR ;
477 
                        ext_ctl = `EXT_NOP;
478 
                        rd_sel = `RD_RD;
479 
                        cmp_ctl = `CMP_NOP;
480 
                        pc_gen_ctl = `PC_NEXT;
481 
                        fsm_dly = `FSM_NOP;
482 
                        muxa_ctl = `MUXA_RS;
483 
                        muxb_ctl = `MUXB_RT;
484 
                        alu_func = `ALU_NOR;
485 
                        alu_we = `EN;
486 
                        dmem_ctl = `DMEM_NOP;
487 
                        wb_we =  `DIS;
488 
                        wb_mux = `WB_ALU;
489 
                        //end of `NOR ;
490 
                    end
491 
                    'd42://SLT rd,rs,rt
492 
                    begin
493 
                        //replaceID  = `SLT ;
494 
                        ext_ctl = `EXT_SIGN;
495 
                        rd_sel = `RD_RD;
496 
                        cmp_ctl = `CMP_NOP;
497 
                        pc_gen_ctl = `PC_NEXT;
498 
                        fsm_dly = `FSM_NOP;
499 
                        muxa_ctl = `MUXA_RS;
500 
                        muxb_ctl = `MUXB_RT;
501 
                        alu_func = `ALU_SLT;
502 
                        alu_we = `EN;
503 
                        dmem_ctl = `DMEM_NOP;
504 
                        wb_we =  `DIS;
505 
                        wb_mux = `WB_ALU;
506 
                        //end of `SLT ;
507 
                    end
508 
                    'd43://SLTU rd,rs,rt
509 
                    begin
510 
                        //replaceID  = `SLTU ;
511 
                        ext_ctl = `EXT_NOP;
512 
                        rd_sel = `RD_RD;
513 
                        cmp_ctl = `CMP_NOP;
514 
                        pc_gen_ctl = `PC_NEXT;
515 
                        fsm_dly = `FSM_NOP;
516 
                        muxa_ctl = `MUXA_RS;
517 
                        muxb_ctl = `MUXB_RT;
518 
                        alu_func = `ALU_SLTU;
519 
                        alu_we = `EN;
520 
                        dmem_ctl = `DMEM_NOP;
521 
                        wb_we =  `DIS;
522 
                        wb_mux = `WB_ALU;
523 
                        //end of `SLTU ;
524 
                    end
525 
                    default:
526 
                    begin
527 
                        //replaceID  = `INVALID ;
528 
                        ext_ctl = `IGN;
529 
                        rd_sel = `IGN;
530 
                        cmp_ctl = `IGN;
531 
                        pc_gen_ctl = `IGN;
532 
                        fsm_dly = `IGN;
533 
                        muxa_ctl = `IGN;
534 
                        muxb_ctl = `IGN;
535 
                        alu_func = `IGN;
536 
                        alu_we = `IGN;
537 
                        dmem_ctl = `IGN;
538 
                        wb_we =  `IGN;
539 
                        wb_mux = `IGN;
540 
                        //end of `INVALID ;
541 
                    end
542 
                endcase
543 
            end
544 
            'd1://regimm opreation
545 
            begin
546 
                case (inst_regimm) //synthesis parallel_case
547 
                    'd0://BLTZ rs,offset(signed)
548 
                    begin
549 
                        //replaceID  = `BLTZ ;
550 
                        ext_ctl = `EXT_B;
551 
                        rd_sel = `RD_NOP;
552 
                        cmp_ctl = `CMP_BLTZ;
553 
                        pc_gen_ctl = `PC_BC;
554 
                        fsm_dly = `FSM_CUR;
555 
                        muxa_ctl = `MUXA_NOP;
556 
                        muxb_ctl = `MUXB_NOP;
557 
                        alu_func = `ALU_NOP;
558 
                        alu_we = `DIS;
559 
                        dmem_ctl = `DMEM_NOP;
560 
                        wb_we =  `DIS;
561 
                        wb_mux = `WB_NOP;
562 
                        //end of `BLTZ ;
563 
                    end
564 
                    'd1://BGEZ rs,offset(signed)
565 
                    begin
566 
                        //replaceID  = `BGEZ ;
567 
                        ext_ctl = `EXT_B;
568 
                        rd_sel = `RD_NOP;
569 
                        cmp_ctl = `CMP_BGEZ;
570 
                        pc_gen_ctl = `PC_BC;
571 
                        fsm_dly = `FSM_CUR;
572 
                        muxa_ctl = `MUXA_NOP;
573 
                        muxb_ctl = `MUXB_NOP;
574 
                        alu_func = `ALU_NOP;
575 
                        alu_we = `DIS;
576 
                        dmem_ctl = `DMEM_NOP;
577 
                        wb_we =  `DIS;
578 
                        wb_mux = `WB_NOP;
579 
                        //end of `BGEZ ;
580 
                    end
581 
                    'd16://BLTZAL rs,offset(signed)
582 
                    begin
583 
                        //replaceID  = `BLTZAL ;
584 
                        ext_ctl = `IGN;
585 
                        rd_sel = `IGN;
586 
                        cmp_ctl = `IGN;
587 
                        pc_gen_ctl = `IGN;
588 
                        fsm_dly = `IGN;
589 
                        muxa_ctl = `IGN;
590 
                        muxb_ctl = `IGN;
591 
                        alu_func = `IGN;
592 
                        alu_we = `IGN;
593 
                        dmem_ctl = `IGN;
594 
                        wb_we =  `IGN;
595 
                        wb_mux = `IGN;
596 
                        //end of `BLTZAL ;
597 
                    end
598 
                    'd17://BGEZAL rs,offset(signed)
599 
                    begin
600 
                        //replaceID  = `BGEZAL ;
601 
                        //replaceID  = `INVALID ;
602 
                        ext_ctl = `IGN;
603 
                        rd_sel = `IGN;
604 
                        cmp_ctl = `IGN;
605 
                        pc_gen_ctl = `IGN;
606 
                        fsm_dly = `IGN;
607 
                        muxa_ctl = `IGN;
608 
                        muxb_ctl = `IGN;
609 
                        alu_func = `IGN;
610 
                        alu_we = `IGN;
611 
                        dmem_ctl = `IGN;
612 
                        wb_we =  `IGN;
613 
                        wb_mux = `IGN;
614 
                        //end of `INVALID ;
615 
                    end
616 
                    default:
617 
                    begin
618 
                        //replaceID   = `INVALID ;
619 
                        //replaceID  = `INVALID ;
620 
                        ext_ctl = `IGN;
621 
                        rd_sel = `IGN;
622 
                        cmp_ctl = `IGN;
623 
                        pc_gen_ctl = `IGN;
624 
                        fsm_dly = `IGN;
625 
                        muxa_ctl = `IGN;
626 
                        muxb_ctl = `IGN;
627 
                        alu_func = `IGN;
628 
                        alu_we = `IGN;
629 
                        dmem_ctl = `IGN;
630 
                        wb_we =  `IGN;
631 
                        wb_mux = `IGN;
632 
                        //end of `INVALID ;
633 
                    end
634 
                endcase
635 
            end
636 
            'd2://J imm26({pc[31:28],imm26,00})
637 
            begin
638 
                //replaceID  = `J ;
639 
                ext_ctl = `EXT_J;
640 
                rd_sel = `RD_NOP;
641 
                cmp_ctl = `CMP_NOP;
642 
                pc_gen_ctl = `PC_J;
643 
                fsm_dly = `FSM_NOI;
644 
                muxa_ctl = `MUXA_NOP;
645 
                muxb_ctl = `MUXB_NOP;
646 
                alu_func = `ALU_NOP;
647 
                alu_we = `DIS;
648 
                dmem_ctl = `DMEM_NOP;
649 
                wb_we =  `DIS;
650 
                wb_mux = `WB_NOP;
651 
                //end of `J ;
652 
            end
653 
            'd3://JAL imm26({pc[31:28],imm26,00})
654 
            begin
655 
                //replaceID  = `JAL ;
656 
 
657 
                ext_ctl = `EXT_J;
658 
                rd_sel = `RD_R31;
659 
                cmp_ctl = `CMP_NOP;
660 
                pc_gen_ctl = `PC_J;
661 
                fsm_dly = `FSM_NOI;
662 
                muxa_ctl = `MUXA_PC;
663 
                muxb_ctl = `MUXB_RT;
664 
                alu_func = `ALU_PA;
665 
                alu_we = `EN;
666 
                dmem_ctl = `DMEM_NOP;
667 
                wb_we =  `DIS;
668 
                wb_mux = `WB_ALU;
669 
                //end of `JAL ;
670 
            end
671 
            'd4://BEQ rs,rt,offset(signed)
672 
            begin
673 
                //replaceID  = `BEQ ;
674 
                ext_ctl = `EXT_B;
675 
                rd_sel = `RD_NOP;
676 
                cmp_ctl = `CMP_BEQ;
677 
                pc_gen_ctl = `PC_BC;
678 
                fsm_dly = `FSM_CUR;
679 
                muxa_ctl = `MUXA_NOP;
680 
                muxb_ctl = `MUXB_NOP;
681 
                alu_func = `ALU_NOP;
682 
                alu_we = `DIS;
683 
                dmem_ctl = `DMEM_NOP;
684 
                wb_we =  `DIS;
685 
                wb_mux = `WB_NOP;
686 
                //end of `BEQ ;
687 
            end
688 
            'd5://BNE rs,rt,offset(signed)
689 
            begin
690 
                //replaceID  = `BNE ;
691 
                ext_ctl = `EXT_B;
692 
                rd_sel = `RD_NOP;
693 
                cmp_ctl = `CMP_BNE;
694 
                pc_gen_ctl = `PC_BC;
695 
                fsm_dly = `FSM_CUR;
696 
                muxa_ctl = `MUXA_NOP;
697 
                muxb_ctl = `MUXB_NOP;
698 
                alu_func = `ALU_NOP;
699 
                alu_we = `DIS;
700 
                dmem_ctl = `DMEM_NOP;
701 
                wb_we =  `DIS;
702 
                wb_mux = `WB_NOP;
703 
                //end of `BNE ;
704 
            end
705 
            'd6://BLEZ rs,offset(signed)
706 
            begin
707 
                //replaceID  = `BLEZ ;
708 
                ext_ctl = `EXT_B;
709 
                rd_sel = `RD_NOP;
710 
                cmp_ctl = `CMP_BLEZ;
711 
                pc_gen_ctl = `PC_BC;
712 
                fsm_dly = `FSM_CUR;
713 
                muxa_ctl = `MUXA_NOP;
714 
                muxb_ctl = `MUXB_NOP;
715 
                alu_func = `ALU_NOP;
716 
                alu_we = `DIS;
717 
                dmem_ctl = `DMEM_NOP;
718 
                wb_we =  `DIS;
719 
                wb_mux = `WB_NOP;
720 
                //end of `BLEZ ;
721 
            end
722 
            'd7://BGTZ rs,offset(signed)
723 
            begin
724 
                //replaceID  = `BGTZ ;
725 
                ext_ctl = `EXT_B;
726 
                rd_sel = `RD_NOP;
727 
                cmp_ctl = `CMP_BGTZ;
728 
                pc_gen_ctl = `PC_BC;
729 
                fsm_dly = `FSM_CUR;
730 
                muxa_ctl = `MUXA_NOP;
731 
                muxb_ctl = `MUXB_NOP;
732 
                alu_func = `ALU_NOP;
733 
                alu_we = `DIS;
734 
                dmem_ctl = `DMEM_NOP;
735 
                wb_we =  `DIS;
736 
                wb_mux = `WB_NOP;
737 
                //end of `BGTZ ;
738 
            end
739 
            'd8://ADDI rt,rs,imm16(singed)
740 
            begin
741 
                //replaceID  = `ADDI ;
742 
                ext_ctl = `EXT_SIGN;
743 
                rd_sel = `RD_RT;
744 
                cmp_ctl = `CMP_NOP;
745 
                pc_gen_ctl = `PC_NEXT;
746 
                fsm_dly = `FSM_NOP;
747 
                muxa_ctl = `MUXA_RS;
748 
                muxb_ctl = `MUXB_EXT;
749 
                alu_func = `ALU_ADD;
750 
                alu_we = `EN;
751 
                dmem_ctl = `DMEM_NOP;
752 
                wb_we =  `DIS;
753 
                wb_mux = `WB_ALU;
754 
                //end of `ADDI ;
755 
            end
756 
            'd9://ADDIU rt,rs,imm16(singed)
757 
            begin
758 
                //replaceID  = `ADDIU ;
759 
                ext_ctl = `EXT_SIGN;
760 
                rd_sel = `RD_RT;
761 
                cmp_ctl = `CMP_NOP;
762 
                pc_gen_ctl = `PC_NEXT;
763 
                fsm_dly = `FSM_NOP;
764 
                muxa_ctl = `MUXA_RS;
765 
                muxb_ctl = `MUXB_EXT;
766 
                alu_func = `ALU_ADD;
767 
                alu_we = `EN;
768 
                dmem_ctl = `DMEM_NOP;
769 
                wb_we =  `DIS;
770 
                wb_mux = `WB_ALU;
771 
                //end of `ADDIU ;
772 
            end
773 
            'd10://SLTI rt,rs,imm16(singed)
774 
            begin
775 
                //replaceID  = `SLTI ;
776 
                ext_ctl = `EXT_SIGN;
777 
                rd_sel = `RD_RT;
778 
                cmp_ctl = `CMP_NOP;
779 
                pc_gen_ctl = `PC_NEXT;
780 
                fsm_dly = `FSM_NOP;
781 
                muxa_ctl = `MUXA_RS;
782 
                muxb_ctl = `MUXB_EXT;
783 
                alu_func = `ALU_SLT;
784 
                alu_we = `EN;
785 
                dmem_ctl = `DMEM_NOP;
786 
                wb_we =  `DIS;
787 
                wb_mux = `WB_ALU;
788 
                //end of `SLTI ;
789 
            end
790 
            'd11://SLTIU rt,rs,imm16(singed)
791 
            begin
792 
                //replaceID  = `SLTIU ;
793 
                ext_ctl = `EXT_UNSIGN;
794 
                rd_sel = `RD_RT;
795 
                cmp_ctl = `CMP_NOP;
796 
                pc_gen_ctl = `PC_NEXT;
797 
                fsm_dly = `FSM_NOP;
798 
                muxa_ctl = `MUXA_RS;
799 
                muxb_ctl = `MUXB_EXT;
800 
                alu_func = `ALU_SLTU;
801 
                alu_we = `EN;
802 
                dmem_ctl = `DMEM_NOP;
803 
                wb_we =  `DIS;
804 
                wb_mux = `WB_ALU;
805 
                //end of `SLTIU ;
806 
            end
807 
            'd12://ANDI rt,rs,imm16(singed)
808 
            begin
809 
                //replaceID  = `ANDI ;
810 
                ext_ctl = `EXT_UNSIGN;
811 
                rd_sel = `RD_RT;
812 
                cmp_ctl = `CMP_NOP;
813 
                pc_gen_ctl = `PC_NEXT;
814 
                fsm_dly = `FSM_NOP;
815 
                muxa_ctl = `MUXA_RS;
816 
                muxb_ctl = `MUXB_EXT;
817 
                alu_func = `ALU_AND;
818 
                alu_we = `EN;
819 
                dmem_ctl = `DMEM_NOP;
820 
                wb_we =  `DIS;
821 
                wb_mux = `WB_ALU;
822 
                //end of `ANDI ;
823 
            end
824 
            'd13://ORI rt,rs,imm16(singed)
825 
            begin
826 
                //replaceID  = `ORI ;
827 
                ext_ctl = `EXT_UNSIGN;
828 
                rd_sel = `RD_RT;
829 
                cmp_ctl = `CMP_NOP;
830 
                pc_gen_ctl = `PC_NEXT;
831 
                fsm_dly = `FSM_NOP;
832 
                muxa_ctl = `MUXA_RS;
833 
                muxb_ctl = `MUXB_EXT;
834 
                alu_func = `ALU_OR;
835 
                alu_we = `EN;
836 
                dmem_ctl = `DMEM_NOP;
837 
                wb_we =  `DIS;
838 
                wb_mux = `WB_NOP;
839 
                //end of `ORI ;
840 
            end
841 
            'd14://XORI rt,rs,imm16(singed)
842 
            begin
843 
                //replaceID  = `XORI ;
844 
                ext_ctl = `EXT_UNSIGN;
845 
                rd_sel = `RD_RT;
846 
                cmp_ctl = `CMP_NOP;
847 
                pc_gen_ctl = `PC_NEXT;
848 
                fsm_dly = `FSM_NOP;
849 
                muxa_ctl = `MUXA_RS;
850 
                muxb_ctl = `MUXB_EXT;
851 
                alu_func = `ALU_XOR;
852 
                alu_we = `EN;
853 
                dmem_ctl = `DMEM_NOP;
854 
                wb_we =  `EN;
855 
                wb_mux = `WB_ALU;
856 
                //end of `XORI ;
857 
            end
858 
            'd15://LUI rt,imm16
859 
            begin
860 
                //replaceID  = `LUI ;
861 
                ext_ctl = `EXT_S2H;
862 
                rd_sel = `RD_RT;
863 
                cmp_ctl = `CMP_NOP;
864 
                pc_gen_ctl = `PC_NEXT;
865 
                fsm_dly = `FSM_NOP;
866 
                muxa_ctl = `MUXA_RS;
867 
                muxb_ctl = `MUXB_EXT;
868 
                alu_func = `ALU_PB;
869 
                alu_we = `EN;
870 
                dmem_ctl = `DMEM_NOP;
871 
                wb_we =  `DIS;
872 
                wb_mux = `WB_ALU;
873 
                //end of `LUI ;
874 
            end
875 
            'd16://COP0 func
876 
            begin
877 
                case(inst_cop0_func) //synthesis parallel_case
878 
                    'd0://mfc0 rt,rd // GPR[rd] = CPR[rt] //differ to mips32 definition
879 
                        //read saved PC
880 
                    begin
881 
                        //replaceID  = `MFC0;
882 
                        ext_ctl = `EXT_NOP;
883 
                        rd_sel = `RD_RD;
884 
                        cmp_ctl = `CMP_NOP;
885 
                        pc_gen_ctl = `PC_NEXT;
886 
                        fsm_dly = `FSM_NOP;
887 
                        muxa_ctl = `MUXA_SPC;
888 
                        muxb_ctl = `MUXB_EXT;
889 
                        alu_func = `ALU_PA;
890 
                        alu_we = `EN;
891 
                        dmem_ctl = `DMEM_LB;
892 
                        wb_we =  `DIS;
893 
                        wb_mux = `WB_ALU;
894 
                    end
895 
 
896 
                    'd4://mtc0 rt,rd // CPR[rd] = GPR[rt] //follow the mips32 definition
897 
                    begin        //return from interrupt
898 
                        $display("mtco");
899 
                        //replaceID  = `MTC0;
900 
                        ext_ctl = `EXT_NOP;
901 
                        rd_sel = `RD_NOP;
902 
                        cmp_ctl = `CMP_NOP;
903 
                        pc_gen_ctl = `PC_SPC;
904 
                        fsm_dly = `FSM_RET;
905 
                        muxa_ctl = `MUXA_NOP;
906 
                        muxb_ctl = `MUXB_NOP;
907 
                        alu_func = `ALU_NOP;
908 
                        alu_we = `DIS;
909 
                        dmem_ctl = `DMEM_NOP;
910 
                        wb_we =  `DIS;
911 
                        wb_mux = `WB_NOP;
912 
                    end
913 
                    default:
914 
                    begin
915 
                        //replaceID  = `INVALID ;
916 
                        ext_ctl = `IGN;
917 
                        rd_sel = `IGN;
918 
                        cmp_ctl = `IGN;
919 
                        pc_gen_ctl = `IGN;
920 
                        fsm_dly = `IGN;
921 
                        muxa_ctl = `IGN;
922 
                        muxb_ctl = `IGN;
923 
                        alu_func = `IGN;
924 
                        alu_we = `IGN;
925 
                        dmem_ctl = `IGN;
926 
                        wb_we =  `IGN;
927 
                        wb_mux = `IGN;
928 
                        //end of `INVALID ;
929 
                    end
930 
                endcase
931 
            end
932 
            'd32://LB rt,offset(base) (offset:signed;base:rs)
933 
            begin
934 
                //replaceID  = `LB ;
935 
                ext_ctl = `EXT_SIGN;
936 
                rd_sel = `RD_RT;
937 
                cmp_ctl = `CMP_NOP;
938 
                pc_gen_ctl = `PC_NEXT;
939 
                fsm_dly = `FSM_NOP;
940 
                muxa_ctl = `MUXA_RS;
941 
                muxb_ctl = `MUXB_EXT;
942 
                alu_func = `ALU_ADD;
943 
                alu_we = `DIS;
944 
                dmem_ctl = `DMEM_LBS;
945 
                wb_we =  `EN;
946 
                wb_mux = `WB_MEM;
947 
                //end of `LB ;
948 
            end
949 
            'd33://LH rt,offset(base) (offset:signed;base:rs)
950 
            begin
951 
                //replaceID  = `LH ;
952 
                ext_ctl = `EXT_SIGN;
953 
                rd_sel = `RD_RT;
954 
                cmp_ctl = `CMP_NOP;
955 
                pc_gen_ctl = `PC_NEXT;
956 
                fsm_dly = `FSM_NOP;
957 
                muxa_ctl = `MUXA_RS;
958 
                muxb_ctl = `MUXB_EXT;
959 
                alu_func = `ALU_ADD;
960 
                alu_we = `DIS;
961 
                dmem_ctl = `DMEM_LHS;
962 
                wb_we =  `EN;
963 
                wb_mux = `WB_MEM;
964 
                //end of `LH ;
965 
            end
966 
            'd34://LWL rt,offset(base) (offset:signed;base:rs)
967 
            begin
968 
                //replaceID  = `LWL ;
969 
                ext_ctl = `IGN;
970 
                rd_sel = `IGN;
971 
                cmp_ctl = `IGN;
972 
                pc_gen_ctl = `IGN;
973 
                fsm_dly = `IGN;
974 
                muxa_ctl = `IGN;
975 
                muxb_ctl = `IGN;
976 
                alu_func = `IGN;
977 
                alu_we = `IGN;
978 
                dmem_ctl = `IGN;
979 
                wb_we =  `IGN;
980 
                wb_mux = `IGN;
981 
                //end of `LWL ;
982 
            end
983 
            'd35://LW rt,offset(base) (offset:signed;base:rs)
984 
            begin
985 
                //replaceID  = `LW ;
986 
                ext_ctl = `EXT_SIGN;
987 
                rd_sel = `RD_RT;
988 
                cmp_ctl = `CMP_NOP;
989 
                pc_gen_ctl = `PC_NEXT;
990 
                fsm_dly = `FSM_NOP;
991 
                muxa_ctl = `MUXA_RS;
992 
                muxb_ctl = `MUXB_EXT;
993 
                alu_func = `ALU_ADD;
994 
                alu_we = `DIS;
995 
                dmem_ctl = `DMEM_LW;
996 
                wb_we =  `EN;
997 
                wb_mux = `WB_MEM;
998 
                //end of `LW ;
999 
            end
1000 
            'd36://LBU rt,offset(base) (offset:signed;base:rs)
1001 
            begin
1002 
                //replaceID  = `LBU ;
1003 
                ext_ctl = `EXT_SIGN;
1004 
                rd_sel = `RD_RT;
1005 
                cmp_ctl = `CMP_NOP;
1006 
                pc_gen_ctl = `PC_NEXT;
1007 
                fsm_dly = `FSM_NOP;
1008 
                muxa_ctl = `MUXA_RS;
1009 
                muxb_ctl = `MUXB_EXT;
1010 
                alu_func = `ALU_ADD;
1011 
                alu_we = `DIS;
1012 
                dmem_ctl = `DMEM_LBU;
1013 
                wb_we =  `EN;
1014 
                wb_mux = `WB_MEM;
1015 
                //end of `LBU ;
1016 
            end
1017 
            'd37://LHU rt,offset(base) (offset:signed;base:rs)
1018 
            begin
1019 
                //replaceID  = `LHU ;
1020 
                ext_ctl = `EXT_SIGN;
1021 
                rd_sel = `RD_RT;
1022 
                cmp_ctl = `CMP_NOP;
1023 
                pc_gen_ctl = `PC_NEXT;
1024 
                fsm_dly = `FSM_NOP;
1025 
                muxa_ctl = `MUXA_RS;
1026 
                muxb_ctl = `MUXB_EXT;
1027 
                alu_func = `ALU_ADD;
1028 
                alu_we = `DIS;
1029 
                dmem_ctl = `DMEM_LHU;
1030 
                wb_we =  `EN;
1031 
                wb_mux = `WB_MEM;
1032 
                //end of `LHU ;
1033 
            end
1034 
            'd38://LWR rt,offset(base) (offset:signed;base:rs)
1035 
            begin
1036 
                //replaceID  = `LWR ;
1037 
                ext_ctl = `IGN;
1038 
                rd_sel = `IGN;
1039 
                cmp_ctl = `IGN;
1040 
                pc_gen_ctl = `IGN;
1041 
                fsm_dly = `IGN;
1042 
                muxa_ctl = `IGN;
1043 
                muxb_ctl = `IGN;
1044 
                alu_func = `IGN;
1045 
                alu_we = `IGN;
1046 
                dmem_ctl = `IGN;
1047 
                wb_we =  `IGN;
1048 
                wb_mux = `IGN;
1049 
                //end of `LWR ;
1050 
            end
1051 
            'd40://SB rt,offset(base) (offset:signed;base:rs)
1052 
            begin
1053 
                //replaceID  = `SB ;
1054 
                ext_ctl = `EXT_SIGN;
1055 
                rd_sel = `RD_NOP;
1056 
                cmp_ctl = `CMP_NOP;
1057 
                pc_gen_ctl = `PC_NEXT;
1058 
                fsm_dly = `FSM_NOP;
1059 
                muxa_ctl = `MUXA_RS;
1060 
                muxb_ctl = `MUXB_EXT;
1061 
                alu_func = `ALU_ADD;
1062 
                alu_we = `DIS;
1063 
                dmem_ctl = `DMEM_SB;
1064 
                wb_we =  `DIS;
1065 
                wb_mux = `WB_NOP;
1066 
                //end of `SB ;
1067 
            end
1068 
            'd41://SH rt,offset(base) (offset:signed;base:rs)
1069 
            begin
1070 
                //replaceID  = `SH ;
1071 
                ext_ctl = `EXT_SIGN;
1072 
                rd_sel = `RD_RT;
1073 
                cmp_ctl = `CMP_NOP;
1074 
                pc_gen_ctl = `PC_NEXT;
1075 
                fsm_dly = `FSM_NOP;
1076 
                muxa_ctl = `MUXA_RS;
1077 
                muxb_ctl = `MUXB_EXT;
1078 
                alu_func = `ALU_ADD;
1079 
                alu_we = `DIS;
1080 
                dmem_ctl = `DMEM_SH;
1081 
                wb_we =  `DIS;
1082 
                wb_mux = `WB_NOP;
1083 
                //end of `SH ;
1084 
            end
1085 
            'd42://SWL rt,offset(base) (offset:signed;base:rs)
1086 
            begin
1087 
                //replaceID  = `SWL ;
1088 
                ext_ctl = `IGN;
1089 
                rd_sel = `IGN;
1090 
                cmp_ctl = `IGN;
1091 
                pc_gen_ctl = `IGN;
1092 
                fsm_dly = `IGN;
1093 
                muxa_ctl = `IGN;
1094 
                muxb_ctl = `IGN;
1095 
                alu_func = `IGN;
1096 
                alu_we = `IGN;
1097 
                dmem_ctl = `IGN;
1098 
                wb_we =  `IGN;
1099 
                wb_mux = `IGN;
1100 
                //end of `SWL ;
1101 
            end
1102 
            'd43://SW rt,offset(base) (offset:signed;base:rs)
1103 
            begin
1104 
                //replaceID  = `SW ;
1105 
                ext_ctl = `EXT_SIGN;
1106 
                rd_sel = `RD_NOP;
1107 
                cmp_ctl = `CMP_NOP;
1108 
                pc_gen_ctl = `PC_NEXT;
1109 
                fsm_dly = `FSM_NOP;
1110 
                muxa_ctl = `MUXA_RS;
1111 
                muxb_ctl = `MUXB_EXT;
1112 
                alu_func = `ALU_ADD;
1113 
                alu_we = `DIS;
1114 
                dmem_ctl = `DMEM_SW;
1115 
                wb_we =  `DIS;
1116 
                wb_mux = `WB_NOP;
1117 
                //end of `SW ;
1118 
            end
1119 
            'd46://SWR rt,offset(base) (offset:signed;base:rs)
1120 
            begin
1121 
                //replaceID  = `SWR ;
1122 
                ext_ctl = `IGN;
1123 
                rd_sel = `IGN;
1124 
                cmp_ctl = `IGN;
1125 
                pc_gen_ctl = `IGN;
1126 
                fsm_dly = `IGN;
1127 
                muxa_ctl = `IGN;
1128 
                muxb_ctl = `IGN;
1129 
                alu_func = `IGN;
1130 
                alu_we = `IGN;
1131 
                dmem_ctl = `IGN;
1132 
                wb_we =  `IGN;
1133 
                wb_mux = `IGN;
1134 
                //end of `SWR ;
1135 
            end
1136 
            default:
1137 
            begin
1138 
                //replaceID  = `INVALID ;
1139 
                ext_ctl = `IGN;
1140 
                rd_sel = `IGN;
1141 
                cmp_ctl = `IGN;
1142 
                pc_gen_ctl = `IGN;
1143 
                fsm_dly = `IGN;
1144 
                muxa_ctl = `IGN;
1145 
                muxb_ctl = `IGN;
1146 
                alu_func = `IGN;
1147 
                alu_we = `IGN;
1148 
                dmem_ctl = `IGN;
1149 
                wb_we =  `IGN;
1150 
                wb_mux = `IGN;
1151 
                //end of `INVALID ;  //replaceID   = `INVALID ;
1152 
            end
1153 
        endcase
1154 
    end
1155 
endmodule
1156 
 
1157 
 
1158 
 
1159 
module pipelinedregs (
1160 
        clk,id2ra_ctl_clr,id2ra_ctl_cls,ra2ex_ctl_clr,
1161 
        alu_func_i,alu_we_i,cmp_ctl_i,dmem_ctl_i,ext_ctl_i,
1162 
        muxa_ctl_i,muxb_ctl_i,pc_gen_ctl_i,rd_sel_i,wb_mux_ctl_i,
1163 
        wb_we_i,alu_func_o,alu_we_o,cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,
1164 
        ext_ctl,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,wb_mux_ctl_o,wb_we_o
1165 
    ) ;
1166 
 
1167 
    input clk;
1168 
    wire clk;
1169 
    input id2ra_ctl_clr;
1170 
    wire id2ra_ctl_clr;
1171 
    input id2ra_ctl_cls;
1172 
    wire id2ra_ctl_cls;
1173 
    input ra2ex_ctl_clr;
1174 
    wire ra2ex_ctl_clr;
1175 
    input [4:0] alu_func_i;
1176 
    wire [4:0] alu_func_i;
1177 
    input [0:0] alu_we_i;
1178 
    wire [0:0] alu_we_i;
1179 
    input [2:0] cmp_ctl_i;
1180 
    wire [2:0] cmp_ctl_i;
1181 
    input [3:0] dmem_ctl_i;
1182 
    wire [3:0] dmem_ctl_i;
1183 
    input [2:0] ext_ctl_i;
1184 
    wire [2:0] ext_ctl_i;
1185 
    input [1:0] muxa_ctl_i;
1186 
    wire [1:0] muxa_ctl_i;
1187 
    input [1:0] muxb_ctl_i;
1188 
    wire [1:0] muxb_ctl_i;
1189 
    input [2:0] pc_gen_ctl_i;
1190 
    wire [2:0] pc_gen_ctl_i;
1191 
    input [1:0] rd_sel_i;
1192 
    wire [1:0] rd_sel_i;
1193 
    input [0:0] wb_mux_ctl_i;
1194 
    wire [0:0] wb_mux_ctl_i;
1195 
    input [0:0] wb_we_i;
1196 
    wire [0:0] wb_we_i;
1197 
    output [4:0] alu_func_o;
1198 
    wire [4:0] alu_func_o;
1199 
    output [0:0] alu_we_o;
1200 
    wire [0:0] alu_we_o;
1201 
    output [2:0] cmp_ctl_o;
1202 
    wire [2:0] cmp_ctl_o;
1203 
    output [3:0] dmem_ctl_o;
1204 
    wire [3:0] dmem_ctl_o;
1205 
    output [3:0] dmem_ctl_ur_o;
1206 
    wire [3:0] dmem_ctl_ur_o;
1207 
    output [2:0] ext_ctl;
1208 
    wire [2:0] ext_ctl;
1209 
    output [1:0] muxa_ctl_o;
1210 
    wire [1:0] muxa_ctl_o;
1211 
    output [1:0] muxb_ctl_o;
1212 
    wire [1:0] muxb_ctl_o;
1213 
    output [2:0] pc_gen_ctl_o;
1214 
    wire [2:0] pc_gen_ctl_o;
1215 
    output [1:0] rd_sel_o;
1216 
    wire [1:0] rd_sel_o;
1217 
    output [0:0] wb_mux_ctl_o;
1218 
    wire [0:0] wb_mux_ctl_o;
1219 
    output [0:0] wb_we_o;
1220 
    wire [0:0] wb_we_o;
1221 
 
1222 
 
1223 
    wire NET7643;
1224 
    wire [0:0] BUS4987;
1225 
    wire [1:0] BUS5008;
1226 
    wire [1:0] BUS5483;
1227 
    wire [0:0] BUS5639;
1228 
    wire [0:0] BUS5651;
1229 
    wire [3:0] BUS5666;
1230 
    wire [4:0] BUS5674;
1231 
    wire [0:0] BUS5682;
1232 
    wire [0:0] BUS5690;
1233 
    wire [0:0] BUS5790;
1234 
    wire [0:0] BUS7299;
1235 
    wire [0:0] BUS7822;
1236 
 
1237 
 
1238 
    muxb_ctl_reg_clr_cls U1
1239 
                         (
1240 
                             .clk(clk),
1241 
                             .clr(id2ra_ctl_clr),
1242 
                             .cls(id2ra_ctl_cls),
1243 
                             .muxb_ctl_i(muxb_ctl_i),
1244 
                             .muxb_ctl_o(BUS5483)
1245 
                         );
1246 
 
1247 
 
1248 
 
1249 
    wb_mux_ctl_reg_clr_cls U10
1250 
                           (
1251 
                               .clk(clk),
1252 
                               .clr(id2ra_ctl_clr),
1253 
                               .cls(id2ra_ctl_cls),
1254 
                               .wb_mux_ctl_i(wb_mux_ctl_i),
1255 
                               .wb_mux_ctl_o(BUS5651)
1256 
                           );
1257 
 
1258 
 
1259 
 
1260 
    wb_we_reg_clr_cls U11
1261 
                      (
1262 
                          .clk(clk),
1263 
                          .clr(id2ra_ctl_clr),
1264 
                          .cls(id2ra_ctl_cls),
1265 
                          .wb_we_i(wb_we_i),
1266 
                          .wb_we_o(BUS5639)
1267 
                      );
1268 
 
1269 
 
1270 
 
1271 
    wb_we_reg U12
1272 
              (
1273 
                  .clk(clk),
1274 
                  .wb_we_i(NET7643),
1275 
                  .wb_we_o(wb_we_o)
1276 
              );
1277 
 
1278 
 
1279 
 
1280 
    wb_mux_ctl_reg_clr U13
1281 
                       (
1282 
                           .clk(clk),
1283 
                           .clr(ra2ex_ctl_clr),
1284 
                           .wb_mux_ctl_i(BUS5651),
1285 
                           .wb_mux_ctl_o(BUS5690)
1286 
                       );
1287 
 
1288 
 
1289 
 
1290 
    muxb_ctl_reg_clr U14
1291 
                     (
1292 
                         .clk(clk),
1293 
                         .clr(ra2ex_ctl_clr),
1294 
                         .muxb_ctl_i(BUS5483),
1295 
                         .muxb_ctl_o(muxb_ctl_o)
1296 
                     );
1297 
 
1298 
 
1299 
 
1300 
    dmem_ctl_reg_clr U15
1301 
                     (
1302 
                         .clk(clk),
1303 
                         .clr(ra2ex_ctl_clr),
1304 
                         .dmem_ctl_i(BUS5666),
1305 
                         .dmem_ctl_o(dmem_ctl_ur_o)
1306 
                     );
1307 
 
1308 
 
1309 
 
1310 
    alu_func_reg_clr U16
1311 
                     (
1312 
                         .alu_func_i(BUS5674),
1313 
                         .alu_func_o(alu_func_o),
1314 
                         .clk(clk),
1315 
                         .clr(ra2ex_ctl_clr)
1316 
                     );
1317 
 
1318 
 
1319 
 
1320 
    muxa_ctl_reg_clr U17
1321 
                     (
1322 
                         .clk(clk),
1323 
                         .clr(ra2ex_ctl_clr),
1324 
                         .muxa_ctl_i(BUS5008),
1325 
                         .muxa_ctl_o(muxa_ctl_o)
1326 
                     );
1327 
 
1328 
 
1329 
 
1330 
    wb_mux_ctl_reg U18
1331 
                   (
1332 
                       .clk(clk),
1333 
                       .wb_mux_ctl_i(BUS5790),
1334 
                       .wb_mux_ctl_o(wb_mux_ctl_o)
1335 
                   );
1336 
 
1337 
 
1338 
 
1339 
    wb_we_reg_clr U19
1340 
                  (
1341 
                      .clk(clk),
1342 
                      .clr(ra2ex_ctl_clr),
1343 
                      .wb_we_i(BUS5639),
1344 
                      .wb_we_o(BUS5682)
1345 
                  );
1346 
 
1347 
 
1348 
 
1349 
    cmp_ctl_reg_clr_cls U2
1350 
                        (
1351 
                            .clk(clk),
1352 
                            .clr(id2ra_ctl_clr),
1353 
                            .cls(id2ra_ctl_cls),
1354 
                            .cmp_ctl_i(cmp_ctl_i),
1355 
                            .cmp_ctl_o(cmp_ctl_o)
1356 
                        );
1357 
 
1358 
 
1359 
 
1360 
    wb_we_reg U20
1361 
              (
1362 
                  .clk(clk),
1363 
                  .wb_we_i(BUS5682),
1364 
                  .wb_we_o(BUS7822)
1365 
              );
1366 
 
1367 
 
1368 
 
1369 
    wb_mux_ctl_reg U21
1370 
                   (
1371 
                       .clk(clk),
1372 
                       .wb_mux_ctl_i(BUS5690),
1373 
                       .wb_mux_ctl_o(BUS5790)
1374 
                   );
1375 
 
1376 
 
1377 
 
1378 
    wb_we_reg U22
1379 
              (
1380 
                  .clk(clk),
1381 
                  .wb_we_i(BUS7299),
1382 
                  .wb_we_o(alu_we_o)
1383 
              );
1384 
 
1385 
 
1386 
 
1387 
    assign NET7643 = alu_we_o[0] | BUS7822[0];
1388 
 
1389 
 
1390 
    alu_we_reg_clr U24
1391 
                   (
1392 
                       .alu_we_i(BUS4987),
1393 
                       .alu_we_o(BUS7299),
1394 
                       .clk(clk),
1395 
                       .clr(ra2ex_ctl_clr)
1396 
                   );
1397 
 
1398 
 
1399 
 
1400 
    alu_func_reg_clr_cls U26
1401 
                         (
1402 
                             .alu_func_i(alu_func_i),
1403 
                             .alu_func_o(BUS5674),
1404 
                             .clk(clk),
1405 
                             .clr(id2ra_ctl_clr),
1406 
                             .cls(id2ra_ctl_cls)
1407 
                         );
1408 
 
1409 
 
1410 
 
1411 
    dmem_ctl_reg_clr_cls U3
1412 
                         (
1413 
                             .clk(clk),
1414 
                             .clr(id2ra_ctl_clr),
1415 
                             .cls(id2ra_ctl_cls),
1416 
                             .dmem_ctl_i(dmem_ctl_i),
1417 
                             .dmem_ctl_o(BUS5666)
1418 
                         );
1419 
 
1420 
 
1421 
 
1422 
    ext_ctl_reg_clr_cls U4
1423 
                        (
1424 
                            .clk(clk),
1425 
                            .clr(id2ra_ctl_clr),
1426 
                            .cls(id2ra_ctl_cls),
1427 
                            .ext_ctl_i(ext_ctl_i),
1428 
                            .ext_ctl_o(ext_ctl)
1429 
                        );
1430 
 
1431 
 
1432 
 
1433 
    rd_sel_reg_clr_cls U5
1434 
                       (
1435 
                           .clk(clk),
1436 
                           .clr(id2ra_ctl_clr),
1437 
                           .cls(id2ra_ctl_cls),
1438 
                           .rd_sel_i(rd_sel_i),
1439 
                           .rd_sel_o(rd_sel_o)
1440 
                       );
1441 
 
1442 
 
1443 
 
1444 
    alu_we_reg_clr_cls U6
1445 
                       (
1446 
                           .alu_we_i(alu_we_i),
1447 
                           .alu_we_o(BUS4987),
1448 
                           .clk(clk),
1449 
                           .clr(id2ra_ctl_clr),
1450 
                           .cls(id2ra_ctl_cls)
1451 
                       );
1452 
 
1453 
 
1454 
 
1455 
    muxa_ctl_reg_clr_cls U7
1456 
                         (
1457 
                             .clk(clk),
1458 
                             .clr(id2ra_ctl_clr),
1459 
                             .cls(id2ra_ctl_cls),
1460 
                             .muxa_ctl_i(muxa_ctl_i),
1461 
                             .muxa_ctl_o(BUS5008)
1462 
                         );
1463 
 
1464 
 
1465 
 
1466 
    pc_gen_ctl_reg_clr_cls U8
1467 
                           (
1468 
                               .clk(clk),
1469 
                               .clr(id2ra_ctl_clr),
1470 
                               .cls(id2ra_ctl_cls),
1471 
                               .pc_gen_ctl_i(pc_gen_ctl_i),
1472 
                               .pc_gen_ctl_o(pc_gen_ctl_o)
1473 
                           );
1474 
 
1475 
 
1476 
 
1477 
    dmem_ctl_reg U9
1478 
                 (
1479 
                     .clk(clk),
1480 
                     .dmem_ctl_i(dmem_ctl_ur_o),
1481 
                     .dmem_ctl_o(dmem_ctl_o)
1482 
                 );
1483 
 
1484 
 
1485 
 
1486 
endmodule
1487 
 
1488 
module decode_pipe
1489 
    (
1490 
        clk,id2ra_ctl_clr,id2ra_ctl_cls,
1491 
        ra2ex_ctl_clr,ins_i,alu_func_o,alu_we_o,
1492 
        cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,ext_ctl_o,
1493 
        fsm_dly,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,
1494 
        wb_mux_ctl_o,wb_we_o
1495 
    ) ;
1496 
 
1497 
    input clk;
1498 
    wire clk;
1499 
    input id2ra_ctl_clr;
1500 
    wire id2ra_ctl_clr;
1501 
    input id2ra_ctl_cls;
1502 
    wire id2ra_ctl_cls;
1503 
    input ra2ex_ctl_clr;
1504 
    wire ra2ex_ctl_clr;
1505 
    input [31:0] ins_i;
1506 
    wire [31:0] ins_i;
1507 
    output [4:0] alu_func_o;
1508 
    wire [4:0] alu_func_o;
1509 
    output [0:0] alu_we_o;
1510 
    wire [0:0] alu_we_o;
1511 
    output [2:0] cmp_ctl_o;
1512 
    wire [2:0] cmp_ctl_o;
1513 
    output [3:0] dmem_ctl_o;
1514 
    wire [3:0] dmem_ctl_o;
1515 
    output [3:0] dmem_ctl_ur_o;
1516 
    wire [3:0] dmem_ctl_ur_o;
1517 
    output [2:0] ext_ctl_o;
1518 
    wire [2:0] ext_ctl_o;
1519 
    output [2:0] fsm_dly;
1520 
    wire [2:0] fsm_dly;
1521 
    output [1:0] muxa_ctl_o;
1522 
    wire [1:0] muxa_ctl_o;
1523 
    output [1:0] muxb_ctl_o;
1524 
    wire [1:0] muxb_ctl_o;
1525 
    output [2:0] pc_gen_ctl_o;
1526 
    wire [2:0] pc_gen_ctl_o;
1527 
    output [1:0] rd_sel_o;
1528 
    wire [1:0] rd_sel_o;
1529 
    output [0:0] wb_mux_ctl_o;
1530 
    wire [0:0] wb_mux_ctl_o;
1531 
    output [0:0] wb_we_o;
1532 
    wire [0:0] wb_we_o;
1533 
 
1534 
 
1535 
    wire [4:0] BUS2040;
1536 
    wire [0:0] BUS2048;
1537 
    wire [2:0] BUS2056;
1538 
    wire [3:0] BUS2064;
1539 
    wire [2:0] BUS2072;
1540 
    wire [1:0] BUS2086;
1541 
    wire [1:0] BUS2094;
1542 
    wire [2:0] BUS2102;
1543 
    wire [1:0] BUS2110;
1544 
    wire [0:0] BUS2118;
1545 
    wire [0:0] BUS2126;
1546 
 
1547 
 
1548 
    decoder idecoder
1549 
            (
1550 
                .alu_func(BUS2040),
1551 
                .alu_we(BUS2048),
1552 
                .cmp_ctl(BUS2056),
1553 
                .dmem_ctl(BUS2064),
1554 
                .ext_ctl(BUS2072),
1555 
                .fsm_dly(fsm_dly),
1556 
                .ins_i(ins_i),
1557 
                .muxa_ctl(BUS2086),
1558 
                .muxb_ctl(BUS2094),
1559 
                .pc_gen_ctl(BUS2102),
1560 
                .rd_sel(BUS2110),
1561 
                .wb_mux(BUS2118),
1562 
                .wb_we(BUS2126)
1563 
            );
1564 
 
1565 
 
1566 
 
1567 
    pipelinedregs pipereg
1568 
                  (
1569 
                      .alu_func_i(BUS2040),
1570 
                      .alu_func_o(alu_func_o),
1571 
                      .alu_we_i(BUS2048),
1572 
                      .alu_we_o(alu_we_o),
1573 
                      .clk(clk),
1574 
                      .cmp_ctl_i(BUS2056),
1575 
                      .cmp_ctl_o(cmp_ctl_o),
1576 
                      .dmem_ctl_i(BUS2064),
1577 
                      .dmem_ctl_o(dmem_ctl_o),
1578 
                      .dmem_ctl_ur_o(dmem_ctl_ur_o),
1579 
                      .ext_ctl(ext_ctl_o),
1580 
                      .ext_ctl_i(BUS2072),
1581 
                      .id2ra_ctl_clr(id2ra_ctl_clr),
1582 
                      .id2ra_ctl_cls(id2ra_ctl_cls),
1583 
                      .muxa_ctl_i(BUS2086),
1584 
                      .muxa_ctl_o(muxa_ctl_o),
1585 
                      .muxb_ctl_i(BUS2094),
1586 
                      .muxb_ctl_o(muxb_ctl_o),
1587 
                      .pc_gen_ctl_i(BUS2102),
1588 
                      .pc_gen_ctl_o(pc_gen_ctl_o),
1589 
                      .ra2ex_ctl_clr(ra2ex_ctl_clr),
1590 
                      .rd_sel_i(BUS2110),
1591 
                      .rd_sel_o(rd_sel_o),
1592 
                      .wb_mux_ctl_i(BUS2118),
1593 
                      .wb_mux_ctl_o(wb_mux_ctl_o),
1594 
                      .wb_we_i(BUS2126),
1595 
                      .wb_we_o(wb_we_o)
1596 
                  );
1597 
 
1598 
 
1599 
 
1600 
endmodule
1601 
 
1602 
 
1603 
 
1604 
 
1605 
 

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