| 1 |
2 |
dimamali |
VER=1.0.19
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| 2 |
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GVER=1019
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| 3 |
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CC=gcc
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| 4 |
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SED=sed
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| 5 |
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DISTLIB=~/vhdl
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| 6 |
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ASICLIBS = ihp25 sgb25vrh ut025crh virage rh_lib18t rh_lib18t_io2 \
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atc18 artisan umc18 virage90 tsmc90 dare nextreme atc18rha_cell
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| 9 |
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FPGALIBS = apa proasic3 axcelerator ec unisim altera altera_mf stratixii \
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eclipsee cycloneiii stratixiii synplify simprim
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ifeq ("$(TECHLIBS)","")
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TECHLIBS=$(FPGALIBS) $(ASICLIBS)
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endif
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XTECHLIBS = $(TECHLIBS:%=tech/% )
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| 15 |
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SIMLIBS = hynix micron cypress
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ACTELLIBS = apa apa3 axcelerator
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XILINXLIBS = unisim simprim
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| 18 |
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ALTERALIBS = altera_mf stratixii altera cycloneiii stratixiii
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LATTICELIBS = ec
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BRMLIBS = core1553bbc core1553brm core1553brt gr1553
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COREPCILIB = corePCIF
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CONTRIBLIBS = openchip gleichmann contrib sun
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RMFTLIBS=ihp25 sgb25vrh ut025crh rh_lib18t rh_lib18t_io2 pere05 rhumc \
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dare tsmc90 atc18rha_cell
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RMCOMLIBS=artisan cust1 virage90 nextreme
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| 28 |
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RMFTLIBSX = $(RMFTLIBS:%=lib/techmap/%) $(RMFTLIBS:%=lib/tech/%)
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RMCOMLIBSX = $(RMCOMLIBS:%=lib/techmap/%) $(RMCOMLIBS:%=lib/tech/%)
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RMFPGALIBSX = $(ASICLIBS:%=lib/techmap/%) $(ASICLIBS:%=lib/tech/%)
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| 31 |
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| 32 |
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HAPSFILES = lib/gaisler/haps doc/haps.pdf boards/hardi* designs/leon3-hardi*
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| 34 |
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INTFILES = TODO.txt \
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| 35 |
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boards/*/doc \
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| 36 |
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doc/crypto doc/companion-core doc/design-reuse doc/esa \
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| 37 |
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doc/gr1553 doc/greth doc/grspw \
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| 38 |
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lib/actel/*/source \
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| 39 |
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lib/esa/leon2* lib/gaisler/fpu \
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| 40 |
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lib/gaisler/leon3ft lib/gaisler/pcif lib/gaisler/satcan \
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| 41 |
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lib/gaisler/crypto lib/ihp* \
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| 42 |
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lib/gaisler/slink \
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| 43 |
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$(RMFTLIBSX) lib/tech/nextreme/cells \
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| 44 |
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lib/topnet lib/tmtc \
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| 45 |
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designs/suidemo \
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| 46 |
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designs/*esa* designs/leon3-ft-a* designs/leon3-ft-d* \
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designs/leon3-ft-r* designs/leon3-ft-m* \
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| 48 |
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designs/leon3-ft-*flex designs/leon3-celeno designs/leon3ihp-tbench \
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| 49 |
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designs/*flexody* designs/*/rhlib* \
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| 50 |
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designs/*-cosim designs/leon2-gr-cpci-xc4v \
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| 51 |
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designs/leon2* \
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| 52 |
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designs/ethspw designs/leon3ihp designs/pcispw \
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| 53 |
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designs/leon3-1553 \
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| 54 |
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designs/gr701-pci-1553-bridge \
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| 55 |
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designs/rasta-if-board designs/leon3-bsd \
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| 56 |
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verification/ahbctrl \
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| 57 |
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verification/b1553brm \
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| 58 |
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verification/dma2ahb verification/esa_spw \
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| 59 |
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verification/grslink verification/grspw \
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| 60 |
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verification/spimctrl \
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| 61 |
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verification/tb_msp verification/rs_gf4_16_8 \
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| 62 |
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verification/tmtc \
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| 63 |
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lib/spansion/flash/s29gl128p.vhd lib/spansion/flash/s29gl128p_vhd.ftm \
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| 64 |
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lib/techmap/*/usbhc_unisim_* netlists/xilinx/spartan3/grspwc2.ngo\
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| 65 |
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lib/techmap/*/corepcif_* lib/actel/corePCIF/netlist \
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| 66 |
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lib/tech/atc18/cells lib/tech/atc18rha_cell\
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| 67 |
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lib/techmap/*/pci_arb_* lib/gaisler/ascs \
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| 68 |
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software/leon3/grslink.c software/leon3/grascs.c \
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| 69 |
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lib/tech/*/doc lib/gaisler/haps/ddr2_1x2* \
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| 70 |
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lib/tech/tsmc90/tci
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| 71 |
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| 72 |
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FTFILES = \
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doc/reedsolomon doc/tmtc \
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| 74 |
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designs/leon3-rtax* designs/leon3-ft* \
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| 75 |
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verification/ft* \
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| 76 |
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lib/actel \
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| 77 |
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lib/gaisler/*/*ft* lib/gaisler/misc/ft* \
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| 78 |
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lib/gaisler/b1553 lib/gr1553 \
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| 79 |
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lib/grlib/ftlib \
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| 80 |
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lib/micron/sdram/ft* \
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| 81 |
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lib/techmap/maps/*ft* \
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| 82 |
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lib/spw/core \
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| 83 |
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lib/techmap/*/grspwc_*_*.vhd \
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| 84 |
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lib/techmap/*/leon3ft*_*.vhd \
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| 85 |
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lib/techmap/*/ftmctrl_*_*.vhd \
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| 86 |
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software/leon3/*ft* software/leon3/bch* \
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| 87 |
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software/leon3/brm.c
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| 88 |
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| 89 |
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USBFILES = \
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verification/grusbhc verification/usbdcl verification/grusbdc \
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lib/gaisler/usb/hc lib/gaisler/usb/dc lib/gaisler/usb/dcl \
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| 92 |
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lib/techmap/*/usbhc_*_*.vhd
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| 93 |
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| 94 |
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GBITFILES = \
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| 95 |
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verification/greth/*gbit* \
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| 96 |
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lib/eth/core/*gbit*
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| 97 |
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| 98 |
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T1FILES = lib/sun designs/t1*
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| 99 |
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| 100 |
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COREMP7FILES = lib/gaisler/coremp7 designs/coremp7-actel-proasic3
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| 102 |
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COMFILES = \
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| 103 |
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designs/leon3-clk2x designs/*spw* \
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| 104 |
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verification/greth verification/spictrl verification/i2c \
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| 105 |
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verification/pci verification/can_oc \
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| 106 |
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verification/mobile_ddr_sdr \
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| 107 |
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lib/grlib/amba/ahbmon.vhd lib/grlib/amba/apbmon.vhd \
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| 108 |
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lib/grlib/amba/ambamon.vhd lib/grlib/amba/ahbctrl_mb.vhd \
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| 109 |
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lib/gaisler/misc/ahb2ahb.vhd lib/gaisler/misc/ahbbridge.vhd \
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| 110 |
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lib/gaisler/leon3/*2x* lib/gaisler/memctrl/ssrctrl.vhd \
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| 111 |
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lib/gaisler/misc/grfifo* \
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| 112 |
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lib/gaisler/misc/gradcdac* \
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| 113 |
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lib/gaisler/can/can_core.vhd lib/gaisler/can/grcan.vhd \
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| 114 |
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lib/gaisler/can/can_top_core_sync.vhd lib/opencores/can/can_top_sync.vhd \
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| 115 |
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lib/gaisler/sim/ulpi.vhd lib/gaisler/sim/utmi.vhd \
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| 116 |
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lib/techmap/inferred/tap_inferred.vhd \
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| 117 |
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$(USBFILES) $(RMCOMLIBSX) $(GBITFILES)
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| 118 |
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| 119 |
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INTFTFPGAFILES = \
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| 120 |
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verification/greth verification/greth/*gbit* \
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| 121 |
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designs/leon3-clk2x lib/gaisler/greth/*gbit* \
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| 122 |
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lib/grlib/amba/ahbctrl_mb.vhd \
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| 123 |
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lib/gaisler/misc/ahb2ahb.vhd lib/gaisler/misc/ahbbridge.vhd \
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| 124 |
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lib/gaisler/usb/usbdclc.vhd lib/usbhc/core \
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| 125 |
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lib/gaisler/leon3/*2x* lib/gaisler/memctrl/ssrctrl.vhd \
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| 126 |
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lib/gaisler/greth/*gbit* \
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| 127 |
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lib/gaisler/memctrl/ftsrctrl-v1.* \
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| 128 |
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lib/gleichmann lib/openchip \
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| 129 |
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lib/tech/altera lib/techmap/altera \
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| 130 |
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lib/tech/cycloneiii lib/techmap/cycloneiii \
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| 131 |
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lib/tech/stratixiii lib/techmap/stratixiii \
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| 132 |
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lib/tech/altera_mf lib/techmap/altera_mf \
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| 133 |
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lib/tech/stratixii lib/techmap/stratixii \
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| 134 |
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lib/tech/apa lib/techmap/apa \
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| 135 |
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lib/tech/proasic3 lib/techmap/proasic3 \
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| 136 |
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lib/tech/ec lib/techmap/ec \
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| 137 |
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designs/leon3-altera* designs/leon3-avnet* designs/leon3-clock-gate \
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| 138 |
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designs/leon3-digilent* designs/leon3-xilinx* \
|
| 139 |
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designs/leon3-nuhorizons-3s1500 \
|
| 140 |
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designs/leon3-jopdesign-ep1c12 designs/leon3-ge-* \
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| 141 |
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designs/leon3-gr-cpci* designs/leon3-gr-pci* \
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| 142 |
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designs/leon3-memec-v2mb1000 designs/leon3-actel* \
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| 143 |
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designs/ut699rh-evab \
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| 144 |
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verification/grusbhc verification/usbdcl \
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| 145 |
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lib/gaisler/sim/ulpi.vhd lib/gaisler/sim/utmi.vhd \
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| 146 |
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designs/actel-coremp7-1000 \
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| 147 |
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netlists/altera netlists/xilinx/*/grfpw* netlists/xilinx/*/xst
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| 148 |
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| 149 |
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INTFPGAFILES = \
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| 150 |
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verification/greth verification/greth/*gbit* \
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| 151 |
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designs/leon3-clk2x lib/gaisler/greth/*gbit* \
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| 152 |
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lib/grlib/amba/ahbctrl_mb.vhd \
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| 153 |
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lib/gaisler/misc/ahb2ahb.vhd lib/gaisler/misc/ahbbridge.vhd \
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| 154 |
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lib/gaisler/usb/usbdclc.vhd lib/gaisler/usb/grusb.vhd \
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| 155 |
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lib/gaisler/leon3/*2x* lib/gaisler/memctrl/ssrctrl.vhd \
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| 156 |
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lib/gaisler/greth/*gbit* \
|
| 157 |
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lib/gaisler/memctrl/ftsrctrl-v1.* \
|
| 158 |
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lib/gleichmann lib/openchip \
|
| 159 |
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designs/leon3-jopdesign-ep1c12 \
|
| 160 |
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designs/leon3-clock-gate \
|
| 161 |
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designs/leon3-asic \
|
| 162 |
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designs/leon3-ge-*
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| 163 |
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|
| 164 |
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VHDLP = vhdlp -s -work
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| 165 |
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SONATALIBSKIP = pere05
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| 166 |
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| 167 |
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ALIB = alib
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| 168 |
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ACOM = acom -quiet $(ACOMOPT) -accept87 -work
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| 169 |
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ALOG = alog -quiet $(ALOGOPT) -work
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| 170 |
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AVHDL = avhdl
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| 171 |
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| 172 |
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VLIB = vlib
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| 173 |
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VCOM = vcom -quiet $(VCOMOPT) -93 -work
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| 174 |
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VLOG = vlog -quiet $(VLOGOPT) -work
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| 175 |
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VSIM = vsim
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| 176 |
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| 177 |
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NCVHDL = ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work
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| 178 |
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NCVLOG = ncvlog -nowarn DLCPTH -nocopyright $(NCVLOGOPT) -work
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| 179 |
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|
| 180 |
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DCVHDL = analyze -f VHDL -library
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| 181 |
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DCVLOG = analyze -f VERILOG -library
|
| 182 |
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ifeq ("$(DCSCRIPT)","")
|
| 183 |
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DCSCRIPT=$(TOP).dc
|
| 184 |
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endif
|
| 185 |
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DCLIBSKIP = $(FPGALIBS) dw02 corePCIF
|
| 186 |
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#DCLIBSKIP = dw02 corePCIF
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| 187 |
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DCDIRSKIP = $(FPGALIBS) corePCIF pcif
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| 188 |
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#DCDIRSKIP = corePCIF pcif
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| 189 |
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XDCLIBSKIP = $(DCLIBSKIP:%=% | ) dummy
|
| 190 |
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XDCDIRSKIP = $(DCDIRSKIP:%=% | ) dummy
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| 191 |
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DCSKIP = $(DCLIBSKIP:%=*_%.vhd | ) dummy
|
| 192 |
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| 193 |
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RTLCVHDL = read_hdl -vhdl -lib
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| 194 |
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RTLCVLOG = read_hdl
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| 195 |
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RCSCRIPT=$(TOP).rc
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| 196 |
|
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| 197 |
|
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SYNPVHDL = add_file -vhdl -lib
|
| 198 |
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SYNPVLOG = add_file -verilog
|
| 199 |
|
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SYNPLIBSKIP = $(ASICLIBS)
|
| 200 |
|
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XSYNPLIBSKIP = $(SYNPLIBSKIP:%=%|) dw02
|
| 201 |
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XSYNPDIRSKIP = $(SYNPLIBSKIP:%=%|) dw02
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| 202 |
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|
| 203 |
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XSTVHDL = elaborate -ifmt vhdl -work_lib
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| 204 |
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XSTVLOG = elaborate -ifmt verilog -work_lib
|
| 205 |
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XSTLIBSKIPX = $(ASICLIBS) $(BRMLIBS) $(ACTELLIBS) $(ALTERALIBS) \
|
| 206 |
|
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$(LATTICELIBS) $(COREPCILIB) $(SIMLIBS)
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| 207 |
|
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XSTLIBSKIP = $(XSTLIBSKIPX:%=%|) dw02
|
| 208 |
|
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XSTDIRSKIPX = $(ASICLIBS) $(ACTELLIBS) $(ALTERALIBS) $(LATTICELIBS) grfpu grfpc grlfpc
|
| 209 |
|
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XSTDIRSKIP = $(XSTDIRSKIPX:%=%|) dw02
|
| 210 |
|
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#XSTSKIPX = $(XSTLIBSKIPX:%=*_%.vhd |)
|
| 211 |
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XSTSKIP = $(XSTSKIPX) b1553* | pci_components* | pcicore* | snpsmul.vhd
|
| 212 |
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|
|
| 213 |
|
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ifeq ("$(ISETECH)","")
|
| 214 |
|
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ISETECH=$(TECHNOLOGY)
|
| 215 |
|
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endif
|
| 216 |
|
|
|
| 217 |
|
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PRECLIBSKIPX = $(SIMLIBS) $(ASICLIBS)
|
| 218 |
|
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PRECLIBSKIP = $(PRECLIBSKIPX:%=%|) dw02
|
| 219 |
|
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PRECDIRSKIP = $(PRECLIBSKIPX:%=%|) dw02
|
| 220 |
|
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PRECSKIP = dummy
|
| 221 |
|
|
|
| 222 |
|
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XLIBEROLIBSKIP = $(ASICLIBS) $(LATTICELIBS) \
|
| 223 |
|
|
$(ALTERALIBS) $(XILINXLIBS)
|
| 224 |
|
|
LIBEROLIBSKIP = $(XLIBEROLIBSKIP:%=%|) dw02
|
| 225 |
|
|
LIBERODIRSKIPX = $(ASICLIBS) $(XILINXLIBS) $(ALTERALIBS) $(LATTICELIBS)
|
| 226 |
|
|
LIBERODIRSKIP = $(LIBERODIRSKIPX:%=%|) dw02
|
| 227 |
|
|
LIBEROSKIP = dummy
|
| 228 |
|
|
|
| 229 |
|
|
# The paths below apply to CoreConsole v. 1.4
|
| 230 |
|
|
ifeq ("$(CORECONSOLE)","")
|
| 231 |
|
|
CORECONSOLE = dummy
|
| 232 |
|
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else
|
| 233 |
|
|
CORECONSOLE_PATH = $(CORECONSOLE)/repository/Components/Actel/DirectCore
|
| 234 |
|
|
COREMP7BRIDGE_PATH = $(CORECONSOLE_PATH)/CoreMP7Bridge/2.1/rtl/vhdl/o
|
| 235 |
|
|
COREMP7BRIDGE_FILES = A7WrapMaster.vhd A7WrapSM.vhd CoreMP7Bridge_a3p.vhd Sync.vhd uj_jtag.vhd
|
| 236 |
|
|
COREMP7_PATH = $(CORECONSOLE_PATH)/A7S/2.0/M7A3P1000-2/debug/timingshell/vhdl
|
| 237 |
|
|
COREMP7_FILES = arm_synplify.vhd
|
| 238 |
|
|
endif
|
| 239 |
|
|
|
| 240 |
|
|
SYNPSKIP = snpsmul.vhd
|
| 241 |
|
|
|
| 242 |
|
|
GHDL = ghdl -a --ieee=synopsys
|
| 243 |
|
|
GHDLE = ghdl -e --ieee=synopsys
|
| 244 |
|
|
GHDLM = ghdl --gen-makefile --ieee=synopsys
|
| 245 |
|
|
GHDLSKIP = orca.vhd _ec.vhd grcan.vhd
|
| 246 |
|
|
|
| 247 |
|
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SYNPLIFY = synplify_pro
|
| 248 |
|
|
|
| 249 |
|
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DESIGNER = designer
|
| 250 |
|
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LIBERO = libero
|
| 251 |
|
|
|
| 252 |
|
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OS = `uname`
|
| 253 |
|
|
|
| 254 |
|
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UNISIM = $(XILINX)/vhdl/src/unisims/unisim_VPKG.vhd \
|
| 255 |
|
|
$(XILINX)/vhdl/src/unisims/unisim_VCOMP.vhd \
|
| 256 |
|
|
$(XILINX)/vhdl/src/unisims/unisim_VITAL.vhd
|
| 257 |
|
|
|
| 258 |
|
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SIMPRIM = $(XILINX)/vhdl/src/simprims/simprim_Vpackage.vhd \
|
| 259 |
|
|
$(XILINX)/vhdl/src/simprims/simprim_Vcomponents.vhd \
|
| 260 |
|
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$(XILINX)/vhdl/src/simprims/simprim_VITAL.vhd
|
| 261 |
|
|
|
| 262 |
|
|
|
| 263 |
|
|
#ifeq ("$(QUARTUS_ROOTDIR)","")
|
| 264 |
|
|
QUARTUS_MAP = quartus_map
|
| 265 |
|
|
QUARTUS_FIT = quartus_fit
|
| 266 |
|
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QUARTUS_ASM = quartus_asm
|
| 267 |
|
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QUARTUS_TAN = quartus_tan
|
| 268 |
|
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QUARTUS_PGM = quartus_pgm
|
| 269 |
|
|
#else
|
| 270 |
|
|
#QUARTUS_MAP = $(QUARTUS_ROOTDIR)/bin/quartus_map
|
| 271 |
|
|
#QUARTUS_FIT = $(QUARTUS_ROOTDIR)/bin/quartus_fit
|
| 272 |
|
|
#QUARTUS_ASM = $(QUARTUS_ROOTDIR)/bin/quartus_asm
|
| 273 |
|
|
#QUARTUS_TAN = $(QUARTUS_ROOTDIR)/bin/quartus_tan
|
| 274 |
|
|
#endif
|
| 275 |
|
|
ALTCABLE=USB-Blaster
|
| 276 |
|
|
QLIBSKIPX = $(SIMLIBS) $(ASICLIBS) $(BRMLIBS) $(ACTELLIBS) $(XILINXLIBS) \
|
| 277 |
|
|
$(LATTICELIBS) $(COREPCILIB)
|
| 278 |
|
|
QUARTUSLIBSKIP = $(QLIBSKIPX:%=%|) dw02
|
| 279 |
|
|
QDIRSKIPX = $(ASICLIBS) $(ACTELLIBS) $(XILINXLIBS) $(LATTICELIBS)
|
| 280 |
|
|
QDIRSKIP = $(QDIRSKIPX:%=%|) dw02 | satcan | leon2ft
|
| 281 |
|
|
QUARTUSSKIP = b1553* | pci_components* | pcicore* | snpsmul.vhd | \
|
| 282 |
|
|
grfpw_* | grlfpw_* | usbhc_stratixii.vhd | usbhc_stratixiipkg.vhd
|
| 283 |
|
|
|
| 284 |
|
|
SYN=synplify
|
| 285 |
|
|
SIM=$(VSIM)
|
| 286 |
|
|
PR=ise
|
| 287 |
|
|
|
| 288 |
|
|
PRECISION=precision
|
| 289 |
|
|
|
| 290 |
|
|
ifeq ("$(SIMTOP)","")
|
| 291 |
|
|
SIMTOP=$(TOP)
|
| 292 |
|
|
endif
|
| 293 |
|
|
|
| 294 |
|
|
ifeq ("$(LIBSKIP)","")
|
| 295 |
|
|
XLIBSKIP="x"
|
| 296 |
|
|
else
|
| 297 |
|
|
XLIBSKIP= $(LIBSKIP:%=%|) dummy
|
| 298 |
|
|
endif
|
| 299 |
|
|
|
| 300 |
|
|
YDIRSKIP=$(DIRSKIP) $(LIBSKIP)
|
| 301 |
|
|
|
| 302 |
|
|
ifeq ("$(YDIRSKIP)","")
|
| 303 |
|
|
XDIRSKIP="dummy"
|
| 304 |
|
|
else
|
| 305 |
|
|
XDIRSKIP= $(YDIRSKIP:%=%|) $(LIBSKIP:%=%|) dummy
|
| 306 |
|
|
endif
|
| 307 |
|
|
|
| 308 |
|
|
XFILESKIP = $(FILESKIP:%=%|) $(LIBSKIP:%=*_%.vhd|) dummy
|
| 309 |
|
|
|
| 310 |
|
|
all: help
|
| 311 |
|
|
|
| 312 |
|
|
help:
|
| 313 |
|
|
@echo
|
| 314 |
|
|
@echo " interactive targets:"
|
| 315 |
|
|
@echo
|
| 316 |
|
|
@echo " make avhdl-launch : start active-hdl gui mode"
|
| 317 |
|
|
@echo " make riviera-launch : start riviera"
|
| 318 |
|
|
@echo " make vsim-launch : start modelsim"
|
| 319 |
|
|
@echo " make ncsim-launch : compile design using ncsim"
|
| 320 |
|
|
@echo " make sonata-launch : compile design using sonata"
|
| 321 |
|
|
@echo " make actel-launch-synp : start Actel Designer for current project"
|
| 322 |
|
|
@echo " make ise-launch : start ISE project navigator for XST project"
|
| 323 |
|
|
@echo " make ise-launch-synp : start ISE project navigator for synplify project"
|
| 324 |
|
|
@echo " make quartus-launch : start Quartus for current project"
|
| 325 |
|
|
@echo " make quartus-launch-synp : start Quartus for synplify project"
|
| 326 |
|
|
@echo " make synplify-launch : start synplify"
|
| 327 |
|
|
@echo " make xgrlib : start grlib GUI"
|
| 328 |
|
|
@echo
|
| 329 |
|
|
@echo " batch targets:"
|
| 330 |
|
|
@echo
|
| 331 |
|
|
@echo " make avhdl : compile design using active-hdl gui mode"
|
| 332 |
|
|
@echo " make vsimsa : compile design using active-hdl batch mode"
|
| 333 |
|
|
@echo " make riviera : compile design using riviera"
|
| 334 |
|
|
@echo " make sonata : compile design using sonata"
|
| 335 |
|
|
@echo " make vsim : compile design using modelsim"
|
| 336 |
|
|
@echo " make ncsim : compile design using ncsim"
|
| 337 |
|
|
@echo " make ghdl : compile design using GHDL"
|
| 338 |
|
|
@echo " make actel : synthesize with synplify, place&route Actel Designer"
|
| 339 |
|
|
@echo " make ise : synthesize and place&route with Xilinx ISE"
|
| 340 |
|
|
@echo " make ise-map : synthesize design using Xilinx XST"
|
| 341 |
|
|
@echo " make ise-prec : synthesize with precision, place&route with Xilinx ISE"
|
| 342 |
|
|
@echo " make ise-synp : synthesize with synplify, place&route with Xilinx ISE"
|
| 343 |
|
|
@echo " make isp-synp : synthesize with synplify, place&route with ISPLever"
|
| 344 |
|
|
@echo " make quartus : synthesize and place&route using Quartus"
|
| 345 |
|
|
@echo " make quartus-map : synthesize design using Quartus"
|
| 346 |
|
|
@echo " make quartus-synp : synthesize with synplify, place&route with Quartus"
|
| 347 |
|
|
@echo " make precision : synthesize design using precision"
|
| 348 |
|
|
@echo " make synplify : synthesize design using synplify"
|
| 349 |
|
|
@echo " make import-actel-cc : import CoreMP7 files from CoreConsole library"
|
| 350 |
|
|
@echo " make scripts : generate compile scripts only"
|
| 351 |
|
|
@echo " make clean : remove all temporary files except scripts"
|
| 352 |
|
|
@echo " make distclean : remove all temporary files"
|
| 353 |
|
|
@echo
|
| 354 |
|
|
|
| 355 |
|
|
make xgrlib:
|
| 356 |
|
|
@if test -r "/mingw/bin/wish84.exe"; then \
|
| 357 |
|
|
if !(test -r "/mingw/bin/echo.bat"); then \
|
| 358 |
|
|
cp $(GRLIB)/bin/echo.bat /mingw/bin/echo.bat; \
|
| 359 |
|
|
fi; \
|
| 360 |
|
|
if !(test -r "/mingw/bin/wish"); then \
|
| 361 |
|
|
cp $(GRLIB)/bin/wish /mingw/bin/wish; \
|
| 362 |
|
|
fi; \
|
| 363 |
|
|
fi; \
|
| 364 |
|
|
$(GRLIB)/bin/xgrlib.tcl $(TOP) $(TECHNOLOGY) $(DEVICE) $(BOARD)
|
| 365 |
|
|
|
| 366 |
|
|
############ AHB ROM Geneartion ########################
|
| 367 |
|
|
|
| 368 |
|
|
FILE=prom.exe
|
| 369 |
|
|
|
| 370 |
|
|
ahbrom: $(GRLIB)/bin/ahbrom.c
|
| 371 |
|
|
$(CC) $(GRLIB)/bin/ahbrom.c -o ahbrom
|
| 372 |
|
|
|
| 373 |
|
|
ahbrom.vhd:
|
| 374 |
|
|
make ahbrom
|
| 375 |
|
|
sparc-elf-objcopy -O binary $(FILE) ahbrom.bin
|
| 376 |
|
|
./ahbrom ahbrom.bin ahbrom.vhd
|
| 377 |
|
|
|
| 378 |
|
|
######### Generic simulation target ###############
|
| 379 |
|
|
|
| 380 |
|
|
sim:
|
| 381 |
|
|
make $(SIM)
|
| 382 |
|
|
|
| 383 |
|
|
sim-run:
|
| 384 |
|
|
make $(SIM)-run
|
| 385 |
|
|
|
| 386 |
|
|
sim-launch:
|
| 387 |
|
|
make $(SIM)-launch
|
| 388 |
|
|
|
| 389 |
|
|
######### Symphony-EDA Sonata targets ############
|
| 390 |
|
|
|
| 391 |
|
|
make.son: compile.son
|
| 392 |
|
|
sonata sonata/compiled : make.son
|
| 393 |
|
|
@make -f make.son sonata-compile
|
| 394 |
|
|
@touch sonata/compiled
|
| 395 |
|
|
|
| 396 |
|
|
sonata-run : sonata/compiled
|
| 397 |
|
|
vhdle -ini sonata.sws -work sonata -breakon FAILURE -r 1ps testbench
|
| 398 |
|
|
|
| 399 |
|
|
sonata-launch : sonata/compiled
|
| 400 |
|
|
sonata sonata.sws
|
| 401 |
|
|
|
| 402 |
|
|
sonata-clean:
|
| 403 |
|
|
-rm -rf *\.sym sonata.sws sonata symphony.ini symphony.sws tmp.son
|
| 404 |
|
|
|
| 405 |
|
|
######### Active-HDL batch mode targets ############
|
| 406 |
|
|
|
| 407 |
|
|
vsimsa: compile.vsim
|
| 408 |
|
|
@cat libs.do | sed -e s/modelsim/activehdl/ | sed -e s/vlib/alib/ > alibs-batch.do
|
| 409 |
|
|
@echo "do alibs-batch.do" > vsimsa-batch.do
|
| 410 |
|
|
@vsimsa vsimsa-batch.do
|
| 411 |
|
|
@vmap work activehdl/work
|
| 412 |
|
|
@make -f make.vsim
|
| 413 |
|
|
@-rm -f alibs-batch.do vsimsa-batch.do
|
| 414 |
|
|
|
| 415 |
|
|
vsimsa-run:
|
| 416 |
|
|
@vsim $(SIMTOP) < $(GRLIB)/bin/runvsim.do
|
| 417 |
|
|
|
| 418 |
|
|
vsimsa-launch: vsimsa-run
|
| 419 |
|
|
|
| 420 |
|
|
vsimsa-clean:
|
| 421 |
|
|
-rm -rf activehdl vsimsa.cfg library.cfg wave.asdb alibs-batch.do vsimsa-batch.do
|
| 422 |
|
|
|
| 423 |
|
|
#vsimsa-modelsim:
|
| 424 |
|
|
# echo "importmodelsim $(SIMTOP).mpf" . > activehdl.tcl
|
| 425 |
|
|
# echo "quiet on" >> activehdl.tcl
|
| 426 |
|
|
# echo "SET SIM_WORKING_FOLDER ..\\.." >> activehdl.tcl
|
| 427 |
|
|
# AVHDL -do activehdl.tcl &
|
| 428 |
|
|
|
| 429 |
|
|
######### Active-HDL gui mode targets ############
|
| 430 |
|
|
|
| 431 |
|
|
avhdl: compile.asim
|
| 432 |
|
|
@echo "createdesign work ." > avhdl.tcl
|
| 433 |
|
|
@echo "opendesign -a work.adf" >> avhdl.tcl
|
| 434 |
|
|
@cat alibs.do >> avhdl.tcl
|
| 435 |
|
|
@echo "" >> avhdl.tcl
|
| 436 |
|
|
@cat make.asim-addfile >> avhdl.tcl
|
| 437 |
|
|
@cat make.asim >> avhdl.tcl
|
| 438 |
|
|
@echo "" >> avhdl.tcl
|
| 439 |
|
|
@echo SET SIM_WORKING_FOLDER $$\DSN/.. >> avhdl.tcl
|
| 440 |
|
|
@echo "" >> avhdl.tcl
|
| 441 |
|
|
@echo asim work.testbench >> avhdl.tcl
|
| 442 |
|
|
|
| 443 |
|
|
avhdl-run: avhdl-launch
|
| 444 |
|
|
|
| 445 |
|
|
avhdl-launch:
|
| 446 |
|
|
@avhdl -do avhdl.tcl
|
| 447 |
|
|
|
| 448 |
|
|
avhdl-clean:
|
| 449 |
|
|
-rm -rf work avhdl.tcl vsimsa.cfg wave.asdb
|
| 450 |
|
|
|
| 451 |
|
|
######### Riviera targets ############
|
| 452 |
|
|
|
| 453 |
|
|
riviera: compile.vsim
|
| 454 |
|
|
@cat libs.do | sed -e s/modelsim/riviera/ > rlibs.do
|
| 455 |
|
|
@vsimsa rlibs.do
|
| 456 |
|
|
@make -f make.vsim
|
| 457 |
|
|
@vmap work riviera/work
|
| 458 |
|
|
@-rm -f rlibs.do
|
| 459 |
|
|
|
| 460 |
|
|
riviera-run:
|
| 461 |
|
|
@vsim $(SIMTOP) < $(GRLIB)/bin/runvsim.do
|
| 462 |
|
|
|
| 463 |
|
|
riviera-launch:
|
| 464 |
|
|
@echo asim $(SIMTOP) > riviera.do
|
| 465 |
|
|
@echo run -all >> riviera.do
|
| 466 |
|
|
@echo abort >> riviera.do
|
| 467 |
|
|
@riviera riviera.do
|
| 468 |
|
|
|
| 469 |
|
|
riviera-clean:
|
| 470 |
|
|
-rm -rf riviera vsimsa.cfg wave.asdb riviera.do library.cfg .riviera_project rlibs.do
|
| 471 |
|
|
|
| 472 |
|
|
######### Modelsim targets ############
|
| 473 |
|
|
|
| 474 |
|
|
vsim: make.work
|
| 475 |
|
|
@make -f make.work
|
| 476 |
|
|
|
| 477 |
|
|
make.work: compile.vsim modelsim
|
| 478 |
|
|
@make -f make.vsim
|
| 479 |
|
|
@echo "" > make.work
|
| 480 |
|
|
@for i in `cat libs.txt`; do vmake $$i >> make.work ; done
|
| 481 |
|
|
|
| 482 |
|
|
modelsim: compile.vsim
|
| 483 |
|
|
@vsim -c -quiet -do "do libs.do; quit"
|
| 484 |
|
|
|
| 485 |
|
|
vsim-grlib: modelsim
|
| 486 |
|
|
make vsim
|
| 487 |
|
|
# @for i in `cat libs.txt`; do \
|
| 488 |
|
|
# make -f modelsim/make.$$i ; \
|
| 489 |
|
|
# done ;
|
| 490 |
|
|
|
| 491 |
|
|
vsim-run: vsim
|
| 492 |
|
|
@vsim -c $(SIMTOP) < $(GRLIB)/bin/runvsim.do
|
| 493 |
|
|
|
| 494 |
|
|
vsim-launch: scripts modelsim
|
| 495 |
|
|
@vsim -quiet $(SIMTOP).mpf
|
| 496 |
|
|
|
| 497 |
|
|
vsim-unisim: modelsim
|
| 498 |
|
|
vcom -quiet -explicit -work unisim $(UNISIM)
|
| 499 |
|
|
|
| 500 |
|
|
vsim-simprim: modelsim
|
| 501 |
|
|
vcom -quiet -explicit -work simprim -ignorevitalerrors $(SIMPRIM)
|
| 502 |
|
|
|
| 503 |
|
|
vsim-clean:
|
| 504 |
|
|
-rm -rf modelsim transcript *.mti stdout.log vsim.wlf \
|
| 505 |
|
|
$(SIMTOP).mpf.bak $(SIMTOP).mti *.mpf
|
| 506 |
|
|
|
| 507 |
|
|
vsim-fix:
|
| 508 |
|
|
cat make.work | sed 's/\([a-zA-Z]\)\(:\\\)/\/\1\//' > make.work2
|
| 509 |
|
|
mv make.work2 make.work
|
| 510 |
|
|
|
| 511 |
|
|
######### GHDL targets ############
|
| 512 |
|
|
|
| 513 |
|
|
ghdl $(SIMTOP): make.ghdl
|
| 514 |
|
|
make -f make.ghdl GHDLFLAGS="--workdir=gnu/work --work=work `cat ghdl.path`"
|
| 515 |
|
|
|
| 516 |
|
|
make.ghdl: compile.ghdl
|
| 517 |
|
|
-rm -rf gnu
|
| 518 |
|
|
make -f tmpmake.ghdl ghdl
|
| 519 |
|
|
$(GHDLE) $(VHDLOPT) --workdir=gnu/work --work=work `cat ghdl.path` $(SIMTOP)
|
| 520 |
|
|
$(GHDLM) $(VHDLOPT) --workdir=gnu/work --work=work `cat ghdl.path` $(SIMTOP) > make.ghdl
|
| 521 |
|
|
cat tmpmake.ghdl >> make.ghdl
|
| 522 |
|
|
|
| 523 |
|
|
ghdl-run ghdl-launch: $(TOP)
|
| 524 |
|
|
./$(SIMTOP)
|
| 525 |
|
|
|
| 526 |
|
|
ghdl-clean:
|
| 527 |
|
|
-rm -rf gnu $(SIMTOP) make.ghdl
|
| 528 |
|
|
|
| 529 |
|
|
######### NcSim targets ############
|
| 530 |
|
|
|
| 531 |
|
|
ncsim: xncsim/done
|
| 532 |
|
|
ncupdate $(SIMTOP)
|
| 533 |
|
|
|
| 534 |
|
|
ncsim-run: ncsim
|
| 535 |
|
|
ncsim $(SIMTOP)
|
| 536 |
|
|
|
| 537 |
|
|
ncsim-launch: ncsim
|
| 538 |
|
|
ncsim -gui $(SIMTOP)&
|
| 539 |
|
|
|
| 540 |
|
|
xncsim xncsim/done : compile.ncsim
|
| 541 |
|
|
-rm -rf xncsim
|
| 542 |
|
|
make -f make.ncsim
|
| 543 |
|
|
touch xncsim/done
|
| 544 |
|
|
|
| 545 |
|
|
ncsim-clean:
|
| 546 |
|
|
-rm -rf xncsim nc*.log ncsim.key
|
| 547 |
|
|
|
| 548 |
|
|
######### Lattice ISE targets ############
|
| 549 |
|
|
|
| 550 |
|
|
isp-synp: $(TOP)_synplify.prj synplify/$(TOP).edf
|
| 551 |
|
|
$(GRLIB)/bin/route_lattice $(TOP) $(UCF) $(PART) synplify $(ISPLIB) $(ISPPACKAGE) $(BITGEN)
|
| 552 |
|
|
|
| 553 |
|
|
isp-prec: $(TOP)_precision.prj precision/$(TOP).edf
|
| 554 |
|
|
$(GRLIB)/bin/route_lattice $(TOP) $(UCF) $(PART) precision $(ISPLIB) $(ISPPACKAGE) $(BITGEN)
|
| 555 |
|
|
|
| 556 |
|
|
isp-launch-synp: $(TOP)_synplify.prj synplify/$(TOP).edf
|
| 557 |
|
|
projnav ./$(TOP).syn
|
| 558 |
|
|
|
| 559 |
|
|
isp-launch-prec: $(TOP)_precision.prj precision/$(TOP).edf
|
| 560 |
|
|
projnav ./$(TOP)_precision.syn
|
| 561 |
|
|
|
| 562 |
|
|
isp-prom:
|
| 563 |
|
|
synsvf $(PROMGENPAR)
|
| 564 |
|
|
isp-clean:
|
| 565 |
|
|
-rm -rf $(TOP).dir *.jid *.alt *.lci *.mt *.nc1 *.nc2 *.p?t \
|
| 566 |
|
|
*.err compxlib.cfg *.jhd *.lct $(TOP).log *.ngy *.prf *.pt *.rev \
|
| 567 |
|
|
*.syn *.t2b *.tcm *.tcp *.tw1 $(TOP).tcl *.sty *.svl *.env fonts.dir \
|
| 568 |
|
|
$(TOP)_tcl.ini
|
| 569 |
|
|
|
| 570 |
|
|
|
| 571 |
|
|
|
| 572 |
|
|
######### Xilinx ISE targets ############
|
| 573 |
|
|
|
| 574 |
|
|
ise: $(TOP).ngc
|
| 575 |
|
|
$(GRLIB)/bin/route_ngc $(TOP) $(UCF) $(DEVICE) $(EFFORT) $(BITGEN) $(GRLIB)/netlists/xilinx/$(TECHNOLOGY)
|
| 576 |
|
|
|
| 577 |
|
|
ise-synp: $(TOP)_synplify.prj synplify/$(TOP).edf
|
| 578 |
|
|
$(GRLIB)/bin/route $(TOP) $(UCF) $(DEVICE) $(EFFORT) $(BITGEN) synplify \
|
| 579 |
|
|
$(GRLIB)/netlists/xilinx/$(TECHNOLOGY) $(ISEMAPOPT)
|
| 580 |
|
|
|
| 581 |
|
|
ise-prec: $(TOP).psp precision/$(TOP).edf
|
| 582 |
|
|
$(GRLIB)/bin/route $(TOP) $(UCF) $(DEVICE) $(EFFORT) $(BITGEN) precision \
|
| 583 |
|
|
$(GRLIB)/netlists/xilinx/$(TECHNOLOGY) $(ISEMAPOPT)
|
| 584 |
|
|
|
| 585 |
|
|
ise-launch8 xst-launch: $(TOP).npl $(TOP)_ise.tcl
|
| 586 |
|
|
ise $(TOP).npl>& ise.err&
|
| 587 |
|
|
|
| 588 |
|
|
ise-launch : $(TOP).ise
|
| 589 |
|
|
ise $(TOP).ise
|
| 590 |
|
|
|
| 591 |
|
|
ise-launch-synp: $(TOP).npl $(TOP)_synplify.prj synplify/$(TOP).edf $(TOP)_synplify.prj
|
| 592 |
|
|
ise $(TOP)_synplify.npl>& ise.err&
|
| 593 |
|
|
|
| 594 |
|
|
$(TOP).xst: compile.xst
|
| 595 |
|
|
@touch $(TOP).xst; rm $(TOP).xst
|
| 596 |
|
|
@for i in $(VHDLSYNFILES); do $(GRLIB)/bin/xstvhdl $$i >> $(TOP).xst ; done
|
| 597 |
|
|
# @for i in $(VERILOGSYNFILES); do $(GRLIB)/bin/xstverilog $ii >> $(TOP).xst; done
|
| 598 |
|
|
@$(GRLIB)/bin/xstrun $(TOP) $(TOP).vhd $(DEVICE) $(XSTOPT) -sd $(GRLIB)/netlists/xilinx/$(TECHNOLOGY)/xst >> $(TOP).xst
|
| 599 |
|
|
@echo $(TOP).xst
|
| 600 |
|
|
|
| 601 |
|
|
ise-xstmod :
|
| 602 |
|
|
$(GRLIB)/bin/xstmod $(CORE) $(CORE).vhd $(DEVICE) vhdl > tmp.xst
|
| 603 |
|
|
xst -ifn tmp.xst
|
| 604 |
|
|
|
| 605 |
|
|
$(TOP).bit: $(TOP).ngc
|
| 606 |
|
|
$(GRLIB)/bin/route_ngc $(TOP) $(UCF) $(DEVICE) $(EFFORT) $(BITGEN) $(GRLIB)/netlists/xilinx/$(TECHNOLOGY)
|
| 607 |
|
|
|
| 608 |
|
|
ise-map xst-map ise-xst xst: $(TOP).ngc
|
| 609 |
|
|
|
| 610 |
|
|
$(TOP).ngc: $(TOP).xst $(VHDLSYNFILES) $(VERILOGSYNFILES) compile.xst
|
| 611 |
|
|
-rm -rf xst
|
| 612 |
|
|
xst -ifn compile.xst
|
| 613 |
|
|
xst -ifn $(TOP).xst
|
| 614 |
|
|
|
| 615 |
|
|
$(TOP).ise: $(TOP)_ise.tcl
|
| 616 |
|
|
xtclsh $(TOP)_ise.tcl
|
| 617 |
|
|
|
| 618 |
|
|
ise-prom:
|
| 619 |
|
|
ifeq ("$(PROMGENPAR)","")
|
| 620 |
|
|
@echo "not prom programming support for this board"
|
| 621 |
|
|
@exit 1
|
| 622 |
|
|
else
|
| 623 |
|
|
promgen $(PROMGENPAR)
|
| 624 |
|
|
cp $(TOP).bit $(BOARD).bit
|
| 625 |
|
|
cp $(TOP).msk $(BOARD).msk
|
| 626 |
|
|
endif
|
| 627 |
|
|
|
| 628 |
|
|
ise-cp-ref:
|
| 629 |
|
|
cp bitfiles/*.* .
|
| 630 |
|
|
|
| 631 |
|
|
ise-prog-prom: ise-prom
|
| 632 |
|
|
impact -batch $(GRLIB)/boards/$(BOARD)/prom.cmd
|
| 633 |
|
|
|
| 634 |
|
|
ise-prog-prom-usb: ise-prom
|
| 635 |
|
|
impact -batch $(GRLIB)/boards/$(BOARD)/prom-usb.cmd
|
| 636 |
|
|
|
| 637 |
|
|
ise-prog-prom-ref: ise-cp-ref ise-prom
|
| 638 |
|
|
impact -batch $(GRLIB)/boards/$(BOARD)/prom.cmd
|
| 639 |
|
|
|
| 640 |
|
|
ise-prog-prom-ref-usb: ise-cp-ref ise-prom
|
| 641 |
|
|
impact -batch $(GRLIB)/boards/$(BOARD)/prom-usb.cmd
|
| 642 |
|
|
|
| 643 |
|
|
ise-prog-fpga:
|
| 644 |
|
|
cp $(TOP).bit $(BOARD).bit
|
| 645 |
|
|
cp $(TOP).msk $(BOARD).msk
|
| 646 |
|
|
impact -batch $(GRLIB)/boards/$(BOARD)/fpga.cmd
|
| 647 |
|
|
|
| 648 |
|
|
ise-prog-fpga-usb:
|
| 649 |
|
|
cp $(TOP).bit $(BOARD).bit
|
| 650 |
|
|
cp $(TOP).msk $(BOARD).msk
|
| 651 |
|
|
impact -batch $(GRLIB)/boards/$(BOARD)/fpga-usb.cmd
|
| 652 |
|
|
|
| 653 |
|
|
|
| 654 |
|
|
ise-prog-fpga-ref: ise-cp-ref
|
| 655 |
|
|
cp $(TOP).bit $(BOARD).bit
|
| 656 |
|
|
cp $(TOP).msk $(BOARD).msk
|
| 657 |
|
|
impact -batch $(GRLIB)/boards/$(BOARD)/fpga.cmd
|
| 658 |
|
|
|
| 659 |
|
|
ise-prog-fpga-ref-usb: ise-cp-ref
|
| 660 |
|
|
cp $(TOP).bit $(BOARD).bit
|
| 661 |
|
|
cp $(TOP).msk $(BOARD).msk
|
| 662 |
|
|
impact -batch $(GRLIB)/boards/$(BOARD)/fpga-usb.cmd
|
| 663 |
|
|
|
| 664 |
|
|
ise-clean xst-clean:
|
| 665 |
|
|
-rm -rf xst *.srp xstmods *.twr *.pad _impact* coregen.log \
|
| 666 |
|
|
tmp.xst *.ngc __projnav* *.stx *.lso *.dhp automake.log \
|
| 667 |
|
|
$(TOP).prj $(TOP)_vhdl.prj coregen* *.bit *.bgn *.bld \
|
| 668 |
|
|
*.cmd_log *.ll *.mrp *.msk *.ncd *.ngd *.syr *.xpi *.csv \
|
| 669 |
|
|
*pad.txt *.ngm *.lst *.drc *.par *.pcf *.ngo *.mcs *.prm \
|
| 670 |
|
|
*.sig *.rba *.rbb *.rbd *.rbt *.msd _ngo _impact* stdout.log \
|
| 671 |
|
|
ngd2vhdl.log _xmsgs tmp.txt $(TOP).unroutes $(TOP)_usage.xml *.cfi \
|
| 672 |
|
|
$(TOP).ise* $(TOP).npl* xlnx_auto_0* *.xrpt *.ptwx $(TOP)_xdb \
|
| 673 |
|
|
$(TOP)_summary.html $(TOP).restore $(TOP).ntrc_log $(TOP).twx \
|
| 674 |
|
|
$(TOP)_map.map $(TOP).ngr
|
| 675 |
|
|
|
| 676 |
|
|
######### Altera Quartus targets ############
|
| 677 |
|
|
|
| 678 |
|
|
quartus:
|
| 679 |
|
|
-@case $(TECHNOLOGY) in \
|
| 680 |
|
|
CYCLONEII) \
|
| 681 |
|
|
cp $(GRLIB)/netlists/altera/cyclone2/*.vqm . ;;\
|
| 682 |
|
|
CYCLONEIII) \
|
| 683 |
|
|
cp $(GRLIB)/netlists/altera/cyclone3/*.vqm . ;;\
|
| 684 |
|
|
STRATIXII) \
|
| 685 |
|
|
cp $(GRLIB)/netlists/altera/stratix2/*.vqm . ;;\
|
| 686 |
|
|
esac
|
| 687 |
|
|
make quartus-map quartus-route
|
| 688 |
|
|
|
| 689 |
|
|
quartus-synp: $(TOP)_synplify.prj synplify/$(TOP).edf
|
| 690 |
|
|
-@case $(TECHNOLOGY) in \
|
| 691 |
|
|
CYCLONEII) \
|
| 692 |
|
|
cp $(GRLIB)/netlists/altera/cyclone2/*.vqm . ;;\
|
| 693 |
|
|
CYCLONEIII) \
|
| 694 |
|
|
cp $(GRLIB)/netlists/altera/cyclone3/*.vqm . ;;\
|
| 695 |
|
|
STRATIXII) \
|
| 696 |
|
|
cp $(GRLIB)/netlists/altera/stratix2/*.vqm . ;;\
|
| 697 |
|
|
esac
|
| 698 |
|
|
@-cp synplify/*.hex .
|
| 699 |
|
|
$(QUARTUS_MAP) --import_settings_files=on --export_settings_files=off $(TOP)_synplify -c $(TOP)_synplify
|
| 700 |
|
|
$(QUARTUS_FIT) --import_settings_files=off --export_settings_files=off $(TOP)_synplify -c $(TOP)_synplify
|
| 701 |
|
|
$(QUARTUS_ASM) --import_settings_files=off --export_settings_files=off $(TOP)_synplify -c $(TOP)_synplify
|
| 702 |
|
|
$(QUARTUS_TAN) --import_settings_files=off --export_settings_files=off $(TOP)_synplify -c $(TOP)_synplify --timing_analysis_only
|
| 703 |
|
|
|
| 704 |
|
|
quartus-launch: $(TOP).qsf
|
| 705 |
|
|
-@case $(TECHNOLOGY) in \
|
| 706 |
|
|
CYCLONEII) \
|
| 707 |
|
|
cp $(GRLIB)/netlists/altera/cyclone2/*.vqm . ;;\
|
| 708 |
|
|
CYCLONEIII) \
|
| 709 |
|
|
cp $(GRLIB)/netlists/altera/cyclone3/*.vqm . ;;\
|
| 710 |
|
|
STRATIXII) \
|
| 711 |
|
|
cp $(GRLIB)/netlists/altera/stratix2/*.vqm . ;;\
|
| 712 |
|
|
esac
|
| 713 |
|
|
quartus $(TOP).qpf
|
| 714 |
|
|
|
| 715 |
|
|
quartus-launch-synp: $(TOP)_synplify.prj synplify/$(TOP).edf
|
| 716 |
|
|
-@case $(TECHNOLOGY) in \
|
| 717 |
|
|
CYCLONEII) \
|
| 718 |
|
|
cp $(GRLIB)/netlists/altera/cyclone2/*.vqm . ;;\
|
| 719 |
|
|
CYCLONEIII) \
|
| 720 |
|
|
cp $(GRLIB)/netlists/altera/cyclone3/*.vqm . ;;\
|
| 721 |
|
|
STRATIXII) \
|
| 722 |
|
|
cp $(GRLIB)/netlists/altera/stratix2/*.vqm . ;;\
|
| 723 |
|
|
esac
|
| 724 |
|
|
quartus $(TOP)_synplify.qpf
|
| 725 |
|
|
|
| 726 |
|
|
quartus-map: $(TOP).qsf
|
| 727 |
|
|
-@case $(TECHNOLOGY) in \
|
| 728 |
|
|
CYCLONEII) \
|
| 729 |
|
|
cp $(GRLIB)/netlists/altera/cyclone2/*.vqm . ;;\
|
| 730 |
|
|
CYCLONEIII) \
|
| 731 |
|
|
cp $(GRLIB)/netlists/altera/cyclone3/*.vqm . ;;\
|
| 732 |
|
|
STRATIXII) \
|
| 733 |
|
|
cp $(GRLIB)/netlists/altera/stratix2/*.vqm . ;;\
|
| 734 |
|
|
esac
|
| 735 |
|
|
$(QUARTUS_MAP) --import_settings_files=on --export_settings_files=off $(TOP) -c $(TOP)
|
| 736 |
|
|
|
| 737 |
|
|
quartus-route: $(TOP).qsf
|
| 738 |
|
|
$(QUARTUS_FIT) --import_settings_files=off --export_settings_files=off $(TOP) -c $(TOP)
|
| 739 |
|
|
$(QUARTUS_ASM) --import_settings_files=off --export_settings_files=off $(TOP) -c $(TOP)
|
| 740 |
|
|
$(QUARTUS_TAN) --import_settings_files=off --export_settings_files=off $(TOP) -c $(TOP) --timing_analysis_only
|
| 741 |
|
|
|
| 742 |
|
|
quartus-prog-fpga:
|
| 743 |
|
|
$(QUARTUS_PGM) -c $(ALTCABLE) -m JTAG -o p\;$(TOP).sof
|
| 744 |
|
|
|
| 745 |
|
|
quartus-prog-fpga-ref:
|
| 746 |
|
|
cp bitfiles/$(TOP).sof $(TOP)_ref.sof
|
| 747 |
|
|
$(QUARTUS_PGM) -c $(CABLE) -m JTAG -o p\;$(TOP)_ref.sof
|
| 748 |
|
|
|
| 749 |
|
|
quartus-srec:
|
| 750 |
|
|
$(QUARTUS_PGM)
|
| 751 |
|
|
|
| 752 |
|
|
quartus-clean:
|
| 753 |
|
|
-rm -rf db *.syr *.qws automake.log dumpdata.txt \
|
| 754 |
|
|
*.rpt *.done *.eqn *.pof *.summary *.ttf *.pin *.sof \
|
| 755 |
|
|
*.jam *.jbc cmp_state.ini simulation undo_redo.txt *.vqm *.qdf \
|
| 756 |
|
|
*.csf *.psf *.quartus *.smsg .undefinedlib .jaguarc .unorderedFilePath
|
| 757 |
|
|
|
| 758 |
|
|
######## Synplify targets ########################
|
| 759 |
|
|
|
| 760 |
|
|
synplify synplify-map: $(TOP)_synplify.prj synplify/$(TOP).edf
|
| 761 |
|
|
|
| 762 |
|
|
synplify-launch: $(TOP)_synplify.prj
|
| 763 |
|
|
$(SYNPLIFY) $(TOP)_synplify.prj&
|
| 764 |
|
|
-@mkdir synplify>& tmp.err; touch synplify/dummy.mif
|
| 765 |
|
|
-@mv synplify/*.mif .
|
| 766 |
|
|
|
| 767 |
|
|
synplify/$(TOP).edf: $(VHDLSYNFILES) $(VERILOGSYNFILES)
|
| 768 |
|
|
$(SYNPLIFY) -batch $(TOP)_synplify.prj
|
| 769 |
|
|
@touch synplify/dummy.mif
|
| 770 |
|
|
-@mv synplify/*.mif .
|
| 771 |
|
|
|
| 772 |
|
|
$(TOP)_synplify.prj: compile.synp
|
| 773 |
|
|
@echo source compile.synp > $(TOP)_synplify.prj
|
| 774 |
|
|
@for i in $(VHDLSYNFILES); do echo add_file "-vhdl -lib work" $$i >> $(TOP)_synplify.prj; done
|
| 775 |
|
|
# @for i in $(VERILOGSYNFILES); do echo add_file "-verilog -lib work" $ii >> $(TOP)_synplify.prj; done
|
| 776 |
|
|
@for i in $(SDCFILE); do echo add_file "-constraint " $$i >> $(TOP)_synplify.prj; done
|
| 777 |
|
|
@cat $(GRLIB)/bin/synplify.prj | sed -e s/TOP/$(TOP)/ \
|
| 778 |
|
|
-e s/TECHNOLOGY/$(TECHNOLOGY)/ \
|
| 779 |
|
|
-e s/PART/$(PART)/ -e s/SPEED/$(SPEED)/ -e s/SYNFREQ/$(SYNFREQ)/ >> $(TOP)_synplify.prj
|
| 780 |
|
|
ifneq ("$(PACKAGE)","")
|
| 781 |
|
|
@echo set_option -package $(PACKAGE) >> $(TOP)_synplify.prj
|
| 782 |
|
|
endif
|
| 783 |
|
|
ifneq ("$(SYNPVLOGDEFS)","")
|
| 784 |
|
|
@echo set_option -hdl_define -set \"$(SYNPVLOGDEFS)\" >> $(TOP)_synplify.prj
|
| 785 |
|
|
endif
|
| 786 |
|
|
ifneq ("$(SYNPVLOGINC)","")
|
| 787 |
|
|
@echo set_option -include_path \"$(SYNPVLOGINC)\" >> $(TOP)_synplify.prj
|
| 788 |
|
|
endif
|
| 789 |
|
|
@echo $(SYNPOPT) >> $(TOP)_synplify.prj
|
| 790 |
|
|
@echo impl -active \"synplify\" >> $(TOP)_synplify.prj
|
| 791 |
|
|
@echo $(TOP)_synplify.prj
|
| 792 |
|
|
|
| 793 |
|
|
synplify-clean:
|
| 794 |
|
|
-rm -rf synplify *.prd stdout.log *.mif syntmp.* synplify_* \
|
| 795 |
|
|
$(TOP).map $(TOP)_summary.xml
|
| 796 |
|
|
|
| 797 |
|
|
######## Precision targets ########################
|
| 798 |
|
|
|
| 799 |
|
|
precision precision-map: $(TOP)_precision.tcl $(TOP).psp precision/$(TOP).edf
|
| 800 |
|
|
|
| 801 |
|
|
$(TOP).psp: $(TOP)_precision.tcl
|
| 802 |
|
|
$(PRECISION) -shell -file $(TOP)_precision.tcl
|
| 803 |
|
|
|
| 804 |
|
|
precision-launch: $(TOP).psp
|
| 805 |
|
|
$(PRECISION) -project $(TOP).psp
|
| 806 |
|
|
|
| 807 |
|
|
precision/$(TOP).edf: $(TOP)_precision.tcl $(VHDLSYNFILES) $(VERILOGSYNFILES)
|
| 808 |
|
|
$(PRECISION) -shell -file $(TOP)_precrun.tcl
|
| 809 |
|
|
|
| 810 |
|
|
precision-clean:
|
| 811 |
|
|
-rm -rf *.psp stdout.log prec.log $(TOP)_prec* precision* $(TOP)_temp*
|
| 812 |
|
|
|
| 813 |
|
|
######### Actel Libero targets ############################
|
| 814 |
|
|
|
| 815 |
|
|
libero-launch : $(TOP)_libero.prj
|
| 816 |
|
|
$(LIBERO) $(TOP)_libero.prj
|
| 817 |
|
|
|
| 818 |
|
|
######### Actel Designer targets ############################
|
| 819 |
|
|
|
| 820 |
|
|
actel: $(TOP)_synplify.prj synplify/$(TOP).edf $(TOP)_designer.tcl
|
| 821 |
|
|
-mkdir ./actel
|
| 822 |
|
|
$(DESIGNER) script:$(TOP)_designer.tcl
|
| 823 |
|
|
|
| 824 |
|
|
actel-launch actel-launch-synp: $(TOP)_synplify.prj synplify/$(TOP).edf $(TOP)_designer.tcl $(TOP).adb
|
| 825 |
|
|
$(DESIGNER) $(TOP).adb &
|
| 826 |
|
|
|
| 827 |
|
|
$(TOP).adb:
|
| 828 |
|
|
$(DESIGNER) script:$(TOP)_designer_act.tcl
|
| 829 |
|
|
|
| 830 |
|
|
$(TOP)_designer.tcl:
|
| 831 |
|
|
@echo "new_design -name \""$(TOP)\"" -family \""$(TECHNOLOGY)\"" " > $(TOP)_designer.tcl
|
| 832 |
|
|
ifeq ("$(DESIGNER_RADEXP)","")
|
| 833 |
|
|
@echo "set_device -die \""$(PART)\"" -package \""$(DESIGNER_PINS) $(DESIGNER_PACKAGE)\"" -speed \""$(SPEED)\"" -voltage \"1.5\" -iostd \"LVTTL\" -jtag \"yes\" -probe \"yes\" -trst \"yes\" -temprange \""$(DESIGNER_VOLTAGE)\"" -voltrange \""$(DESIGNER_VOLTAGE)\"" " >> $(TOP)_designer.tcl
|
| 834 |
|
|
else
|
| 835 |
|
|
@echo "set_device -die \""$(PART)\"" -package \""$(DESIGNER_PINS) $(DESIGNER_PACKAGE)\"" -speed \""$(SPEED)\"" -voltage \"1.5\" -iostd \"LVTTL\" -jtag \"yes\" -probe \"yes\" -trst \"yes\" -temprange \""$(DESIGNER_VOLTAGE)\"" -voltrange \""$(DESIGNER_VOLTAGE)\"" -radexp \""$(DESIGNER_RADEXP)\"" " >> $(TOP)_designer.tcl
|
| 836 |
|
|
endif
|
| 837 |
|
|
@echo "if {[file exist "$(TOP).pdc"]} {" >> $(TOP)_designer.tcl
|
| 838 |
|
|
@echo "import_source -format \"edif\" -edif_flavor \"GENERIC\" " -merge_physical \"no\" -merge_timing \"no\"" {"synplify/$(TOP)".edf"} -format \"pdc\" -abort_on_error \"no\" {"$(TOP).pdc"} >> $(TOP)_designer.tcl
|
| 839 |
|
|
@echo "} else {" >> $(TOP)_designer.tcl
|
| 840 |
|
|
@echo "import_source -format \"edif\" -edif_flavor \"GENERIC\" " -merge_physical \"no\" -merge_timing \"no\"" {"synplify/$(TOP)".edf"} >> $(TOP)_designer.tcl
|
| 841 |
|
|
@echo "}" >> $(TOP)_designer.tcl
|
| 842 |
|
|
@cp $(TOP)_designer.tcl $(TOP)_designer_act.tcl
|
| 843 |
|
|
@echo "save_design {"$(TOP).adb"}" >> $(TOP)_designer_act.tcl
|
| 844 |
|
|
@echo "compile -combine_register 1" >> $(TOP)_designer.tcl
|
| 845 |
|
|
@echo "if {[file exist "$(PDC)"]} {" >> $(TOP)_designer.tcl
|
| 846 |
|
|
@echo " import_aux -format \"pdc\" -abort_on_error \"no\" {"$(PDC)"}" >> $(TOP)_designer.tcl
|
| 847 |
|
|
@echo " pin_commit" >> $(TOP)_designer.tcl
|
| 848 |
|
|
@echo "} else {" >> $(TOP)_designer.tcl
|
| 849 |
|
|
@echo " puts \"WARNING: No PDC file imported.\"" >> $(TOP)_designer.tcl
|
| 850 |
|
|
@echo "}" >> $(TOP)_designer.tcl
|
| 851 |
|
|
ifeq ("$(PDC_EXTRA)","")
|
| 852 |
|
|
else
|
| 853 |
|
|
@echo "if {[file exist "$(PDC_EXTRA)"]} {" >> $(TOP)_designer.tcl
|
| 854 |
|
|
@echo " import_aux -format \"pdc\" -abort_on_error \"no\" {"$(PDC_EXTRA)"}" >> $(TOP)_designer.tcl
|
| 855 |
|
|
@echo " pin_commit" >> $(TOP)_designer.tcl
|
| 856 |
|
|
@echo "} else {" >> $(TOP)_designer.tcl
|
| 857 |
|
|
@echo " puts \"WARNING: No PDC_EXTRA file imported.\"" >> $(TOP)_designer.tcl
|
| 858 |
|
|
@echo "}" >> $(TOP)_designer.tcl
|
| 859 |
|
|
endif
|
| 860 |
|
|
|
| 861 |
|
|
@echo "if {[file exist "$(SDC)"]} {" >> $(TOP)_designer.tcl
|
| 862 |
|
|
@echo " import_aux -format \"sdc\" -merge_timing \"no\" {"$(SDC)"}" >> $(TOP)_designer.tcl
|
| 863 |
|
|
@echo "} else {" >> $(TOP)_designer.tcl
|
| 864 |
|
|
@echo " puts \"WARNING: No SDC file imported.\"" >> $(TOP)_designer.tcl
|
| 865 |
|
|
@echo "}" >> $(TOP)_designer.tcl
|
| 866 |
|
|
ifeq ("$(SDC_EXTRA)","")
|
| 867 |
|
|
else
|
| 868 |
|
|
@echo "if {[file exist "$(SDC_EXTRA)"]} {" >> $(TOP)_designer.tcl
|
| 869 |
|
|
@echo " import_aux -format \"sdc\" -merge_timing \"yes\" {"$(SDC_EXTRA)"}" >> $(TOP)_designer.tcl
|
| 870 |
|
|
@echo "} else {" >> $(TOP)_designer.tcl
|
| 871 |
|
|
@echo " puts \"WARNING: No SDC_EXTRA file imported.\"" >> $(TOP)_designer.tcl
|
| 872 |
|
|
@echo "}" >> $(TOP)_designer.tcl
|
| 873 |
|
|
endif
|
| 874 |
|
|
@echo "save_design {"$(TOP).adb"}" >> $(TOP)_designer.tcl
|
| 875 |
|
|
@echo "report -type status {./actel/report_status_pre.log}" >> $(TOP)_designer.tcl
|
| 876 |
|
|
ifeq ("$(TECHNOLOGY)","AXCELERATOR")
|
| 877 |
|
|
@echo "layout -effort_level 5 -timing_driven -incremental \"OFF\"" >> $(TOP)_designer.tcl
|
| 878 |
|
|
else
|
| 879 |
|
|
@echo "layout -timing_driven -incremental \"OFF\"" >> $(TOP)_designer.tcl
|
| 880 |
|
|
endif
|
| 881 |
|
|
@echo "save_design {"$(TOP).adb"}" >> $(TOP)_designer.tcl
|
| 882 |
|
|
@echo "backannotate -dir {./actel} -name \"$(TOP)\" -format \"SDF\" -language \"VHDL93\" -netlist" >> $(TOP)_designer.tcl
|
| 883 |
|
|
@echo "report -type \"timer\" -sortby \"actual\" -maxpaths \"100\" -case \"worst\" -path_selection \"critical\" -setup_hold \"on\" -expand_failed \"off\" -clkpinbreak \"off\" -clrpinbreak \"on\" -latchdatapinbreak \"off\" -slack {./actel/report_timer_worst.txt}" >> $(TOP)_designer.tcl
|
| 884 |
|
|
@echo "report -type \"timer\" -sortby \"actual\" -maxpaths \"100\" -case \"best\" -path_selection \"critical\" -setup_hold \"on\" -expand_failed \"off\" -clkpinbreak \"off\" -clrpinbreak \"on\" -latchdatapinbreak \"off\" -slack {./actel/report_timer_best.txt}" >> $(TOP)_designer.tcl
|
| 885 |
|
|
@echo "report -type \"timer\" -analysis \"max\" -print_summary \"yes\" -use_slack_threshold \"no\" -print_paths \"yes\" -max_paths 100 -max_expanded_paths 5 -include_user_sets \"yes\" -include_pin_to_pin \"yes\" -select_clock_domains \"no\" {./actel/report_timer_max.txt}" >> $(TOP)_designer.tcl
|
| 886 |
|
|
@echo "report -type \"timer\" -analysis \"min\" -print_summary \"yes\" -use_slack_threshold \"no\" -print_paths \"yes\" -max_paths 100 -max_expanded_paths 5 -include_user_sets \"yes\" -include_pin_to_pin \"yes\" -select_clock_domains \"no\" {./actel/report_timer_min.txt}" >> $(TOP)_designer.tcl
|
| 887 |
|
|
@echo "report -type \"pin\" -listby \"name\" {./actel/report_pin_name.log}" >> $(TOP)_designer.tcl
|
| 888 |
|
|
@echo "report -type \"pin\" -listby \"number\" {./actel/report_pin_number.log}" >> $(TOP)_designer.tcl
|
| 889 |
|
|
@echo "report -type \"datasheet\" {./actel/report_datasheet.txt}" >> $(TOP)_designer.tcl
|
| 890 |
|
|
ifeq ("$(TECHNOLOGY)","AXCELERATOR")
|
| 891 |
|
|
@echo "export -format \"AFM-APS2\" -trstb_pullup \"yes\" -global_set_fuse \"reset\" -axprg_set_algo \"UMA\" {./actel/$(TOP).afm}" >> $(TOP)_designer.tcl
|
| 892 |
|
|
@echo "export -format \"prb\" {./actel/$(TOP).prb}" >> $(TOP)_designer.tcl
|
| 893 |
|
|
else
|
| 894 |
|
|
@echo "export -format \"pdb\" -feature \"prog_fpga\" -io_state \"Tri-State\" {./actel/$(TOP).pdb}" >> $(TOP)_designer.tcl
|
| 895 |
|
|
endif
|
| 896 |
|
|
@echo "export -format log -diagnostic {./actel/report_log.log}" >> $(TOP)_designer.tcl
|
| 897 |
|
|
@echo "report -type status {./actel/report_status_post.log}" >> $(TOP)_designer.tcl
|
| 898 |
|
|
@echo "save_design {"$(TOP).adb"}" >> $(TOP)_designer.tcl
|
| 899 |
|
|
|
| 900 |
|
|
actel-clean:
|
| 901 |
|
|
-rm -rf *.adb report*.log ./actel hdl constraint \
|
| 902 |
|
|
actgen constraint designer package phy_synthesis simulation \
|
| 903 |
|
|
smartgen stimulus synthesis viewdraw libero x $(TOP)_libero.prj \
|
| 904 |
|
|
libero_sim_files libero_syn_files coreconsole libero_simlist \
|
| 905 |
|
|
libero_synlist libero.do component *.pdb *.pdb.depends *.stp \
|
| 906 |
|
|
*.sdb *_layout.log *.dtf
|
| 907 |
|
|
|
| 908 |
|
|
############ Synopsys DC targets ########################
|
| 909 |
|
|
|
| 910 |
|
|
dc-launch: $(TOP)_dc.tcl
|
| 911 |
|
|
-mkdir synopsys
|
| 912 |
|
|
design_compiler&
|
| 913 |
|
|
|
| 914 |
|
|
dc: $(TOP)_dc.tcl
|
| 915 |
|
|
-mkdir synopsys
|
| 916 |
|
|
dc_shell-xg-t -f $(DCSCRIPT)
|
| 917 |
|
|
|
| 918 |
|
|
$(TOP)_dc.tcl: compile.dc
|
| 919 |
|
|
@cp $(GRLIB)/bin/top.dc $(TOP)_dc.tcl
|
| 920 |
|
|
# @for i in $(VERILOGSYNFILES); do echo "analyze -f verilog -library work" $$i >> $(TOP)_dc.tcl; done
|
| 921 |
|
|
@for i in $(VHDLSYNFILES); do echo "analyze -f VHDL -library work" $$i >> $(TOP)_dc.tcl; done
|
| 922 |
|
|
@echo elaborate $(TOP) >> $(TOP)_dc.tcl
|
| 923 |
|
|
@echo $(TOP)_dc.tcl
|
| 924 |
|
|
|
| 925 |
|
|
dc-clean:
|
| 926 |
|
|
-rm -rf synopsys view_command.log command.log dumpdata.txt filenames.log \
|
| 927 |
|
|
dc.log dwsvf* alib* $(TOP)_dc.tcl
|
| 928 |
|
|
|
| 929 |
|
|
############ Cadence RTL Compiler ########################
|
| 930 |
|
|
|
| 931 |
|
|
rc: $(TOP).rc
|
| 932 |
|
|
-mkdir rtlc
|
| 933 |
|
|
rc -files $(RCSCRIPT)
|
| 934 |
|
|
|
| 935 |
|
|
$(TOP).rc: compile.rc
|
| 936 |
|
|
@cp $(GRLIB)/bin/top.rc $(TOP).rc
|
| 937 |
|
|
@for i in $(VHDLSYNFILES); do echo "read_hdl -vhdl -lib work" $$i >> $(TOP).rc; done
|
| 938 |
|
|
# @for i in $(VERILOGSYNFILES); do echo "read_hdl " $$i >> $(TOP).rc; done
|
| 939 |
|
|
@echo elaborate $(TOP) >> $(TOP).rc
|
| 940 |
|
|
@echo $(TOP).rc
|
| 941 |
|
|
|
| 942 |
|
|
rc-clean:
|
| 943 |
|
|
-rm -rf rtlc rc.log rc.cmd
|
| 944 |
|
|
|
| 945 |
|
|
########## Generation of compile scripts ###############
|
| 946 |
|
|
|
| 947 |
|
|
scripts: compile.dc compile.synp compile.son compile.vsim compile.asim compile.xst compile.ncsim compile.rc \
|
| 948 |
|
|
$(TOP)_synplify.prj $(TOP)_dc.tcl $(TOP).rc $(TOP).xst $(TOP).npl $(TOP)_ise.tcl $(TOP).qsf \
|
| 949 |
|
|
$(TOP)_designer.tcl $(TOP)_libero.prj
|
| 950 |
|
|
|
| 951 |
|
|
verilog.txt $(TOP)_libero.prj compile.dc compile.synp compile.son compile.vsim compile.asim compile.xst compile.ncsim compile.rc compile.ghdl $(TOP).npl $(TOP)_ise.tcl $(TOP).qsf $(TOP)_precision.tcl :
|
| 952 |
|
|
@touch libs.txt; rm libs.txt;
|
| 953 |
|
|
@touch tmp.son; rm tmp.son;
|
| 954 |
|
|
@cp $(GRLIB)/bin/cds.lib cds.lib; touch hdl.var;
|
| 955 |
|
|
@for i in vsim synp xst dc ncsim ghdl rc son; do \
|
| 956 |
|
|
touch compile.$$i; rm compile.$$i ; \
|
| 957 |
|
|
done
|
| 958 |
|
|
@printf "\tmkdir xncsim\n" > compile.ncsim
|
| 959 |
|
|
@echo sh mkdir synopsys > compile.dc
|
| 960 |
|
|
@echo vlib modelsim > libs.do
|
| 961 |
|
|
@echo "" > alibs.do
|
| 962 |
|
|
@printf "\tmkdir gnu\n" > compile.ghdl
|
| 963 |
|
|
@echo set_attribute input_pragma_keyword \"cadence synopsys get2chip g2c fast ambit pragma\" > compile.rc
|
| 964 |
|
|
@echo "[Library]" > modelsim.ini;
|
| 965 |
|
|
@echo "" > tmp.mpf;
|
| 966 |
|
|
@echo "" > verilog.txt;
|
| 967 |
|
|
@echo [Device] > $(TOP).lct
|
| 968 |
|
|
@echo Family = $(ISPLIB)\; >> $(TOP).lct
|
| 969 |
|
|
@echo PartNumber = $(PART)$(SPEED)$(PACKAGE)\; >> $(TOP).lct
|
| 970 |
|
|
@echo Package = $(ISPPACKAGE)\; >> $(TOP).lct
|
| 971 |
|
|
@echo PartType = $(PART)\; >> $(TOP).lct
|
| 972 |
|
|
@echo Speed = $(SPEED)\; >> $(TOP).lct
|
| 973 |
|
|
@echo Operating_condition = COM\; >> $(TOP).lct
|
| 974 |
|
|
@echo Status = Production\; >> $(TOP).lct
|
| 975 |
|
|
@echo JDF B > $(TOP).syn
|
| 976 |
|
|
@echo PROJECT $(TOP) >> $(TOP).syn
|
| 977 |
|
|
@echo DESIGN $(TOP) Normal >> $(TOP).syn
|
| 978 |
|
|
@echo DEVKIT $(PART)$(SPEED)$(PACKAGE) >> $(TOP).syn
|
| 979 |
|
|
@echo ENTRY EDIF >> $(TOP).syn
|
| 980 |
|
|
@echo MODULE ./synplify/$(TOP).edf >> $(TOP).syn
|
| 981 |
|
|
@echo MODSTYLE $(TOP) Normal >> $(TOP).syn
|
| 982 |
|
|
@echo JDF G > $(TOP).npl
|
| 983 |
|
|
@echo PROJECT $(TOP) >> $(TOP).npl
|
| 984 |
|
|
@echo project new $(TOP).ise > $(TOP)_ise.tcl
|
| 985 |
|
|
@echo DESIGN $(TOP) >> $(TOP).npl
|
| 986 |
|
|
@echo DEVFAM $(TECHNOLOGY) >> $(TOP).npl
|
| 987 |
|
|
@echo project set family \"$(ISETECH)\" >> $(TOP)_ise.tcl
|
| 988 |
|
|
@echo DEVICE $(PART) >> $(TOP).npl
|
| 989 |
|
|
@echo project set device $(PART) >> $(TOP)_ise.tcl
|
| 990 |
|
|
@echo DEVSPEED $(SPEED) >> $(TOP).npl
|
| 991 |
|
|
@echo project set speed $(SPEED) >> $(TOP)_ise.tcl
|
| 992 |
|
|
@echo DEVPKG $(PACKAGE) >> $(TOP).npl
|
| 993 |
|
|
@echo project set package $(PACKAGE) >> $(TOP)_ise.tcl
|
| 994 |
|
|
@cp $(TOP).npl $(TOP)_synplify.npl
|
| 995 |
|
|
@echo DEVTOPLEVELMODULETYPE HDL >> $(TOP).npl
|
| 996 |
|
|
@echo DEVTOPLEVELMODULETYPE EDIF >> $(TOP)_synplify.npl
|
| 997 |
|
|
@cat $(GRLIB)/bin/def.npl >> $(TOP).npl
|
| 998 |
|
|
@cat $(GRLIB)/bin/def.npl >> $(TOP)_synplify.npl
|
| 999 |
|
|
@touch tmp.npl; rm tmp.npl
|
| 1000 |
|
|
@for i in $(VHDLSYNFILES); do \
|
| 1001 |
|
|
echo SOURCE $$i >> tmp.npl; \
|
| 1002 |
|
|
echo xfile add \"$$i\" -lib_vhdl work >> $(TOP)_ise.tcl; \
|
| 1003 |
|
|
done; \
|
| 1004 |
|
|
echo xfile add \"$(UCF)\" >> $(TOP)_ise.tcl; \
|
| 1005 |
|
|
cp $(GRLIB)/bin/quartus.qsf_head $(TOP).qsf; \
|
| 1006 |
|
|
cp $(GRLIB)/bin/quartus.qsf_head $(TOP)_synplify.qsf; \
|
| 1007 |
|
|
echo "set_global_assignment -name VQM_FILE" "synplify/$(TOP).edf" >> $(TOP)_synplify.qsf; \
|
| 1008 |
|
|
if test -r "$(QSF)"; then cat $(QSF) >> $(TOP)_synplify.qsf; fi; \
|
| 1009 |
|
|
cp $(GRLIB)/bin/quartus.qpf $(TOP).qpf; \
|
| 1010 |
|
|
cp $(TOP).qpf $(TOP)_synplify.qpf; \
|
| 1011 |
|
|
echo PROJECT_REVISION = $(TOP) >> $(TOP).qpf; \
|
| 1012 |
|
|
echo PROJECT_REVISION = $(TOP)_synplify >> $(TOP)_synplify.qpf; \
|
| 1013 |
|
|
echo KEY LIBERO \"8.1\" > $(TOP)_libero.prj; \
|
| 1014 |
|
|
echo KEY CAPTURE \"8.1.0.32\" >> $(TOP)_libero.prj; \
|
| 1015 |
|
|
echo KEY HDLTechnology \"VHDL\" >> $(TOP)_libero.prj; \
|
| 1016 |
|
|
echo KEY VendorTechnology_Family \"$(MGCTECHNOLOGY)\" >> $(TOP)_libero.prj; \
|
| 1017 |
|
|
echo KEY VendorTechnology_Die \"$(LIBERO_DIE)\" >> $(TOP)_libero.prj; \
|
| 1018 |
|
|
echo KEY VendorTechnology_Package \"$(LIBERO_PACKAGE)\" >> $(TOP)_libero.prj; \
|
| 1019 |
|
|
echo KEY ProjectLocation \"\.\" >> $(TOP)_libero.prj; \
|
| 1020 |
|
|
echo KEY SimulationType \"VHDL\" >> $(TOP)_libero.prj; \
|
| 1021 |
|
|
echo KEY Vendor \"Actel\" >> $(TOP)_libero.prj; \
|
| 1022 |
|
|
echo KEY ActiveRoot \"$(TOP)\" >> $(TOP)_libero.prj; \
|
| 1023 |
|
|
echo LIST REVISIONS >> $(TOP)_libero.prj; \
|
| 1024 |
|
|
echo VALUE=\"Impl1\",NUM=1 >> $(TOP)_libero.prj; \
|
| 1025 |
|
|
echo CURREV=1 >> $(TOP)_libero.prj; \
|
| 1026 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1027 |
|
|
echo LIST FileManager > libero_syn_files ; \
|
| 1028 |
|
|
echo LIST ExcludePackageForSynthesis > libero_sim_files; \
|
| 1029 |
|
|
echo LIST $(TOP) >> libero_sim_files; \
|
| 1030 |
|
|
echo LIST \"ideSYNTHESIS\" > libero_synlist; \
|
| 1031 |
|
|
echo USE_LIST=TRUE >> libero_synlist; \
|
| 1032 |
|
|
echo FILELIST >> libero_synlist; \
|
| 1033 |
|
|
echo LIST \"ideSIMULATION\" > libero_simlist; \
|
| 1034 |
|
|
echo USE_LIST=TRUE >> libero_simlist; \
|
| 1035 |
|
|
echo FILELIST >> libero_simlist; \
|
| 1036 |
|
|
ppath="gnu"; nfiles=0; xfiles=8;\
|
| 1037 |
|
|
cat $(GRLIB)/bin/sonata1.sws > sonata.sws; \
|
| 1038 |
|
|
echo "open_project ./$(TOP).psp"> $(TOP)_precrun.tcl; \
|
| 1039 |
|
|
echo compile >> $(TOP)_precrun.tcl; echo synthesize >> $(TOP)_precrun.tcl; \
|
| 1040 |
|
|
echo save_impl >> $(TOP)_precrun.tcl; \
|
| 1041 |
|
|
echo "new_project -name $(TOP) -folder . -createimpl_name precision"> $(TOP)_precision.tcl; \
|
| 1042 |
|
|
echo "setup_design -manufacturer $(MANUFACTURER) -family $(MGCTECHNOLOGY) -part $(MGCPART) -package $(MGCPACKAGE) -speed $(SPEED)" >> $(TOP)_precision.tcl; \
|
| 1043 |
|
|
echo "set_input_dir ." >> $(TOP)_precision.tcl ;\
|
| 1044 |
|
|
echo "Scanning libraries" ; \
|
| 1045 |
|
|
if (test -r $(EXTRALIBS)/libs.txt); then extralib=$(EXTRALIBS)/libs.txt; else \
|
| 1046 |
|
|
extralib=$(GRLIB)/bin/libs.txt; fi; \
|
| 1047 |
|
|
for j in grlib $(XTECHLIBS) `cat $(GRLIB)/lib/libs.txt $(GRLIB)/lib/*/libs.txt $$extralib` $(LIBADD) work ; do \
|
| 1048 |
|
|
bn=`basename $$j` ; \
|
| 1049 |
|
|
ppath="$$ppath -Pgnu/$$bn"; \
|
| 1050 |
|
|
k=$(GRLIB)/lib/$$j; \
|
| 1051 |
|
|
if test -r $$k; then xxx=0; else k=$(EXTRALIBS)/$$j; fi;\
|
| 1052 |
|
|
if (test $$bn = "techmap"); then tdirs="$(TECHLIBS) maps"; \
|
| 1053 |
|
|
else tdirs=""; fi; \
|
| 1054 |
|
|
case $$bn in $(XLIBSKIP) )\
|
| 1055 |
|
|
;; \
|
| 1056 |
|
|
*) \
|
| 1057 |
|
|
if (test -r $$k/dirs.txt); then \
|
| 1058 |
|
|
echo DEFINE $$bn xncsim/$$bn "" >> cds.lib; \
|
| 1059 |
|
|
printf "\tmkdir gnu/$$bn\n" >> compile.ghdl; \
|
| 1060 |
|
|
echo -n $$bn "" >> libs.txt; echo $$bn = modelsim/$$bn >> modelsim.ini; \
|
| 1061 |
|
|
echo vlib modelsim/$$bn "" >> libs.do; \
|
| 1062 |
|
|
echo alib $$bn $$bn.lib "" >> alibs.do; \
|
| 1063 |
|
|
printf "\tmkdir xncsim/$$bn\n" >> compile.ncsim; \
|
| 1064 |
|
|
if (test $$bn != "dw02"); then \
|
| 1065 |
|
|
echo sh mkdir synopsys/$$bn "" >> compile.dc; \
|
| 1066 |
|
|
echo define_design_lib $$bn -path synopsys/$$bn "" >> compile.dc; \
|
| 1067 |
|
|
fi ; \
|
| 1068 |
|
|
case $$bn in \
|
| 1069 |
|
|
work) \
|
| 1070 |
|
|
echo " "sonata "=" sonata/sonata.sym >> sonata.sws; \
|
| 1071 |
|
|
set bn = "sonata"; \
|
| 1072 |
|
|
echo "[library]" >> tmp.son; \
|
| 1073 |
|
|
echo name = sonata >> tmp.son; \
|
| 1074 |
|
|
echo toplevel = $(SIMTOP) >> tmp.son; \
|
| 1075 |
|
|
echo " [options]" >> tmp.son; \
|
| 1076 |
|
|
echo " [booloption]" >> tmp.son; \
|
| 1077 |
|
|
echo " name = -autoorder" >> tmp.son; \
|
| 1078 |
|
|
echo " value = 0" >> tmp.son; \
|
| 1079 |
|
|
echo " invert = 0" >> tmp.son; \
|
| 1080 |
|
|
echo " []" >> tmp.son; \
|
| 1081 |
|
|
echo " []" >> tmp.son;; \
|
| 1082 |
|
|
*) \
|
| 1083 |
|
|
echo " "$$bn "=" sonata/$$bn.sym >> sonata.sws; \
|
| 1084 |
|
|
echo "[library]" >> tmp.son; \
|
| 1085 |
|
|
echo name = $$bn >> tmp.son; \
|
| 1086 |
|
|
echo " [options]" >> tmp.son; \
|
| 1087 |
|
|
echo " [booloption]" >> tmp.son; \
|
| 1088 |
|
|
echo " name = -autoorder" >> tmp.son; \
|
| 1089 |
|
|
echo " value = 0" >> tmp.son; \
|
| 1090 |
|
|
echo " invert = 0" >> tmp.son; \
|
| 1091 |
|
|
echo " []" >> tmp.son; \
|
| 1092 |
|
|
echo " []" >> tmp.son;; \
|
| 1093 |
|
|
esac; \
|
| 1094 |
|
|
case $$bn in $(XSTLIBSKIP) )\
|
| 1095 |
|
|
uu=0;; \
|
| 1096 |
|
|
*) \
|
| 1097 |
|
|
echo SUBLIB $$bn VhdlLibrary vhdl >> tmp.npl; \
|
| 1098 |
|
|
echo lib_vhdl new $$bn >> $(TOP)_ise.tcl;; \
|
| 1099 |
|
|
esac; \
|
| 1100 |
|
|
echo -n " "$$bn":"; \
|
| 1101 |
|
|
for l in `cat $$k/dirs.txt` $$tdirs ; do \
|
| 1102 |
|
|
case $$l in $(XDIRSKIP) )\
|
| 1103 |
|
|
;; \
|
| 1104 |
|
|
*) \
|
| 1105 |
|
|
if test -r $$k/$$l; then \
|
| 1106 |
|
|
echo -n " "$$l; \
|
| 1107 |
|
|
fi; \
|
| 1108 |
|
|
for i in vlogsyn vhdlsyn vlogsim vhdlsim ; do \
|
| 1109 |
|
|
m=$$k/$$l/$$i; \
|
| 1110 |
|
|
if test -r $$m.txt; then \
|
| 1111 |
|
|
for q in `cat $$m.txt`; do \
|
| 1112 |
|
|
case $$q in $(XFILESKIP) )\
|
| 1113 |
|
|
;; \
|
| 1114 |
|
|
*) \
|
| 1115 |
|
|
if test -r $$k/$$l/$$q; then \
|
| 1116 |
|
|
case $$i in \
|
| 1117 |
|
|
vhdlsyn) \
|
| 1118 |
|
|
echo Project_File_$$nfiles = $$k/$$l/$$q >> tmp.mpf; \
|
| 1119 |
|
|
echo Project_File_P_$$nfiles = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to $$bn compile_order $$nfiles dont_compile 0 cover_stmt 1 vhdl_use93 93 >> tmp.mpf; \
|
| 1120 |
|
|
nfiles=`expr $$nfiles + 1`; \
|
| 1121 |
|
|
printf "\t$(VCOM) $(VHDLOPT) $$bn $$k/$$l/$$q\n" >> compile.vsim; \
|
| 1122 |
|
|
printf "\t$(ACOM) $(VHDLOPT) $$bn ../../$$k/$$l/$$q\n" >> compile.asim; \
|
| 1123 |
|
|
printf "\t$(NCVHDL) $(VHDLOPT) $$bn $$k/$$l/$$q\n" >> compile.ncsim; \
|
| 1124 |
|
|
printf "\t$(GHDL) $(VHDLOPT) --workdir=gnu/$$bn --work=$$bn -P$$ppath $$k/$$l/$$q\n" >> compile.ghdl; \
|
| 1125 |
|
|
case $$bn in $(XDCLIBSKIP) ) ;; *) \
|
| 1126 |
|
|
case $$l in $(XDCDIRSKIP) ) ;; *) \
|
| 1127 |
|
|
case $$q in $(DCSKIP) ) ;; *) \
|
| 1128 |
|
|
echo $(DCVHDL) $(VHDLOPT) $$bn $$k/$$l/$$q >> compile.dc; \
|
| 1129 |
|
|
echo $(RTLCVHDL) $(VHDLOPT) $$bn $$k/$$l/$$q >> compile.rc; \
|
| 1130 |
|
|
esac; \
|
| 1131 |
|
|
esac; \
|
| 1132 |
|
|
esac; \
|
| 1133 |
|
|
case $$bn in $(XSYNPLIBSKIP) )\
|
| 1134 |
|
|
uu=0;; \
|
| 1135 |
|
|
*) \
|
| 1136 |
|
|
case $$l in $(XSYNPDIRSKIP) ) ;; *) \
|
| 1137 |
|
|
case $$q in $(SYNPSKIP) ) ;; *) \
|
| 1138 |
|
|
echo $(SYNPVHDL) $(VHDLOPT) $$bn $$k/$$l/$$q >> compile.synp;; \
|
| 1139 |
|
|
esac; \
|
| 1140 |
|
|
esac; \
|
| 1141 |
|
|
esac; \
|
| 1142 |
|
|
if (test $$bn = "work"); then \
|
| 1143 |
|
|
printf "\t$(VHDLP) $(VHDLOPT) sonata $$k/$$l/$$q\n" >> compile.son; \
|
| 1144 |
|
|
else \
|
| 1145 |
|
|
printf "\t$(VHDLP) $(VHDLOPT) $$bn $$k/$$l/$$q\n" >> compile.son; \
|
| 1146 |
|
|
fi; \
|
| 1147 |
|
|
echo " [file]" >> tmp.son; \
|
| 1148 |
|
|
echo " name" = $$k/$$l/$$q >> tmp.son; \
|
| 1149 |
|
|
echo " []" >> tmp.son; \
|
| 1150 |
|
|
case $$bn in $(LIBEROLIBSKIP) )\
|
| 1151 |
|
|
uu=0;; \
|
| 1152 |
|
|
*) \
|
| 1153 |
|
|
case $$l in $(LIBERODIRSKIP) ) ;; *) \
|
| 1154 |
|
|
case $$q in $(LIBEROSKIP) ) ;; *) \
|
| 1155 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_syn_files; \
|
| 1156 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_synlist; \
|
| 1157 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_simlist; \
|
| 1158 |
|
|
echo STATE=\"utd\" >> libero_syn_files; \
|
| 1159 |
|
|
echo LIBRARY=\"$$bn\" >> libero_syn_files; \
|
| 1160 |
|
|
echo ENDFILE >> libero_syn_files;; \
|
| 1161 |
|
|
esac; \
|
| 1162 |
|
|
esac; \
|
| 1163 |
|
|
esac; \
|
| 1164 |
|
|
case $$bn in $(XSTLIBSKIP) )\
|
| 1165 |
|
|
uu=0;; \
|
| 1166 |
|
|
*) \
|
| 1167 |
|
|
case $$l in $(XSTDIRSKIP) )\
|
| 1168 |
|
|
uu=0;; \
|
| 1169 |
|
|
*) \
|
| 1170 |
|
|
case $$q in $(XSTSKIP) ) ;; *) \
|
| 1171 |
|
|
echo LIBFILE $$k/$$l/$$q $$bn vhdl >> tmp.npl; \
|
| 1172 |
|
|
echo xfile add \"$$k/$$l/$$q\" -lib_vhdl $$bn >> $(TOP)_ise.tcl; \
|
| 1173 |
|
|
echo $(XSTVHDL) $(VHDLOPT) $$bn -ifn $$k/$$l/$$q >> compile.xst; \
|
| 1174 |
|
|
xfiles=`expr $$xfiles + 1`;; \
|
| 1175 |
|
|
esac; \
|
| 1176 |
|
|
esac; \
|
| 1177 |
|
|
esac; \
|
| 1178 |
|
|
case $$bn in $(QUARTUSLIBSKIP) )\
|
| 1179 |
|
|
uu=0;; \
|
| 1180 |
|
|
*) \
|
| 1181 |
|
|
case $$l in $(QDIRSKIP) )\
|
| 1182 |
|
|
uu=0;; \
|
| 1183 |
|
|
*) \
|
| 1184 |
|
|
case $$q in $(QUARTUSSKIP) ) ;; *) \
|
| 1185 |
|
|
echo set_global_assignment -name VHDL_FILE $$k/$$l/$$q -library $$bn >> $(TOP).qsf;; \
|
| 1186 |
|
|
esac; \
|
| 1187 |
|
|
esac; \
|
| 1188 |
|
|
esac; \
|
| 1189 |
|
|
case $$bn in $(PRECLIBSKIP) )\
|
| 1190 |
|
|
uu=0;; \
|
| 1191 |
|
|
*) \
|
| 1192 |
|
|
case $$bn in $(PRECDIRSKIP) )\
|
| 1193 |
|
|
uu=0;; \
|
| 1194 |
|
|
*) \
|
| 1195 |
|
|
case $$q in $(PRECSKIP) ) ;; *) \
|
| 1196 |
|
|
echo add_input_file -format VHDL -work $$bn $$k/$$l/$$q >> $(TOP)_precision.tcl;; \
|
| 1197 |
|
|
esac; \
|
| 1198 |
|
|
esac; \
|
| 1199 |
|
|
esac;; \
|
| 1200 |
|
|
vlogsyn) \
|
| 1201 |
|
|
echo Project_File_$$nfiles = $$k/$$l/$$q >> tmp.mpf; \
|
| 1202 |
|
|
echo Project_File_P_$$nfiles = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 compile_to $$bn vlog_upper 0 vlog_options {} compile_order $$nfiles dont_compile 0 >> tmp.mpf; \
|
| 1203 |
|
|
nfiles=`expr $$nfiles + 1`; \
|
| 1204 |
|
|
printf "\t$(VLOG) $$bn +incdir+$$k/$$l $$k/$$l/$$q\n" >> compile.vsim; \
|
| 1205 |
|
|
printf "\t$(ALOG) $$bn ../../$$k/$$l/$$q\n" >> compile.asim; \
|
| 1206 |
|
|
printf "\t$(NCVLOG) $$bn -INCDIR $$k/$$l $$k/$$l/$$q\n" >> compile.ncsim; \
|
| 1207 |
|
|
echo $(XSTVLOG) $$bn -ifn $$k/$$l/$$q >> compile.xst; \
|
| 1208 |
|
|
case $$bn in $(LIBEROLIBSKIP) )\
|
| 1209 |
|
|
uu=0;; \
|
| 1210 |
|
|
*) \
|
| 1211 |
|
|
case $$q in $(LIBEROSKIP) ) ;; *) \
|
| 1212 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_syn_files; \
|
| 1213 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_synlist; \
|
| 1214 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_simlist; \
|
| 1215 |
|
|
echo STATE=\"utd\" >> libero_syn_files; \
|
| 1216 |
|
|
echo LIBRARY=\"$$bn\" >> libero_syn_files; \
|
| 1217 |
|
|
echo ENDFILE >> libero_syn_files;; \
|
| 1218 |
|
|
esac; \
|
| 1219 |
|
|
esac; \
|
| 1220 |
|
|
echo $$k/$$l/$$q >> verilog.txt; \
|
| 1221 |
|
|
echo $(DCVLOG) $$bn $$k/$$l/$$q >> compile.dc; \
|
| 1222 |
|
|
echo $(RTLCVLOG) $$k/$$l/$$q >> compile.rc; \
|
| 1223 |
|
|
echo LIBFILE $$k/$$l/$$q $$bn verilog >> tmp.npl; \
|
| 1224 |
|
|
echo $(SYNPVLOG) $$k/$$l/$$q >> compile.synp; \
|
| 1225 |
|
|
echo add_input_file -format VERILOG -work $$bn $$k/$$l/$$q >> $(TOP)_precision.tcl; \
|
| 1226 |
|
|
echo set_global_assignment -name VERILOG_FILE $$k/$$l/$$q -library $$bn >> $(TOP).qsf;; \
|
| 1227 |
|
|
vhdlsim) \
|
| 1228 |
|
|
echo " [file]" >> tmp.son; \
|
| 1229 |
|
|
echo " name" = $$k/$$l/$$q >> tmp.son; \
|
| 1230 |
|
|
echo " []" >> tmp.son; \
|
| 1231 |
|
|
case $$bn in $(LIBEROLIBSKIP) )\
|
| 1232 |
|
|
uu=0;; \
|
| 1233 |
|
|
*) \
|
| 1234 |
|
|
case $$q in $(LIBEROSKIP) ) ;; *) \
|
| 1235 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_sim_files; \
|
| 1236 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_syn_files; \
|
| 1237 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_simlist; \
|
| 1238 |
|
|
echo STATE=\"utd\" >> libero_syn_files; \
|
| 1239 |
|
|
echo LIBRARY=\"$$bn\" >> libero_syn_files; \
|
| 1240 |
|
|
echo ENDFILE >> libero_syn_files;; \
|
| 1241 |
|
|
esac; \
|
| 1242 |
|
|
esac; \
|
| 1243 |
|
|
echo Project_File_$$nfiles = $$k/$$l/$$q >> tmp.mpf; \
|
| 1244 |
|
|
echo Project_File_P_$$nfiles = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to $$bn compile_order $$nfiles dont_compile 0 cover_stmt 1 vhdl_use93 93 >> tmp.mpf; \
|
| 1245 |
|
|
nfiles=`expr $$nfiles + 1`; \
|
| 1246 |
|
|
printf "\t$(VCOM) $(VHDLOPT) $$bn $$k/$$l/$$q\n" >> compile.vsim; \
|
| 1247 |
|
|
if (test $$bn = "work"); then \
|
| 1248 |
|
|
printf "\t$(VHDLP) $(VHDLOPT) sonata $$k/$$l/$$q\n" >> compile.son; \
|
| 1249 |
|
|
else \
|
| 1250 |
|
|
printf "\t$(VHDLP) $(VHDLOPT) $$bn $$k/$$l/$$q\n" >> compile.son; \
|
| 1251 |
|
|
fi; \
|
| 1252 |
|
|
printf "\t$(ACOM) $(VHDLOPT) $$bn ../../$$k/$$l/$$q\n" >> compile.asim; \
|
| 1253 |
|
|
printf "\t$(NCVHDL) $(VHDLOPT) $$bn $$k/$$l/$$q\n" >> compile.ncsim; \
|
| 1254 |
|
|
printf "\t$(GHDL) $(VHDLOPT) --workdir=gnu/$$bn --work=$$bn -P$$ppath $$k/$$l/$$q\n" >> compile.ghdl;; \
|
| 1255 |
|
|
vlogsim) \
|
| 1256 |
|
|
echo Project_File_$$nfiles = $$k/$$l/$$q >> tmp.mpf; \
|
| 1257 |
|
|
echo Project_File_P_$$nfiles = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 compile_to $$bn vlog_upper 0 vlog_options {} compile_order $$nfiles dont_compile 0 >> tmp.mpf; \
|
| 1258 |
|
|
nfiles=`expr $$nfiles + 1`; \
|
| 1259 |
|
|
case $$bn in $(LIBEROLIBSKIP) )\
|
| 1260 |
|
|
uu=0;; \
|
| 1261 |
|
|
*) \
|
| 1262 |
|
|
case $$q in $(LIBEROSKIP) ) ;; *) \
|
| 1263 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_syn_files; \
|
| 1264 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_sim_files; \
|
| 1265 |
|
|
echo VALUE \"\/$$k/$$l/$$q,hdl\" >> libero_simlist; \
|
| 1266 |
|
|
echo STATE=\"utd\" >> libero_syn_files; \
|
| 1267 |
|
|
echo LIBRARY=\"$$bn\" >> libero_syn_files; \
|
| 1268 |
|
|
echo ENDFILE >> libero_syn_files;; \
|
| 1269 |
|
|
esac; \
|
| 1270 |
|
|
esac; \
|
| 1271 |
|
|
printf "\t$(VLOG) $$bn $$k/$$l/$$q\n" >> compile.vsim; \
|
| 1272 |
|
|
printf "\t$(ALOG) $$bn ../../$$k/$$l/$$q\n" >> compile.asim; \
|
| 1273 |
|
|
printf "\t$(NCVLOG) $$bn $$k/$$l/$$q\n" >> compile.ncsim;; \
|
| 1274 |
|
|
esac ; \
|
| 1275 |
|
|
fi ;; \
|
| 1276 |
|
|
esac; \
|
| 1277 |
|
|
done ; \
|
| 1278 |
|
|
fi ; \
|
| 1279 |
|
|
done;; \
|
| 1280 |
|
|
esac; \
|
| 1281 |
|
|
done ; \
|
| 1282 |
|
|
if (test $$bn = "work"); then \
|
| 1283 |
|
|
for i in $(VHDLSYNFILES) $(VHDLSIMFILES); do \
|
| 1284 |
|
|
echo " [file]" >> tmp.son; \
|
| 1285 |
|
|
echo " name" = $$i >> tmp.son; \
|
| 1286 |
|
|
echo " []" >> tmp.son; \
|
| 1287 |
|
|
done; \
|
| 1288 |
|
|
fi ; \
|
| 1289 |
|
|
echo "[]" >> tmp.son; \
|
| 1290 |
|
|
echo ""; \
|
| 1291 |
|
|
fi ; \
|
| 1292 |
|
|
esac; \
|
| 1293 |
|
|
done ; \
|
| 1294 |
|
|
for i in $(VHDLSYNFILES); do \
|
| 1295 |
|
|
echo add_input_file -format VHDL -work work $$i >> $(TOP)_precision.tcl; \
|
| 1296 |
|
|
echo set_global_assignment -name VHDL_FILE $$i >> $(TOP).qsf; \
|
| 1297 |
|
|
echo VALUE \"\/$$i,hdl\" >> libero_synlist; \
|
| 1298 |
|
|
done; \
|
| 1299 |
|
|
echo setup_design -design $(TOP) >> $(TOP)_precision.tcl; \
|
| 1300 |
|
|
echo setup_design -retiming >> $(TOP)_precision.tcl; \
|
| 1301 |
|
|
echo setup_design -vhdl >> $(TOP)_precision.tcl; \
|
| 1302 |
|
|
echo setup_design -transformations=false >> $(TOP)_precision.tcl; \
|
| 1303 |
|
|
echo setup_design -frequency=\"$(SYNFREQ)\" >> $(TOP)_precision.tcl; \
|
| 1304 |
|
|
echo $(PRECOPT) >> $(TOP)_precision.tcl; \
|
| 1305 |
|
|
echo save_impl >> $(TOP)_precision.tcl; \
|
| 1306 |
|
|
echo "" >> $(TOP).qsf; \
|
| 1307 |
|
|
echo "set_global_assignment -name TOP_LEVEL_ENTITY" \"$(TOP)\" >> $(TOP).qsf; \
|
| 1308 |
|
|
echo "" >> $(TOP)_synplify.qsf; \
|
| 1309 |
|
|
echo "set_global_assignment -name TOP_LEVEL_ENTITY" \"$(TOP)\" >> $(TOP)_synplify.qsf; \
|
| 1310 |
|
|
cat tmp.npl >> $(TOP).npl; \
|
| 1311 |
|
|
echo DEPASSOC $(TOP) $(UCF) >> $(TOP).npl; \
|
| 1312 |
|
|
echo project set \"Bus Delimiter\" \(\) >> $(TOP)_ise.tcl ;\
|
| 1313 |
|
|
echo project set \"FSM Encoding Algorithm\" None >> $(TOP)_ise.tcl ;\
|
| 1314 |
|
|
echo project set \"Pack I/O Registers into IOBs\" yes >> $(TOP)_ise.tcl ;\
|
| 1315 |
|
|
echo project set \"Other XST Command Line Options\" \"$(XSTOPT)\" >> $(TOP)_ise.tcl ;\
|
| 1316 |
|
|
echo project set \"Allow Unmatched LOC Constraints\" true >> $(TOP)_ise.tcl ;\
|
| 1317 |
|
|
echo project set \"Macro Search Path\" \"$(GRLIB)/netlists/xilinx/$(TECHNOLOGY)\" -process \"Translate\" >> $(TOP)_ise.tcl ;\
|
| 1318 |
|
|
echo project set \"Pack I/O Registers/Latches into IOBs\" \{For Inputs and Outputs\} >> $(TOP)_ise.tcl ;\
|
| 1319 |
|
|
echo project set \"Other MAP Command Line Options\" \"$(ISEMAPOPT)\" >> $(TOP)_ise.tcl ;\
|
| 1320 |
|
|
echo project set \"Create ReadBack Data Files\" true >> $(TOP)_ise.tcl ;\
|
| 1321 |
|
|
echo project set \"Create Mask File\" true >> $(TOP)_ise.tcl ;\
|
| 1322 |
|
|
echo project close >> $(TOP)_ise.tcl ;\
|
| 1323 |
|
|
echo exit >> $(TOP)_ise.tcl ;\
|
| 1324 |
|
|
xfiles=`expr $$xfiles + 1`; \
|
| 1325 |
|
|
echo SOURCE synplify/$(TOP).edf >> $(TOP)_synplify.npl; \
|
| 1326 |
|
|
echo DEPASSOC $(TOP) $(UCF) >> $(TOP)_synplify.npl; \
|
| 1327 |
|
|
echo "[Normal]" >> $(TOP).npl; echo "[Normal]" >> $(TOP)_synplify.npl; \
|
| 1328 |
|
|
echo "_SynthFsmEncode=xstvhd, " $(TECHNOLOGY)", VHDL.t_synthesize, 1102507235, None" >> $(TOP).npl; \
|
| 1329 |
|
|
echo "p_xstBusDelimiter=xstvhd, " $(TECHNOLOGY)", VHDL.t_synthesize, 1102507235, ()" >> $(TOP).npl; \
|
| 1330 |
|
|
echo "xilxMapAllowLogicOpt=xstvhd, " $(TECHNOLOGY)", VHDL.t_placeAndRouteDes, 1102861051, True" >> $(TOP).npl; \
|
| 1331 |
|
|
echo "xilxMapCoverMode=xstvhd, " $(TECHNOLOGY)", VHDL.t_placeAndRouteDes, 1102861051, Speed" >> $(TOP).npl; \
|
| 1332 |
|
|
echo "xilxMapTimingDrivenPacking=xstvhd, " $(TECHNOLOGY)", VHDL.t_placeAndRouteDes, 1102861051, True" >> $(TOP).npl; \
|
| 1333 |
|
|
echo "xilxNgdbld_AUL=xstvhd, " $(TECHNOLOGY)", VHDL.t_placeAndRouteDes, 1102861051, True" >> $(TOP).npl; \
|
| 1334 |
|
|
echo "xilxNgdbldMacro=xstvhd, " $(TECHNOLOGY)", VHDL.t_ngdbuild, 1105377047, "$(GRLIB)/netlists/xilinx/$(TECHNOLOGY) >> $(TOP).npl; \
|
| 1335 |
|
|
echo "xilxPAReffortLevel=xstvhd, " $(TECHNOLOGY)", VHDL.t_placeAndRouteDes, 1102861051, Medium" >> $(TOP).npl; \
|
| 1336 |
|
|
echo "xilxMapAllowLogicOpt=edif, " $(TECHNOLOGY)", EDIF.t_placeAndRouteDes, 1102861051, True" >> $(TOP)_synplify.npl; \
|
| 1337 |
|
|
echo "xilxMapCoverMode=edif, " $(TECHNOLOGY)", EDIF.t_placeAndRouteDes, 1102861051, Speed" >> $(TOP)_synplify.npl; \
|
| 1338 |
|
|
echo "xilxNgdbld_AUL=edif, " $(TECHNOLOGY)", EDIF.t_placeAndRouteDes, 1102861051, True" >> $(TOP)_synplify.npl; \
|
| 1339 |
|
|
echo "xilxPAReffortLevel=edif, " $(TECHNOLOGY)", EDIF.t_placeAndRouteDes, 1102861051, Medium" >> $(TOP)_synplify.npl; \
|
| 1340 |
|
|
echo "xilxNgdbldMacro=edif, " $(TECHNOLOGY)", EDIF.t_placeAndRouteDes, 1105378344, "$(GRLIB)/netlists/xilinx/$(TECHNOLOGY) >> $(TOP)_synplify.npl; \
|
| 1341 |
|
|
cat $(TOP).npl | sed -e s/'\/'/'\\'/g > tmp.npl; \
|
| 1342 |
|
|
cp tmp.npl $(TOP)_win32.npl; \
|
| 1343 |
|
|
cat $(TOP)_synplify.npl | sed -e s/'\/'/'\\'/g > tmp.npl; \
|
| 1344 |
|
|
cp tmp.npl $(TOP)_synplify_win32.npl; \
|
| 1345 |
|
|
if test $(OS) != "Linux"; then \
|
| 1346 |
|
|
if test $(OS) != "SunOs"; then \
|
| 1347 |
|
|
cp $(TOP)_win32.npl $(TOP).npl; \
|
| 1348 |
|
|
cp $(TOP)_synplify_win32.npl $(TOP)_synplify.npl; \
|
| 1349 |
|
|
fi; \
|
| 1350 |
|
|
fi; \
|
| 1351 |
|
|
echo "[STRATEGY-LIST]" >> $(TOP).npl; echo "[STRATEGY-LIST]" >> $(TOP)_synplify.npl; \
|
| 1352 |
|
|
echo "Normal=True" >> $(TOP).npl; echo "Normal=True" >> $(TOP)_synplify.npl; \
|
| 1353 |
|
|
echo "DEVSYNTHESISTOOL XST (VHDL/Verilog)" >> $(TOP).npl; \
|
| 1354 |
|
|
for i in $(VHDLSYNFILES) $(VHDLSIMFILES); do \
|
| 1355 |
|
|
echo Project_File_$$nfiles = $$i >> tmp.mpf; \
|
| 1356 |
|
|
echo Project_File_P_$$nfiles = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to $$bn compile_order $$nfiles dont_compile 0 cover_stmt 1 vhdl_use93 93 >> tmp.mpf; \
|
| 1357 |
|
|
nfiles=`expr $$nfiles + 1`; \
|
| 1358 |
|
|
printf "\t$(VHDLP) $(VHDLOPT) sonata $$i\n" >> compile.son; \
|
| 1359 |
|
|
done; rm tmp.npl; \
|
| 1360 |
|
|
echo "Project_Sim_Count = 1" >> tmp.mpf; \
|
| 1361 |
|
|
echo "Project_Sim_0 = Simulation 1" >> tmp.mpf; \
|
| 1362 |
|
|
echo "Project_Sim_P_0 = Generics {} timing default -std_output {} +notimingchecks 0 -L {} selected_du {} -hazards 0 -sdf {} +acc {} ok 1 folder {Top Level} -absentisempty 0 +pulse_r {} OtherArgs {} -multisource_delay {} +pulse_e {} -coverage 0 -sdfnoerror 0 +plusarg {} -vital2.2b 0 -t ps additional_dus" work.$(SIMTOP) "-nofileshare 0 -noglitch 0 -wlf {} +no_pulse_msg 0 -assertfile {} -sdfnowarn 0 -Lf {} -std_input {}" >> tmp.mpf; \
|
| 1363 |
|
|
for i in $(GHDLSKIP); do grep -v $$i compile.ghdl > xx; mv xx compile.ghdl; done;\
|
| 1364 |
|
|
for i in $(SONATALIBSKIP); do grep -v $$i compile.son > xx; mv xx compile.son; done;\
|
| 1365 |
|
|
cat $(GRLIB)/bin/modelsim.ini >> modelsim.ini; \
|
| 1366 |
|
|
cp modelsim.ini $(SIMTOP).mpf; \
|
| 1367 |
|
|
echo "[Project]" >> $(SIMTOP).mpf; \
|
| 1368 |
|
|
echo Project_Version = 5 >> $(SIMTOP).mpf; \
|
| 1369 |
|
|
echo Project_DefaultLib = work >> $(SIMTOP).mpf; \
|
| 1370 |
|
|
echo Project_SortMethod = unused >> $(SIMTOP).mpf; \
|
| 1371 |
|
|
echo Project_Files_Count = $$nfiles >> $(SIMTOP).mpf; \
|
| 1372 |
|
|
cat tmp.mpf >> $(SIMTOP).mpf; rm tmp.mpf; \
|
| 1373 |
|
|
cat $(GRLIB)/bin/mt1.mpf >> $(SIMTOP).mpf; \
|
| 1374 |
|
|
echo -P$$ppath > ghdl.path; \
|
| 1375 |
|
|
if test -r "$(QSF)"; then cat $(QSF) >> $(TOP).qsf; fi; \
|
| 1376 |
|
|
echo ghdl: > tmpmake.ghdl; cat compile.ghdl >> tmpmake.ghdl; \
|
| 1377 |
|
|
echo ncsim: > make.ncsim; cat compile.ncsim >> make.ncsim; \
|
| 1378 |
|
|
echo vsim: > make.vsim; cat compile.vsim >> make.vsim; \
|
| 1379 |
|
|
echo sonata-compile: > make.son; cat compile.son >> make.son; \
|
| 1380 |
|
|
cat compile.asim >> make.asim; \
|
| 1381 |
|
|
for i in $(VHDLSYNFILES) $(VHDLSIMFILES); do \
|
| 1382 |
|
|
printf "\t$(VCOM) $(VHDLOPT) $$bn $$i\n" >> make.vsim; \
|
| 1383 |
|
|
printf "\t$(ACOM) $(VHDLOPT) $$bn ../../$$i\n" >> make.asim; \
|
| 1384 |
|
|
printf "\t$(NCVHDL) $(VHDLOPT) $$bn $$i\n" >> make.ncsim; \
|
| 1385 |
|
|
printf "\t$(GHDL) $(VHDLOPT) --workdir=gnu/$$bn --work=$$bn -P$$ppath $$i\n" >> tmpmake.ghdl; \
|
| 1386 |
|
|
echo VALUE \"\/$$i,hdl\" >> libero_sim_files; \
|
| 1387 |
|
|
echo VALUE \"\/$$i,hdl\" >> libero_simlist; \
|
| 1388 |
|
|
echo VALUE \"\/$$i,hdl\" >> libero_syn_files; \
|
| 1389 |
|
|
echo STATE=\"utd\" >> libero_syn_files; \
|
| 1390 |
|
|
echo LIBRARY=\"work\" >> libero_syn_files; \
|
| 1391 |
|
|
echo ENDFILE >> libero_syn_files; \
|
| 1392 |
|
|
done; \
|
| 1393 |
|
|
if test -r "$(SDC)"; then \
|
| 1394 |
|
|
echo VALUE \"\/$(SDC),sdc\" >> libero_syn_files; \
|
| 1395 |
|
|
echo STATE=\"utd\" >> libero_syn_files; \
|
| 1396 |
|
|
echo ENDFILE >> libero_syn_files; \
|
| 1397 |
|
|
fi; \
|
| 1398 |
|
|
if test -r "$(PDC)"; then \
|
| 1399 |
|
|
echo VALUE \"\/$(PDC),pdc\" >> libero_syn_files; \
|
| 1400 |
|
|
echo STATE=\"utd\" >> libero_syn_files; \
|
| 1401 |
|
|
echo ENDFILE >> libero_syn_files; \
|
| 1402 |
|
|
fi; \
|
| 1403 |
|
|
echo "cd .." > libero.do; \
|
| 1404 |
|
|
echo do libs.do >> libero.do; \
|
| 1405 |
|
|
echo project open $(SIMTOP).mpf >> libero.do; \
|
| 1406 |
|
|
echo project compileoutofdate >> libero.do; \
|
| 1407 |
|
|
echo vsim $(SIMTOP) >> libero.do; \
|
| 1408 |
|
|
echo do wave.do >> libero.do; \
|
| 1409 |
|
|
mkdir simulation; mv libero.do simulation; \
|
| 1410 |
|
|
echo "" > make.asim-addfile; \
|
| 1411 |
|
|
for i in $(VHDLSYNFILES) $(VHDLSIMFILES); do \
|
| 1412 |
|
|
echo addfile -vhdl ../../$$i >> make.asim-addfile; \
|
| 1413 |
|
|
done; \
|
| 1414 |
|
|
if test -r "$(SIMTOP)".vhd; then \
|
| 1415 |
|
|
arch=`grep -i architecture $(SIMTOP).vhd | grep -i $(SIMTOP) | awk '{ print $$2}'`; \
|
| 1416 |
|
|
printf "\tncelab -timescale 10ps/10ps $(SIMTOP):$$arch\n" >> make.ncsim ; \
|
| 1417 |
|
|
fi; \
|
| 1418 |
|
|
echo $(SIMTOP).mpf; \
|
| 1419 |
|
|
for i in $(VHDLSIMFILES); do \
|
| 1420 |
|
|
echo VALUE \"\/$$i,hdl\" >> libero_sim_files; \
|
| 1421 |
|
|
done; \
|
| 1422 |
|
|
echo LIST LIBRARIES >> $(TOP)_libero.prj; \
|
| 1423 |
|
|
for i in `cat libs.txt`; do \
|
| 1424 |
|
|
case $$i in $(LIBEROLIBSKIP) )\
|
| 1425 |
|
|
uu=0;; \
|
| 1426 |
|
|
*) \
|
| 1427 |
|
|
echo $$i >> $(TOP)_libero.prj; \
|
| 1428 |
|
|
esac; \
|
| 1429 |
|
|
done; \
|
| 1430 |
|
|
cat $(GRLIB)/bin/sonata2.sws >> sonata.sws; \
|
| 1431 |
|
|
cp sonata.sws symphony.ini; \
|
| 1432 |
|
|
cat tmp.son >> sonata.sws; \
|
| 1433 |
|
|
echo "[properties]" >> sonata.sws; \
|
| 1434 |
|
|
echo " work = sonata" >> sonata.sws; \
|
| 1435 |
|
|
echo "[]" >> sonata.sws; \
|
| 1436 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1437 |
|
|
echo ENDFILELIST >> libero_simlist; \
|
| 1438 |
|
|
echo ENDLIST >> libero_simlist; \
|
| 1439 |
|
|
echo ENDFILELIST >> libero_synlist; \
|
| 1440 |
|
|
echo ENDLIST >> libero_synlist; \
|
| 1441 |
|
|
for i in `cat libs.txt`; do \
|
| 1442 |
|
|
case $$i in $(LIBEROLIBSKIP) )\
|
| 1443 |
|
|
uu=0;; \
|
| 1444 |
|
|
*) \
|
| 1445 |
|
|
echo LIST LIBRARIES_$$i >> $(TOP)_libero.prj; \
|
| 1446 |
|
|
echo ALIAS=$$i >> $(TOP)_libero.prj; \
|
| 1447 |
|
|
echo "COMPILE_OPTION=COMPILE" >> $(TOP)_libero.prj; \
|
| 1448 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1449 |
|
|
esac; \
|
| 1450 |
|
|
done; \
|
| 1451 |
|
|
cat libero_syn_files >> $(TOP)_libero.prj; \
|
| 1452 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1453 |
|
|
echo LIST SimulationOptions >> $(TOP)_libero.prj; \
|
| 1454 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1455 |
|
|
echo LIST ExcludePackageForSimulation >> $(TOP)_libero.prj; \
|
| 1456 |
|
|
echo LIST $(TOP) >> $(TOP)_libero.prj; \
|
| 1457 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1458 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1459 |
|
|
cat libero_sim_files >> $(TOP)_libero.prj; \
|
| 1460 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1461 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1462 |
|
|
echo LIST IncludeModuleForSimulation >> $(TOP)_libero.prj; \
|
| 1463 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1464 |
|
|
echo LIST UserCustomizedFileList >> $(TOP)_libero.prj; \
|
| 1465 |
|
|
echo LIST \"$(TOP)\" >> $(TOP)_libero.prj; \
|
| 1466 |
|
|
cat libero_synlist >> $(TOP)_libero.prj; \
|
| 1467 |
|
|
cat libero_simlist >> $(TOP)_libero.prj; \
|
| 1468 |
|
|
echo ENDLIST >> $(TOP)_libero.prj; \
|
| 1469 |
|
|
echo ENDLIST >> $(TOP)_libero.prj;
|
| 1470 |
|
|
# for i in $(TOOLSKIP); do \
|
| 1471 |
|
|
case $$i in \
|
| 1472 |
|
|
libero ) rm -rf simulation $(TOP)_libero.prj;; \
|
| 1473 |
|
|
quartus ) rm $(TOP).q?f;; \
|
| 1474 |
|
|
ghdl ) rm compile.ghdl tmpmake.ghdl ;; \
|
| 1475 |
|
|
sonata ) rm -rf sonata.sws compile.son make.son ;; \
|
| 1476 |
|
|
esac; \
|
| 1477 |
|
|
done
|
| 1478 |
|
|
|
| 1479 |
|
|
########## Import from other libraries ###############
|
| 1480 |
|
|
|
| 1481 |
|
|
import-actel-cc:
|
| 1482 |
|
|
@if test -r $(CORECONSOLE); then \
|
| 1483 |
|
|
echo "Importing CoreMP7 files from Actel CoreConsole IP Library"; \
|
| 1484 |
|
|
echo " Importing $(COREMP7BRIDGE_FILES) to lib/techmap/proasic3"; \
|
| 1485 |
|
|
for i in $(COREMP7BRIDGE_FILES); do cp $(COREMP7BRIDGE_PATH)/$$i $(GRLIB)/lib/techmap/proasic3; done; \
|
| 1486 |
|
|
echo " Importing $(COREMP7_FILES) to lib/techmap/proasic3";\
|
| 1487 |
|
|
for i in $(COREMP7_FILES); do cp $(COREMP7_PATH)/$$i $(GRLIB)/lib/techmap/proasic3; done; \
|
| 1488 |
|
|
else \
|
| 1489 |
|
|
echo "CORECONSOLE environment variable is not correctly set!"; \
|
| 1490 |
|
|
fi
|
| 1491 |
|
|
|
| 1492 |
|
|
######## Common cleaning ####################
|
| 1493 |
|
|
|
| 1494 |
|
|
clean: $(CLEAN) vsim-clean ise-clean ncsim-clean ghdl-clean synplify-clean quartus-clean sonata-clean \
|
| 1495 |
|
|
actel-clean dc-clean rc-clean isp-clean precision-clean vsimsa-clean avhdl-clean riviera-clean
|
| 1496 |
|
|
-rm -rf verilog.txt tkparse.exe main.tk ahbrom outdata ahbrom.bin
|
| 1497 |
|
|
|
| 1498 |
|
|
scripts-clean:
|
| 1499 |
|
|
-rm -rf compile\.* libs.txt *.qsf *.qpf *\.ghdl ghdl.path \
|
| 1500 |
|
|
compile\.* libs.do make\.* *.xst cds.lib *.npl $(TOP)_ise.tcl \
|
| 1501 |
|
|
config.h .config.old hdl.var $(TOP)_dc.tcl $(TOP).rc \
|
| 1502 |
|
|
$(TOP)_synplify.prj $(SIMTOP).mpf tmpmake.ghdl \
|
| 1503 |
|
|
$(TOP)_designer.tcl $(TOP)_designer_act.tcl \
|
| 1504 |
|
|
modelsim.ini \
|
| 1505 |
|
|
alibs.do avhdl.tcl riviera.do
|
| 1506 |
|
|
|
| 1507 |
|
|
distclean: $(CLEAN) clean scripts-clean
|
| 1508 |
|
|
|
| 1509 |
|
|
libclean:
|
| 1510 |
|
|
-@rm work.v; \
|
| 1511 |
|
|
for j in `cat libs.txt` work ; do \
|
| 1512 |
|
|
rm $$j.vhd; \
|
| 1513 |
|
|
done;
|
| 1514 |
|
|
make distclean
|
| 1515 |
|
|
|
| 1516 |
|
|
none-clean:
|
| 1517 |
|
|
|
| 1518 |
|
|
######## xconfig targets ####################
|
| 1519 |
|
|
|
| 1520 |
|
|
ifneq ($(CURLIB), $(GRLIB))
|
| 1521 |
|
|
include $(GRLIB)/bin/Makefile.config
|
| 1522 |
|
|
endif
|
| 1523 |
|
|
|
| 1524 |
|
|
TKCONFIG= $(GRLIB)/bin/tkconfig
|
| 1525 |
|
|
|
| 1526 |
|
|
tkparse.o: $(TKCONFIG)/tkparse.c
|
| 1527 |
|
|
$(CC) -g -c $<
|
| 1528 |
|
|
|
| 1529 |
|
|
tkcond.o: $(TKCONFIG)/tkcond.c
|
| 1530 |
|
|
$(CC) -g -c $<
|
| 1531 |
|
|
|
| 1532 |
|
|
tkgen.o: $(TKCONFIG)/tkgen.c
|
| 1533 |
|
|
$(CC) -g -c $<
|
| 1534 |
|
|
|
| 1535 |
|
|
|
| 1536 |
|
|
tkparse.exe: tkparse.o tkcond.o tkgen.o
|
| 1537 |
|
|
$(CC) -g tkparse.o tkcond.o tkgen.o -o tkparse.exe
|
| 1538 |
|
|
|
| 1539 |
|
|
lconfig.tk: config.in $(CONFDEP) $(HELPDEP)
|
| 1540 |
|
|
make main.tk
|
| 1541 |
|
|
cat $(TKCONFIG)/header.tk main.tk $(TKCONFIG)/tail.tk > lconfig.tk
|
| 1542 |
|
|
chmod a+x lconfig.tk
|
| 1543 |
|
|
|
| 1544 |
|
|
main.tk : config.in tkparse.exe $(CONFDEP) $(HELPDEP)
|
| 1545 |
|
|
./tkparse.exe config.in $(GRLIB) $(EXTRALIBS) > main.tk
|
| 1546 |
|
|
|
| 1547 |
|
|
$(GRLIB)/bin/Makefile.config:
|
| 1548 |
|
|
make -C $(GRLIB) -f bin/Makefile cfgdep
|
| 1549 |
|
|
|
| 1550 |
|
|
xconfig: lconfig.tk $(GRLIB)/bin/Makefile.config
|
| 1551 |
|
|
@if test -r "/usr/bin/wish84.exe"; then /usr/bin/wish84.exe -f lconfig.tk; \
|
| 1552 |
|
|
else \
|
| 1553 |
|
|
if test -r "/mingw/bin/wish84.exe"; then \
|
| 1554 |
|
|
if !(test -r "/mingw/bin/echo.bat"); then \
|
| 1555 |
|
|
cp $(GRLIB)/bin/echo.bat /mingw/bin/echo.bat; \
|
| 1556 |
|
|
fi; \
|
| 1557 |
|
|
if !(test -r "/mingw/bin/wish"); then \
|
| 1558 |
|
|
cp $(GRLIB)/bin/wish /mingw/bin/wish; \
|
| 1559 |
|
|
fi; \
|
| 1560 |
|
|
fi; \
|
| 1561 |
|
|
wish -f lconfig.tk; \
|
| 1562 |
|
|
fi; \
|
| 1563 |
|
|
if test $$? = "2" ; then \
|
| 1564 |
|
|
cpp -P -DGRLIB_PATH=$(GRLIB) config.vhd.in > config.vhd; \
|
| 1565 |
|
|
echo config.vhd created; \
|
| 1566 |
|
|
fi
|
| 1567 |
|
|
|
| 1568 |
|
|
xdep:
|
| 1569 |
|
|
cpp -P -DGRLIB_PATH=$(GRLIB) config.vhd.in > config.vhd
|
| 1570 |
|
|
|
| 1571 |
|
|
config:
|
| 1572 |
|
|
cp $(GRLIB)/boards/$(BOARD)/config .config
|
| 1573 |
|
|
cp $(GRLIB)/boards/$(BOARD)/config.h config.h
|
| 1574 |
|
|
make xdep
|
| 1575 |
|
|
|
| 1576 |
|
|
.PHONY: sonata xst precision synplify scripts netlists bitfiles cut-actel
|
| 1577 |
|
|
|
| 1578 |
|
|
############ Maintenance - do not remove! ##################
|
| 1579 |
|
|
|
| 1580 |
|
|
docs:
|
| 1581 |
|
|
find ./ -name '*.gif' | zip ../grdocs.zip -@
|
| 1582 |
|
|
find ./ -name '*.html' | zip ../grdocs.zip -@
|
| 1583 |
|
|
find ./ -name '*.pdf' | zip ../grdocs.zip -@
|
| 1584 |
|
|
find ./ -name '*.jpg' | zip ../grdocs.zip -@
|
| 1585 |
|
|
|
| 1586 |
|
|
netlistsft:
|
| 1587 |
|
|
tar czf ../grlib-ft-netlists-$(VER).tar.gz netlists \
|
| 1588 |
|
|
lib/techmap/stratixii/gr*fp*_*_* lib/techmap/unisim/gr*fp*_*_*
|
| 1589 |
|
|
|
| 1590 |
|
|
netlists:
|
| 1591 |
|
|
tar czf ../grlib-netlists-$(VER).tar.gz netlists \
|
| 1592 |
|
|
lib/techmap/stratixii/gr*fp*_*_* lib/techmap/unisim/gr*fp*_*_*
|
| 1593 |
|
|
rm -rf netlists lib/techmap/*/gr*fp*_*_*
|
| 1594 |
|
|
|
| 1595 |
|
|
usbhost:
|
| 1596 |
|
|
tar czf ../grlib-usb-$(VER).tar.gz $(USBFILES)
|
| 1597 |
|
|
rm -rf $(USBFILES)
|
| 1598 |
|
|
|
| 1599 |
|
|
bitfiles:
|
| 1600 |
|
|
@echo creating grlib-bitfiles-$(VER).tar.gz ;\
|
| 1601 |
|
|
tar czf ../grlib-bitfiles-$(VER).tar.gz `find -name '*bitfiles' -print | xargs` ;\
|
| 1602 |
|
|
rm -rf `find -name '*bitfiles' -print | xargs`
|
| 1603 |
|
|
|
| 1604 |
|
|
cfgdep:
|
| 1605 |
|
|
@printf "CONFDEP = " > bin/Makefile.config
|
| 1606 |
|
|
@for i in `find lib -name '*.in' -print | grep -v vhd | xargs`; do \
|
| 1607 |
|
|
echo -n '$$(GRLIB)'/$$i >> bin/Makefile.config ; \
|
| 1608 |
|
|
printf " \\" >> bin/Makefile.config ; \
|
| 1609 |
|
|
printf "\n" >> bin/Makefile.config ; \
|
| 1610 |
|
|
done;
|
| 1611 |
|
|
@printf " \n" >> bin/Makefile.config
|
| 1612 |
|
|
@printf "HELPDEP = " >> bin/Makefile.config
|
| 1613 |
|
|
@for i in `find lib -name '*.in.help' -print | xargs`; do \
|
| 1614 |
|
|
echo -n '$$(GRLIB)'/$$i >> bin/Makefile.config ; \
|
| 1615 |
|
|
printf " \\" >> bin/Makefile.config ; \
|
| 1616 |
|
|
printf "\n" >> bin/Makefile.config ; \
|
| 1617 |
|
|
done;
|
| 1618 |
|
|
@printf " \n" >> bin/Makefile.config
|
| 1619 |
|
|
|
| 1620 |
|
|
clean-lib:
|
| 1621 |
|
|
@make -f bin/Makefile cfgdep
|
| 1622 |
|
|
@-rm `find -name '*.backup.fm' -print | xargs`
|
| 1623 |
|
|
@-rm `find -name '*.recover.fm' -print | xargs`
|
| 1624 |
|
|
@-rm `find -name '*.backup.book' -print | xargs`
|
| 1625 |
|
|
@-rm `find -name '*.backup.book' -print | xargs`
|
| 1626 |
|
|
@echo "-- pragma translate_off" > lib/grlib/stdlib/version.vhd ;\
|
| 1627 |
|
|
echo "use std.textio.all;" >> lib/grlib/stdlib/version.vhd ;\
|
| 1628 |
|
|
echo "-- pragma translate_on" >> lib/grlib/stdlib/version.vhd ;\
|
| 1629 |
|
|
echo "package version is" >> lib/grlib/stdlib/version.vhd ;\
|
| 1630 |
|
|
echo " constant grlib_version : integer := $(GVER);" >> lib/grlib/stdlib/version.vhd ;\
|
| 1631 |
|
|
echo "-- pragma translate_off" >> lib/grlib/stdlib/version.vhd ;\
|
| 1632 |
|
|
echo -n " constant grlib_date : string := \"" >> lib/grlib/stdlib/version.vhd ;\
|
| 1633 |
|
|
date +%Y%m%d | tr "\n" "\"" >> lib/grlib/stdlib/version.vhd ;\
|
| 1634 |
|
|
echo ";" >> lib/grlib/stdlib/version.vhd ;\
|
| 1635 |
|
|
echo "-- pragma translate_on" >> lib/grlib/stdlib/version.vhd ;\
|
| 1636 |
|
|
echo -n " constant grlib_build : integer := " >> lib/grlib/stdlib/version.vhd ;\
|
| 1637 |
|
|
svn info | awk '/Revision:/ {print $$2 + 1}' | tr "\n" ";" >> lib/grlib/stdlib/version.vhd ;\
|
| 1638 |
|
|
echo "" >> lib/grlib/stdlib/version.vhd ;\
|
| 1639 |
|
|
echo "end;" >> lib/grlib/stdlib/version.vhd ;\
|
| 1640 |
|
|
|
| 1641 |
|
|
delint:
|
| 1642 |
|
|
@if test -r .svn; then echo .svn found, exiting; exit; fi;
|
| 1643 |
|
|
@rm -rf $(INTFILES)
|
| 1644 |
|
|
@cd doc; mv grlib/grlib.pdf grip/grip.pdf haps/haps.pdf tmtc/tmtc.pdf .; \
|
| 1645 |
|
|
mkdir devices ;\
|
| 1646 |
|
|
mv leon3ft-rtax/leon3-rtax.pdf leon3ft-rtax/leon3-rtax-um.pdf devices; \
|
| 1647 |
|
|
mv ftfpga/ftfpga.pdf grlib-ft-fpga.pdf ; \
|
| 1648 |
|
|
mv gr701/*.pdf devices ; \
|
| 1649 |
|
|
rm -rf grlib grip leon3ft-rtax ftfpga gr701 haps
|
| 1650 |
|
|
@echo creating grlib-haps-$(VER).tar.gz ;\
|
| 1651 |
|
|
tar czf ../grlib-haps-$(VER).tar.gz $(HAPSFILES) ;\
|
| 1652 |
|
|
rm -rf $(HAPSFILES)
|
| 1653 |
|
|
@-rm `find -name '*.fm' -print | xargs`
|
| 1654 |
|
|
@-rm `find -name '*.book' -print | xargs`
|
| 1655 |
|
|
@-rm -rf designs/leon3-ft*/bitfiles
|
| 1656 |
|
|
@make -f bin/Makefile bitfiles
|
| 1657 |
|
|
@cd lib/gaisler; mv leon3sim leon3ft
|
| 1658 |
|
|
@cat lib/techmap/unisim/vhdlsyn.txt | sed -e s/#// > x; mv x lib/techmap/unisim/vhdlsyn.txt
|
| 1659 |
|
|
@cat lib/techmap/axcelerator/vhdlsyn.txt | sed -e s/#// > x; mv x lib/techmap/axcelerator/vhdlsyn.txt
|
| 1660 |
|
|
|
| 1661 |
|
|
ft: delint
|
| 1662 |
|
|
@if test -r .svn; then echo .svn found, exiting; exit; fi; \
|
| 1663 |
|
|
echo creating grlib-ft-netlists-$(VER).tar.gz ;\
|
| 1664 |
|
|
tar czf ../grlib-ft-netlists-$(VER).tar.gz netlists ;\
|
| 1665 |
|
|
rm -rf netlists lib/techmap/*/gr*fp*_*_*
|
| 1666 |
|
|
rm -rf $(USBFILES) $(COREMP7FILES) $(T1FILES)
|
| 1667 |
|
|
@cd lib/actel/core1553brm; mv dirs_netlist.txt dirs.txt
|
| 1668 |
|
|
@make -f bin/Makefile cfgdep
|
| 1669 |
|
|
@for i in `find -name '*.vhd' -print | xargs`; do \
|
| 1670 |
|
|
if test -r $$i; then sed -f bin/gr.sed $$i > x; mv x $$i; fi; \
|
| 1671 |
|
|
done
|
| 1672 |
|
|
@xpwd=`pwd`; tname=`basename $$xpwd`; \
|
| 1673 |
|
|
echo creating $$xpwd.tar.gz ;\
|
| 1674 |
|
|
cd .. ; tar czf $$tname.tar.gz $$tname
|
| 1675 |
|
|
|
| 1676 |
|
|
ftfpga: delint
|
| 1677 |
|
|
@if test -r .svn; then echo .svn found, exiting; exit; fi;
|
| 1678 |
|
|
@cd lib/tech; rm -rf $(ASICLIBS)
|
| 1679 |
|
|
@cd lib/techmap; rm -rf $(ASICLIBS)
|
| 1680 |
|
|
@cd lib/spw; rm -rf core
|
| 1681 |
|
|
@cd boards; rm -rf ge-* altera* jop* ut699rh*
|
| 1682 |
|
|
@rm -rf $(INTFTFPGAFILES) $(USBFILES) $(COREMP7FILES) $(T1FILES)
|
| 1683 |
|
|
@cd lib/actel/core1553brm; mv dirs_netlist.txt dirs.txt
|
| 1684 |
|
|
@make -f bin/Makefile cfgdep
|
| 1685 |
|
|
@for i in `find -name '*.vhd' -print | xargs`; do \
|
| 1686 |
|
|
if test -r $$i; then sed -f bin/gr.sed $$i > x; mv x $$i; fi; \
|
| 1687 |
|
|
done
|
| 1688 |
|
|
@xpwd=`pwd`; tname=`basename $$xpwd`; \
|
| 1689 |
|
|
echo creating $$xpwd.tar.gz ;\
|
| 1690 |
|
|
cd .. ; tar czf $$tname.tar.gz $$tname
|
| 1691 |
|
|
|
| 1692 |
|
|
delft: delint
|
| 1693 |
|
|
@if test -r .svn; then echo .svn found, exiting; exit; fi;
|
| 1694 |
|
|
@-rm netlists/*/*/*ft*
|
| 1695 |
|
|
@-rm netlists/*/*/*grspw* ;\
|
| 1696 |
|
|
rm -rf doc/devices doc/grlib-ft-fpga.pdf doc/tmtc.pdf ;\
|
| 1697 |
|
|
echo creating grlib-netlists-$(VER).tar.gz ;\
|
| 1698 |
|
|
tar czf ../grlib-netlists-$(VER).tar.gz netlists ;\
|
| 1699 |
|
|
echo creating grlib-niagara-$(VER).tar.gz ;\
|
| 1700 |
|
|
tar czf ../grlib-niagara-$(VER).tar.gz $(T1FILES) ; \
|
| 1701 |
|
|
rm -rf $(T1FILES) ; \
|
| 1702 |
|
|
echo creating grlib-coremp7-$(VER).tar.gz ;\
|
| 1703 |
|
|
tar czf ../grlib-coremp7-$(VER).tar.gz $(COREMP7FILES) ; \
|
| 1704 |
|
|
rm -rf $(COREMP7FILES) ; \
|
| 1705 |
|
|
rm -rf netlists lib/techmap/*/gr*fp*_*_* ; \
|
| 1706 |
|
|
rm -rf netlists ;\
|
| 1707 |
|
|
rm -rf $(FTFILES)
|
| 1708 |
|
|
@mv software/leon3/Makefile.gpl software/leon3/Makefile
|
| 1709 |
|
|
@make -f bin/Makefile cfgdep
|
| 1710 |
|
|
|
| 1711 |
|
|
com: delft
|
| 1712 |
|
|
@if test -r .svn; then echo .svn found, exiting; exit; fi; \
|
| 1713 |
|
|
for i in `find -name '*.vhd' -print | xargs`; do \
|
| 1714 |
|
|
if test -r $$i; then sed -f bin/gr.sed $$i > x; mv x $$i; fi; \
|
| 1715 |
|
|
done ;\
|
| 1716 |
|
|
rm -rf $(CONTRIBLIBS) designs/*ft* designs/t1*;\
|
| 1717 |
|
|
rm -rf lib/spw/netlists ; \
|
| 1718 |
|
|
echo creating grlib-usb-$(VER).tar.gz ;\
|
| 1719 |
|
|
tar czf ../grlib-usb-$(VER).tar.gz $(USBFILES) ; \
|
| 1720 |
|
|
rm -rf $(USBFILES) ; \
|
| 1721 |
|
|
make -f bin/Makefile cfgdep ;\
|
| 1722 |
|
|
xpwd=`pwd`; tname=`basename $$xpwd`; \
|
| 1723 |
|
|
echo creating $$xpwd.tar.gz ;\
|
| 1724 |
|
|
cd .. ; tar czf $$tname.tar.gz $$tname
|
| 1725 |
|
|
|
| 1726 |
|
|
fpga-com: delft
|
| 1727 |
|
|
@if test -r .svn; then echo .svn found, exiting; exit; fi
|
| 1728 |
|
|
@cd lib/tech; rm -rf $(ASICLIBS)
|
| 1729 |
|
|
@cd lib/techmap; rm -rf $(ASICLIBS)
|
| 1730 |
|
|
@for i in `find -name '*.vhd' -print | xargs`; do \
|
| 1731 |
|
|
if test -r $$i; then sed -f bin/gr.sed $$i > x; mv x $$i; fi; \
|
| 1732 |
|
|
done ;\
|
| 1733 |
|
|
rm -rf lib/openchip designs/*ft* ;\
|
| 1734 |
|
|
rm -rf lib/spw/netlists ; \
|
| 1735 |
|
|
rm -rf $(USBFILES) ; \
|
| 1736 |
|
|
make -f bin/Makefile cfgdep ;\
|
| 1737 |
|
|
xpwd=`pwd`; tname=`basename $$xpwd`; \
|
| 1738 |
|
|
echo creating $$xpwd.tar.gz ;\
|
| 1739 |
|
|
cd .. ; tar czf $$tname.tar.gz $$tname
|
| 1740 |
|
|
|
| 1741 |
|
|
gpl: delft
|
| 1742 |
|
|
@if test -r .svn; then echo .svn found, exiting; exit; fi; \
|
| 1743 |
|
|
rm -rf $(COMFILES) ;\
|
| 1744 |
|
|
for i in `find -name '*.vhd' -print | xargs`; do \
|
| 1745 |
|
|
if test -r $$i; then sed -f bin/gpl.sed $$i > x; mv x $$i; fi; \
|
| 1746 |
|
|
done ;\
|
| 1747 |
|
|
make -f bin/Makefile cfgdep ;\
|
| 1748 |
|
|
xpwd=`pwd`; tname=`basename $$xpwd`; \
|
| 1749 |
|
|
echo creating $$xpwd.tar.gz ;\
|
| 1750 |
|
|
cd .. ; tar czf $$tname.tar.gz $$tname
|
| 1751 |
|
|
|
| 1752 |
|
|
fpga: delft
|
| 1753 |
|
|
@if test -r .svn; then echo .svn found, exiting; exit; fi
|
| 1754 |
|
|
@cd lib/tech; rm -rf $(ASICLIBS)
|
| 1755 |
|
|
@cd lib/techmap; rm -rf $(ASICLIBS)
|
| 1756 |
|
|
@cd boards; rm -rf ge-* jop*
|
| 1757 |
|
|
@rm -rf $(INTFPGAFILES) ;\
|
| 1758 |
|
|
rm -rf $(COMFILES) ;\
|
| 1759 |
|
|
for i in `find -name '*.vhd' -print | xargs`; do \
|
| 1760 |
|
|
if test -r $$i; then sed -f bin/gr.sed $$i > x; mv x $$i; fi; \
|
| 1761 |
|
|
done ;\
|
| 1762 |
|
|
make -f bin/Makefile cfgdep ;\
|
| 1763 |
|
|
xpwd=`pwd`; tname=`basename $$xpwd`; \
|
| 1764 |
|
|
echo creating $$xpwd.tar.gz ;\
|
| 1765 |
|
|
cd .. ; tar czf $$tname.tar.gz $$tname
|
| 1766 |
|
|
|
| 1767 |
|
|
distft:
|
| 1768 |
|
|
@-nsvn=`svn info | awk '/Revision:/ {print $$2 + 1}'` ;\
|
| 1769 |
|
|
rm -rf ~/vhdl/grlib-ft-$(VER)-b$$nsvn ;\
|
| 1770 |
|
|
echo exporting repository to ~/vhdl/grlib-ft-$(VER)-b$$nsvn ;\
|
| 1771 |
|
|
svn export . ~/vhdl/grlib-ft-$(VER)-b$$nsvn ;\
|
| 1772 |
|
|
make -C ~/vhdl/grlib-ft-$(VER)-b$$nsvn ft
|
| 1773 |
|
|
|
| 1774 |
|
|
distftfpga:
|
| 1775 |
|
|
@-nsvn=`svn info | awk '/Revision:/ {print $$2 + 1}'` ;\
|
| 1776 |
|
|
rm -rf ~/vhdl/grlib-ft-fpga-$(VER)-b$$nsvn ;\
|
| 1777 |
|
|
echo exporting repository to ~/vhdl/grlib-ft-fpga-$(VER)-b$$nsvn ;\
|
| 1778 |
|
|
svn export . ~/vhdl/grlib-ft-fpga-$(VER)-b$$nsvn ;\
|
| 1779 |
|
|
make -C ~/vhdl/grlib-ft-fpga-$(VER)-b$$nsvn ftfpga
|
| 1780 |
|
|
|
| 1781 |
|
|
distfpga:
|
| 1782 |
|
|
@-nsvn=`svn info | awk '/Revision:/ {print $$2 + 1}'` ;\
|
| 1783 |
|
|
rm -rf ~/vhdl/grlib-fpga-$(VER)-b$$nsvn ;\
|
| 1784 |
|
|
echo exporting repository to ~/vhdl/grlib-fpga-$(VER)-b$$nsvn ;\
|
| 1785 |
|
|
svn export . ~/vhdl/grlib-fpga-$(VER)-b$$nsvn ;\
|
| 1786 |
|
|
make -C ~/vhdl/grlib-fpga-$(VER)-b$$nsvn fpga
|
| 1787 |
|
|
|
| 1788 |
|
|
distfpga-com:
|
| 1789 |
|
|
@-nsvn=`svn info | awk '/Revision:/ {print $$2 + 1}'` ;\
|
| 1790 |
|
|
rm -rf ~/vhdl/grlib-fpga-com-$(VER)-b$$nsvn ;\
|
| 1791 |
|
|
echo exporting repository to ~/vhdl/grlib-fpga-com-$(VER)-b$$nsvn ;\
|
| 1792 |
|
|
svn export . ~/vhdl/grlib-fpga-com-$(VER)-b$$nsvn ;\
|
| 1793 |
|
|
make -C ~/vhdl/grlib-fpga-com-$(VER)-b$$nsvn fpga-com
|
| 1794 |
|
|
|
| 1795 |
|
|
distcom:
|
| 1796 |
|
|
@-nsvn=`svn info | awk '/Revision:/ {print $$2 + 1}'` ;\
|
| 1797 |
|
|
rm -rf ~/vhdl/grlib-com-$(VER)-b$$nsvn ;\
|
| 1798 |
|
|
echo exporting repository to ~/vhdl/grlib-com-$(VER)-b$$nsvn ;\
|
| 1799 |
|
|
svn export . ~/vhdl/grlib-com-$(VER)-b$$nsvn ;\
|
| 1800 |
|
|
make -C ~/vhdl/grlib-com-$(VER)-b$$nsvn com
|
| 1801 |
|
|
|
| 1802 |
|
|
distgpl:
|
| 1803 |
|
|
@-nsvn=`svn info | awk '/Revision:/ {print $$2 + 1}'` ;\
|
| 1804 |
|
|
rm -rf ~/vhdl/grlib-gpl-$(VER)-b$$nsvn ;\
|
| 1805 |
|
|
echo exporting repository to ~/vhdl/grlib-gpl-$(VER)-b$$nsvn ;\
|
| 1806 |
|
|
svn export . ~/vhdl/grlib-gpl-$(VER)-b$$nsvn ;\
|
| 1807 |
|
|
make -C ~/vhdl/grlib-gpl-$(VER)-b$$nsvn gpl
|
| 1808 |
|
|
|
| 1809 |
|
|
dist:
|
| 1810 |
|
|
make distft distcom distgpl distfpga
|
| 1811 |
|
|
|
| 1812 |
|
|
axsmall:
|
| 1813 |
|
|
cp $(GRLIB)/lib/tech/axcelerator/components/axcelerator_small.vhd \
|
| 1814 |
|
|
$(GRLIB)/lib/tech/axcelerator/components/axcelerator.vhd
|
| 1815 |
|
|
cp $(GRLIB)/lib/tech/axcelerator/components/axcelerator_components_small.vhd \
|
| 1816 |
|
|
$(GRLIB)/lib/tech/axcelerator/components/axcelerator_components.vhd
|
| 1817 |
|
|
|
| 1818 |
|
|
axfull:
|
| 1819 |
|
|
cp $(GRLIB)/lib/tech/axcelerator/components/axcelerator_full.vhd \
|
| 1820 |
|
|
$(GRLIB)/lib/tech/axcelerator/components/axcelerator.vhd
|
| 1821 |
|
|
cp $(GRLIB)/lib/tech/axcelerator/components/axcelerator_components_full.vhd \
|
| 1822 |
|
|
$(GRLIB)/lib/tech/axcelerator/components/axcelerator_components.vhd
|
| 1823 |
|
|
|
| 1824 |
|
|
cut-lattice:
|
| 1825 |
|
|
mv boards/ge-hpe-mini-lattice .; rm -rf boards/*; mv ge-hpe-mini-lattice boards
|
| 1826 |
|
|
mv designs/leon3-ge-hpe-mini-lattice .; rm -rf designs/*; mv leon3-ge-hpe-mini-lattice designs
|
| 1827 |
|
|
-mkdir x
|
| 1828 |
|
|
mv lib/tech/lattice lib/tech/synplify x; rm -rf lib/tech/*; mv x/* lib/tech
|
| 1829 |
|
|
cd lib/techmap; rm -rf buffers/clkbuf_actel.vhd buffers/clkbuf_xilinx.vhd \
|
| 1830 |
|
|
clocks/clkgen_actel.vhd clocks/clkgen_altera.vhd memory/mem_altera_gen.vhd \
|
| 1831 |
|
|
clocks/clkgen_xilinx.vhd tap/tap_xilinx_gen.vhd ddr/ddr_xilinx.vhd \
|
| 1832 |
|
|
memory/mem_ihp25_gen.vhd memory/mem_xilinx_gen.vhd \
|
| 1833 |
|
|
memory/mem_umc_gen.vhd memory/mem_virage_gen.vhd memory/mem_apa_gen.vhd \
|
| 1834 |
|
|
memory/mem_apa3_gen.vhd memory/mem_axcelerator_gen.vhd \
|
| 1835 |
|
|
pads/pad_atc18_gen.vhd pads/pad_ihp25_gen.vhd pads/pad_rhumc_gen.vhd \
|
| 1836 |
|
|
pads/pad_actel_gen.vhd pads/pad_xilinx_gen.vhd ddr/ddr_xilinx.vhd \
|
| 1837 |
|
|
tap/tap_xilinx_gen.vhd
|
| 1838 |
|
|
cd lib; rm -rf contrib openchip gaisler/usb
|
| 1839 |
|
|
|
| 1840 |
|
|
cut-altera:
|
| 1841 |
|
|
mkdir x; mv boards/ge-hpe-com* boards/altera* boards/ge-hpe-mini \
|
| 1842 |
|
|
boards/jopdesign-ep1c12 x; rm -rf boards/*; mv x/* boards
|
| 1843 |
|
|
mv designs/leon3-altera-ep1c20 designs/leon3-ge-compact* \
|
| 1844 |
|
|
designs/leon3-jopdesign-ep1c12 designs/leon3-ge-hpe-mini x; \
|
| 1845 |
|
|
rm -rf designs/*; mv x/* designs
|
| 1846 |
|
|
mv lib/tech/altera lib/tech/synplify x; rm -rf lib/tech/*; mv x/* lib/tech
|
| 1847 |
|
|
cd lib/techmap; rm -rf buffers/clkbuf_actel.vhd buffers/clkbuf_xilinx.vhd \
|
| 1848 |
|
|
clocks/clkgen_xilinx.vhd clocks/clkgen_actel.vhd memory/mem_xilinx.vhd \
|
| 1849 |
|
|
memory/mem_ihp25_gen.vhd memory/mem_lattice_gen.vhd ddr/ddr_lattice.vhd \
|
| 1850 |
|
|
memory/mem_umc_gen.vhd memory/mem_virage_gen.vhd memory/mem_apa_gen.vhd \
|
| 1851 |
|
|
memory/mem_apa3_gen.vhd memory/mem_axcelerator_gen.vhd memory/mem_xilinx_gen.vhd \
|
| 1852 |
|
|
pads/pad_atc18_gen.vhd pads/pad_ihp25_gen.vhd pads/pad_rhumc_gen.vhd \
|
| 1853 |
|
|
pads/pad_xilinx_gen.vhd pads/pad_actel_gen.vhd \
|
| 1854 |
|
|
ddr/ddr_xilinx.vhd ddr/ddr_lattice.vhd tap/tap_xilinx_gen.vhd
|
| 1855 |
|
|
rm bin/route_lattice
|
| 1856 |
|
|
cd lib; rm -rf contrib gleichmann openchip gaisler/ddr gaisler/usb
|
| 1857 |
|
|
|
| 1858 |
|
|
|
| 1859 |
|
|
cut-xilinx:
|
| 1860 |
|
|
mkdir x; mv boards/gr-* x; rm -rf boards/*; mv x/* boards; rm -rf boards/gr-cpci-ax
|
| 1861 |
|
|
mv designs/leon3-gr* x; rm -rf designs/*; mv x/* designs; rm -rf designs/leon3-gr-cpci-ax
|
| 1862 |
|
|
mv lib/tech/xilinx lib/tech/synplify x; rm -rf lib/tech/*; mv x/* lib/tech
|
| 1863 |
|
|
cd lib/techmap; rm -rf buffers/clkbuf_actel.vhd \
|
| 1864 |
|
|
clocks/clkgen_actel.vhd clocks/clkgen_altera.vhd memory/mem_altera_gen.vhd \
|
| 1865 |
|
|
memory/mem_ihp25_gen.vhd memory/mem_lattice_gen.vhd ddr/ddr_lattice.vhd \
|
| 1866 |
|
|
memory/mem_umc_gen.vhd memory/mem_virage_gen.vhd memory/mem_apa_gen.vhd \
|
| 1867 |
|
|
memory/mem_apa3_gen.vhd memory/mem_axcelerator_gen.vhd \
|
| 1868 |
|
|
pads/pad_atc18_gen.vhd pads/pad_ihp25_gen.vhd pads/pad_rhumc_gen.vhd \
|
| 1869 |
|
|
pads/pad_actel_gen.vhd ddr/ddr_lattice.vhd
|
| 1870 |
|
|
cd lib; rm -rf contrib gleichmann openchip
|
| 1871 |
|
|
|
| 1872 |
|
|
|
| 1873 |
|
|
xonly:
|
| 1874 |
|
|
rm compile.dc compile.rc ghdl.path leon3mp_synplify.qpf \
|
| 1875 |
|
|
leon3mp_synplify.qsf verilog.txt tmpmake.ghdl tmp.txt \
|
| 1876 |
|
|
leon3mp_designer.tcl leon3mp_designer_act.tcl leon3mp.rc leon3mp.qsf \
|
| 1877 |
|
|
leon3mp.qpf leon3mp.ise_ISE_Backup leon3mp_dc.tcl
|
| 1878 |
|
|
|
| 1879 |
|
|
cut-actel:
|
| 1880 |
|
|
-mkdir x
|
| 1881 |
|
|
mv boards/gr-cpci-ax x; rm -rf boards/*; mv x boards/gr-cpci-ax
|
| 1882 |
|
|
mv designs/leon3-gr-cpci-ax x; rm -rf designs/*; mv x designs/leon3-gr-cpci-ax
|
| 1883 |
|
|
rm -rf lib/tech lib/gaisler/ddr
|
| 1884 |
|
|
cd lib/techmap; rm -rf buffers/clkbuf_xilinx.vhd \
|
| 1885 |
|
|
clocks/clkgen_xilinx.vhd clocks/clkgen_altera.vhd memory/mem_altera_gen.vhd \
|
| 1886 |
|
|
memory/mem_ihp25_gen.vhd memory/mem_lattice_gen.vhd \
|
| 1887 |
|
|
memory/mem_umc_gen.vhd memory/mem_virage_gen.vhd memory/mem_xilinx_gen.vhd \
|
| 1888 |
|
|
pads/pad_atc18_gen.vhd pads/pad_ihp25_gen.vhd pads/pad_rhumc_gen.vhd \
|
| 1889 |
|
|
pads/pad_xilinx_gen.vhd ddr/ddr_xilinx.vhd ddr/ddr_lattice.vhd \
|
| 1890 |
|
|
tap/tap_xilinx_gen.vhd
|
| 1891 |
|
|
cd lib; rm -rf contrib gleichmann openchip gaisler/ddr gaisler/usb
|
