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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [digilent-xc3s1600e/] [system2.ucf] - Blame information for rev 2

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1 2 dimamali
# ==== Clock inputs (CLK) ====
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NET "clk_in" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
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NET "clk_in" PERIOD = 20ns HIGH 40%;
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# ==== Pushbuttons (BTN) ====
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#NET "BTN_EAST" LOC = "H13" |  IOSTANDARD = LVTTL | PULLDOWN ;
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#NET "BTN_NORTH" LOC = "V4" |  IOSTANDARD = LVTTL | PULLDOWN ;
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#NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
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NET "reset_in" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
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#NET "btn0"     LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
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#NET "btn1"     LOC = "V4"  | IOSTANDARD = LVTTL | PULLDOWN ;
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#NET "btn2"     LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
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# ==== Discrete LEDs (LED) ====
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# These are shared connections with the FX2 connector
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NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
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NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
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NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
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NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
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NET "led<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
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NET "led<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
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NET "led<6>" LOC = "E9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
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NET "led<7>" LOC = "F9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
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# ==== Rotary Encoder ====
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NET "rotary<0>" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
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NET "rotary<1>" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
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NET "rotary<2>" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
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# ==== Slide Switches (SW) ====
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NET "sw<0>"  LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
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NET "sw<1>"  LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
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NET "sw<2>"  LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
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NET "sw<3>"  LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
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# ==== RS-232 Serial Ports (RS232) ====
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NET "uart_rx"  LOC = "R7" |  IOSTANDARD = LVTTL ;
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NET "uart_tx"  LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
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# ==== DDR SDRAM (SD) ====   (I/O Bank 3, VCCO=2.5V)
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NET "ddr_addr<0>"          LOC = "T1" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<1>"          LOC = "R3" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<2>"          LOC = "R2" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<3>"          LOC = "P1" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<4>"          LOC = "F4" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<5>"          LOC = "H4" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<6>"          LOC = "H3" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<7>"          LOC = "H1" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<8>"          LOC = "H2" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<9>"          LOC = "N4" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<10>"  LOC = "T2" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<11>"  LOC = "N5" | IOSTANDARD = SSTL2_I ;
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NET "ddr_addr<12>"  LOC = "P2" | IOSTANDARD = SSTL2_I ;
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NET "ddr_ba<0>"            LOC = "K5" | IOSTANDARD = SSTL2_I ;
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NET "ddr_ba<1>"            LOC = "K6" | IOSTANDARD = SSTL2_I ;
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NET "ddr_cas_n"         LOC = "C2" | IOSTANDARD = SSTL2_I ;
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NET "ddr_clk_n"         LOC = "J4" | IOSTANDARD = SSTL2_I ;
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NET "ddr_clk"                   LOC = "J5" | IOSTANDARD = SSTL2_I ;
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NET "ddr_cke"                   LOC = "K3" | IOSTANDARD = SSTL2_I ;
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NET "ddr_cs_n"                  LOC = "K4" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<0>"            LOC = "L2" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<1>"            LOC = "L1" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<2>"            LOC = "L3" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<3>"            LOC = "L4" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<4>"            LOC = "M3" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<5>"            LOC = "M4" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<6>"            LOC = "M5" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<7>"            LOC = "M6" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<8>"            LOC = "E2" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<9>"            LOC = "E1" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<10>"            LOC = "F1" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<11>"            LOC = "F2" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<12>"            LOC = "G6" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<13>"            LOC = "G5" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<14>"            LOC = "H6" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dq<15>"            LOC = "H5" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dm<0>"            LOC = "J2" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dqs<0>"           LOC = "L6" | IOSTANDARD = SSTL2_I ;
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NET "ddr_ras_n"         LOC = "C1" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dm<1>"            LOC = "J1" | IOSTANDARD = SSTL2_I ;
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NET "ddr_dqs<1>"           LOC = "G3" | IOSTANDARD = SSTL2_I ;
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NET "ddr_we_n"          LOC = "D1" | IOSTANDARD = SSTL2_I ;
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# Path to allow connection to top DCM connection
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NET "ddr_clk_fb"                LOC = "B9" | IOSTANDARD = LVCMOS33 ;
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#NET "ddr_clk_fb" PERIOD = 7.5ns HIGH 40%;
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# Prohibit VREF pins
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CONFIG PROHIBIT = D2;
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CONFIG PROHIBIT = G4;
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CONFIG PROHIBIT = J6;
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CONFIG PROHIBIT = L5;
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CONFIG PROHIBIT = R4;
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