OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [gr-pci-xc5v/] [default.sdc] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
# Synplicity, Inc. constraint file
2
# /home/jiri/ibm/vhdl/grlib/boards/gr-cpci-xc2v/default.sdc
3
# Written on Mon Feb 14 11:45:37 2005
4
# by Synplify Pro, Synplify Pro 8.0 Scope Editor
5
 
6
#
7
# Collections
8
#
9
 
10
#
11
# Clocks
12
#
13
define_clock -disable   -name {clk}  -freq 50.000 -clockgroup default_clkgroup
14
define_clock -disable   -name {pci_clk}  -freq 40.000 -clockgroup pci_clkgroup
15
define_clock -disable   -name {usb_clkout}  -freq 60.000 -clockgroup usb_clkgroup
16
 
17
#
18
# Clock to Clock
19
#
20
 
21
#
22
# Inputs/Outputs
23
#
24
define_output_delay -disable     -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
25
define_input_delay -disable      -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
26
define_output_delay -disable     -default  14.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
27
define_input_delay  -disable     -default  18.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
28
define_input_delay  -disable     {pci_rst}  0.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
29
 
30
#
31
# Registers
32
#
33
 
34
#
35
# Multicycle Path
36
#
37
 
38
#
39
# False Path
40
#
41
 
42
#
43
# Path Delay
44
#
45
 
46
#
47
# Attributes
48
#
49
define_global_attribute          syn_useioff {1}
50
 
51
#
52
# I/O standards
53
#
54
 
55
#
56
# Compile Points
57
#
58
 
59
#
60
# Other Constraints
61
#

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.