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dimamali |
#
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# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
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# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
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# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE.
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#
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# (c) Copyright 2005 Xilinx, Inc.
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# All rights reserved.
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#
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# Bus clock nets
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NET "sys_clk" TNM_NET = "sys_clk";
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NET "tft_clk" TNM_NET = "tft_clk";
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NET sys_clk_in TNM_NET = "sys_clk_in";
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TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
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NET sys_clk_in LOC = AE14;
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NET sys_clk_in IOSTANDARD = LVCMOS33;
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NET sys_rst_in LOC = D6;
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NET sys_rst_in PULLUP;
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NET sys_rst_in TIG;
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NET uart_RX LOC = W2;
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NET uart_RX IOSTANDARD = LVCMOS33;
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NET uart_RX TIG;
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NET uart_TX LOC = W1;
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NET uart_TX IOSTANDARD = LVCMOS33;
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NET uart_TX TIG;
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NET ext_irq TIG;
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# Reset timing ignore - treat as async paths
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NET sys_rst TIG;
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NET opb_v20_0_OPB_Rst TIG;
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NET lmb_v10_1_OPB_Rst TIG;
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NET lmb_v10_0_OPB_Rst TIG;
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NET opb_v20_0_Debug_SYS_Rst TIG;
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NET Debug_Rst TIG;
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NET plb_v34_0_PLB_Rst TIG;
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NET dcm_locked TIG;
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# Locate DCM/BUFG - Tools can probably figure them out automatically
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# but just LOC them down to be safe
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INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
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INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
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INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
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INST dcm_0/dcm_0/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y0;
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INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
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INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
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INST dcm_1/dcm_1/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y31;
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INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
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////////////////////////////////////////////////////////////////////////////
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// Buttons, LEDs, and DIP Switches
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////////////////////////////////////////////////////////////////////////////
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# GPLED 0-3
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NET gpio<0> LOC = G5; #GPLED0
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NET gpio<1> LOC = G6; #GPLED1
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NET gpio<2> LOC = A11; #GPLED2
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NET gpio<3> LOC = A12; #GPLED3
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# North-East-South-West-Center LEDs
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NET gpio<4> LOC = C6; # C LED
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NET gpio<5> LOC = F9; # W LED
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NET gpio<6> LOC = A5; # S LED
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NET gpio<7> LOC = E10; # E LED
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NET gpio<8> LOC = E2; # N LED
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# North-East-South-West-Center Buttons
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NET gpio<9> LOC = B6; # C Button
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NET gpio<10> LOC = E9; # W Button
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NET gpio<11> LOC = A6; # S Button
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NET gpio<12> LOC = F10; # E Button
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NET gpio<13> LOC = E7; # N Button
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# Dip Switches 1-8
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NET gpio<14> LOC = U24; # DIP SW 8
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NET gpio<15> LOC = U25; # DIP SW 7
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NET gpio<16> LOC = V23; # DIP SW 6
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NET gpio<17> LOC = U23; # DIP SW 5
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NET gpio<18> LOC = U26; # DIP SW 4
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NET gpio<19> LOC = T26; # DIP SW 3
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NET gpio<20> LOC = R19; # DIP SW 2
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NET gpio<21> LOC = R20; # DIP SW 1
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NET gpio<14> IOSTANDARD = LVCMOS33;
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NET gpio<15> IOSTANDARD = LVCMOS33;
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NET gpio<16> IOSTANDARD = LVCMOS33;
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NET gpio<17> IOSTANDARD = LVCMOS33;
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NET gpio<18> IOSTANDARD = LVCMOS33;
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NET gpio<19> IOSTANDARD = LVCMOS33;
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NET gpio<20> IOSTANDARD = LVCMOS33;
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NET gpio<21> IOSTANDARD = LVCMOS33;
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#SMA Connectors
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NET gpio<22> LOC = C12; # SMA_IN_N
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NET gpio<23> LOC = C13; # SMA_IN_P
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NET gpio<24> LOC = D7; # SMA_OUT_N
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NET gpio<25> LOC = D8; # SMA_OUT_P
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NET gpio<26> LOC = AD12;# USERCLK
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NET gpio<26> IOSTANDARD = LVCMOS33;
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NET "gpio<*>" PULLDOWN;
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NET "gpio<*>" TIG;
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NET "gpio<*>" SLEW = SLOW;
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NET "gpio<*>" DRIVE = 2;
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NET "gpio<22>" SLEW = FAST;
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NET "gpio<22>" DRIVE = 12;
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NET "gpio<23>" SLEW = FAST;
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NET "gpio<23>" DRIVE = 12;
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NET "gpio<24>" SLEW = FAST;
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NET "gpio<24>" DRIVE = 12;
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NET "gpio<25>" SLEW = FAST;
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NET "gpio<25>" DRIVE = 12;
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NET "gpio2_d_out<*>" TIG;
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NET "gpio2_t_out<*>" TIG;
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NET "gpio2_in<*>" TIG;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for PS/2 Ports
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#------------------------------------------------------------------------------
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#Keyboard
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NET ps2_keyb_clk LOC = D2;
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NET ps2_keyb_clk SLEW = SLOW;
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NET ps2_keyb_clk DRIVE = 2;
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NET ps2_keyb_clk TIG;
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NET ps2_keyb_data LOC = G9;
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NET ps2_keyb_data SLEW = SLOW;
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NET ps2_keyb_data DRIVE = 2;
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NET ps2_keyb_data TIG;
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#Mouse
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NET ps2_mouse_clk LOC = B14;
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NET ps2_mouse_clk SLEW = SLOW;
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NET ps2_mouse_clk DRIVE = 2;
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NET ps2_mouse_clk TIG;
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NET ps2_mouse_data LOC = C14;
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NET ps2_mouse_data SLEW = SLOW;
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NET ps2_mouse_data DRIVE = 2;
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NET ps2_mouse_data TIG;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for IIC Controller
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#------------------------------------------------------------------------------
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NET iic_scl LOC = A17;
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NET iic_sda LOC = B17;
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NET iic_scl SLEW = SLOW;
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NET iic_scl DRIVE = 6;
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NET iic_scl TIG;
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NET iic_sda SLEW = SLOW;
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NET iic_sda DRIVE = 6;
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NET iic_sda TIG;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for AC97 Sound Controller
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#------------------------------------------------------------------------------
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NET ac97_bit_clk LOC = AE10;
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NET ac97_bit_clk IOSTANDARD = LVCMOS33;
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NET ac97_bit_clk PERIOD = 80;
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NET ac97_sdata_in LOC = AD16;
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NET ac97_sdata_in IOSTANDARD = LVCMOS33;
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NET ac97_reset_n LOC = AD10;
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NET ac97_reset_n IOSTANDARD = LVCMOS33;
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NET ac97_reset_n TIG;
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NET ac97_sdata_out LOC = C8;
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NET ac97_sync LOC = D9;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for System ACE MPU / USB
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#------------------------------------------------------------------------------
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NET sysace_clk_in LOC = AF11;
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NET sysace_clk_in IOSTANDARD = LVCMOS33;
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NET sysace_clk_in TNM_NET = "sysace_clk_in";
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# Leave 1 ns margin
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TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
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NET sace_usb_a<0> LOC = U22;
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NET sace_usb_a<1> LOC = Y10;
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NET sace_usb_a<2> LOC = AA10;
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NET sace_usb_a<3> LOC = AC7;
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NET sace_usb_a<4> LOC = Y7;
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NET sace_usb_a<5> LOC = AA9;
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NET sace_usb_a<6> LOC = Y9;
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NET sace_usb_a<*> IOSTANDARD = LVCMOS33;
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NET sace_usb_a<*> SLEW = FAST;
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NET sace_usb_a<*> DRIVE = 8;
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NET sace_mpce LOC = AD5;
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NET sace_mpce IOSTANDARD = LVCMOS33;
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NET sace_mpce SLEW = FAST;
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NET sace_mpce DRIVE = 8;
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NET sace_usb_d<0> LOC = AB7;
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NET sace_usb_d<1> LOC = AC9;
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NET sace_usb_d<2> LOC = AB9;
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NET sace_usb_d<3> LOC = AE6;
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NET sace_usb_d<4> LOC = AD6;
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NET sace_usb_d<5> LOC = AF9;
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NET sace_usb_d<6> LOC = AE9;
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NET sace_usb_d<7> LOC = AD8;
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NET sace_usb_d<8> LOC = AC8;
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NET sace_usb_d<9> LOC = AF4;
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NET sace_usb_d<10> LOC = AE4;
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NET sace_usb_d<11> LOC = AD3;
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NET sace_usb_d<12> LOC = AC3;
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NET sace_usb_d<13> LOC = AF6;
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NET sace_usb_d<14> LOC = AF5;
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NET sace_usb_d<15> LOC = AA7;
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NET sace_usb_d<*> IOSTANDARD = LVCMOS33;
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NET sace_usb_d<*> SLEW = FAST;
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NET sace_usb_d<*> DRIVE = 8;
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NET sace_usb_d<*> PULLDOWN;
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NET sace_usb_oen LOC = AA8;
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NET sace_usb_oen IOSTANDARD = LVCMOS33;
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NET sace_usb_oen SLEW = FAST;
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NET sace_usb_oen DRIVE = 8;
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NET sace_usb_wen LOC = Y8;
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NET sace_usb_wen IOSTANDARD = LVCMOS33;
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NET sace_usb_wen SLEW = FAST;
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NET sace_usb_wen DRIVE = 8;
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NET sysace_mpirq LOC = AD4;
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NET sysace_mpirq IOSTANDARD = LVCMOS33;
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NET sysace_mpirq TIG;
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NET sysace_mpirq PULLDOWN;
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NET usb_csn LOC = AF10;
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NET usb_csn IOSTANDARD = LVCMOS33;
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NET usb_csn SLEW = FAST;
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NET usb_csn DRIVE = 8;
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NET usb_hpi_reset_n LOC = A7;
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NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
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NET usb_hpi_reset_n TIG;
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NET usb_hpi_int LOC = V5;
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NET usb_hpi_int IOSTANDARD = LVCMOS33;
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NET usb_hpi_int TIG;
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NET usb_hpi_int PULLDOWN;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for DDR Controllers
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#------------------------------------------------------------------------------
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NET ddr_ad<0> LOC = C26; # DDR_A0
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NET ddr_ad<1> LOC = E17; # DDR_A1
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NET ddr_ad<2> LOC = D18; # DDR_A2
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NET ddr_ad<3> LOC = C19; # DDR_A3
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NET ddr_ad<4> LOC = F17; # DDR_A4
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NET ddr_ad<5> LOC = B18; # DDR_A5
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NET ddr_ad<6> LOC = B20; # DDR_A6
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NET ddr_ad<7> LOC = C20; # DDR_A7
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NET ddr_ad<8> LOC = D20; # DDR_A8
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NET ddr_ad<9> LOC = C21; # DDR_A9
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NET ddr_ad<10> LOC = A18; # DDR_A10
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NET ddr_ad<11> LOC = B21; # DDR_A11
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NET ddr_ad<12> LOC = A24; # DDR_A12
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NET ddr_ba<0> LOC = B12; # DDR_BA0
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NET ddr_ba<1> LOC = A16; # DDR_BA1
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NET ddr_casb LOC = F23; # DDR_CAS_N
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NET ddr_cke LOC = G22; # DDR_CKE
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NET ddr_csb LOC = G21; # DDR_CS_N
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NET ddr_rasb LOC = F24; # DDR_RAS_N
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NET ddr_web LOC = A23; # DDR_WE_N
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NET ddr_clk LOC = A10; # DDR_CK1_P
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NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
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NET ddr_clkb LOC = B10; # DDR_CK1_N
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NET ddr_dm<0> LOC = G19; # DDR_DM0
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NET ddr_dm<1> LOC = G24; # DDR_DM1
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NET ddr_dm<2> LOC = G20; # DDR_DM2
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NET ddr_dm<3> LOC = C22; # DDR_DM3
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NET ddr_dqs<0> LOC = D25; # DDR_DQS0
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NET ddr_dqs<1> LOC = G18; # DDR_DQS1
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NET ddr_dqs<2> LOC = G17; # DDR_DQS2
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NET ddr_dqs<3> LOC = D26; # DDR_DQS3
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NET ddr_dq<0> LOC = H20; # DDR_D0
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NET ddr_dq<1> LOC = E23; # DDR_D1
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NET ddr_dq<2> LOC = H26; # DDR_D2
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NET ddr_dq<3> LOC = H22; # DDR_D3
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NET ddr_dq<4> LOC = E25; # DDR_D4
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NET ddr_dq<5> LOC = E26; # DDR_D5
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NET ddr_dq<6> LOC = F26; # DDR_D6
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NET ddr_dq<7> LOC = E24; # DDR_D7
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NET ddr_dq<8> LOC = E20; # DDR_D8
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NET ddr_dq<9> LOC = A22; # DDR_D9
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298 |
|
|
NET ddr_dq<10> LOC = C23; # DDR_D10
|
299 |
|
|
NET ddr_dq<11> LOC = C24; # DDR_D11
|
300 |
|
|
NET ddr_dq<12> LOC = A20; # DDR_D12
|
301 |
|
|
NET ddr_dq<13> LOC = A21; # DDR_D13
|
302 |
|
|
NET ddr_dq<14> LOC = D24; # DDR_D14
|
303 |
|
|
NET ddr_dq<15> LOC = E18; # DDR_D15
|
304 |
|
|
NET ddr_dq<16> LOC = F18; # DDR_D16
|
305 |
|
|
NET ddr_dq<17> LOC = A19; # DDR_D17
|
306 |
|
|
NET ddr_dq<18> LOC = F19; # DDR_D18
|
307 |
|
|
NET ddr_dq<19> LOC = B23; # DDR_D19
|
308 |
|
|
NET ddr_dq<20> LOC = E21; # DDR_D20
|
309 |
|
|
NET ddr_dq<21> LOC = D22; # DDR_D21
|
310 |
|
|
NET ddr_dq<22> LOC = D23; # DDR_D22
|
311 |
|
|
NET ddr_dq<23> LOC = B24; # DDR_D23
|
312 |
|
|
NET ddr_dq<24> LOC = E22; # DDR_D24
|
313 |
|
|
NET ddr_dq<25> LOC = F20; # DDR_D25
|
314 |
|
|
NET ddr_dq<26> LOC = H23; # DDR_D26
|
315 |
|
|
NET ddr_dq<27> LOC = G25; # DDR_D27
|
316 |
|
|
NET ddr_dq<28> LOC = G26; # DDR_D28
|
317 |
|
|
NET ddr_dq<29> LOC = H25; # DDR_D29
|
318 |
|
|
NET ddr_dq<30> LOC = H24; # DDR_D30
|
319 |
|
|
NET ddr_dq<31> LOC = H21; # DDR_D31
|
320 |
|
|
|
321 |
|
|
NET ddr_ad<*> IOSTANDARD = SSTL2_I;
|
322 |
|
|
NET ddr_ba<*> IOSTANDARD = SSTL2_I;
|
323 |
|
|
NET ddr_casb IOSTANDARD = SSTL2_I;
|
324 |
|
|
NET ddr_cke IOSTANDARD = SSTL2_I;
|
325 |
|
|
NET ddr_clk IOSTANDARD = SSTL2_I;
|
326 |
|
|
NET ddr_clk_fb IOSTANDARD = LVCMOS25;
|
327 |
|
|
NET ddr_clkb IOSTANDARD = SSTL2_I;
|
328 |
|
|
NET ddr_casb IOSTANDARD = SSTL2_I;
|
329 |
|
|
NET ddr_csb IOSTANDARD = SSTL2_I;
|
330 |
|
|
NET ddr_rasb IOSTANDARD = SSTL2_I;
|
331 |
|
|
NET ddr_web IOSTANDARD = SSTL2_I;
|
332 |
|
|
|
333 |
|
|
NET ddr_dqs<*> IOSTANDARD = SSTL2_II;
|
334 |
|
|
NET ddr_dm<*> IOSTANDARD = SSTL2_II;
|
335 |
|
|
NET ddr_dq<*> IOSTANDARD = SSTL2_II;
|
336 |
|
|
|
337 |
|
|
// Timing Constraint for DDR Feedback Clock
|
338 |
|
|
NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
|
339 |
|
|
TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
|
340 |
|
|
|
341 |
|
|
#------------------------------------------------------------------------------
|
342 |
|
|
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
|
343 |
|
|
#------------------------------------------------------------------------------
|
344 |
|
|
|
345 |
|
|
NET tft_lcd_b<0> LOC = L26; # VGA_B2
|
346 |
|
|
NET tft_lcd_b<0> IOSTANDARD = LVCMOS33;
|
347 |
|
|
NET tft_lcd_b<1> LOC = C5; # VGA_B3
|
348 |
|
|
NET tft_lcd_b<2> LOC = C7; # VGA_B4
|
349 |
|
|
NET tft_lcd_b<3> LOC = B7; # VGA_B5
|
350 |
|
|
NET tft_lcd_b<4> LOC = G8; # VGA_B6
|
351 |
|
|
NET tft_lcd_b<5> LOC = F8; # VGA_B7
|
352 |
|
|
NET tft_lcd_b<*> SLEW = FAST;
|
353 |
|
|
NET tft_lcd_b<*> DRIVE = 8;
|
354 |
|
|
|
355 |
|
|
NET tft_lcd_clk LOC = AF8;
|
356 |
|
|
NET tft_lcd_clk IOSTANDARD = LVDCI_33;
|
357 |
|
|
NET tft_lcd_clk SLEW = FAST;
|
358 |
|
|
NET tft_lcd_clk DRIVE = 8;
|
359 |
|
|
|
360 |
|
|
NET tft_lcd_g<0> LOC = M20; # VGA_G2
|
361 |
|
|
NET tft_lcd_g<0> IOSTANDARD = LVCMOS33;
|
362 |
|
|
NET tft_lcd_g<1> LOC = E4; # VGA_G3
|
363 |
|
|
NET tft_lcd_g<2> LOC = D3; # VGA_G4
|
364 |
|
|
NET tft_lcd_g<3> LOC = H7; # VGA_G5
|
365 |
|
|
NET tft_lcd_g<4> LOC = H8; # VGA_G6
|
366 |
|
|
NET tft_lcd_g<5> LOC = C1; # VGA_G7
|
367 |
|
|
NET tft_lcd_g<*> SLEW = FAST;
|
368 |
|
|
NET tft_lcd_g<*> DRIVE = 8;
|
369 |
|
|
|
370 |
|
|
NET tft_lcd_hsync LOC = C10;
|
371 |
|
|
NET tft_lcd_hsync SLEW = FAST;
|
372 |
|
|
NET tft_lcd_hsync DRIVE = 8;
|
373 |
|
|
|
374 |
|
|
NET tft_lcd_r<0> LOC = N25; #VGA_R2
|
375 |
|
|
NET tft_lcd_r<0> IOSTANDARD = LVCMOS33;
|
376 |
|
|
NET tft_lcd_r<1> LOC = C2; #VGA_R3
|
377 |
|
|
NET tft_lcd_r<2> LOC = G7; #VGA_R4
|
378 |
|
|
NET tft_lcd_r<3> LOC = F7; #VGA_R5
|
379 |
|
|
NET tft_lcd_r<4> LOC = E5; #VGA_R6
|
380 |
|
|
NET tft_lcd_r<5> LOC = E6; #VGA_R7
|
381 |
|
|
NET tft_lcd_r<*> SLEW = FAST;
|
382 |
|
|
NET tft_lcd_r<*> DRIVE = 8;
|
383 |
|
|
|
384 |
|
|
NET tft_lcd_vsync LOC = A8;
|
385 |
|
|
NET tft_lcd_vsync SLEW = FAST;
|
386 |
|
|
NET tft_lcd_vsync DRIVE = 8;
|
387 |
|
|
|
388 |
|
|
TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
|
389 |
|
|
TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
|
390 |
|
|
|
391 |
|
|
////////////////////////////////////////////////////////////////////////////
|
392 |
|
|
// Misc Board Signals
|
393 |
|
|
////////////////////////////////////////////////////////////////////////////
|
394 |
|
|
|
395 |
|
|
NET plb_error LOC = L24;
|
396 |
|
|
NET plb_error IOSTANDARD = LVCMOS33;
|
397 |
|
|
NET plb_error TIG;
|
398 |
|
|
NET opb_error LOC = V6;
|
399 |
|
|
NET opb_error IOSTANDARD = LVCMOS33;
|
400 |
|
|
NET opb_error TIG;
|
401 |
|
|
|
402 |
|
|
#------------------------------------------------------------------------------
|
403 |
|
|
# IO Pad Location Constraints / Properties for Ethernet
|
404 |
|
|
#------------------------------------------------------------------------------
|
405 |
|
|
|
406 |
|
|
NET phy_col LOC = E3;
|
407 |
|
|
NET phy_crs LOC = D5;
|
408 |
|
|
NET phy_dv LOC = A9;
|
409 |
|
|
NET phy_rx_clk LOC = B15;
|
410 |
|
|
NET phy_rx_data<3> LOC = C4;
|
411 |
|
|
NET phy_rx_data<2> LOC = D4;
|
412 |
|
|
NET phy_rx_data<1> LOC = E1;
|
413 |
|
|
NET phy_rx_data<0> LOC = F1;
|
414 |
|
|
|
415 |
|
|
NET phy_rx_er LOC = B9;
|
416 |
|
|
NET phy_tx_clk LOC = C15;
|
417 |
|
|
NET phy_mii_clk LOC = D1;
|
418 |
|
|
NET phy_mii_int_n LOC = H4;
|
419 |
|
|
NET phy_rst_n LOC = D10;
|
420 |
|
|
NET phy_tx_data<3> LOC = G1;
|
421 |
|
|
NET phy_tx_data<2> LOC = H3;
|
422 |
|
|
NET phy_tx_data<1> LOC = H2;
|
423 |
|
|
NET phy_tx_data<0> LOC = H1;
|
424 |
|
|
NET phy_tx_en LOC = F4;
|
425 |
|
|
NET phy_tx_er LOC = F3;
|
426 |
|
|
NET phy_mii_data LOC = G4;
|
427 |
|
|
|
428 |
|
|
NET phy_mii_int_n PULLUP;
|
429 |
|
|
|
430 |
|
|
NET phy_mii_int_n TIG;
|
431 |
|
|
NET phy_rst_n TIG;
|
432 |
|
|
|
433 |
|
|
# Timing Constraints (these are recommended in documentation and
|
434 |
|
|
# are unaltered except for the TIG)
|
435 |
|
|
NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
|
436 |
|
|
NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
|
437 |
|
|
TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
|
438 |
|
|
TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
|
439 |
|
|
|
440 |
|
|
NET "phy_tx_clk" MAXSKEW= 1.0 ns;
|
441 |
|
|
NET "phy_rx_clk" MAXSKEW= 1.0 ns;
|
442 |
|
|
NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
|
443 |
|
|
NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
|
444 |
|
|
|
445 |
|
|
NET "phy_rx_data<3>" IOBDELAY=NONE;
|
446 |
|
|
NET "phy_rx_data<2>" IOBDELAY=NONE;
|
447 |
|
|
NET "phy_rx_data<1>" IOBDELAY=NONE;
|
448 |
|
|
NET "phy_rx_data<0>" IOBDELAY=NONE;
|
449 |
|
|
NET "phy_dv" IOBDELAY=NONE;
|
450 |
|
|
NET "phy_rx_er" IOBDELAY=NONE;
|
451 |
|
|
NET "phy_crs" IOBDELAY=NONE;
|
452 |
|
|
NET "phy_col" IOBDELAY=NONE;
|
453 |
|
|
|
454 |
|
|
# Timing ignores (to specify unconstrained paths)
|
455 |
|
|
TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
|
456 |
|
|
TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
|
457 |
|
|
TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
|
458 |
|
|
TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
|
459 |
|
|
|
460 |
|
|
#------------------------------------------------------------------------------
|
461 |
|
|
# IO Pad Location Constraints / Properties for SRAM/FLASH
|
462 |
|
|
#------------------------------------------------------------------------------
|
463 |
|
|
|
464 |
|
|
NET sram_clk LOC = AF7;
|
465 |
|
|
NET sram_clk_fb LOC = AD17;
|
466 |
|
|
NET flash_a23 LOC = T21;
|
467 |
|
|
NET sram_flash_addr<22> LOC = U20;
|
468 |
|
|
NET sram_flash_addr<21> LOC = T19;
|
469 |
|
|
NET sram_flash_addr<20> LOC = AC5;
|
470 |
|
|
NET sram_flash_addr<19> LOC = AB5;
|
471 |
|
|
NET sram_flash_addr<18> LOC = AC4;
|
472 |
|
|
NET sram_flash_addr<17> LOC = AB4;
|
473 |
|
|
|
474 |
|
|
NET sram_flash_addr<16> LOC = AB3;
|
475 |
|
|
NET sram_flash_addr<15> LOC = AA4;
|
476 |
|
|
NET sram_flash_addr<14> LOC = AA3;
|
477 |
|
|
NET sram_flash_addr<13> LOC = W5;
|
478 |
|
|
NET sram_flash_addr<12> LOC = W6;
|
479 |
|
|
NET sram_flash_addr<11> LOC = W3;
|
480 |
|
|
NET sram_flash_addr<10> LOC = AF3;
|
481 |
|
|
NET sram_flash_addr<9> LOC = AE3;
|
482 |
|
|
NET sram_flash_addr<8> LOC = AD2;
|
483 |
|
|
NET sram_flash_addr<7> LOC = AD1;
|
484 |
|
|
NET sram_flash_addr<6> LOC = AC2;
|
485 |
|
|
NET sram_flash_addr<5> LOC = AC1;
|
486 |
|
|
NET sram_flash_addr<4> LOC = AB2;
|
487 |
|
|
NET sram_flash_addr<3> LOC = AB1;
|
488 |
|
|
NET sram_flash_addr<2> LOC = AA1;
|
489 |
|
|
NET sram_flash_addr<1> LOC = Y2;
|
490 |
|
|
NET sram_flash_addr<0> LOC = Y1;
|
491 |
|
|
NET sram_flash_data<31> LOC = F14;
|
492 |
|
|
NET sram_flash_data<30> LOC = F13;
|
493 |
|
|
NET sram_flash_data<29> LOC = F12;
|
494 |
|
|
NET sram_flash_data<28> LOC = F11;
|
495 |
|
|
NET sram_flash_data<27> LOC = F16;
|
496 |
|
|
NET sram_flash_data<26> LOC = F15;
|
497 |
|
|
NET sram_flash_data<25> LOC = D14;
|
498 |
|
|
NET sram_flash_data<24> LOC = D13;
|
499 |
|
|
NET sram_flash_data<23> LOC = D15;
|
500 |
|
|
NET sram_flash_data<22> LOC = E14;
|
501 |
|
|
NET sram_flash_data<21> LOC = C11;
|
502 |
|
|
NET sram_flash_data<20> LOC = D11;
|
503 |
|
|
NET sram_flash_data<19> LOC = D16;
|
504 |
|
|
NET sram_flash_data<18> LOC = C16;
|
505 |
|
|
NET sram_flash_data<17> LOC = E13;
|
506 |
|
|
NET sram_flash_data<16> LOC = D12;
|
507 |
|
|
NET sram_flash_data<15> LOC = AA14;
|
508 |
|
|
NET sram_flash_data<14> LOC = AB14;
|
509 |
|
|
NET sram_flash_data<13> LOC = AC12;
|
510 |
|
|
NET sram_flash_data<12> LOC = AC11;
|
511 |
|
|
NET sram_flash_data<11> LOC = AA16;
|
512 |
|
|
NET sram_flash_data<10> LOC = AA15;
|
513 |
|
|
NET sram_flash_data<9> LOC = AB13;
|
514 |
|
|
NET sram_flash_data<8> LOC = AA13;
|
515 |
|
|
NET sram_flash_data<7> LOC = AC14;
|
516 |
|
|
NET sram_flash_data<6> LOC = AD14;
|
517 |
|
|
NET sram_flash_data<5> LOC = AA12;
|
518 |
|
|
NET sram_flash_data<4> LOC = AA11;
|
519 |
|
|
NET sram_flash_data<3> LOC = AC16;
|
520 |
|
|
NET sram_flash_data<2> LOC = AC15;
|
521 |
|
|
NET sram_flash_data<1> LOC = AC13;
|
522 |
|
|
NET sram_flash_data<0> LOC = AD13;
|
523 |
|
|
NET sram_cen LOC = V7;
|
524 |
|
|
NET sram_flash_oe_n LOC = AC6;
|
525 |
|
|
NET sram_flash_we_n LOC = AB6;
|
526 |
|
|
NET sram_bw<3> LOC = Y3; #Y4;
|
527 |
|
|
NET sram_bw<2> LOC = Y4; #Y3;
|
528 |
|
|
NET sram_bw<1> LOC = Y5; #Y6;
|
529 |
|
|
NET sram_bw<0> LOC = Y6; #Y5;
|
530 |
|
|
NET flash_ce LOC = W7;
|
531 |
|
|
NET sram_adv_ld_n LOC = W4;
|
532 |
|
|
NET sram_mode LOC = V26;
|
533 |
|
|
|
534 |
|
|
NET sram_clk IOSTANDARD = LVCMOS33;
|
535 |
|
|
NET sram_clk DRIVE = 16;
|
536 |
|
|
NET sram_clk SLEW = FAST;
|
537 |
|
|
NET sram_clk_fb IOSTANDARD = LVCMOS33;
|
538 |
|
|
|
539 |
|
|
NET flash_a23 IOSTANDARD = LVDCI_33;
|
540 |
|
|
NET flash_a23 SLEW = FAST;
|
541 |
|
|
NET flash_a23 DRIVE = 8;
|
542 |
|
|
|
543 |
|
|
NET sram_mode IOSTANDARD = LVDCI_33;
|
544 |
|
|
NET sram_mode SLEW = FAST;
|
545 |
|
|
NET sram_mode DRIVE = 8;
|
546 |
|
|
|
547 |
|
|
NET sram_flash_addr<*> IOSTANDARD = LVDCI_33;
|
548 |
|
|
NET sram_flash_addr<*> SLEW = FAST;
|
549 |
|
|
NET sram_flash_addr<*> DRIVE = 8;
|
550 |
|
|
|
551 |
|
|
NET sram_flash_data<*> IOSTANDARD = LVCMOS33;
|
552 |
|
|
NET sram_flash_data<*> DRIVE = 12;
|
553 |
|
|
NET sram_flash_data<*> SLEW = FAST;
|
554 |
|
|
NET sram_flash_data<*> PULLDOWN;
|
555 |
|
|
|
556 |
|
|
NET sram_flash_oe_n IOSTANDARD = LVDCI_33;
|
557 |
|
|
NET sram_flash_oe_n SLEW = FAST;
|
558 |
|
|
NET sram_flash_oe_n DRIVE = 8;
|
559 |
|
|
|
560 |
|
|
NET sram_flash_we_n IOSTANDARD = LVDCI_33;
|
561 |
|
|
NET sram_flash_we_n SLEW = FAST;
|
562 |
|
|
NET sram_flash_we_n DRIVE = 8;
|
563 |
|
|
|
564 |
|
|
NET sram_bw<*> IOSTANDARD = LVDCI_33;
|
565 |
|
|
NET sram_bw<*> SLEW = FAST;
|
566 |
|
|
NET sram_bw<*> DRIVE = 8;
|
567 |
|
|
|
568 |
|
|
NET flash_ce IOSTANDARD = LVDCI_33;
|
569 |
|
|
NET flash_ce SLEW = FAST;
|
570 |
|
|
NET flash_ce DRIVE = 8;
|
571 |
|
|
|
572 |
|
|
NET sram_cen IOSTANDARD = LVDCI_33;
|
573 |
|
|
NET sram_cen SLEW = FAST;
|
574 |
|
|
NET sram_cen DRIVE = 8;
|
575 |
|
|
|
576 |
|
|
NET sram_adv_ld_n IOSTANDARD = LVDCI_33;
|
577 |
|
|
NET sram_adv_ld_n SLEW = FAST;
|
578 |
|
|
NET sram_adv_ld_n DRIVE = 8;
|
579 |
|
|
|
580 |
|
|
#------------------------------------------------------------------------------
|
581 |
|
|
# IO Pad Location Constraints / Properties for Expansion Header GPIO
|
582 |
|
|
#------------------------------------------------------------------------------
|
583 |
|
|
|
584 |
|
|
NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64
|
585 |
|
|
NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62
|
586 |
|
|
NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8
|
587 |
|
|
NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58
|
588 |
|
|
NET gpio_exp_hdr1<27> LOC = W20; # HDR1_44
|
589 |
|
|
NET gpio_exp_hdr1<26> LOC = W21; # HDR1_48
|
590 |
|
|
NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14
|
591 |
|
|
NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20
|
592 |
|
|
NET gpio_exp_hdr1<23> LOC = W22; # HDR1_46
|
593 |
|
|
NET gpio_exp_hdr1<22> LOC = V21; # HDR1_56
|
594 |
|
|
NET gpio_exp_hdr1<21> LOC = V22; # HDR1_54
|
595 |
|
|
NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16
|
596 |
|
|
NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18
|
597 |
|
|
NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34
|
598 |
|
|
NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6
|
599 |
|
|
NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30
|
600 |
|
|
NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4
|
601 |
|
|
NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24
|
602 |
|
|
NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60
|
603 |
|
|
NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10
|
604 |
|
|
NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22
|
605 |
|
|
NET gpio_exp_hdr1<10> LOC = Y25; # HDR1_40
|
606 |
|
|
NET gpio_exp_hdr1<9> LOC = Y26; # HDR1_38
|
607 |
|
|
NET gpio_exp_hdr1<8> LOC = W26; # HDR1_50
|
608 |
|
|
NET gpio_exp_hdr1<7> LOC = AB23; # HDR1_12
|
609 |
|
|
NET gpio_exp_hdr1<6> LOC = Y24; # HDR1_26
|
610 |
|
|
NET gpio_exp_hdr1<5> LOC = AB24; # HDR1_32
|
611 |
|
|
NET gpio_exp_hdr1<4> LOC = W25; # HDR1_52
|
612 |
|
|
NET gpio_exp_hdr1<3> LOC = AC24; # HDR1_2
|
613 |
|
|
NET gpio_exp_hdr1<2> LOC = AC25; # HDR1_36
|
614 |
|
|
NET gpio_exp_hdr1<1> LOC = V20; # HDR1_42
|
615 |
|
|
NET gpio_exp_hdr1<0> LOC = AA24; # HDR1_28
|
616 |
|
|
NET gpio_exp_hdr1<*> TIG;
|
617 |
|
|
NET gpio_exp_hdr1<*> PULLDOWN;
|
618 |
|
|
|
619 |
|
|
NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40
|
620 |
|
|
NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38
|
621 |
|
|
NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32
|
622 |
|
|
NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30
|
623 |
|
|
NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44
|
624 |
|
|
NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42
|
625 |
|
|
NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24
|
626 |
|
|
NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22
|
627 |
|
|
NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48
|
628 |
|
|
NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46
|
629 |
|
|
NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64
|
630 |
|
|
NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62
|
631 |
|
|
NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16
|
632 |
|
|
NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14
|
633 |
|
|
NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36
|
634 |
|
|
NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34
|
635 |
|
|
NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52
|
636 |
|
|
NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50
|
637 |
|
|
NET gpio_exp_hdr2<13> LOC = Y17; # HDR2_56
|
638 |
|
|
NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54
|
639 |
|
|
NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60
|
640 |
|
|
NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58
|
641 |
|
|
NET gpio_exp_hdr2<9> LOC = Y22; # HDR2_8
|
642 |
|
|
NET gpio_exp_hdr2<8> LOC = Y23; # HDR2_6
|
643 |
|
|
NET gpio_exp_hdr2<7> LOC = W23; # HDR2_12
|
644 |
|
|
NET gpio_exp_hdr2<6> LOC = W24; # HDR2_10
|
645 |
|
|
NET gpio_exp_hdr2<5> LOC = Y20; # HDR2_20
|
646 |
|
|
NET gpio_exp_hdr2<4> LOC = Y21; # HDR2_18
|
647 |
|
|
NET gpio_exp_hdr2<3> LOC = Y19; # HDR2_28
|
648 |
|
|
NET gpio_exp_hdr2<2> LOC = W19; # HDR2_26
|
649 |
|
|
NET gpio_exp_hdr2<1> LOC = AA18; # HDR2_4
|
650 |
|
|
NET gpio_exp_hdr2<0> LOC = Y18; # HDR2_2
|
651 |
|
|
NET gpio_exp_hdr2<*> TIG;
|
652 |
|
|
NET gpio_exp_hdr2<*> PULLDOWN;
|
653 |
|
|
|
654 |
|
|
#------------------------------------------------------------------------------
|
655 |
|
|
# IO Pad Location Constraints / Properties for Character LCD GPIO
|
656 |
|
|
#------------------------------------------------------------------------------
|
657 |
|
|
|
658 |
|
|
NET gpio_char_lcd<6> LOC = AE13; # LCD_E
|
659 |
|
|
NET gpio_char_lcd<5> LOC = AC17; # LCD_RS
|
660 |
|
|
NET gpio_char_lcd<4> LOC = AB17; # LCD_RW
|
661 |
|
|
NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7
|
662 |
|
|
NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6
|
663 |
|
|
NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5
|
664 |
|
|
NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4
|
665 |
|
|
NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33;
|
666 |
|
|
NET gpio_char_lcd<*> TIG;
|
667 |
|
|
NET gpio_char_lcd<*> PULLDOWN;
|