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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [xilinx-ml501-xc5vlx50/] [system.ucf] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
#
2 
#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
3 
#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
4 
#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
5 
#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
6 
#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
7 
#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
8 
#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
9 
#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
10 
#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
11 
#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
12 
#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
13 
#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14 
#     FOR A PARTICULAR PURPOSE.
15 
#
16 
#     (c) Copyright 2006 Xilinx, Inc.
17 
#     All rights reserved.
18 
#
19 
 
20 
NET "sys_clk_s" TNM_NET = "sys_clk";
21 
#TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 10 ns HIGH 50 %;
22 
NET "sys_clk_in_200" TNM_NET = "sys_clk_in_200";
23 
TIMESPEC "TSSYSCLK200" = PERIOD "sys_clk_in_200" 5 ns HIGH 50 %;
24 
 
25 
NET sys_clk_in_p LOC = E16;
26 
NET sys_clk_in_n LOC = E17;
27 
NET sys_clk_in_p IOSTANDARD = LVDS_25;
28 
NET sys_clk_in_n IOSTANDARD = LVDS_25;
29 
INST *sys_clk_in_ibufds DIFF_TERM=TRUE;
30 
 
31 
NET sys_rst_pin LOC = T23 | IOSTANDARD = LVCMOS33 | PULLUP;
32 
 
33 
NET Interrupt TIG;
34 
 
35 
# Reset timing ignore - treat as async paths
36 
NET sys_rst_s TIG;
37 
NET opb_v20_0_OPB_Rst TIG;
38 
NET lmb_v10_1_OPB_Rst TIG;
39 
NET lmb_v10_0_OPB_Rst TIG;
40 
NET opb_v20_0_Debug_SYS_Rst TIG;
41 
NET plb_v34_0_PLB_Rst TIG;
42 
NET dcm_locked TIG;
43 
 
44 
////////////////////////////////////////////////////////////////////////////
45 
// Buttons, LEDs, Piezo, and DIP Switches
46 
////////////////////////////////////////////////////////////////////////////
47 
 
48 
# GPLED
49 
NET gpio<0>  LOC = E11; #GPLED7 (Rightmost - LSB)
50 
NET gpio<1>  LOC = E10; #GPLED6
51 
NET gpio<2>  LOC = E15; #GPLED5
52 
NET gpio<3>  LOC = D15; #GPLED4
53 
NET gpio<27> LOC = F12; #GPLED3
54 
NET gpio<28> LOC = E12; #GPLED2
55 
NET gpio<29> LOC = D14; #GPLED1
56 
NET gpio<30> LOC = E13; #GPLED0 (Leftmost - MSB)
57 
 
58 
NET gpio<0>  IOSTANDARD = LVCMOS25;
59 
NET gpio<1>  IOSTANDARD = LVCMOS25;
60 
NET gpio<2>  IOSTANDARD = LVCMOS25;
61 
NET gpio<3>  IOSTANDARD = LVCMOS25;
62 
NET gpio<27> IOSTANDARD = LVCMOS25;
63 
NET gpio<28> IOSTANDARD = LVCMOS25;
64 
NET gpio<29> IOSTANDARD = LVCMOS25;
65 
NET gpio<30> IOSTANDARD = LVCMOS25;
66 
# North-East-South-West-Center LEDs
67 
NET gpio<4>  LOC = T22;  # C LED
68 
NET gpio<5>  LOC = AA18; # W LED
69 
NET gpio<6>  LOC = AA8;  # S LED
70 
NET gpio<7>  LOC = Y18;  # E LED
71 
NET gpio<8>  LOC = Y8;   # N LED
72 
NET gpio<4> IOSTANDARD = LVCMOS33;
73 
NET gpio<5> IOSTANDARD = LVCMOS33;
74 
NET gpio<6> IOSTANDARD = LVCMOS33;
75 
NET gpio<7> IOSTANDARD = LVCMOS33;
76 
NET gpio<8> IOSTANDARD = LVCMOS33;
77 
# North-East-South-West-Center Buttons
78 
NET gpio<9>  LOC = B21; # C Button
79 
NET gpio<10> LOC = C21; # W Button
80 
NET gpio<11> LOC = B22; # S Button
81 
NET gpio<12> LOC = A23; # E Button
82 
NET gpio<13> LOC = A22; # N Button
83 
NET gpio<9>  IOSTANDARD = LVCMOS33;
84 
NET gpio<10> IOSTANDARD = LVCMOS33;
85 
NET gpio<11> IOSTANDARD = LVCMOS33;
86 
NET gpio<12> IOSTANDARD = LVCMOS33;
87 
NET gpio<13> IOSTANDARD = LVCMOS33;
88 
 
89 
# Dip Switches 1-8
90 
NET gpio<14> LOC = T7; # DIP SW 8
91 
NET gpio<15> LOC = U7; # DIP SW 7
92 
NET gpio<16> LOC = U5; # DIP SW 6
93 
NET gpio<17> LOC = U6; # DIP SW 5
94 
NET gpio<18> LOC = T5; # DIP SW 4
95 
NET gpio<19> LOC = T4; # DIP SW 3
96 
NET gpio<20> LOC = V3; # DIP SW 2
97 
NET gpio<21> LOC = U4; # DIP SW 1
98 
NET gpio<14> IOSTANDARD = LVCMOS18;
99 
NET gpio<15> IOSTANDARD = LVCMOS18;
100 
NET gpio<16> IOSTANDARD = LVCMOS18;
101 
NET gpio<17> IOSTANDARD = LVCMOS18;
102 
NET gpio<18> IOSTANDARD = LVCMOS18;
103 
NET gpio<19> IOSTANDARD = LVCMOS18;
104 
NET gpio<20> IOSTANDARD = LVCMOS18;
105 
NET gpio<21> IOSTANDARD = LVCMOS18;
106 
#SMA Connectors
107 
NET gpio<22> LOC = F10; # SMA_IN_N
108 
NET gpio<23> LOC = F9;  # SMA_IN_P
109 
NET gpio<24> LOC = F19; # SMA_OUT_N
110 
NET gpio<25> LOC = E18; # SMA_OUT_P
111 
NET gpio<26> LOC = AD8; # USERCLK
112 
NET gpio<22> IOSTANDARD = LVCMOS25;
113 
NET gpio<23> IOSTANDARD = LVCMOS25;
114 
NET gpio<24> IOSTANDARD = LVCMOS25;
115 
NET gpio<25> IOSTANDARD = LVCMOS25;
116 
NET gpio<26> IOSTANDARD = LVCMOS33;
117 
 
118 
NET "gpio<*>" PULLDOWN;
119 
NET "gpio<*>" TIG;
120 
NET "gpio<*>" SLEW = SLOW;
121 
NET "gpio<*>" DRIVE = 2;
122 
 
123 
NET "gpio<22>" SLEW = FAST;
124 
NET "gpio<22>" DRIVE = 12;
125 
NET "gpio<23>" SLEW = FAST;
126 
NET "gpio<23>" DRIVE = 12;
127 
NET "gpio<24>" SLEW = FAST;
128 
NET "gpio<24>" DRIVE = 12;
129 
NET "gpio<25>" SLEW = FAST;
130 
NET "gpio<25>" DRIVE = 12;
131 
 
132 
#NET  "gpio2_d_out<*>" TIG;
133 
#NET  "gpio2_t_out<*>" TIG;
134 
NET  "gpio2_in<*>" TIG;
135 
 
136 
NET  "piezo" LOC = V1;
137 
NET  "piezo" IOSTANDARD = LVCMOS18;
138 
NET  "piezo" TIG;
139 
 
140 
#------------------------------------------------------------------------------
141 
# IO Pad Location Constraints / Properties for PS/2 Ports
142 
#------------------------------------------------------------------------------
143 
 
144 
#Keyboard
145 
NET ps2_keyb_clk  LOC = J1;
146 
NET ps2_keyb_clk  SLEW = SLOW;
147 
NET ps2_keyb_clk  DRIVE = 2;
148 
NET ps2_keyb_clk  IOSTANDARD = LVCMOS18;
149 
NET ps2_keyb_clk  TIG;
150 
NET ps2_keyb_data LOC = H2;
151 
NET ps2_keyb_data SLEW = SLOW;
152 
NET ps2_keyb_data DRIVE = 2;
153 
NET ps2_keyb_data IOSTANDARD = LVCMOS18;
154 
NET ps2_keyb_data TIG;
155 
 
156 
#Mouse
157 
NET ps2_mouse_clk  LOC = L2;
158 
NET ps2_mouse_clk  SLEW = SLOW;
159 
NET ps2_mouse_clk  DRIVE = 2;
160 
NET ps2_mouse_clk  IOSTANDARD = LVCMOS18;
161 
NET ps2_mouse_clk  TIG;
162 
NET ps2_mouse_data LOC = K1;
163 
NET ps2_mouse_data SLEW = SLOW;
164 
NET ps2_mouse_data DRIVE = 2;
165 
NET ps2_mouse_data IOSTANDARD = LVCMOS18;
166 
NET ps2_mouse_data TIG;
167 
 
168 
#------------------------------------------------------------------------------
169 
# IO Pad Location Constraints / Properties for IIC Controller
170 
#------------------------------------------------------------------------------
171 
 
172 
NET iic_scl    LOC = R20;
173 
NET iic_sda    LOC = T20;
174 
NET iic_scl    SLEW = SLOW;
175 
NET iic_scl    DRIVE = 6;
176 
NET iic_scl    TIG;
177 
NET iic_scl    IOSTANDARD = LVCMOS33;
178 
NET iic_sda    SLEW = SLOW;
179 
NET iic_sda    DRIVE = 6;
180 
NET iic_sda    TIG;
181 
NET iic_sda    IOSTANDARD = LVCMOS33;
182 
 
183 
NET ddr2_iic_scl  LOC = Y7;
184 
NET ddr2_iic_sda  LOC = AA7;
185 
NET ddr2_iic_scl  SLEW = SLOW;
186 
NET ddr2_iic_scl  DRIVE = 6;
187 
NET ddr2_iic_scl  TIG;
188 
NET ddr2_iic_scl  IOSTANDARD = LVCMOS18;
189 
NET ddr2_iic_sda  SLEW = SLOW;
190 
NET ddr2_iic_sda  DRIVE = 6;
191 
NET ddr2_iic_sda  TIG;
192 
NET ddr2_iic_sda  IOSTANDARD = LVCMOS18;
193 
 
194 
#------------------------------------------------------------------------------
195 
# IO Pad Location Constraints / Properties for System ACE MPU / USB
196 
#------------------------------------------------------------------------------
197 
 
198 
NET sysace_clk_in   LOC        = AB12;
199 
NET sysace_clk_in   IOSTANDARD = LVCMOS33;
200 
NET sysace_clk_in   TNM_NET    = "sysace_clk_in";
201 
# Leave 1 ns margin
202 
TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
203 
 
204 
NET sace_usb_a<0>   LOC        = N6;
205 
NET sace_usb_a<1>   LOC        = E5;
206 
NET sace_usb_a<2>   LOC        = F5;
207 
NET sace_usb_a<3>   LOC        = F4;
208 
NET sace_usb_a<4>   LOC        = J5;
209 
NET sace_usb_a<5>   LOC        = E7;
210 
NET sace_usb_a<6>   LOC        = G7;
211 
NET sace_usb_a<*>   IOSTANDARD = LVCMOS33;
212 
NET sace_usb_a<*>   SLEW       = FAST;
213 
NET sace_usb_a<*>   DRIVE      = 8;
214 
NET sace_mpce       LOC        = F7;
215 
NET sace_mpce       IOSTANDARD = LVCMOS33;
216 
NET sace_mpce       SLEW       = FAST;
217 
NET sace_mpce       DRIVE      = 8;
218 
NET sace_usb_d<0>   LOC        = M6;
219 
NET sace_usb_d<1>   LOC        = K5;
220 
NET sace_usb_d<2>   LOC        = L3;
221 
NET sace_usb_d<3>   LOC        = L4;
222 
NET sace_usb_d<4>   LOC        = L7;
223 
NET sace_usb_d<5>   LOC        = L5;
224 
NET sace_usb_d<6>   LOC        = H6;
225 
NET sace_usb_d<7>   LOC        = G5;
226 
NET sace_usb_d<8>   LOC        = M7;
227 
NET sace_usb_d<9>   LOC        = H7;
228 
NET sace_usb_d<10>  LOC        = J6;
229 
NET sace_usb_d<11>  LOC        = G4;
230 
NET sace_usb_d<12>  LOC        = K7;
231 
NET sace_usb_d<13>  LOC        = J4;
232 
NET sace_usb_d<14>  LOC        = H4;
233 
NET sace_usb_d<15>  LOC        = K6;
234 
NET sace_usb_d<*>   IOSTANDARD = LVCMOS33;
235 
NET sace_usb_d<*>   SLEW       = FAST;
236 
NET sace_usb_d<*>   DRIVE      = 8;
237 
NET sace_usb_d<*>   PULLDOWN;
238 
NET sace_usb_oen    LOC        = E6;
239 
NET sace_usb_oen    IOSTANDARD = LVCMOS33;
240 
NET sace_usb_oen    SLEW       = FAST;
241 
NET sace_usb_oen    DRIVE      = 8;
242 
NET sace_usb_wen    LOC        = M5;
243 
NET sace_usb_wen    IOSTANDARD = LVCMOS33;
244 
NET sace_usb_wen    SLEW       = FAST;
245 
NET sace_usb_wen    DRIVE      = 8;
246 
NET sysace_mpirq    LOC        = G6;
247 
NET sysace_mpirq    IOSTANDARD = LVCMOS33;
248 
NET sysace_mpirq    TIG;
249 
NET sysace_mpirq    PULLDOWN;
250 
 
251 
NET usb_csn         LOC        = N3;
252 
NET usb_csn         IOSTANDARD = LVCMOS33;
253 
NET usb_csn         SLEW       = FAST;
254 
NET usb_csn         DRIVE      = 8;
255 
NET usb_hpi_reset_n LOC        = P3;
256 
NET usb_hpi_reset_n IOSTANDARD = LVCMOS33;
257 
NET usb_hpi_reset_n TIG;
258 
NET usb_hpi_int     LOC        = M4;
259 
NET usb_hpi_int     IOSTANDARD = LVCMOS33;
260 
NET usb_hpi_int     TIG;
261 
NET usb_hpi_int     PULLDOWN;
262 
 
263 
////////////////////////////////////////////////////////////////////////////
264 
// Misc Board Signals
265 
////////////////////////////////////////////////////////////////////////////
266 
 
267 
NET plb_error LOC = N4; # Bus Error 1
268 
NET plb_error IOSTANDARD = LVCMOS33;
269 
NET plb_error TIG;
270 
NET opb_error LOC = P5; # Bus Error 2
271 
NET opb_error IOSTANDARD = LVCMOS33;
272 
NET opb_error TIG;
273 
 
274 
#------------------------------------------------------------------------------
275 
# IO Pad Location Constraints / Properties for Expansion Header GPIO
276 
#------------------------------------------------------------------------------
277 
 
278 
NET gpio_exp_hdr1<31> LOC = AB26; # HDR1_64
279 
NET gpio_exp_hdr1<30> LOC = AC26; # HDR1_62
280 
NET gpio_exp_hdr1<29> LOC = AA25; # HDR1_60
281 
NET gpio_exp_hdr1<28> LOC = P26;  # HDR1_58
282 
NET gpio_exp_hdr1<27> LOC = Y26; # HDR1_56
283 
NET gpio_exp_hdr1<26> LOC = Y25; # HDR1_54
284 
NET gpio_exp_hdr1<25> LOC = W26; # HDR1_52
285 
NET gpio_exp_hdr1<24> LOC = W25; # HDR1_50
286 
NET gpio_exp_hdr1<23> LOC = U25; # HDR1_48
287 
NET gpio_exp_hdr1<22> LOC = U24; # HDR1_46
288 
NET gpio_exp_hdr1<21> LOC = T25; # HDR1_44
289 
NET gpio_exp_hdr1<20> LOC = T24; # HDR1_42
290 
NET gpio_exp_hdr1<19> LOC = P24; # HDR1_40
291 
NET gpio_exp_hdr1<18> LOC = P25; # HDR1_38
292 
NET gpio_exp_hdr1<17> LOC = N26; # HDR1_36
293 
NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_34
294 
NET gpio_exp_hdr1<15> LOC = M24; # HDR1_32
295 
NET gpio_exp_hdr1<14> LOC = N24; # HDR1_30
296 
NET gpio_exp_hdr1<13> LOC = M25; # HDR1_28
297 
NET gpio_exp_hdr1<12> LOC = M26; # HDR1_26
298 
NET gpio_exp_hdr1<11> LOC = K25; # HDR1_24
299 
NET gpio_exp_hdr1<10> LOC = K26; # HDR1_22
300 
NET gpio_exp_hdr1<9>  LOC = L24; # HDR1_20
301 
NET gpio_exp_hdr1<8>  LOC = L25; # HDR1_18
302 
NET gpio_exp_hdr1<7>  LOC = M21; # HDR1_16
303 
NET gpio_exp_hdr1<6>  LOC = K21; # HDR1_14
304 
NET gpio_exp_hdr1<5>  LOC = K20; # HDR1_12
305 
NET gpio_exp_hdr1<4>  LOC = M22; # HDR1_10
306 
NET gpio_exp_hdr1<3>  LOC = H23; # HDR1_8
307 
NET gpio_exp_hdr1<2>  LOC = J21; # HDR1_6
308 
NET gpio_exp_hdr1<1>  LOC = J23; # HDR1_4
309 
NET gpio_exp_hdr1<0>  LOC = J20; # HDR1_2
310 
NET gpio_exp_hdr1<*> TIG;
311 
NET gpio_exp_hdr1<*> PULLDOWN;
312 
NET gpio_exp_hdr1<*> IOSTANDARD = LVCMOS25;
313 
 
314 
NET gpio_exp_hdr2<31> LOC = P21; # HDR2_64
315 
NET gpio_exp_hdr2<30> LOC = P20; # HDR2_62
316 
NET gpio_exp_hdr2<29> LOC = H24; # HDR2_60
317 
NET gpio_exp_hdr2<28> LOC = J24; # HDR2_58
318 
NET gpio_exp_hdr2<27> LOC = M20; # HDR2_56
319 
NET gpio_exp_hdr2<26> LOC = M19; # HDR2_54
320 
NET gpio_exp_hdr2<25> LOC = G24; # HDR2_52
321 
NET gpio_exp_hdr2<24> LOC = G25; # HDR2_50
322 
NET gpio_exp_hdr2<23> LOC = P23; # HDR2_48
323 
NET gpio_exp_hdr2<22> LOC = N23; # HDR2_46
324 
NET gpio_exp_hdr2<21> LOC = L20; # HDR2_44
325 
NET gpio_exp_hdr2<20> LOC = L19; # HDR2_42
326 
NET gpio_exp_hdr2<19> LOC = G26; # HDR2_40
327 
NET gpio_exp_hdr2<18> LOC = H26; # HDR2_38
328 
NET gpio_exp_hdr2<17> LOC = K23; # HDR2_36
329 
NET gpio_exp_hdr2<16> LOC = K22; # HDR2_34
330 
NET gpio_exp_hdr2<15> LOC = V26; # HDR2_32
331 
NET gpio_exp_hdr2<14> LOC = U26; # HDR2_30
332 
NET gpio_exp_hdr2<13> LOC = N22; # HDR2_28
333 
NET gpio_exp_hdr2<12> LOC = N21; # HDR2_26
334 
NET gpio_exp_hdr2<11> LOC = R22; # HDR2_24
335 
NET gpio_exp_hdr2<10> LOC = R23; # HDR2_22
336 
NET gpio_exp_hdr2<9>  LOC = J25; # HDR2_20
337 
NET gpio_exp_hdr2<8>  LOC = J26; # HDR2_18
338 
NET gpio_exp_hdr2<7>  LOC = P19; # HDR2_16
339 
NET gpio_exp_hdr2<6>  LOC = N19; # HDR2_14
340 
NET gpio_exp_hdr2<5>  LOC = G21; # HDR2_12
341 
NET gpio_exp_hdr2<4>  LOC = G22; # HDR2_10
342 
NET gpio_exp_hdr2<3>  LOC = E25; # HDR2_8
343 
NET gpio_exp_hdr2<2>  LOC = E26; # HDR2_6
344 
NET gpio_exp_hdr2<1>  LOC = F24; # HDR2_4
345 
NET gpio_exp_hdr2<0>  LOC = F25; # HDR2_2
346 
NET gpio_exp_hdr2<*> TIG;
347 
NET gpio_exp_hdr2<*> PULLDOWN;
348 
NET gpio_exp_hdr2<*> IOSTANDARD = LVCMOS25;
349 
 
350 
#------------------------------------------------------------------------------
351 
# IO Pad Location Constraints / Properties for Character LCD GPIO
352 
#------------------------------------------------------------------------------
353 
 
354 
NET gpio_char_lcd<6> LOC = P6; # LCD_E
355 
NET gpio_char_lcd<5> LOC = R7; # LCD_RS
356 
NET gpio_char_lcd<4> LOC = R5; # LCD_RW
357 
NET gpio_char_lcd<3> LOC = P4; # LCD_DB7
358 
NET gpio_char_lcd<2> LOC = R3; # LCD_DB6
359 
NET gpio_char_lcd<1> LOC = T3; # LCD_DB5
360 
NET gpio_char_lcd<0> LOC = R6; # LCD_DB4
361 
NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33;
362 
NET gpio_char_lcd<*> TIG;
363 
NET gpio_char_lcd<*> PULLDOWN;
364 
 
365 
#------------------------------------------------------------------------------
366 
# IO Pad Location Constraints / Properties for DDR Controllers
367 
#------------------------------------------------------------------------------
368 
 
369 
NET ddr2_ad<0>  LOC = Y5; # DDR_A0
370 
NET ddr2_ad<1>  LOC = Y6; # DDR_A1
371 
NET ddr2_ad<2>  LOC = W6; # DDR_A2
372 
NET ddr2_ad<3>  LOC = W5; # DDR_A3
373 
NET ddr2_ad<4>  LOC = V7; # DDR_A4
374 
NET ddr2_ad<5>  LOC = V6; # DDR_A5
375 
NET ddr2_ad<6>  LOC = Y3; # DDR_A6
376 
NET ddr2_ad<7>  LOC = W3; # DDR_A7
377 
NET ddr2_ad<8>  LOC = W4; # DDR_A8
378 
NET ddr2_ad<9>  LOC = V4; # DDR_A9
379 
NET ddr2_ad<10> LOC = AD3; # DDR_A10
380 
NET ddr2_ad<11> LOC = AD4; # DDR_A11
381 
NET ddr2_ad<12> LOC = AC3; # DDR_A12
382 
NET ddr2_ba<0>  LOC = AB5; # DDR_BA0
383 
NET ddr2_ba<1>  LOC = AB6; # DDR_BA1
384 
NET ddr2_casb   LOC = AE3; # DDR_CAS_N
385 
NET ddr2_cke<0> LOC = AA3; # DDR_CKE
386 
NET ddr2_cke<1> LOC = AB4; # DDR_CKE
387 
NET ddr2_csb<0>  LOC = AF3; # DDR_CS_N
388 
NET ddr2_csb<1>  LOC = AD6; # DDR_CS_N
389 
NET ddr2_rasb   LOC = AC6; # DDR_RAS_N
390 
NET ddr2_web    LOC = AB7; # DDR_WE_N
391 
NET ddr2_clk<0>    LOC = E2; # DDR_CK0_P
392 
NET ddr2_clkb<0>   LOC = E1; # DDR_CK0_N
393 
NET ddr2_clk<1>    LOC = P1; # DDR_CK1_P
394 
NET ddr2_clkb<1>   LOC = R1; # DDR_CK1_N
395 
NET ddr2_odt<0>  LOC =AE6; # DDR_ODT0
396 
NET ddr2_odt<1>  LOC =AE5; # DDR_ODT1
397 
 
398 
NET ddr2_dm<0>  LOC = B9; # DDR_DM0
399 
NET ddr2_dm<1>  LOC = A8; # DDR_DM1
400 
NET ddr2_dm<2>  LOC = C4; # DDR_DM2
401 
NET ddr2_dm<3>  LOC = F2; # DDR_DM3
402 
NET ddr2_dm<4>  LOC = AB1; # DDR_DM4
403 
NET ddr2_dm<5>  LOC = AF24; # DDR_DM5
404 
NET ddr2_dm<6>  LOC = AF22; # DDR_DM6
405 
NET ddr2_dm<7>  LOC = AF8; # DDR_DM7
406 
 
407 
NET ddr2_dqs<0>  LOC = B7; # DDR_DQS0
408 
NET ddr2_dqsb<0> LOC = A7; # DDR_DQSN0
409 
NET ddr2_dqs<1>  LOC = D5; # DDR_DQS1
410 
NET ddr2_dqsb<1> LOC = D6; # DDR_DQSN1
411 
NET ddr2_dqs<2>  LOC = C6; # DDR_DQS2
412 
NET ddr2_dqsb<2> LOC = C7; # DDR_DQSN2
413 
NET ddr2_dqs<3>  LOC = M1; # DDR_DQS3
414 
NET ddr2_dqsb<3> LOC = N1; # DDR_DQSN3
415 
NET ddr2_dqs<4>  LOC = T2; # DDR_DQS4
416 
NET ddr2_dqsb<4> LOC = R2; # DDR_DQSN4
417 
NET ddr2_dqs<5>  LOC = AF18; # DDR_DQS5
418 
NET ddr2_dqsb<5> LOC = AE18; # DDR_DQSN5
419 
NET ddr2_dqs<6>  LOC = AF19; # DDR_DQS6
420 
NET ddr2_dqsb<6> LOC = AF20; # DDR_DQSN6
421 
NET ddr2_dqs<7>  LOC = AF17; # DDR_DQS7
422 
NET ddr2_dqsb<7> LOC = AE17; # DDR_DQSN7
423 
 
424 
NET ddr2_dq<0> LOC = C11; # DDR_D0
425 
NET ddr2_dq<1> LOC = C13; # DDR_D1
426 
NET ddr2_dq<2> LOC = A12; # DDR_D2
427 
NET ddr2_dq<3> LOC = C9; # DDR_D3
428 
NET ddr2_dq<4> LOC = D10; # DDR_D4
429 
NET ddr2_dq<5> LOC = C12; # DDR_D5
430 
NET ddr2_dq<6> LOC = B12; # DDR_D6
431 
NET ddr2_dq<7> LOC = A13; # DDR_D7
432 
NET ddr2_dq<8> LOC = A10; # DDR_D8
433 
NET ddr2_dq<9> LOC = A9; # DDR_D9
434 
NET ddr2_dq<10> LOC = B5; # DDR_D10
435 
NET ddr2_dq<11> LOC = D3; # DDR_D11
436 
NET ddr2_dq<12> LOC = B10; # DDR_D12
437 
NET ddr2_dq<13> LOC = B11; # DDR_D13
438 
NET ddr2_dq<14> LOC = B6; # DDR_D14
439 
NET ddr2_dq<15> LOC = B4; # DDR_D15
440 
NET ddr2_dq<16> LOC = C2; # DDR_D16
441 
NET ddr2_dq<17> LOC = A2; # DDR_D17
442 
NET ddr2_dq<18> LOC = D1; # DDR_D18
443 
NET ddr2_dq<19> LOC = B1; # DDR_D19
444 
NET ddr2_dq<20> LOC = C3; # DDR_D20
445 
NET ddr2_dq<21> LOC = A3; # DDR_D21
446 
NET ddr2_dq<22> LOC = C1; # DDR_D22
447 
NET ddr2_dq<23> LOC = B2; # DDR_D23
448 
NET ddr2_dq<24> LOC = F3; # DDR_D24
449 
NET ddr2_dq<25> LOC = G1; # DDR_D25
450 
NET ddr2_dq<26> LOC = G2; # DDR_D26
451 
NET ddr2_dq<27> LOC = H3; # DDR_D27
452 
NET ddr2_dq<28> LOC = E3; # DDR_D28
453 
NET ddr2_dq<29> LOC = H1; # DDR_D29
454 
NET ddr2_dq<30> LOC = K3; # DDR_D30
455 
NET ddr2_dq<31> LOC = J3; # DDR_D31
456 
 
457 
NET ddr2_dq<32> LOC = Y1; # DDR_D32
458 
NET ddr2_dq<33> LOC = Y2; # DDR_D33
459 
NET ddr2_dq<34> LOC = AC1; # DDR_D34
460 
NET ddr2_dq<35> LOC = AD1; # DDR_D35
461 
NET ddr2_dq<36> LOC = AA2; # DDR_D36
462 
NET ddr2_dq<37> LOC = AB2; # DDR_D37
463 
NET ddr2_dq<38> LOC = AC2; # DDR_D38
464 
NET ddr2_dq<39> LOC = AE1; # DDR_D39
465 
NET ddr2_dq<40> LOC = AD23; # DDR_D40
466 
NET ddr2_dq<41> LOC = AD26; # DDR_D41
467 
NET ddr2_dq<42> LOC = AF25; # DDR_D42
468 
NET ddr2_dq<43> LOC = AD25; # DDR_D43
469 
NET ddr2_dq<44> LOC = AD24; # DDR_D44
470 
NET ddr2_dq<45> LOC = AE26; # DDR_D45
471 
NET ddr2_dq<46> LOC = AE25; # DDR_D46
472 
NET ddr2_dq<47> LOC = AF23; # DDR_D47
473 
NET ddr2_dq<48> LOC = AD20; # DDR_D48
474 
NET ddr2_dq<49> LOC = AE20; # DDR_D49
475 
NET ddr2_dq<50> LOC = AF14; # DDR_D50
476 
NET ddr2_dq<51> LOC = AF12; # DDR_D51
477 
NET ddr2_dq<52> LOC = AD21; # DDR_D52
478 
NET ddr2_dq<53> LOC = AE21; # DDR_D53
479 
NET ddr2_dq<54> LOC = AF13; # DDR_D54
480 
NET ddr2_dq<55> LOC = AE12; # DDR_D55
481 
NET ddr2_dq<56> LOC = AE11; # DDR_D56
482 
NET ddr2_dq<57> LOC = AE10; # DDR_D57
483 
NET ddr2_dq<58> LOC = AF7; # DDR_D58
484 
NET ddr2_dq<59> LOC = AE7; # DDR_D59
485 
NET ddr2_dq<60> LOC = AF10; # DDR_D60
486 
NET ddr2_dq<61> LOC = AF9; # DDR_D61
487 
NET ddr2_dq<62> LOC = AE8; # DDR_D62
488 
NET ddr2_dq<63> LOC = AD9; # DDR_D63
489 
 
490 
NET ddr2_ad<*>   IOSTANDARD = SSTL18_II;
491 
NET ddr2_ba<*>   IOSTANDARD = SSTL18_II;
492 
NET ddr2_casb    IOSTANDARD = SSTL18_II;
493 
NET ddr2_cke<*>  IOSTANDARD = SSTL18_II;
494 
NET ddr2_clk<*>  IOSTANDARD = SSTL18_II;
495 
NET ddr2_clkb<*> IOSTANDARD = SSTL18_II;
496 
NET ddr2_casb    IOSTANDARD = SSTL18_II;
497 
NET ddr2_csb<*>  IOSTANDARD = SSTL18_II;
498 
NET ddr2_rasb    IOSTANDARD = SSTL18_II;
499 
NET ddr2_web     IOSTANDARD = SSTL18_II;
500 
NET ddr2_odt<*>  IOSTANDARD = SSTL18_II;
501 
 
502 
#NET ddr2_dqs<*>  IOSTANDARD = SSTL18_II_DCI;
503 
#NET ddr2_dqsb<*> IOSTANDARD = SSTL18_II_DCI;
504 
#NET ddr2_dm<*>   IOSTANDARD = SSTL18_II_DCI;
505 
#NET ddr2_dq<*>   IOSTANDARD = SSTL18_II_DCI;
506 
 
507 
NET ddr2_dqs<*>  IOSTANDARD = SSTL18_II;
508 
NET ddr2_dqsb<*> IOSTANDARD = SSTL18_II;
509 
NET ddr2_dm<*>   IOSTANDARD = SSTL18_II;
510 
NET ddr2_dq<*>   IOSTANDARD = SSTL18_II;
511 
 
512 
NET "ddr2_cal_clk"   TNM_NET = "ddr2_cal_clk";
513 
NET "ddr2_dev_clk_*" TNM_NET = "ddr2_dev_clk";
514 
TIMESPEC "TSCAL_DEV" = FROM "ddr2_cal_clk" TO "ddr2_dev_clk" TIG;
515 
TIMESPEC "TSDEV_CAL" = FROM "ddr2_dev_clk" TO "ddr2_cal_clk" TIG;
516 
 
517 
#------------------------------------------------------------------------------
518 
# IO Pad Location Constraints / Properties for UART
519 
#------------------------------------------------------------------------------
520 
 
521 
NET uart_RX LOC = AC7;
522 
NET uart_RX IOSTANDARD = LVCMOS33;
523 
NET uart_RX TIG;
524 
NET uart_TX LOC = AD14;
525 
NET uart_TX IOSTANDARD = LVCMOS33;
526 
NET uart_TX TIG;
527 
 
528 
#------------------------------------------------------------------------------
529 
# IO Pad Location Constraints / Properties for SRAM
530 
#------------------------------------------------------------------------------
531 
 
532 
NET sram_clk            LOC = U22;
533 
NET sram_clk_fb         LOC = AD15;
534 
NET sram_clk_fb         IOSTANDARD = LVCMOS33;
535 
NET sram_clk            IOSTANDARD = LVDCI_33;
536 
 
537 
NET sram_flash_addr<23> LOC = Y10;
538 
NET sram_flash_addr<22> LOC = Y11;
539 
NET sram_flash_addr<21> LOC = AA17;
540 
NET sram_flash_addr<20> LOC = AB17;
541 
NET sram_flash_addr<19> LOC = G14;
542 
NET sram_flash_addr<18> LOC = F13;
543 
NET sram_flash_addr<17> LOC = H14;
544 
NET sram_flash_addr<16> LOC = H13;
545 
NET sram_flash_addr<15> LOC = F15;
546 
NET sram_flash_addr<14> LOC = G15;
547 
NET sram_flash_addr<13> LOC = G12;
548 
NET sram_flash_addr<12> LOC = H12;
549 
NET sram_flash_addr<11> LOC = G16;
550 
NET sram_flash_addr<10> LOC = H16;
551 
NET sram_flash_addr<9>  LOC = H11;
552 
NET sram_flash_addr<8>  LOC = G11;
553 
NET sram_flash_addr<7>  LOC = H17;
554 
NET sram_flash_addr<6>  LOC = G17;
555 
NET sram_flash_addr<5>  LOC = G10;
556 
NET sram_flash_addr<4>  LOC = G9;
557 
NET sram_flash_addr<3>  LOC = G19;
558 
NET sram_flash_addr<2>  LOC = H18;
559 
NET sram_flash_addr<1>  LOC = H9;
560 
NET sram_flash_addr<0>  LOC = H8;
561 
NET sram_flash_addr<*>  IOSTANDARD = LVCMOS33;
562 
NET sram_flash_addr<*>  SLEW = FAST;
563 
NET sram_flash_addr<*>  DRIVE = 8;
564 
 
565 
NET sram_flash_data<31> LOC = AD18 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
566 
NET sram_flash_data<30> LOC = AC18 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
567 
NET sram_flash_data<29> LOC = AB10 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
568 
NET sram_flash_data<28> LOC = AB9  | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
569 
NET sram_flash_data<27> LOC = AC17 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
570 
NET sram_flash_data<26> LOC = AC16 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
571 
NET sram_flash_data<25> LOC = AC8  | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
572 
NET sram_flash_data<24> LOC = AC9  | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
573 
NET sram_flash_data<23> LOC = Y12  | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
574 
NET sram_flash_data<22> LOC = Y13  | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
575 
NET sram_flash_data<21> LOC = AA15 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
576 
NET sram_flash_data<20> LOC = AB14 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
577 
NET sram_flash_data<19> LOC = AA12 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
578 
NET sram_flash_data<18> LOC = AB11 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
579 
NET sram_flash_data<17> LOC = AA13 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
580 
NET sram_flash_data<16> LOC = AA14 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
581 
NET sram_flash_data<15> LOC = AC24 | IOSTANDARD = LVDCI_33;
582 
NET sram_flash_data<14> LOC = AB22 | IOSTANDARD = LVDCI_33;
583 
NET sram_flash_data<13> LOC = AA22 | IOSTANDARD = LVDCI_33;
584 
NET sram_flash_data<12> LOC = AC21 | IOSTANDARD = LVDCI_33;
585 
NET sram_flash_data<11> LOC = AB21 | IOSTANDARD = LVDCI_33;
586 
NET sram_flash_data<10> LOC = W21  | IOSTANDARD = LVDCI_33;
587 
NET sram_flash_data<9>  LOC = W20  | IOSTANDARD = LVDCI_33;
588 
NET sram_flash_data<8>  LOC = U19  | IOSTANDARD = LVDCI_33;
589 
NET sram_flash_data<7>  LOC = U20  | IOSTANDARD = LVDCI_33;
590 
NET sram_flash_data<6>  LOC = V19  | IOSTANDARD = LVDCI_33;
591 
NET sram_flash_data<5>  LOC = W19  | IOSTANDARD = LVDCI_33;
592 
NET sram_flash_data<4>  LOC = Y21  | IOSTANDARD = LVDCI_33;
593 
NET sram_flash_data<3>  LOC = Y20  | IOSTANDARD = LVDCI_33;
594 
NET sram_flash_data<2>  LOC = AD19 | IOSTANDARD = LVDCI_33;
595 
NET sram_flash_data<1>  LOC = AC19 | IOSTANDARD = LVDCI_33;
596 
NET sram_flash_data<0>  LOC = AB20 | IOSTANDARD = LVDCI_33;
597 
 
598 
NET sram_flash_data<*> PULLDOWN;
599 
 
600 
NET sram_cen            LOC = AB24 | IOSTANDARD = LVDCI_33;
601 
NET sram_oe_n           LOC = AC22 | IOSTANDARD = LVDCI_33;
602 
NET flash_oe_n          LOC = AA9  | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
603 
NET sram_flash_we_n     LOC = AB15 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
604 
NET sram_bw<3>          LOC = W24  | IOSTANDARD = LVDCI_33;
605 
NET sram_bw<2>          LOC = W23  | IOSTANDARD = LVDCI_33;
606 
NET sram_bw<1>          LOC = V24  | IOSTANDARD = LVDCI_33;
607 
NET sram_bw<0>          LOC = V23  | IOSTANDARD = LVDCI_33;
608 
NET flash_cen           LOC = AA10 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
609 
NET sram_adv_ld_n       LOC = U21  | IOSTANDARD = LVDCI_33;
610 
NET sram_mode           LOC = AC23 | IOSTANDARD = LVDCI_33;
611 
NET flash_audio_reset_n LOC = AD10 | IOSTANDARD = LVCMOS33;
612 
 
613 
#------------------------------------------------------------------------------
614 
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
615 
#------------------------------------------------------------------------------
616 
 
617 
NET dvi_iic_scl  LOC = D21;
618 
NET dvi_iic_sda  LOC = D20;
619 
NET dvi_iic_scl  SLEW = SLOW;
620 
NET dvi_iic_scl  DRIVE = 6;
621 
NET dvi_iic_scl  TIG;
622 
NET dvi_iic_scl  IOSTANDARD = LVCMOS33;
623 
NET dvi_iic_sda  SLEW = SLOW;
624 
NET dvi_iic_sda  DRIVE = 6;
625 
NET dvi_iic_sda  TIG;
626 
NET dvi_iic_sda  IOSTANDARD = LVCMOS33;
627 
 
628 
NET tft_lcd_data<0>  LOC = A17;
629 
NET tft_lcd_data<1>  LOC = B17;
630 
NET tft_lcd_data<2>  LOC = C17;
631 
NET tft_lcd_data<3>  LOC = D18;
632 
NET tft_lcd_data<4>  LOC = C16;
633 
NET tft_lcd_data<5>  LOC = D16;
634 
NET tft_lcd_data<6>  LOC = B16;
635 
NET tft_lcd_data<7>  LOC = B15;
636 
NET tft_lcd_data<8>  LOC = A15;
637 
NET tft_lcd_data<9>  LOC = A14;
638 
NET tft_lcd_data<10> LOC = B14;
639 
NET tft_lcd_data<11> LOC = C14;
640 
NET tft_lcd_data<*> IOSTANDARD = LVDCI_33;
641 
 
642 
NET tft_lcd_clk_p LOC = A20;
643 
NET tft_lcd_clk_p IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = FAST;
644 
NET tft_lcd_clk_n LOC = B20;
645 
NET tft_lcd_clk_n IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = FAST;
646 
 
647 
NET tft_lcd_hsync LOC = C19;
648 
NET tft_lcd_hsync IOSTANDARD = LVDCI_33;
649 
NET tft_lcd_vsync LOC = D19;
650 
NET tft_lcd_vsync IOSTANDARD = LVDCI_33;
651 
NET tft_lcd_de    LOC = C18;
652 
NET tft_lcd_de    IOSTANDARD = LVDCI_33;
653 
NET tft_lcd_reset_b LOC = A18;
654 
NET tft_lcd_reset_b IOSTANDARD = LVCMOS33;
655 
 
656 
NET "tft_clk"  TNM_NET = "tft_clk";
657 
TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
658 
TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
659 
 
660 
#------------------------------------------------------------------------------
661 
# IO Pad Location Constraints / Properties for Ethernet
662 
#------------------------------------------------------------------------------
663 
 
664 
NET phy_col        LOC = G20 | IOSTANDARD = LVCMOS25;
665 
NET phy_crs        LOC = H22 | IOSTANDARD = LVCMOS25;
666 
NET phy_dv         LOC = J19 | IOSTANDARD = LVCMOS25;
667 
NET phy_rx_clk     LOC = F14 | IOSTANDARD = LVCMOS25;
668 
NET phy_rx_data<3> LOC = E22 | IOSTANDARD = LVCMOS25;
669 
NET phy_rx_data<2> LOC = E20 | IOSTANDARD = LVCMOS25;
670 
NET phy_rx_data<1> LOC = E21 | IOSTANDARD = LVCMOS25;
671 
NET phy_rx_data<0> LOC = F20 | IOSTANDARD = LVCMOS25;
672 
 
673 
NET phy_rx_er      LOC = H19 | IOSTANDARD = LVCMOS25;
674 
NET phy_tx_clk     LOC = D13 | IOSTANDARD = LVCMOS25;
675 
NET phy_mii_clk    LOC = F18 | IOSTANDARD = LVCMOS25;
676 
NET phy_mii_int_n  LOC = F17 | IOSTANDARD = LVCMOS25;
677 
NET phy_rst_n      LOC = F8  | IOSTANDARD = LVCMOS25;
678 
NET phy_tx_data<3> LOC = B25 | IOSTANDARD = LVDCI_33;
679 
NET phy_tx_data<2> LOC = C24 | IOSTANDARD = LVDCI_33;
680 
NET phy_tx_data<1> LOC = D24 | IOSTANDARD = LVDCI_33;
681 
NET phy_tx_data<0> LOC = C23 | IOSTANDARD = LVDCI_33;
682 
NET phy_tx_en      LOC = B24 | IOSTANDARD = LVDCI_33;
683 
NET phy_tx_er      LOC = A24 | IOSTANDARD = LVDCI_33;
684 
NET phy_mii_data   LOC = E8  | IOSTANDARD = LVCMOS25;
685 
 
686 
NET phy_mii_int_n  PULLUP;
687 
 
688 
NET phy_mii_int_n  TIG;
689 
NET phy_rst_n      TIG;
690 
 
691 
# Timing Constraints (these are recommended in documentation and
692 
# are unaltered except for the TIG)
693 
NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
694 
NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
695 
TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
696 
TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
697 
 
698 
NET "phy_rx_data<3>" IOBDELAY=NONE;
699 
NET "phy_rx_data<2>" IOBDELAY=NONE;
700 
NET "phy_rx_data<1>" IOBDELAY=NONE;
701 
NET "phy_rx_data<0>" IOBDELAY=NONE;
702 
NET "phy_dv" IOBDELAY=NONE;
703 
NET "phy_rx_er" IOBDELAY=NONE;
704 
NET "phy_crs" IOBDELAY=NONE;
705 
NET "phy_col" IOBDELAY=NONE;
706 
 
707 
# Timing ignores (to specify unconstrained paths)
708 
TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
709 
TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
710 
TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
711 
TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
712 
 
713 
#------------------------------------------------------------------------------
714 
# IO Pad Location Constraints / Properties for AC97 Sound Controller
715 
#------------------------------------------------------------------------------
716 
 
717 
NET ac97_bit_clk   LOC = AC13;
718 
NET ac97_bit_clk   IOSTANDARD = LVCMOS33;
719 
NET ac97_bit_clk   PERIOD = 80;
720 
NET ac97_sdata_in  LOC = AC12;
721 
NET ac97_sdata_in  IOSTANDARD = LVCMOS33;
722 
NET ac97_sdata_out LOC = AC11;
723 
NET ac97_sdata_out IOSTANDARD = LVCMOS33;
724 
NET ac97_sync      LOC = AD11;
725 
NET ac97_sync      IOSTANDARD = LVCMOS33;
726 
 
727 
 

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