OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-actel-proasic3/] [Makefile] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
GRLIB=../..
2
TOP=leon3mp
3
BOARD=actel-coremp7-1000
4
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
5
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
6
UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
7
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
8
EFFORT=high
9
XSTOPT=
10
SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
11
VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
12
VHDLSIMFILES=testbench.vhd
13
SIMTOP=testbench
14
SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
15
SDC=leon3mp.sdc
16
PDC=leon3mp.pdc
17
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
18
CLEAN=soft-clean
19
 
20
TECHLIBS = proasic3
21
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22
        tmtc openchip hynix ihp gleichmann micron spw usbhc
23
DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
24
        pci spacewire leon3ft grusbhc haps
25
 
26
FILESKIP = i2cmst.vhd
27
 
28
include $(GRLIB)/bin/Makefile
29
include $(GRLIB)/software/leon3/Makefile
30
 
31
 
32
##################  project specific targets ##########################

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.