OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-actel-proasic3/] [leon3mp.sdc] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
################################################################################
2
# Actel Designer Software Release Designer
3
################################################################################
4
 
5
########  Clock Constraints  ########
6
 
7
create_clock  -period 20.0000 [get_ports {clk}]
8
 
9
#create_clock  -period 30.0000 [get_ports {pci_clk}]
10
#
11
#create_clock  -period 10.0000 [get_ports {spw_clk}]
12
#
13
#create_clock  -period 10.0000 [get_ports {spwclk}]
14
 
15
 
16
########   Delay Constraints  ########
17
 
18
#set_max_delay  7.00 -from [all_inputs]  -to [get_clocks {pci_clk}]
19
#set_max_delay 11.00 -from [get_clocks {pci_clk}]  -to [all_outputs]
20
 
21
#set_max_delay 11.00 -from [all_inputs]  -to [all_outputs]
22
 
23
#set_max_delay  5.00 -from [all_inputs]  -to [get_clocks {clk}]
24
#set_max_delay 10.00 -from [get_clocks {clk}]  -to [all_outputs]
25
 
26
 
27
########   False Path Constraints  ########
28
 
29
 
30
########   OutPut load Constraints  ########
31
 
32
 
33
########   Multicycle Constraints  ########

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.