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dimamali |
------------------------------------------------------------------------------
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-- LEON3 Demonstration design test bench
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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library techmap;
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use techmap.gencomp.all;
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library micron;
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use micron.components.all;
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use work.debug.all;
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use work.config.all; -- configuration
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entity testbench is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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ncpu : integer := CFG_NCPU;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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clkperiod : integer := 20; -- system clock period
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romwidth : integer := 8; -- rom data width (8/32)
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romdepth : integer := 23; -- rom address depth
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sramwidth : integer := 32; -- ram data width (8/16/32)
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sramdepth : integer := 20; -- ram address depth
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srambanks : integer := 1 -- number of ram banks
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);
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end;
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architecture behav of testbench is
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constant promfile : string := "prom.srec"; -- rom contents
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constant sramfile : string := "sram.srec"; -- ram contents
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constant sdramfile : string := "sdram.srec"; -- sdram contents
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component leon3mp
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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ncpu : integer := CFG_NCPU;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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resetn : in std_ulogic;
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clk : in std_ulogic;
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clkout : out std_ulogic;
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pllref : in std_ulogic;
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errorn : out std_ulogic;
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address : out std_logic_vector(27 downto 0);
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data : inout std_logic_vector(31 downto 0);
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ramsn : out std_ulogic;
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ramoen : out std_ulogic;
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rwen : out std_ulogic;
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mben : out std_logic_vector (3 downto 0);
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iosn : out std_ulogic;
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romsn : out std_ulogic;
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oen : out std_ulogic;
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writen : out std_ulogic;
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sa : out std_logic_vector(11 downto 0);
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sd : inout std_logic_vector(31 downto 0);
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sdclk : out std_ulogic;
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sdcke : out std_ulogic; -- sdram clock enable
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sdcsn : out std_ulogic; -- sdram chip select
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sdwen : out std_ulogic; -- sdram write enable
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sdrasn : out std_ulogic; -- sdram ras
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sdcasn : out std_ulogic; -- sdram cas
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sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
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sdba : out std_logic_vector (1 downto 0);
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dsutx : out std_ulogic; -- DSU tx data
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dsurx : in std_ulogic; -- DSU rx data
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dsubren : in std_ulogic;
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dsuact : out std_ulogic;
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rxd1 : in std_ulogic; -- UART1 rx data
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txd1 : out std_ulogic; -- UART1 tx data
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ata_rst : out std_logic;
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ata_data : inout std_logic_vector(15 downto 0);
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ata_da : out std_logic_vector(2 downto 0);
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ata_cs0 : out std_logic;
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ata_cs1 : out std_logic;
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ata_dior : out std_logic;
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ata_diow : out std_logic;
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ata_iordy : in std_logic;
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ata_intrq : in std_logic;
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ata_dmack : out std_logic;
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cf_power : out std_logic;
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cf_gnd_da : out std_logic_vector(10 downto 3); -- grounded address lines
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cf_atasel : out std_logic; -- grounded to select true IDE mode
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cf_we : out std_logic; -- should be connected to VCC in true IDE mode
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cf_csel : out std_logic;
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-- for smc lan chip
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eth_aen : out std_ulogic;
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eth_readn : out std_ulogic;
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eth_writen : out std_ulogic;
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eth_nbe : out std_logic_vector (3 downto 0);
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eth_lclk : out std_ulogic;
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eth_nads : out std_logic;
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eth_ncycle : out std_logic;
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eth_wnr : out std_logic;
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eth_nvlbus : out std_logic;
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eth_nrdyrtn : out std_logic;
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eth_ndatacs : out std_logic
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);
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end component;
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signal clk : std_logic := '0';
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signal clkout, pllref : std_ulogic;
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signal Rst : std_logic := '0'; -- Reset
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constant ct : integer := clkperiod/2;
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signal address : std_logic_vector(27 downto 0);
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signal data : std_logic_vector(31 downto 0);
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signal ramsn : std_ulogic;
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signal ramoen : std_ulogic;
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signal rwen : std_ulogic;
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signal mben : std_logic_vector(3 downto 0);
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--signal rwenx : std_logic_vector(3 downto 0);
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signal romsn : std_ulogic;
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signal iosn : std_ulogic;
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signal oen : std_ulogic;
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--signal read : std_ulogic;
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signal writen : std_ulogic;
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signal brdyn : std_ulogic;
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signal bexcn : std_ulogic;
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signal wdog : std_ulogic;
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signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
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signal dsurst : std_ulogic;
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signal test : std_ulogic;
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signal error : std_logic;
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signal gpio : std_logic_vector(7 downto 0);
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signal GND : std_ulogic := '0';
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signal VCC : std_ulogic := '1';
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signal NC : std_ulogic := 'Z';
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signal clk2 : std_ulogic := '1';
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signal sdcke : std_ulogic; -- clk en
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signal sdcsn : std_ulogic; -- chip sel
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signal sdwen : std_ulogic; -- write en
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signal sdrasn : std_ulogic; -- row addr stb
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signal sdcasn : std_ulogic; -- col addr stb
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signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
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signal sdclk : std_ulogic;
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signal sdba : std_logic_vector(1 downto 0);
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signal plllock : std_ulogic;
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signal txd1, rxd1 : std_ulogic;
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--signal txd2, rxd2 : std_ulogic;
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-- for smc lan chip
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signal eth_aen : std_ulogic; -- for smsc eth
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signal eth_readn : std_ulogic; -- for smsc eth
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signal eth_writen : std_ulogic; -- for smsc eth
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signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
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signal eth_datacsn : std_ulogic;
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constant lresp : boolean := false;
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signal sa : std_logic_vector(14 downto 0);
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signal sd : std_logic_vector(31 downto 0);
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-- ATA signals
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signal ata_rst : std_logic;
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signal ata_data : std_logic_vector(15 downto 0);
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signal ata_da : std_logic_vector(2 downto 0);
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signal ata_cs0 : std_logic;
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signal ata_cs1 : std_logic;
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signal ata_dior : std_logic;
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signal ata_diow : std_logic;
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signal ata_iordy : std_logic;
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signal ata_intrq : std_logic;
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signal ata_dmack : std_logic;
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signal cf_gnd_da : std_logic_vector(10 downto 3);
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signal cf_atasel : std_logic;
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signal cf_we : std_logic;
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signal cf_power : std_logic;
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signal cf_csel : std_logic;
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signal from_ata : ata_out_type := ATAO_RESET_VECTOR;
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signal to_ata : ata_in_type := ATAI_RESET_VECTOR;
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begin
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-- clock and reset
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clk <= not clk after ct * 1 ns;
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rst <= dsurst;
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dsubren <= '1'; rxd1 <= '1';
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pllref <= clkout;
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d3 : leon3mp
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generic map ( fabtech, memtech, padtech, clktech, ncpu,
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disas, dbguart, pclow )
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port map (rst, clk, clkout, pllref, error, address, data,
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ramsn, ramoen, rwen, mben, iosn,
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romsn, oen, writen,
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sa(11 downto 0), sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba,
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dsutx, dsurx, dsubren, dsuact,
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rxd1, txd1,
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ata_rst, ata_data, ata_da, ata_cs0, ata_cs1, ata_dior, ata_diow,
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ata_iordy, ata_intrq, ata_dmack,
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cf_power, cf_gnd_da, cf_atasel, cf_we, cf_csel,
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eth_aen, eth_readn, eth_writen, eth_nbe);
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-- optional sdram
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sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
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u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
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PORT MAP(
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Dq => sd(31 downto 16), Addr => sa(12 downto 0),
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Ba => sdba, Clk => sdclk, Cke => sdcke,
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Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm => sddqm(3 downto 2));
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u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
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PORT MAP(
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Dq => sd(15 downto 0), Addr => sa(12 downto 0),
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Ba => sdba, Clk => sdclk, Cke => sdcke,
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Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm => sddqm(1 downto 0));
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u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
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PORT MAP(
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Dq => sd(31 downto 16), Addr => sa(12 downto 0),
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Ba => sdba, Clk => sdclk, Cke => sdcke,
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Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm => sddqm(3 downto 2));
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u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
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PORT MAP(
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Dq => sd(15 downto 0), Addr => sa(12 downto 0),
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Ba => sdba, Clk => sdclk, Cke => sdcke,
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Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm => sddqm(1 downto 0));
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end generate;
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-- 8 bit prom
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prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
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port map (address(romdepth-1 downto 0), data(31 downto 24),
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romsn, rwen, oen);
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sram0 : for i in 0 to (sramwidth/8)-1 generate
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sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
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port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
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rwen, ramoen);
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end generate;
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disk: ata_device
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generic map( sector_length => 512, log2_size => 14)
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port map( clk => clk, rst => rst, d => ata_data, atai => to_ata,
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atao => from_ata
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);
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to_ata.cs(0)<=ata_cs0; to_ata.cs(1)<=ata_cs1;
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to_ata.da<=ata_da; to_ata.dmack<=ata_dmack;
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to_ata.dior<=ata_dior; to_ata.diow<=ata_diow; to_ata.reset<=ata_rst;
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ata_intrq<=from_ata.intrq; ata_iordy<=from_ata.iordy;
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error <= 'H'; -- ERROR pull-up
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iuerr : process
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begin
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wait for 2500 ns;
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if to_x01(error) = '1' then wait on error; end if;
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assert (to_x01(error) = '1')
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report "*** IU in error mode, simulation halted ***"
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severity failure ;
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end process;
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data <= buskeep(data), (others => 'H') after 250 ns;
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sd <= buskeep(sd), (others => 'H') after 250 ns;
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test0 : grtestmod
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port map ( rst, clk, error, address(21 downto 2), data,
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iosn, oen, writen, brdyn);
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dsucom : process
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procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
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variable w32 : std_logic_vector(31 downto 0);
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variable c8 : std_logic_vector(7 downto 0);
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constant txp : time := 160 * 1 ns;
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begin
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dsutx <= '1';
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dsurst <= '0';
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wait for 500 ns;
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dsurst <= '1';
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wait;
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wait for 5000 ns;
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|
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txc(dsutx, 16#55#, txp); -- sync uart
|
316 |
|
|
|
317 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
318 |
|
|
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
319 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
|
320 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
321 |
|
|
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
|
322 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
|
323 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
324 |
|
|
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
|
325 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
|
326 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
327 |
|
|
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
328 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
|
329 |
|
|
|
330 |
|
|
txc(dsutx, 16#c0#, txp);
|
331 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
332 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
|
333 |
|
|
txc(dsutx, 16#c0#, txp);
|
334 |
|
|
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
|
335 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
|
336 |
|
|
txc(dsutx, 16#c0#, txp);
|
337 |
|
|
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
|
338 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
|
339 |
|
|
txc(dsutx, 16#c0#, txp);
|
340 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
|
341 |
|
|
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
|
342 |
|
|
txc(dsutx, 16#c0#, txp);
|
343 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
344 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
|
345 |
|
|
|
346 |
|
|
txc(dsutx, 16#c0#, txp);
|
347 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
348 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
|
349 |
|
|
|
350 |
|
|
txc(dsutx, 16#c0#, txp);
|
351 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
|
352 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
|
353 |
|
|
|
354 |
|
|
txc(dsutx, 16#c0#, txp);
|
355 |
|
|
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
|
356 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
|
357 |
|
|
txc(dsutx, 16#c0#, txp);
|
358 |
|
|
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
|
359 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
txc(dsutx, 16#c0#, txp);
|
366 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
367 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
|
368 |
|
|
|
369 |
|
|
txc(dsutx, 16#c0#, txp);
|
370 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
|
371 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
|
372 |
|
|
|
373 |
|
|
txc(dsutx, 16#c0#, txp);
|
374 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
|
375 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
|
376 |
|
|
|
377 |
|
|
txc(dsutx, 16#80#, txp);
|
378 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
379 |
|
|
rxi(dsurx, w32, txp, lresp);
|
380 |
|
|
|
381 |
|
|
txc(dsutx, 16#a0#, txp);
|
382 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
|
383 |
|
|
rxi(dsurx, w32, txp, lresp);
|
384 |
|
|
|
385 |
|
|
end;
|
386 |
|
|
|
387 |
|
|
begin
|
388 |
|
|
|
389 |
|
|
dsucfg(dsutx, dsurx);
|
390 |
|
|
|
391 |
|
|
wait;
|
392 |
|
|
end process;
|
393 |
|
|
end ;
|
394 |
|
|
|