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dimamali |
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This leon3 design is tailored to the Altera NiosII Cyclone-III
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Development board, with 16-bit DDR SDRAM and 1 Mbyte of SSRAM.
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0. Introduction
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---------------
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The leon3 design can be synthesized with quartus or synplify,
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and can reach 50 - 70 MHz depending on configuration and synthesis
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options. Use 'make quartus' or 'make quartus-synp' to run the
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complete flow. To program the FPGA in batch mode, use
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'make quartus-prog-fpga' or 'make quartus-prog-fpga-ref (reference config).
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The output from grmon should look something like this:
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grmon -altjtag -jtagdevice 1 -ramrws 1 -normw -u
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GRMON LEON debug monitor v1.1.30
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Copyright (C) 2004,2005 Gaisler Research - all rights reserved.
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For latest updates, go to http://www.gaisler.com/
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Comments or bug-reports to support@gaisler.com
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using Altera JTAG cable
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Can't open file '/root/.jtag.conf', errno = 2
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Can't open file '/root/.jtag.conf', errno = 2
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Selected cable 1 - USB-Blaster [USB 1-1.2]
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JTAG chain:
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@1: EP3C25 (0x020F30DD)
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GRLIB build version: 2996
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initialising ..........
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detected frequency: 51 MHz
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Component Vendor
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LEON3 SPARC V8 Processor Gaisler Research
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AHB Debug JTAG TAP Gaisler Research
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LEON2 Memory Controller European Space Agency
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AHB/APB Bridge Gaisler Research
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LEON3 Debug Support Unit Gaisler Research
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DDR266 Controller Gaisler Research
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Generic APB UART Gaisler Research
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Multi-processor Interrupt Ctrl Gaisler Research
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Modular Timer Unit Gaisler Research
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General purpose I/O port Gaisler Research
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Use command 'info sys' to print a detailed report of attached cores
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grlib> info sys
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00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
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ahb master 0
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01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
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ahb master 1
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00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
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ahb: 00000000 - 20000000
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ahb: 20000000 - 40000000
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ahb: a0000000 - b0000000
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apb: 80000000 - 80000100
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16-bit prom @ 0x00000000
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32-bit static ram: 1 * 1024 kbyte @ 0xa0000000
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01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
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ahb: 80000000 - 80100000
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02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
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ahb: 90000000 - a0000000
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AHB trace 128 lines, stack pointer 0xa00ffff0
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CPU#0 win 8, hwbp 2, itrace 128, V8 mul/div, lddel 1
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icache 2 * 8 kbyte, 32 byte/line lru
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dcache 2 * 4 kbyte, 16 byte/line lru
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03.01:025 Gaisler Research DDR266 Controller (ver 0x0)
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ahb: 40000000 - 50000000
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ahb: fff00100 - fff00200
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16-bit DDR : 1 * 32 Mbyte @ 0x40000000
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100 MHz, col 9, ref 7.8 us
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01.01:00c Gaisler Research Generic APB UART (ver 0x1)
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irq 2
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apb: 80000100 - 80000200
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baud rate 38403, DSU mode (FIFO debug)
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02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
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apb: 80000200 - 80000300
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03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
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irq 8
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apb: 80000300 - 80000400
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8-bit scaler, 2 * 32-bit timers, divisor 51
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05.01:01a Gaisler Research General purpose I/O port (ver 0x0)
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apb: 80000500 - 80000600
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grlib>
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1. DDR interface
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----------------
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The DDR interface is supported and runs at 100 MHz.
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The read data clock phase shift should be set to 90' (rskew = 2500).
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2. SSRAM interface
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------------------
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The SSRAM can be accessed using the standard LEON2 MCTRL core.
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One read waitstate is needed, start grmon with :
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grmon -altjtag -jtagdevice 1 -ramrws 1 -normw -u
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3. UART
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-------
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The board has no RS232 connector, so grmon should be started
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with -u to loop-back the UART output to the console.
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4. Flash memory
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---------------
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The 16-bit flash memory can be accessed and programmed by grmon,
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if the SSRAM is working. The output from the 'flash' command is
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listed below:
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grlib> fla
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Intel-style 16-bit flash on D[31:16]
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Manuf. Intel
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Device 0x881B
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Device ID 70a6ffff00684403
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User ID ffffffffffffffff
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1 x 16 Mbyte = 16 Mbyte total @ 0x00000000
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CFI info
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flash family : 1
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flash size : 128 Mbit
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erase regions : 2
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erase blocks : 131
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write buffer : 64 bytes
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region 0 : 4 blocks of 32 Kbytes
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region 1 : 127 blocks of 128 Kbytes
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5.1 How to program the flash prom with a FPGA programming file
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--------------------------------------------------------------
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There are two ways of programming the Flash memory. One using
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Altera's Parallel Flash Loader and one using GRMON.
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Programming the Flash using Altera's Parallel Flash Loader:
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1. Start Quartus II and select File -> Convert Programming Files
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2. Make the following settings:
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Programming File Type: Programmer Object file (.pof)
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Mode: Active Parallel
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Configuration device: CFI_128MB
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3. Select "Configuration Master" under "Input files to convert" and click
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"Add file"
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4. Select the leon3mp.sof file and click OK
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5. Select "SOF data" and click "Properties"
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6. Change the following properties:
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Address mode for selected pages: Start
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Start address: 0x020000
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7. Generate the programmer object file by clicking "Generate"
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8. Start the Quartus II programmer
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9. Click "Auto Detect"
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10. Right-click on the detected EP3C25 device and select "Attach Flash Device"
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11. Select Flash Memory, CFI_128MB and click "OK"
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12. Right click on the added CFI_128MB Flash device and select "Change File"
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13. Select the .pof file that was generated in step 7 and click "OK".
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14. Check the "Program/Configure" box for the added file under the Flash
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device. Checking this box will change the Device File to "Factory
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default PFL image"
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15. Click "Start"
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16. When programming has successfully finished press "Reconfigure" on the
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board to load the leon3mp design.
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Programming the Flash with GRMON:
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1. Create a hex file of the programming file with Quartus. Choose
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"Active Parallel" as the Mode. This mode is available in Quartus II 7.2
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2. Convert the Intel Hex file to srecord format. The hexfile needs to be byte
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swapped. This can be done with a tool from the SRecord package which can be
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downloaded from http://srecord.sourceforge.net/. Issue the command:
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srec_cat output_file.hexout -Intel -byteswap > fpga.srec
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If the resulting fpga.srec file does not have the correct offset, the
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offset may have to be given as an argument to srec_cat:
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srec_cat output_file.hexout -Intel -byteswap -offset 0x20000 > fpga.srec
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To see that the data has the correct offset, issue the command:
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srec_info fpga.srec
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The "Data:" area should start at 020000.
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3. Program the flash memory using grmon:
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flash unlock all
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flash erase 0x20000 0x100000
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flash load fpga.srec
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The programming is slow, and will take at approximately 30 minutes.
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