1 |
2 |
dimamali |
|
2 |
|
|
|
3 |
|
|
Prompt for target technology
|
4 |
|
|
CONFIG_SYN_INFERRED
|
5 |
|
|
Selects the target technology for memory and pads.
|
6 |
|
|
The following are available:
|
7 |
|
|
|
8 |
|
|
- Inferred: Generic FPGA or ASIC targets if your synthesis tool
|
9 |
|
|
is capable of inferring RAMs and pads automatically.
|
10 |
|
|
|
11 |
|
|
- Actel ProAsic/P/3 and Axellerator FPGAs
|
12 |
|
|
- Aeroflex UT25CRH Rad-Hard 0.25 um CMOS
|
13 |
|
|
- Altera: Most Altera FPGA families
|
14 |
|
|
- Altera-Stratix: Altera Stratix FPGA family
|
15 |
|
|
- Altera-StratixII: Altera Stratix-II FPGA family
|
16 |
|
|
- ATC18: Atmel-Nantes 0.18 um rad-hard CMOS
|
17 |
|
|
- IHP25: IHP 0.25 um CMOS
|
18 |
|
|
- IHP25RH: IHP Rad-Hard 0.25 um CMOS
|
19 |
|
|
- Lattice : EC/ECP/XP FPGAs
|
20 |
|
|
- Quicklogic : Eclipse/E/II FPGAs
|
21 |
|
|
- UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
|
22 |
|
|
- Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries
|
23 |
|
|
- Xilinx-Spartan3E: Xilinx Spartan3E libraries
|
24 |
|
|
- Xilinx-Virtex/E: Xilinx Virtex/E libraries
|
25 |
|
|
- Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries
|
26 |
|
|
|
27 |
|
|
|
28 |
|
|
Ram library
|
29 |
|
|
CONFIG_MEM_VIRAGE
|
30 |
|
|
Select RAM generators for ASIC targets.
|
31 |
|
|
|
32 |
|
|
Infer ram
|
33 |
|
|
CONFIG_SYN_INFER_RAM
|
34 |
|
|
Say Y here if you want the synthesis tool to infer your
|
35 |
|
|
RAM automatically. Say N to directly instantiate technology-
|
36 |
|
|
specific RAM cells for the selected target technology package.
|
37 |
|
|
|
38 |
|
|
Infer pads
|
39 |
|
|
CONFIG_SYN_INFER_PADS
|
40 |
|
|
Say Y here if you want the synthesis tool to infer pads.
|
41 |
|
|
Say N to directly instantiate technology-specific pads from
|
42 |
|
|
the selected target technology package.
|
43 |
|
|
|
44 |
|
|
No async reset
|
45 |
|
|
CONFIG_SYN_NO_ASYNC
|
46 |
|
|
Say Y here if you disable asynchronous reset in some of the IP cores.
|
47 |
|
|
Might be necessary if the target library does not have cells with
|
48 |
|
|
asynchronous set/reset.
|
49 |
|
|
|
50 |
|
|
Scan support
|
51 |
|
|
CONFIG_SYN_SCAN
|
52 |
|
|
Say Y here to enable scan support in some cores. This will enable
|
53 |
|
|
the scan support generics where available and add logic to make
|
54 |
|
|
the design testable using full-scan.
|
55 |
|
|
|
56 |
|
|
Use Virtex CLKDLL for clock synchronisation
|
57 |
|
|
CONFIG_CLK_INFERRED
|
58 |
|
|
Certain target technologies include clock generators to scale or
|
59 |
|
|
phase-adjust the system and SDRAM clocks. This is currently supported
|
60 |
|
|
for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you
|
61 |
|
|
can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2),
|
62 |
|
|
the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL
|
63 |
|
|
(Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred'
|
64 |
|
|
option to skip a clock generator.
|
65 |
|
|
|
66 |
|
|
Clock multiplier
|
67 |
|
|
CONFIG_CLK_MUL
|
68 |
|
|
When using the Xilinx DCM or Altera ALTPLL, the system clock can
|
69 |
|
|
be multiplied with a factor of 2 - 32, and divided by a factor of
|
70 |
|
|
1 - 32. This makes it possible to generate almost any desired
|
71 |
|
|
processor frequency. When using the Xilinx CLKDLL generator,
|
72 |
|
|
the resulting frequency scale factor (mul/div) must be one of
|
73 |
|
|
1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
|
74 |
|
|
|
75 |
|
|
WARNING: The resulting clock must be within the limits specified
|
76 |
|
|
by the target FPGA family.
|
77 |
|
|
|
78 |
|
|
Clock divider
|
79 |
|
|
CONFIG_CLK_DIV
|
80 |
|
|
When using the Xilinx DCM or Altera ALTPLL, the system clock can
|
81 |
|
|
be multiplied with a factor of 2 - 32, and divided by a factor of
|
82 |
|
|
1 - 32. This makes it possible to generate almost any desired
|
83 |
|
|
processor frequency. When using the Xilinx CLKDLL generator,
|
84 |
|
|
the resulting frequency scale factor (mul/div) must be one of
|
85 |
|
|
1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
|
86 |
|
|
|
87 |
|
|
WARNING: The resulting clock must be within the limits specified
|
88 |
|
|
by the target FPGA family.
|
89 |
|
|
|
90 |
|
|
Output clock divider
|
91 |
|
|
CONFIG_OCLK_DIV
|
92 |
|
|
When using the Proasic3 PLL, the system clock is generated by three
|
93 |
|
|
parameters: input clock multiplication, input clock division and
|
94 |
|
|
output clock division. Only certain values of these parameters
|
95 |
|
|
are allowed, but unfortunately this is not documented by Actel.
|
96 |
|
|
To find the correct values, run the Libero Smartgen tool and
|
97 |
|
|
insert you desired input and output clock frequencies in the
|
98 |
|
|
Static PLL configurator. The mul/div factors can then be read
|
99 |
|
|
out from tool.
|
100 |
|
|
|
101 |
|
|
System clock multiplier
|
102 |
|
|
CONFIG_CLKDLL_1_2
|
103 |
|
|
The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0,
|
104 |
|
|
or 2.0. Useful when the target board has an oscillator with a too high
|
105 |
|
|
(or low) frequency for your design. The divided clock will be used as the
|
106 |
|
|
main clock for the whole processor (except PCI and ethernet clocks).
|
107 |
|
|
|
108 |
|
|
System clock multiplier
|
109 |
|
|
CONFIG_DCM_2_3
|
110 |
|
|
The Xilinx DCM and Altera ALTDLL can scale the input clock with a large
|
111 |
|
|
range of factors. Useful when the target board has an oscillator with a
|
112 |
|
|
too high (or low) frequency for your design. The divided clock will
|
113 |
|
|
be used as the main clock for the whole processor (except PCI and
|
114 |
|
|
ethernet clocks). NOTE: the resulting frequency must be at least
|
115 |
|
|
24 MHz or the DCM and ALTDLL might not work.
|
116 |
|
|
|
117 |
|
|
Enable CLKDLL for PCI clock
|
118 |
|
|
CONFIG_PCI_CLKDLL
|
119 |
|
|
Say Y here to re-synchronize the PCI clock using a
|
120 |
|
|
Virtex BUFGDLL macro. Will improve PCI clock-to-output
|
121 |
|
|
delays on the expense of input-setup requirements.
|
122 |
|
|
|
123 |
|
|
Use PCI clock system clock
|
124 |
|
|
CONFIG_PCI_SYSCLK
|
125 |
|
|
Say Y here to the PCI clock to generate the system clock.
|
126 |
|
|
The PCI clock can be scaled using the DCM or CLKDLL to
|
127 |
|
|
generate a suitable processor clock.
|
128 |
|
|
|
129 |
|
|
External SDRAM clock feedback
|
130 |
|
|
CONFIG_CLK_NOFB
|
131 |
|
|
Say Y here to disable the external clock feedback to synchronize the
|
132 |
|
|
SDRAM clock. This option is necessary if your board or design does not
|
133 |
|
|
have an external clock feedback that is connected to the pllref input
|
134 |
|
|
of the clock generator.
|
135 |
|
|
|
136 |
|
|
Number of processors
|
137 |
|
|
CONFIG_PROC_NUM
|
138 |
|
|
The number of processor cores. The LEON3MP design can accomodate
|
139 |
|
|
up to 4 LEON3 processor cores. Use 1 unless you know what you are
|
140 |
|
|
doing ...
|
141 |
|
|
|
142 |
|
|
Number of SPARC register windows
|
143 |
|
|
CONFIG_IU_NWINDOWS
|
144 |
|
|
The SPARC architecture (and LEON) allows 2 - 32 register windows.
|
145 |
|
|
However, any number except 8 will require that you modify and
|
146 |
|
|
recompile your run-time system or kernel. Unless you know what
|
147 |
|
|
you are doing, use 8.
|
148 |
|
|
|
149 |
|
|
SPARC V8 multiply and divide instruction
|
150 |
|
|
CONFIG_IU_V8MULDIV
|
151 |
|
|
If you say Y here, the SPARC V8 multiply and divide instructions
|
152 |
|
|
will be implemented. The instructions are: UMUL, UMULCC, SMUL,
|
153 |
|
|
SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent
|
154 |
|
|
integer multiplications and divisions, significant performance
|
155 |
|
|
increase can be achieved. Emulated floating-point operations will
|
156 |
|
|
also benefit from this option.
|
157 |
|
|
|
158 |
|
|
By default, the gcc compiler does not emit multiply or divide
|
159 |
|
|
instructions and your code must be compiled with -mv8 to see any
|
160 |
|
|
performance increase. On the other hand, code compiled with -mv8
|
161 |
|
|
will generate an illegal instruction trap when executed on processors
|
162 |
|
|
with this option disabled.
|
163 |
|
|
|
164 |
|
|
The divider consumes approximately 2 kgates, the multiplier 6 kgates.
|
165 |
|
|
|
166 |
|
|
Multiplier latency
|
167 |
|
|
CONFIG_IU_MUL_LATENCY_2
|
168 |
|
|
Implementation options for the integer multiplier.
|
169 |
|
|
|
170 |
|
|
Type Implementation issue-rate/latency
|
171 |
|
|
2-clocks 32x32 pipelined multiplier 1/2
|
172 |
|
|
4-clocks 16x16 standard multiplier 4/4
|
173 |
|
|
5-clocks 16x16 pipelined multiplier 4/5
|
174 |
|
|
|
175 |
|
|
Multiplier latency
|
176 |
|
|
CONFIG_IU_MUL_MAC
|
177 |
|
|
If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)
|
178 |
|
|
instructions will be enabled. The instructions implement a
|
179 |
|
|
single-cycle 16x16->32 bits multiply with a 40-bits accumulator.
|
180 |
|
|
The details of these instructions can be found in the LEON manual,
|
181 |
|
|
This option is only available when 16x16 multiplier is used.
|
182 |
|
|
|
183 |
|
|
Single vector trapping
|
184 |
|
|
CONFIG_IU_SVT
|
185 |
|
|
Single-vector trapping is a SPARC V8e option to reduce code-size
|
186 |
|
|
in small applications. If enabled, the processor will jump to
|
187 |
|
|
the address of trap 0 (tt = 0x00) for all traps. No trap table
|
188 |
|
|
is then needed. The trap type is present in %psr.tt and must
|
189 |
|
|
be decoded by the O/S. Saves 4 Kbyte of code, but increases
|
190 |
|
|
trap and interrupt overhead. Currently, the only O/S supporting
|
191 |
|
|
this option is eCos. To enable SVT, the O/S must also set bit 13
|
192 |
|
|
in %asr17.
|
193 |
|
|
|
194 |
|
|
Load latency
|
195 |
|
|
CONFIG_IU_LDELAY
|
196 |
|
|
Defines the pipeline load delay (= pipeline cycles before the data
|
197 |
|
|
from a load instruction is available for the next instruction).
|
198 |
|
|
One cycle gives best performance, but might create a critical path
|
199 |
|
|
on targets with slow (data) cache memories. A 2-cycle delay can
|
200 |
|
|
improve timing but will reduce performance with about 5%.
|
201 |
|
|
|
202 |
|
|
Reset address
|
203 |
|
|
CONFIG_IU_RSTADDR
|
204 |
|
|
By default, a SPARC processor starts execution at address 0.
|
205 |
|
|
With this option, any 4-kbyte aligned reset start address can be
|
206 |
|
|
choosen. Keep at 0 unless you really know what you are doing.
|
207 |
|
|
|
208 |
|
|
Power-down
|
209 |
|
|
CONFIG_PWD
|
210 |
|
|
Say Y here to enable the power-down feature of the processor.
|
211 |
|
|
Might reduce the maximum frequency slightly on FPGA targets.
|
212 |
|
|
For details on the power-down operation, see the LEON3 manual.
|
213 |
|
|
|
214 |
|
|
Hardware watchpoints
|
215 |
|
|
CONFIG_IU_WATCHPOINTS
|
216 |
|
|
The processor can have up to 4 hardware watchpoints, allowing to
|
217 |
|
|
create both data and instruction breakpoints at any memory location,
|
218 |
|
|
also in PROM. Each watchpoint will use approximately 500 gates.
|
219 |
|
|
Use 0 to disable the watchpoint function.
|
220 |
|
|
|
221 |
|
|
Floating-point enable
|
222 |
|
|
CONFIG_FPU_ENABLE
|
223 |
|
|
Say Y here to enable the floating-point interface for the MEIKO
|
224 |
|
|
or GRFPU. Note that no FPU's are provided with the GPL version
|
225 |
|
|
of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial
|
226 |
|
|
cores and must be obtained separately.
|
227 |
|
|
|
228 |
|
|
FPU selection
|
229 |
|
|
CONFIG_FPU_GRFPU
|
230 |
|
|
Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun
|
231 |
|
|
Meiko FPU core. All cores are fully IEEE-754 compatible and support
|
232 |
|
|
all SPARC FPU instructions.
|
233 |
|
|
|
234 |
|
|
GRFPU Multiplier
|
235 |
|
|
CONFIG_FPU_GRFPU_INFMUL
|
236 |
|
|
On FPGA targets choose inferred multiplier. For ASIC implementations
|
237 |
|
|
choose between Synopsys Design Ware (DW) multiplier or Module
|
238 |
|
|
Generator (ModGen) multiplier. DW multiplier gives better results
|
239 |
|
|
(smaller area and better timing) but requires DW license. ModGen
|
240 |
|
|
multiplier is part of GRLIB and does not require license.
|
241 |
|
|
|
242 |
|
|
Shared GRFPU
|
243 |
|
|
CONFIG_FPU_GRFPU_SH
|
244 |
|
|
If enabled multiple CPU cores will share one GRFPU.
|
245 |
|
|
|
246 |
|
|
GRFPC Configuration
|
247 |
|
|
CONFIG_FPU_GRFPC0
|
248 |
|
|
Configures the GRFPU-LITE controller.
|
249 |
|
|
|
250 |
|
|
In simple configuration controller executes FP instructions
|
251 |
|
|
in parallel with integer instructions. FP operands are fetched
|
252 |
|
|
in the register file stage and the result is written in the write
|
253 |
|
|
stage. This option uses least area resources.
|
254 |
|
|
|
255 |
|
|
Data forwarding configuration gives ~ 10 % higher FP performance than
|
256 |
|
|
the simple configuration by adding data forwarding between the pipeline
|
257 |
|
|
stages.
|
258 |
|
|
|
259 |
|
|
Non-blocking controller allows FP load and store instructions to
|
260 |
|
|
execute in parallel with FP instructions. The performance increase is
|
261 |
|
|
~ 20 % for FP applications. This option uses most logic resources and
|
262 |
|
|
is suitable for ASIC implementations.
|
263 |
|
|
|
264 |
|
|
Floating-point netlist
|
265 |
|
|
CONFIG_FPU_NETLIST
|
266 |
|
|
Say Y here to use a VHDL netlist of the GRFPU-Lite. This is
|
267 |
|
|
only available in certain versions of grlib.
|
268 |
|
|
|
269 |
|
|
Enable Instruction cache
|
270 |
|
|
CONFIG_ICACHE_ENABLE
|
271 |
|
|
The instruction cache should always be enabled to allow
|
272 |
|
|
maximum performance. Some low-end system might want to
|
273 |
|
|
save area and disable the cache, but this will reduce
|
274 |
|
|
the performance with a factor of 2 - 3.
|
275 |
|
|
|
276 |
|
|
Enable Data cache
|
277 |
|
|
CONFIG_DCACHE_ENABLE
|
278 |
|
|
The data cache should always be enabled to allow
|
279 |
|
|
maximum performance. Some low-end system might want to
|
280 |
|
|
save area and disable the cache, but this will reduce
|
281 |
|
|
the performance with a factor of 2 at least.
|
282 |
|
|
|
283 |
|
|
Instruction cache associativity
|
284 |
|
|
CONFIG_ICACHE_ASSO1
|
285 |
|
|
The instruction cache can be implemented as a multi-set cache with
|
286 |
|
|
1 - 4 sets. Higher associativity usually increases the cache hit
|
287 |
|
|
rate and thereby the performance. The downside is higher power
|
288 |
|
|
consumption and increased gate-count for tag comparators.
|
289 |
|
|
|
290 |
|
|
Note that a 1-set cache is effectively a direct-mapped cache.
|
291 |
|
|
|
292 |
|
|
Instruction cache set size
|
293 |
|
|
CONFIG_ICACHE_SZ1
|
294 |
|
|
The size of each set in the instuction cache (kbytes). Valid values
|
295 |
|
|
are 1 - 64 in binary steps. Note that the full range is only supported
|
296 |
|
|
by the generic and virtex2 targets. Most target packages are limited
|
297 |
|
|
to 2 - 16 kbyte. Large set size gives higher performance but might
|
298 |
|
|
affect the maximum frequency (on ASIC targets). The total instruction
|
299 |
|
|
cache size is the number of set multiplied with the set size.
|
300 |
|
|
|
301 |
|
|
Instruction cache line size
|
302 |
|
|
CONFIG_ICACHE_LZ16
|
303 |
|
|
The instruction cache line size. Can be set to either 16 or 32
|
304 |
|
|
bytes per line. Instruction caches typically benefit from larger
|
305 |
|
|
line sizes, but on small caches it migh be better with 16 bytes/line
|
306 |
|
|
to limit eviction miss rate.
|
307 |
|
|
|
308 |
|
|
Instruction cache replacement algorithm
|
309 |
|
|
CONFIG_ICACHE_ALGORND
|
310 |
|
|
Cache replacement algorithm for caches with 2 - 4 sets. The 'random'
|
311 |
|
|
algorithm selects the set to evict randomly. The least-recently-used
|
312 |
|
|
(LRR) algorithm evicts the set least recently replaced. The least-
|
313 |
|
|
recently-used (LRU) algorithm evicts the set least recently accessed.
|
314 |
|
|
The random algorithm uses a simple 1- or 2-bit counter to select
|
315 |
|
|
the eviction set and has low area overhead. The LRR scheme uses one
|
316 |
|
|
extra bit in the tag ram and has therefore also low area overhead.
|
317 |
|
|
However, the LRR scheme can only be used with 2-set caches. The LRU
|
318 |
|
|
scheme has typically the best performance but also highest area overhead.
|
319 |
|
|
A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops
|
320 |
|
|
per line, and a 4-set LRU uses 5 flip-flops per line to store the access
|
321 |
|
|
history.
|
322 |
|
|
|
323 |
|
|
Instruction cache locking
|
324 |
|
|
CONFIG_ICACHE_LOCK
|
325 |
|
|
Say Y here to enable cache locking in the instruction cache.
|
326 |
|
|
Locking can be done on cache-line level, but will increase the
|
327 |
|
|
width of the tag ram with one bit. If you don't know what
|
328 |
|
|
locking is good for, it is safe to say N.
|
329 |
|
|
|
330 |
|
|
Data cache associativity
|
331 |
|
|
CONFIG_DCACHE_ASSO1
|
332 |
|
|
The data cache can be implemented as a multi-set cache with
|
333 |
|
|
1 - 4 sets. Higher associativity usually increases the cache hit
|
334 |
|
|
rate and thereby the performance. The downside is higher power
|
335 |
|
|
consumption and increased gate-count for tag comparators.
|
336 |
|
|
|
337 |
|
|
Note that a 1-set cache is effectively a direct-mapped cache.
|
338 |
|
|
|
339 |
|
|
Data cache set size
|
340 |
|
|
CONFIG_DCACHE_SZ1
|
341 |
|
|
The size of each set in the data cache (kbytes). Valid values are
|
342 |
|
|
1 - 64 in binary steps. Note that the full range is only supported
|
343 |
|
|
by the generic and virtex2 targets. Most target packages are limited
|
344 |
|
|
to 2 - 16 kbyte. A large cache gives higher performance but the
|
345 |
|
|
data cache is timing critical an a too large setting might affect
|
346 |
|
|
the maximum frequency (on ASIC targets). The total data cache size
|
347 |
|
|
is the number of set multiplied with the set size.
|
348 |
|
|
|
349 |
|
|
Data cache line size
|
350 |
|
|
CONFIG_DCACHE_LZ16
|
351 |
|
|
The data cache line size. Can be set to either 16 or 32 bytes per
|
352 |
|
|
line. A smaller line size gives better associativity and higher
|
353 |
|
|
cache hit rate, but requires a larger tag memory.
|
354 |
|
|
|
355 |
|
|
Data cache replacement algorithm
|
356 |
|
|
CONFIG_DCACHE_ALGORND
|
357 |
|
|
See the explanation for instruction cache replacement algorithm.
|
358 |
|
|
|
359 |
|
|
Data cache locking
|
360 |
|
|
CONFIG_DCACHE_LOCK
|
361 |
|
|
Say Y here to enable cache locking in the data cache.
|
362 |
|
|
Locking can be done on cache-line level, but will increase the
|
363 |
|
|
width of the tag ram with one bit. If you don't know what
|
364 |
|
|
locking is good for, it is safe to say N.
|
365 |
|
|
|
366 |
|
|
Data cache snooping
|
367 |
|
|
CONFIG_DCACHE_SNOOP
|
368 |
|
|
Say Y here to enable data cache snooping on the AHB bus. Is only
|
369 |
|
|
useful if you have additional AHB masters such as the DSU or a
|
370 |
|
|
target PCI interface. Note that the target technology must support
|
371 |
|
|
dual-port RAMs for this option to be enabled. Dual-port RAMS are
|
372 |
|
|
currently supported on Virtex/2, Virage and Actel targets.
|
373 |
|
|
|
374 |
|
|
Data cache snooping implementation
|
375 |
|
|
CONFIG_DCACHE_SNOOP_FAST
|
376 |
|
|
The default snooping implementation is 'slow', which works if you
|
377 |
|
|
don't have AHB slaves in cacheable areas capable of zero-waitstates
|
378 |
|
|
non-sequential write accesses. Otherwise use 'fast' and suffer a
|
379 |
|
|
few kgates extra area. This option is currently only needed in
|
380 |
|
|
multi-master systems with the SSRAM or DDR memory controllers.
|
381 |
|
|
|
382 |
|
|
Separate snoop tags
|
383 |
|
|
CONFIG_DCACHE_SNOOP_SEPTAG
|
384 |
|
|
Enable a separate memory to store the data tags used for snooping.
|
385 |
|
|
This is necessary when snooping support is wanted in systems
|
386 |
|
|
with MMU, typically for SMP systems. In this case, the snoop
|
387 |
|
|
tags will contain the physical tag address while the normal
|
388 |
|
|
tags contain the virtual tag address. This option can also be
|
389 |
|
|
together with the 'fast snooping' option to enable snooping
|
390 |
|
|
support on technologies without dual-port RAMs. In such case,
|
391 |
|
|
the snoop tag RAM will be implemented using a two-port RAM.
|
392 |
|
|
|
393 |
|
|
Fixed cacheability map
|
394 |
|
|
CONFIG_CACHE_FIXED
|
395 |
|
|
If this variable is 0, the cacheable memory regions are defined
|
396 |
|
|
by the AHB plug&play information (default). To overriden the
|
397 |
|
|
plug&play settings, this variable can be set to indicate which
|
398 |
|
|
areas should be cached. The value is treated as a 16-bit hex value
|
399 |
|
|
with each bit defining if a 256 Mbyte segment should be cached or not.
|
400 |
|
|
The right-most (LSB) bit defines the cacheability of AHB address
|
401 |
|
|
|
402 |
|
|
3840 - 4096 MByte. If the bit is set, the corresponding area is
|
403 |
|
|
cacheable. A value of 00F3 defines address 0 - 0x20000000 and
|
404 |
|
|
0x40000000 - 0x80000000 as cacheable.
|
405 |
|
|
|
406 |
|
|
Local data ram
|
407 |
|
|
CONFIG_DCACHE_LRAM
|
408 |
|
|
Say Y here to add a local ram to the data cache controller.
|
409 |
|
|
Accesses to the ram (load/store) will be performed at 0 waitstates
|
410 |
|
|
and store data will never be written back to the AHB bus.
|
411 |
|
|
|
412 |
|
|
Size of local data ram
|
413 |
|
|
CONFIG_DCACHE_LRAM_SZ1
|
414 |
|
|
Defines the size of the local data ram in Kbytes. Note that most
|
415 |
|
|
technology libraries do not support larger rams than 16 Kbyte.
|
416 |
|
|
|
417 |
|
|
Start address of local data ram
|
418 |
|
|
CONFIG_DCACHE_LRSTART
|
419 |
|
|
Defines the 8 MSB bits of start address of the local data ram.
|
420 |
|
|
By default set to 8f (start address = 0x8f000000), but any value
|
421 |
|
|
(except 0) is possible. Note that the local data ram 'shadows'
|
422 |
|
|
a 16 Mbyte block of the address space.
|
423 |
|
|
|
424 |
|
|
MMU enable
|
425 |
|
|
CONFIG_MMU_ENABLE
|
426 |
|
|
Say Y here to enable the Memory Management Unit.
|
427 |
|
|
|
428 |
|
|
MMU split icache/dcache table lookaside buffer
|
429 |
|
|
CONFIG_MMU_COMBINED
|
430 |
|
|
Select "combined" for a combined icache/dcache table lookaside buffer,
|
431 |
|
|
"split" for a split icache/dcache table lookaside buffer
|
432 |
|
|
|
433 |
|
|
MMU tlb replacement scheme
|
434 |
|
|
CONFIG_MMU_REPARRAY
|
435 |
|
|
Select "LRU" to use the "least recently used" algorithm for TLB
|
436 |
|
|
replacement, or "Increment" for a simple incremental replacement
|
437 |
|
|
scheme.
|
438 |
|
|
|
439 |
|
|
Combined i/dcache tlb
|
440 |
|
|
CONFIG_MMU_I2
|
441 |
|
|
Select the number of entries for the instruction TLB, or the
|
442 |
|
|
combined icache/dcache TLB if such is used.
|
443 |
|
|
|
444 |
|
|
Split tlb, dcache
|
445 |
|
|
CONFIG_MMU_D2
|
446 |
|
|
Select the number of entries for the dcache TLB.
|
447 |
|
|
|
448 |
|
|
Fast writebuffer
|
449 |
|
|
CONFIG_MMU_FASTWB
|
450 |
|
|
Only selectable if split tlb is enabled. In case fast writebuffer is
|
451 |
|
|
enabled the tlb hit will be made concurrent to the cache hit. This
|
452 |
|
|
leads to higher store performance, but increased power and area.
|
453 |
|
|
|
454 |
|
|
DSU enable
|
455 |
|
|
CONFIG_DSU_ENABLE
|
456 |
|
|
The debug support unit (DSU) allows non-intrusive debugging and tracing
|
457 |
|
|
of both executed instructions and AHB transfers. If you want to enable
|
458 |
|
|
the DSU, say Y here and select the configuration below.
|
459 |
|
|
|
460 |
|
|
Trace buffer enable
|
461 |
|
|
CONFIG_DSU_TRACEBUF
|
462 |
|
|
Say Y to enable the trace buffer. The buffer is not necessary for
|
463 |
|
|
debugging, only for tracing instructions and data transfers.
|
464 |
|
|
|
465 |
|
|
Enable instruction tracing
|
466 |
|
|
CONFIG_DSU_ITRACE
|
467 |
|
|
If you say Y here, an instruction trace buffer will be implemented
|
468 |
|
|
in each processor. The trace buffer will trace executed instructions
|
469 |
|
|
and their results, and place them in a circular buffer. The buffer
|
470 |
|
|
can be read out by any AHB master, and in particular by the debug
|
471 |
|
|
communication link.
|
472 |
|
|
|
473 |
|
|
Size of trace buffer
|
474 |
|
|
CONFIG_DSU_ITRACESZ1
|
475 |
|
|
Select the buffer size (in kbytes) for the instruction trace buffer.
|
476 |
|
|
Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
|
477 |
|
|
need 2 kbyte.
|
478 |
|
|
|
479 |
|
|
Enable AHB tracing
|
480 |
|
|
CONFIG_DSU_ATRACE
|
481 |
|
|
If you say Y here, an AHB trace buffer will be implemented in the
|
482 |
|
|
debug support unit processor. The AHB buffer will trace all transfers
|
483 |
|
|
on the AHB bus and save them in a circular buffer. The trace buffer
|
484 |
|
|
can be read out by any AHB master, and in particular by the debug
|
485 |
|
|
communication link.
|
486 |
|
|
|
487 |
|
|
Size of trace buffer
|
488 |
|
|
CONFIG_DSU_ATRACESZ1
|
489 |
|
|
Select the buffer size (in kbytes) for the AHB trace buffer.
|
490 |
|
|
Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
|
491 |
|
|
need 2 kbyte.
|
492 |
|
|
|
493 |
|
|
|
494 |
|
|
LEON3FT enable
|
495 |
|
|
CONFIG_LEON3FT_EN
|
496 |
|
|
Say Y here to use the fault-tolerant LEON3FT core instead of the
|
497 |
|
|
standard non-FT LEON3.
|
498 |
|
|
|
499 |
|
|
IU Register file protection
|
500 |
|
|
CONFIG_IUFT_NONE
|
501 |
|
|
Select the FT implementation in the LEON3FT integer unit
|
502 |
|
|
register file. The options include parity, parity with
|
503 |
|
|
sparing, 7-bit BCH and TMR.
|
504 |
|
|
|
505 |
|
|
FPU Register file protection
|
506 |
|
|
CONFIG_FPUFT_EN
|
507 |
|
|
Say Y to enable SEU protection of the FPU register file.
|
508 |
|
|
The GRFPU will be protected using 8-bit parity without restart, while
|
509 |
|
|
the GRFPU-Lite will be protected with 4-bit parity with restart. If
|
510 |
|
|
disabled the FPU register file will be implemented using flip-flops.
|
511 |
|
|
|
512 |
|
|
Cache memory error injection
|
513 |
|
|
CONFIG_RF_ERRINJ
|
514 |
|
|
Say Y here to enable error injection in to the IU/FPU regfiles.
|
515 |
|
|
Affects only simulation.
|
516 |
|
|
|
517 |
|
|
Cache memory protection
|
518 |
|
|
CONFIG_CACHE_FT_EN
|
519 |
|
|
Enable SEU error-correction in the cache memories.
|
520 |
|
|
|
521 |
|
|
Cache memory error injection
|
522 |
|
|
CONFIG_CACHE_ERRINJ
|
523 |
|
|
Say Y here to enable error injection in to the cache memories.
|
524 |
|
|
Affects only simulation.
|
525 |
|
|
|
526 |
|
|
Leon3ft netlist
|
527 |
|
|
CONFIG_LEON3_NETLIST
|
528 |
|
|
Say Y here to use a VHDL netlist of the LEON3FT. This is
|
529 |
|
|
only available in certain versions of grlib.
|
530 |
|
|
|
531 |
|
|
IU assembly printing
|
532 |
|
|
CONFIG_IU_DISAS
|
533 |
|
|
Enable printing of executed instructions to the console.
|
534 |
|
|
|
535 |
|
|
IU assembly printing in netlist
|
536 |
|
|
CONFIG_IU_DISAS_NET
|
537 |
|
|
Enable printing of executed instructions to the console also
|
538 |
|
|
when simulating a netlist. NOTE: with this option enabled, it
|
539 |
|
|
will not be possible to pass place&route.
|
540 |
|
|
|
541 |
|
|
32-bit program counters
|
542 |
|
|
CONFIG_DEBUG_PC32
|
543 |
|
|
Since the LSB 2 bits of the program counters always are zero, they are
|
544 |
|
|
normally not implemented. If you say Y here, the program counters will
|
545 |
|
|
be implemented with full 32 bits, making debugging of the VHDL model
|
546 |
|
|
much easier. Turn of this option for synthesis or you will be wasting
|
547 |
|
|
area.
|
548 |
|
|
|
549 |
|
|
|
550 |
|
|
CONFIG_AHB_DEFMST
|
551 |
|
|
Sets the default AHB master (see AMBA 2.0 specification for definition).
|
552 |
|
|
Should not be set to a value larger than the number of AHB masters - 1.
|
553 |
|
|
For highest processor performance, leave it at 0.
|
554 |
|
|
|
555 |
|
|
Default AHB master
|
556 |
|
|
CONFIG_AHB_RROBIN
|
557 |
|
|
Say Y here to enable round-robin arbitration of the AHB bus. A N will
|
558 |
|
|
select fixed priority, with the master with the highest bus index having
|
559 |
|
|
the highest priority.
|
560 |
|
|
|
561 |
|
|
Support AHB split-transactions
|
562 |
|
|
CONFIG_AHB_SPLIT
|
563 |
|
|
Say Y here to enable AHB split-transaction support in the AHB arbiter.
|
564 |
|
|
Unless you actually have an AHB slave that can generate AHB split
|
565 |
|
|
responses, say N and save some gates.
|
566 |
|
|
|
567 |
|
|
Default AHB master
|
568 |
|
|
CONFIG_AHB_IOADDR
|
569 |
|
|
Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined
|
570 |
|
|
in the plug&play extentions of the AMBA bus. Should be kept to FFF
|
571 |
|
|
unless you really know what you are doing.
|
572 |
|
|
|
573 |
|
|
APB bridge address
|
574 |
|
|
CONFIG_APB_HADDR
|
575 |
|
|
Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be
|
576 |
|
|
kept at 800 for software compatibility.
|
577 |
|
|
|
578 |
|
|
AHB monitor
|
579 |
|
|
CONFIG_AHB_MON
|
580 |
|
|
Say Y to enable the AHB bus monitor. The monitor will check for
|
581 |
|
|
illegal AHB transactions during simulation. It has no impact on
|
582 |
|
|
synthesis.
|
583 |
|
|
|
584 |
|
|
Report AHB errors
|
585 |
|
|
CONFIG_AHB_MONERR
|
586 |
|
|
Print out detected AHB violations on console.
|
587 |
|
|
|
588 |
|
|
Report AHB warnings
|
589 |
|
|
CONFIG_AHB_MONWAR
|
590 |
|
|
Print out detected AHB warnings on console.
|
591 |
|
|
|
592 |
|
|
|
593 |
|
|
DSU enable
|
594 |
|
|
CONFIG_DSU_UART
|
595 |
|
|
Say Y to enable the AHB uart (serial-to-AHB). This is the most
|
596 |
|
|
commonly used debug communication link.
|
597 |
|
|
|
598 |
|
|
JTAG Enable
|
599 |
|
|
CONFIG_DSU_JTAG
|
600 |
|
|
Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done
|
601 |
|
|
with GRMON through the boards JTAG chain at speed of 300 kbits/s.
|
602 |
|
|
Supported JTAG cables are Xilinx Parallel Cable III and IV.
|
603 |
|
|
|
604 |
|
|
Leon2 memory controller
|
605 |
|
|
CONFIG_MCTRL_LEON2
|
606 |
|
|
Say Y here to enable the LEON2 memory controller. The controller
|
607 |
|
|
can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
|
608 |
|
|
and SRAM is programmable to 8-, 16- or 32-bits.
|
609 |
|
|
|
610 |
|
|
8-bit memory support
|
611 |
|
|
CONFIG_MCTRL_8BIT
|
612 |
|
|
If you say Y here, the PROM/SRAM memory controller will support
|
613 |
|
|
8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
|
614 |
|
|
Say N to save a few hundred gates.
|
615 |
|
|
|
616 |
|
|
16-bit memory support
|
617 |
|
|
CONFIG_MCTRL_16BIT
|
618 |
|
|
If you say Y here, the PROM/SRAM memory controller will support
|
619 |
|
|
16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
|
620 |
|
|
Say N to save a few hundred gates.
|
621 |
|
|
|
622 |
|
|
Write strobe feedback
|
623 |
|
|
CONFIG_MCTRL_WFB
|
624 |
|
|
If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
|
625 |
|
|
be used to enable the data bus drivers during write cycles. This
|
626 |
|
|
will guarantee that the data is still valid on the rising edge of
|
627 |
|
|
the write strobe. If you say N, the write strobes and the data bus
|
628 |
|
|
drivers will be clocked on the rising edge, potentially creating
|
629 |
|
|
a hold time problem in external memory or I/O. However, in all
|
630 |
|
|
practical cases, there is enough capacitance in the data bus lines
|
631 |
|
|
to keep the value stable for a few (many?) nano-seconds after the
|
632 |
|
|
buffers have been disabled, making it safe to say N and remove a
|
633 |
|
|
combinational path in the netlist that might be difficult to
|
634 |
|
|
analyze.
|
635 |
|
|
|
636 |
|
|
Write strobe feedback
|
637 |
|
|
CONFIG_MCTRL_5CS
|
638 |
|
|
If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
|
639 |
|
|
be enabled. If you don't intend to use it, say N and save some gates.
|
640 |
|
|
|
641 |
|
|
SDRAM controller enable
|
642 |
|
|
CONFIG_MCTRL_SDRAM
|
643 |
|
|
Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
|
644 |
|
|
intend to use SDRAM, say N and save about 1 kgates.
|
645 |
|
|
|
646 |
|
|
SDRAM controller inverted clock
|
647 |
|
|
CONFIG_MCTRL_SDRAM_INVCLK
|
648 |
|
|
If you say Y here, the SDRAM controller output signals will be delayed
|
649 |
|
|
with 1/2 clock in respect to the SDRAM clock. This will allow the used
|
650 |
|
|
of an SDRAM clock which in not strictly in phase with the internal
|
651 |
|
|
clock. This option will limit the SDRAM frequency to 40 - 50 MHz.
|
652 |
|
|
|
653 |
|
|
On FPGA targets without SDRAM clock synchronizations through PLL/DLL,
|
654 |
|
|
say Y. On ASIC targets, say N and tell your foundry to balance the
|
655 |
|
|
SDRAM clock output.
|
656 |
|
|
|
657 |
|
|
SDRAM separate address buses
|
658 |
|
|
CONFIG_MCTRL_SDRAM_SEPBUS
|
659 |
|
|
Say Y here if your SDRAM is connected through separate address
|
660 |
|
|
and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
|
661 |
|
|
board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.
|
662 |
|
|
|
663 |
|
|
64-bit data bus
|
664 |
|
|
CONFIG_MCTRL_SDRAM_BUS64
|
665 |
|
|
Say Y here to enable 64-bit SDRAM data bus.
|
666 |
|
|
|
667 |
|
|
Page burst enable
|
668 |
|
|
CONFIG_MCTRL_PAGE
|
669 |
|
|
Say Y here to enable SDRAM page burst operation. This will implement
|
670 |
|
|
read operations using page bursts rather than 8-word bursts and save
|
671 |
|
|
about 500 gates (100 LUTs). Note that not all SDRAM supports page
|
672 |
|
|
burst, so use this option with care.
|
673 |
|
|
|
674 |
|
|
Programmable page burst enable
|
675 |
|
|
CONFIG_MCTRL_PROGPAGE
|
676 |
|
|
Say Y here to enable programmable SDRAM page burst operation. This
|
677 |
|
|
will allow to dynamically enable/disable page burst by setting
|
678 |
|
|
bit 17 in MCFG2.
|
679 |
|
|
|
680 |
|
|
SDRAM controller enable
|
681 |
|
|
CONFIG_SSCTRL
|
682 |
|
|
Say Y here to enabled a 32-bit synchronous SRAM (SSRAM) controller.
|
683 |
|
|
The controller is designed for piplined ZBT SSRAM.
|
684 |
|
|
|
685 |
|
|
CONFIG_SSCTRL_PROM16
|
686 |
|
|
Say Y here to enabled a 16-bit PROM support. The PROM should be
|
687 |
|
|
connected to D[31:16] of the data bus.
|
688 |
|
|
|
689 |
|
|
SDRAM controller enable
|
690 |
|
|
CONFIG_DDRSP
|
691 |
|
|
Say Y here to enabled a 16-bit DDR266 SDRAM controller.
|
692 |
|
|
|
693 |
|
|
Power-on init
|
694 |
|
|
CONFIG_DDRSP_INIT
|
695 |
|
|
Say Y here to enable the automatic DDR initialization sequence.
|
696 |
|
|
If disabled, the sequencemust be performed in software before
|
697 |
|
|
the DDR can be used. If unsure, say Y.
|
698 |
|
|
|
699 |
|
|
Memory frequency
|
700 |
|
|
CONFIG_DDRSP_FREQ
|
701 |
|
|
Enter the frequency of the DDR clock (in MHz). The value is
|
702 |
|
|
typically between 80 - 133, depending on system configuration.
|
703 |
|
|
Some template design (such as the leon3-avnet-eval-lx25)
|
704 |
|
|
calculate this value automatically and this value is not used.
|
705 |
|
|
|
706 |
|
|
Column bits
|
707 |
|
|
CONFIG_DDRSP_COL
|
708 |
|
|
Select the number of colomn address bits of the DDR memory.
|
709 |
|
|
Typical values are 8 - 11. Only needed when automatic DDR
|
710 |
|
|
initialisation is choosen. The column size can always be
|
711 |
|
|
programmed by software as well.
|
712 |
|
|
|
713 |
|
|
Chip select size
|
714 |
|
|
CONFIG_DDRSP_MBYTE
|
715 |
|
|
Select the memory size (Mbytes) that each chip select should decode.
|
716 |
|
|
Only needed when automatic DDR initialisation is choosen. The chip
|
717 |
|
|
select size can always be programmed by software as well.
|
718 |
|
|
|
719 |
|
|
Read clock phase shift
|
720 |
|
|
CONFIG_DDRSP_RSKEW
|
721 |
|
|
On Xilinx targets, the read clock is de-skewed and phase-shifted
|
722 |
|
|
using a DCM connected to the feed-back clock input. On some boards,
|
723 |
|
|
the de-skewing does not work perfectly, and some extra phase shifting
|
724 |
|
|
must be added manually. The entered value is set to the PHASE_SHIFT
|
725 |
|
|
generic on the Xilinx DCM. The Digilent Sparten3E-1600 board typically
|
726 |
|
|
needs a value of 35, while the Avnet Virtex4 Eval board needs -90.
|
727 |
|
|
For Altera CycloneIII, the entered value is set to the PHASE_SHIFT of
|
728 |
|
|
the PLL in ps (e.g 2500 for 90' shift in 100MHz)
|
729 |
|
|
On-chip rom
|
730 |
|
|
CONFIG_AHBROM_ENABLE
|
731 |
|
|
Say Y here to add a block on on-chip rom to the AHB bus. The ram
|
732 |
|
|
provides 0-waitstates read access, burst support, and 8-, 16-
|
733 |
|
|
and 32-bit data size. The rom will be syntheised into block rams
|
734 |
|
|
on Xilinx and Altera FPGA devices, and into gates on ASIC
|
735 |
|
|
technologies. GRLIB includes a utility to automatically create
|
736 |
|
|
the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB
|
737 |
|
|
documentation for details.
|
738 |
|
|
|
739 |
|
|
On-chip rom address
|
740 |
|
|
CONFIG_AHBROM_START
|
741 |
|
|
Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy
|
742 |
|
|
a 1 Mbyte slot at the selected address. Default is 000, corresponding
|
743 |
|
|
to AHB address 0x00000000. When address 0x0 is selected, the rom area
|
744 |
|
|
of any other memory controller is set to 0x10000000 to avoid conflicts.
|
745 |
|
|
|
746 |
|
|
Enable pipeline register for on-chip rom
|
747 |
|
|
CONFIG_AHBROM_PIPE
|
748 |
|
|
Say Y here to add a data pipeline register to the on-chip rom.
|
749 |
|
|
This should be done when the rom is implemenented in (ASIC) gates,
|
750 |
|
|
or in logic cells on FPGAs. Do not use this option when the rom is
|
751 |
|
|
implemented in block rams. If enabled, the rom will operate with
|
752 |
|
|
one waitstate.
|
753 |
|
|
|
754 |
|
|
On-chip ram
|
755 |
|
|
CONFIG_AHBRAM_ENABLE
|
756 |
|
|
Say Y here to add a block on on-chip ram to the AHB bus. The ram
|
757 |
|
|
provides 0-waitstates read access and 0/1 waitstates write access.
|
758 |
|
|
All AHB burst types are supported, as well as 8-, 16- and 32-bit
|
759 |
|
|
data size.
|
760 |
|
|
|
761 |
|
|
On-chip ram size
|
762 |
|
|
CONFIG_AHBRAM_SZ1
|
763 |
|
|
Set the size of the on-chip AHB ram. The ram is infered/instantiated
|
764 |
|
|
as four byte-wide ram slices to allow byte and half-word write
|
765 |
|
|
accesses. It is therefore essential that the target package can
|
766 |
|
|
infer byte-wide rams. This is currently supported on the generic,
|
767 |
|
|
virtex, virtex2, proasic and axellerator targets.
|
768 |
|
|
|
769 |
|
|
On-chip ram address
|
770 |
|
|
CONFIG_AHBRAM_START
|
771 |
|
|
Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
|
772 |
|
|
a 1 Mbyte slot at the selected address. Default is A00, corresponding
|
773 |
|
|
to AHB address 0xA0000000.
|
774 |
|
|
|
775 |
|
|
UART1 enable
|
776 |
|
|
CONFIG_UART1_ENABLE
|
777 |
|
|
Say Y here to enable UART1, or the console UART. This is needed to
|
778 |
|
|
get any print-out from LEON3 systems regardless of operating system.
|
779 |
|
|
|
780 |
|
|
UART1 FIFO
|
781 |
|
|
CONFIG_UA1_FIFO1
|
782 |
|
|
The UART has configurable transmitt and receive FIFO's, which can
|
783 |
|
|
be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
|
784 |
|
|
maximum throughput.
|
785 |
|
|
|
786 |
|
|
|
787 |
|
|
LEON3 interrupt controller
|
788 |
|
|
CONFIG_IRQ3_ENABLE
|
789 |
|
|
Say Y here to enable the LEON3 interrupt controller. This is needed
|
790 |
|
|
if you want to be able to receive interrupts. Operating systems like
|
791 |
|
|
Linux, RTEMS and eCos needs this option to be enabled. If you intend
|
792 |
|
|
to use the Bare-C run-time and not use interrupts, you could disable
|
793 |
|
|
the interrupt controller and save about 500 gates.
|
794 |
|
|
|
795 |
|
|
LEON3 interrupt controller broadcast
|
796 |
|
|
CONFIG_IRQ3_BROADCAST_ENABLE
|
797 |
|
|
If enabled the broadcast register is used to determine which
|
798 |
|
|
interrupt should be sent to all cpus instead of just the first
|
799 |
|
|
one that consumes it.
|
800 |
|
|
|
801 |
|
|
Secondary interrupts
|
802 |
|
|
CONFIG_IRQ3_SEC
|
803 |
|
|
The interrupt controller handles 15 interrupts by default (1 - 15).
|
804 |
|
|
These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F),
|
805 |
|
|
and AMBA interrupts 1 - 15. This option will enable 16 additional
|
806 |
|
|
(secondary) interrupts, corresponding to AMBA interrupts 16 - 31.
|
807 |
|
|
The secondary interrupts will be multiplexed onto one of the first
|
808 |
|
|
15 interrupts. The total number of handled interrupts can then
|
809 |
|
|
be up to 30 (14 primary and 16 secondary).
|
810 |
|
|
|
811 |
|
|
Number of interrupts
|
812 |
|
|
CONFIG_IRQ3_NSEC
|
813 |
|
|
Defines which of the first 15 interrupts should be used for the
|
814 |
|
|
secondary (16 - 31) interrupts. Interrupt 15 should be avoided
|
815 |
|
|
since it is not maskable by the processor.
|
816 |
|
|
Timer module enable
|
817 |
|
|
CONFIG_GPT_ENABLE
|
818 |
|
|
Say Y here to enable the Modular Timer Unit. The timer unit consists
|
819 |
|
|
of one common scaler and up to 7 independent timers. The timer unit
|
820 |
|
|
is needed for Linux, RTEMS, eCos and the Bare-C run-times.
|
821 |
|
|
|
822 |
|
|
Timer module enable
|
823 |
|
|
CONFIG_GPT_NTIM
|
824 |
|
|
Set the number of timers in the timer unit (1 - 7).
|
825 |
|
|
|
826 |
|
|
Scaler width
|
827 |
|
|
CONFIG_GPT_SW
|
828 |
|
|
Set the width if the common pre-scaler (2 - 16 bits). The scaler
|
829 |
|
|
is used to divide the system clock down to 1 MHz, so 8 bits should
|
830 |
|
|
be sufficient for most implementations (allows clocks up to 256 MHz).
|
831 |
|
|
|
832 |
|
|
Timer width
|
833 |
|
|
CONFIG_GPT_TW
|
834 |
|
|
Set the width if the timers (2 - 32 bits). 32 bits is recommended
|
835 |
|
|
for the Bare-C run-time, lower values (e.g. 16 bits) can work with
|
836 |
|
|
RTEMS and Linux.
|
837 |
|
|
|
838 |
|
|
Timer Interrupt
|
839 |
|
|
CONFIG_GPT_IRQ
|
840 |
|
|
Set the interrupt number for the first timer. Remaining timers will
|
841 |
|
|
have incrementing interrupts, unless the separate-interrupts option
|
842 |
|
|
below is disabled.
|
843 |
|
|
|
844 |
|
|
Watchdog enable
|
845 |
|
|
CONFIG_GPT_WDOGEN
|
846 |
|
|
Say Y here to enable the watchdog functionality in the timer unit.
|
847 |
|
|
|
848 |
|
|
Watchdog time-out value
|
849 |
|
|
CONFIG_GPT_WDOG
|
850 |
|
|
This value will be loaded in the watchdog timer at reset.
|
851 |
|
|
|
852 |
|
|
GPIO port
|
853 |
|
|
CONFIG_GRGPIO_ENABLE
|
854 |
|
|
Say Y here to enable a general purpose I/O port. The port can be
|
855 |
|
|
configured from 1 - 32 bits, whith each port signal individually
|
856 |
|
|
programmable as input or output. The port signals can also serve
|
857 |
|
|
as interrupt inputs.
|
858 |
|
|
|
859 |
|
|
GPIO port witdth
|
860 |
|
|
CONFIG_GRGPIO_WIDTH
|
861 |
|
|
Number of bits in the I/O port. Must be in the range of 1 - 32.
|
862 |
|
|
|
863 |
|
|
GPIO interrupt mask
|
864 |
|
|
CONFIG_GRGPIO_IMASK
|
865 |
|
|
The I/O port interrupt mask defines which bits in the I/O port
|
866 |
|
|
should be able to create an interrupt.
|
867 |
|
|
|
868 |
|
|
UART debugging
|
869 |
|
|
CONFIG_DEBUG_UART
|
870 |
|
|
During simulation, the output from the UARTs is printed on the
|
871 |
|
|
simulator console. Since the ratio between the system clock and
|
872 |
|
|
UART baud-rate is quite high, simulating UART output will be very
|
873 |
|
|
slow. If you say Y here, the UARTs will print a character as soon
|
874 |
|
|
as it is stored in the transmitter data register. The transmitter
|
875 |
|
|
ready flag will be permanently set, speeding up simulation. However,
|
876 |
|
|
the output on the UART tx line will be garbled. Has not impact on
|
877 |
|
|
synthesis, but will cause the LEON test bench to fail.
|
878 |
|
|
|
879 |
|
|
FPU register tracing
|
880 |
|
|
CONFIG_DEBUG_FPURF
|
881 |
|
|
If you say Y here, all writes to the floating-point unit register file
|
882 |
|
|
will be printed on the simulator console.
|
883 |
|
|
|