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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Altera Cyclone-III Embedded Evaluation Kit LEON3 Demonstration design test
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-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
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-- Adapted for EEK by Jan Andersson, Gaisler Research
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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library techmap;
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use techmap.gencomp.all;
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library micron;
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use micron.components.all;
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library cypress;
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use cypress.components.all;
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use work.debug.all;
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use work.config.all; -- configuration
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entity testbench is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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ncpu : integer := CFG_NCPU;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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clkperiod : integer := 20; -- system clock period
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romwidth : integer := 8; -- rom data width (8/32)
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romdepth : integer := 23; -- rom address depth
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sramwidth : integer := 32; -- ram data width (8/16/32)
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sramdepth : integer := 20; -- ram address depth
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srambanks : integer := 1 -- number of ram banks
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);
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end;
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architecture behav of testbench is
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constant promfile : string := "prom.srec"; -- rom contents
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constant sramfile : string := "sram.srec"; -- ram contents
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constant sdramfile : string := "sdram.srec"; -- sdram contents
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signal clk : std_logic := '0';
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signal clkout, pllref : std_ulogic;
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signal rst : std_logic := '0'; -- Reset
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constant ct : integer := clkperiod/2;
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signal address : std_logic_vector(25 downto 0);
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signal data : std_logic_vector(31 downto 0);
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signal romsn : std_ulogic;
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signal iosn : std_ulogic;
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signal oen : std_ulogic;
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signal writen : std_ulogic;
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signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
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signal dsurst : std_ulogic;
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signal test : std_ulogic;
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signal error : std_logic;
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signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
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signal GND : std_ulogic := '0';
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signal VCC : std_ulogic := '1';
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signal NC : std_ulogic := 'Z';
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signal clk2 : std_ulogic := '1';
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signal ssram_cen : std_logic;
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signal ssram_wen : std_logic;
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signal ssram_bw : std_logic_vector (0 to 3);
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signal ssram_oen : std_ulogic;
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signal ssram_clk : std_ulogic;
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signal ssram_adscn : std_ulogic;
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signal ssram_adsp_n : std_ulogic;
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signal ssram_adv_n : std_ulogic;
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signal datazz : std_logic_vector(3 downto 0);
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-- ddr memory
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signal ddr_clk : std_logic;
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signal ddr_clkb : std_logic;
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signal ddr_clkin : std_logic;
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signal ddr_cke : std_logic;
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signal ddr_csb : std_logic;
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signal ddr_web : std_ulogic; -- ddr write enable
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signal ddr_rasb : std_ulogic; -- ddr ras
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signal ddr_casb : std_ulogic; -- ddr cas
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signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
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signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
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signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
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signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
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signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
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-- Connections over HSMC connector
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-- LCD touch panel display
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signal hc_vd : std_logic;
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signal hc_hd : std_logic;
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signal hc_den : std_logic;
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signal hc_nclk : std_logic;
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signal hc_lcd_data : std_logic_vector(7 downto 0);
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signal hc_grest : std_logic;
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signal hc_scen : std_logic;
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signal hc_sda : std_logic;
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signal hc_adc_penirq_n : std_logic;
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signal hc_adc_dout : std_logic;
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signal hc_adc_busy : std_logic;
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signal hc_adc_din : std_logic;
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signal hc_adc_dclk : std_logic;
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signal hc_adc_cs_n : std_logic;
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-- Shared by video decoder and audio codec
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signal hc_i2c_sclk : std_logic;
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signal hc_i2c_sdat : std_logic;
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-- Video decoder
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signal hc_td_d : std_logic_vector(7 downto 0);
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signal hc_td_hs : std_logic;
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signal hc_td_vs : std_logic;
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signal hc_td_27mhz : std_logic;
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signal hc_td_reset : std_logic;
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-- Audio codec
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signal hc_aud_adclrck : std_logic;
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signal hc_aud_adcdat : std_logic;
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signal hc_aud_daclrck : std_logic;
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signal hc_aud_dacdat : std_logic;
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signal hc_aud_bclk : std_logic;
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signal hc_aud_xck : std_logic;
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-- SD card
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signal hc_sd_dat : std_logic;
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signal hc_sd_dat3 : std_logic;
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signal hc_sd_cmd : std_logic;
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signal hc_sd_clk : std_logic;
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-- Ethernet PHY
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signal hc_tx_d : std_logic_vector(3 downto 0);
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signal hc_rx_d : std_logic_vector(3 downto 0);
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signal hc_tx_clk : std_logic;
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signal hc_rx_clk : std_logic;
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signal hc_tx_en : std_logic;
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signal hc_rx_dv : std_logic;
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signal hc_rx_crs : std_logic;
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signal hc_rx_err : std_logic;
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signal hc_rx_col : std_logic;
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signal hc_mdio : std_logic;
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signal hc_mdc : std_logic;
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signal hc_eth_reset_n : std_logic;
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-- RX232 (console/debug UART)
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signal hc_uart_rxd : std_logic;
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signal hc_uart_txd : std_logic;
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-- PS/2
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signal hc_ps2_dat : std_logic;
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signal hc_ps2_clk : std_logic;
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-- VGA/DAC
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signal hc_vga_data : std_logic_vector(9 downto 0);
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signal hc_vga_clock : std_ulogic;
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signal hc_vga_hs : std_ulogic;
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signal hc_vga_vs : std_ulogic;
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signal hc_vga_blank : std_ulogic;
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signal hc_vga_sync : std_ulogic;
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-- I2C EEPROM
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signal hc_id_i2cscl : std_logic;
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signal hc_id_i2cdat : std_logic;
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-- Ethernet PHY sim model
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signal phy_tx_er : std_ulogic;
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signal phy_gtx_clk : std_ulogic;
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signal hc_tx_dt : std_logic_vector(7 downto 0) := (others => '0');
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signal hc_rx_dt : std_logic_vector(7 downto 0) := (others => '0');
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constant lresp : boolean := false;
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begin
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-- clock and reset
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clk <= not clk after ct * 1 ns;
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ddr_clkin <= not clk after ct * 1 ns;
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rst <= dsurst;
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dsubren <= '1'; hc_uart_rxd <= '1';
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address(0) <= '0';
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-- ddr_dqs <= (others => 'L');
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d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
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ncpu, disas, dbguart, pclow )
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port map (rst, clk, error,
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address(25 downto 1), data, romsn, oen, writen, open,
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ssram_cen, ssram_wen, ssram_bw, ssram_oen,
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ssram_clk, ssram_adscn, iosn,
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-- DDR
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ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
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ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
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-- DSU
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dsubren, dsuact,
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-- I/O port
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gpio,
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-- LCD
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hc_vd, hc_hd, hc_den, hc_nclk, hc_lcd_data, hc_grest, hc_scen,
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hc_sda, hc_adc_penirq_n, hc_adc_dout, hc_adc_busy, hc_adc_din,
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hc_adc_dclk, hc_adc_cs_n,
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-- Shared by video decoder and audio codec
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hc_i2c_sclk, hc_i2c_sdat,
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-- Video decoder
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hc_td_d, hc_td_hs, hc_td_vs, hc_td_27mhz, hc_td_reset,
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-- Audio codec
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hc_aud_adclrck, hc_aud_adcdat, hc_aud_daclrck, hc_aud_dacdat,
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hc_aud_bclk, hc_aud_xck,
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-- SD card
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hc_sd_dat, hc_sd_dat3, hc_sd_cmd, hc_sd_clk,
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-- Ethernet PHY
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hc_tx_d, hc_rx_d, hc_tx_clk, hc_rx_clk, hc_tx_en, hc_rx_dv, hc_rx_crs,
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hc_rx_err, hc_rx_col, hc_mdio, hc_mdc, hc_eth_reset_n,
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-- RX232 (console/debug UART)
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hc_uart_rxd, hc_uart_txd,
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-- PS/2
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hc_ps2_dat, hc_ps2_clk,
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-- VGA/DAC
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hc_vga_data, hc_vga_clock, hc_vga_hs, hc_vga_vs, hc_vga_blank, hc_vga_sync,
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-- I2C EEPROM
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hc_id_i2cscl, hc_id_i2cdat
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);
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-- I2C bus pull-ups
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hc_i2c_sclk <= 'H'; hc_i2c_sdat <= 'H';
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hc_id_i2cscl <= 'H'; hc_id_i2cdat <= 'H';
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-- SD card signals
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hc_sd_dat <= 'L'; hc_sd_cmd <= 'Z';
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ddr0 : mt46v16m16
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generic map (index => -1, fname => sdramfile)
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port map(
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Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
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Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
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Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
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Dm => ddr_dm(1 downto 0));
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datazz <= "HHHH";
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ssram_adsp_n <= '1'; ssram_adv_n <= '1';
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ssram0 : cy7c1380d generic map (fname => sramfile)
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port map(
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ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => data,
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iAddr => address(20 downto 2), iMode => gnd,
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inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
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inADSP => ssram_adsp_n, inADSC => ssram_adscn,
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iClk => ssram_clk,
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inBwa => ssram_bw(3), inBwb => ssram_bw(2),
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inBwc => ssram_bw(1), inBwd => ssram_bw(0),
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inOE => ssram_oen, inCE1 => ssram_cen,
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iCE2 => vcc, inCE3 => gnd, iZz => gnd);
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-- 16 bit prom
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prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
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port map (address(romdepth downto 1), data(31 downto 16),
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gnd, gnd, romsn, writen, oen);
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-- Ethernet PHY
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hc_mdio <= 'H';
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phy_tx_er <= '0';
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phy_gtx_clk <= '0';
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hc_tx_dt(3 downto 0) <= hc_tx_d;
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hc_rx_d <= hc_rx_dt(3 downto 0);
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p0: phy
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generic map(base1000_t_fd => 0, base1000_t_hd => 0)
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port map(hc_eth_reset_n, hc_mdio, hc_tx_clk, hc_rx_clk, hc_rx_dt, hc_rx_dv,
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hc_rx_err, hc_rx_col, hc_rx_crs, hc_tx_dt, hc_tx_en, phy_tx_er, hc_mdc, phy_gtx_clk);
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-- I2C memory
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i0: i2c_slave_model
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port map (hc_id_i2cscl, hc_id_i2cdat);
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error <= 'H'; -- ERROR pull-up
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iuerr : process
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begin
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wait for 2500 ns;
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if to_x01(error) = '1' then wait on error; end if;
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assert (to_x01(error) = '1')
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report "*** IU in error mode, simulation halted ***"
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severity failure ;
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end process;
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306 |
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307 |
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data <= buskeep(data), (others => 'H') after 250 ns;
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308 |
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309 |
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test0 : grtestmod
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310 |
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port map ( rst, clk, error, address(21 downto 2), data,
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311 |
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iosn, oen, writen, open);
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312 |
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313 |
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dsucom : process
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314 |
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procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
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315 |
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variable w32 : std_logic_vector(31 downto 0);
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316 |
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variable c8 : std_logic_vector(7 downto 0);
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317 |
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constant txp : time := 160 * 1 ns;
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318 |
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begin
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319 |
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dsutx <= '1';
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320 |
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dsurst <= '0';
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321 |
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wait for 500 ns;
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322 |
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dsurst <= '1';
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323 |
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wait;
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324 |
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wait for 5000 ns;
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325 |
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txc(dsutx, 16#55#, txp); -- sync uart
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326 |
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327 |
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-- txc(dsutx, 16#c0#, txp);
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328 |
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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329 |
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-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
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330 |
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-- txc(dsutx, 16#c0#, txp);
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331 |
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-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
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332 |
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-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
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333 |
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-- txc(dsutx, 16#c0#, txp);
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334 |
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
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335 |
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-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
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336 |
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-- txc(dsutx, 16#c0#, txp);
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337 |
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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338 |
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-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
|
339 |
|
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|
340 |
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txc(dsutx, 16#c0#, txp);
|
341 |
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
342 |
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
|
343 |
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txc(dsutx, 16#c0#, txp);
|
344 |
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txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
|
345 |
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
|
346 |
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txc(dsutx, 16#c0#, txp);
|
347 |
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txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
|
348 |
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
|
349 |
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txc(dsutx, 16#c0#, txp);
|
350 |
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
|
351 |
|
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txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
|
352 |
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txc(dsutx, 16#c0#, txp);
|
353 |
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
354 |
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
|
355 |
|
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|
356 |
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txc(dsutx, 16#c0#, txp);
|
357 |
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
358 |
|
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
|
359 |
|
|
|
360 |
|
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txc(dsutx, 16#c0#, txp);
|
361 |
|
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txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
|
362 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
|
363 |
|
|
|
364 |
|
|
txc(dsutx, 16#c0#, txp);
|
365 |
|
|
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
|
366 |
|
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
|
367 |
|
|
txc(dsutx, 16#c0#, txp);
|
368 |
|
|
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
|
369 |
|
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
txc(dsutx, 16#c0#, txp);
|
373 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
374 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
|
375 |
|
|
|
376 |
|
|
txc(dsutx, 16#c0#, txp);
|
377 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
|
378 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
|
379 |
|
|
|
380 |
|
|
txc(dsutx, 16#c0#, txp);
|
381 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
|
382 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
|
383 |
|
|
|
384 |
|
|
txc(dsutx, 16#80#, txp);
|
385 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
386 |
|
|
rxi(dsurx, w32, txp, lresp);
|
387 |
|
|
|
388 |
|
|
txc(dsutx, 16#a0#, txp);
|
389 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
|
390 |
|
|
rxi(dsurx, w32, txp, lresp);
|
391 |
|
|
|
392 |
|
|
end;
|
393 |
|
|
|
394 |
|
|
begin
|
395 |
|
|
|
396 |
|
|
dsucfg(dsutx, dsurx);
|
397 |
|
|
|
398 |
|
|
wait;
|
399 |
|
|
end process;
|
400 |
|
|
end ;
|
401 |
|
|
|