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dimamali |
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This leon3 design is tailored to the Altera NiosII Stratix-III
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Development board, with 64-bit DDR2 SDRAM and 4 Mbyte PSRAM.
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0. Introduction
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---------------
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The leon3 design can be synthesized with quartus or synplify,
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and can reach 150 - 170 MHz depending on configuration and synthesis
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options. Use 'make quartus' or 'make quartus-synp' to run the
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complete flow. To program the FPGA in batch mode, use
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'make quartus-prog-fpga' or 'make quartus-prog-fpga-ref (reference config).
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The output from grmon should look something like this:
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grmon -altjtag -jtagdevice 1 -u
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GRMON LEON debug monitor v1.1.29
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Copyright (C) 2004,2005 Gaisler Research - all rights reserved.
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For latest updates, go to http://www.gaisler.com/
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Comments or bug-reports to support@gaisler.com
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using Altera JTAG cable
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Selected cable 1 - USB-Blaster [USB 1-1.2]
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JTAG chain:
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@1: EP3SL150 (0x121020DD)
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GRLIB build version: 2949
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initialising ...........
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detected frequency: 152 MHz
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Component Vendor
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LEON3 SPARC V8 Processor Gaisler Research
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AHB Debug JTAG TAP Gaisler Research
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GR Ethernet MAC Gaisler Research
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LEON2 Memory Controller European Space Agency
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AHB/APB Bridge Gaisler Research
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LEON3 Debug Support Unit Gaisler Research
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DDR2 Controller Gaisler Research
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Generic APB UART Gaisler Research
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Multi-processor Interrupt Ctrl Gaisler Research
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Modular Timer Unit Gaisler Research
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General purpose I/O port Gaisler Research
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Use command 'info sys' to print a detailed report of attached cores
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grlib> info sys
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00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
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ahb master 0
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01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
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ahb master 1
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02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
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ahb master 2, irq 12
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apb: 80000b00 - 80000c00
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edcl ip 192.168.0.88, buffer 2 kbyte
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00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
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ahb: 00000000 - 20000000
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ahb: 20000000 - 40000000
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ahb: a0000000 - b0000000
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apb: 80000000 - 80000100
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16-bit prom @ 0x00000000
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01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
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ahb: 80000000 - 80100000
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02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
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ahb: 90000000 - a0000000
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AHB trace 128 lines, stack pointer 0x7ffffff0
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CPU#0 win 8, hwbp 2, itrace 128, V8 mul/div, lddel 1
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icache 2 * 8 kbyte, 32 byte/line lru
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dcache 2 * 4 kbyte, 32 byte/line lru
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03.01:02e Gaisler Research DDR2 Controller (ver 0x0)
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ahb: 40000000 - 80000000
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ahb: fff00100 - fff00200
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64-bit DDR2 : 2 * 512 Mbyte @ 0x40000000
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200 MHz, col 10, ref 7.8 us
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01.01:00c Gaisler Research Generic APB UART (ver 0x1)
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irq 2
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apb: 80000100 - 80000200
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baud rate 38383, DSU mode (FIFO debug)
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02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
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apb: 80000200 - 80000300
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03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
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irq 8
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apb: 80000300 - 80000400
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8-bit scaler, 2 * 32-bit timers, divisor 152
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05.01:01a Gaisler Research General purpose I/O port (ver 0x0)
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apb: 80000500 - 80000600
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grlib>
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1. DDR2 interface
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----------------
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The DDR2 interface has been tested up to 200 MHz. The input data delay
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has to be recalibrated when the interface frequency change. This can be
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done dynamically or by changing the delay in the .qsf file.
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2. SSRAM interface
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------------------
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The PSRAM is not supported.
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3. UART
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-------
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The board has no RS232 connector, so grmon should be started
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with -u to loop-back the UART output to the console.
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4. Flash memory
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---------------
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The 16-bit flash memory can be accessed and programmed by grmon,
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if the SSRAM is working. The output from the 'flash' command is
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listed below:
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grlib> flash
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Intel-style 16-bit flash on D[31:16]
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Manuf. Intel
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Device 0x891C
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Device ID a1d1ffff02824530
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User ID ffffffffffffffff
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1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
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CFI info
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flash family : 1
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flash size : 256 Mbit
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erase regions : 2
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erase blocks : 259
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write buffer : 64 bytes
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region 0 : 4 blocks of 32 Kbytes
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region 1 : 255 blocks of 128 Kbytes
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* How to program the flash prom with a FPGA programming file
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1. Create a hex file of the programming file with Quartus.
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2. Convert it to srecord and adjust the load address:
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objcopy --adjust-vma=0x20000 output_file.hexout -O srec fpga.srec
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3. Program the flash memory using grmon:
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flash unlock all
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flash erase 0x20000 0x100000
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flash load fpga.srec
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The programming is slow, and will take at approximately 30 minutes.
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5. Ethernet
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-----------
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The Ethernet debug link is enabled with IP=192.168.0.88.
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To be able to connect to the EDCL, the PHY has to be configured by
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the following grmon command:
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wmdio 18 27 0x808f
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wmdio 18 0 0xb100
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