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dimamali |
------------------------------------------------------------------------------
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-- LEON3 Demonstration design test bench
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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use work.debug.all;
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library techmap;
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use techmap.gencomp.all;
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library micron;
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use micron.components.all;
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use gaisler.jtagtst.all;
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use work.config.all; -- configuration
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entity testbench is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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clkperiod : integer := 20; -- system clock period
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romwidth : integer := 32; -- rom data width (8/32)
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romdepth : integer := 16; -- rom address depth
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sramwidth : integer := 32; -- ram data width (8/16/32)
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sramdepth : integer := 18; -- ram address depth
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srambanks : integer := 2; -- number of ram banks
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testen : integer := 0;
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scanen : integer := 0;
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testrst : integer := 0;
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testoen : integer := 0
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);
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end;
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architecture behav of testbench is
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constant promfile : string := "prom.srec"; -- rom contents
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constant sramfile : string := "sram.srec"; -- ram contents
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constant sdramfile : string := "sdram.srec"; -- sdram contents
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signal clk : std_logic := '0';
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signal Rst : std_logic := '0'; -- Reset
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constant ct : integer := clkperiod/2;
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signal address : std_logic_vector(27 downto 0);
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signal data : std_logic_vector(31 downto 0);
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signal cb : std_logic_vector(15 downto 0);
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signal ramsn : std_logic_vector(4 downto 0);
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signal ramoen : std_logic_vector(4 downto 0);
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signal rwen : std_logic_vector(3 downto 0);
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signal rwenx : std_logic_vector(3 downto 0);
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signal romsn : std_logic_vector(1 downto 0);
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signal iosn : std_ulogic;
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signal oen : std_ulogic;
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signal read : std_ulogic;
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signal writen : std_ulogic;
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signal brdyn : std_ulogic;
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signal bexcn : std_ulogic;
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signal wdogn : std_logic;
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signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
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signal dsurst : std_ulogic;
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signal test : std_ulogic;
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signal error : std_logic;
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signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
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signal VCC : std_ulogic := '1';
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signal NC : std_ulogic := 'Z';
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signal clk2 : std_ulogic := '1';
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signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
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signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
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signal sdwen : std_ulogic; -- write en
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signal sdrasn : std_ulogic; -- row addr stb
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signal sdcasn : std_ulogic; -- col addr stb
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signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
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signal sdclk : std_ulogic := '0';
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signal lock : std_ulogic;
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signal txd1, rxd1 : std_ulogic;
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signal txd2, rxd2 : std_ulogic;
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signal roen, roout, nandout, promedac : std_ulogic;
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constant lresp : boolean := false;
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signal gnd : std_logic_vector(3 downto 0);
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signal clksel : std_logic_vector(1 downto 0);
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signal prom32 : std_ulogic;
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signal spw_clksel : std_logic_vector(1 downto 0);
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signal spw_clk : std_ulogic := '0';
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signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
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signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
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begin
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-- clock and reset
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test <= '0' when testen = 0 else '1';
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rxd1 <= '1' when (testen = 1) and (testoen = 1) else
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'0' when (testen = 1) and (testoen = 0) else txd1;
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dsuen <= '1' when (testen = 1) and (testrst = 1) else
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'0' when (testen = 1) and (testrst = 0) else '1', '0' after 1500 ns;
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dsubre <= '1' when (testen = 1) and (scanen = 1) else
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-- '0' when (testen = 1) and (scanen = 0) else '1';
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'0' when (testen = 1) and (scanen = 0) else '0';
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clksel <= "00";
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spw_clksel <= "00";
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error <= 'H';
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gnd <= "0000";
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clk <= not clk after ct * 1 ns;
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spw_clk <= not spw_clk after ct * 1 ns;
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rst <= dsurst;
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bexcn <= '1'; wdogn <= 'H';
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gpio(2 downto 0) <= "HHL";
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-- gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
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gpio(15 downto 11) <= "HLLHH"; --19
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gpio(10 downto 8) <= "HLL"; --4
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gpio(7 downto 0) <= (others => 'L');
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cb(15 downto 8) <= "HHHHHHHH";
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spw_rxdp <= spw_txdp; spw_rxsp <= spw_txsp;
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spw_rxdn <= spw_txdn; spw_rxsn <= spw_txsn;
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roen <= '0';
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promedac <= '0';
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prom32 <= '1';
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rxd2 <= txd2;
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d3 : entity work.leon3mp
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generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
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port map (rst, clksel, clk, lock, error, wdogn, address, data,
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cb(7 downto 0), sdclk, sdcsn, sdwen,
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sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
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txd1, rxd1, txd2, rxd2,
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ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
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prom32, promedac,
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spw_clksel, spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp, spw_txdn,
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spw_txsp, spw_txsn, gnd(0), roen, roout, nandout, test);
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-- optional sdram
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sdcke <= "11";
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sd0 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 0) generate
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u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
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PORT MAP(
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Dq => data(31 downto 16), Addr => address(14 downto 2),
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Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
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Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm => sddqm(3 downto 2));
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u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
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PORT MAP(
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Dq => data(15 downto 0), Addr => address(14 downto 2),
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Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
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Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm => sddqm(1 downto 0));
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u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
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PORT MAP(
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Dq => data(31 downto 16), Addr => address(14 downto 2),
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Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
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Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm => sddqm(3 downto 2));
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u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
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PORT MAP(
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Dq => data(15 downto 0), Addr => address(14 downto 2),
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Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
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Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm => sddqm(1 downto 0));
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end generate;
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prom0 : for i in 0 to (romwidth/8)-1 generate
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sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
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port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
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rwen(i), oen);
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end generate;
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sram0 : for i in 0 to (sramwidth/8)-1 generate
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sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
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port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
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rwen(0), ramoen(0));
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end generate;
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iuerr : process
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begin
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wait for 2500 ns;
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if to_x01(error) = '1' then wait on error; end if;
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assert (to_x01(error) = '1')
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report "*** IU in error mode, simulation halted ***"
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severity failure ;
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end process;
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test0 : grtestmod
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port map ( rst, clk, error, address(21 downto 2), data,
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iosn, oen, writen, brdyn);
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data <= buskeep(data) after 5 ns;
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cb <= buskeep(cb) after 5 ns;
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dsucom : process
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procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
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variable w32 : std_logic_vector(31 downto 0);
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variable c8 : std_logic_vector(7 downto 0);
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constant txp : time := clkperiod*16 * 1 ns;
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begin
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dsutx <= '1';
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dsurst <= '0';
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wait for 500 ns;
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dsurst <= '1';
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wait; -- remove to run the DSU UART
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wait for 5010 ns;
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txc(dsutx, 16#55#, txp); -- sync uart
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txc(dsutx, 16#55#, txp); -- sync uart
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
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txc(dsutx, 16#80#, txp);
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txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
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rxi(dsurx, w32, txp, lresp);
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wait;
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0e#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#06#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
|
| 279 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
|
| 280 |
|
|
|
| 281 |
|
|
txc(dsutx, 16#c0#, txp);
|
| 282 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
| 283 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
|
| 284 |
|
|
|
| 285 |
|
|
txc(dsutx, 16#c0#, txp);
|
| 286 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
|
| 287 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
|
| 288 |
|
|
|
| 289 |
|
|
txc(dsutx, 16#c0#, txp);
|
| 290 |
|
|
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
|
| 291 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
|
| 292 |
|
|
txc(dsutx, 16#c0#, txp);
|
| 293 |
|
|
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
|
| 294 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
|
| 295 |
|
|
|
| 296 |
|
|
|
| 297 |
|
|
|
| 298 |
|
|
|
| 299 |
|
|
|
| 300 |
|
|
txc(dsutx, 16#c0#, txp);
|
| 301 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
| 302 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
|
| 303 |
|
|
|
| 304 |
|
|
txc(dsutx, 16#c0#, txp);
|
| 305 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
|
| 306 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
|
| 307 |
|
|
|
| 308 |
|
|
txc(dsutx, 16#c0#, txp);
|
| 309 |
|
|
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
|
| 310 |
|
|
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
|
| 311 |
|
|
|
| 312 |
|
|
txc(dsutx, 16#80#, txp);
|
| 313 |
|
|
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
| 314 |
|
|
rxi(dsurx, w32, txp, lresp);
|
| 315 |
|
|
|
| 316 |
|
|
txc(dsutx, 16#a0#, txp);
|
| 317 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
|
| 318 |
|
|
rxi(dsurx, w32, txp, lresp);
|
| 319 |
|
|
|
| 320 |
|
|
end;
|
| 321 |
|
|
|
| 322 |
|
|
begin
|
| 323 |
|
|
|
| 324 |
|
|
dsucfg(dsutx, dsurx);
|
| 325 |
|
|
|
| 326 |
|
|
wait;
|
| 327 |
|
|
end process;
|
| 328 |
|
|
|
| 329 |
|
|
end ;
|
| 330 |
|
|
|
