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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-asic/] [testbench_netlist.vhd] - Blame information for rev 2

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1 2 dimamali 
------------------------------------------------------------------------------
2 
--  LEON3 Demonstration design test bench
3 
--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 
--
5 
--  This program is free software; you can redistribute it and/or modify
6 
--  it under the terms of the GNU General Public License as published by
7 
--  the Free Software Foundation; either version 2 of the License, or
8 
--  (at your option) any later version.
9 
--
10 
--  This program is distributed in the hope that it will be useful,
11 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
--  GNU General Public License for more details.
14 
------------------------------------------------------------------------------
15 
 
16 
library ieee;
17 
use ieee.std_logic_1164.all;
18 
library gaisler;
19 
use gaisler.libdcom.all;
20 
use gaisler.sim.all;
21 
use work.debug.all;
22 
library techmap;
23 
use techmap.gencomp.all;
24 
library micron;
25 
use micron.components.all;
26 
use gaisler.jtagtst.all;
27 
library dare;
28 
 
29 
use work.config.all;    -- configuration
30 
 
31 
entity testbench_netlist is
32 
  generic (
33 
    fabtech   : integer := CFG_FABTECH;
34 
    memtech   : integer := CFG_MEMTECH;
35 
    padtech   : integer := CFG_PADTECH;
36 
    clktech   : integer := CFG_CLKTECH;
37 
    disas     : integer := CFG_DISAS;   -- Enable disassembly to console
38 
    dbguart   : integer := CFG_DUART;   -- Print UART on console
39 
    pclow     : integer := CFG_PCLOW;
40 
 
41 
    clkperiod : integer := 1000;                -- system clock period
42 
    romwidth  : integer := 32;          -- rom data width (8/32)
43 
    romdepth  : integer := 16;          -- rom address depth
44 
    sramwidth  : integer := 32;         -- ram data width (8/16/32)
45 
    sramdepth  : integer := 18;         -- ram address depth
46 
    srambanks  : integer := 2;          -- number of ram banks
47 
    testen  : integer := 0;
48 
    scanen  : integer := 0;
49 
    testrst : integer := 0;
50 
    testoen : integer := 0
51 
  );
52 
end;
53 
 
54 
architecture behav of testbench_netlist is
55 
 
56 
constant promfile  : string := "prom.srec";  -- rom contents
57 
constant sramfile  : string := "sram.srec";  -- ram contents
58 
constant sdramfile : string := "sdram.srec"; -- sdram contents
59 
signal clk : std_logic := '0';
60 
signal Rst    : std_logic := '0';                        -- Reset
61 
constant ct : integer := clkperiod/2;
62 
 
63 
signal address  : std_logic_vector(27 downto 0);
64 
signal data     : std_logic_vector(31 downto 0);
65 
signal cb  : std_logic_vector(15 downto 0);
66 
 
67 
signal ramsn    : std_logic_vector(4 downto 0);
68 
signal ramoen   : std_logic_vector(4 downto 0);
69 
signal rwen     : std_logic_vector(3 downto 0);
70 
signal rwenx    : std_logic_vector(3 downto 0);
71 
signal romsn    : std_logic_vector(1 downto 0);
72 
signal iosn     : std_ulogic;
73 
signal oen      : std_ulogic;
74 
signal read     : std_ulogic;
75 
signal writen   : std_ulogic;
76 
signal brdyn    : std_ulogic;
77 
signal bexcn    : std_ulogic;
78 
signal wdogn    : std_logic;
79 
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
80 
signal dsurst   : std_ulogic;
81 
signal test     : std_ulogic;
82 
signal error    : std_logic;
83 
signal gpio     : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
84 
signal VCC      : std_ulogic := '1';
85 
signal NC       : std_ulogic := 'Z';
86 
signal clk2     : std_ulogic := '1';
87 
 
88 
signal sdcke    : std_logic_vector ( 1 downto 0);  -- clk en
89 
signal sdcsn    : std_logic_vector ( 1 downto 0);  -- chip sel
90 
signal sdwen    : std_ulogic;                       -- write en
91 
signal sdrasn   : std_ulogic;                       -- row addr stb
92 
signal sdcasn   : std_ulogic;                       -- col addr stb
93 
signal sddqm    : std_logic_vector ( 3 downto 0);  -- data i/o mask
94 
signal sdclk    : std_ulogic := '0';
95 
signal plllock    : std_ulogic;
96 
signal txd1, rxd1 : std_ulogic;
97 
signal txd2, rxd2 : std_ulogic;
98 
signal roen, roout, nandout, promedac : std_ulogic;
99 
 
100 
constant lresp : boolean := false;
101 
 
102 
signal gnd      : std_logic_vector(3 downto 0);
103 
signal clksel   : std_logic_vector(1 downto 0);
104 
signal promwidth: std_logic_vector(1 downto 0);
105 
signal spw_clksel : std_logic_vector(1 downto 0);
106 
 
107 
signal spw_clk  : std_ulogic := '0';
108 
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1);
109 
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1);
110 
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
111 
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
112 
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1);
113 
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1);
114 
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
115 
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
116 
 
117 
begin
118 
 
119 
-- clock and reset
120 
 
121 
  test <= '0' when testen  = 0 else '1';
122 
  rxd1 <= '1' when (testen = 1) and (testoen = 1) else
123 
          '0' when (testen = 1) and (testoen = 0) else txd1;
124 
  dsuen <= '1' when (testen = 1) and (testrst = 1) else
125 
          '0' when (testen = 1) and (testrst = 0) else '1';
126 
  dsubre <= '1' when (testen = 1) and (scanen = 1) else
127 
          '0' when (testen = 1) and (scanen = 0) else '0';
128 
 
129 
  clksel <= "00";
130 
  spw_clksel <= "00";
131 
  error <= 'H';
132 
  gnd <= "0000";
133 
  clk <= not clk after ct * 1 ns;
134 
  spw_clk <= not spw_clk after 10 ns;
135 
  rst <= dsurst;
136 
  bexcn <= '1'; wdogn <= 'H';
137 
  gpio(2 downto 0) <= "HHL";
138 
--  gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
139 
  gpio(15 downto 11) <= "HLLHH"; --19
140 
  gpio(10 downto 8) <= "HLL"; --4
141 
  gpio(7 downto 0) <= (others => 'L');
142 
  cb(15 downto 8) <= "HHHHHHHH";
143 
  spw_rxdp <= spw_txdp; spw_rxsp <= spw_txsp;
144 
  spw_rxdn <= spw_txdn; spw_rxsn <= spw_txsn;
145 
  roen <= '0';
146 
  promedac <= '0';
147 
  promwidth <= "10";
148 
  rxd2 <= txd2;
149 
 
150 
  d3 : entity dare.leon3mp
151 
        port map (rst, clksel, clk, error, wdogn, address, data,
152 
        cb(7 downto 0), sdclk, sdcsn, sdwen,
153 
        sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
154 
        txd1, rxd1, txd2, rxd2,
155 
        ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
156 
        promwidth, promedac,
157 
        spw_clksel, spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp, spw_txdn,
158 
        spw_txsp, spw_txsn, gnd(0), roen, roout, nandout, test);
159 
 
160 
-- optional sdram
161 
 
162 
  sd0 : if (CFG_MCTRLFT_SDEN = 1) and (CFG_MCTRLFT_SEPBUS = 0) generate
163 
    u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
164 
        PORT MAP(
165 
            Dq => data(31 downto 16), Addr => address(14 downto 2),
166 
            Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
167 
            Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
168 
            Dqm => sddqm(3 downto 2));
169 
    u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
170 
        PORT MAP(
171 
            Dq => data(15 downto 0), Addr => address(14 downto 2),
172 
            Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
173 
            Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
174 
            Dqm => sddqm(1 downto 0));
175 
    cb0: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
176 
        PORT MAP(
177 
            Dq => cb(15 downto 0), Addr => address(14 downto 2),
178 
            Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
179 
            Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
180 
            Dqm => sddqm(1 downto 0));
181 
    u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
182 
        PORT MAP(
183 
            Dq => data(31 downto 16), Addr => address(14 downto 2),
184 
            Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
185 
            Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
186 
            Dqm => sddqm(3 downto 2));
187 
    u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
188 
        PORT MAP(
189 
            Dq => data(15 downto 0), Addr => address(14 downto 2),
190 
            Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
191 
            Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
192 
            Dqm => sddqm(1 downto 0));
193 
    cb1: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
194 
        PORT MAP(
195 
            Dq => cb(15 downto 0), Addr => address(14 downto 2),
196 
            Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
197 
            Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
198 
            Dqm => sddqm(1 downto 0));
199 
  end generate;
200 
 
201 
  prom0 : for i in 0 to (romwidth/8)-1 generate
202 
      sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
203 
        port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
204 
                  rwen(i), oen);
205 
  end generate;
206 
 
207 
  promcb0 : sramft generic map (index => 7, abits => romdepth, fname => promfile)
208 
        port map (address(romdepth+1 downto 2), cb(7 downto 0), romsn(0), writen, oen);
209 
 
210 
  sram0 : for i in 0 to (sramwidth/8)-1 generate
211 
      sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
212 
        port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
213 
                  rwen(0), ramoen(0));
214 
  end generate;
215 
 
216 
  sramcb0 : sramft generic map (index => 7, abits => sramdepth, fname => sramfile)
217 
        port map (address(sramdepth+1 downto 2), cb(7 downto 0), ramsn(0), rwen(0), ramoen(0));
218 
 
219 
   iuerr : process
220 
   begin
221 
     wait for (100*clkperiod) * 1 ns;
222 
     if to_x01(error) = '1' then wait on error; end if;
223 
     assert (to_x01(error) = '1')
224 
       report "*** IU in error mode, simulation halted ***"
225 
         severity failure ;
226 
   end process;
227 
 
228 
  test0 :  grtestmod
229 
    port map ( rst, clk, error, address(21 downto 2), data,
230 
               iosn, oen, writen, brdyn);
231 
 
232 
  data <= buskeep(data), (others => 'H') after 250 ns;
233 
  cb <= buskeep(cb), (others => 'H') after 250 ns;
234 
 
235 
  dsucom : process
236 
    procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
237 
    variable w32 : std_logic_vector(31 downto 0);
238 
    variable c8  : std_logic_vector(7 downto 0);
239 
    constant txp : time := clkperiod*16 * 1 ns;
240 
    begin
241 
    dsutx <= '1';
242 
    dsurst <= '0';
243 
    wait for 500 ns;
244 
    dsurst <= '1';
245 
    wait;       -- remove to run the DSU UART
246 
    wait for 5010 ns;
247 
    txc(dsutx, 16#55#, txp);            -- sync uart
248 
 
249 
--    txc(dsutx, 16#c0#, txp);
250 
--    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
251 
--    txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
252 
--    txc(dsutx, 16#c0#, txp);
253 
--    txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
254 
--    txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
255 
--    txc(dsutx, 16#c0#, txp);
256 
--    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
257 
--    txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
258 
--    txc(dsutx, 16#c0#, txp);
259 
--    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
260 
--    txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
261 
 
262 
    txc(dsutx, 16#c0#, txp);
263 
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
264 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
265 
    txc(dsutx, 16#c0#, txp);
266 
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
267 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
268 
    txc(dsutx, 16#c0#, txp);
269 
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
270 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0e#, txp);
271 
    txc(dsutx, 16#c0#, txp);
272 
    txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
273 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
274 
    txc(dsutx, 16#c0#, txp);
275 
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
276 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#06#, txp);
277 
    txc(dsutx, 16#c0#, txp);
278 
    txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
279 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
280 
    txc(dsutx, 16#c0#, txp);
281 
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
282 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
283 
    txc(dsutx, 16#c0#, txp);
284 
    txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
285 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
286 
 
287 
    txc(dsutx, 16#c0#, txp);
288 
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
289 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
290 
 
291 
    txc(dsutx, 16#c0#, txp);
292 
    txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
293 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
294 
 
295 
    txc(dsutx, 16#c0#, txp);
296 
    txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
297 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
298 
    txc(dsutx, 16#c0#, txp);
299 
    txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
300 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
301 
 
302 
 
303 
 
304 
 
305 
 
306 
    txc(dsutx, 16#c0#, txp);
307 
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
308 
    txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
309 
 
310 
    txc(dsutx, 16#c0#, txp);
311 
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
312 
    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
313 
 
314 
    txc(dsutx, 16#c0#, txp);
315 
    txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
316 
    txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
317 
 
318 
    txc(dsutx, 16#80#, txp);
319 
    txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
320 
    rxi(dsurx, w32, txp, lresp);
321 
 
322 
    txc(dsutx, 16#a0#, txp);
323 
    txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
324 
    rxi(dsurx, w32, txp, lresp);
325 
 
326 
    end;
327 
 
328 
  begin
329 
 
330 
    dsucfg(dsutx, dsurx);
331 
 
332 
    wait;
333 
  end process;
334 
 
335 
end ;
336 
 

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