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dimamali |
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set_operating_conditions -library RH_UMC018_IOLIB_WCMIL WCMIL
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set_operating_conditions -library RH_UMC018_LVDSLIB_WCMIL WCMIL
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set_operating_conditions -library RadHardUMC18_CORE_STD_WCMIL WCMIL
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set_operating_conditions -library RadHardUMC18_CORE_HIT_WCMIL WCMIL
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set_wire_load_mode segmented
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set auto_wire_load_selection "true"
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set_wire_load_mode segmented
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set sys_clk_freq 300.0
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set spw_clk_freq 300.0
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set clock_skew 0.10
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set input_setup 2.0
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set output_delay 6.0
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set sys_peri [expr 1000.0 / $sys_clk_freq]
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set spw_peri [expr 1000.0 / $spw_clk_freq]
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set spw_rxperi [expr 1500.0 / $spw_clk_freq]
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set input_delay [expr $sys_peri - $input_setup]
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set tdelay [expr $output_delay + 1]
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create_clock -name "clk" -period $sys_peri {"core0/leon3core0/clk" }
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set_dont_touch_network clk
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create_clock -name "spw_txclk" -period $spw_peri { "core0/leon3core0/spw_clk"}
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set_dont_touch_network spw_txclk
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create_clock -name "spw_rxclk0" -period $spw_peri { "core0/leon3core0/grspw0_0/grspwc0/rx0_0/rxclko" }
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#create_clock -name "spw_rxclk0" -period $spw_peri { "spw_rxsp[0]" }
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set_dont_touch_network spw_rxclk0
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create_clock -name "spw_rxclk1" -period $spw_peri { "core0/leon3core0/grspw0_1/grspwc0/rx0_0/rxclko" }
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#create_clock -name "spw_rxclk1" -period $spw_peri { "spw_rxsp[1]" }
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set_dont_touch_network spw_rxclk1
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set_false_path -from resetn
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set_false_path -from testen
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set_ideal_network testen
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set_false_path -from rxd1
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set_false_path -from dsubre
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set_false_path -from dsuen
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set_false_path -from dsurx
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set_false_path -to dsuact
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set_false_path -from clk -to spw_txclk
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set_false_path -to clk -from spw_txclk
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set_false_path -from clk -to spw_rxclk0
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set_false_path -to clk -from spw_rxclk0
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set_false_path -from clk -to spw_rxclk1
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set_false_path -to clk -from spw_rxclk1
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set_false_path -from spw_txclk -to spw_rxclk0
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set_false_path -to spw_txclk -from spw_rxclk0
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set_false_path -from spw_txclk -to spw_rxclk1
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set_false_path -to spw_txclk -from spw_rxclk1
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set_false_path -from core0/leon3core0/ftmctrl0/rst -to [get_ports {data* cb*}]
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set_false_path -from core0/leon3core0/grgpio0/rst -to [get_ports {gpio*}]
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set_input_delay $input_delay -clock clk { \
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gpio\[*\] data\[*\] brdyn bexcn cb\[*\] }
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set_max_delay $output_delay -to { data\[*\] cb\[*\] }
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set_max_delay 15 -to { errorn wdogn txd1 gpio\[*\] }
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set_max_delay $output_delay -to { \
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writen romsn\[*\] read oen iosn rwen\[*\] ramsn\[*\] \
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ramoen\[*\] sdcsn\[*\] sdwen sdrasn sdcasn \
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sddqm\[*\] address\[*\] \
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}
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#set_load 8.0 [all_outputs]
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#set_load 50 { address\[2\] address\[3\] address\[4\] address\[5\] \
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address\[6\] address\[7\] address\[8\] address\[9\] address\[10\] \
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address\[11\] address\[12\] address\[13\] address\[14\] address\[15\] \
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address\[16\] address\[17\] address\[18\] address\[19\] address\[20\]}
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#set_load 20 [get_ports {data* cb*}]
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set_critical_range 2.0 leon3mp
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