OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-avnet-3s1500/] [index.html] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
2
<html><head>
3
  <meta http-equiv="CONTENT-TYPE" content="text/html; charset=iso-8859-1"><title>LEON3MP Reference Design</title>
4
 
5
  <meta name="GENERATOR" content="OpenOffice.org 1.1.0  (Linux)">
6
  <meta name="CREATED" content="20040423;18351200">
7
  <meta name="CHANGED" content="20040426;16351800"></head>
8
<body dir="ltr" lang="en-US">
9
<table border="0" cellpadding="2" cellspacing="2" width="750">
10
  <tbody>
11
    <tr>
12
      <td valign="top">
13
      <h3><span style="font-family: helvetica,arial,sans-serif;">LEON3MP for the Avnet Spartan3-1500 evaluation board<br>
14
</span></h3>
15
 
16
 
17
      <h4 style="font-family: helvetica,arial,sans-serif;">Introduction</h4>
18
 
19
      <small><span style="font-family: helvetica,arial,sans-serif;">The
20
LEON3MP provides a reference
21
design for LEON3-based systems. This version is specifically tailored
22
for the <a href="http://www.em.avnet.com/evk/home/0,4534,CID%253D7816%2526CCD%253DUSA%2526SID%253DNoNav%2526DID%253DDF2%2526LID%253DNoNav%25255F%2526BID%253DDF2%2526CTP%253DEVK,00.html">Avnet Spartan3-1500 evaluation board</a>. It can be configured
23
with the following blocks:<br>
24
<br>
25
</span></small>
26
      <table cellpadding="2" cellspacing="2" width="700">
27
 
28
  <tbody>
29
    <tr>
30
      <td valign="top">
31
      <ul><li><small><span style="font-family: helvetica,arial,sans-serif;">1 -
32
4 LEON3 processor
33
cores with MP support</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Multi-processor
34
debug support unit (DSU) for LEON3</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">On-chip boot-prom<br>
35
    </span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit SRAM controller</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Round-robin
36
AHB arbiter and controller with plug&amp;play support</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">AHB/APB bridge with
37
plug&amp;play support<br>
38
    </span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Multi-processor
39
interrupt controller</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit modular timer
40
unit</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">UART with FIFO<br>
41
    </span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">10/100 ethernet MAC</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit, 33 MHz PCI interface (master/target, FIFO, DMA)<br>
42
    </span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">JTAG debug communication link<br>
43
    </span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Serial debug
44
communication link</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Etherner debug
45
communication link</span></small></li></ul>
46
      </td>
47
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"><img alt="" src="../../boards/avnet-xc3s1500/Xilinx-Spartan3-Eval_Kit.jpg" align="right" height="167" width="252"></span></small></td>
48
    </tr>
49
  </tbody>
50
      </table>
51
 
52
      <small><span style="font-family: helvetica,arial,sans-serif;"><br>
53
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
54
The&nbsp; LEON3 MP design is provided together with GRLIB, and is
55
located in grlib/designs/leon3-avnet-3s1500<br>
56
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
57
</span></small>
58
      <h4><span style="font-family: helvetica,arial,sans-serif;">Reference
59
architecture</span></h4>
60
 
61
      <small><span style="font-family: helvetica,arial,sans-serif;">The
62
LEON3MP is made up by cores from the GRLIB IP library, which are
63
connected together via the AMBA AHB and APB buses. The plug&amp;play
64
configuration method of GRLIB makes it possible to assign any
65
combination of addresses and interrupts to the cores. However, to be
66
software compatible with simple operating systems such as the LEON
67
Bare-C cross-compiler, some of the vital cores must be assigned to
68
predefined addresses and interrupts. The table below shows the
69
reference assigment in the LEON3MP design:<br>
70
<br>
71
</span></small>
72
      <table style="width: 100%; text-align: left;" border="1" cellpadding="2" cellspacing="2">
73
 
74
  <tbody>
75
    <tr>
76
      <th style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Core</span></small></th>
77
      <th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Memory area<br>
78
      </span></small></th>
79
      <th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt</span></small></th>
80
    </tr>
81
    <tr>
82
      <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">On-chip boot-prom<br>
83
      </span></small></td>
84
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x00000000 -
85
0x20000000 : PROM<br>
86
      </span></small></td>
87
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
88
    </tr>
89
    <tr>
90
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">SRAM Controller</span></small></td>
91
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">
92
0x40000000 - 0x80000000 : 1 Mbyte SRAM</span></small></td>
93
      <td valign="top"><br>
94
      </td>
95
    </tr>
96
<tr>
97
      <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">APB bridge<br>
98
      </span></small></td>
99
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000000 -
100
0x80100000 : APB bus<br>
101
      </span></small></td>
102
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
103
    </tr>
104
    <tr>
105
      <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">UART</span></small></td>
106
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000100 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000200 : UART
107
registers</span></small></td>
108
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">2</span></small><br>
109
      </td>
110
    </tr>
111
    <tr>
112
      <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt controller</span></small><br>
113
      </td>
114
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000200 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000300 : IRQ
115
registers<br>
116
      </span></small></td>
117
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
118
    </tr>
119
    <tr>
120
      <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Timer unit<br>
121
      </span></small></td>
122
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000300</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0x80000400 : timer
123
registers<br>
124
      </span></small></td>
125
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">8, 9<br>
126
      </span></small></td>
127
    </tr>
128
    <tr>
129
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">LEON3 debug support
130
unit (DSU)<br>
131
      </span></small></td>
132
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x90000000 -
133
0xA0000000 : DSU registers<br>
134
      </span></small></td>
135
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
136
    </tr>
137
  </tbody>
138
      </table>
139
 
140
      <small><span style="font-family: helvetica,arial,sans-serif;"><br>
141
Additional (optional) IP cores are assigned addresses and interrupts as
142
desribed in the table below. These assignments are LEON3MP specific and
143
can be changed without impact on software compatibility.<br>
144
<br>
145
</span></small>
146
      <table style="width: 100%; text-align: left;" border="1" cellpadding="2" cellspacing="2">
147
 
148
  <tbody>
149
    <tr>
150
      <th style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Core</span></small></th>
151
      <th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Memory area<br>
152
      </span></small></th>
153
      <th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt</span></small></th>
154
    </tr>
155
 
156
 
157
 
158
    <tr>
159
      <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Serial debug
160
communication link<br>
161
      </span></small></td>
162
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000700 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000800 : AHB UART
163
registers</span></small></td>
164
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small> </td>
165
    </tr>
166
    <tr>
167
      <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Ethernet debug
168
communication link</span></small><br>
169
      </td>
170
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
171
      </span></small></td>
172
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small> </td>
173
    </tr>
174
    <tr>
175
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">JTAG debug
176
communication link</span></small></td>
177
      <td valign="top">-<br>
178
      </td>
179
      <td valign="top"><br>
180
      </td>
181
    </tr>
182
<tr>
183
      <td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">10/100 Mbit ethernet MAC<br>
184
      </span></small></td>
185
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xFFFB0000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xFFFB1000 :
186
ethernet
187
control registers<br>
188
      </span></small></td>
189
      <td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">12</span></small></td>
190
    </tr>
191
    <tr>
192
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">PCI interface</span></small></td>
193
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xE0000000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0x00000000 : PCI bus<br>
194
</span></small></td>
195
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">13</span></small></td>
196
    </tr>
197
    <tr>
198
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">On-chip RAM<br>
199
 
200
      </span></small></td>
201
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xA0000000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xA0100000 : On-chip
202
RAM<br>
203
      </span></small></td>
204
      <td valign="top"><br>
205
      </td>
206
    </tr>
207
 
208
  </tbody>
209
      </table>
210
 
211
      <br>
212
 
213
      <h4><small><span style="font-family: helvetica,arial,sans-serif;">
214
</span></small></h4>
215
 
216
      <h4><span style="font-family: helvetica,arial,sans-serif;">Configuration</span></h4>
217
 
218
      <div style="text-align: left;"><small><span style="font-family: helvetica,arial,sans-serif;">The configuartion of
219
the LEON3MP design is defined through the config package located <a href="config.vhd">config.vhd</a>.
220
This file can be automatically generated using a GUI based on tkconfig.
221
To launch the GUI, do 'make xconfig'. After the configuration is
222
completed, save and
223
exit the tool and config.vhd will be created automatically.
224
<br>
225
<br>
226
<br>
227
<img alt="" src="../share/gui.gif" height="148" width="561"><br>
228
<br>
229
<i>Figure 1. LEON3MP configuration GUI<br>
230
<br>
231
</i></span></small><small><span style="font-family: helvetica,arial,sans-serif;">The
232
design is pre-configured in a suitable manner for the Avnet board. The
233
32-bit SRAM is used to access the on-board 1 Mbyte SRAM. The PCI and
234
ethernet interface can also be enabled and are fully functional. The 66
235
MHz board oscillator is multiplied with 3/5 by
236
an on-chip DCM to generate 40 MHz frequency.</span></small><br style="font-family: helvetica,arial,sans-serif;">
237
<small>
238
</small></div>
239
 
240
      <h4><span style="font-family: helvetica,arial,sans-serif;">Simulation</span></h4>
241
 
242
      <small><span style="font-family: helvetica,arial,sans-serif;">To
243
simulate the testbench, first compile the model for simulation. This
244
can be done automatically for three different simulators. Execute one
245
of the following commands:</span><br style="font-family: helvetica,arial,sans-serif;">
246
      </small>
247
      <ul style="font-family: helvetica,arial,sans-serif;">
248
<li><small>make vsim</small></li><li><small>make ncsim</small></li><li><small>make ghdl</small></li>
249
      </ul>
250
 
251
      <small><span style="font-family: helvetica,arial,sans-serif;">For vsim,
252
start the simulation with 'vsim testbench' and do 'run 100'. This
253
should print the current LEON3MP configuration:</span><br style="font-family: helvetica,arial,sans-serif;">
254
      </small><br>
255
 
256
      <small><span style="font-family: courier new,courier,monospace;">$ vsim
257
-c -quiet testbench</span><br style="font-family: courier new,courier,monospace;">
258
<span style="font-family: courier new,courier,monospace;">Reading
259
/usr/local/model58/tcl/vsim/pref.tcl</span><br style="font-family: courier new,courier,monospace;">
260
<span style="font-family: courier new,courier,monospace;">Reading
261
/home/jiri/modelsim.tcl</span><br style="font-family: courier new,courier,monospace;">
262
      </small><small><span style="font-family: courier new,courier,monospace;"></span></small><br style="font-family: courier new,courier,monospace;">
263
 
264
      <small><span style="font-family: courier new,courier,monospace;"># 5.8</span><br style="font-family: courier new,courier,monospace;">
265
      </small><small><span style="font-family: courier new,courier,monospace;"></span><big><tt>#
266
VSIM 1&gt; run<br>
267
# LEON3 Demonstration design<br>
268
# GRLIB Version 0.13<br>
269
# Target technology: virtex2 ,&nbsp; memory library: virtex2<br>
270
# ahbctrl: mst0: Gaisler
271
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Leon3 SPARC V8
272
Processor<br>
273
# ahbctrl: mst1: Gaisler
274
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AHB Debug UART<br>
275
# ahbctrl: mst2: Gaisler
276
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fast 32-bit PCI
277
Bridge<br>
278
# ahbctrl: mst3: Gaisler
279
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AMBA DMA controller<br>
280
# ahbctrl: mst5: Gaisler
281
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OC ethernet AHB
282
interface<br>
283
# ahbctrl: slv0: Gaisler
284
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Simple SRAM
285
Controller<br>
286
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0x00000000,
287
size 16 Mbyte, cacheable, prefetch<br>
288
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0x40000000,
289
size 16 Mbyte, cacheable, prefetch<br>
290
# ahbctrl: slv1: Gaisler
291
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AHB/APB Bridge<br>
292
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0x80000000,
293
size 1 Mbyte<br>
294
# ahbctrl: slv2: Gaisler
295
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Leon3 Debug Support
296
Unit<br>
297
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0x90000000,
298
size 256 Mbyte<br>
299
# ahbctrl: slv4: Gaisler
300
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fast 32-bit PCI
301
Bridge<br>
302
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0xe0000000,
303
size 256 Mbyte<br>
304
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O port at 0xfff80000,
305
size 128kbyte<br>
306
# ahbctrl: slv5: Gaisler
307
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OC ethernet AHB
308
interface<br>
309
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O port at 0xfffb0000,
310
size 4kbyte<br>
311
# ahbctrl: slv6: Gaisler
312
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OC CAN AHB interface<br>
313
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O port at 0xfffc0000,
314
size 4kbyte<br>
315
# ahbctrl: slv7: Gaisler
316
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Generic AHB SRAM
317
module<br>
318
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0xa0000000,
319
size 1 Mbyte, cacheable, prefetch<br>
320
# ahbctrl: AHB arbiter/multiplexer rev 1<br>
321
# ahbctrl: Common I/O area at 0xfff00000, 1 Mbyte<br>
322
# ahbctrl: Configuration area at 0xfffff000, 4 kbyte<br>
323
# apbctrl: APB Bridge at 0x80000000 rev 1<br>
324
# apbctrl: slv1: Gaisler
325
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Generic UART<br>
326
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000100,
327
size 256 byte<br>
328
# apbctrl: slv2: Gaisler
329
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Multi-processor
330
Interrupt Ctrl.<br>
331
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000200,
332
size 256 byte<br>
333
# apbctrl: slv3: Gaisler
334
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Modular Timer Unit<br>
335
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000300,
336
size 256 byte<br>
337
# apbctrl: slv4: Gaisler
338
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fast 32-bit PCI
339
Bridge<br>
340
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000400,
341
size 256 byte<br>
342
# apbctrl: slv5: Gaisler
343
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AMBA DMA controller<br>
344
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000500,
345
size 256 byte<br>
346
# apbctrl: slv7: Gaisler
347
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AHB Debug UART<br>
348
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000700,
349
size 256 byte<br>
350
# ahbram7: AHB SRAM Module rev 1, 2 kbytes<br>
351
# can_oc6: Opencores CAN MAC, rev 0, irq 13<br>
352
# eth_oc5: Wishbone/AHB interface for OC ethernet MAC, irq 12<br>
353
# eth_oc5: Opencores 10/100 Mbit ethernet MAC, rev 0<br>
354
# pci_mtf4: 32-bit PCI/AHB bridge&nbsp; rev 0, 2 Mbyte PCI memory BAR,
355
8-word FIFOs<br>
356
# dmactrl5: 32-bit DMA controller &amp; AHB/AHB bridge&nbsp; rev 0<br>
357
# gptimer3: GR Timer Unit rev 0, 16-bit scaler, 1 32-bit timers, irq 8<br>
358
# irqmp: Multi-processor Interrupt Controller rev 1, #cpu 1<br>
359
# apbuart1: Generic UART rev 1, irq 2<br>
360
# srctrl0: 32-bit PROM/SRAM controller rev 0<br>
361
# ahbuart7: AHB Debug UART rev 0<br>
362
# dsu3_2: LEON3 Debug support unit<br>
363
# leon3_0: LEON3 SPARC V8 processor rev 0<br>
364
# leon3_0: icache 1*4 kbyte, dcache 1*4 kbyte</tt></big><br style="font-family: courier new,courier,monospace;">
365
<span style="font-family: courier new,courier,monospace;"></span><span style="font-family: courier new,courier,monospace;"></span><br style="font-family: courier new,courier,monospace;">
366
<span style="font-family: courier new,courier,monospace;">VSIM 2&gt;
367
run -all<br>
368
##<br>
369
# **** GRLIB system test starting ****<br>
370
# Leon3 SPARC V8 Processor<br>
371
#&nbsp;&nbsp; register file<br>
372
#&nbsp;&nbsp; multiplier<br>
373
#&nbsp;&nbsp; radix-2 divider<br>
374
#&nbsp;&nbsp; cache system<br>
375
# Multi-processor Interrupt Ctrl.<br>
376
# Generic UART<br>
377
# Modular Timer Unit<br>
378
# Test passed, halting with IU error mode<br>
379
#<br>
380
# ** Failure: *** IU in error mode, simulation halted ***<br>
381
VSIM 2&gt;</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
382
</span></small>
383
      <h4><small><span style="font-family: helvetica,arial,sans-serif;">Synthesis<br>
384
</span></small></h4>
385
 
386
      <h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
387
 
388
      <small><span style="font-family: helvetica,arial,sans-serif;">To
389
synthesize and place&amp;route, use the make utility and issue either 'make ise' or 'make ise-synp' to<br>
390
use the XST or Synplify tools respectively.<br>
391
<br>
392
</span></small><small><span style="font-family: helvetica,arial,sans-serif;">Alternatively, the design can be implemented using
393
the graphical XGrlib tool, which is started with 'make xgrlib'.</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
394
<br>
395
<br>
396
<img alt="" src="../../doc/grlib/xgrlib.gif" height="537" width="619"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">&nbsp;</span></small><br>
397
 
398
      <div style="text-align: justify;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></div>
399
 
400
      <small><span style="font-family: helvetica,arial,sans-serif;">
401
<br>
402
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><i>Figure 2. XGrlib
403
implementation tool</i></span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
404
<br>
405
</span></small><small><span style="font-family: helvetica,arial,sans-serif;">To program the fpga, issue 'make ise-prog-fpga'. To re-program the configuration proms, do 'make ise-prog-prom'.<br>
406
After programming the proms, power-cycle the board to re-load the fpga.<br>
407
<br>
408
</span></small><small><span style="font-family: helvetica,arial,sans-serif;">To get
409
started quicker, suitable leon3mp.bit and leon3mp.msk files are provided in the <i>bitfiles</i>
410
directory. The fpga or
411
configuration proms can be programmed directly with this configuration,
412
using the following commands: 'make ise-prog-fpga-ref' or <br>
413
'make
414
ise-prog-prom-ref '.</span></small>
415
      <h4><small><span style="font-family: helvetica,arial,sans-serif;">Software
416
development</span></small></h4>
417
 
418
      <h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
419
 
420
      <small><span style="font-family: helvetica,arial,sans-serif;">To
421
develop RTEMS applications, download and install the <a href="http://www.gaisler.se/bin/linux/rcc-1.0.0.pdf">LEON3 RTEMS
422
Cross-compiler</a> from gaisler.com. The LEON3 bsp automatically
423
detects
424
the location of UARTs, timers, interrupt controller and ethernet core
425
using the plug&amp;play information. </span></small><small><span style="font-family: helvetica,arial,sans-serif;">
426
A <a href="http://www.gaisler.com/doc/bcc.html">LEON3 bare-C compiler</a>
427
is also available for download from gaisler.com. Both the RTEMS
428
and the bare-C compilers now come with full source code for both the
429
low-level I/O routines as well as the mkprom prom builder. This should
430
allow users to adapt the run-time to their own needs. All sources are
431
provided under GNU GPL, contact <a href="mailto:sales@gaisler.com">Gaisler
432
Research</a> for commercial licenses of this software.<br>
433
<br>
434
A Leon3 port of uClinux and linux-2.6.11 is available in the <a href="http://www.gaisler.com/products/linux.html">snapgear
435
linux distribution</a>.<br>
436
</span></small>
437
      <h4><small><span style="font-family: helvetica,arial,sans-serif;">Debugging<br>
438
</span></small></h4>
439
 
440
      <small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">The
441
on-chip debug support unit (DSU) makes debugging of target hardware
442
relatively easy. </span></small><small><span style="font-family: helvetica,arial,sans-serif;">The
443
design support both serial, ethernet and JTAG debug interface, and the </span></small><small><span style="font-family: helvetica,arial,sans-serif;"> <a href="http://www.gaisler.com/products/grmon/grmon.html">GRMON debug
444
monitor</a></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> can be attached with a serial cable, over a LAN, or using the Xilinx JTAG programming cable. </span></small><small><span style="font-family: helvetica,arial,sans-serif;"> Note that when you use the ethernet or the JTAG
445
interface, you need specify the frequency of the AHB clock since it is
446
not auto-detected. </span></small><small><span style="font-family: helvetica,arial,sans-serif;">Below
447
is a log from a debug session.<br>
448
<br>
449
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">
450
<span style="font-family: courier new,courier,monospace;"><br>
451
$&nbsp; grmon -u -grlib -jtag -freq 40<br>
452
      <br>
453
&nbsp;GRMON - The LEON multi purpose monitor v1.0.9<br>
454
      <br>
455
&nbsp;Copyright (C) 2004, Gaisler Research - all rights reserved.<br>
456
&nbsp;For latest updates, go to http://www.gaisler.com/<br>
457
&nbsp;Comments or bug-reports to grmon@gaisler.com<br>
458
      <br>
459
      <br>
460
&nbsp;GRLIB DSU Monitor backend 1.0.2&nbsp; (professional version)<br>
461
      <br>
462
using JTAG cable on parallel port<br>
463
      <br>
464
&nbsp;initialising ...........<br>
465
      <br>&nbsp;Component&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
466
Vendor<br>
467
&nbsp;Leon3 SPARC V8 Processor&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Gaisler Research<br>
468
&nbsp;AHB Debug JTAG
469
TAP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
470
Gaisler Research<br>
471
&nbsp;Simple 32-bit PCI Target&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Gaisler Research<br>
472
&nbsp;AHB interface for 10/100 Mbit MA&nbsp;&nbsp;&nbsp;&nbsp; Gaisler Research<br>
473
&nbsp;Simple SRAM
474
Controller&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
475
Gaisler Research<br>
476
&nbsp;AHB/APB
477
Bridge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
478
Gaisler Research<br>
479
&nbsp;Leon3 Debug Support Unit&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Gaisler Research<br>
480
&nbsp;AHB interface for 10/100 Mbit MA&nbsp;&nbsp;&nbsp;&nbsp; Gaisler Research<br>
481
&nbsp;Generic APB
482
UART&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
483
Gaisler Research<br>
484
&nbsp;Multi-processor Interrupt Ctrl&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Gaisler Research<br>
485
&nbsp;Modular Timer
486
Unit&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
487
Gaisler Research<br>
488
      <br>
489
&nbsp;Use command 'info sys' to print a detailed report of attached cores<br>
490
      <br>
491
grmon[grlib]&gt; inf sys<br>
492
00.01:003&nbsp;&nbsp; Gaisler Research&nbsp; Leon3 SPARC V8 Processor (ver 0)<br>
493
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ahb master 0<br>
494
01.01:01c&nbsp;&nbsp; Gaisler Research&nbsp; AHB Debug JTAG TAP (ver 0)<br>
495
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ahb master 1<br>
496
02.01:012&nbsp;&nbsp; Gaisler Research&nbsp; Simple 32-bit PCI Target (ver 0)<br>
497
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ahb master 2<br>
498
03.01:005&nbsp;&nbsp; Gaisler Research&nbsp; AHB interface for 10/100 Mbit MA (ver 0)<br>
499
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ahb master 3<br>
500
00.01:008&nbsp;&nbsp; Gaisler Research&nbsp; Simple SRAM Controller (ver 0)<br>
501
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ahb: 00000000 - 01000000<br>
502
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ahb: 40000000 - 41000000<br>
503
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1024 kbyte static ram @ 0x40000000<br>
504
01.01:006&nbsp;&nbsp; Gaisler Research&nbsp; AHB/APB Bridge (ver 0)<br>
505
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ahb: 80000000 - 80100000<br>
506
02.01:004&nbsp;&nbsp; Gaisler Research&nbsp; Leon3 Debug Support Unit (ver 0)<br>
507
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ahb: 90000000 - a0000000<br>
508
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AHB trace 64 lines, stack pointer 0x400fffe0<br>
509
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU#0 win 8, hwbp 2, itrace 64, V8 mul/div, lddel 1<br>
510
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
511
icache 2 * 4 kbyte, 32 byte/line lru<br>
512
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
513
dcache 2 * 4 kbyte, 32 byte/line lru<br>
514
05.01:005&nbsp;&nbsp; Gaisler Research&nbsp; AHB interface for 10/100 Mbit MA (ver 0)<br>
515
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; irq 12<br>
516
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ahb: fffb0000 - fffb1000<br>
517
01.01:00c&nbsp;&nbsp; Gaisler Research&nbsp; Generic APB UART (ver 1)<br>
518
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; irq 2<br>
519
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; apb: 80000100 - 80000200<br>
520
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; baud rate 38400, DSU mode<br>
521
02.01:00d&nbsp;&nbsp; Gaisler Research&nbsp; Multi-processor Interrupt Ctrl (ver 2)<br>
522
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; apb: 80000200 - 80000300<br>
523
03.01:011&nbsp;&nbsp; Gaisler Research&nbsp; Modular Timer Unit (ver 0)<br>
524
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; irq 8<br>
525
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; apb: 80000300 - 80000400<br>
526
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 8-bit scaler, 2 * 32-bit timers, divisor 40<br>
527
      <br>
528
grmon[grlib]&gt; lo /opt/sparc-elf/src/examples/stanford<br>
529
section: .text at 0x40000000, size 61200 bytes<br>
530
section: .data at 0x4000ef10, size 2080 bytes<br>
531
total size: 63280 bytes (316.8 kbit/s)<br>
532
read 197 symbols<br>
533
entry point: 0x40000000<br>
534
grmon[grlib]&gt; run<br>
535
Starting<br>
536
&nbsp;&nbsp;&nbsp; Perm&nbsp; Towers&nbsp; Queens&nbsp;&nbsp;
537
Intmm&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mm&nbsp; Puzzle&nbsp;&nbsp;
538
Quick&nbsp; Bubble&nbsp;&nbsp;&nbsp; Tree&nbsp;&nbsp;&nbsp;&nbsp; FFT<br>
539
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 33&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
540
50&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 33&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
541
34&nbsp;&nbsp;&nbsp;&nbsp; 883&nbsp;&nbsp;&nbsp;&nbsp;
542
283&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 33&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
543
50&nbsp;&nbsp;&nbsp;&nbsp; 216&nbsp;&nbsp;&nbsp; 1084<br>
544
      <br>
545
Nonfloating point composite is&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 111<br>
546
      <br>
547
Floating point composite is&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 850<br>
548
      <br>
549
Program exited normally.<br>
550
grmon[grlib]&gt;<br>
551
</span></span></small>
552
      <small><span style="font-family: helvetica,arial,sans-serif;">
553
<br>
554
The LEON3MP test bench includes memory models of both boot-prom, sram
555
and sdram. To build memory images for these models, do 'make soft' .
556
Note: this will require that the bare-C compiler for LEON3 is
557
installed,
558
and /opt/sparc-elf/bin is added to the PATH.<br>
559
<br>
560
<br>
561
</span></small></td>
562
    </tr>
563
    <tr>
564
      <td valign="top"><br>
565
      </td>
566
    </tr>
567
  </tbody>
568
</table>
569
<small><span style="font-family: helvetica,arial,sans-serif;">
570
</span></small>
571
</body></html>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.