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dimamali |
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design for AVNET Spartan3 Evaluation Board
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.pci.all;
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use gaisler.net.all;
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use gaisler.jtag.all;
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use gaisler.can.all;
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library esa;
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use esa.memoryctrl.all;
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use esa.pcicomp.all;
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use work.config.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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mezz : integer := CFG_ADS_DAU_MEZZ
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);
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port (
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clk_66mhz : in std_logic;
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clk_socket : in std_logic;
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leds : out std_logic_vector(7 downto 0);
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switches : in std_logic_vector(5 downto 0);
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sram_a : out std_logic_vector(24 downto 0);
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sram_ben_l : out std_logic_vector(0 to 3);
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sram_cs_l : out std_logic_vector(1 downto 0);
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sram_oe_l : out std_logic;
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sram_we_l : out std_logic;
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sram_dq : inout std_logic_vector(31 downto 0);
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flash_cs_l : out std_logic;
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flash_rst_l : out std_logic;
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iosn : out std_logic;
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sdclk : out std_logic;
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rasn : out std_logic;
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casn : out std_logic;
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sdcke : out std_logic;
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sdcsn : out std_logic;
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tx : out std_logic;
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rx : in std_logic;
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can_txd : out std_logic;
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can_rxd : in std_logic;
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phy_txck : in std_logic;
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phy_rxck : in std_logic;
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phy_rxd : in std_logic_vector(3 downto 0);
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phy_rxdv : in std_logic;
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phy_rxer : in std_logic;
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phy_col : in std_logic;
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phy_crs : in std_logic;
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phy_txd : out std_logic_vector(3 downto 0);
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phy_txen : out std_logic;
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phy_txer : out std_logic;
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phy_mdc : out std_logic;
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phy_mdio : inout std_logic; -- ethernet PHY interface
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phy_reset_l : inout std_logic;
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video_clk : in std_logic;
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comp_sync : out std_logic;
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horiz_sync : out std_logic;
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vert_sync : out std_logic;
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blank : out std_logic;
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video_out : out std_logic_vector(23 downto 0);
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msclk : inout std_logic;
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msdata : inout std_logic;
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kbclk : inout std_logic;
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kbdata : inout std_logic;
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disp_seg1 : out std_logic_vector(7 downto 0);
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disp_seg2 : out std_logic_vector(7 downto 0);
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pci_clk : in std_logic;
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pci_gnt : in std_logic;
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pci_idsel : in std_logic;
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pci_lock : inout std_logic;
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pci_ad : inout std_logic_vector(31 downto 0);
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pci_cbe : inout std_logic_vector(3 downto 0);
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pci_frame : inout std_logic;
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pci_irdy : inout std_logic;
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pci_trdy : inout std_logic;
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pci_devsel : inout std_logic;
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pci_stop : inout std_logic;
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pci_perr : inout std_logic;
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pci_par : inout std_logic;
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pci_req : inout std_logic;
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pci_serr : inout std_logic;
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pci_host : in std_logic;
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pci_66 : in std_logic
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);
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end;
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architecture rtl of leon3mp is
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constant blength : integer := 12;
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constant fifodepth : integer := 8;
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constant mahbmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_PCI+
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CFG_SVGA_ENABLE + CFG_GRETH+CFG_AHB_JTAG;
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signal vcc, gnd : std_logic_vector(23 downto 0);
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal sdi : sdctrl_in_type;
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signal sdo : sdram_out_type;
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signal sdo2, sdo3 : sdctrl_out_type;
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signal abus : std_logic_vector(17 downto 0);
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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signal clk, rstn, rstraw, pciclk, sdclkl : std_logic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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signal u1i, u2i, dui : uart_in_type;
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signal u1o, u2o, duo : uart_out_type;
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signal irqi : irq_in_vector(0 to CFG_NCPU-1);
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signal irqo : irq_out_vector(0 to CFG_NCPU-1);
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signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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signal kbdi : ps2_in_type;
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signal kbdo : ps2_out_type;
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signal moui : ps2_in_type;
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signal mouo : ps2_out_type;
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signal vgao : apbvga_out_type;
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signal pcii : pci_in_type;
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signal pcio : pci_out_type;
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signal ethi, ethi1, ethi2 : eth_in_type;
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signal etho, etho1, etho2 : eth_out_type;
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signal gpti : gptimer_in_type;
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signal tck, tms, tdi, tdo : std_logic;
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signal pllref, errorn, pci_rst : std_logic;
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signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
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signal dac_clk, clk25, clk_66mhzl, pci_lclk : std_logic;
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signal can_ltx, can_lrx : std_logic;
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attribute keep : boolean;
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attribute syn_keep : boolean;
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attribute syn_preserve : boolean;
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attribute syn_keep of clk : signal is true;
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attribute syn_preserve of clk : signal is true;
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attribute keep of clk : signal is true;
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signal switchesl : std_logic_vector(5 downto 0);
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constant padlevel : integer := 0;
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constant IOAEN : integer := CFG_CAN;
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constant BOARD_FREQ : integer := 66667; -- input frequency in KHz
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constant CPU_FREQ : integer := (BOARD_FREQ * CFG_CLKMUL) / CFG_CLKDIV;
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begin
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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---------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0'); pllref <= '0';
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= pllref;
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clkgen0 : clkgen -- clock generator
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generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
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CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, 66000)
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port map (clk_66mhzl, pci_lclk, clk, open, open, sdclkl, pciclk, cgi, cgo);
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sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 8)
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port map (sdclk, sdclkl);
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clk_pad : clkpad generic map (tech => padtech, level => padlevel)
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port map (clk_66mhz, clk_66mhzl);
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clk2_pad : clkpad generic map (tech => padtech, level => padlevel)
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port map (clk_socket, open);
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pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
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port map (pci_clk, pci_lclk);
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rst0 : rstgen generic map (acthigh => 1)
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port map (switchesl(4), clk, cgo.clklock, rstn, rstraw);
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flash_rst_l_pad : outpad generic map (level => padlevel, tech => padtech)
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port map (flash_rst_l, rstraw);
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----------------------------------------------------------------------
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--- AHB CONTROLLER --------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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nahbm => mahbmax, nahbs => 8, ioen => IOAEN)
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port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- LEON3 processor and DSU -----------------------------------------
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----------------------------------------------------------------------
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l3 : if CFG_LEON3 = 1 generate
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cpu : for i in 0 to CFG_NCPU-1 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
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port map (clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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dsugen : if CFG_DSU = 1 generate
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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port map (rstn, clk, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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end generate;
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dsui.break <= switchesl(5);
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dsui.enable <= '1';
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dsuact_pad : outpad generic map (tech => padtech, level => padlevel)
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port map (leds(1), dsuo.active);
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end generate;
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end generate;
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nodsu : if CFG_DSU = 0 generate
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ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
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end generate;
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dcomgen : if CFG_AHB_UART = 1 generate
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dcom0: ahbuart -- Debug UART
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generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
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port map (rstn, clk, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
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end generate;
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nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
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ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
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ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
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port map(rstn, clk, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
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open, open, open, open, open, open, open, gnd(0));
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end generate;
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dcompads : if CFG_AHB_UART = 1 generate
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dsurx_pad : inpad generic map (tech => padtech, level => padlevel)
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port map (rx, dui.rxd);
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dsutx_pad : outpad generic map (tech => padtech, level => padlevel)
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port map (tx, duo.txd);
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u1i.rxd <= '1';
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end generate;
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----------------------------------------------------------------------
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--- Memory controllers ----------------------------------------------
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----------------------------------------------------------------------
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mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
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sr1 : entity work.mctrl_avnet generic map (hindex => 0, pindex => 0, paddr => 0,
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srbanks => 4, sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
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pageburst => CFG_MCTRL_PAGE, avnetmezz => mezz)
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port map (rstn, clk, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
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sdpads : if CFG_MCTRL_SDEN = 1 generate -- no SDRAM controller
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-- sdwen_pad : outpad generic map (tech => padtech)
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-- port map (sdwen, sdo.sdwen);
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sdras_pad : outpad generic map (tech => padtech)
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port map (rasn, sdo.rasn);
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|
|
sdcas_pad : outpad generic map (tech => padtech)
|
308 |
|
|
port map (casn, sdo.casn);
|
309 |
|
|
-- sddqm_pad : outpadv generic map (width =>4, tech => padtech)
|
310 |
|
|
-- port map (sddqm, sdo.dqm);
|
311 |
|
|
end generate;
|
312 |
|
|
sdcke_pad : outpad generic map (tech => padtech)
|
313 |
|
|
port map (sdcke, sdo.sdcke(0));
|
314 |
|
|
sdcsn_pad : outpad generic map (tech => padtech)
|
315 |
|
|
port map (sdcsn, sdo.sdcsn(0));
|
316 |
|
|
end generate;
|
317 |
|
|
|
318 |
|
|
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
|
319 |
|
|
sdcke_pad : outpad generic map (tech => padtech)
|
320 |
|
|
port map (sdcke, vcc(0));
|
321 |
|
|
sdcsn_pad : outpad generic map (tech => padtech)
|
322 |
|
|
port map (sdcsn, vcc(0));
|
323 |
|
|
end generate;
|
324 |
|
|
|
325 |
|
|
memi.brdyn <= '1'; memi.bexcn <= '1';
|
326 |
|
|
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
|
327 |
|
|
|
328 |
|
|
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- None PROM/SRAM controller
|
329 |
|
|
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
|
330 |
|
|
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
|
331 |
|
|
port map (sram_cs_l, vcc(1 downto 0));
|
332 |
|
|
end generate;
|
333 |
|
|
|
334 |
|
|
mgpads : if CFG_MCTRL_LEON2 /= 0 generate -- prom/sram pads
|
335 |
|
|
addr_pad : outpadv generic map (level => padlevel, width => 25, tech => padtech)
|
336 |
|
|
port map (sram_a, memo.address(24 downto 0));
|
337 |
|
|
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
|
338 |
|
|
port map (sram_cs_l, memo.ramsn(1 downto 0));
|
339 |
|
|
flash_pad : outpad generic map (level => padlevel, tech => padtech)
|
340 |
|
|
port map (flash_cs_l, memo.romsn(0));
|
341 |
|
|
oen_pad : outpad generic map (level => padlevel, tech => padtech)
|
342 |
|
|
port map (sram_oe_l, memo.oen);
|
343 |
|
|
iosn_pad : outpad generic map (level => padlevel, tech => padtech)
|
344 |
|
|
port map (iosn, memo.iosn);
|
345 |
|
|
wri_pad : outpad generic map (level => padlevel, tech => padtech)
|
346 |
|
|
port map (sram_we_l, memo.writen);
|
347 |
|
|
bdr : for i in 0 to 3 generate
|
348 |
|
|
data_pad : iopadv generic map (level => padlevel, tech => padtech, width => 8)
|
349 |
|
|
port map (sram_dq(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
|
350 |
|
|
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
|
351 |
|
|
end generate;
|
352 |
|
|
ben_pad : outpadv generic map (level => padlevel, width => 4, tech => padtech)
|
353 |
|
|
port map (sram_ben_l, memo.mben);
|
354 |
|
|
end generate;
|
355 |
|
|
|
356 |
|
|
----------------------------------------------------------------------
|
357 |
|
|
--- APB Bridge and various periherals -------------------------------
|
358 |
|
|
----------------------------------------------------------------------
|
359 |
|
|
|
360 |
|
|
apb0 : apbctrl -- AHB/APB bridge
|
361 |
|
|
generic map (hindex => 1, haddr => CFG_APBADDR)
|
362 |
|
|
port map (rstn, clk, ahbsi, ahbso(1), apbi, apbo );
|
363 |
|
|
|
364 |
|
|
ua1 : if CFG_UART1_ENABLE /= 0 generate
|
365 |
|
|
uart1 : apbuart -- UART 1
|
366 |
|
|
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
367 |
|
|
fifosize => CFG_UART1_FIFO)
|
368 |
|
|
port map (rstn, clk, apbi, apbo(1), u1i, u1o);
|
369 |
|
|
u1i.ctsn <= '0'; u1i.extclk <= '0';
|
370 |
|
|
end generate;
|
371 |
|
|
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
|
372 |
|
|
ua1pads : if CFG_AHB_UART = 0 generate
|
373 |
|
|
rx_pad : inpad generic map (tech => padtech, level => padlevel)
|
374 |
|
|
port map (rx, u1i.rxd);
|
375 |
|
|
tx_pad : outpad generic map (tech => padtech, level => padlevel)
|
376 |
|
|
port map (tx, u1o.txd);
|
377 |
|
|
end generate;
|
378 |
|
|
|
379 |
|
|
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
|
380 |
|
|
irqctrl0 : irqmp -- interrupt controller
|
381 |
|
|
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
|
382 |
|
|
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
|
383 |
|
|
end generate;
|
384 |
|
|
irq3 : if CFG_IRQ3_ENABLE = 0 generate
|
385 |
|
|
x : for i in 0 to CFG_NCPU-1 generate
|
386 |
|
|
irqi(i).irl <= "0000";
|
387 |
|
|
end generate;
|
388 |
|
|
apbo(2) <= apb_none;
|
389 |
|
|
end generate;
|
390 |
|
|
|
391 |
|
|
gpt : if CFG_GPT_ENABLE /= 0 generate
|
392 |
|
|
timer0 : gptimer -- timer unit
|
393 |
|
|
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
394 |
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
395 |
|
|
nbits => CFG_GPT_TW)
|
396 |
|
|
port map (rstn, clk, apbi, apbo(3), gpti, open);
|
397 |
|
|
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
|
398 |
|
|
end generate;
|
399 |
|
|
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
400 |
|
|
|
401 |
|
|
kbd : if CFG_KBD_ENABLE /= 0 generate
|
402 |
|
|
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
|
403 |
|
|
port map(rstn, clk, apbi, apbo(4), moui, mouo);
|
404 |
|
|
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
|
405 |
|
|
port map(rstn, clk, apbi, apbo(5), kbdi, kbdo);
|
406 |
|
|
end generate;
|
407 |
|
|
nokbd : if CFG_KBD_ENABLE = 0 generate
|
408 |
|
|
apbo(4) <= apb_none; mouo <= ps2o_none;
|
409 |
|
|
apbo(5) <= apb_none; kbdo <= ps2o_none;
|
410 |
|
|
end generate;
|
411 |
|
|
kbdclk_pad : iopad generic map (tech => padtech)
|
412 |
|
|
port map (kbclk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
|
413 |
|
|
kbdata_pad : iopad generic map (tech => padtech)
|
414 |
|
|
port map (kbdata, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
|
415 |
|
|
mouclk_pad : iopad generic map (tech => padtech)
|
416 |
|
|
port map (msclk,mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
|
417 |
|
|
mouata_pad : iopad generic map (tech => padtech)
|
418 |
|
|
port map (msdata, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
|
419 |
|
|
|
420 |
|
|
vga : if CFG_VGA_ENABLE /= 0 generate
|
421 |
|
|
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
|
422 |
|
|
port map(rstn, clk, clk25, apbi, apbo(6), vgao);
|
423 |
|
|
vgaclk0 : entity techmap.clkmul_virtex2 generic map (3, 8) -- 25 MHz video clock
|
424 |
|
|
port map (rstn, clk, dac_clk, open);
|
425 |
|
|
end generate;
|
426 |
|
|
|
427 |
|
|
svga : if CFG_SVGA_ENABLE /= 0 generate
|
428 |
|
|
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
|
429 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
|
430 |
|
|
clk0 => 39722, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 5)
|
431 |
|
|
port map(rstn, clk, clk25, apbi, apbo(6), vgao, ahbmi,
|
432 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
|
433 |
|
|
clk25 <= not dac_clk;
|
434 |
|
|
end generate;
|
435 |
|
|
|
436 |
|
|
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
|
437 |
|
|
apbo(6) <= apb_none; vgao <= vgao_none;
|
438 |
|
|
end generate;
|
439 |
|
|
|
440 |
|
|
video_clk_pad : inpad generic map (tech => padtech)
|
441 |
|
|
port map (video_clk, dac_clk);
|
442 |
|
|
blank_pad : outpad generic map (tech => padtech)
|
443 |
|
|
port map (blank, vgao.blank);
|
444 |
|
|
comp_sync_pad : outpad generic map (tech => padtech)
|
445 |
|
|
port map (comp_sync, vgao.comp_sync);
|
446 |
|
|
vert_sync_pad : outpad generic map (tech => padtech)
|
447 |
|
|
port map (vert_sync, vgao.vsync);
|
448 |
|
|
horiz_sync_pad : outpad generic map (tech => padtech)
|
449 |
|
|
port map (horiz_sync, vgao.hsync);
|
450 |
|
|
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
|
451 |
|
|
port map (video_out(23 downto 16), vgao.video_out_r);
|
452 |
|
|
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
|
453 |
|
|
port map (video_out(15 downto 8), vgao.video_out_g);
|
454 |
|
|
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
|
455 |
|
|
port map (video_out(7 downto 0), vgao.video_out_b);
|
456 |
|
|
|
457 |
|
|
-----------------------------------------------------------------------
|
458 |
|
|
--- PCI ------------------------------------------------------------
|
459 |
|
|
-----------------------------------------------------------------------
|
460 |
|
|
|
461 |
|
|
pp : if CFG_PCI /= 0 generate
|
462 |
|
|
|
463 |
|
|
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
|
464 |
|
|
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
|
465 |
|
|
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
|
466 |
|
|
port map (rstn, clk, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE));
|
467 |
|
|
end generate;
|
468 |
|
|
|
469 |
|
|
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
|
470 |
|
|
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
|
471 |
|
|
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
|
472 |
|
|
hslvndx => 4, pindex => 9, paddr => 4, haddr => 16#E00#,
|
473 |
|
|
ioaddr => 16#400#, nsync => 2)
|
474 |
|
|
port map (rstn, clk, pciclk, pcii, pcio, apbi, apbo(9),
|
475 |
|
|
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbsi, ahbso(4));
|
476 |
|
|
end generate;
|
477 |
|
|
|
478 |
|
|
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
|
479 |
|
|
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1+CFG_SVGA_ENABLE,
|
480 |
|
|
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
|
481 |
|
|
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
|
482 |
|
|
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
|
483 |
|
|
nsync => 1)
|
484 |
|
|
port map (rstn, clk, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1+CFG_SVGA_ENABLE),
|
485 |
|
|
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbsi, ahbso(4));
|
486 |
|
|
end generate;
|
487 |
|
|
|
488 |
|
|
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
|
489 |
|
|
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
|
490 |
|
|
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
|
491 |
|
|
port map ( rstn, clk, pciclk, pcii, apbi, apbo(8));
|
492 |
|
|
end generate;
|
493 |
|
|
|
494 |
|
|
end generate;
|
495 |
|
|
|
496 |
|
|
pcipads0 : pcipads
|
497 |
|
|
generic map (padtech => padtech, noreset => 1, host => 0)-- PCI pads
|
498 |
|
|
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
|
499 |
|
|
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
|
500 |
|
|
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
|
501 |
|
|
|
502 |
|
|
-----------------------------------------------------------------------
|
503 |
|
|
--- ETHERNET ---------------------------------------------------------
|
504 |
|
|
-----------------------------------------------------------------------
|
505 |
|
|
|
506 |
|
|
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
|
507 |
|
|
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
|
508 |
|
|
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
|
509 |
|
|
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
|
510 |
|
|
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
|
511 |
|
|
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
|
512 |
|
|
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
|
513 |
|
|
port map( rst => rstn, clk => clk, ahbmi => ahbmi,
|
514 |
|
|
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
|
515 |
|
|
apbo => apbo(11), ethi => ethi, etho => etho);
|
516 |
|
|
end generate;
|
517 |
|
|
|
518 |
|
|
|
519 |
|
|
ethpads : if (CFG_GRETH = 0) generate -- no eth
|
520 |
|
|
etho <= ('0', "00000000", '0', '0', '0', '0', '1');
|
521 |
|
|
end generate;
|
522 |
|
|
|
523 |
|
|
emdio_pad : iopad generic map (tech => padtech, level => padlevel)
|
524 |
|
|
port map (phy_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
|
525 |
|
|
etxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
|
526 |
|
|
port map (phy_txck, ethi.tx_clk);
|
527 |
|
|
erxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
|
528 |
|
|
port map (phy_rxck, ethi.rx_clk);
|
529 |
|
|
erxd_pad : inpadv generic map (tech => padtech, level => padlevel, width => 4)
|
530 |
|
|
port map (phy_rxd, ethi.rxd(3 downto 0));
|
531 |
|
|
erxdv_pad : inpad generic map (tech => padtech, level => padlevel)
|
532 |
|
|
port map (phy_rxdv, ethi.rx_dv);
|
533 |
|
|
erxer_pad : inpad generic map (tech => padtech, level => padlevel)
|
534 |
|
|
port map (phy_rxer, ethi.rx_er);
|
535 |
|
|
erxco_pad : inpad generic map (tech => padtech, level => padlevel)
|
536 |
|
|
port map (phy_col, ethi.rx_col);
|
537 |
|
|
erxcr_pad : inpad generic map (tech => padtech, level => padlevel)
|
538 |
|
|
port map (phy_crs, ethi.rx_crs);
|
539 |
|
|
|
540 |
|
|
etxd_pad : outpadv generic map (tech => padtech, level => padlevel, width => 4)
|
541 |
|
|
port map (phy_txd, etho.txd(3 downto 0));
|
542 |
|
|
etxen_pad : outpad generic map (tech => padtech, level => padlevel)
|
543 |
|
|
port map ( phy_txen, etho.tx_en);
|
544 |
|
|
etxer_pad : outpad generic map (tech => padtech, level => padlevel)
|
545 |
|
|
port map (phy_txer, etho.tx_er);
|
546 |
|
|
emdc_pad : outpad generic map (tech => padtech, level => padlevel)
|
547 |
|
|
port map (phy_mdc, etho.mdc);
|
548 |
|
|
|
549 |
|
|
|
550 |
|
|
phy_reset_pad : iodpad generic map (tech => padtech, level => padlevel)
|
551 |
|
|
port map (phy_reset_l, rstn, pci_rst);
|
552 |
|
|
|
553 |
|
|
can0 : if CFG_CAN = 1 generate
|
554 |
|
|
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
|
555 |
|
|
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
|
556 |
|
|
port map (rstn, clk, ahbsi, ahbso(6), can_lrx, can_ltx );
|
557 |
|
|
|
558 |
|
|
can_tx_pad : outpad generic map (tech => padtech)
|
559 |
|
|
port map (can_txd, can_ltx);
|
560 |
|
|
can_rx_pad : inpad generic map (tech => padtech)
|
561 |
|
|
port map (can_rxd, can_lrx);
|
562 |
|
|
end generate;
|
563 |
|
|
|
564 |
|
|
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
|
565 |
|
|
|
566 |
|
|
-----------------------------------------------------------------------
|
567 |
|
|
--- AHB RAM ----------------------------------------------------------
|
568 |
|
|
-----------------------------------------------------------------------
|
569 |
|
|
|
570 |
|
|
ocram : if CFG_AHBRAMEN = 1 generate
|
571 |
|
|
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
|
572 |
|
|
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
|
573 |
|
|
port map (rstn, clk, ahbsi, ahbso(7));
|
574 |
|
|
end generate;
|
575 |
|
|
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
|
576 |
|
|
|
577 |
|
|
-----------------------------------------------------------------------
|
578 |
|
|
--- Misc ----------------------------------------------------------
|
579 |
|
|
-----------------------------------------------------------------------
|
580 |
|
|
|
581 |
|
|
errorn <= not dbgo(0).error;
|
582 |
|
|
led0_pad : outpad generic map (level => padlevel, tech => padtech)
|
583 |
|
|
port map (leds(0), errorn);
|
584 |
|
|
led2_7_pad : outpadv generic map (level => padlevel, width => 6, tech => padtech)
|
585 |
|
|
port map (leds(7 downto 2), gnd(5 downto 0));
|
586 |
|
|
|
587 |
|
|
disp_seg1_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
|
588 |
|
|
port map (disp_seg1, gnd(7 downto 0));
|
589 |
|
|
disp_seg2_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
|
590 |
|
|
port map (disp_seg2, gnd(7 downto 0));
|
591 |
|
|
switche_pad : inpadv generic map (tech => padtech, level => padlevel, width => 6)
|
592 |
|
|
port map (switches, switchesl);
|
593 |
|
|
|
594 |
|
|
-----------------------------------------------------------------------
|
595 |
|
|
--- Drive unused bus elements ---------------------------------------
|
596 |
|
|
-----------------------------------------------------------------------
|
597 |
|
|
|
598 |
|
|
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_PCI+ CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE) to NAHBMST-1 generate
|
599 |
|
|
ahbmo(i) <= ahbm_none;
|
600 |
|
|
end generate;
|
601 |
|
|
nam2 : if CFG_PCI > 1 generate
|
602 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG-1+CFG_SVGA_ENABLE) <= ahbm_none;
|
603 |
|
|
end generate;
|
604 |
|
|
nap0 : for i in 12 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
|
605 |
|
|
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
|
606 |
|
|
|
607 |
|
|
-----------------------------------------------------------------------
|
608 |
|
|
--- Boot message ----------------------------------------------------
|
609 |
|
|
-----------------------------------------------------------------------
|
610 |
|
|
|
611 |
|
|
-- pragma translate_off
|
612 |
|
|
x : report_version
|
613 |
|
|
generic map (
|
614 |
|
|
msg1 => "LEON3 Avnet Spartan3-1500 Demonstration design",
|
615 |
|
|
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
|
616 |
|
|
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
|
617 |
|
|
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
|
618 |
|
|
mdel => 1
|
619 |
|
|
);
|
620 |
|
|
-- pragma translate_on
|
621 |
|
|
end;
|