URL
https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
2 |
dimamali |
# Synplicity, Inc. constraint file
|
2 |
|
|
# /home/jiri/ibm/vhdl/grlib/designs/leon3-avnet-eval-xc4vlx25/default.sdc
|
3 |
|
|
# Written on Sun Oct 1 16:16:08 2006
|
4 |
|
|
# by Synplify Pro, Synplify Pro 8.6.1 Scope Editor
|
5 |
|
|
|
6 |
|
|
#
|
7 |
|
|
# Collections
|
8 |
|
|
#
|
9 |
|
|
|
10 |
|
|
#
|
11 |
|
|
# Clocks
|
12 |
|
|
#
|
13 |
|
|
define_clock -name {clk_100mhz} -freq 120.000 -clockgroup ddr_clkgroup
|
14 |
|
|
define_clock -name {clk_50mhz} -freq 60.000 -clockgroup ahb_clkgroup
|
15 |
|
|
define_clock -name {etx_clk} -freq 25.000 -clockgroup phy_rx_clkgroup -route 10.000
|
16 |
|
|
define_clock -name {erx_clk} -freq 25.000 -clockgroup phy_tx_clkgroup -route 10.000
|
17 |
|
|
|
18 |
|
|
#define_clock -name {leon3mp|ddrsp0.ddrc.ddr_phy0.clk} -freq 100.000 -route 1.0 -clockgroup ddr_clkgroup
|
19 |
|
|
#define_clock -name {leon3mp|clkgen0.clkin} -freq 50.000 -route 1.0 -clockgroup ahb_clkgroup
|
20 |
|
|
define_clock -name {ddr_clk_fb} -freq 125.000 -clockgroup ddr_fb_clkgroup -route 1.000
|
21 |
|
|
#
|
22 |
|
|
# Clock to Clock
|
23 |
|
|
#
|
24 |
|
|
#define_clock_delay -rise {clk_100mhz} -fall {clk_100mhz} -false
|
25 |
|
|
|
26 |
|
|
#define_clock_delay -rise leon3mp|clkgen0.xc2v.v.clk0B_derived_clock -rise ddrspa_work_leon3mp_rtl_88layer0|ddr_phy0.ddr_phy0.xc4v.ddr_phy0.clk_270ro_derived_clock -false
|
27 |
|
|
#define_clock_delay -rise ddrspa_work_leon3mp_rtl_88layer0|ddr_phy0.ddr_phy0.xc4v.ddr_phy0.clk_270ro_derived_clock -rise leon3mp|clkgen0.xc2v.v.clk0B_derived_clock -false
|
28 |
|
|
#define_clock_delay -rise ddrspa_work_leon3mp_rtl_88layer0|ddr_phy0.ddr_phy0.xc4v.ddr_phy0.clk_0ro_derived_clock -rise leon3mp|clkgen0.xc2v.v.clk0B_derived_clock -false
|
29 |
|
|
|
30 |
|
|
#define_clock_delay -rise leon3mp|clkgen0.xc2v.v.clk0B_derived_clock -rise ddrspa|ddr_phy0.xc4v.ddr_phy0.clk_270ro_derived_clock -false
|
31 |
|
|
#define_clock_delay -rise ddrspa|ddr_phy0.xc4v.ddr_phy0.clk_270ro_derived_clock -rise leon3mp|clkgen0.xc2v.v.clk0B_derived_clock -false
|
32 |
|
|
#define_clock_delay -rise ddr_phy0.xc4v.ddr_phy0.clk_0ro_derived_clock -rise leon3mp|clkgen0.xc2v.v.clk0B_derived_clock -false
|
33 |
|
|
|
34 |
|
|
#
|
35 |
|
|
# Inputs/Outputs
|
36 |
|
|
#
|
37 |
|
|
define_output_delay -disable -default 10.00 -improve 0.00 -route 0.00 -ref {clk:r}
|
38 |
|
|
define_input_delay -disable -default 10.00 -improve 0.00 -route 0.00 -ref {clk:r}
|
39 |
|
|
|
40 |
|
|
#
|
41 |
|
|
# Registers
|
42 |
|
|
#
|
43 |
|
|
|
44 |
|
|
#
|
45 |
|
|
# Multicycle Path
|
46 |
|
|
#
|
47 |
|
|
|
48 |
|
|
#
|
49 |
|
|
# False Path
|
50 |
|
|
#
|
51 |
|
|
|
52 |
|
|
#
|
53 |
|
|
# Path Delay
|
54 |
|
|
#
|
55 |
|
|
|
56 |
|
|
#
|
57 |
|
|
# Attributes
|
58 |
|
|
#
|
59 |
|
|
define_global_attribute syn_useioff {1}
|
60 |
|
|
|
61 |
|
|
#
|
62 |
|
|
# I/O standards
|
63 |
|
|
#
|
64 |
|
|
|
65 |
|
|
#
|
66 |
|
|
# Compile Points
|
67 |
|
|
#
|
68 |
|
|
|
69 |
|
|
#
|
70 |
|
|
# Other Constraints
|
71 |
|
|
#
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.