OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-avnet-xc2v1500/] [wave.do] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
onerror {resume}
2
quietly WaveActivateNextPane {} 0
3
add wave -noupdate -format Logic /testbench/sys_clk
4
add wave -noupdate -format Logic /testbench/sys_rst_in
5
add wave -noupdate -format Logic /testbench/errorn
6
add wave -noupdate -format Literal -radix hexadecimal /testbench/address
7
add wave -noupdate -format Literal -radix hexadecimal /testbench/data
8
add wave -noupdate -format Literal /testbench/romsn
9
add wave -noupdate -format Logic /testbench/iosn
10
add wave -noupdate -format Logic /testbench/writen
11
add wave -noupdate -format Logic /testbench/read
12
add wave -noupdate -format Logic /testbench/oen
13
add wave -noupdate -format Logic /testbench/flash_rstn
14
add wave -noupdate -format Logic /testbench/clk125
15
add wave -noupdate -format Literal /testbench/ddr_clk
16
add wave -noupdate -format Literal /testbench/ddr_clkb
17
add wave -noupdate -format Logic /testbench/ddr_clk_fb
18
add wave -noupdate -format Literal /testbench/ddr_cke
19
add wave -noupdate -format Literal /testbench/ddr_csb
20
add wave -noupdate -format Logic /testbench/ddr_web
21
add wave -noupdate -format Logic /testbench/ddr_rasb
22
add wave -noupdate -format Logic /testbench/ddr_casb
23
add wave -noupdate -format Literal /testbench/ddr_dm
24
add wave -noupdate -format Literal /testbench/ddr_dqs
25
add wave -noupdate -format Literal -radix hexadecimal /testbench/ddr_ad
26
add wave -noupdate -format Literal -radix hexadecimal /testbench/ddr_ba
27
add wave -noupdate -format Literal -radix hexadecimal /testbench/ddr_dq
28
add wave -noupdate -format Logic /testbench/txd1
29
add wave -noupdate -format Logic /testbench/rxd1
30
add wave -noupdate -format Literal /testbench/gpio
31
add wave -noupdate -divider {CPU 1}
32
add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/apbi
33
add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/apbo
34
add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbsi
35
add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbso
36
add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbmi
37
add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbmo
38
add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ddrsp0/ddr0/ddr64/ddrc/r
39
add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ddrsp0/ddr0/ddr64/ddrc/ra
40
TreeUpdate [SetDefaultTree]
41
WaveRestoreCursors {{Cursor 1} {15761477 ps} 0}
42
configure wave -namecolwidth 171
43
configure wave -valuecolwidth 75
44
configure wave -justifyvalue left
45
configure wave -signalnamewidth 0
46
configure wave -snapdistance 10
47
configure wave -datasetprefix 0
48
configure wave -rowmargin 4
49
configure wave -childrowmargin 2
50
configure wave -gridoffset 0
51
configure wave -gridperiod 1
52
configure wave -griddelta 40
53
configure wave -timeline 0
54
update
55
WaveRestoreZoom {15700807 ps} {15812937 ps}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.