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------------------------------------------------------------------------------

--  LEON3 Demonstration design

--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research

--

--  This program is free software; you can redistribute it and/or modify

--  it under the terms of the GNU General Public License as published by

--  the Free Software Foundation; either version 2 of the License, or

--  (at your option) any later version.

--

--  This program is distributed in the hope that it will be useful,

--  but WITHOUT ANY WARRANTY; without even the implied warranty of

--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--  GNU General Public License for more details.

--

--  You should have received a copy of the GNU General Public License

--  along with this program; if not, write to the Free Software

--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

------------------------------------------------------------------------------

--  maintained by Florian Wex, Gleichmann Electronics 2007

--  updated to grlib-eval-1.0.16 in , September 2007

------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

library grlib;

use grlib.amba.all;

use grlib.stdlib.all;

use grlib.devices.all;

library techmap;

use techmap.gencomp.all;

library gaisler;

use gaisler.memctrl.all;

use gaisler.leon3.all;

use gaisler.uart.all;

use gaisler.misc.all;

use gaisler.can.all;

use gaisler.net.all;

use gaisler.grusb.all;

use gaisler.jtag.all;

library esa;

use esa.memoryctrl.all;

library gleichmann;

use gleichmann.hpi.all;

use gleichmann.miscellaneous.all;

use gleichmann.multiio.all;

use gleichmann.dac.all;

use gleichmann.sspi.all;

use gleichmann.ge_clkgen.all;

use gleichmann.ac97.all;

library work;

use work.config.all;

entity leon3hpe is

  generic (

    fabtech : integer := CFG_FABTECH;

    memtech : integer := CFG_MEMTECH;

    padtech : integer := CFG_PADTECH;

    clktech : integer := CFG_CLKTECH;

    disas   : integer := CFG_DISAS;     -- Enable disassembly to console

    dbguart : integer := CFG_DUART;     -- Print UART on console

    pclow   : integer := CFG_PCLOW

    );

  port (

    resetn  : in  std_logic;

    resoutn : out std_logic;

    clk : in std_logic;

    errorn  : out   std_logic;

    address : out   std_logic_vector(27 downto 0);

    data    : inout std_logic_vector(31 downto 0);

    ramsn   : out   std_logic_vector (4 downto 0);

    ramoen  : out   std_logic_vector (4 downto 0);

    rwen    : inout std_logic_vector (3 downto 0);

    -- ram byte enable for hpe board

    -- necessary because individual bytes have to

    -- be selected for reading as well

    rben    : out   std_logic_vector(3 downto 0);

    romsn   : out   std_logic_vector (1 downto 0);

    iosn    : out   std_logic;

    oen     : out   std_logic;

    read    : out   std_logic;

    writen  : out   std_logic;

    -- SDRAM interface

    sdclk  : out   std_logic_vector(1 downto 0);

    sdcke  : out   std_logic_vector(1 downto 0);   -- sdram clock enable

    sdaddr : out   std_logic_vector(12 downto 0);

    sddq   : inout std_logic_vector(63 downto 0);

    sddqm  : out   std_logic_vector(7 downto 0);   -- sdram dqm

    sdwen  : out   std_logic;                     -- sdram write enable

    sdcasn : out   std_logic;                     -- sdram cas

    sdrasn : out   std_logic;                     -- sdram ras

    sdcsn  : out   std_logic_vector (1 downto 0);  -- sdram chip select

    sdba   : out   std_logic_vector(1 downto 0);   -- sdram bank address

    -- debug support unit

    dsutx   : out std_logic;           -- DSU tx data

    dsurx   : in  std_logic;           -- DSU rx data

    dsubre  : in  std_logic;

    dsuactn : out std_logic;

    -- console UART

    rxd1 : in  std_logic;

    txd1 : out std_logic;

    -- ethernet signals

    emdio   : inout std_logic;          -- ethernet PHY interface

    etx_clk : in    std_logic;

    erx_clk : in    std_logic;

    erxd    : in    std_logic_vector(3 downto 0);

    erx_dv  : in    std_logic;

    erx_er  : in    std_logic;

    erx_col : in    std_logic;

    erx_crs : in    std_logic;

    etxd    : out   std_logic_vector(3 downto 0);

    etx_en  : out   std_logic;

    etx_er  : out   std_logic;

    emdc    : out   std_logic;

    ereset  : out   std_logic;

    --  CAN receive and transmit signals

    can_txd : out std_logic;

    can_rxd : in  std_logic;

    can_stb : out std_logic;

    -------------------------------------------------------------------------------------

    -- IO SECTION

    -------------------------------------------------------------------------------------

    dsw : in std_logic_vector(7 downto 0);

    led_enable : out std_logic;

    sevensegment : out std_logic_vector(9 downto 0);  -- 7-segments and 2 strobes

    lcd_enable : out std_logic;

    lcd_regsel : out std_logic;

    lcd_rw     : out std_logic;

    -- keyboard

    tst_col : out std_logic_vector(2 downto 0);  -- column outputs

    tst_row : in  std_logic_vector(3 downto 0);  -- row inputs

    -- only one PS/2 interface possible due to routing problems

    -- see instantiation of the interface below

    ps2_clk  : inout std_logic_vector(1 downto 0);

    ps2_data : inout std_logic_vector(1 downto 0);

    -- expansion connector signals

    exp_datao : out std_logic_vector(19 downto 0);

    exp_datai : in  std_logic_vector(19 downto 0);

    ---------------------------------------------------------------------------

    -- VGA interface

    ---------------------------------------------------------------------------

    vga_clk    : out std_logic;

    vga_syncn  : out std_logic;

    vga_blankn : out std_logic;

    vga_vsync  : out std_logic;

    vga_hsync  : out std_logic;

    vga_rd     : out std_logic_vector(7 downto 0);

    vga_gr     : out std_logic_vector(7 downto 0);

    vga_bl     : out std_logic_vector(7 downto 0);

    ---------------------------------------------------------------------------

    -- AC97 AUDIO CODEC

    ---------------------------------------------------------------------------

    ac97_bit_clk   : in  std_logic;

    ac97_sync      : out std_logic;

    ac97_sdata_out : out std_logic;

    ac97_sdata_in  : in  std_logic;

    -- when no crystal is assembled, drive this signal with a 24.5 (or 25) MHz clock

    ac97_ext_clk   : out std_logic;

    ac97_resetn    : out std_logic;

    -------------------------------------------------------------------------------------

    -- USB DEBUG INTERFACE

    -------------------------------------------------------------------------------------

    usb_clkout    : in    std_logic;

    usb_d         : inout std_logic_vector(15 downto 0);

    usb_linestate : in    std_logic_vector(1 downto 0);

    usb_opmode    : out   std_logic_vector(1 downto 0);

    usb_reset     : out   std_logic;

    usb_rxactive  : in    std_logic;

    usb_rxerror   : in    std_logic;

    usb_rxvalid   : in    std_logic;

    usb_suspend   : out   std_logic;

    usb_termsel   : out   std_logic;

    usb_txready   : in    std_logic;

    usb_txvalid   : out   std_logic;

    usb_validh    : inout std_logic;

    usb_xcvrsel   : out   std_logic;

    usb_vbus      : in    std_logic;

    usb_dbus16    : out   std_logic;

    usb_unidir    : out   std_logic;

    ---------------------------------------------------------------------------

    -- ADC/DAC INTERFACE

    ---------------------------------------------------------------------------

    adc_dout : in  std_logic;

    adc_ain  : out std_logic;

    dac_out  : out std_logic;

    -------------------------------------------------------------------------------------

    -- SDCARD interface (SPI mode)

    -------------------------------------------------------------------------------------

    sdcard_cs   : out std_logic;

    sdcard_di   : out std_logic;

    sdcard_sclk : out std_logic;

    sdcard_do   : in  std_logic;

    -------------------------------------------------------------------------------

    -- HPI PORT

    -------------------------------------------------------------------------------

    hpiaddr : out   std_logic_vector(1 downto 0);

    hpidata : inout std_logic_vector(15 downto 0);

    hpicsn  : out   std_logic;

    hpiwrn  : out   std_logic;

    hpirdn  : out   std_logic;

    hpiint  : in    std_logic

    );

end;

architecture rtl of leon3hpe is

  constant blength   : integer := 12;

  constant fifodepth : integer := 8;

  signal reset    : std_logic;

  signal vcc, gnd : std_logic_vector(4 downto 0);

  signal memi     : memory_in_type;

  signal memo     : memory_out_type;

  signal wpo      : wprot_out_type;

  signal sdi  : sdctrl_in_type;

  signal sdo  : sdram_out_type;

  signal sdo2 : sdctrl_out_type;

  signal sdo3 : sdctrl_out_type;

  signal apbi  : apb_slv_in_type;

  signal apbo  : apb_slv_out_vector := (others => apb_none);

  signal ahbsi : ahb_slv_in_type;

  signal ahbso : ahb_slv_out_vector := (others => ahbs_none);

  signal ahbmi : ahb_mst_in_type;

  signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);

  signal clkm, clk_25MHz, rstn, sdclkl : std_logic;

  -- signal clkvga             : std_logic;

  signal cgi                           : clkgen_in_type;

  signal cgo                           : clkgen_out_type;

  signal u1i, dui                      : uart_in_type;

  signal u1o, duo                      : uart_out_type;

  signal irqi : irq_in_vector(0 to CFG_NCPU-1);

  signal irqo : irq_out_vector(0 to CFG_NCPU-1);

  signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);

  signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);

  signal dsui : dsu_in_type;

  signal dsuo : dsu_out_type;

  signal ethi, ethi1, ethi2 : eth_in_type;

  signal etho, etho1, etho2 : eth_out_type;

  signal gpti : gptimer_in_type;

  signal emddis  : std_logic;

  signal epwrdwn : std_logic;

  signal esleep  : std_logic;

  signal epause  : std_logic;

-- Adaptions for HPE Compact

  signal dsuact         : std_logic;

  signal oen_ctrl       : std_logic;

  signal sdram_selected : std_logic;

  signal sd_clk         : std_logic;

  signal s_ramsn        : std_logic_vector (4 downto 0);

  signal s_sddqm        : std_logic_vector (7 downto 0);

  signal shortcut : std_logic;

  signal rx       : std_logic;

  signal tx       : std_logic;

  constant BOARD_FREQ : integer := 100_000;  -- input frequency in KHz

  constant CPU_FREQ   : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV * 1_000;  -- cpu frequency in KHz

  constant PS2_SCALER : integer := CPU_FREQ / 10_000;  -- PS2 Freq = 10 kHz

  constant IOAEN      : integer := 1;   --CFG_ETH + CFG_CAN;

  signal mioi : MultiIO_in_type;

  signal mioo : MultiIO_out_type;

  signal kbdi0, kbdi1 : ps2_in_type;

  signal kbdo0, kbdo1 : ps2_out_type;

  -- VGA interface

  signal vgao : apbvga_out_type;

  signal uclk : std_logic;

  signal usbi : grusb_in_type;

  signal usbo : grusb_out_type;

  -- simple SPI controller

  signal spii  : sspi_in_type;

  signal spio  : sspi_out_type;

  signal gspii : spi_in_type;

  signal gspio : spi_out_type;

  -- ADC/DAC

  signal adcdaci : adcdac_in_type;

  signal adcdaco : adcdac_out_type;

  ---------------------------------------------------------------------------------------

  -- AC97 AUDIO CODEC

  ---------------------------------------------------------------------------------------

  signal dma_ack   : std_logic_vector(8 downto 0);

  signal int       : std_logic;

  signal dma_req   : std_logic_vector(8 downto 0);

  signal suspended : std_logic;

  -- intermediate signals for outputs in order to be able

  -- to propagate to two signal sinks

  signal ac97_int_sync      : std_logic;

  signal ac97_int_sdata_out : std_logic;

  signal ac97_int_resetn    : std_logic;

  signal ac97_int_irq       : std_logic;

  ---------------------------------------------------------------------------------------

  -- HPI SIGNALS

  ---------------------------------------------------------------------------------------

  signal hpiwriten : std_logic;        -- intermediate signal

  signal hpirdata  : std_logic_vector(15 downto 0);

  signal hpiwdata  : std_logic_vector(15 downto 0);

  signal drive_bus : std_logic;

  signal dbg_equal  : std_logic;

  signal sample_clk : std_logic;

  ---------------------------------------------------------------------------------------

begin

----------------------------------------------------------------------

---  Reset and Clock generation  -------------------------------------

----------------------------------------------------------------------

  reset <= not resetn;

  vcc         <= (others => '1'); gnd <= (others => '0');

  cgi.pllctrl <= "00"; cgi.pllrst <= resetn;

  cgi.pllref  <= clk;

  vga_clk_gen : if (CFG_VGA_ENABLE /= 0) generate

    no_vga_clk_gen : if ((CFG_CLKDIV/CFG_CLKMUL) = 4) generate

      clk_25MHz <= clkm;

    end generate;

    vga_clk_gen : if ((CFG_CLKDIV/CFG_CLKMUL) /= 4) generate

      vga_clk_gen_inst : clkgen

        generic map (

          tech      => clktech,

          clk_mul   => 1,

          clk_div   => 4,

          sdramen   => 0,

          noclkfb   => 1,

          pcien     => 0,

          pcidll    => 0,

          pcisysclk => 0,

          freq      => BOARD_FREQ,

          clk2xen   => 0)

        port map (

          clkin    => clk,

          clk      => clk_25MHz,

          pciclkin => gnd(0),

          cgi      => cgi,

          cgo      => open);

    end generate;

  end generate;

  clkgen_1 : clkgen

    generic map (

      tech      => clktech,

      clk_mul   => CFG_CLKMUL,

      clk_div   => CFG_CLKDIV,

      sdramen   => CFG_SDCTRL + CFG_MCTRL_SDEN,

      noclkfb   => CFG_CLK_NOFB,

      pcien     => 0,

      pcidll    => 0,

      pcisysclk => 0,

      freq      => BOARD_FREQ,

      clk2xen   => 1)

    port map (

      clkin    => clk,

      pciclkin => gnd(0),

      clk      => clkm,

      clkn     => open,

      clk2x    => sample_clk,

      sdclk    => sdclkl,

      pciclk   => open,

      cgi      => cgi,

      cgo      => cgo,

      clk4x    => open);

  rst0 : rstgen                         -- reset generator

    port map (resetn, clkm, cgo.clklock, rstn);

---------------------------------------------------------------------- 

---  AHB CONTROLLER --------------------------------------------------

----------------------------------------------------------------------

  ahb0 : ahbctrl                        -- AHB arbiter/multiplexer

    generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,

                 rrobin  => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,

                 nahbm   => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_GRUSB_DCL+CFG_AHB_JTAG,

                 nahbs   => 9)

    port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);

----------------------------------------------------------------------

---  LEON3 processor and DSU -----------------------------------------

----------------------------------------------------------------------

  cpu : for i in 0 to CFG_NCPU-1 generate

    u0 : leon3s                         -- LEON3 processor

      generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,

                   0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,

                   CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,

                   CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,

                   CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,

                   CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)

      port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,

                irqi(i), irqo(i), dbgi(i), dbgo(i));

  end generate;

  errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);

  dsugen : if CFG_DSU = 1 generate

    dsu0 : dsu3                         -- LEON3 Debug Support Unit

      generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,

                   ncpu   => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)

      port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);

    dsuen_pad  : inpad generic map (tech  => padtech) port map (vcc(0), dsui.enable);

    dsubre_pad : inpad generic map (tech  => padtech) port map (dsubre, dsui.break);

    dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);

  end generate;

  nodsu : if CFG_DSU = 0 generate

    ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';

  end generate;

  dcomgen : if CFG_AHB_UART = 1 generate

    dcom0 : ahbuart                     -- Debug UART

      generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)

      port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));

    dsurx_pad : inpad generic map (tech  => padtech) port map (dsurx, dui.rxd);

    dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);

  end generate;

  nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;

  ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate

    ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)

      port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),

               open, open, open, open, open, open, open, gnd(0));

  end generate;

-----------------------------------------------------------------------

---  USB DEBUG LINK  --------------------------------------------------

-----------------------------------------------------------------------

  usb0 : if CFG_GRUSB_DCL = 1 generate

    usb_d_pads : for i in 0 to 15 generate

      usb_d_pad : iopad generic map(tech => padtech)

        port map (usb_d(i), usbo.dataout(i), usbo.oen, usbi.datain(i));

    end generate;

    usb_h_pad : iopad generic map(tech => padtech)

      port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);

    usb_i0_pad : inpad generic map (tech => padtech) port map (usb_txready, usbi.txready);

    usb_i1_pad : inpad generic map (tech => padtech) port map (usb_rxvalid, usbi.rxvalid);

    usb_i2_pad : inpad generic map (tech => padtech) port map (usb_rxerror, usbi.rxerror);

    usb_i3_pad : inpad generic map (tech => padtech) port map (usb_rxactive, usbi.rxactive);

    usb_i4_pad : inpad generic map (tech => padtech) port map (usb_linestate(0), usbi.linestate(0));

    usb_i5_pad : inpad generic map (tech => padtech) port map (usb_linestate(1), usbi.linestate(1));

    usb_i6_pad : inpad generic map (tech  => padtech) port map (usb_vbus, usbi.vbusvalid);

    usb_o0_pad : outpad generic map (tech => padtech) port map (usb_reset, usbo.reset);

    usb_o1_pad : outpad generic map (tech => padtech) port map (usb_suspend, usbo.suspendm);

    usb_o2_pad : outpad generic map (tech => padtech) port map (usb_termsel, usbo.termselect);

    usb_o3_pad : outpad generic map (tech => padtech) port map (usb_xcvrsel, usbo.xcvrselect(0));

    usb_o4_pad : outpad generic map (tech => padtech) port map (usb_opmode(0), usbo.opmode(0));

    usb_o5_pad : outpad generic map (tech => padtech) port map (usb_opmode(1), usbo.opmode(1));

    usb_o6_pad : outpad generic map (tech => padtech) port map (usb_txvalid, usbo.txvalid);

    usb_clk_pad : clkpad generic map (tech => padtech) port map (usb_clkout, uclk);

    -- USB transceiver shall operate in 8-bit mode

    usb_dbus16 <= not dsw(1);

    -- USB transceiver shall use 8-bit data bus bidirectionally

    -- (bits 15 downto 8 are undriven)

    usb_unidir <= not dsw(2);

    usb_ctrl : grusb_dcl

      generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, memtech => memtech)

      port map (uclk, usbi, usbo, clkm, rstn, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));

  end generate;

----------------------------------------------------------------------

---  Memory controllers ----------------------------------------------

----------------------------------------------------------------------

  mg1 : if CFG_SRCTRL = 1 generate      -- 32-bit PROM/SRAM controller

    sr0 : srctrl generic map (hindex  => 0,

                              ramws   => CFG_SRCTRL_RAMWS, romws => CFG_SRCTRL_PROMWS,

                              ramaddr => 16#400#, rmw => 1)

      port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);

    apbo(0) <= apb_none;

  end generate;

  mg2 : if CFG_MCTRL_LEON2 = 1 generate  -- LEON2 memory controller

    sr1 : mctrl generic map (

      hindex => 0, pindex => 0,

      paddr  => 0, srbanks => 2, sden => CFG_MCTRL_SDEN,

      invclk => CFG_MCTRL_INVCLK, sdlsb => CFG_SDSHIFT,

      sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64

      )

      port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);

    sdpads : if CFG_MCTRL_SDEN = 1 generate  -- SDRAM controller

      sd2 : if CFG_MCTRL_SEPBUS = 1 generate

        sa_pad : outpadv generic map (width => 13) port map (sdaddr, memo.sa(12 downto 0));

        ba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));

        bdr    : for i in 0 to 3 generate

          sddq_pad : iopadv generic map (tech => padtech, width => 8)

            port map (sddq(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),

                      memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));

          sddq2 : if CFG_MCTRL_SD64 = 1 generate

            sddq_pad2 : iopadv generic map (tech => padtech, width => 8)

              port map (sddq(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),

                        memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));

          end generate;

        end generate;

      end generate;

      sdwen_pad : outpad generic map (tech => padtech)

        port map (sdwen, sdo.sdwen);

      sdras_pad : outpad generic map (tech => padtech)

        port map (sdrasn, sdo.rasn);

      sdcas_pad : outpad generic map (tech => padtech)

        port map (sdcasn, sdo.casn);

      sddqm_pad : outpadv generic map (width => 8, tech => padtech)

        port map (sddqm, sdo.dqm);

      sdcke_pad : outpadv generic map (width => 2, tech => padtech)

        port map (sdcke, sdo.sdcke);

      sdcsn_pad : outpadv generic map (width => 2, tech => padtech)

        port map (sdcsn, sdo.sdcsn);

    end generate;

  end generate;

  sdclk_pad  : outpad generic map (tech => padtech, slew => 1) port map (sdclk(0), sdclkl);

  sdclk_pad2 : outpad generic map (tech => padtech, slew => 1) port map (sdclk(1), gnd(0));

  sd_controller : if CFG_SDCTRL /= 0 generate

    sdctrl_1 : sdctrl

      generic map (

        hindex => 5,

        haddr  => 16#600#,

        hmask  => 16#F00#,

        ioaddr => 16#500#,

        iomask => 16#FFF#,

        wprot  => 0,

        invclk => CFG_SDCTRL_INVCLK,

        fast   => 0,

        pwron  => 0,

        sdbits => 32 + 32*CFG_SDCTRL_SD64)

      port map (

        rst   => rstn,

        clk   => clkm,

        ahbsi => ahbsi,

        ahbso => ahbso(5),

        sdi   => sdi,

        sdo   => sdo2);

    -- output signals

    sdaddr <= sdo2.address(14 downto 2);

    sdba   <= sdo2.address(16 downto 15);

    sdcke  <= sdo2.sdcke;

    sdwen  <= sdo2.sdwen;

    sdcsn  <= sdo2.sdcsn;

    sdrasn <= sdo2.rasn;

    sdcasn <= sdo2.casn;

    sddqm  <= sdo2.dqm(7 downto 0);

    query_64_bit : if (CFG_SDCTRL_SD64 /= 0) generate

      sd_pad : iopadv generic map (width => 32)

        port map (sddq(63 downto 32),

                  sdo2.data(63 downto 32),

                  sdo2.bdrive,

                  sdi.data(63 downto 32));

    end generate;

    sd_pad2 : iopadv generic map (width => 32)

      port map (sddq(31 downto 0),

                sdo2.data(31 downto 0),

                sdo2.bdrive,

                sdi.data(31 downto 0));