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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-ge-hpe-mini-lattice/] [testbench.vhd] - Blame information for rev 2

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1 2 dimamali
-----------------------------------------------------------------------------
2
--  LEON3 Demonstration design test bench
3
--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4
--
5
--  This program is free software; you can redistribute it and/or modify
6
--  it under the terms of the GNU General Public License as published by
7
--  the Free Software Foundation; either version 2 of the License, or
8
--  (at your option) any later version.
9
--
10
--  This program is distributed in the hope that it will be useful,
11
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
--  GNU General Public License for more details.
14
------------------------------------------------------------------------------
15
--  modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
16
--  support the use of an external AHB slave and different HPE board versions
17
------------------------------------------------------------------------------
18
--  further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
19
------------------------------------------------------------------------------
20
 
21
 
22
library ieee;
23
use ieee.std_logic_1164.all;
24
library gaisler;
25
use gaisler.libdcom.all;
26
use gaisler.sim.all;
27
library techmap;
28
use techmap.gencomp.all;
29
library micron;
30
use micron.components.all;
31
library gleichmann;
32
use gleichmann.hpi.all;
33
 
34
use work.config.all;                    -- configuration
35
use work.debug.all;
36
use std.textio.all;
37
library grlib;
38
use grlib.stdlib.all;
39
use grlib.stdio.all;
40
use grlib.devices.all;
41
 
42
 
43
entity testbench is
44
  generic (
45
    fabtech : integer := CFG_FABTECH;
46
    memtech : integer := CFG_MEMTECH;
47
    padtech : integer := CFG_PADTECH;
48
    clktech : integer := CFG_CLKTECH;
49
    disas   : integer := CFG_DISAS;     -- Enable disassembly to console
50
    dbguart : integer := CFG_DUART;     -- Print UART on console
51
    pclow   : integer := CFG_PCLOW;
52
 
53
    clkperiod : integer := 40;          -- system clock period
54
    romwidth  : integer := 32;          -- rom data width (8/32)
55
    romdepth  : integer := 16;          -- rom address depth
56
    sramwidth : integer := 32;          -- ram data width (8/16/32)
57
    sramdepth : integer := 18;          -- ram address depth
58
    srambanks : integer := 2            -- number of ram banks
59
    );
60
end;
61
 
62
architecture behav of testbench is
63
 
64
  constant promfile  : string := "prom.srec";   -- rom contents
65
  constant sramfile  : string := "sram.srec";   -- ram contents
66
  constant sdramfile : string := "sdram.srec";  -- sdram contents
67
 
68
 
69
  signal   clk : std_logic := '0';
70
  signal   Rst : std_logic := '0';      -- Reset
71
  constant ct  : integer   := clkperiod/2;
72
 
73
  signal address : std_logic_vector(27 downto 0);
74
  signal data    : std_logic_vector(31 downto 0);
75
 
76
  signal ramsn  : std_logic_vector(4 downto 0);
77
  signal ramoen : std_logic_vector(4 downto 0);
78
  signal rwen   : std_logic_vector(3 downto 0);
79
  signal rwenx  : std_logic_vector(3 downto 0);
80
  signal romsn  : std_logic_vector(1 downto 0);
81
  signal iosn   : std_ulogic;
82
  signal oen    : std_ulogic;
83
  signal read   : std_ulogic;
84
  signal writen : std_ulogic;
85
  signal rben   : std_logic_vector(3 downto 0);
86
  signal tmp    : std_logic_vector(3 downto 0);
87
 
88
  -- ddr memory  
89
  signal ddr_clk    : std_logic;
90
  signal ddr_clkb   : std_logic;
91
  signal ddr_clk_fb : std_logic;
92
  signal ddr_cke    : std_logic;
93
  signal ddr_csb    : std_logic;
94
  signal ddr_web    : std_ulogic;                      -- ddr write enable
95
  signal ddr_rasb   : std_ulogic;                      -- ddr ras
96
  signal ddr_casb   : std_ulogic;                      -- ddr cas
97
  signal ddr_dm     : std_logic_vector (3 downto 0);   -- ddr dm
98
  signal ddr_dqs    : std_logic_vector (3 downto 0);   -- ddr dqs
99
  signal ddr_ad     : std_logic_vector (12 downto 0);  -- ddr address
100
  signal ddr_ba     : std_logic_vector (1 downto 0);   -- ddr bank address
101
  signal ddr_dq     : std_logic_vector (31 downto 0);  -- ddr data
102
 
103
  signal ddr_clk_del  : std_logic;      -- delayed DDR memory clocks
104
  signal ddr_clkb_del : std_logic;
105
 
106
  signal brdyn                               : std_ulogic;
107
  signal bexcn                               : std_ulogic;
108
  signal wdog                                : std_ulogic;
109
  signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
110
  signal dsurst                              : std_ulogic;
111
  signal test                                : std_ulogic;
112
 
113
  signal error : std_logic;
114
 
115
  signal pio  : std_logic_vector(15 downto 0);
116
  signal GND  : std_ulogic := '0';
117
  signal VCC  : std_ulogic := '1';
118
  signal NC   : std_ulogic := 'Z';
119
  signal clk2 : std_ulogic := '1';
120
 
121
  signal sdcke  : std_logic_vector (1 downto 0);  -- clk en
122
  signal sdcsn  : std_logic_vector (1 downto 0);  -- chip sel
123
  signal sdwen  : std_ulogic;                     -- write en
124
  signal sdrasn : std_ulogic;                     -- row addr stb
125
  signal sdcasn : std_ulogic;                     -- col addr stb
126
  signal sddqm  : std_logic_vector (3 downto 0);  -- data i/o mask
127
  signal sd_clk : std_logic_vector(1 downto 0);
128
 
129
  signal sdclk   : std_ulogic;
130
--  alias sdclk   : std_logic is sd_clk(0);
131
  signal plllock : std_ulogic;
132
 
133
-- pulled up high, therefore std_logic
134
  signal txd1, rxd1 : std_logic;
135
 
136
  signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic                    := '0';
137
  signal erxd, etxd                                                         : std_logic_vector(3 downto 0) := (others => '0');
138
  signal erxdt, etxdt                                                       : std_logic_vector(7 downto 0) := (others => '0');
139
  signal emdc, emdio                                                        : std_logic;
140
  signal gtx_clk                                                            : std_ulogic                   := '0';
141
 
142
  signal emddis  : std_logic;
143
  signal epwrdwn : std_logic;
144
  signal ereset  : std_logic;
145
  signal esleep  : std_logic;
146
  signal epause  : std_logic;
147
  signal tp_out  : std_logic_vector(7 downto 0);
148
  signal led_cfg : std_logic_vector(2 downto 0);
149
 
150
  constant lresp : boolean := false;
151
 
152
  signal sa : std_logic_vector(14 downto 0);
153
  signal sd : std_logic_vector(63 downto 0);
154
 
155
 
156
-- Added for Hpe
157
 
158
  signal resoutn : std_logic;
159
  signal disrams : std_logic;
160
  signal sdclk0  : std_ulogic;
161
  signal sdclk1  : std_ulogic;
162
  signal sdba0   : std_logic;           -- bank address zero
163
  signal sdba1   : std_logic;           -- bank address one
164
  signal dsubren : std_ulogic;
165
  signal dsuactn : std_ulogic;
166
  signal bufdir  : std_logic;
167
  signal bufoen  : std_logic;
168
  signal s_sddqm : std_logic_vector (3 downto 0);
169
 
170
  signal HRESETn   : std_ulogic;
171
  signal HSEL      : std_ulogic;
172
  signal HREADY_ba : std_ulogic;        -- hready input signal
173
  signal HADDR     : std_logic_vector(31 downto 0);
174
  signal HWRITE    : std_ulogic;
175
  signal HTRANS    : std_logic_vector(1 downto 0);
176
  signal HSIZE     : std_logic_vector(2 downto 0);
177
  signal HBURST    : std_logic_vector(2 downto 0);
178
  signal HWDATA    : std_logic_vector(31 downto 0);
179
  signal HMASTER   : std_logic_vector(3 downto 0);
180
  signal HMASTLOCK : std_ulogic;
181
  signal HREADY    : std_ulogic;
182
  signal HRESP     : std_logic_vector(1 downto 0);
183
  signal HRDATA    : std_logic_vector(31 downto 0);
184
  signal HSPLIT    : std_logic_vector(15 downto 0);
185
 
186
  signal clk_ctrl        : std_logic_vector(1 downto 0);  -- cpld      
187
  signal CAN_RXD         : std_logic;
188
  signal CAN_TXD         : std_logic;
189
  signal CAN_STB         : std_logic;
190
  signal CAN_TXD_delayed : std_logic := '1';
191
  signal gpio            : std_logic_vector(7 downto 0);
192
 
193
  signal dac : std_ulogic;              -- ouput of sigma delta DAC
194
 
195
  subtype sd_address_range is natural range 14 downto 2;
196
  subtype sd_ba_range is natural range 16 downto 15;
197
 
198
  signal vga_vsync : std_ulogic;
199
  signal vga_hsync : std_ulogic;
200
  signal vga_rd    : std_logic_vector(1 downto 0);
201
  signal vga_gr    : std_logic_vector(1 downto 0);
202
  signal vga_bl    : std_logic_vector(1 downto 0);
203
 
204
  signal ata_data  : std_logic_vector(15 downto 0);
205
  signal ata_da    : std_logic_vector(2 downto 0);
206
  signal ata_cs0   : std_logic;
207
  signal ata_cs1   : std_logic;
208
  signal ata_dior  : std_logic;
209
  signal ata_diow  : std_logic;
210
  signal ata_iordy : std_logic;
211
  signal ata_intrq : std_logic;
212
 
213
 
214
  ---------------------------------------------------------------------------------------
215
  -- HPI SIGNALS
216
  ---------------------------------------------------------------------------------------
217
  signal hpiaddr           : std_logic_vector(1 downto 0);
218
  signal hpidata, hpirdata : std_logic_vector(15 downto 0);
219
  signal hpicsn            : std_ulogic;
220
  signal hpiwrn            : std_ulogic;
221
  signal hpirdn            : std_ulogic;
222
  signal hpiint            : std_ulogic;
223
  signal dbg_equal         : std_ulogic;
224
  signal drive_bus         : std_ulogic;
225
  ---------------------------------------------------------------------------------------
226
begin
227
 
228
  dsubren <= not dsubre;
229
  disrams <= '0';
230
 
231
-- clock and reset
232
 
233
  clk     <= not clk after ct * 1 ns;
234
  rst     <= '1'     after 10 ns;
235
  dsuen   <= '0'; dsubre <= '0'; rxd1 <= 'H';
236
  led_cfg <= "000";                     --put the phy in base10h mode
237
 
238
  d3 : entity work.leon3mini
239
    port map (
240
      resetn  => rst,
241
      resoutn => resoutn,
242
      clk     => clk,
243
      errorn  => error,
244
      address => address,
245
      data    => data,
246
 
247
      ddr_clk0   => ddr_clk,
248
      ddr_clk0b  => ddr_clkb,
249
      ddr_clk_fb => ddr_clk_fb,
250
      ddr_cke0   => ddr_cke,
251
      ddr_cs0b   => ddr_csb,
252
      ddr_web    => ddr_web,
253
      ddr_rasb   => ddr_rasb,
254
      ddr_casb   => ddr_casb,
255
      ddr_dm     => ddr_dm,
256
      ddr_dqs    => ddr_dqs,
257
      ddr_ad     => ddr_ad,
258
      ddr_ba     => ddr_ba,
259
      ddr_dq     => ddr_dq,
260
      ddr_clk1   => open,
261
      ddr_clk1b  => open,
262
      ddr_cke1   => open,
263
      ddr_cs1b   => open,
264
      sertx      => dsutx,
265
      serrx      => dsurx,
266
 
267
      dsuen   => dsuen,
268
      dsubre  => dsubre,
269
      dsuactn => dsuactn,
270
 
271
      ramsn  => ramsn(0),
272
      oen    => oen,
273
      rben   => rben,
274
      writen => writen,
275
      read   => read,
276
      iosn   => iosn,
277
      romsn  => romsn(0),
278
 
279
      emdio   => emdio,
280
      etx_clk => etx_clk,
281
      erx_clk => erx_clk,
282
      erxd    => erxd,
283
      erx_dv  => erx_dv,
284
      erx_er  => erx_er,
285
      erx_col => erx_col,
286
      erx_crs => erx_crs,
287
      etxd    => etxd,
288
      etx_en  => etx_en,
289
      etx_er  => etx_er,
290
      emdc    => emdc,
291
 
292
      ata_data  => ata_data,
293
      ata_da    => ata_da,
294
      ata_cs0   => ata_cs0,
295
      ata_cs1   => ata_cs1,
296
      ata_dior  => ata_dior,
297
      ata_diow  => ata_diow,
298
      ata_iordy => ata_iordy,
299
      ata_intrq => ata_intrq,
300
 
301
      dac       => dac,
302
      vga_vsync => vga_vsync,
303
      vga_hsync => vga_hsync,
304
      vga_rd    => vga_rd,
305
      vga_gr    => vga_gr,
306
      vga_bl    => vga_bl
307
      );
308
 
309
  hpidata <= hpirdata when hpirdn = '0' else (others => 'Z');
310
 
311
  hpiint <= '0';
312
 
313
  hpi_ram_1 : hpi_ram
314
    generic map (
315
      abits => 10,
316
      dbits => 16)
317
    port map (
318
      clk     => clk,
319
      address => hpiaddr,
320
      datain  => hpidata,
321
      dataout => hpirdata,
322
      writen  => hpiwrn,
323
      readn   => hpirdn,
324
      csn     => hpicsn
325
      );
326
 
327
-- optional sdram
328
 
329
  sd0 : if (CFG_MCTRL_SDEN = 1) generate
330
    u0 : mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
331
      port map(
332
        Dq   => data(31 downto 16), Addr => address(sd_address_range),
333
        Ba   => address(sd_ba_range), Clk => sdclk, Cke => sdcke(0),
334
        Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
335
        Dqm  => sddqm(3 downto 2));
336
    u1 : mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
337
      port map(
338
        Dq   => data(15 downto 0), Addr => address(sd_address_range),
339
        Ba   => address(sd_ba_range), Clk => sdclk, Cke => sdcke(0),
340
        Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
341
        Dqm  => sddqm(1 downto 0));
342
    u2 : mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
343
      port map(
344
        Dq   => data(31 downto 16), Addr => address(sd_address_range),
345
        Ba   => address(sd_ba_range), Clk => sdclk, Cke => sdcke(0),
346
        Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
347
        Dqm  => sddqm(3 downto 2));
348
    u3 : mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
349
      port map(
350
        Dq   => data(15 downto 0), Addr => address(sd_address_range),
351
        Ba   => address(sd_ba_range), Clk => sdclk, Cke => sdcke(0),
352
        Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
353
        Dqm  => sddqm(1 downto 0));
354
  end generate;
355
 
356
  ddr_clk_del  <= transport ddr_clk  after 5 ns;
357
  ddr_clkb_del <= transport ddr_clkb after 5 ns;
358
 
359
  u1 : mt46v16m16
360
    port map(
361
      Dq   => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
362
      Ba   => ddr_ba, Clk => ddr_clk_del, Clk_n => ddr_clkb_del, Cke => ddr_cke,
363
      Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
364
      Dm   => ddr_dm(1 downto 0));
365
 
366
  u2 : mt46v16m16
367
    port map(
368
      Dq   => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad,
369
      Ba   => ddr_ba, Clk => ddr_clk_del, Clk_n => ddr_clkb_del, Cke => ddr_cke,
370
      Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
371
      Dm   => ddr_dm(3 downto 2));
372
 
373
  tmp <= not rben;
374
  extbprom : if CFG_BOOTOPT = 0 generate
375
    prom0 : for i in 0 to (romwidth/8)-1 generate
376
      sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
377
        port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
378
                  tmp(i), oen);         -- **** tame: changed rwen to rben
379
    end generate;
380
  end generate extbprom;
381
 
382
 
383
  sram0 : for i in 0 to (sramwidth/8)-1 generate
384
    sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
385
      port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
386
                writen, oen);           -- **** tame: changed rwen to rben
387
    --  rben(0), ramoen(0));    -- **** tame: changed rwen to rben
388
  end generate;
389
 
390
  phy0 : if CFG_GRETH > 0 generate
391
    emdio <= 'H';
392
    erxd  <= erxdt(3 downto 0);
393
    etxdt <= "0000" & etxd;
394
 
395
    p0 : phy
396
      generic map(base1000_t_fd => 0, base1000_t_hd => 0)
397
      port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
398
               erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
399
  end generate;
400
  error <= 'H';                         -- ERROR pull-up
401
 
402
  iuerr : process
403
  begin
404
    wait for 5 us;
405
    assert (to_X01(error) /= '0')
406
      report "*** IU in error mode, simulation halted ***"
407
      severity failure;
408
  end process;
409
 
410
  data <= buskeep(data), (others => 'H') after 250 ns;
411
  sd   <= buskeep(sd), (others   => 'H') after 250 ns;
412
 
413
  test0 : grtestmod
414
    port map (rst, clk, error, address(21 downto 2), data,
415
              iosn, oen, writen, brdyn);
416
 
417
  dcomstart : if CFG_BOOTOPT = 0 generate
418
 
419
    dsucom : process
420
      procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
421
        variable w32 : std_logic_vector(31 downto 0);
422
        variable c8  : std_logic_vector(7 downto 0);
423
        constant txp : time := 160 * 1 ns;
424
      begin
425
        dsutx  <= '1';
426
        dsurst <= '1';
427
--        wait;
428
        wait for 5000 ns;
429
        txc(dsutx, 16#55#, txp);        -- sync uart
430
 
431
--        txc(dsutx, 16#c0#, txp);
432
--        txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
433
--        txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
434
--
435
--        txc(dsutx, 16#c0#, txp);
436
--        txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
437
--        txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
438
--
439
--        txc(dsutx, 16#c0#, txp);
440
--        txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
441
--        txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
442
--
443
--        txc(dsutx, 16#c0#, txp);
444
--        txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
445
--        txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
446
--
447
--        txc(dsutx, 16#80#, txp);
448
--        txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
449
--        rxi(dsurx, w32, txp, lresp);
450
--**********
451
--        print("Start write");
452
        txc(dsutx, 16#c2#, txp);
453
        txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
454
        txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#a0#, txp);
455
        txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#a4#, txp);
456
        txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#a8#, txp);
457
--        txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#ac#, txp);
458
--        txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#10#, txp);
459
--        txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#14#, txp);
460
--        txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#18#, txp);
461
--        txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#1c#, txp);
462
 
463
--        print("Start read");
464
        txc(dsutx, 16#80#, txp);
465
        txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
466
        rxi(dsurx, w32, txp, lresp);
467
 
468
--        print("Res: " & tost(w32));
469
--**********        
470
 
471
        txc(dsutx, 16#a0#, txp);
472
        txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
473
        rxi(dsurx, w32, txp, lresp);
474
 
475
      end;
476
 
477
    begin
478
 
479
      dsucfg(dsutx, dsurx);
480
 
481
      wait;
482
    end process;
483
 
484
  end generate dcomstart;
485
 
486
 
487
  altstimuli : if CFG_BOOTOPT = 1 generate
488
    stimuli : process
489
    begin
490
      dsurx <= '1';
491
      -- rxd1 <= 'H'; --already defined above
492
      txd1  <= 'H';
493
 
494
 
495
      wait;
496
    end process STIMULI;
497
  end generate altstimuli;
498
 
499
end;
500
 
501
 

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