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dimamali |
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design test bench
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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------------------------------------------------------------------------------
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-- modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
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-- support the use of an external AHB slave and different HPE board versions
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------------------------------------------------------------------------------
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-- further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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library techmap;
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use techmap.gencomp.all;
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library micron;
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use micron.components.all;
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library gleichmann;
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use gleichmann.hpi.all;
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use work.config.all; -- configuration
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use work.debug.all;
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use std.textio.all;
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library grlib;
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use grlib.stdlib.all;
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use grlib.stdio.all;
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use grlib.devices.all;
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entity testbench is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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clkperiod : integer := 40; -- system clock period
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romwidth : integer := 32; -- rom data width (8/32)
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romdepth : integer := 16; -- rom address depth
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sramwidth : integer := 32; -- ram data width (8/16/32)
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sramdepth : integer := 18; -- ram address depth
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srambanks : integer := 2 -- number of ram banks
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);
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end;
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architecture behav of testbench is
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constant promfile : string := "prom.srec"; -- rom contents
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constant sramfile : string := "sram.srec"; -- ram contents
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constant sdramfile : string := "sdram.srec"; -- sdram contents
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signal clk : std_logic := '0';
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signal Rst : std_logic := '0'; -- Reset
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constant ct : integer := clkperiod/2;
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signal address : std_logic_vector(27 downto 0);
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signal data : std_logic_vector(31 downto 0);
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signal ramsn : std_logic_vector(4 downto 0);
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signal ramoen : std_logic_vector(4 downto 0);
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signal rwen : std_logic_vector(3 downto 0);
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signal rwenx : std_logic_vector(3 downto 0);
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signal romsn : std_logic_vector(1 downto 0);
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signal iosn : std_ulogic;
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signal oen : std_ulogic;
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signal read : std_ulogic;
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signal writen : std_ulogic;
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signal rben : std_logic_vector(3 downto 0);
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signal tmp : std_logic_vector(3 downto 0);
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-- ddr memory
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signal ddr_clk : std_logic;
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signal ddr_clkb : std_logic;
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signal ddr_clk_fb : std_logic;
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signal ddr_cke : std_logic;
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signal ddr_csb : std_logic;
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signal ddr_web : std_ulogic; -- ddr write enable
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signal ddr_rasb : std_ulogic; -- ddr ras
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signal ddr_casb : std_ulogic; -- ddr cas
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signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
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signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
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signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
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signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
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signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
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signal ddr_clk_del : std_logic; -- delayed DDR memory clocks
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signal ddr_clkb_del : std_logic;
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signal brdyn : std_ulogic;
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signal bexcn : std_ulogic;
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signal wdog : std_ulogic;
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signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
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signal dsurst : std_ulogic;
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signal test : std_ulogic;
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signal error : std_logic;
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signal pio : std_logic_vector(15 downto 0);
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signal GND : std_ulogic := '0';
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signal VCC : std_ulogic := '1';
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signal NC : std_ulogic := 'Z';
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signal clk2 : std_ulogic := '1';
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signal sdcke : std_logic_vector (1 downto 0); -- clk en
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signal sdcsn : std_logic_vector (1 downto 0); -- chip sel
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signal sdwen : std_ulogic; -- write en
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signal sdrasn : std_ulogic; -- row addr stb
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signal sdcasn : std_ulogic; -- col addr stb
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signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
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signal sd_clk : std_logic_vector(1 downto 0);
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signal sdclk : std_ulogic;
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-- alias sdclk : std_logic is sd_clk(0);
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signal plllock : std_ulogic;
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-- pulled up high, therefore std_logic
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signal txd1, rxd1 : std_logic;
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signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
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signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
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signal erxdt, etxdt : std_logic_vector(7 downto 0) := (others => '0');
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signal emdc, emdio : std_logic;
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signal gtx_clk : std_ulogic := '0';
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signal emddis : std_logic;
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signal epwrdwn : std_logic;
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signal ereset : std_logic;
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signal esleep : std_logic;
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signal epause : std_logic;
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signal tp_out : std_logic_vector(7 downto 0);
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signal led_cfg : std_logic_vector(2 downto 0);
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constant lresp : boolean := false;
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signal sa : std_logic_vector(14 downto 0);
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signal sd : std_logic_vector(63 downto 0);
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-- Added for Hpe
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signal resoutn : std_logic;
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signal disrams : std_logic;
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signal sdclk0 : std_ulogic;
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signal sdclk1 : std_ulogic;
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signal sdba0 : std_logic; -- bank address zero
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signal sdba1 : std_logic; -- bank address one
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signal dsubren : std_ulogic;
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signal dsuactn : std_ulogic;
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signal bufdir : std_logic;
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signal bufoen : std_logic;
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signal s_sddqm : std_logic_vector (3 downto 0);
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signal HRESETn : std_ulogic;
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signal HSEL : std_ulogic;
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signal HREADY_ba : std_ulogic; -- hready input signal
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signal HADDR : std_logic_vector(31 downto 0);
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signal HWRITE : std_ulogic;
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signal HTRANS : std_logic_vector(1 downto 0);
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signal HSIZE : std_logic_vector(2 downto 0);
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signal HBURST : std_logic_vector(2 downto 0);
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signal HWDATA : std_logic_vector(31 downto 0);
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signal HMASTER : std_logic_vector(3 downto 0);
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signal HMASTLOCK : std_ulogic;
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signal HREADY : std_ulogic;
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signal HRESP : std_logic_vector(1 downto 0);
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signal HRDATA : std_logic_vector(31 downto 0);
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signal HSPLIT : std_logic_vector(15 downto 0);
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signal clk_ctrl : std_logic_vector(1 downto 0); -- cpld
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signal CAN_RXD : std_logic;
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signal CAN_TXD : std_logic;
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signal CAN_STB : std_logic;
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signal CAN_TXD_delayed : std_logic := '1';
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signal gpio : std_logic_vector(7 downto 0);
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signal dac : std_ulogic; -- ouput of sigma delta DAC
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subtype sd_address_range is natural range 14 downto 2;
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subtype sd_ba_range is natural range 16 downto 15;
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signal vga_vsync : std_ulogic;
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signal vga_hsync : std_ulogic;
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signal vga_rd : std_logic_vector(1 downto 0);
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signal vga_gr : std_logic_vector(1 downto 0);
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signal vga_bl : std_logic_vector(1 downto 0);
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signal ata_data : std_logic_vector(15 downto 0);
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signal ata_da : std_logic_vector(2 downto 0);
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signal ata_cs0 : std_logic;
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signal ata_cs1 : std_logic;
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signal ata_dior : std_logic;
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signal ata_diow : std_logic;
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signal ata_iordy : std_logic;
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signal ata_intrq : std_logic;
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---------------------------------------------------------------------------------------
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-- HPI SIGNALS
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---------------------------------------------------------------------------------------
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signal hpiaddr : std_logic_vector(1 downto 0);
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signal hpidata, hpirdata : std_logic_vector(15 downto 0);
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signal hpicsn : std_ulogic;
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signal hpiwrn : std_ulogic;
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signal hpirdn : std_ulogic;
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signal hpiint : std_ulogic;
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signal dbg_equal : std_ulogic;
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signal drive_bus : std_ulogic;
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---------------------------------------------------------------------------------------
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begin
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dsubren <= not dsubre;
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disrams <= '0';
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-- clock and reset
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clk <= not clk after ct * 1 ns;
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rst <= '1' after 10 ns;
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dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
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led_cfg <= "000"; --put the phy in base10h mode
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d3 : entity work.leon3mini
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port map (
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resetn => rst,
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resoutn => resoutn,
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clk => clk,
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errorn => error,
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address => address,
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data => data,
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ddr_clk0 => ddr_clk,
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ddr_clk0b => ddr_clkb,
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ddr_clk_fb => ddr_clk_fb,
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ddr_cke0 => ddr_cke,
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ddr_cs0b => ddr_csb,
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ddr_web => ddr_web,
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ddr_rasb => ddr_rasb,
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ddr_casb => ddr_casb,
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ddr_dm => ddr_dm,
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ddr_dqs => ddr_dqs,
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ddr_ad => ddr_ad,
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ddr_ba => ddr_ba,
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ddr_dq => ddr_dq,
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ddr_clk1 => open,
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ddr_clk1b => open,
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ddr_cke1 => open,
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ddr_cs1b => open,
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sertx => dsutx,
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serrx => dsurx,
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dsuen => dsuen,
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dsubre => dsubre,
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dsuactn => dsuactn,
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ramsn => ramsn(0),
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oen => oen,
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rben => rben,
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writen => writen,
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read => read,
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iosn => iosn,
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romsn => romsn(0),
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emdio => emdio,
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etx_clk => etx_clk,
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erx_clk => erx_clk,
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erxd => erxd,
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erx_dv => erx_dv,
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erx_er => erx_er,
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erx_col => erx_col,
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erx_crs => erx_crs,
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etxd => etxd,
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etx_en => etx_en,
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etx_er => etx_er,
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emdc => emdc,
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ata_data => ata_data,
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ata_da => ata_da,
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ata_cs0 => ata_cs0,
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ata_cs1 => ata_cs1,
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ata_dior => ata_dior,
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ata_diow => ata_diow,
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ata_iordy => ata_iordy,
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ata_intrq => ata_intrq,
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dac => dac,
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vga_vsync => vga_vsync,
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vga_hsync => vga_hsync,
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vga_rd => vga_rd,
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vga_gr => vga_gr,
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vga_bl => vga_bl
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);
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hpidata <= hpirdata when hpirdn = '0' else (others => 'Z');
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hpiint <= '0';
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hpi_ram_1 : hpi_ram
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generic map (
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abits => 10,
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dbits => 16)
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port map (
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clk => clk,
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address => hpiaddr,
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datain => hpidata,
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dataout => hpirdata,
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writen => hpiwrn,
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readn => hpirdn,
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csn => hpicsn
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);
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-- optional sdram
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sd0 : if (CFG_MCTRL_SDEN = 1) generate
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u0 : mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
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port map(
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Dq => data(31 downto 16), Addr => address(sd_address_range),
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Ba => address(sd_ba_range), Clk => sdclk, Cke => sdcke(0),
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Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm => sddqm(3 downto 2));
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|
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u1 : mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
|
337 |
|
|
port map(
|
338 |
|
|
Dq => data(15 downto 0), Addr => address(sd_address_range),
|
339 |
|
|
Ba => address(sd_ba_range), Clk => sdclk, Cke => sdcke(0),
|
340 |
|
|
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
341 |
|
|
Dqm => sddqm(1 downto 0));
|
342 |
|
|
u2 : mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
|
343 |
|
|
port map(
|
344 |
|
|
Dq => data(31 downto 16), Addr => address(sd_address_range),
|
345 |
|
|
Ba => address(sd_ba_range), Clk => sdclk, Cke => sdcke(0),
|
346 |
|
|
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
347 |
|
|
Dqm => sddqm(3 downto 2));
|
348 |
|
|
u3 : mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
|
349 |
|
|
port map(
|
350 |
|
|
Dq => data(15 downto 0), Addr => address(sd_address_range),
|
351 |
|
|
Ba => address(sd_ba_range), Clk => sdclk, Cke => sdcke(0),
|
352 |
|
|
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
|
353 |
|
|
Dqm => sddqm(1 downto 0));
|
354 |
|
|
end generate;
|
355 |
|
|
|
356 |
|
|
ddr_clk_del <= transport ddr_clk after 5 ns;
|
357 |
|
|
ddr_clkb_del <= transport ddr_clkb after 5 ns;
|
358 |
|
|
|
359 |
|
|
u1 : mt46v16m16
|
360 |
|
|
port map(
|
361 |
|
|
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
|
362 |
|
|
Ba => ddr_ba, Clk => ddr_clk_del, Clk_n => ddr_clkb_del, Cke => ddr_cke,
|
363 |
|
|
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
|
364 |
|
|
Dm => ddr_dm(1 downto 0));
|
365 |
|
|
|
366 |
|
|
u2 : mt46v16m16
|
367 |
|
|
port map(
|
368 |
|
|
Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad,
|
369 |
|
|
Ba => ddr_ba, Clk => ddr_clk_del, Clk_n => ddr_clkb_del, Cke => ddr_cke,
|
370 |
|
|
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
|
371 |
|
|
Dm => ddr_dm(3 downto 2));
|
372 |
|
|
|
373 |
|
|
tmp <= not rben;
|
374 |
|
|
extbprom : if CFG_BOOTOPT = 0 generate
|
375 |
|
|
prom0 : for i in 0 to (romwidth/8)-1 generate
|
376 |
|
|
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
|
377 |
|
|
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
|
378 |
|
|
tmp(i), oen); -- **** tame: changed rwen to rben
|
379 |
|
|
end generate;
|
380 |
|
|
end generate extbprom;
|
381 |
|
|
|
382 |
|
|
|
383 |
|
|
sram0 : for i in 0 to (sramwidth/8)-1 generate
|
384 |
|
|
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
|
385 |
|
|
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
|
386 |
|
|
writen, oen); -- **** tame: changed rwen to rben
|
387 |
|
|
-- rben(0), ramoen(0)); -- **** tame: changed rwen to rben
|
388 |
|
|
end generate;
|
389 |
|
|
|
390 |
|
|
phy0 : if CFG_GRETH > 0 generate
|
391 |
|
|
emdio <= 'H';
|
392 |
|
|
erxd <= erxdt(3 downto 0);
|
393 |
|
|
etxdt <= "0000" & etxd;
|
394 |
|
|
|
395 |
|
|
p0 : phy
|
396 |
|
|
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
|
397 |
|
|
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
|
398 |
|
|
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
|
399 |
|
|
end generate;
|
400 |
|
|
error <= 'H'; -- ERROR pull-up
|
401 |
|
|
|
402 |
|
|
iuerr : process
|
403 |
|
|
begin
|
404 |
|
|
wait for 5 us;
|
405 |
|
|
assert (to_X01(error) /= '0')
|
406 |
|
|
report "*** IU in error mode, simulation halted ***"
|
407 |
|
|
severity failure;
|
408 |
|
|
end process;
|
409 |
|
|
|
410 |
|
|
data <= buskeep(data), (others => 'H') after 250 ns;
|
411 |
|
|
sd <= buskeep(sd), (others => 'H') after 250 ns;
|
412 |
|
|
|
413 |
|
|
test0 : grtestmod
|
414 |
|
|
port map (rst, clk, error, address(21 downto 2), data,
|
415 |
|
|
iosn, oen, writen, brdyn);
|
416 |
|
|
|
417 |
|
|
dcomstart : if CFG_BOOTOPT = 0 generate
|
418 |
|
|
|
419 |
|
|
dsucom : process
|
420 |
|
|
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
|
421 |
|
|
variable w32 : std_logic_vector(31 downto 0);
|
422 |
|
|
variable c8 : std_logic_vector(7 downto 0);
|
423 |
|
|
constant txp : time := 160 * 1 ns;
|
424 |
|
|
begin
|
425 |
|
|
dsutx <= '1';
|
426 |
|
|
dsurst <= '1';
|
427 |
|
|
-- wait;
|
428 |
|
|
wait for 5000 ns;
|
429 |
|
|
txc(dsutx, 16#55#, txp); -- sync uart
|
430 |
|
|
|
431 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
432 |
|
|
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
433 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
|
434 |
|
|
--
|
435 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
436 |
|
|
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
|
437 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
|
438 |
|
|
--
|
439 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
440 |
|
|
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
|
441 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
|
442 |
|
|
--
|
443 |
|
|
-- txc(dsutx, 16#c0#, txp);
|
444 |
|
|
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
|
445 |
|
|
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
|
446 |
|
|
--
|
447 |
|
|
-- txc(dsutx, 16#80#, txp);
|
448 |
|
|
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
|
449 |
|
|
-- rxi(dsurx, w32, txp, lresp);
|
450 |
|
|
--**********
|
451 |
|
|
-- print("Start write");
|
452 |
|
|
txc(dsutx, 16#c2#, txp);
|
453 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
|
454 |
|
|
txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#a0#, txp);
|
455 |
|
|
txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#a4#, txp);
|
456 |
|
|
txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#a8#, txp);
|
457 |
|
|
-- txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#ac#, txp);
|
458 |
|
|
-- txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#10#, txp);
|
459 |
|
|
-- txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#14#, txp);
|
460 |
|
|
-- txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#18#, txp);
|
461 |
|
|
-- txa(dsutx, 16#aa#, 16#aa#, 16#aa#, 16#1c#, txp);
|
462 |
|
|
|
463 |
|
|
-- print("Start read");
|
464 |
|
|
txc(dsutx, 16#80#, txp);
|
465 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
|
466 |
|
|
rxi(dsurx, w32, txp, lresp);
|
467 |
|
|
|
468 |
|
|
-- print("Res: " & tost(w32));
|
469 |
|
|
--**********
|
470 |
|
|
|
471 |
|
|
txc(dsutx, 16#a0#, txp);
|
472 |
|
|
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
|
473 |
|
|
rxi(dsurx, w32, txp, lresp);
|
474 |
|
|
|
475 |
|
|
end;
|
476 |
|
|
|
477 |
|
|
begin
|
478 |
|
|
|
479 |
|
|
dsucfg(dsutx, dsurx);
|
480 |
|
|
|
481 |
|
|
wait;
|
482 |
|
|
end process;
|
483 |
|
|
|
484 |
|
|
end generate dcomstart;
|
485 |
|
|
|
486 |
|
|
|
487 |
|
|
altstimuli : if CFG_BOOTOPT = 1 generate
|
488 |
|
|
stimuli : process
|
489 |
|
|
begin
|
490 |
|
|
dsurx <= '1';
|
491 |
|
|
-- rxd1 <= 'H'; --already defined above
|
492 |
|
|
txd1 <= 'H';
|
493 |
|
|
|
494 |
|
|
|
495 |
|
|
wait;
|
496 |
|
|
end process STIMULI;
|
497 |
|
|
end generate altstimuli;
|
498 |
|
|
|
499 |
|
|
end;
|
500 |
|
|
|
501 |
|
|
|