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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-cpci-xc2v6000/] [Makefile] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali
GRLIB=../..
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TOP=leon3mp
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BOARD=gr-cpci-xc2v
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include $(GRLIB)/boards/$(BOARD)/Makefile.inc
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DEVICE=$(PART)-$(PACKAGE)$(SPEED)
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UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
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QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
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EFFORT=high
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XSTOPT=
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SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
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ISEMAPOPT=-timing
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VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
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VHDLSIMFILES=testbench.vhd
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SIMTOP=testbench
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SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
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BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
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CLEAN=soft-clean
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TECHLIBS = simprim unisim
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LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
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        tmtc openchip hynix cypress ihp gleichmann usbhc
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DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata grusbhc \
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        haps ascs slink coremp7
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FILESKIP = grcan.vhd
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include $(GRLIB)/bin/Makefile
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include $(GRLIB)/software/leon3/Makefile
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##################  project specific targets ##########################

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