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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-pci-xc5v/] [default.sdc] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali
# Synplicity, Inc. constraint file
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# /home/jiri/ibm/vhdl/grlib/boards/gr-cpci-xc2v/default.sdc
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# Written on Mon Feb 14 11:45:37 2005
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# by Synplify Pro, Synplify Pro 8.0 Scope Editor
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#
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# Collections
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#
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#
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# Clocks
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#
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define_clock  -name {clk}  -freq 65.000 -clockgroup default_clkgroup
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define_clock  -name {pci_clk}  -freq 33.000 -clockgroup pci_clkgroup -route 6
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define_clock  -name {usb_clkout}  -freq 60.000 -clockgroup usb_clkgroup
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define_clock  -name {leon3mp|etx_clk} -freq 25.000 -clockgroup etx_clkgroup
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define_clock  -name {leon3mp|erx_clk} -freq 125.000 -clockgroup erx_clkgroup
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#define_clock  -name {leon3mp|egtx_clk}  -freq 125.000 -clockgroup phy_egtx_clkgroup -route 2.000
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define_clock  -name {leon3mp|eth_macclk}  -freq 125.000 -clockgroup phy_egtx_clkgroup -route 2.000
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define_clock  -name {leon3mp|clkgen0.clkin}  -freq 50.000 -route 2.0 -clockgroup ahb_clkgroup
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#
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# Clock to Clock
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define_clock_delay -rise leon3mp|clkgen0.xc5l.v.clk0B_derived_clock -rise leon3mp|egtx_clk -false
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define_clock_delay -rise leon3mp|egtx_clk -rise leon3mp|clkgen0.xc5l.v.clk0B_derived_clock -false
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#
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#
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# Inputs/Outputs
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#
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define_output_delay -disable    -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
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define_input_delay -disable      -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
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define_output_delay      -default  19.00 -improve 0.00 -route 3.00 -ref {pci_clk:r}
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define_input_delay       -default  23.00 -improve 0.00 -route 2.00 -ref {pci_clk:r}
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define_input_delay       {pci_rst}  0.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
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define_input_delay       -default 6.50 -improve 0.00 -route 1.00 -ref {usb_clkout:r}
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define_output_delay      -default 6.50 -improve 0.00 -route 1.00 -ref {usb_clkout:r}
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define_output_delay      {usb_resetn} 0.00 -improve 0.00 -route 0.00 -ref {usb_clkout:r}
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define_input_delay       -default 2.00 -improve 0.00 -route 1.00 -ref {eth_macclk:r}
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define_output_delay      -default 5.50 -improve 0.00 -route 1.00 -ref {eth_macclk:r}
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#
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# Registers
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#
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#
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# Multicycle Path
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#
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#
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# False Path
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#
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#
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# Path Delay
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#
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#
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# Attributes
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#
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define_global_attribute          syn_useioff {1}
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#
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# I/O standards
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#
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#
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# Compile Points
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#
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#
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# Other Constraints
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#

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