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dimamali |
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.can.all;
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use gaisler.pci.all;
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use gaisler.net.all;
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use gaisler.jtag.all;
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use gaisler.spacewire.all;
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use gaisler.grusb.all;
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library esa;
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use esa.memoryctrl.all;
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use esa.pcicomp.all;
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use work.config.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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resetn : in std_logic;
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clk : in std_logic;
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pllref : in std_logic;
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errorn : out std_logic;
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wdogn : out std_logic;
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address : out std_logic_vector(27 downto 0);
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data : inout std_logic_vector(31 downto 0);
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sa : out std_logic_vector(14 downto 0);
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sd : inout std_logic_vector(63 downto 0);
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sdclk : out std_logic;
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sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
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sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
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sdwen : out std_logic; -- sdram write enable
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sdrasn : out std_logic; -- sdram ras
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sdcasn : out std_logic; -- sdram cas
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sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
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dsutx : out std_logic; -- DSU tx data
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dsurx : in std_logic; -- DSU rx data
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dsuen : in std_logic;
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dsubre : in std_logic;
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dsuact : out std_logic;
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txd1 : out std_logic; -- UART1 tx data
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rxd1 : in std_logic; -- UART1 rx data
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txd2 : out std_logic; -- UART2 tx data
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rxd2 : in std_logic; -- UART2 rx data
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ramsn : out std_logic_vector (4 downto 0);
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ramoen : out std_logic_vector (4 downto 0);
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rwen : out std_logic_vector (3 downto 0);
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oen : out std_logic;
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writen : out std_logic;
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read : out std_logic;
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iosn : out std_logic;
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romsn : out std_logic_vector (1 downto 0);
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brdyn : in std_logic; -- bus ready
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bexcn : in std_logic; -- bus exception
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gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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emdio : inout std_logic; -- ethernet PHY interface
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eth_macclk : in std_logic;
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etx_clk : in std_logic;
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erx_clk : in std_logic;
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erxd : in std_logic_vector(7 downto 0);
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erx_dv : in std_logic;
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erx_er : in std_logic;
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erx_col : in std_logic;
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erx_crs : in std_logic;
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etxd : out std_logic_vector(7 downto 0);
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etx_en : out std_logic;
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etx_er : out std_logic;
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emdc : out std_logic;
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pci_rst : inout std_logic; -- PCI bus
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pci_clk : in std_logic;
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pci_gnt : in std_logic;
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pci_idsel : in std_logic;
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pci_lock : inout std_logic;
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pci_ad : inout std_logic_vector(31 downto 0);
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pci_cbe : inout std_logic_vector(3 downto 0);
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pci_frame : inout std_logic;
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pci_irdy : inout std_logic;
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pci_trdy : inout std_logic;
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pci_devsel : inout std_logic;
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pci_stop : inout std_logic;
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pci_perr : inout std_logic;
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pci_par : inout std_logic;
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pci_req : inout std_logic;
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pci_serr : inout std_logic;
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pci_host : in std_logic;
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pci_66 : in std_logic;
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pci_arb_req : in std_logic_vector(0 to 3);
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pci_arb_gnt : out std_logic_vector(0 to 3);
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can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
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can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
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-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
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spw_clk : in std_logic;
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spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
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usb_clkout : in std_logic;
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usb_d : inout std_logic_vector(7 downto 0);
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usb_nxt : in std_logic;
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usb_stp : out std_logic;
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usb_dir : in std_logic;
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usb_resetn : out std_ulogic
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);
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end;
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architecture rtl of leon3mp is
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constant blength : integer := 12;
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constant fifodepth : integer := 8;
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signal vcc, gnd : std_logic_vector(4 downto 0);
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal sdi : sdctrl_in_type;
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signal sdo : sdram_out_type;
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signal sdo2, sdo3 : sdctrl_out_type;
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
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signal cgi, cgi2 : clkgen_in_type;
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signal cgo, cgo2 : clkgen_out_type;
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signal u1i, u2i, dui : uart_in_type;
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signal u1o, u2o, duo : uart_out_type;
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signal irqi : irq_in_vector(0 to CFG_NCPU-1);
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signal irqo : irq_out_vector(0 to CFG_NCPU-1);
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signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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signal pcii : pci_in_type;
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signal pcio : pci_out_type;
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signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
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signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
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signal spw_clkl : std_logic;
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signal stati : ahbstat_in_type;
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signal ethi, ethi1, ethi2 : eth_in_type;
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signal etho, etho1, etho2 : eth_out_type;
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signal ethclk, egtx_clk_fb : std_logic;
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signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
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signal gpti : gptimer_in_type;
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signal gpto : gptimer_out_type;
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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signal clklock, elock, ulock : std_ulogic;
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signal can_lrx, can_ltx : std_logic_vector(0 to 7);
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signal lclk, pci_lclk : std_logic;
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signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
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signal tck, tms, tdi, tdo : std_logic;
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signal usbi : grusb_in_vector(0 downto 0);
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signal usbo : grusb_out_vector(0 downto 0);
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signal uclk : std_ulogic := '0';
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constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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constant IOAEN : integer := CFG_CAN + CFG_PCI + CFG_GRUSBHC +
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CFG_GRUSBDC;
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constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
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constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
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constant OEPOL : integer := padoen_polarity(padtech);
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constant notag : integer := 1;
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attribute syn_keep : boolean;
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attribute syn_preserve : boolean;
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attribute keep : boolean;
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begin
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
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clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
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pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
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port map (pci_clk, pci_lclk);
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clkgen0 : clkgen -- clock generator
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generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
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CFG_INVCLK, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
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port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
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sdclk_pad : outpad generic map (tech => padtech, slew => 1)
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port map (sdclk, sdclkl);
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rst0 : rstgen -- reset generator
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port map (resetn, clkm, clklock, rstn, rstraw);
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clklock <= cgo.clklock and elock and ulock;
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----------------------------------------------------------------------
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--- AHB CONTROLLER --------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
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nahbm => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+
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CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+
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CFG_GRUSBHC*(CFG_GRUSBHC_EHC+CFG_GRUSBHC_UHC)+
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CFG_GRUSBDC*CFG_GRUSBDC_AIFACE,
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nahbs => 8+CFG_GRUSBHC*CFG_GRUSBHC_UHC+CFG_GRUSBDC)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- LEON3 processor and DSU -----------------------------------------
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----------------------------------------------------------------------
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cpu : for i in 0 to CFG_NCPU-1 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, notag, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
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port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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end generate;
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errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
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dsugen : if CFG_DSU = 1 generate
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
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dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
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dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
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end generate;
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nodsu : if CFG_DSU = 0 generate
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ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
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|
end generate;
|
301 |
|
|
|
302 |
|
|
dcomgen : if CFG_AHB_UART = 1 generate
|
303 |
|
|
dcom0: ahbuart -- Debug UART
|
304 |
|
|
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
|
305 |
|
|
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
|
306 |
|
|
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
|
307 |
|
|
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
|
308 |
|
|
end generate;
|
309 |
|
|
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
|
310 |
|
|
|
311 |
|
|
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
|
312 |
|
|
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
|
313 |
|
|
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
|
314 |
|
|
open, open, open, open, open, open, open, gnd(0));
|
315 |
|
|
end generate;
|
316 |
|
|
|
317 |
|
|
----------------------------------------------------------------------
|
318 |
|
|
--- Memory controllers ----------------------------------------------
|
319 |
|
|
----------------------------------------------------------------------
|
320 |
|
|
|
321 |
|
|
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
|
322 |
|
|
|
323 |
|
|
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
|
324 |
|
|
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
|
325 |
|
|
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
|
326 |
|
|
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
|
327 |
|
|
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
|
328 |
|
|
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
|
329 |
|
|
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
|
330 |
|
|
|
331 |
|
|
addr_pad : outpadv generic map (width => 28, tech => padtech)
|
332 |
|
|
port map (address, memo.address(27 downto 0));
|
333 |
|
|
rams_pad : outpadv generic map (width => 5, tech => padtech)
|
334 |
|
|
port map (ramsn, memo.ramsn(4 downto 0));
|
335 |
|
|
roms_pad : outpadv generic map (width => 2, tech => padtech)
|
336 |
|
|
port map (romsn, memo.romsn(1 downto 0));
|
337 |
|
|
oen_pad : outpad generic map (tech => padtech)
|
338 |
|
|
port map (oen, memo.oen);
|
339 |
|
|
rwen_pad : outpadv generic map (width => 4, tech => padtech)
|
340 |
|
|
port map (rwen, memo.wrn);
|
341 |
|
|
roen_pad : outpadv generic map (width => 5, tech => padtech)
|
342 |
|
|
port map (ramoen, memo.ramoen(4 downto 0));
|
343 |
|
|
wri_pad : outpad generic map (tech => padtech)
|
344 |
|
|
port map (writen, memo.writen);
|
345 |
|
|
read_pad : outpad generic map (tech => padtech)
|
346 |
|
|
port map (read, memo.read);
|
347 |
|
|
iosn_pad : outpad generic map (tech => padtech)
|
348 |
|
|
port map (iosn, memo.iosn);
|
349 |
|
|
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
|
350 |
|
|
port map (data, memo.data, memo.vbdrive, memi.data);
|
351 |
|
|
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
|
352 |
|
|
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
|
353 |
|
|
memi.writen <= '1'; memi.wrn <= "1111";
|
354 |
|
|
|
355 |
|
|
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
|
356 |
|
|
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
|
357 |
|
|
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
|
358 |
|
|
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
|
359 |
|
|
port map (sd(31 downto 0), memo.sddata(31 downto 0),
|
360 |
|
|
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
|
361 |
|
|
sd2 : if CFG_MCTRL_SD64 = 1 generate
|
362 |
|
|
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
|
363 |
|
|
port map (sd(63 downto 32), memo.data(31 downto 0),
|
364 |
|
|
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
|
365 |
|
|
end generate;
|
366 |
|
|
end generate;
|
367 |
|
|
sdwen_pad : outpad generic map (tech => padtech)
|
368 |
|
|
port map (sdwen, sdo.sdwen);
|
369 |
|
|
sdras_pad : outpad generic map (tech => padtech)
|
370 |
|
|
port map (sdrasn, sdo.rasn);
|
371 |
|
|
sdcas_pad : outpad generic map (tech => padtech)
|
372 |
|
|
port map (sdcasn, sdo.casn);
|
373 |
|
|
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
|
374 |
|
|
port map (sddqm, sdo.dqm);
|
375 |
|
|
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
|
376 |
|
|
port map (sdcke, sdo.sdcke);
|
377 |
|
|
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
|
378 |
|
|
port map (sdcsn, sdo.sdcsn);
|
379 |
|
|
end generate;
|
380 |
|
|
end generate;
|
381 |
|
|
|
382 |
|
|
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
|
383 |
|
|
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
|
384 |
|
|
port map (sdcke, sdo3.sdcke);
|
385 |
|
|
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
|
386 |
|
|
port map (sdcsn, sdo3.sdcsn);
|
387 |
|
|
end generate;
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
|
391 |
|
|
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
|
392 |
|
|
rams_pad : outpadv generic map (width => 5, tech => padtech)
|
393 |
|
|
port map (ramsn, vcc);
|
394 |
|
|
roms_pad : outpadv generic map (width => 2, tech => padtech)
|
395 |
|
|
port map (romsn, vcc(1 downto 0));
|
396 |
|
|
end generate;
|
397 |
|
|
|
398 |
|
|
|
399 |
|
|
----------------------------------------------------------------------
|
400 |
|
|
--- APB Bridge and various periherals -------------------------------
|
401 |
|
|
----------------------------------------------------------------------
|
402 |
|
|
|
403 |
|
|
apb0 : apbctrl -- AHB/APB bridge
|
404 |
|
|
generic map (hindex => 1, haddr => CFG_APBADDR)
|
405 |
|
|
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
|
406 |
|
|
|
407 |
|
|
ua1 : if CFG_UART1_ENABLE /= 0 generate
|
408 |
|
|
uart1 : apbuart -- UART 1
|
409 |
|
|
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
410 |
|
|
fifosize => CFG_UART1_FIFO)
|
411 |
|
|
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
|
412 |
|
|
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
|
413 |
|
|
end generate;
|
414 |
|
|
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
|
415 |
|
|
|
416 |
|
|
ua2 : if CFG_UART2_ENABLE /= 0 generate
|
417 |
|
|
uart2 : apbuart -- UART 2
|
418 |
|
|
generic map (pindex => 6, paddr => 6, pirq => 3, fifosize => CFG_UART2_FIFO)
|
419 |
|
|
port map (rstn, clkm, apbi, apbo(6), u2i, u2o);
|
420 |
|
|
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
|
421 |
|
|
end generate;
|
422 |
|
|
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(6) <= apb_none; end generate;
|
423 |
|
|
|
424 |
|
|
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
|
425 |
|
|
irqctrl0 : irqmp -- interrupt controller
|
426 |
|
|
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
|
427 |
|
|
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
|
428 |
|
|
end generate;
|
429 |
|
|
irq3 : if CFG_IRQ3_ENABLE = 0 generate
|
430 |
|
|
x : for i in 0 to CFG_NCPU-1 generate
|
431 |
|
|
irqi(i).irl <= "0000";
|
432 |
|
|
end generate;
|
433 |
|
|
-- apbo(2) <= apb_none;
|
434 |
|
|
end generate;
|
435 |
|
|
|
436 |
|
|
gpt : if CFG_GPT_ENABLE /= 0 generate
|
437 |
|
|
timer0 : gptimer -- timer unit
|
438 |
|
|
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
439 |
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
440 |
|
|
nbits => CFG_GPT_TW)
|
441 |
|
|
port map (rstn, clkm, apbi, apbo(3), gpti, open);
|
442 |
|
|
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
|
443 |
|
|
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, gpto.wdog);
|
444 |
|
|
end generate;
|
445 |
|
|
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
446 |
|
|
|
447 |
|
|
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
|
448 |
|
|
grgpio0: grgpio
|
449 |
|
|
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
|
450 |
|
|
nbits => CFG_GRGPIO_WIDTH)
|
451 |
|
|
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
|
452 |
|
|
|
453 |
|
|
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
|
454 |
|
|
pio_pad : iopad generic map (tech => padtech)
|
455 |
|
|
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
|
456 |
|
|
end generate;
|
457 |
|
|
end generate;
|
458 |
|
|
|
459 |
|
|
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
|
460 |
|
|
stati.cerror(0) <= memo.ce;
|
461 |
|
|
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
|
462 |
|
|
nftslv => CFG_AHBSTATN)
|
463 |
|
|
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
|
464 |
|
|
end generate;
|
465 |
|
|
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
|
466 |
|
|
|
467 |
|
|
-----------------------------------------------------------------------
|
468 |
|
|
--- PCI ------------------------------------------------------------
|
469 |
|
|
-----------------------------------------------------------------------
|
470 |
|
|
|
471 |
|
|
pp : if CFG_PCI /= 0 generate
|
472 |
|
|
|
473 |
|
|
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
|
474 |
|
|
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
|
475 |
|
|
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, nsync => 2)
|
476 |
|
|
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
|
477 |
|
|
end generate;
|
478 |
|
|
|
479 |
|
|
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
|
480 |
|
|
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
|
481 |
|
|
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
|
482 |
|
|
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
|
483 |
|
|
ioaddr => 16#400#, nsync => 2, hostrst => 1)
|
484 |
|
|
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
|
485 |
|
|
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
|
486 |
|
|
end generate;
|
487 |
|
|
|
488 |
|
|
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
|
489 |
|
|
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
|
490 |
|
|
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
|
491 |
|
|
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
|
492 |
|
|
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
|
493 |
|
|
nsync => 2, hostrst => 1)
|
494 |
|
|
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
|
495 |
|
|
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
|
496 |
|
|
end generate;
|
497 |
|
|
|
498 |
|
|
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
|
499 |
|
|
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
|
500 |
|
|
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
|
501 |
|
|
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
|
502 |
|
|
end generate;
|
503 |
|
|
|
504 |
|
|
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
|
505 |
|
|
pciarb0 : pciarb generic map (pindex => 8, paddr => 8,
|
506 |
|
|
apb_en => CFG_PCI_ARBAPB)
|
507 |
|
|
port map ( clk => pciclk, rst_n => pcii.rst,
|
508 |
|
|
req_n => pci_arb_req_n, frame_n => pcii.frame,
|
509 |
|
|
gnt_n => pci_arb_gnt_n, pclk => clkm,
|
510 |
|
|
prst_n => rstn, apbi => apbi, apbo => apbo(10)
|
511 |
|
|
);
|
512 |
|
|
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
|
513 |
|
|
port map (pci_arb_gnt, pci_arb_gnt_n);
|
514 |
|
|
preq_pad : inpadv generic map (tech => padtech, width => 4)
|
515 |
|
|
port map (pci_arb_req, pci_arb_req_n);
|
516 |
|
|
end generate;
|
517 |
|
|
|
518 |
|
|
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
|
519 |
|
|
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
|
520 |
|
|
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
|
521 |
|
|
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
|
522 |
|
|
|
523 |
|
|
end generate;
|
524 |
|
|
|
525 |
|
|
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
|
526 |
|
|
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
|
527 |
|
|
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
|
528 |
|
|
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
|
529 |
|
|
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
|
530 |
|
|
|
531 |
|
|
|
532 |
|
|
-----------------------------------------------------------------------
|
533 |
|
|
--- ETHERNET ---------------------------------------------------------
|
534 |
|
|
-----------------------------------------------------------------------
|
535 |
|
|
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
|
536 |
|
|
e1 : grethm generic map(
|
537 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG,
|
538 |
|
|
pindex => 14, paddr => 14, pirq => 14, memtech => memtech,
|
539 |
|
|
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
|
540 |
|
|
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
|
541 |
|
|
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
|
542 |
|
|
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
|
543 |
|
|
port map(
|
544 |
|
|
rst => rstn, clk => clkm, ahbmi => ahbmi,
|
545 |
|
|
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
|
546 |
|
|
apbo => apbo(14), ethi => ethi, etho => etho);
|
547 |
|
|
|
548 |
|
|
greth1g: if CFG_GRETH1G = 1 generate
|
549 |
|
|
eth_macclk_pad : clkpad
|
550 |
|
|
generic map (tech => padtech, arch => 3, hf => 1)
|
551 |
|
|
port map (eth_macclk, egtx_clk, cgo.clklock, elock);
|
552 |
|
|
end generate greth1g;
|
553 |
|
|
|
554 |
|
|
emdio_pad : iopad generic map (tech => padtech)
|
555 |
|
|
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
|
556 |
|
|
|
557 |
|
|
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
|
558 |
|
|
port map (etx_clk, ethi.tx_clk);
|
559 |
|
|
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
|
560 |
|
|
port map (erx_clk, ethi.rx_clk);
|
561 |
|
|
erxd_pad : inpadv generic map (tech => padtech, width => 8)
|
562 |
|
|
port map (erxd, ethi.rxd(7 downto 0));
|
563 |
|
|
erxdv_pad : inpad generic map (tech => padtech)
|
564 |
|
|
port map (erx_dv, ethi.rx_dv);
|
565 |
|
|
erxer_pad : inpad generic map (tech => padtech)
|
566 |
|
|
port map (erx_er, ethi.rx_er);
|
567 |
|
|
erxco_pad : inpad generic map (tech => padtech)
|
568 |
|
|
port map (erx_col, ethi.rx_col);
|
569 |
|
|
erxcr_pad : inpad generic map (tech => padtech)
|
570 |
|
|
port map (erx_crs, ethi.rx_crs);
|
571 |
|
|
|
572 |
|
|
etxd_pad : outpadv generic map (tech => padtech, width => 8)
|
573 |
|
|
port map (etxd, etho.txd(7 downto 0));
|
574 |
|
|
etxen_pad : outpad generic map (tech => padtech)
|
575 |
|
|
port map ( etx_en, etho.tx_en);
|
576 |
|
|
etxer_pad : outpad generic map (tech => padtech)
|
577 |
|
|
port map (etx_er, etho.tx_er);
|
578 |
|
|
emdc_pad : outpad generic map (tech => padtech)
|
579 |
|
|
port map (emdc, etho.mdc);
|
580 |
|
|
|
581 |
|
|
-- emdis_pad : outpad generic map (tech => padtech)
|
582 |
|
|
-- port map (emddis, vcc(0));
|
583 |
|
|
-- eepwrdwn_pad : outpad generic map (tech => padtech)
|
584 |
|
|
-- port map (epwrdwn, gnd(0));
|
585 |
|
|
-- esleep_pad : outpad generic map (tech => padtech)
|
586 |
|
|
-- port map (esleep, gnd(0));
|
587 |
|
|
-- epause_pad : outpad generic map (tech => padtech)
|
588 |
|
|
-- port map (epause, gnd(0));
|
589 |
|
|
-- ereset_pad : outpad generic map (tech => padtech)
|
590 |
|
|
-- port map (ereset, gnd(0));
|
591 |
|
|
|
592 |
|
|
ethi.gtx_clk <= egtx_clk;
|
593 |
|
|
end generate;
|
594 |
|
|
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
|
595 |
|
|
elock <= '1';
|
596 |
|
|
end generate noeth;
|
597 |
|
|
|
598 |
|
|
-----------------------------------------------------------------------
|
599 |
|
|
--- CAN --------------------------------------------------------------
|
600 |
|
|
-----------------------------------------------------------------------
|
601 |
|
|
|
602 |
|
|
can0 : if CFG_CAN = 1 generate
|
603 |
|
|
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
|
604 |
|
|
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
|
605 |
|
|
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
|
606 |
|
|
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
|
607 |
|
|
|
608 |
|
|
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
|
609 |
|
|
can_tx_pad : outpad generic map (tech => padtech)
|
610 |
|
|
port map (can_txd(i), can_ltx(i));
|
611 |
|
|
can_rx_pad : inpad generic map (tech => padtech)
|
612 |
|
|
port map (can_rxd(i), can_lrx(i));
|
613 |
|
|
end generate;
|
614 |
|
|
end generate;
|
615 |
|
|
|
616 |
|
|
-- can_stb <= '0'; -- no standby
|
617 |
|
|
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
|
618 |
|
|
|
619 |
|
|
-----------------------------------------------------------------------
|
620 |
|
|
--- AHB RAM ----------------------------------------------------------
|
621 |
|
|
-----------------------------------------------------------------------
|
622 |
|
|
|
623 |
|
|
-- ocram : if CFG_AHBRAMEN = 1 generate
|
624 |
|
|
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
|
625 |
|
|
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
|
626 |
|
|
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
|
627 |
|
|
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
|
628 |
|
|
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
|
629 |
|
|
-- end generate;
|
630 |
|
|
--
|
631 |
|
|
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
|
632 |
|
|
|
633 |
|
|
-----------------------------------------------------------------------
|
634 |
|
|
--- SPACEWIRE -------------------------------------------------------
|
635 |
|
|
-----------------------------------------------------------------------
|
636 |
|
|
|
637 |
|
|
spw : if CFG_SPW_EN > 0 generate
|
638 |
|
|
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
|
639 |
|
|
-- spw_clkl <= pciclk;
|
640 |
|
|
swloop : for i in 0 to CFG_SPW_NUM-1 generate
|
641 |
|
|
sw0 : grspwm generic map(tech => memtech,
|
642 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i,
|
643 |
|
|
pindex => 10+i,
|
644 |
|
|
paddr => 10+i, pirq => 10+i,
|
645 |
|
|
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
|
646 |
|
|
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
|
647 |
|
|
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1,
|
648 |
|
|
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1, dmachan => 1,
|
649 |
|
|
netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW)
|
650 |
|
|
port map(rstn, clkm, spw_clkl, ahbmi,
|
651 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i),
|
652 |
|
|
apbi, apbo(10+i), spwi(i), spwo(i));
|
653 |
|
|
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
|
654 |
|
|
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
|
655 |
|
|
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
|
656 |
|
|
port map (spw_rxdp(i), spw_rxdn(i), spwi(i).d(0));
|
657 |
|
|
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
|
658 |
|
|
port map (spw_rxsp(i), spw_rxsn(i), spwi(i).s(0));
|
659 |
|
|
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
|
660 |
|
|
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
|
661 |
|
|
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
|
662 |
|
|
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
|
663 |
|
|
end generate;
|
664 |
|
|
end generate;
|
665 |
|
|
nospw : if CFG_SPW_EN = 0 generate
|
666 |
|
|
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
|
667 |
|
|
port map (spw_rxdp(0), spw_rxdn(0), spwi(0).d(0));
|
668 |
|
|
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
|
669 |
|
|
port map (spw_rxsp(0), spw_rxsn(0), spwi(0).s(0));
|
670 |
|
|
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
|
671 |
|
|
port map (spw_txdp(0), spw_txdn(0), spwi(0).d(0), gnd(0));
|
672 |
|
|
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
|
673 |
|
|
port map (spw_txsp(0), spw_txsn(0), spwi(0).s(0), gnd(0));
|
674 |
|
|
end generate;
|
675 |
|
|
|
676 |
|
|
-------------------------------------------------------------------------------
|
677 |
|
|
-- USB ------------------------------------------------------------------------
|
678 |
|
|
-------------------------------------------------------------------------------
|
679 |
|
|
-- Note that more than one USB component can not be instantiated at the same
|
680 |
|
|
-- time (board has only one USB transceiver), therefore they share AHB
|
681 |
|
|
-- master/slave indexes
|
682 |
|
|
-----------------------------------------------------------------------------
|
683 |
|
|
-- Shared pads
|
684 |
|
|
-----------------------------------------------------------------------------
|
685 |
|
|
usbpads: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
|
686 |
|
|
-- Incoming 60 MHz clock from transceiver, arch 3 = through BUFGDLL or
|
687 |
|
|
-- similiar.
|
688 |
|
|
usb_clkout_pad : clkpad
|
689 |
|
|
generic map (tech => padtech, arch => 3)
|
690 |
|
|
port map (usb_clkout, uclk, cgo.clklock, ulock);
|
691 |
|
|
|
692 |
|
|
usb_d_pad: iopadv
|
693 |
|
|
generic map(tech => padtech, width => 8)
|
694 |
|
|
port map (usb_d, usbo(0).dataout(7 downto 0), usbo(0).oen,
|
695 |
|
|
usbi(0).datain(7 downto 0));
|
696 |
|
|
usb_nxt_pad : inpad generic map (tech => padtech)
|
697 |
|
|
port map (usb_nxt, usbi(0).nxt);
|
698 |
|
|
usb_dir_pad : inpad generic map (tech => padtech)
|
699 |
|
|
port map (usb_dir, usbi(0).dir);
|
700 |
|
|
usb_resetn_pad : outpad generic map (tech => padtech)
|
701 |
|
|
port map (usb_resetn, usbo(0).reset);
|
702 |
|
|
usb_stp_pad : outpad generic map (tech => padtech)
|
703 |
|
|
port map (usb_stp, usbo(0).stp);
|
704 |
|
|
end generate usbpads;
|
705 |
|
|
nousb: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
|
706 |
|
|
ulock <= '1';
|
707 |
|
|
end generate nousb;
|
708 |
|
|
|
709 |
|
|
-----------------------------------------------------------------------------
|
710 |
|
|
-- USB 2.0 Host Controller
|
711 |
|
|
-----------------------------------------------------------------------------
|
712 |
|
|
usbhc0: if CFG_GRUSBHC = 1 generate
|
713 |
|
|
usbhc0 : grusbhc
|
714 |
|
|
generic map (
|
715 |
|
|
ehchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
|
716 |
|
|
ehcpindex => 13, ehcpaddr => 13, ehcpirq => 13, ehcpmask => 16#fff#,
|
717 |
|
|
uhchindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1,
|
718 |
|
|
uhchsindex => 8, uhchaddr => 16#A00#, uhchmask => 16#fff#, uhchirq => 9, tech => fabtech,
|
719 |
|
|
memtech => memtech, ehcgen => CFG_GRUSBHC_EHC, uhcgen => CFG_GRUSBHC_UHC,
|
720 |
|
|
endian_conv => CFG_GRUSBHC_ENDIAN, be_regs => CFG_GRUSBHC_BEREGS,
|
721 |
|
|
be_desc => CFG_GRUSBHC_BEDESC, uhcblo => CFG_GRUSBHC_BLO,
|
722 |
|
|
bwrd => CFG_GRUSBHC_BWRD, vbusconf => CFG_GRUSBHC_VBUSCONF)
|
723 |
|
|
port map (
|
724 |
|
|
clkm,uclk,rstn,apbi,apbo(13),ahbmi,ahbsi,
|
725 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
|
726 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1
|
727 |
|
|
downto
|
728 |
|
|
CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1),
|
729 |
|
|
ahbso(8 downto 8),
|
730 |
|
|
usbo,usbi);
|
731 |
|
|
end generate usbhc0;
|
732 |
|
|
|
733 |
|
|
-----------------------------------------------------------------------------
|
734 |
|
|
-- USB 2.0 Device Controller
|
735 |
|
|
-----------------------------------------------------------------------------
|
736 |
|
|
usbdc0: if CFG_GRUSBDC = 1 generate
|
737 |
|
|
usbdc0: grusbdc
|
738 |
|
|
generic map(
|
739 |
|
|
hsindex => 8, hirq => 9, haddr => 16#004#, hmask => 16#FFC#,
|
740 |
|
|
hmindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
|
741 |
|
|
aiface => CFG_GRUSBDC_AIFACE, uiface => 1,
|
742 |
|
|
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
|
743 |
|
|
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
|
744 |
|
|
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
|
745 |
|
|
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
|
746 |
|
|
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
|
747 |
|
|
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
|
748 |
|
|
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
|
749 |
|
|
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
|
750 |
|
|
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
|
751 |
|
|
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
|
752 |
|
|
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
|
753 |
|
|
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
|
754 |
|
|
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
|
755 |
|
|
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
|
756 |
|
|
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
|
757 |
|
|
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
|
758 |
|
|
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
|
759 |
|
|
memtech => memtech, keepclk => 1)
|
760 |
|
|
port map(
|
761 |
|
|
uclk => uclk,
|
762 |
|
|
usbi => usbi(0),
|
763 |
|
|
usbo => usbo(0),
|
764 |
|
|
hclk => clkm,
|
765 |
|
|
hrst => rstn,
|
766 |
|
|
ahbmi => ahbmi,
|
767 |
|
|
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
|
768 |
|
|
ahbsi => ahbsi,
|
769 |
|
|
ahbso => ahbso(8)
|
770 |
|
|
);
|
771 |
|
|
end generate usbdc0;
|
772 |
|
|
|
773 |
|
|
-----------------------------------------------------------------------------
|
774 |
|
|
-- USB DCL
|
775 |
|
|
-----------------------------------------------------------------------------
|
776 |
|
|
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
|
777 |
|
|
usb_dcl0: grusb_dcl
|
778 |
|
|
generic map (
|
779 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
|
780 |
|
|
memtech => memtech, keepclk => 1, uiface => 1)
|
781 |
|
|
port map (
|
782 |
|
|
uclk, usbi(0), usbo(0), clkm, rstn, ahbmi,
|
783 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM));
|
784 |
|
|
end generate usb_dcl0;
|
785 |
|
|
|
786 |
|
|
-----------------------------------------------------------------------
|
787 |
|
|
--- Drive unused bus elements ---------------------------------------
|
788 |
|
|
-----------------------------------------------------------------------
|
789 |
|
|
|
790 |
|
|
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
|
791 |
|
|
-- ahbmo(i) <= ahbm_none;
|
792 |
|
|
-- end generate;
|
793 |
|
|
-- nam2 : if CFG_PCI > 1 generate
|
794 |
|
|
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
|
795 |
|
|
-- end generate;
|
796 |
|
|
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
|
797 |
|
|
-- apbo(6) <= apb_none;
|
798 |
|
|
|
799 |
|
|
-----------------------------------------------------------------------
|
800 |
|
|
--- Boot message ----------------------------------------------------
|
801 |
|
|
-----------------------------------------------------------------------
|
802 |
|
|
|
803 |
|
|
-- pragma translate_off
|
804 |
|
|
x : report_version
|
805 |
|
|
generic map (
|
806 |
|
|
msg1 => "LEON3 GR-PCI-XC5LX50 Demonstration design",
|
807 |
|
|
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
|
808 |
|
|
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
|
809 |
|
|
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
|
810 |
|
|
mdel => 1
|
811 |
|
|
);
|
812 |
|
|
-- pragma translate_on
|
813 |
|
|
end;
|