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URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [leon3mp_precision.tcl] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
new_project -name leon3mp -folder . -createimpl_name precision
2 
setup_design -manufacturer Xilinx -family spartan3 -part 3s1500fg456 -package fg456 -speed -4
3 
set_input_dir .
4 
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5 
add_input_file -format VHDL -work grlib ../../lib/grlib/stdlib/stdlib.vhd
6 
add_input_file -format VHDL -work grlib ../../lib/grlib/sparc/sparc.vhd
7 
add_input_file -format VHDL -work grlib ../../lib/grlib/modgen/multlib.vhd
8 
add_input_file -format VHDL -work grlib ../../lib/grlib/modgen/leaves.vhd
9 
add_input_file -format VHDL -work grlib ../../lib/grlib/amba/amba.vhd
10 
add_input_file -format VHDL -work grlib ../../lib/grlib/amba/devices.vhd
11 
add_input_file -format VHDL -work grlib ../../lib/grlib/amba/defmst.vhd
12 
add_input_file -format VHDL -work grlib ../../lib/grlib/amba/apbctrl.vhd
13 
add_input_file -format VHDL -work grlib ../../lib/grlib/amba/ahbctrl.vhd
14 
add_input_file -format VHDL -work grlib ../../lib/grlib/amba/dma2ahb_pkg.vhd
15 
add_input_file -format VHDL -work grlib ../../lib/grlib/amba/dma2ahb.vhd
16 
add_input_file -format VHDL -work techmap ../../lib/techmap/gencomp/gencomp.vhd
17 
add_input_file -format VHDL -work techmap ../../lib/techmap/gencomp/netcomp.vhd
18 
add_input_file -format VHDL -work techmap ../../lib/techmap/inferred/memory_inferred.vhd
19 
add_input_file -format VHDL -work techmap ../../lib/techmap/inferred/ddr_inferred.vhd
20 
add_input_file -format VHDL -work techmap ../../lib/techmap/inferred/mul_inferred.vhd
21 
add_input_file -format VHDL -work techmap ../../lib/techmap/inferred/ddr_phy_inferred.vhd
22 
add_input_file -format VHDL -work techmap ../../lib/techmap/dw02/mul_dw_gen.vhd
23 
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24 
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add_input_file -format VHDL -work techmap ../../lib/techmap/unisim/pads_unisim.vhd
26 
add_input_file -format VHDL -work techmap ../../lib/techmap/unisim/clkgen_unisim.vhd
27 
add_input_file -format VHDL -work techmap ../../lib/techmap/unisim/tap_unisim.vhd
28 
add_input_file -format VHDL -work techmap ../../lib/techmap/unisim/ddr_unisim.vhd
29 
add_input_file -format VHDL -work techmap ../../lib/techmap/unisim/ddr_phy_unisim.vhd
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add_input_file -format VHDL -work techmap ../../lib/techmap/unisim/grspwc_unisim.vhd
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add_input_file -format VHDL -work techmap ../../lib/techmap/unisim/grfpw_unisim.vhd
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36 
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44 
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50 
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51 
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52 
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53 
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54 
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55 
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56 
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57 
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58 
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59 
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60 
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61 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/lvds_combo.vhd
62 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/odpad.vhd
63 
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64 
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65 
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66 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/skew_outpad.vhd
67 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/grspwc_net.vhd
68 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/grlfpw_net.vhd
69 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/grfpw_net.vhd
70 
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71 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/cpu_disas_net.vhd
72 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/grusbhc_net.vhd
73 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/ringosc.vhd
74 
add_input_file -format VHDL -work techmap ../../lib/techmap/maps/ssrctrl_net.vhd
75 
add_input_file -format VHDL -work spw ../../lib/spw/comp/spwcomp.vhd
76 
add_input_file -format VHDL -work spw ../../lib/spw/wrapper/grspw_gen.vhd
77 
add_input_file -format VHDL -work eth ../../lib/eth/comp/ethcomp.vhd
78 
add_input_file -format VHDL -work eth ../../lib/eth/core/greth_pkg.vhd
79 
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80 
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81 
add_input_file -format VHDL -work eth ../../lib/eth/core/greth_tx.vhd
82 
add_input_file -format VHDL -work eth ../../lib/eth/core/greth_rx.vhd
83 
add_input_file -format VHDL -work eth ../../lib/eth/core/grethc.vhd
84 
add_input_file -format VHDL -work eth ../../lib/eth/wrapper/greth_gen.vhd
85 
add_input_file -format VHDL -work eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
86 
add_input_file -format VHDL -work opencores ../../lib/opencores/occomp/occomp.vhd
87 
add_input_file -format VHDL -work opencores ../../lib/opencores/can/cancomp.vhd
88 
add_input_file -format VHDL -work opencores ../../lib/opencores/can/can_top.vhd
89 
add_input_file -format VHDL -work opencores ../../lib/opencores/can/can_top_core_sync.vhd
90 
add_input_file -format VHDL -work opencores ../../lib/opencores/i2c/i2c_master_bit_ctrl.vhd
91 
add_input_file -format VHDL -work opencores ../../lib/opencores/i2c/i2c_master_byte_ctrl.vhd
92 
add_input_file -format VHDL -work opencores ../../lib/opencores/i2c/i2coc.vhd
93 
add_input_file -format VERILOG -work opencores ../../lib/opencores/spi/simple_spi_top.v
94 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/ud_cnt.vhd
95 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/ro_cnt.vhd
96 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/atahost_dma_fifo.vhd
97 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/atahost_dma_actrl.vhd
98 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/atahost_dma_tctrl.vhd
99 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/atahost_pio_tctrl.vhd
100 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/atahost_pio_actrl.vhd
101 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/atahost_controller.vhd
102 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/atahost_pio_controller.vhd
103 
add_input_file -format VHDL -work opencores ../../lib/opencores/ata/ocidec2_controller.vhd
104 
add_input_file -format VERILOG -work opencores ../../lib/opencores/ac97/ac97_top.v
105 
add_input_file -format VHDL -work gaisler ../../lib/gaisler/arith/arith.vhd
106 
add_input_file -format VHDL -work gaisler ../../lib/gaisler/arith/mul32.vhd
107 
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108 
add_input_file -format VHDL -work gaisler ../../lib/gaisler/memctrl/memctrl.vhd
109 
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110 
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111 
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112 
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113 
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114 
add_input_file -format VHDL -work gaisler ../../lib/gaisler/leon3/reg_zero.vhd
115 
add_input_file -format VHDL -work gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
116 
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117 
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118 
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119 
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120 
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121 
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122 
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123 
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124 
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125 
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126 
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127 
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130 
add_input_file -format VHDL -work gaisler ../../lib/gaisler/leon3/mmu.vhd
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132 
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135 
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137 
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138 
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142 
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143 
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151 
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152 
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220 
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221 
add_input_file -format VHDL -work work ahbrom.vhd
222 
add_input_file -format VHDL -work work vga_clkgen.vhd
223 
add_input_file -format VHDL -work work leon3mp.vhd
224 
setup_design -design leon3mp
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setup_design -retiming
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setup_design -vhdl
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setup_design -transformations=false
228 
setup_design -frequency="60"
229 
 
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save_impl

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