URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [add32/] [_primary.vhd] - Blame information for rev 2

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library verilog;
use verilog.vl_types.all;
entity add32 is
    port(
        d_i             : in     vl_logic_vector(31 downto 0);
        d_o             : out    vl_logic_vector(31 downto 0)
    );
end add32;

Line No.	Rev	Author	Line
1	2	dimamali	`library verilog;`
2			`use verilog.vl_types.all;`
3			`entity add32 is`
4			`port(`
5			`d_i : in vl_logic_vector(31 downto 0);`
6			`d_o : out vl_logic_vector(31 downto 0)`
7			`);`
8			`end add32;`

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [add32/] [_primary.vhd] - Blame information for rev 2