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URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [opencores/] [_info] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
m255
2 
K3
3 
13
4 
cModel Technology
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R22
753 
R48
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R31
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R25
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R18
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R19
758 
Ecan_ibo
759 
R8
760 
R14
761 
R7
762 
R45
763 
R46
764 
l0
765 
L1527
766 
V3aViO=m5V0EO7E0`;lj?B3
767 
R17
768 
31
769 
R18
770 
R19
771 
Artl
772 
R14
773 
DEx4 work 7 can_ibo 0 22 3aViO=m5V0EO7E0`;lj?B3
774 
l1542
775 
L1533
776 
V1;m
777 
R17
778 
31
779 
Z51 Mx1 4 ieee 14 std_logic_1164
780 
R18
781 
R19
782 
Ecan_ibo_core_sync
783 
R8
784 
R9
785 
R11
786 
R12
787 
R10
788 
R14
789 
R7
790 
R49
791 
R50
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l0
793 
L792
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VCbbH@M3SE?0?Agi9aGRzN2
795 
R17
796 
31
797 
R18
798 
R19
799 
Artl
800 
R9
801 
R11
802 
R12
803 
R10
804 
R14
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DEx4 work 17 can_ibo_core_sync 0 22 CbbH@M3SE?0?Agi9aGRzN2
806 
l807
807 
L798
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VWn?S_zX
809 
R17
810 
31
811 
R47
812 
R29
813 
R30
814 
R31
815 
R25
816 
R18
817 
R19
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Ecan_register
819 
R8
820 
R14
821 
R7
822 
R45
823 
R46
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l0
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L4289
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VfzP]j`R0@ZN0T37nMV62h2
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R17
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31
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R18
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R19
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Artl
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R14
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DEx4 work 12 can_register 0 22 fzP]j`R0@ZN0T37nMV62h2
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l4308
835 
L4299
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VSB=GO1_[UbeddR87R3_Z53
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R17
838 
31
839 
R51
840 
R18
841 
R19
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Ecan_register_asyn
843 
R8
844 
R9
845 
R11
846 
R10
847 
R12
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R14
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R7
850 
R45
851 
R46
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l0
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L4422
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V_oEA^=mLU7;SGW6i5l[ZQ1
855 
R17
856 
31
857 
R18
858 
R19
859 
Artl
860 
R9
861 
R11
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R10
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R12
864 
R14
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DEx4 work 17 can_register_asyn 0 22 _oEA^=mLU7;SGW6i5l[ZQ1
866 
l4443
867 
L4434
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VjQmSkJk?nRFLjGlF1@;D83
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R17
870 
31
871 
R47
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R22
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R48
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R31
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R25
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R18
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R19
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Ecan_register_asyn_syn
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R8
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R9
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R11
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R12
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R10
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R14
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R7
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R45
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R46
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l0
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L4559
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VXm2dMi@5ThkeVZmCoedNk2
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R17
892 
31
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R18
894 
R19
895 
Artl
896 
R9
897 
R11
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R12
899 
R10
900 
R14
901 
DEx4 work 21 can_register_asyn_syn 0 22 Xm2dMi@5ThkeVZmCoedNk2
902 
l4581
903 
L4572
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V]2mOF0:R2?g
905 
R17
906 
31
907 
R47
908 
R29
909 
R30
910 
R31
911 
R25
912 
R18
913 
R19
914 
Ecan_register_syn
915 
R8
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R9
917 
R11
918 
R12
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R10
920 
R14
921 
R7
922 
R45
923 
R46
924 
l0
925 
L4698
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VFGIPRA8JUR:W<4NZ2zIlB0
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R17
928 
31
929 
R18
930 
R19
931 
Artl
932 
R9
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R11
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R12
935 
R10
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R14
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DEx4 work 16 can_register_syn 0 22 FGIPRA8JUR:W<4NZ2zIlB0
938 
l4719
939 
L4710
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V42oLLnl4ji2V?MOdNf99U3
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R17
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31
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R47
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R29
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R30
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R31
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R25
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R18
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Ecan_registers
951 
R8
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R9
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R11
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R10
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R12
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R14
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R7
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R45
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R46
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l0
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L4933
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VNAOFhDle?WOzHa4O:8`lX2
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R17
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31
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R18
966 
R19
967 
Artl
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R9
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R11
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R10
971 
R12
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R14
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DEx4 work 13 can_registers 0 22 NAOFhDle?WOzHa4O:8`lX2
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l5254
975 
L5027
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VFGgn5[TJQkK412FW7nU;63
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R17
978 
31
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R47
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R22
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R48
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R31
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R25
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R18
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R19
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Ecan_top
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R8
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R9
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R11
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R12
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R10
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R14
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R7
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R45
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R46
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l0
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L6421
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V
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R17
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R18
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R19
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Artl
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R9
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R11
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R12
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DEx4 work 7 can_top 0 22
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L6467
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V2WUZV=;NDQ1P`6>JfL^K81
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R17
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R47
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R29
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R30
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R31
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R25
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R18
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Ecan_top_core_sync
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R8
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R9
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R11
1026 
R10
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R12
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R14
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R7
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l0
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L3749
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VhVihNAL`eeIalECRmm]l30
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R17
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R18
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R19
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Artl
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R9
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R11
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R10
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R12
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R14
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DEx4 work 17 can_top_core_sync 0 22 hVihNAL`eeIalECRmm]l30
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l4009
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L3821
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VF9:
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R17
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R47
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8C:/grlib-gpl-1.0.19-b3188/lib/opencores/can/cancomp.vhd
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R18
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vfifo4
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Vc511
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Ei2c_master_bit_ctrl
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R11
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VU8KX7i_a14Ac[NJG4`dN?3
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Astructural
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R10
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DEx4 work 19 i2c_master_bit_ctrl 0 22 U8KX7i_a14Ac[NJG4`dN?3
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l201
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L179
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Z58 FC:/grlib-gpl-1.0.19-b3188/lib/opencores/i2c/i2c_master_byte_ctrl.vhd
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l0
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R19
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Astructural
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R9
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R11
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R12
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R10
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R14
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DEx4 work 20 i2c_master_byte_ctrl 0 22 ZDSn>z:e
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L116
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VFZi>bdMW4n5>faz[7hoN`3
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R17
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R29
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R30
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Pi2coc
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8C:/grlib-gpl-1.0.19-b3188/lib/opencores/i2c/i2coc.vhd
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R37
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Z59 Mx1 4 ieee 11 numeric_std
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R18
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R19
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Poccomp
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R14
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R8
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R7
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8C:/grlib-gpl-1.0.19-b3188/lib/opencores/occomp/occomp.vhd
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FC:/grlib-gpl-1.0.19-b3188/lib/opencores/occomp/occomp.vhd
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VbYl:[QA2W:U0Q^RE>:0BQ2
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Z61 FC:/grlib-gpl-1.0.19-b3188/lib/opencores/ata/ocidec2_controller.vhd
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L70
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R17
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R18
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R12
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DEx4 work 18 ocidec2_controller 0 22 9ih>GNEVIlFJaW7mF`Yg50
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R12
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R7
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R14
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DEx4 work 6 ro_cnt 0 22 ;5I?Sb]LCa>VXmDLe[]fB3
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L77
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VRIdgzcOKmk
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R17
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R37
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R59
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R18
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R4
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r1
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R5
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R6
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Eud_cnt
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R8
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R9
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R11
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R12
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R10
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R14
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R7
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Z64 8C:/grlib-gpl-1.0.19-b3188/lib/opencores/ata/ud_cnt.vhd
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R18
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R19
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R11
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R12
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R10
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R14
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DEx4 work 6 ud_cnt 0 22 k[7dF8
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L82
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R17
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R30
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R31
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R19

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